Commit | Line | Data |
---|---|---|
c5aa9e3b LT |
1 | /* |
2 | * AMD 10Gb Ethernet driver | |
3 | * | |
4 | * This file is available to you under your choice of the following two | |
5 | * licenses: | |
6 | * | |
7 | * License 1: GPLv2 | |
8 | * | |
b3b71597 | 9 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
10 | * |
11 | * This file is free software; you may copy, redistribute and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation, either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | * | |
24 | * This file incorporates work covered by the following copyright and | |
25 | * permission notice: | |
26 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
27 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
28 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
29 | * and you. | |
30 | * | |
31 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
32 | * under any End User Software License Agreement or Agreement for Licensed | |
33 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
34 | * granted, free of charge, to any person obtaining a copy of this software | |
35 | * annotated with this license and the Software, to deal in the Software | |
36 | * without restriction, including without limitation the rights to use, | |
37 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
38 | * of the Software, and to permit persons to whom the Software is furnished | |
39 | * to do so, subject to the following conditions: | |
40 | * | |
41 | * The above copyright notice and this permission notice shall be included | |
42 | * in all copies or substantial portions of the Software. | |
43 | * | |
44 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
45 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
46 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
47 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
48 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
49 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
50 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
51 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
52 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
53 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
54 | * THE POSSIBILITY OF SUCH DAMAGE. | |
55 | * | |
56 | * | |
57 | * License 2: Modified BSD | |
58 | * | |
b3b71597 | 59 | * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. |
c5aa9e3b LT |
60 | * All rights reserved. |
61 | * | |
62 | * Redistribution and use in source and binary forms, with or without | |
63 | * modification, are permitted provided that the following conditions are met: | |
64 | * * Redistributions of source code must retain the above copyright | |
65 | * notice, this list of conditions and the following disclaimer. | |
66 | * * Redistributions in binary form must reproduce the above copyright | |
67 | * notice, this list of conditions and the following disclaimer in the | |
68 | * documentation and/or other materials provided with the distribution. | |
69 | * * Neither the name of Advanced Micro Devices, Inc. nor the | |
70 | * names of its contributors may be used to endorse or promote products | |
71 | * derived from this software without specific prior written permission. | |
72 | * | |
73 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
74 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
75 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
76 | * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY | |
77 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
78 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
79 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
80 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
81 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
82 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
83 | * | |
84 | * This file incorporates work covered by the following copyright and | |
85 | * permission notice: | |
86 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
87 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
88 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
89 | * and you. | |
90 | * | |
91 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
92 | * under any End User Software License Agreement or Agreement for Licensed | |
93 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
94 | * granted, free of charge, to any person obtaining a copy of this software | |
95 | * annotated with this license and the Software, to deal in the Software | |
96 | * without restriction, including without limitation the rights to use, | |
97 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
98 | * of the Software, and to permit persons to whom the Software is furnished | |
99 | * to do so, subject to the following conditions: | |
100 | * | |
101 | * The above copyright notice and this permission notice shall be included | |
102 | * in all copies or substantial portions of the Software. | |
103 | * | |
104 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
105 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
106 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
107 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
108 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
109 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
110 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
111 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
112 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
113 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
114 | * THE POSSIBILITY OF SUCH DAMAGE. | |
115 | */ | |
116 | ||
117 | #ifndef __XGBE_H__ | |
118 | #define __XGBE_H__ | |
119 | ||
120 | #include <linux/dma-mapping.h> | |
121 | #include <linux/netdevice.h> | |
122 | #include <linux/workqueue.h> | |
123 | #include <linux/phy.h> | |
801c62d9 LT |
124 | #include <linux/if_vlan.h> |
125 | #include <linux/bitops.h> | |
23e4eef7 | 126 | #include <linux/ptp_clock_kernel.h> |
74d23cc7 | 127 | #include <linux/timecounter.h> |
23e4eef7 | 128 | #include <linux/net_tstamp.h> |
fca2d994 | 129 | #include <net/dcbnl.h> |
5ab1dcd5 | 130 | #include <linux/completion.h> |
c5aa9e3b | 131 | |
c5aa9e3b | 132 | #define XGBE_DRV_NAME "amd-xgbe" |
e57f7a3f | 133 | #define XGBE_DRV_VERSION "1.0.3" |
c5aa9e3b LT |
134 | #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" |
135 | ||
136 | /* Descriptor related defines */ | |
d0a8ba6c LT |
137 | #define XGBE_TX_DESC_CNT 512 |
138 | #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) | |
139 | #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) | |
140 | #define XGBE_RX_DESC_CNT 512 | |
c5aa9e3b | 141 | |
d0a8ba6c | 142 | #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) |
c5aa9e3b | 143 | |
e1c05067 | 144 | /* Descriptors required for maximum contiguous TSO/GSO packet */ |
16958a2b LT |
145 | #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) |
146 | ||
147 | /* Maximum possible descriptors needed for an SKB: | |
148 | * - Maximum number of SKB frags | |
149 | * - Maximum descriptors for contiguous TSO/GSO packet | |
150 | * - Possible context descriptor | |
151 | * - Possible TSO header descriptor | |
152 | */ | |
153 | #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) | |
154 | ||
d0a8ba6c LT |
155 | #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) |
156 | #define XGBE_RX_BUF_ALIGN 64 | |
08dcc47c | 157 | #define XGBE_SKB_ALLOC_SIZE 256 |
174fd259 | 158 | #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */ |
c5aa9e3b | 159 | |
d5c48582 | 160 | #define XGBE_MAX_DMA_CHANNELS 16 |
fca2d994 | 161 | #define XGBE_MAX_QUEUES 16 |
43e0dcf7 | 162 | #define XGBE_PRIORITY_QUEUES 8 |
4b8acdf5 | 163 | #define XGBE_DMA_STOP_TIMEOUT 1 |
d0a8ba6c LT |
164 | |
165 | /* DMA cache settings - Outer sharable, write-back, write-allocate */ | |
cfa50c78 LT |
166 | #define XGBE_DMA_OS_AXDOMAIN 0x2 |
167 | #define XGBE_DMA_OS_ARCACHE 0xb | |
168 | #define XGBE_DMA_OS_AWCACHE 0xf | |
169 | ||
170 | /* DMA cache settings - System, no caches used */ | |
171 | #define XGBE_DMA_SYS_AXDOMAIN 0x3 | |
172 | #define XGBE_DMA_SYS_ARCACHE 0x0 | |
173 | #define XGBE_DMA_SYS_AWCACHE 0x0 | |
d0a8ba6c | 174 | |
4c70dd8a LT |
175 | /* DMA channel interrupt modes */ |
176 | #define XGBE_IRQ_MODE_EDGE 0 | |
177 | #define XGBE_IRQ_MODE_LEVEL 1 | |
178 | ||
d0a8ba6c | 179 | #define XGBE_DMA_INTERRUPT_MASK 0x31c7 |
c5aa9e3b LT |
180 | |
181 | #define XGMAC_MIN_PACKET 60 | |
182 | #define XGMAC_STD_PACKET_MTU 1500 | |
183 | #define XGMAC_MAX_STD_PACKET 1518 | |
184 | #define XGMAC_JUMBO_PACKET_MTU 9000 | |
185 | #define XGMAC_MAX_JUMBO_PACKET 9018 | |
43e0dcf7 LT |
186 | #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ |
187 | ||
188 | #define XGMAC_PFC_DATA_LEN 46 | |
189 | #define XGMAC_PFC_DELAYS 14000 | |
190 | ||
191 | #define XGMAC_PRIO_QUEUES(_cnt) \ | |
192 | min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) | |
c5aa9e3b | 193 | |
82a19035 LT |
194 | /* Common property names */ |
195 | #define XGBE_MAC_ADDR_PROPERTY "mac-address" | |
196 | #define XGBE_PHY_MODE_PROPERTY "phy-mode" | |
197 | #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" | |
7c12aa08 | 198 | #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" |
82a19035 | 199 | |
23e4eef7 LT |
200 | /* Device-tree clock names */ |
201 | #define XGBE_DMA_CLOCK "dma_clk" | |
202 | #define XGBE_PTP_CLOCK "ptp_clk" | |
82a19035 LT |
203 | |
204 | /* ACPI property names */ | |
205 | #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" | |
206 | #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" | |
23e4eef7 | 207 | |
47f164de LT |
208 | /* PCI BAR mapping */ |
209 | #define XGBE_XGMAC_BAR 0 | |
210 | #define XGBE_XPCS_BAR 1 | |
211 | #define XGBE_MAC_PROP_OFFSET 0x1d000 | |
212 | #define XGBE_I2C_CTRL_OFFSET 0x1e000 | |
213 | ||
214 | /* PCI MSIx support */ | |
215 | #define XGBE_MSIX_BASE_COUNT 4 | |
216 | #define XGBE_MSIX_MIN_COUNT (XGBE_MSIX_BASE_COUNT + 1) | |
217 | ||
218 | /* PCI clock frequencies */ | |
219 | #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ | |
220 | #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ | |
221 | ||
23e4eef7 LT |
222 | /* Timestamp support - values based on 50MHz PTP clock |
223 | * 50MHz => 20 nsec | |
224 | */ | |
225 | #define XGBE_TSTAMP_SSINC 20 | |
226 | #define XGBE_TSTAMP_SNSINC 0 | |
227 | ||
c5aa9e3b LT |
228 | /* Driver PMT macros */ |
229 | #define XGMAC_DRIVER_CONTEXT 1 | |
230 | #define XGMAC_IOCTL_CONTEXT 2 | |
231 | ||
43e0dcf7 LT |
232 | #define XGMAC_FIFO_MIN_ALLOC 2048 |
233 | #define XGMAC_FIFO_UNIT 256 | |
234 | #define XGMAC_FIFO_ALIGN(_x) \ | |
235 | (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) | |
236 | #define XGMAC_FIFO_FC_OFF 2048 | |
237 | #define XGMAC_FIFO_FC_MIN 4096 | |
c5aa9e3b | 238 | |
fca2d994 | 239 | #define XGBE_TC_MIN_QUANTUM 10 |
c5aa9e3b LT |
240 | |
241 | /* Helper macro for descriptor handling | |
d0a8ba6c | 242 | * Always use XGBE_GET_DESC_DATA to access the descriptor data |
c5aa9e3b LT |
243 | * since the index is free-running and needs to be and-ed |
244 | * with the descriptor count value of the ring to index to | |
245 | * the proper descriptor data. | |
246 | */ | |
d0a8ba6c | 247 | #define XGBE_GET_DESC_DATA(_ring, _idx) \ |
c5aa9e3b LT |
248 | ((_ring)->rdata + \ |
249 | ((_idx) & ((_ring)->rdesc_count - 1))) | |
250 | ||
c5aa9e3b | 251 | /* Default coalescing parameters */ |
c635eaac | 252 | #define XGMAC_INIT_DMA_TX_USECS 1000 |
9867e8fb | 253 | #define XGMAC_INIT_DMA_TX_FRAMES 25 |
c5aa9e3b LT |
254 | |
255 | #define XGMAC_MAX_DMA_RIWT 0xff | |
9867e8fb LT |
256 | #define XGMAC_INIT_DMA_RX_USECS 30 |
257 | #define XGMAC_INIT_DMA_RX_FRAMES 25 | |
c5aa9e3b LT |
258 | |
259 | /* Flow control queue count */ | |
260 | #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 | |
261 | ||
43e0dcf7 LT |
262 | /* Flow control threshold units */ |
263 | #define XGMAC_FLOW_CONTROL_UNIT 512 | |
264 | #define XGMAC_FLOW_CONTROL_ALIGN(_x) \ | |
265 | (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) | |
266 | #define XGMAC_FLOW_CONTROL_VALUE(_x) \ | |
267 | (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) | |
268 | #define XGMAC_FLOW_CONTROL_MAX 33280 | |
269 | ||
b85e4d89 LT |
270 | /* Maximum MAC address hash table size (256 bits = 8 bytes) */ |
271 | #define XGBE_MAC_HASH_TABLE_SIZE 8 | |
c5aa9e3b | 272 | |
5b9dfe29 LT |
273 | /* Receive Side Scaling */ |
274 | #define XGBE_RSS_HASH_KEY_SIZE 40 | |
275 | #define XGBE_RSS_MAX_TABLE_SIZE 256 | |
276 | #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 | |
277 | #define XGBE_RSS_HASH_KEY_TYPE 1 | |
278 | ||
7c12aa08 LT |
279 | /* Auto-negotiation */ |
280 | #define XGBE_AN_MS_TIMEOUT 500 | |
1bf40ada LT |
281 | #define XGBE_LINK_TIMEOUT 5 |
282 | ||
283 | #define XGBE_SGMII_AN_LINK_STATUS BIT(1) | |
284 | #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) | |
285 | #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 | |
286 | #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 | |
287 | #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) | |
7c12aa08 | 288 | |
e78332b2 LT |
289 | /* ECC correctable error notification window (seconds) */ |
290 | #define XGBE_ECC_LIMIT 60 | |
291 | ||
732f2ab7 LT |
292 | /* MDIO port types */ |
293 | #define XGMAC_MAX_C22_PORT 3 | |
294 | ||
c5aa9e3b LT |
295 | struct xgbe_prv_data; |
296 | ||
297 | struct xgbe_packet_data { | |
16958a2b LT |
298 | struct sk_buff *skb; |
299 | ||
c5aa9e3b LT |
300 | unsigned int attributes; |
301 | ||
302 | unsigned int errors; | |
303 | ||
304 | unsigned int rdesc_count; | |
305 | unsigned int length; | |
306 | ||
307 | unsigned int header_len; | |
308 | unsigned int tcp_header_len; | |
309 | unsigned int tcp_payload_len; | |
310 | unsigned short mss; | |
311 | ||
312 | unsigned short vlan_ctag; | |
23e4eef7 LT |
313 | |
314 | u64 rx_tstamp; | |
5b9dfe29 LT |
315 | |
316 | u32 rss_hash; | |
317 | enum pkt_hash_types rss_hash_type; | |
5fb4b86a LT |
318 | |
319 | unsigned int tx_packets; | |
320 | unsigned int tx_bytes; | |
c5aa9e3b LT |
321 | }; |
322 | ||
323 | /* Common Rx and Tx descriptor mapping */ | |
324 | struct xgbe_ring_desc { | |
5226cfc5 LT |
325 | __le32 desc0; |
326 | __le32 desc1; | |
327 | __le32 desc2; | |
328 | __le32 desc3; | |
c5aa9e3b LT |
329 | }; |
330 | ||
08dcc47c LT |
331 | /* Page allocation related values */ |
332 | struct xgbe_page_alloc { | |
333 | struct page *pages; | |
334 | unsigned int pages_len; | |
335 | unsigned int pages_offset; | |
336 | ||
337 | dma_addr_t pages_dma; | |
338 | }; | |
339 | ||
174fd259 LT |
340 | /* Ring entry buffer data */ |
341 | struct xgbe_buffer_data { | |
342 | struct xgbe_page_alloc pa; | |
343 | struct xgbe_page_alloc pa_unmap; | |
344 | ||
cfbfd86b LT |
345 | dma_addr_t dma_base; |
346 | unsigned long dma_off; | |
174fd259 LT |
347 | unsigned int dma_len; |
348 | }; | |
349 | ||
c9f140eb LT |
350 | /* Tx-related ring data */ |
351 | struct xgbe_tx_ring_data { | |
5fb4b86a LT |
352 | unsigned int packets; /* BQL packet count */ |
353 | unsigned int bytes; /* BQL byte count */ | |
c9f140eb LT |
354 | }; |
355 | ||
356 | /* Rx-related ring data */ | |
357 | struct xgbe_rx_ring_data { | |
358 | struct xgbe_buffer_data hdr; /* Header locations */ | |
359 | struct xgbe_buffer_data buf; /* Payload locations */ | |
360 | ||
361 | unsigned short hdr_len; /* Length of received header */ | |
362 | unsigned short len; /* Length of received packet */ | |
363 | }; | |
364 | ||
c5aa9e3b LT |
365 | /* Structure used to hold information related to the descriptor |
366 | * and the packet associated with the descriptor (always use | |
d0a8ba6c | 367 | * use the XGBE_GET_DESC_DATA macro to access this data from the ring) |
c5aa9e3b LT |
368 | */ |
369 | struct xgbe_ring_data { | |
370 | struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ | |
371 | dma_addr_t rdesc_dma; /* DMA address of descriptor */ | |
372 | ||
373 | struct sk_buff *skb; /* Virtual address of SKB */ | |
374 | dma_addr_t skb_dma; /* DMA address of SKB data */ | |
375 | unsigned int skb_dma_len; /* Length of SKB DMA area */ | |
c5aa9e3b | 376 | |
c9f140eb LT |
377 | struct xgbe_tx_ring_data tx; /* Tx-related data */ |
378 | struct xgbe_rx_ring_data rx; /* Rx-related data */ | |
c5aa9e3b | 379 | |
c5aa9e3b | 380 | unsigned int mapped_as_page; |
23e4eef7 LT |
381 | |
382 | /* Incomplete receive save location. If the budget is exhausted | |
383 | * or the last descriptor (last normal descriptor or a following | |
384 | * context descriptor) has not been DMA'd yet the current state | |
385 | * of the receive processing needs to be saved. | |
386 | */ | |
387 | unsigned int state_saved; | |
388 | struct { | |
23e4eef7 LT |
389 | struct sk_buff *skb; |
390 | unsigned int len; | |
391 | unsigned int error; | |
392 | } state; | |
c5aa9e3b LT |
393 | }; |
394 | ||
395 | struct xgbe_ring { | |
396 | /* Ring lock - used just for TX rings at the moment */ | |
397 | spinlock_t lock; | |
398 | ||
399 | /* Per packet related information */ | |
400 | struct xgbe_packet_data packet_data; | |
401 | ||
402 | /* Virtual/DMA addresses and count of allocated descriptor memory */ | |
403 | struct xgbe_ring_desc *rdesc; | |
404 | dma_addr_t rdesc_dma; | |
405 | unsigned int rdesc_count; | |
406 | ||
407 | /* Array of descriptor data corresponding the descriptor memory | |
d0a8ba6c | 408 | * (always use the XGBE_GET_DESC_DATA macro to access this data) |
c5aa9e3b LT |
409 | */ |
410 | struct xgbe_ring_data *rdata; | |
411 | ||
08dcc47c | 412 | /* Page allocation for RX buffers */ |
174fd259 LT |
413 | struct xgbe_page_alloc rx_hdr_pa; |
414 | struct xgbe_page_alloc rx_buf_pa; | |
08dcc47c | 415 | |
c5aa9e3b LT |
416 | /* Ring index values |
417 | * cur - Tx: index of descriptor to be used for current transfer | |
418 | * Rx: index of descriptor to check for packet availability | |
419 | * dirty - Tx: index of descriptor to check for transfer complete | |
270894e7 | 420 | * Rx: index of descriptor to check for buffer reallocation |
c5aa9e3b LT |
421 | */ |
422 | unsigned int cur; | |
423 | unsigned int dirty; | |
424 | ||
425 | /* Coalesce frame count used for interrupt bit setting */ | |
426 | unsigned int coalesce_count; | |
427 | ||
428 | union { | |
429 | struct { | |
430 | unsigned int queue_stopped; | |
16958a2b | 431 | unsigned int xmit_more; |
c5aa9e3b LT |
432 | unsigned short cur_mss; |
433 | unsigned short cur_vlan_ctag; | |
434 | } tx; | |
c5aa9e3b LT |
435 | }; |
436 | } ____cacheline_aligned; | |
437 | ||
438 | /* Structure used to describe the descriptor rings associated with | |
439 | * a DMA channel. | |
440 | */ | |
441 | struct xgbe_channel { | |
442 | char name[16]; | |
443 | ||
444 | /* Address of private data area for device */ | |
445 | struct xgbe_prv_data *pdata; | |
446 | ||
447 | /* Queue index and base address of queue's DMA registers */ | |
448 | unsigned int queue_index; | |
449 | void __iomem *dma_regs; | |
450 | ||
9227dc5e LT |
451 | /* Per channel interrupt irq number */ |
452 | int dma_irq; | |
54ceb9ec | 453 | char dma_irq_name[IFNAMSIZ + 32]; |
9227dc5e LT |
454 | |
455 | /* Netdev related settings */ | |
456 | struct napi_struct napi; | |
457 | ||
c5aa9e3b LT |
458 | unsigned int saved_ier; |
459 | ||
460 | unsigned int tx_timer_active; | |
c635eaac | 461 | struct timer_list tx_timer; |
c5aa9e3b LT |
462 | |
463 | struct xgbe_ring *tx_ring; | |
464 | struct xgbe_ring *rx_ring; | |
465 | } ____cacheline_aligned; | |
466 | ||
7c12aa08 LT |
467 | enum xgbe_state { |
468 | XGBE_DOWN, | |
7c12aa08 LT |
469 | XGBE_LINK_INIT, |
470 | XGBE_LINK_ERR, | |
e78332b2 | 471 | XGBE_STOPPED, |
7c12aa08 LT |
472 | }; |
473 | ||
c5aa9e3b | 474 | enum xgbe_int { |
c5aa9e3b LT |
475 | XGMAC_INT_DMA_CH_SR_TI, |
476 | XGMAC_INT_DMA_CH_SR_TPS, | |
477 | XGMAC_INT_DMA_CH_SR_TBU, | |
478 | XGMAC_INT_DMA_CH_SR_RI, | |
479 | XGMAC_INT_DMA_CH_SR_RBU, | |
480 | XGMAC_INT_DMA_CH_SR_RPS, | |
9867e8fb | 481 | XGMAC_INT_DMA_CH_SR_TI_RI, |
c5aa9e3b LT |
482 | XGMAC_INT_DMA_CH_SR_FBE, |
483 | XGMAC_INT_DMA_ALL, | |
484 | }; | |
485 | ||
486 | enum xgbe_int_state { | |
487 | XGMAC_INT_STATE_SAVE, | |
488 | XGMAC_INT_STATE_RESTORE, | |
489 | }; | |
490 | ||
e78332b2 LT |
491 | enum xgbe_ecc_sec { |
492 | XGBE_ECC_SEC_TX, | |
493 | XGBE_ECC_SEC_RX, | |
494 | XGBE_ECC_SEC_DESC, | |
495 | }; | |
496 | ||
7c12aa08 LT |
497 | enum xgbe_speed { |
498 | XGBE_SPEED_1000 = 0, | |
499 | XGBE_SPEED_2500, | |
500 | XGBE_SPEED_10000, | |
501 | XGBE_SPEEDS, | |
502 | }; | |
503 | ||
b03a4a6f LT |
504 | enum xgbe_xpcs_access { |
505 | XGBE_XPCS_ACCESS_V1 = 0, | |
506 | XGBE_XPCS_ACCESS_V2, | |
507 | }; | |
508 | ||
a64def41 LT |
509 | enum xgbe_an_mode { |
510 | XGBE_AN_MODE_CL73 = 0, | |
d7445d1f | 511 | XGBE_AN_MODE_CL73_REDRV, |
1bf40ada LT |
512 | XGBE_AN_MODE_CL37, |
513 | XGBE_AN_MODE_CL37_SGMII, | |
a64def41 LT |
514 | XGBE_AN_MODE_NONE, |
515 | }; | |
516 | ||
7c12aa08 LT |
517 | enum xgbe_an { |
518 | XGBE_AN_READY = 0, | |
519 | XGBE_AN_PAGE_RECEIVED, | |
520 | XGBE_AN_INCOMPAT_LINK, | |
521 | XGBE_AN_COMPLETE, | |
522 | XGBE_AN_NO_LINK, | |
523 | XGBE_AN_ERROR, | |
524 | }; | |
525 | ||
526 | enum xgbe_rx { | |
527 | XGBE_RX_BPA = 0, | |
528 | XGBE_RX_XNP, | |
529 | XGBE_RX_COMPLETE, | |
530 | XGBE_RX_ERROR, | |
531 | }; | |
532 | ||
533 | enum xgbe_mode { | |
e57f7a3f LT |
534 | XGBE_MODE_KX_1000 = 0, |
535 | XGBE_MODE_KX_2500, | |
536 | XGBE_MODE_KR, | |
abf0a1c2 LT |
537 | XGBE_MODE_X, |
538 | XGBE_MODE_SGMII_100, | |
539 | XGBE_MODE_SGMII_1000, | |
540 | XGBE_MODE_SFI, | |
e57f7a3f | 541 | XGBE_MODE_UNKNOWN, |
7c12aa08 LT |
542 | }; |
543 | ||
544 | enum xgbe_speedset { | |
545 | XGBE_SPEEDSET_1000_10000 = 0, | |
546 | XGBE_SPEEDSET_2500_10000, | |
547 | }; | |
548 | ||
abf0a1c2 LT |
549 | enum xgbe_mdio_mode { |
550 | XGBE_MDIO_MODE_NONE = 0, | |
551 | XGBE_MDIO_MODE_CL22, | |
552 | XGBE_MDIO_MODE_CL45, | |
553 | }; | |
554 | ||
7c12aa08 LT |
555 | struct xgbe_phy { |
556 | u32 supported; | |
557 | u32 advertising; | |
558 | u32 lp_advertising; | |
559 | ||
560 | int address; | |
561 | ||
562 | int autoneg; | |
563 | int speed; | |
564 | int duplex; | |
7c12aa08 LT |
565 | |
566 | int link; | |
c1ce2f77 LT |
567 | |
568 | int pause_autoneg; | |
569 | int tx_pause; | |
570 | int rx_pause; | |
7c12aa08 LT |
571 | }; |
572 | ||
5ab1dcd5 LT |
573 | enum xgbe_i2c_cmd { |
574 | XGBE_I2C_CMD_READ = 0, | |
575 | XGBE_I2C_CMD_WRITE, | |
576 | }; | |
577 | ||
578 | struct xgbe_i2c_op { | |
579 | enum xgbe_i2c_cmd cmd; | |
580 | ||
581 | unsigned int target; | |
582 | ||
583 | void *buf; | |
584 | unsigned int len; | |
585 | }; | |
586 | ||
587 | struct xgbe_i2c_op_state { | |
588 | struct xgbe_i2c_op *op; | |
589 | ||
590 | unsigned int tx_len; | |
591 | unsigned char *tx_buf; | |
592 | ||
593 | unsigned int rx_len; | |
594 | unsigned char *rx_buf; | |
595 | ||
596 | unsigned int tx_abort_source; | |
597 | ||
598 | int ret; | |
599 | }; | |
600 | ||
601 | struct xgbe_i2c { | |
602 | unsigned int started; | |
603 | unsigned int max_speed_mode; | |
604 | unsigned int rx_fifo_size; | |
605 | unsigned int tx_fifo_size; | |
606 | ||
607 | struct xgbe_i2c_op_state op_state; | |
608 | }; | |
609 | ||
c5aa9e3b LT |
610 | struct xgbe_mmc_stats { |
611 | /* Tx Stats */ | |
612 | u64 txoctetcount_gb; | |
613 | u64 txframecount_gb; | |
614 | u64 txbroadcastframes_g; | |
615 | u64 txmulticastframes_g; | |
616 | u64 tx64octets_gb; | |
617 | u64 tx65to127octets_gb; | |
618 | u64 tx128to255octets_gb; | |
619 | u64 tx256to511octets_gb; | |
620 | u64 tx512to1023octets_gb; | |
621 | u64 tx1024tomaxoctets_gb; | |
622 | u64 txunicastframes_gb; | |
623 | u64 txmulticastframes_gb; | |
624 | u64 txbroadcastframes_gb; | |
625 | u64 txunderflowerror; | |
626 | u64 txoctetcount_g; | |
627 | u64 txframecount_g; | |
628 | u64 txpauseframes; | |
629 | u64 txvlanframes_g; | |
630 | ||
631 | /* Rx Stats */ | |
632 | u64 rxframecount_gb; | |
633 | u64 rxoctetcount_gb; | |
634 | u64 rxoctetcount_g; | |
635 | u64 rxbroadcastframes_g; | |
636 | u64 rxmulticastframes_g; | |
637 | u64 rxcrcerror; | |
638 | u64 rxrunterror; | |
639 | u64 rxjabbererror; | |
640 | u64 rxundersize_g; | |
641 | u64 rxoversize_g; | |
642 | u64 rx64octets_gb; | |
643 | u64 rx65to127octets_gb; | |
644 | u64 rx128to255octets_gb; | |
645 | u64 rx256to511octets_gb; | |
646 | u64 rx512to1023octets_gb; | |
647 | u64 rx1024tomaxoctets_gb; | |
648 | u64 rxunicastframes_g; | |
649 | u64 rxlengtherror; | |
650 | u64 rxoutofrangetype; | |
651 | u64 rxpauseframes; | |
652 | u64 rxfifooverflow; | |
653 | u64 rxvlanframes_gb; | |
654 | u64 rxwatchdogerror; | |
655 | }; | |
656 | ||
5452b2df LT |
657 | struct xgbe_ext_stats { |
658 | u64 tx_tso_packets; | |
659 | u64 rx_split_header_packets; | |
72c9ac4e | 660 | u64 rx_buffer_unavailable; |
5452b2df LT |
661 | }; |
662 | ||
c5aa9e3b LT |
663 | struct xgbe_hw_if { |
664 | int (*tx_complete)(struct xgbe_ring_desc *); | |
665 | ||
c5aa9e3b | 666 | int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr); |
b876382b | 667 | int (*config_rx_mode)(struct xgbe_prv_data *); |
c5aa9e3b LT |
668 | |
669 | int (*enable_rx_csum)(struct xgbe_prv_data *); | |
670 | int (*disable_rx_csum)(struct xgbe_prv_data *); | |
671 | ||
672 | int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); | |
673 | int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); | |
801c62d9 LT |
674 | int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); |
675 | int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); | |
676 | int (*update_vlan_hash_table)(struct xgbe_prv_data *); | |
c5aa9e3b LT |
677 | |
678 | int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); | |
679 | void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); | |
e57f7a3f | 680 | int (*set_speed)(struct xgbe_prv_data *, int); |
c5aa9e3b | 681 | |
732f2ab7 LT |
682 | int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, |
683 | enum xgbe_mdio_mode); | |
684 | int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int); | |
685 | int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, u16); | |
686 | ||
687 | int (*set_gpio)(struct xgbe_prv_data *, unsigned int); | |
688 | int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); | |
689 | ||
c5aa9e3b LT |
690 | void (*enable_tx)(struct xgbe_prv_data *); |
691 | void (*disable_tx)(struct xgbe_prv_data *); | |
692 | void (*enable_rx)(struct xgbe_prv_data *); | |
693 | void (*disable_rx)(struct xgbe_prv_data *); | |
694 | ||
695 | void (*powerup_tx)(struct xgbe_prv_data *); | |
696 | void (*powerdown_tx)(struct xgbe_prv_data *); | |
697 | void (*powerup_rx)(struct xgbe_prv_data *); | |
698 | void (*powerdown_rx)(struct xgbe_prv_data *); | |
699 | ||
700 | int (*init)(struct xgbe_prv_data *); | |
701 | int (*exit)(struct xgbe_prv_data *); | |
702 | ||
703 | int (*enable_int)(struct xgbe_channel *, enum xgbe_int); | |
704 | int (*disable_int)(struct xgbe_channel *, enum xgbe_int); | |
a9d41981 | 705 | void (*dev_xmit)(struct xgbe_channel *); |
c5aa9e3b LT |
706 | int (*dev_read)(struct xgbe_channel *); |
707 | void (*tx_desc_init)(struct xgbe_channel *); | |
708 | void (*rx_desc_init)(struct xgbe_channel *); | |
c5aa9e3b | 709 | void (*tx_desc_reset)(struct xgbe_ring_data *); |
8dee19e6 LT |
710 | void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *, |
711 | unsigned int); | |
c5aa9e3b LT |
712 | int (*is_last_desc)(struct xgbe_ring_desc *); |
713 | int (*is_context_desc)(struct xgbe_ring_desc *); | |
16958a2b | 714 | void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *); |
c5aa9e3b LT |
715 | |
716 | /* For FLOW ctrl */ | |
717 | int (*config_tx_flow_control)(struct xgbe_prv_data *); | |
718 | int (*config_rx_flow_control)(struct xgbe_prv_data *); | |
719 | ||
720 | /* For RX coalescing */ | |
721 | int (*config_rx_coalesce)(struct xgbe_prv_data *); | |
722 | int (*config_tx_coalesce)(struct xgbe_prv_data *); | |
723 | unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); | |
724 | unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); | |
725 | ||
726 | /* For RX and TX threshold config */ | |
727 | int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); | |
728 | int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); | |
729 | ||
730 | /* For RX and TX Store and Forward Mode config */ | |
731 | int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); | |
732 | int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); | |
733 | ||
734 | /* For TX DMA Operate on Second Frame config */ | |
735 | int (*config_osp_mode)(struct xgbe_prv_data *); | |
736 | ||
737 | /* For RX and TX PBL config */ | |
738 | int (*config_rx_pbl_val)(struct xgbe_prv_data *); | |
739 | int (*get_rx_pbl_val)(struct xgbe_prv_data *); | |
740 | int (*config_tx_pbl_val)(struct xgbe_prv_data *); | |
741 | int (*get_tx_pbl_val)(struct xgbe_prv_data *); | |
742 | int (*config_pblx8)(struct xgbe_prv_data *); | |
743 | ||
744 | /* For MMC statistics */ | |
745 | void (*rx_mmc_int)(struct xgbe_prv_data *); | |
746 | void (*tx_mmc_int)(struct xgbe_prv_data *); | |
747 | void (*read_mmc_stats)(struct xgbe_prv_data *); | |
23e4eef7 LT |
748 | |
749 | /* For Timestamp config */ | |
750 | int (*config_tstamp)(struct xgbe_prv_data *, unsigned int); | |
751 | void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int); | |
752 | void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec, | |
753 | unsigned int nsec); | |
754 | u64 (*get_tstamp_time)(struct xgbe_prv_data *); | |
755 | u64 (*get_tx_tstamp)(struct xgbe_prv_data *); | |
fca2d994 LT |
756 | |
757 | /* For Data Center Bridging config */ | |
b3b71597 | 758 | void (*config_tc)(struct xgbe_prv_data *); |
fca2d994 LT |
759 | void (*config_dcb_tc)(struct xgbe_prv_data *); |
760 | void (*config_dcb_pfc)(struct xgbe_prv_data *); | |
5b9dfe29 LT |
761 | |
762 | /* For Receive Side Scaling */ | |
763 | int (*enable_rss)(struct xgbe_prv_data *); | |
764 | int (*disable_rss)(struct xgbe_prv_data *); | |
f6ac8628 LT |
765 | int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *); |
766 | int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *); | |
e78332b2 LT |
767 | |
768 | /* For ECC */ | |
769 | void (*disable_ecc_ded)(struct xgbe_prv_data *); | |
770 | void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec); | |
c5aa9e3b LT |
771 | }; |
772 | ||
e57f7a3f LT |
773 | /* This structure represents implementation specific routines for an |
774 | * implementation of a PHY. All routines are required unless noted below. | |
775 | * Optional routines: | |
776 | * kr_training_pre, kr_training_post | |
777 | */ | |
778 | struct xgbe_phy_impl_if { | |
779 | /* Perform Setup/teardown actions */ | |
780 | int (*init)(struct xgbe_prv_data *); | |
781 | void (*exit)(struct xgbe_prv_data *); | |
782 | ||
783 | /* Perform start/stop specific actions */ | |
784 | int (*reset)(struct xgbe_prv_data *); | |
785 | int (*start)(struct xgbe_prv_data *); | |
786 | void (*stop)(struct xgbe_prv_data *); | |
787 | ||
788 | /* Return the link status */ | |
abf0a1c2 | 789 | int (*link_status)(struct xgbe_prv_data *, int *); |
e57f7a3f LT |
790 | |
791 | /* Indicate if a particular speed is valid */ | |
792 | bool (*valid_speed)(struct xgbe_prv_data *, int); | |
793 | ||
794 | /* Check if the specified mode can/should be used */ | |
795 | bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); | |
796 | /* Switch the PHY into various modes */ | |
797 | void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); | |
798 | /* Retrieve mode needed for a specific speed */ | |
799 | enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); | |
800 | /* Retrieve new/next mode when trying to auto-negotiate */ | |
801 | enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); | |
802 | /* Retrieve current mode */ | |
803 | enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); | |
804 | ||
a64def41 LT |
805 | /* Retrieve current auto-negotiation mode */ |
806 | enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); | |
807 | ||
abf0a1c2 LT |
808 | /* Configure auto-negotiation settings */ |
809 | int (*an_config)(struct xgbe_prv_data *); | |
810 | ||
d7445d1f LT |
811 | /* Set/override auto-negotiation advertisement settings */ |
812 | unsigned int (*an_advertising)(struct xgbe_prv_data *); | |
813 | ||
e57f7a3f LT |
814 | /* Process results of auto-negotiation */ |
815 | enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); | |
816 | ||
817 | /* Pre/Post KR training enablement support */ | |
818 | void (*kr_training_pre)(struct xgbe_prv_data *); | |
819 | void (*kr_training_post)(struct xgbe_prv_data *); | |
820 | }; | |
821 | ||
7c12aa08 | 822 | struct xgbe_phy_if { |
e57f7a3f LT |
823 | /* For PHY setup/teardown */ |
824 | int (*phy_init)(struct xgbe_prv_data *); | |
825 | void (*phy_exit)(struct xgbe_prv_data *); | |
7c12aa08 LT |
826 | |
827 | /* For PHY support when setting device up/down */ | |
828 | int (*phy_reset)(struct xgbe_prv_data *); | |
829 | int (*phy_start)(struct xgbe_prv_data *); | |
830 | void (*phy_stop)(struct xgbe_prv_data *); | |
831 | ||
832 | /* For PHY support while device is up */ | |
833 | void (*phy_status)(struct xgbe_prv_data *); | |
834 | int (*phy_config_aneg)(struct xgbe_prv_data *); | |
e57f7a3f LT |
835 | |
836 | /* For PHY settings validation */ | |
837 | bool (*phy_valid_speed)(struct xgbe_prv_data *, int); | |
838 | ||
47f164de LT |
839 | /* For single interrupt support */ |
840 | irqreturn_t (*an_isr)(int, struct xgbe_prv_data *); | |
841 | ||
e57f7a3f LT |
842 | /* PHY implementation specific services */ |
843 | struct xgbe_phy_impl_if phy_impl; | |
7c12aa08 LT |
844 | }; |
845 | ||
5ab1dcd5 LT |
846 | struct xgbe_i2c_if { |
847 | /* For initial I2C setup */ | |
848 | int (*i2c_init)(struct xgbe_prv_data *); | |
849 | ||
850 | /* For I2C support when setting device up/down */ | |
851 | int (*i2c_start)(struct xgbe_prv_data *); | |
852 | void (*i2c_stop)(struct xgbe_prv_data *); | |
853 | ||
854 | /* For performing I2C operations */ | |
855 | int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); | |
856 | ||
857 | /* For single interrupt support */ | |
858 | irqreturn_t (*i2c_isr)(int, struct xgbe_prv_data *); | |
859 | }; | |
860 | ||
c5aa9e3b LT |
861 | struct xgbe_desc_if { |
862 | int (*alloc_ring_resources)(struct xgbe_prv_data *); | |
863 | void (*free_ring_resources)(struct xgbe_prv_data *); | |
864 | int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *); | |
270894e7 LT |
865 | int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, |
866 | struct xgbe_ring_data *); | |
08dcc47c | 867 | void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); |
c5aa9e3b LT |
868 | void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); |
869 | void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); | |
870 | }; | |
871 | ||
872 | /* This structure contains flags that indicate what hardware features | |
873 | * or configurations are present in the device. | |
874 | */ | |
875 | struct xgbe_hw_features { | |
a9a4a2d9 LT |
876 | /* HW Version */ |
877 | unsigned int version; | |
878 | ||
c5aa9e3b LT |
879 | /* HW Feature Register0 */ |
880 | unsigned int gmii; /* 1000 Mbps support */ | |
881 | unsigned int vlhash; /* VLAN Hash Filter */ | |
882 | unsigned int sma; /* SMA(MDIO) Interface */ | |
883 | unsigned int rwk; /* PMT remote wake-up packet */ | |
884 | unsigned int mgk; /* PMT magic packet */ | |
885 | unsigned int mmc; /* RMON module */ | |
886 | unsigned int aoe; /* ARP Offload */ | |
dbedd44e | 887 | unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ |
c5aa9e3b LT |
888 | unsigned int eee; /* Energy Efficient Ethernet */ |
889 | unsigned int tx_coe; /* Tx Checksum Offload */ | |
890 | unsigned int rx_coe; /* Rx Checksum Offload */ | |
891 | unsigned int addn_mac; /* Additional MAC Addresses */ | |
892 | unsigned int ts_src; /* Timestamp Source */ | |
893 | unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ | |
894 | ||
895 | /* HW Feature Register1 */ | |
896 | unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ | |
897 | unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ | |
898 | unsigned int adv_ts_hi; /* Advance Timestamping High Word */ | |
386d325d | 899 | unsigned int dma_width; /* DMA width */ |
c5aa9e3b LT |
900 | unsigned int dcb; /* DCB Feature */ |
901 | unsigned int sph; /* Split Header Feature */ | |
902 | unsigned int tso; /* TCP Segmentation Offload */ | |
903 | unsigned int dma_debug; /* DMA Debug Registers */ | |
904 | unsigned int rss; /* Receive Side Scaling */ | |
fca2d994 | 905 | unsigned int tc_cnt; /* Number of Traffic Classes */ |
c5aa9e3b LT |
906 | unsigned int hash_table_size; /* Hash Table Size */ |
907 | unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ | |
908 | ||
909 | /* HW Feature Register2 */ | |
910 | unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ | |
911 | unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ | |
912 | unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ | |
913 | unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ | |
914 | unsigned int pps_out_num; /* Number of PPS outputs */ | |
915 | unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ | |
916 | }; | |
917 | ||
e57f7a3f LT |
918 | struct xgbe_version_data { |
919 | void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); | |
b03a4a6f | 920 | enum xgbe_xpcs_access xpcs_access; |
e5a20b90 | 921 | unsigned int mmc_64bit; |
bd8255d8 LT |
922 | unsigned int tx_max_fifo_size; |
923 | unsigned int rx_max_fifo_size; | |
aba9777a | 924 | unsigned int tx_tstamp_workaround; |
e78332b2 | 925 | unsigned int ecc_support; |
5ab1dcd5 | 926 | unsigned int i2c_support; |
e57f7a3f LT |
927 | }; |
928 | ||
c5aa9e3b LT |
929 | struct xgbe_prv_data { |
930 | struct net_device *netdev; | |
47f164de | 931 | struct pci_dev *pcidev; |
bd8255d8 | 932 | struct platform_device *platdev; |
82a19035 | 933 | struct acpi_device *adev; |
c5aa9e3b | 934 | struct device *dev; |
bd8255d8 | 935 | struct platform_device *phy_platdev; |
e57f7a3f LT |
936 | struct device *phy_dev; |
937 | ||
938 | /* Version related data */ | |
939 | struct xgbe_version_data *vdata; | |
c5aa9e3b | 940 | |
82a19035 LT |
941 | /* ACPI or DT flag */ |
942 | unsigned int use_acpi; | |
943 | ||
c5aa9e3b LT |
944 | /* XGMAC/XPCS related mmio registers */ |
945 | void __iomem *xgmac_regs; /* XGMAC CSRs */ | |
946 | void __iomem *xpcs_regs; /* XPCS MMD registers */ | |
7c12aa08 LT |
947 | void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */ |
948 | void __iomem *sir0_regs; /* SerDes integration registers (1/2) */ | |
949 | void __iomem *sir1_regs; /* SerDes integration registers (2/2) */ | |
47f164de LT |
950 | void __iomem *xprop_regs; /* XGBE property registers */ |
951 | void __iomem *xi2c_regs; /* XGBE I2C CSRs */ | |
c5aa9e3b LT |
952 | |
953 | /* Overall device lock */ | |
954 | spinlock_t lock; | |
955 | ||
ced3fcae LT |
956 | /* XPCS indirect addressing lock */ |
957 | spinlock_t xpcs_lock; | |
4eccbfc3 LT |
958 | unsigned int xpcs_window_def_reg; |
959 | unsigned int xpcs_window_sel_reg; | |
b03a4a6f LT |
960 | unsigned int xpcs_window; |
961 | unsigned int xpcs_window_size; | |
962 | unsigned int xpcs_window_mask; | |
c5aa9e3b | 963 | |
5b9dfe29 LT |
964 | /* RSS addressing mutex */ |
965 | struct mutex rss_mutex; | |
966 | ||
7c12aa08 LT |
967 | /* Flags representing xgbe_state */ |
968 | unsigned long dev_state; | |
969 | ||
e78332b2 LT |
970 | /* ECC support */ |
971 | unsigned long tx_sec_period; | |
972 | unsigned long tx_ded_period; | |
973 | unsigned long rx_sec_period; | |
974 | unsigned long rx_ded_period; | |
975 | unsigned long desc_sec_period; | |
976 | unsigned long desc_ded_period; | |
977 | ||
978 | unsigned int tx_sec_count; | |
979 | unsigned int tx_ded_count; | |
980 | unsigned int rx_sec_count; | |
981 | unsigned int rx_ded_count; | |
982 | unsigned int desc_ded_count; | |
983 | unsigned int desc_sec_count; | |
984 | ||
47f164de | 985 | struct msix_entry *msix_entries; |
9227dc5e | 986 | int dev_irq; |
47f164de LT |
987 | int ecc_irq; |
988 | int i2c_irq; | |
bd8255d8 | 989 | int channel_irq[XGBE_MAX_DMA_CHANNELS]; |
c5aa9e3b | 990 | |
47f164de LT |
991 | unsigned int per_channel_irq; |
992 | unsigned int irq_shared; | |
993 | unsigned int irq_count; | |
994 | unsigned int channel_irq_count; | |
4c70dd8a | 995 | unsigned int channel_irq_mode; |
47f164de | 996 | |
e78332b2 LT |
997 | char ecc_name[IFNAMSIZ + 32]; |
998 | ||
c5aa9e3b | 999 | struct xgbe_hw_if hw_if; |
7c12aa08 | 1000 | struct xgbe_phy_if phy_if; |
c5aa9e3b | 1001 | struct xgbe_desc_if desc_if; |
5ab1dcd5 | 1002 | struct xgbe_i2c_if i2c_if; |
c5aa9e3b | 1003 | |
cfa50c78 | 1004 | /* AXI DMA settings */ |
82a19035 | 1005 | unsigned int coherent; |
cfa50c78 LT |
1006 | unsigned int axdomain; |
1007 | unsigned int arcache; | |
1008 | unsigned int awcache; | |
1009 | ||
7c12aa08 LT |
1010 | /* Service routine support */ |
1011 | struct workqueue_struct *dev_workqueue; | |
1012 | struct work_struct service_work; | |
1013 | struct timer_list service_timer; | |
1014 | ||
c5aa9e3b LT |
1015 | /* Rings for Tx/Rx on a DMA channel */ |
1016 | struct xgbe_channel *channel; | |
bd8255d8 LT |
1017 | unsigned int tx_max_channel_count; |
1018 | unsigned int rx_max_channel_count; | |
c5aa9e3b LT |
1019 | unsigned int channel_count; |
1020 | unsigned int tx_ring_count; | |
1021 | unsigned int tx_desc_count; | |
1022 | unsigned int rx_ring_count; | |
1023 | unsigned int rx_desc_count; | |
1024 | ||
bd8255d8 LT |
1025 | unsigned int tx_max_q_count; |
1026 | unsigned int rx_max_q_count; | |
853eb16b LT |
1027 | unsigned int tx_q_count; |
1028 | unsigned int rx_q_count; | |
1029 | ||
c5aa9e3b LT |
1030 | /* Tx/Rx common settings */ |
1031 | unsigned int pblx8; | |
1032 | ||
1033 | /* Tx settings */ | |
1034 | unsigned int tx_sf_mode; | |
1035 | unsigned int tx_threshold; | |
1036 | unsigned int tx_pbl; | |
1037 | unsigned int tx_osp_mode; | |
bd8255d8 | 1038 | unsigned int tx_max_fifo_size; |
c5aa9e3b LT |
1039 | |
1040 | /* Rx settings */ | |
1041 | unsigned int rx_sf_mode; | |
1042 | unsigned int rx_threshold; | |
1043 | unsigned int rx_pbl; | |
bd8255d8 | 1044 | unsigned int rx_max_fifo_size; |
c5aa9e3b LT |
1045 | |
1046 | /* Tx coalescing settings */ | |
1047 | unsigned int tx_usecs; | |
1048 | unsigned int tx_frames; | |
1049 | ||
1050 | /* Rx coalescing settings */ | |
1051 | unsigned int rx_riwt; | |
4a57ebcc | 1052 | unsigned int rx_usecs; |
c5aa9e3b LT |
1053 | unsigned int rx_frames; |
1054 | ||
08dcc47c | 1055 | /* Current Rx buffer size */ |
c5aa9e3b LT |
1056 | unsigned int rx_buf_size; |
1057 | ||
1058 | /* Flow control settings */ | |
1059 | unsigned int pause_autoneg; | |
1060 | unsigned int tx_pause; | |
1061 | unsigned int rx_pause; | |
43e0dcf7 LT |
1062 | unsigned int rx_rfa[XGBE_MAX_QUEUES]; |
1063 | unsigned int rx_rfd[XGBE_MAX_QUEUES]; | |
c5aa9e3b | 1064 | |
5b9dfe29 LT |
1065 | /* Receive Side Scaling settings */ |
1066 | u8 rss_key[XGBE_RSS_HASH_KEY_SIZE]; | |
1067 | u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE]; | |
1068 | u32 rss_options; | |
1069 | ||
c5aa9e3b | 1070 | /* Netdev related settings */ |
82a19035 | 1071 | unsigned char mac_addr[ETH_ALEN]; |
c5aa9e3b LT |
1072 | netdev_features_t netdev_features; |
1073 | struct napi_struct napi; | |
1074 | struct xgbe_mmc_stats mmc_stats; | |
5452b2df | 1075 | struct xgbe_ext_stats ext_stats; |
c5aa9e3b | 1076 | |
801c62d9 LT |
1077 | /* Filtering support */ |
1078 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
1079 | ||
23e4eef7 LT |
1080 | /* Device clocks */ |
1081 | struct clk *sysclk; | |
82a19035 | 1082 | unsigned long sysclk_rate; |
23e4eef7 | 1083 | struct clk *ptpclk; |
82a19035 | 1084 | unsigned long ptpclk_rate; |
23e4eef7 LT |
1085 | |
1086 | /* Timestamp support */ | |
1087 | spinlock_t tstamp_lock; | |
1088 | struct ptp_clock_info ptp_clock_info; | |
1089 | struct ptp_clock *ptp_clock; | |
1090 | struct hwtstamp_config tstamp_config; | |
1091 | struct cyclecounter tstamp_cc; | |
1092 | struct timecounter tstamp_tc; | |
1093 | unsigned int tstamp_addend; | |
1094 | struct work_struct tx_tstamp_work; | |
1095 | struct sk_buff *tx_tstamp_skb; | |
1096 | u64 tx_tstamp; | |
c5aa9e3b | 1097 | |
fca2d994 LT |
1098 | /* DCB support */ |
1099 | struct ieee_ets *ets; | |
1100 | struct ieee_pfc *pfc; | |
1101 | unsigned int q2tc_map[XGBE_MAX_QUEUES]; | |
1102 | unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; | |
43e0dcf7 LT |
1103 | unsigned int pfcq[XGBE_MAX_QUEUES]; |
1104 | unsigned int pfc_rfa; | |
b3b71597 | 1105 | u8 num_tcs; |
fca2d994 | 1106 | |
c5aa9e3b LT |
1107 | /* Hardware features of the device */ |
1108 | struct xgbe_hw_features hw_feat; | |
1109 | ||
e78332b2 | 1110 | /* Device work structures */ |
c5aa9e3b | 1111 | struct work_struct restart_work; |
e78332b2 | 1112 | struct work_struct stopdev_work; |
c5aa9e3b LT |
1113 | |
1114 | /* Keeps track of power mode */ | |
1115 | unsigned int power_down; | |
1116 | ||
34bf65df LT |
1117 | /* Network interface message level setting */ |
1118 | u32 msg_enable; | |
1119 | ||
7c12aa08 LT |
1120 | /* Current PHY settings */ |
1121 | phy_interface_t phy_mode; | |
1122 | int phy_link; | |
1123 | int phy_speed; | |
7c12aa08 LT |
1124 | |
1125 | /* MDIO/PHY related settings */ | |
e57f7a3f LT |
1126 | unsigned int phy_started; |
1127 | void *phy_data; | |
7c12aa08 LT |
1128 | struct xgbe_phy phy; |
1129 | int mdio_mmd; | |
1130 | unsigned long link_check; | |
732f2ab7 | 1131 | struct completion mdio_complete; |
7c12aa08 | 1132 | |
d7445d1f LT |
1133 | unsigned int kr_redrv; |
1134 | ||
7c12aa08 LT |
1135 | char an_name[IFNAMSIZ + 32]; |
1136 | struct workqueue_struct *an_workqueue; | |
1137 | ||
1138 | int an_irq; | |
1139 | struct work_struct an_irq_work; | |
1140 | ||
7c12aa08 | 1141 | /* Auto-negotiation state machine support */ |
ced3fcae | 1142 | unsigned int an_int; |
1bf40ada | 1143 | unsigned int an_status; |
7c12aa08 LT |
1144 | struct mutex an_mutex; |
1145 | enum xgbe_an an_result; | |
1146 | enum xgbe_an an_state; | |
1147 | enum xgbe_rx kr_state; | |
1148 | enum xgbe_rx kx_state; | |
1149 | struct work_struct an_work; | |
1150 | unsigned int an_supported; | |
1151 | unsigned int parallel_detect; | |
1152 | unsigned int fec_ability; | |
1153 | unsigned long an_start; | |
a64def41 | 1154 | enum xgbe_an_mode an_mode; |
7c12aa08 | 1155 | |
5ab1dcd5 LT |
1156 | /* I2C support */ |
1157 | struct xgbe_i2c i2c; | |
1158 | struct mutex i2c_mutex; | |
1159 | struct completion i2c_complete; | |
1160 | char i2c_name[IFNAMSIZ + 32]; | |
1161 | ||
7c12aa08 LT |
1162 | unsigned int lpm_ctrl; /* CTRL1 for resume */ |
1163 | ||
c5aa9e3b LT |
1164 | #ifdef CONFIG_DEBUG_FS |
1165 | struct dentry *xgbe_debugfs; | |
1166 | ||
1167 | unsigned int debugfs_xgmac_reg; | |
1168 | ||
1169 | unsigned int debugfs_xpcs_mmd; | |
1170 | unsigned int debugfs_xpcs_reg; | |
47f164de LT |
1171 | |
1172 | unsigned int debugfs_xprop_reg; | |
5ab1dcd5 LT |
1173 | |
1174 | unsigned int debugfs_xi2c_reg; | |
c5aa9e3b LT |
1175 | #endif |
1176 | }; | |
1177 | ||
1178 | /* Function prototypes*/ | |
bd8255d8 LT |
1179 | struct xgbe_prv_data *xgbe_alloc_pdata(struct device *); |
1180 | void xgbe_free_pdata(struct xgbe_prv_data *); | |
1181 | void xgbe_set_counts(struct xgbe_prv_data *); | |
1182 | int xgbe_config_netdev(struct xgbe_prv_data *); | |
1183 | void xgbe_deconfig_netdev(struct xgbe_prv_data *); | |
1184 | ||
1185 | int xgbe_platform_init(void); | |
1186 | void xgbe_platform_exit(void); | |
47f164de LT |
1187 | #ifdef CONFIG_PCI |
1188 | int xgbe_pci_init(void); | |
1189 | void xgbe_pci_exit(void); | |
1190 | #else | |
1191 | static inline int xgbe_pci_init(void) { return 0; } | |
1192 | static inline void xgbe_pci_exit(void) { } | |
1193 | #endif | |
c5aa9e3b LT |
1194 | |
1195 | void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); | |
7c12aa08 | 1196 | void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); |
e57f7a3f | 1197 | void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); |
47f164de | 1198 | void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); |
c5aa9e3b | 1199 | void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); |
5ab1dcd5 | 1200 | void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); |
ce0b15d1 | 1201 | const struct net_device_ops *xgbe_get_netdev_ops(void); |
1202 | const struct ethtool_ops *xgbe_get_ethtool_ops(void); | |
1203 | ||
fca2d994 LT |
1204 | #ifdef CONFIG_AMD_XGBE_DCB |
1205 | const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void); | |
1206 | #endif | |
c5aa9e3b | 1207 | |
23e4eef7 LT |
1208 | void xgbe_ptp_register(struct xgbe_prv_data *); |
1209 | void xgbe_ptp_unregister(struct xgbe_prv_data *); | |
34bf65df LT |
1210 | void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *, |
1211 | unsigned int, unsigned int, unsigned int); | |
1212 | void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *, | |
c5aa9e3b LT |
1213 | unsigned int); |
1214 | void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool); | |
1215 | void xgbe_get_all_hw_features(struct xgbe_prv_data *); | |
1216 | int xgbe_powerup(struct net_device *, unsigned int); | |
1217 | int xgbe_powerdown(struct net_device *, unsigned int); | |
1218 | void xgbe_init_rx_coalesce(struct xgbe_prv_data *); | |
1219 | void xgbe_init_tx_coalesce(struct xgbe_prv_data *); | |
1220 | ||
1221 | #ifdef CONFIG_DEBUG_FS | |
1222 | void xgbe_debugfs_init(struct xgbe_prv_data *); | |
1223 | void xgbe_debugfs_exit(struct xgbe_prv_data *); | |
1224 | #else | |
1225 | static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {} | |
1226 | static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {} | |
1227 | #endif /* CONFIG_DEBUG_FS */ | |
1228 | ||
c5aa9e3b LT |
1229 | /* NOTE: Uncomment for function trace log messages in KERNEL LOG */ |
1230 | #if 0 | |
1231 | #define YDEBUG | |
1232 | #define YDEBUG_MDIO | |
1233 | #endif | |
1234 | ||
1235 | /* For debug prints */ | |
1236 | #ifdef YDEBUG | |
1237 | #define DBGPR(x...) pr_alert(x) | |
c5aa9e3b LT |
1238 | #else |
1239 | #define DBGPR(x...) do { } while (0) | |
c5aa9e3b LT |
1240 | #endif |
1241 | ||
1242 | #ifdef YDEBUG_MDIO | |
1243 | #define DBGPR_MDIO(x...) pr_alert(x) | |
1244 | #else | |
1245 | #define DBGPR_MDIO(x...) do { } while (0) | |
1246 | #endif | |
1247 | ||
1248 | #endif |