[linux-2.6-block.git] / drivers / net / ethernet / amd / xgbe / xgbe-main.c

/*
 * AMD 10Gb Ethernet driver
 *
 * This file is available to you under your choice of the following two
 * licenses:
 *
 * License 1: GPLv2
 *
 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
 *
 * This file is free software; you may copy, redistribute and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 2 of the License, or (at
 * your option) any later version.
 *
 * This file is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * This file incorporates work covered by the following copyright and
 * permission notice:
 *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
 *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
 *     Inc. unless otherwise expressly agreed to in writing between Synopsys
 *     and you.
 *
 *     The Software IS NOT an item of Licensed Software or Licensed Product
 *     under any End User Software License Agreement or Agreement for Licensed
 *     Product with Synopsys or any supplement thereto.  Permission is hereby
 *     granted, free of charge, to any person obtaining a copy of this software
 *     annotated with this license and the Software, to deal in the Software
 *     without restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
 *     of the Software, and to permit persons to whom the Software is furnished
 *     to do so, subject to the following conditions:
 *
 *     The above copyright notice and this permission notice shall be included
 *     in all copies or substantial portions of the Software.
 *
 *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 *     THE POSSIBILITY OF SUCH DAMAGE.
 *
 *
 * License 2: Modified BSD
 *
 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Advanced Micro Devices, Inc. nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * This file incorporates work covered by the following copyright and
 * permission notice:
 *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
 *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
 *     Inc. unless otherwise expressly agreed to in writing between Synopsys
 *     and you.
 *
 *     The Software IS NOT an item of Licensed Software or Licensed Product
 *     under any End User Software License Agreement or Agreement for Licensed
 *     Product with Synopsys or any supplement thereto.  Permission is hereby
 *     granted, free of charge, to any person obtaining a copy of this software
 *     annotated with this license and the Software, to deal in the Software
 *     without restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
 *     of the Software, and to permit persons to whom the Software is furnished
 *     to do so, subject to the following conditions:
 *
 *     The above copyright notice and this permission notice shall be included
 *     in all copies or substantial portions of the Software.
 *
 *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 *     THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/module.h>
#include <linux/device.h>
#include <linux/spinlock.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/io.h>
#include <linux/notifier.h>

#include "xgbe.h"
#include "xgbe-common.h"

MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_VERSION(XGBE_DRV_VERSION);
MODULE_DESCRIPTION(XGBE_DRV_DESC);

static int debug = -1;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, " Network interface message level setting");

static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN |
				      NETIF_MSG_IFUP);

static void xgbe_default_config(struct xgbe_prv_data *pdata)
{
	DBGPR("-->xgbe_default_config\n");

	pdata->blen = DMA_SBMR_BLEN_64;
	pdata->pbl = DMA_PBL_128;
	pdata->aal = 1;
	pdata->rd_osr_limit = 8;
	pdata->wr_osr_limit = 8;
	pdata->tx_sf_mode = MTL_TSF_ENABLE;
	pdata->tx_threshold = MTL_TX_THRESHOLD_64;
	pdata->tx_osp_mode = DMA_OSP_ENABLE;
	pdata->rx_sf_mode = MTL_RSF_DISABLE;
	pdata->rx_threshold = MTL_RX_THRESHOLD_64;
	pdata->pause_autoneg = 1;
	pdata->tx_pause = 1;
	pdata->rx_pause = 1;
	pdata->phy_speed = SPEED_UNKNOWN;
	pdata->power_down = 0;

	DBGPR("<--xgbe_default_config\n");
}

static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
{
	xgbe_init_function_ptrs_dev(&pdata->hw_if);
	xgbe_init_function_ptrs_phy(&pdata->phy_if);
	xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
	xgbe_init_function_ptrs_desc(&pdata->desc_if);

	pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
}

struct xgbe_prv_data *xgbe_alloc_pdata(struct device *dev)
{
	struct xgbe_prv_data *pdata;
	struct net_device *netdev;

	netdev = alloc_etherdev_mq(sizeof(struct xgbe_prv_data),
				   XGBE_MAX_DMA_CHANNELS);
	if (!netdev) {
		dev_err(dev, "alloc_etherdev_mq failed\n");
		return ERR_PTR(-ENOMEM);
	}
	SET_NETDEV_DEV(netdev, dev);
	pdata = netdev_priv(netdev);
	pdata->netdev = netdev;
	pdata->dev = dev;

	spin_lock_init(&pdata->lock);
	spin_lock_init(&pdata->xpcs_lock);
	mutex_init(&pdata->rss_mutex);
	spin_lock_init(&pdata->tstamp_lock);
	mutex_init(&pdata->i2c_mutex);
	init_completion(&pdata->i2c_complete);
	init_completion(&pdata->mdio_complete);
	INIT_LIST_HEAD(&pdata->vxlan_ports);

	pdata->msg_enable = netif_msg_init(debug, default_msg_level);

	set_bit(XGBE_DOWN, &pdata->dev_state);
	set_bit(XGBE_STOPPED, &pdata->dev_state);

	return pdata;
}

void xgbe_free_pdata(struct xgbe_prv_data *pdata)
{
	struct net_device *netdev = pdata->netdev;

	free_netdev(netdev);
}

void xgbe_set_counts(struct xgbe_prv_data *pdata)
{
	/* Set all the function pointers */
	xgbe_init_all_fptrs(pdata);

	/* Populate the hardware features */
	xgbe_get_all_hw_features(pdata);

	/* Set default max values if not provided */
	if (!pdata->tx_max_channel_count)
		pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
	if (!pdata->rx_max_channel_count)
		pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;

	if (!pdata->tx_max_q_count)
		pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
	if (!pdata->rx_max_q_count)
		pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;

	/* Calculate the number of Tx and Rx rings to be created
	 *  -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
	 *   the number of Tx queues to the number of Tx channels
	 *   enabled
	 *  -Rx (DMA) Channels do not map 1-to-1 so use the actual
	 *   number of Rx queues or maximum allowed
	 */
	pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
				     pdata->hw_feat.tx_ch_cnt);
	pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
				     pdata->tx_max_channel_count);
	pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
				     pdata->tx_max_q_count);

	pdata->tx_q_count = pdata->tx_ring_count;

	pdata->rx_ring_count = min_t(unsigned int, num_online_cpus(),
				     pdata->hw_feat.rx_ch_cnt);
	pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
				     pdata->rx_max_channel_count);

	pdata->rx_q_count = min_t(unsigned int, pdata->hw_feat.rx_q_cnt,
				  pdata->rx_max_q_count);

	if (netif_msg_probe(pdata)) {
		dev_dbg(pdata->dev, "TX/RX DMA channel count = %u/%u\n",
			pdata->tx_ring_count, pdata->rx_ring_count);
		dev_dbg(pdata->dev, "TX/RX hardware queue count = %u/%u\n",
			pdata->tx_q_count, pdata->rx_q_count);
	}
}

int xgbe_config_netdev(struct xgbe_prv_data *pdata)
{
	struct net_device *netdev = pdata->netdev;
	struct device *dev = pdata->dev;
	int ret;

	netdev->irq = pdata->dev_irq;
	netdev->base_addr = (unsigned long)pdata->xgmac_regs;
	memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);

	/* Initialize ECC timestamps */
	pdata->tx_sec_period = jiffies;
	pdata->tx_ded_period = jiffies;
	pdata->rx_sec_period = jiffies;
	pdata->rx_ded_period = jiffies;
	pdata->desc_sec_period = jiffies;
	pdata->desc_ded_period = jiffies;

	/* Issue software reset to device */
	ret = pdata->hw_if.exit(pdata);
	if (ret) {
		dev_err(dev, "software reset failed\n");
		return ret;
	}

	/* Set default configuration data */
	xgbe_default_config(pdata);

	/* Set the DMA mask */
	ret = dma_set_mask_and_coherent(dev,
					DMA_BIT_MASK(pdata->hw_feat.dma_width));
	if (ret) {
		dev_err(dev, "dma_set_mask_and_coherent failed\n");
		return ret;
	}

	/* Set default max values if not provided */
	if (!pdata->tx_max_fifo_size)
		pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
	if (!pdata->rx_max_fifo_size)
		pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;

	/* Set and validate the number of descriptors for a ring */
	BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT);
	pdata->tx_desc_count = XGBE_TX_DESC_CNT;

	BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT);
	pdata->rx_desc_count = XGBE_RX_DESC_CNT;

	/* Adjust the number of queues based on interrupts assigned */
	if (pdata->channel_irq_count) {
		pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
					     pdata->channel_irq_count);
		pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
					     pdata->channel_irq_count);

		if (netif_msg_probe(pdata))
			dev_dbg(pdata->dev,
				"adjusted TX/RX DMA channel count = %u/%u\n",
				pdata->tx_ring_count, pdata->rx_ring_count);
	}

	/* Initialize RSS hash key */
	netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));

	XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
	XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
	XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);

	/* Call MDIO/PHY initialization routine */
	pdata->debugfs_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
	ret = pdata->phy_if.phy_init(pdata);
	if (ret)
		return ret;

	/* Set device operations */
	netdev->netdev_ops = xgbe_get_netdev_ops();
	netdev->ethtool_ops = xgbe_get_ethtool_ops();
#ifdef CONFIG_AMD_XGBE_DCB
	netdev->dcbnl_ops = xgbe_get_dcbnl_ops();
#endif

	/* Set device features */
	netdev->hw_features = NETIF_F_SG |
			      NETIF_F_IP_CSUM |
			      NETIF_F_IPV6_CSUM |
			      NETIF_F_RXCSUM |
			      NETIF_F_TSO |
			      NETIF_F_TSO6 |
			      NETIF_F_GRO |
			      NETIF_F_HW_VLAN_CTAG_RX |
			      NETIF_F_HW_VLAN_CTAG_TX |
			      NETIF_F_HW_VLAN_CTAG_FILTER;

	if (pdata->hw_feat.rss)
		netdev->hw_features |= NETIF_F_RXHASH;

	if (pdata->hw_feat.vxn) {
		netdev->hw_enc_features = NETIF_F_SG |
					  NETIF_F_IP_CSUM |
					  NETIF_F_IPV6_CSUM |
					  NETIF_F_RXCSUM |
					  NETIF_F_TSO |
					  NETIF_F_TSO6 |
					  NETIF_F_GRO |
					  NETIF_F_GSO_UDP_TUNNEL |
					  NETIF_F_GSO_UDP_TUNNEL_CSUM |
					  NETIF_F_RX_UDP_TUNNEL_PORT;

		netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
				       NETIF_F_GSO_UDP_TUNNEL_CSUM |
				       NETIF_F_RX_UDP_TUNNEL_PORT;

		pdata->vxlan_offloads_set = 1;
		pdata->vxlan_features = NETIF_F_GSO_UDP_TUNNEL |
					NETIF_F_GSO_UDP_TUNNEL_CSUM |
					NETIF_F_RX_UDP_TUNNEL_PORT;
	}

	netdev->vlan_features |= NETIF_F_SG |
				 NETIF_F_IP_CSUM |
				 NETIF_F_IPV6_CSUM |
				 NETIF_F_TSO |
				 NETIF_F_TSO6;

	netdev->features |= netdev->hw_features;
	pdata->netdev_features = netdev->features;

	netdev->priv_flags |= IFF_UNICAST_FLT;
	netdev->min_mtu = 0;
	netdev->max_mtu = XGMAC_JUMBO_PACKET_MTU;

	/* Use default watchdog timeout */
	netdev->watchdog_timeo = 0;

	xgbe_init_rx_coalesce(pdata);
	xgbe_init_tx_coalesce(pdata);

	netif_carrier_off(netdev);
	ret = register_netdev(netdev);
	if (ret) {
		dev_err(dev, "net device registration failed\n");
		return ret;
	}

	if (IS_REACHABLE(CONFIG_PTP_1588_CLOCK))
		xgbe_ptp_register(pdata);

	xgbe_debugfs_init(pdata);

	netif_dbg(pdata, drv, pdata->netdev, "%u Tx software queues\n",
		  pdata->tx_ring_count);
	netif_dbg(pdata, drv, pdata->netdev, "%u Rx software queues\n",
		  pdata->rx_ring_count);

	return 0;
}

void xgbe_deconfig_netdev(struct xgbe_prv_data *pdata)
{
	struct net_device *netdev = pdata->netdev;

	xgbe_debugfs_exit(pdata);

	if (IS_REACHABLE(CONFIG_PTP_1588_CLOCK))
		xgbe_ptp_unregister(pdata);

	unregister_netdev(netdev);

	pdata->phy_if.phy_exit(pdata);
}

static int xgbe_netdev_event(struct notifier_block *nb, unsigned long event,
			     void *data)
{
	struct net_device *netdev = netdev_notifier_info_to_dev(data);
	struct xgbe_prv_data *pdata = netdev_priv(netdev);

	if (netdev->netdev_ops != xgbe_get_netdev_ops())
		goto out;

	switch (event) {
	case NETDEV_CHANGENAME:
		xgbe_debugfs_rename(pdata);
		break;

	default:
		break;
	}

out:
	return NOTIFY_DONE;
}

static struct notifier_block xgbe_netdev_notifier = {
	.notifier_call = xgbe_netdev_event,
};

static int __init xgbe_mod_init(void)
{
	int ret;

	ret = register_netdevice_notifier(&xgbe_netdev_notifier);
	if (ret)
		return ret;

	ret = xgbe_platform_init();
	if (ret)
		goto err_platform_init;

	ret = xgbe_pci_init();
	if (ret)
		goto err_pci_init;

	return 0;

err_pci_init:
	xgbe_platform_exit();
err_platform_init:
	unregister_netdevice_notifier(&xgbe_netdev_notifier);
	return ret;
}

static void __exit xgbe_mod_exit(void)
{
	xgbe_pci_exit();

	xgbe_platform_exit();

	unregister_netdevice_notifier(&xgbe_netdev_notifier);
}

module_init(xgbe_mod_init);
module_exit(xgbe_mod_exit);
Commit	Line	Data
c5aa9e3b LT	1	/*
	2	* AMD 10Gb Ethernet driver
	3	*
	4	* This file is available to you under your choice of the following two
	5	* licenses:
	6	*
	7	* License 1: GPLv2
	8	*
ced3fcae	9	* Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
c5aa9e3b LT	10	*
	11	* This file is free software; you may copy, redistribute and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation, either version 2 of the License, or (at
	14	* your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful, but
	17	* WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	19	* General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	23	*
	24	* This file incorporates work covered by the following copyright and
	25	* permission notice:
	26	* The Synopsys DWC ETHER XGMAC Software Driver and documentation
	27	* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
	28	* Inc. unless otherwise expressly agreed to in writing between Synopsys
	29	* and you.
	30	*
	31	* The Software IS NOT an item of Licensed Software or Licensed Product
	32	* under any End User Software License Agreement or Agreement for Licensed
	33	* Product with Synopsys or any supplement thereto. Permission is hereby
	34	* granted, free of charge, to any person obtaining a copy of this software
	35	* annotated with this license and the Software, to deal in the Software
	36	* without restriction, including without limitation the rights to use,
	37	* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
	38	* of the Software, and to permit persons to whom the Software is furnished
	39	* to do so, subject to the following conditions:
	40	*
	41	* The above copyright notice and this permission notice shall be included
	42	* in all copies or substantial portions of the Software.
	43	*
	44	* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
	45	* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
	46	* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
	47	* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
	48	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	49	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	50	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	51	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	52	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	53	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	54	* THE POSSIBILITY OF SUCH DAMAGE.
	55	*
	56	*
	57	* License 2: Modified BSD
	58	*
ced3fcae	59	* Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
c5aa9e3b LT	60	* All rights reserved.
	61	*
	62	* Redistribution and use in source and binary forms, with or without
	63	* modification, are permitted provided that the following conditions are met:
	64	* * Redistributions of source code must retain the above copyright
	65	* notice, this list of conditions and the following disclaimer.
	66	* * Redistributions in binary form must reproduce the above copyright
	67	* notice, this list of conditions and the following disclaimer in the
	68	* documentation and/or other materials provided with the distribution.
	69	* * Neither the name of Advanced Micro Devices, Inc. nor the
	70	* names of its contributors may be used to endorse or promote products
	71	* derived from this software without specific prior written permission.
	72	*
	73	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	74	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	75	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	76	* ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
	77	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	78	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	79	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	80	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	81	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	82	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	83	*
	84	* This file incorporates work covered by the following copyright and
	85	* permission notice:
	86	* The Synopsys DWC ETHER XGMAC Software Driver and documentation
	87	* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
	88	* Inc. unless otherwise expressly agreed to in writing between Synopsys
	89	* and you.
	90	*
	91	* The Software IS NOT an item of Licensed Software or Licensed Product
	92	* under any End User Software License Agreement or Agreement for Licensed
	93	* Product with Synopsys or any supplement thereto. Permission is hereby
	94	* granted, free of charge, to any person obtaining a copy of this software
	95	* annotated with this license and the Software, to deal in the Software
	96	* without restriction, including without limitation the rights to use,
	97	* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
	98	* of the Software, and to permit persons to whom the Software is furnished
	99	* to do so, subject to the following conditions:
	100	*
	101	* The above copyright notice and this permission notice shall be included
	102	* in all copies or substantial portions of the Software.
	103	*
	104	* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
	105	* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
	106	* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
	107	* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
	108	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	109	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	110	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	111	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	112	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	113	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	114	* THE POSSIBILITY OF SUCH DAMAGE.
	115	*/
	116
	117	#include <linux/module.h>
	118	#include <linux/device.h>
c5aa9e3b LT	119	#include <linux/spinlock.h>
	120	#include <linux/netdevice.h>
	121	#include <linux/etherdevice.h>
	122	#include <linux/io.h>
efbaa828	123	#include <linux/notifier.h>
c5aa9e3b LT	124
	125	#include "xgbe.h"
	126	#include "xgbe-common.h"
	127
c5aa9e3b LT	128	MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
	129	MODULE_LICENSE("Dual BSD/GPL");
	130	MODULE_VERSION(XGBE_DRV_VERSION);
	131	MODULE_DESCRIPTION(XGBE_DRV_DESC);
	132
34bf65df	133	static int debug = -1;
d3757ba4	134	module_param(debug, int, 0644);
34bf65df LT	135	MODULE_PARM_DESC(debug, " Network interface message level setting");
	136
	137	static const u32 default_msg_level = (NETIF_MSG_LINK \| NETIF_MSG_IFDOWN \|
	138	NETIF_MSG_IFUP);
	139
c5aa9e3b LT	140	static void xgbe_default_config(struct xgbe_prv_data *pdata)
	141	{
	142	DBGPR("-->xgbe_default_config\n");
	143
6f595959	144	pdata->blen = DMA_SBMR_BLEN_64;
7e1e6b86	145	pdata->pbl = DMA_PBL_128;
6f595959 LT	146	pdata->aal = 1;
	147	pdata->rd_osr_limit = 8;
	148	pdata->wr_osr_limit = 8;
c5aa9e3b LT	149	pdata->tx_sf_mode = MTL_TSF_ENABLE;
c5aa9e3b LT	150	pdata->tx_threshold = MTL_TX_THRESHOLD_64;
c5aa9e3b LT	151	pdata->tx_osp_mode = DMA_OSP_ENABLE;
	152	pdata->rx_sf_mode = MTL_RSF_DISABLE;
	153	pdata->rx_threshold = MTL_RX_THRESHOLD_64;
c5aa9e3b LT	154	pdata->pause_autoneg = 1;
	155	pdata->tx_pause = 1;
	156	pdata->rx_pause = 1;
916102c6	157	pdata->phy_speed = SPEED_UNKNOWN;
c5aa9e3b	158	pdata->power_down = 0;
c5aa9e3b LT	159
	160	DBGPR("<--xgbe_default_config\n");
	161	}
	162
	163	static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
	164	{
	165	xgbe_init_function_ptrs_dev(&pdata->hw_if);
7c12aa08	166	xgbe_init_function_ptrs_phy(&pdata->phy_if);
5ab1dcd5	167	xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
c5aa9e3b	168	xgbe_init_function_ptrs_desc(&pdata->desc_if);
e57f7a3f LT	169
e57f7a3f LT	170	pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
c5aa9e3b LT	171	}
c5aa9e3b LT	172
bd8255d8	173	struct xgbe_prv_data xgbe_alloc_pdata(struct device dev)
c5aa9e3b LT	174	{
c5aa9e3b LT	175	struct xgbe_prv_data *pdata;
c5aa9e3b	176	struct net_device *netdev;
c5aa9e3b LT	177
c5aa9e3b LT	178	netdev = alloc_etherdev_mq(sizeof(struct xgbe_prv_data),
d5c48582	179	XGBE_MAX_DMA_CHANNELS);
c5aa9e3b	180	if (!netdev) {
bd8255d8 LT	181	dev_err(dev, "alloc_etherdev_mq failed\n");
bd8255d8 LT	182	return ERR_PTR(-ENOMEM);
c5aa9e3b LT	183	}
	184	SET_NETDEV_DEV(netdev, dev);
	185	pdata = netdev_priv(netdev);
	186	pdata->netdev = netdev;
c5aa9e3b	187	pdata->dev = dev;
c5aa9e3b LT	188
c5aa9e3b LT	189	spin_lock_init(&pdata->lock);
ced3fcae	190	spin_lock_init(&pdata->xpcs_lock);
5b9dfe29	191	mutex_init(&pdata->rss_mutex);
23e4eef7	192	spin_lock_init(&pdata->tstamp_lock);
5ab1dcd5 LT	193	mutex_init(&pdata->i2c_mutex);
5ab1dcd5 LT	194	init_completion(&pdata->i2c_complete);
732f2ab7	195	init_completion(&pdata->mdio_complete);
1a510ccf	196	INIT_LIST_HEAD(&pdata->vxlan_ports);
c5aa9e3b	197
34bf65df LT	198	pdata->msg_enable = netif_msg_init(debug, default_msg_level);
34bf65df LT	199
7c12aa08	200	set_bit(XGBE_DOWN, &pdata->dev_state);
e78332b2	201	set_bit(XGBE_STOPPED, &pdata->dev_state);
7c12aa08	202
bd8255d8 LT	203	return pdata;
bd8255d8 LT	204	}
82a19035	205
bd8255d8 LT	206	void xgbe_free_pdata(struct xgbe_prv_data *pdata)
	207	{
	208	struct net_device *netdev = pdata->netdev;
e57f7a3f	209
bd8255d8 LT	210	free_netdev(netdev);
bd8255d8 LT	211	}
7c12aa08	212
bd8255d8 LT	213	void xgbe_set_counts(struct xgbe_prv_data *pdata)
	214	{
	215	/* Set all the function pointers */
	216	xgbe_init_all_fptrs(pdata);
c5aa9e3b	217
bd8255d8 LT	218	/* Populate the hardware features */
bd8255d8 LT	219	xgbe_get_all_hw_features(pdata);
c5aa9e3b	220
bd8255d8 LT	221	/* Set default max values if not provided */
	222	if (!pdata->tx_max_channel_count)
	223	pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
	224	if (!pdata->rx_max_channel_count)
	225	pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
82a19035	226
bd8255d8 LT	227	if (!pdata->tx_max_q_count)
	228	pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
	229	if (!pdata->rx_max_q_count)
	230	pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
82a19035	231
bd8255d8 LT	232	/* Calculate the number of Tx and Rx rings to be created
	233	* -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
	234	* the number of Tx queues to the number of Tx channels
	235	* enabled
	236	* -Rx (DMA) Channels do not map 1-to-1 so use the actual
	237	* number of Rx queues or maximum allowed
	238	*/
	239	pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
	240	pdata->hw_feat.tx_ch_cnt);
	241	pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
	242	pdata->tx_max_channel_count);
	243	pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
	244	pdata->tx_max_q_count);
cfa50c78	245
bd8255d8 LT	246	pdata->tx_q_count = pdata->tx_ring_count;
bd8255d8 LT	247
8d6b2e92	248	pdata->rx_ring_count = min_t(unsigned int, num_online_cpus(),
bd8255d8 LT	249	pdata->hw_feat.rx_ch_cnt);
	250	pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
	251	pdata->rx_max_channel_count);
	252
	253	pdata->rx_q_count = min_t(unsigned int, pdata->hw_feat.rx_q_cnt,
	254	pdata->rx_max_q_count);
9227dc5e	255
bd8255d8 LT	256	if (netif_msg_probe(pdata)) {
	257	dev_dbg(pdata->dev, "TX/RX DMA channel count = %u/%u\n",
	258	pdata->tx_ring_count, pdata->rx_ring_count);
	259	dev_dbg(pdata->dev, "TX/RX hardware queue count = %u/%u\n",
	260	pdata->tx_q_count, pdata->rx_q_count);
7c12aa08	261	}
bd8255d8 LT	262	}
	263
	264	int xgbe_config_netdev(struct xgbe_prv_data *pdata)
	265	{
	266	struct net_device *netdev = pdata->netdev;
	267	struct device *dev = pdata->dev;
bd8255d8	268	int ret;
7c12aa08	269
9227dc5e	270	netdev->irq = pdata->dev_irq;
c5aa9e3b	271	netdev->base_addr = (unsigned long)pdata->xgmac_regs;
82a19035	272	memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
c5aa9e3b	273
e78332b2 LT	274	/* Initialize ECC timestamps */
	275	pdata->tx_sec_period = jiffies;
	276	pdata->tx_ded_period = jiffies;
	277	pdata->rx_sec_period = jiffies;
	278	pdata->rx_ded_period = jiffies;
	279	pdata->desc_sec_period = jiffies;
	280	pdata->desc_ded_period = jiffies;
	281
c5aa9e3b	282	/* Issue software reset to device */
42d452dc LT	283	ret = pdata->hw_if.exit(pdata);
	284	if (ret) {
	285	dev_err(dev, "software reset failed\n");
	286	return ret;
	287	}
c5aa9e3b	288
c5aa9e3b LT	289	/* Set default configuration data */
	290	xgbe_default_config(pdata);
	291
386d325d	292	/* Set the DMA mask */
386d325d LT	293	ret = dma_set_mask_and_coherent(dev,
	294	DMA_BIT_MASK(pdata->hw_feat.dma_width));
	295	if (ret) {
	296	dev_err(dev, "dma_set_mask_and_coherent failed\n");
bd8255d8	297	return ret;
386d325d LT	298	}
386d325d LT	299
bd8255d8 LT	300	/* Set default max values if not provided */
	301	if (!pdata->tx_max_fifo_size)
	302	pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
	303	if (!pdata->rx_max_fifo_size)
	304	pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
	305
	306	/* Set and validate the number of descriptors for a ring */
	307	BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT);
	308	pdata->tx_desc_count = XGBE_TX_DESC_CNT;
	309
	310	BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT);
	311	pdata->rx_desc_count = XGBE_RX_DESC_CNT;
	312
47f164de LT	313	/* Adjust the number of queues based on interrupts assigned */
	314	if (pdata->channel_irq_count) {
	315	pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
	316	pdata->channel_irq_count);
	317	pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
	318	pdata->channel_irq_count);
	319
	320	if (netif_msg_probe(pdata))
	321	dev_dbg(pdata->dev,
	322	"adjusted TX/RX DMA channel count = %u/%u\n",
	323	pdata->tx_ring_count, pdata->rx_ring_count);
	324	}
	325
22447534	326	/* Initialize RSS hash key */
b2306303	327	netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));
5b9dfe29	328
5b9dfe29 LT	329	XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
	330	XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
	331	XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
	332
7c12aa08	333	/* Call MDIO/PHY initialization routine */
96f4d430	334	pdata->debugfs_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
e57f7a3f LT	335	ret = pdata->phy_if.phy_init(pdata);
e57f7a3f LT	336	if (ret)
bd8255d8	337	return ret;
c5aa9e3b	338
fca2d994	339	/* Set device operations */
c5aa9e3b LT	340	netdev->netdev_ops = xgbe_get_netdev_ops();
c5aa9e3b LT	341	netdev->ethtool_ops = xgbe_get_ethtool_ops();
fca2d994 LT	342	#ifdef CONFIG_AMD_XGBE_DCB
	343	netdev->dcbnl_ops = xgbe_get_dcbnl_ops();
	344	#endif
c5aa9e3b LT	345
	346	/* Set device features */
	347	netdev->hw_features = NETIF_F_SG \|
	348	NETIF_F_IP_CSUM \|
	349	NETIF_F_IPV6_CSUM \|
	350	NETIF_F_RXCSUM \|
	351	NETIF_F_TSO \|
	352	NETIF_F_TSO6 \|
	353	NETIF_F_GRO \|
	354	NETIF_F_HW_VLAN_CTAG_RX \|
801c62d9 LT	355	NETIF_F_HW_VLAN_CTAG_TX \|
801c62d9 LT	356	NETIF_F_HW_VLAN_CTAG_FILTER;
c5aa9e3b	357
5b9dfe29 LT	358	if (pdata->hw_feat.rss)
	359	netdev->hw_features \|= NETIF_F_RXHASH;
	360
1a510ccf LT	361	if (pdata->hw_feat.vxn) {
	362	netdev->hw_enc_features = NETIF_F_SG \|
	363	NETIF_F_IP_CSUM \|
	364	NETIF_F_IPV6_CSUM \|
	365	NETIF_F_RXCSUM \|
	366	NETIF_F_TSO \|
	367	NETIF_F_TSO6 \|
	368	NETIF_F_GRO \|
	369	NETIF_F_GSO_UDP_TUNNEL \|
	370	NETIF_F_GSO_UDP_TUNNEL_CSUM \|
	371	NETIF_F_RX_UDP_TUNNEL_PORT;
	372
	373	netdev->hw_features \|= NETIF_F_GSO_UDP_TUNNEL \|
	374	NETIF_F_GSO_UDP_TUNNEL_CSUM \|
	375	NETIF_F_RX_UDP_TUNNEL_PORT;
	376
	377	pdata->vxlan_offloads_set = 1;
	378	pdata->vxlan_features = NETIF_F_GSO_UDP_TUNNEL \|
	379	NETIF_F_GSO_UDP_TUNNEL_CSUM \|
	380	NETIF_F_RX_UDP_TUNNEL_PORT;
	381	}
	382
c5aa9e3b LT	383	netdev->vlan_features \|= NETIF_F_SG \|
	384	NETIF_F_IP_CSUM \|
	385	NETIF_F_IPV6_CSUM \|
	386	NETIF_F_TSO \|
	387	NETIF_F_TSO6;
	388
	389	netdev->features \|= netdev->hw_features;
	390	pdata->netdev_features = netdev->features;
	391
b85e4d89	392	netdev->priv_flags \|= IFF_UNICAST_FLT;
d894be57 JW	393	netdev->min_mtu = 0;
d894be57 JW	394	netdev->max_mtu = XGMAC_JUMBO_PACKET_MTU;
b85e4d89	395
a8373f1a LT	396	/* Use default watchdog timeout */
	397	netdev->watchdog_timeo = 0;
	398
c5aa9e3b LT	399	xgbe_init_rx_coalesce(pdata);
	400	xgbe_init_tx_coalesce(pdata);
	401
	402	netif_carrier_off(netdev);
	403	ret = register_netdev(netdev);
	404	if (ret) {
	405	dev_err(dev, "net device registration failed\n");
bd8255d8	406	return ret;
7c12aa08 LT	407	}
7c12aa08 LT	408
d1cbfd77 NP	409	if (IS_REACHABLE(CONFIG_PTP_1588_CLOCK))
d1cbfd77 NP	410	xgbe_ptp_register(pdata);
23e4eef7	411
c5aa9e3b LT	412	xgbe_debugfs_init(pdata);
c5aa9e3b LT	413
47f164de LT	414	netif_dbg(pdata, drv, pdata->netdev, "%u Tx software queues\n",
	415	pdata->tx_ring_count);
	416	netif_dbg(pdata, drv, pdata->netdev, "%u Rx software queues\n",
	417	pdata->rx_ring_count);
	418
c5aa9e3b	419	return 0;
c5aa9e3b LT	420	}
c5aa9e3b LT	421
bd8255d8	422	void xgbe_deconfig_netdev(struct xgbe_prv_data *pdata)
c5aa9e3b	423	{
bd8255d8	424	struct net_device *netdev = pdata->netdev;
c5aa9e3b LT	425
	426	xgbe_debugfs_exit(pdata);
	427
d1cbfd77 NP	428	if (IS_REACHABLE(CONFIG_PTP_1588_CLOCK))
d1cbfd77 NP	429	xgbe_ptp_unregister(pdata);
23e4eef7	430
25ff96a9 LT	431	unregister_netdev(netdev);
25ff96a9 LT	432
e57f7a3f	433	pdata->phy_if.phy_exit(pdata);
efbaa828	434	}
e57f7a3f	435
efbaa828 LT	436	static int xgbe_netdev_event(struct notifier_block *nb, unsigned long event,
	437	void *data)
	438	{
	439	struct net_device *netdev = netdev_notifier_info_to_dev(data);
	440	struct xgbe_prv_data *pdata = netdev_priv(netdev);
c5aa9e3b	441
efbaa828 LT	442	if (netdev->netdev_ops != xgbe_get_netdev_ops())
	443	goto out;
	444
	445	switch (event) {
	446	case NETDEV_CHANGENAME:
	447	xgbe_debugfs_rename(pdata);
	448	break;
	449
	450	default:
	451	break;
	452	}
	453
	454	out:
	455	return NOTIFY_DONE;
c5aa9e3b LT	456	}
c5aa9e3b LT	457
efbaa828 LT	458	static struct notifier_block xgbe_netdev_notifier = {
	459	.notifier_call = xgbe_netdev_event,
	460	};
	461
bd8255d8	462	static int __init xgbe_mod_init(void)
c5aa9e3b	463	{
bd8255d8	464	int ret;
c5aa9e3b	465
efbaa828 LT	466	ret = register_netdevice_notifier(&xgbe_netdev_notifier);
	467	if (ret)
	468	return ret;
	469
bd8255d8 LT	470	ret = xgbe_platform_init();
bd8255d8 LT	471	if (ret)
b6b4dc4c	472	goto err_platform_init;
c5aa9e3b	473
47f164de LT	474	ret = xgbe_pci_init();
47f164de LT	475	if (ret)
b6b4dc4c	476	goto err_pci_init;
47f164de	477
bd8255d8	478	return 0;
b6b4dc4c Y	479
	480	err_pci_init:
	481	xgbe_platform_exit();
	482	err_platform_init:
	483	unregister_netdevice_notifier(&xgbe_netdev_notifier);
	484	return ret;
c5aa9e3b LT	485	}
c5aa9e3b LT	486
bd8255d8	487	static void __exit xgbe_mod_exit(void)
c5aa9e3b	488	{
47f164de LT	489	xgbe_pci_exit();
47f164de LT	490
bd8255d8	491	xgbe_platform_exit();
efbaa828 LT	492
efbaa828 LT	493	unregister_netdevice_notifier(&xgbe_netdev_notifier);
c5aa9e3b	494	}
c5aa9e3b	495
bd8255d8 LT	496	module_init(xgbe_mod_init);
bd8255d8 LT	497	module_exit(xgbe_mod_exit);