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ethernet: use eth_hw_addr_set() for dev->addr_len cases
[linux-2.6-block.git] / drivers / net / ethernet / amd / xgbe / xgbe-drv.c
CommitLineData
c5aa9e3b
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
491aefb3 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
c5aa9e3b
LT		 10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
491aefb3 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
c5aa9e3b
LT		 60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
e78332b2 117#include <linux/module.h>
c5aa9e3b
LT		 118#include <linux/spinlock.h>
119#include <linux/tcp.h>
120#include <linux/if_vlan.h>
282ccf6e 121#include <linux/interrupt.h>
c5aa9e3b
LT		 122#include <linux/clk.h>
123#include <linux/if_ether.h>
23e4eef7 124#include <linux/net_tstamp.h>
88131a81 125#include <linux/phy.h>
1a510ccf 126#include <net/vxlan.h>
c5aa9e3b
LT		 127
128#include "xgbe.h"
129#include "xgbe-common.h"
130
e78332b2
LT		 131static unsigned int ecc_sec_info_threshold = 10;
132static unsigned int ecc_sec_warn_threshold = 10000;
133static unsigned int ecc_sec_period = 600;
134static unsigned int ecc_ded_threshold = 2;
135static unsigned int ecc_ded_period = 600;
136
137#ifdef CONFIG_AMD_XGBE_HAVE_ECC
138/* Only expose the ECC parameters if supported */
d3757ba4 139module_param(ecc_sec_info_threshold, uint, 0644);
e78332b2
LT		 140MODULE_PARM_DESC(ecc_sec_info_threshold,
141 " ECC corrected error informational threshold setting");
142
d3757ba4 143module_param(ecc_sec_warn_threshold, uint, 0644);
e78332b2
LT		 144MODULE_PARM_DESC(ecc_sec_warn_threshold,
145 " ECC corrected error warning threshold setting");
146
d3757ba4 147module_param(ecc_sec_period, uint, 0644);
e78332b2
LT		 148MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
149
d3757ba4 150module_param(ecc_ded_threshold, uint, 0644);
e78332b2
LT		 151MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
152
d3757ba4 153module_param(ecc_ded_period, uint, 0644);
e78332b2
LT		 154MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
155#endif
156
9227dc5e
LT		 157static int xgbe_one_poll(struct napi_struct *, int);
158static int xgbe_all_poll(struct napi_struct *, int);
e78332b2 159static void xgbe_stop(struct xgbe_prv_data *);
c5aa9e3b 160
18f9f0ac 161static void *xgbe_alloc_node(size_t size, int node)
4780b7ca 162{
18f9f0ac 163 void *mem;
4780b7ca 164
18f9f0ac
LT		 165 mem = kzalloc_node(size, GFP_KERNEL, node);
166 if (!mem)
167 mem = kzalloc(size, GFP_KERNEL);
168
169 return mem;
170}
171
172static void xgbe_free_channels(struct xgbe_prv_data *pdata)
173{
174 unsigned int i;
175
176 for (i = 0; i < ARRAY_SIZE(pdata->channel); i++) {
177 if (!pdata->channel[i])
178 continue;
179
180 kfree(pdata->channel[i]->rx_ring);
181 kfree(pdata->channel[i]->tx_ring);
182 kfree(pdata->channel[i]);
183
184 pdata->channel[i] = NULL;
185 }
4780b7ca 186
18f9f0ac
LT		 187 pdata->channel_count = 0;
188}
189
190static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
191{
192 struct xgbe_channel *channel;
193 struct xgbe_ring *ring;
194 unsigned int count, i;
f00ba49d 195 unsigned int cpu;
18f9f0ac 196 int node;
4780b7ca 197
18f9f0ac
LT		 198 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
199 for (i = 0; i < count; i++) {
f00ba49d
LT		 200 /* Attempt to use a CPU on the node the device is on */
201 cpu = cpumask_local_spread(i, dev_to_node(pdata->dev));
202
203 /* Set the allocation node based on the returned CPU */
204 node = cpu_to_node(cpu);
205
18f9f0ac
LT		 206 channel = xgbe_alloc_node(sizeof(*channel), node);
207 if (!channel)
208 goto err_mem;
209 pdata->channel[i] = channel;
4780b7ca 210
fb160ebd 211 snprintf(channel->name, sizeof(channel->name), "channel-%u", i);
4780b7ca
LT		 212 channel->pdata = pdata;
213 channel->queue_index = i;
214 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
215 (DMA_CH_INC * i);
18f9f0ac 216 channel->node = node;
f00ba49d 217 cpumask_set_cpu(cpu, &channel->affinity_mask);
4780b7ca 218
bd8255d8
LT		 219 if (pdata->per_channel_irq)
220 channel->dma_irq = pdata->channel_irq[i];
9227dc5e 221
4780b7ca 222 if (i < pdata->tx_ring_count) {
18f9f0ac
LT		 223 ring = xgbe_alloc_node(sizeof(*ring), node);
224 if (!ring)
225 goto err_mem;
226
227 spin_lock_init(&ring->lock);
228 ring->node = node;
229
230 channel->tx_ring = ring;
4780b7ca
LT		 231 }
232
233 if (i < pdata->rx_ring_count) {
18f9f0ac
LT		 234 ring = xgbe_alloc_node(sizeof(*ring), node);
235 if (!ring)
236 goto err_mem;
237
238 spin_lock_init(&ring->lock);
239 ring->node = node;
240
241 channel->rx_ring = ring;
4780b7ca
LT		 242 }
243
18f9f0ac 244 netif_dbg(pdata, drv, pdata->netdev,
f00ba49d 245 "%s: cpu=%u, node=%d\n", channel->name, cpu, node);
18f9f0ac 246
34bf65df
LT		 247 netif_dbg(pdata, drv, pdata->netdev,
248 "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
249 channel->name, channel->dma_regs, channel->dma_irq,
250 channel->tx_ring, channel->rx_ring);
4780b7ca
LT		 251 }
252
4780b7ca
LT		 253 pdata->channel_count = count;
254
255 return 0;
256
18f9f0ac
LT		 257err_mem:
258 xgbe_free_channels(pdata);
4780b7ca 259
18f9f0ac 260 return -ENOMEM;
4780b7ca
LT		 261}
262
c5aa9e3b
LT		 263static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
264{
265 return (ring->rdesc_count - (ring->cur - ring->dirty));
266}
267
270894e7
LT		 268static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
269{
270 return (ring->cur - ring->dirty);
271}
272
16958a2b
LT		 273static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
274 struct xgbe_ring *ring, unsigned int count)
275{
276 struct xgbe_prv_data *pdata = channel->pdata;
277
278 if (count > xgbe_tx_avail_desc(ring)) {
34bf65df
LT		 279 netif_info(pdata, drv, pdata->netdev,
280 "Tx queue stopped, not enough descriptors available\n");
16958a2b
LT		 281 netif_stop_subqueue(pdata->netdev, channel->queue_index);
282 ring->tx.queue_stopped = 1;
283
284 /* If we haven't notified the hardware because of xmit_more
285 * support, tell it now
286 */
287 if (ring->tx.xmit_more)
288 pdata->hw_if.tx_start_xmit(channel, ring);
289
290 return NETDEV_TX_BUSY;
291 }
292
293 return 0;
294}
295
c5aa9e3b
LT		 296static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
297{
298 unsigned int rx_buf_size;
299
c5aa9e3b 300 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
08dcc47c
LT		 301 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
302
d0a8ba6c
LT		 303 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
304 ~(XGBE_RX_BUF_ALIGN - 1);
c5aa9e3b
LT		 305
306 return rx_buf_size;
307}
308
4c70dd8a
LT		 309static void xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata,
310 struct xgbe_channel *channel)
c5aa9e3b
LT		 311{
312 struct xgbe_hw_if *hw_if = &pdata->hw_if;
9867e8fb 313 enum xgbe_int int_id;
4c70dd8a
LT		 314
315 if (channel->tx_ring && channel->rx_ring)
316 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
317 else if (channel->tx_ring)
318 int_id = XGMAC_INT_DMA_CH_SR_TI;
319 else if (channel->rx_ring)
320 int_id = XGMAC_INT_DMA_CH_SR_RI;
321 else
322 return;
323
324 hw_if->enable_int(channel, int_id);
325}
326
327static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
328{
c5aa9e3b
LT		 329 unsigned int i;
330
18f9f0ac
LT		 331 for (i = 0; i < pdata->channel_count; i++)
332 xgbe_enable_rx_tx_int(pdata, pdata->channel[i]);
4c70dd8a 333}
9867e8fb 334
4c70dd8a
LT		 335static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata,
336 struct xgbe_channel *channel)
337{
338 struct xgbe_hw_if *hw_if = &pdata->hw_if;
339 enum xgbe_int int_id;
340
341 if (channel->tx_ring && channel->rx_ring)
342 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
343 else if (channel->tx_ring)
344 int_id = XGMAC_INT_DMA_CH_SR_TI;
345 else if (channel->rx_ring)
346 int_id = XGMAC_INT_DMA_CH_SR_RI;
347 else
348 return;
349
350 hw_if->disable_int(channel, int_id);
c5aa9e3b
LT		 351}
352
353static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
354{
c5aa9e3b
LT		 355 unsigned int i;
356
18f9f0ac
LT		 357 for (i = 0; i < pdata->channel_count; i++)
358 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
c5aa9e3b
LT		 359}
360
e78332b2
LT		 361static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
362 unsigned int *count, const char *area)
363{
364 if (time_before(jiffies, *period)) {
365 (*count)++;
366 } else {
367 *period = jiffies + (ecc_sec_period * HZ);
368 *count = 1;
369 }
370
371 if (*count > ecc_sec_info_threshold)
372 dev_warn_once(pdata->dev,
373 "%s ECC corrected errors exceed informational threshold\n",
374 area);
375
376 if (*count > ecc_sec_warn_threshold) {
377 dev_warn_once(pdata->dev,
378 "%s ECC corrected errors exceed warning threshold\n",
379 area);
380 return true;
381 }
382
383 return false;
384}
385
386static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
387 unsigned int *count, const char *area)
388{
389 if (time_before(jiffies, *period)) {
390 (*count)++;
391 } else {
392 *period = jiffies + (ecc_ded_period * HZ);
393 *count = 1;
394 }
395
396 if (*count > ecc_ded_threshold) {
397 netdev_alert(pdata->netdev,
398 "%s ECC detected errors exceed threshold\n",
399 area);
400 return true;
401 }
402
403 return false;
404}
405
4c58700a 406static void xgbe_ecc_isr_task(struct tasklet_struct *t)
e78332b2 407{
4c58700a 408 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_ecc);
e78332b2
LT		 409 unsigned int ecc_isr;
410 bool stop = false;
411
412 /* Mask status with only the interrupts we care about */
413 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
414 ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
415 netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
416
417 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
418 stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
419 &pdata->tx_ded_count, "TX fifo");
420 }
421
422 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
423 stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
424 &pdata->rx_ded_count, "RX fifo");
425 }
426
427 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
428 stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
429 &pdata->desc_ded_count,
430 "descriptor cache");
431 }
432
433 if (stop) {
434 pdata->hw_if.disable_ecc_ded(pdata);
435 schedule_work(&pdata->stopdev_work);
436 goto out;
437 }
438
439 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
440 if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
441 &pdata->tx_sec_count, "TX fifo"))
442 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
443 }
444
445 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
446 if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
447 &pdata->rx_sec_count, "RX fifo"))
448 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
449
450 if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
451 if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
452 &pdata->desc_sec_count, "descriptor cache"))
453 pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
454
455out:
456 /* Clear all ECC interrupts */
457 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
458
85b85c85
LT		 459 /* Reissue interrupt if status is not clear */
460 if (pdata->vdata->irq_reissue_support)
461 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 1);
e78332b2
LT		 462}
463
85b85c85 464static irqreturn_t xgbe_ecc_isr(int irq, void *data)
c5aa9e3b
LT		 465{
466 struct xgbe_prv_data *pdata = data;
85b85c85
LT		 467
468 if (pdata->isr_as_tasklet)
469 tasklet_schedule(&pdata->tasklet_ecc);
470 else
4c58700a 471 xgbe_ecc_isr_task(&pdata->tasklet_ecc);
85b85c85
LT		 472
473 return IRQ_HANDLED;
474}
475
4c58700a 476static void xgbe_isr_task(struct tasklet_struct *t)
85b85c85 477{
4c58700a 478 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_dev);
c5aa9e3b
LT		 479 struct xgbe_hw_if *hw_if = &pdata->hw_if;
480 struct xgbe_channel *channel;
481 unsigned int dma_isr, dma_ch_isr;
732f2ab7 482 unsigned int mac_isr, mac_tssr, mac_mdioisr;
c5aa9e3b
LT		 483 unsigned int i;
484
485 /* The DMA interrupt status register also reports MAC and MTL
486 * interrupts. So for polling mode, we just need to check for
487 * this register to be non-zero
488 */
489 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
490 if (!dma_isr)
491 goto isr_done;
492
34bf65df 493 netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr);
c5aa9e3b
LT		 494
495 for (i = 0; i < pdata->channel_count; i++) {
496 if (!(dma_isr & (1 << i)))
497 continue;
498
18f9f0ac 499 channel = pdata->channel[i];
c5aa9e3b
LT		 500
501 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
34bf65df
LT		 502 netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n",
503 i, dma_ch_isr);
c5aa9e3b 504
fd972b73
LT		 505 /* The TI or RI interrupt bits may still be set even if using
506 * per channel DMA interrupts. Check to be sure those are not
507 * enabled before using the private data napi structure.
9227dc5e 508 */
fd972b73
LT		 509 if (!pdata->per_channel_irq &&
510 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
511 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
c5aa9e3b
LT		 512 if (napi_schedule_prep(&pdata->napi)) {
513 /* Disable Tx and Rx interrupts */
514 xgbe_disable_rx_tx_ints(pdata);
515
516 /* Turn on polling */
d518691c 517 __napi_schedule(&pdata->napi);
c5aa9e3b 518 }
4c70dd8a
LT		 519 } else {
520 /* Don't clear Rx/Tx status if doing per channel DMA
521 * interrupts, these will be cleared by the ISR for
522 * per channel DMA interrupts.
523 */
524 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
525 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
c5aa9e3b
LT		 526 }
527
72c9ac4e
LT		 528 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
529 pdata->ext_stats.rx_buffer_unavailable++;
530
c5aa9e3b
LT		 531 /* Restart the device on a Fatal Bus Error */
532 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
96aec911 533 schedule_work(&pdata->restart_work);
c5aa9e3b 534
4c70dd8a 535 /* Clear interrupt signals */
c5aa9e3b
LT		 536 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
537 }
538
539 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
540 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
541
732f2ab7
LT		 542 netif_dbg(pdata, intr, pdata->netdev, "MAC_ISR=%#010x\n",
543 mac_isr);
544
c5aa9e3b
LT		 545 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
546 hw_if->tx_mmc_int(pdata);
547
548 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
549 hw_if->rx_mmc_int(pdata);
23e4eef7
LT		 550
551 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
552 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
553
732f2ab7
LT		 554 netif_dbg(pdata, intr, pdata->netdev,
555 "MAC_TSSR=%#010x\n", mac_tssr);
556
23e4eef7
LT		 557 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
558 /* Read Tx Timestamp to clear interrupt */
559 pdata->tx_tstamp =
560 hw_if->get_tx_tstamp(pdata);
afb43e8a
LT		 561 queue_work(pdata->dev_workqueue,
562 &pdata->tx_tstamp_work);
23e4eef7
LT		 563 }
564 }
732f2ab7
LT		 565
566 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
567 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
568
569 netif_dbg(pdata, intr, pdata->netdev,
570 "MAC_MDIOISR=%#010x\n", mac_mdioisr);
571
572 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
573 SNGLCOMPINT))
574 complete(&pdata->mdio_complete);
575 }
c5aa9e3b
LT		 576 }
577
896b4db6 578isr_done:
47f164de
LT		 579 /* If there is not a separate AN irq, handle it here */
580 if (pdata->dev_irq == pdata->an_irq)
85b85c85 581 pdata->phy_if.an_isr(pdata);
47f164de 582
e78332b2
LT		 583 /* If there is not a separate ECC irq, handle it here */
584 if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
4c58700a 585 xgbe_ecc_isr_task(&pdata->tasklet_ecc);
e78332b2 586
5ab1dcd5
LT		 587 /* If there is not a separate I2C irq, handle it here */
588 if (pdata->vdata->i2c_support && (pdata->dev_irq == pdata->i2c_irq))
85b85c85
LT		 589 pdata->i2c_if.i2c_isr(pdata);
590
591 /* Reissue interrupt if status is not clear */
592 if (pdata->vdata->irq_reissue_support) {
593 unsigned int reissue_mask;
594
595 reissue_mask = 1 << 0;
596 if (!pdata->per_channel_irq)
a3276892 597 reissue_mask |= 0xffff << 4;
85b85c85
LT		 598
599 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask);
600 }
601}
602
603static irqreturn_t xgbe_isr(int irq, void *data)
604{
605 struct xgbe_prv_data *pdata = data;
606
607 if (pdata->isr_as_tasklet)
608 tasklet_schedule(&pdata->tasklet_dev);
609 else
4c58700a 610 xgbe_isr_task(&pdata->tasklet_dev);
5ab1dcd5 611
c5aa9e3b
LT		 612 return IRQ_HANDLED;
613}
614
9227dc5e
LT		 615static irqreturn_t xgbe_dma_isr(int irq, void *data)
616{
617 struct xgbe_channel *channel = data;
4c70dd8a
LT		 618 struct xgbe_prv_data *pdata = channel->pdata;
619 unsigned int dma_status;
9227dc5e
LT		 620
621 /* Per channel DMA interrupts are enabled, so we use the per
622 * channel napi structure and not the private data napi structure
623 */
624 if (napi_schedule_prep(&channel->napi)) {
625 /* Disable Tx and Rx interrupts */
4c70dd8a
LT		 626 if (pdata->channel_irq_mode)
627 xgbe_disable_rx_tx_int(pdata, channel);
628 else
629 disable_irq_nosync(channel->dma_irq);
9227dc5e
LT		 630
631 /* Turn on polling */
79349422 632 __napi_schedule_irqoff(&channel->napi);
9227dc5e
LT		 633 }
634
4c70dd8a
LT		 635 /* Clear Tx/Rx signals */
636 dma_status = 0;
637 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
638 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
639 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
640
9227dc5e
LT		 641 return IRQ_HANDLED;
642}
643
c6c52ba1 644static void xgbe_tx_timer(struct timer_list *t)
c5aa9e3b 645{
c6c52ba1 646 struct xgbe_channel *channel = from_timer(channel, t, tx_timer);
c5aa9e3b 647 struct xgbe_prv_data *pdata = channel->pdata;
9227dc5e 648 struct napi_struct *napi;
c5aa9e3b
LT		 649
650 DBGPR("-->xgbe_tx_timer\n");
651
9227dc5e
LT		 652 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
653
9227dc5e 654 if (napi_schedule_prep(napi)) {
c5aa9e3b 655 /* Disable Tx and Rx interrupts */
9227dc5e 656 if (pdata->per_channel_irq)
4c70dd8a
LT		 657 if (pdata->channel_irq_mode)
658 xgbe_disable_rx_tx_int(pdata, channel);
659 else
660 disable_irq_nosync(channel->dma_irq);
9227dc5e
LT		 661 else
662 xgbe_disable_rx_tx_ints(pdata);
c5aa9e3b
LT		 663
664 /* Turn on polling */
9227dc5e 665 __napi_schedule(napi);
c5aa9e3b
LT		 666 }
667
668 channel->tx_timer_active = 0;
669
c5aa9e3b 670 DBGPR("<--xgbe_tx_timer\n");
c5aa9e3b
LT		 671}
672
7c12aa08
LT		 673static void xgbe_service(struct work_struct *work)
674{
675 struct xgbe_prv_data *pdata = container_of(work,
676 struct xgbe_prv_data,
677 service_work);
678
679 pdata->phy_if.phy_status(pdata);
680}
681
c6c52ba1 682static void xgbe_service_timer(struct timer_list *t)
7c12aa08 683{
c6c52ba1 684 struct xgbe_prv_data *pdata = from_timer(pdata, t, service_timer);
7c12aa08 685
afb43e8a 686 queue_work(pdata->dev_workqueue, &pdata->service_work);
7c12aa08
LT		 687
688 mod_timer(&pdata->service_timer, jiffies + HZ);
689}
690
691static void xgbe_init_timers(struct xgbe_prv_data *pdata)
c5aa9e3b
LT		 692{
693 struct xgbe_channel *channel;
694 unsigned int i;
695
c6c52ba1 696 timer_setup(&pdata->service_timer, xgbe_service_timer, 0);
c5aa9e3b 697
18f9f0ac
LT		 698 for (i = 0; i < pdata->channel_count; i++) {
699 channel = pdata->channel[i];
c5aa9e3b
LT		 700 if (!channel->tx_ring)
701 break;
702
c6c52ba1 703 timer_setup(&channel->tx_timer, xgbe_tx_timer, 0);
c5aa9e3b 704 }
7c12aa08 705}
c5aa9e3b 706
7c12aa08
LT		 707static void xgbe_start_timers(struct xgbe_prv_data *pdata)
708{
709 mod_timer(&pdata->service_timer, jiffies + HZ);
c5aa9e3b
LT		 710}
711
7c12aa08 712static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
c5aa9e3b
LT		 713{
714 struct xgbe_channel *channel;
715 unsigned int i;
716
7c12aa08 717 del_timer_sync(&pdata->service_timer);
c5aa9e3b 718
18f9f0ac
LT		 719 for (i = 0; i < pdata->channel_count; i++) {
720 channel = pdata->channel[i];
c5aa9e3b
LT		 721 if (!channel->tx_ring)
722 break;
723
c635eaac 724 del_timer_sync(&channel->tx_timer);
c5aa9e3b 725 }
c5aa9e3b
LT		 726}
727
728void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
729{
730 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
731 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
732
c5aa9e3b
LT		 733 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
734 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
735 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
736
737 memset(hw_feat, 0, sizeof(*hw_feat));
738
a9a4a2d9
LT		 739 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
740
c5aa9e3b
LT		 741 /* Hardware feature register 0 */
742 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
743 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
744 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
745 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
746 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
747 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
748 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
749 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
750 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
751 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
752 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
753 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
754 ADDMACADRSEL);
755 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
756 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
1a510ccf 757 hw_feat->vxn = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VXN);
c5aa9e3b
LT		 758
759 /* Hardware feature register 1 */
760 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
761 RXFIFOSIZE);
762 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
763 TXFIFOSIZE);
73c25916 764 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
386d325d 765 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
c5aa9e3b
LT		 766 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
767 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
768 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
769 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
cf180b8a 770 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
fca2d994 771 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
c5aa9e3b
LT		 772 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
773 HASHTBLSZ);
774 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
775 L3L4FNUM);
776
777 /* Hardware feature register 2 */
778 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
779 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
780 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
781 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
782 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
783 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
784
b85e4d89
LT		 785 /* Translate the Hash Table size into actual number */
786 switch (hw_feat->hash_table_size) {
787 case 0:
788 break;
789 case 1:
790 hw_feat->hash_table_size = 64;
791 break;
792 case 2:
793 hw_feat->hash_table_size = 128;
794 break;
795 case 3:
796 hw_feat->hash_table_size = 256;
797 break;
798 }
799
386d325d
LT		 800 /* Translate the address width setting into actual number */
801 switch (hw_feat->dma_width) {
802 case 0:
803 hw_feat->dma_width = 32;
804 break;
805 case 1:
806 hw_feat->dma_width = 40;
807 break;
808 case 2:
809 hw_feat->dma_width = 48;
810 break;
811 default:
812 hw_feat->dma_width = 32;
813 }
814
211fcf6d 815 /* The Queue, Channel and TC counts are zero based so increment them
c5aa9e3b
LT		 816 * to get the actual number
817 */
818 hw_feat->rx_q_cnt++;
819 hw_feat->tx_q_cnt++;
820 hw_feat->rx_ch_cnt++;
821 hw_feat->tx_ch_cnt++;
211fcf6d 822 hw_feat->tc_cnt++;
c5aa9e3b 823
bd8255d8
LT		 824 /* Translate the fifo sizes into actual numbers */
825 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7);
826 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7);
827
3be95872
LT		 828 if (netif_msg_probe(pdata)) {
829 dev_dbg(pdata->dev, "Hardware features:\n");
830
831 /* Hardware feature register 0 */
832 dev_dbg(pdata->dev, " 1GbE support : %s\n",
833 hw_feat->gmii ? "yes" : "no");
834 dev_dbg(pdata->dev, " VLAN hash filter : %s\n",
835 hw_feat->vlhash ? "yes" : "no");
836 dev_dbg(pdata->dev, " MDIO interface : %s\n",
837 hw_feat->sma ? "yes" : "no");
838 dev_dbg(pdata->dev, " Wake-up packet support : %s\n",
839 hw_feat->rwk ? "yes" : "no");
840 dev_dbg(pdata->dev, " Magic packet support : %s\n",
841 hw_feat->mgk ? "yes" : "no");
842 dev_dbg(pdata->dev, " Management counters : %s\n",
843 hw_feat->mmc ? "yes" : "no");
844 dev_dbg(pdata->dev, " ARP offload : %s\n",
845 hw_feat->aoe ? "yes" : "no");
846 dev_dbg(pdata->dev, " IEEE 1588-2008 Timestamp : %s\n",
847 hw_feat->ts ? "yes" : "no");
848 dev_dbg(pdata->dev, " Energy Efficient Ethernet : %s\n",
849 hw_feat->eee ? "yes" : "no");
850 dev_dbg(pdata->dev, " TX checksum offload : %s\n",
851 hw_feat->tx_coe ? "yes" : "no");
852 dev_dbg(pdata->dev, " RX checksum offload : %s\n",
853 hw_feat->rx_coe ? "yes" : "no");
854 dev_dbg(pdata->dev, " Additional MAC addresses : %u\n",
855 hw_feat->addn_mac);
856 dev_dbg(pdata->dev, " Timestamp source : %s\n",
857 (hw_feat->ts_src == 1) ? "internal" :
858 (hw_feat->ts_src == 2) ? "external" :
859 (hw_feat->ts_src == 3) ? "internal/external" : "n/a");
860 dev_dbg(pdata->dev, " SA/VLAN insertion : %s\n",
861 hw_feat->sa_vlan_ins ? "yes" : "no");
1a510ccf
LT		 862 dev_dbg(pdata->dev, " VXLAN/NVGRE support : %s\n",
863 hw_feat->vxn ? "yes" : "no");
3be95872
LT		 864
865 /* Hardware feature register 1 */
866 dev_dbg(pdata->dev, " RX fifo size : %u\n",
867 hw_feat->rx_fifo_size);
868 dev_dbg(pdata->dev, " TX fifo size : %u\n",
869 hw_feat->tx_fifo_size);
870 dev_dbg(pdata->dev, " IEEE 1588 high word : %s\n",
871 hw_feat->adv_ts_hi ? "yes" : "no");
872 dev_dbg(pdata->dev, " DMA width : %u\n",
873 hw_feat->dma_width);
874 dev_dbg(pdata->dev, " Data Center Bridging : %s\n",
875 hw_feat->dcb ? "yes" : "no");
876 dev_dbg(pdata->dev, " Split header : %s\n",
877 hw_feat->sph ? "yes" : "no");
878 dev_dbg(pdata->dev, " TCP Segmentation Offload : %s\n",
879 hw_feat->tso ? "yes" : "no");
880 dev_dbg(pdata->dev, " Debug memory interface : %s\n",
881 hw_feat->dma_debug ? "yes" : "no");
882 dev_dbg(pdata->dev, " Receive Side Scaling : %s\n",
883 hw_feat->rss ? "yes" : "no");
884 dev_dbg(pdata->dev, " Traffic Class count : %u\n",
885 hw_feat->tc_cnt);
886 dev_dbg(pdata->dev, " Hash table size : %u\n",
887 hw_feat->hash_table_size);
888 dev_dbg(pdata->dev, " L3/L4 Filters : %u\n",
889 hw_feat->l3l4_filter_num);
890
891 /* Hardware feature register 2 */
892 dev_dbg(pdata->dev, " RX queue count : %u\n",
893 hw_feat->rx_q_cnt);
894 dev_dbg(pdata->dev, " TX queue count : %u\n",
895 hw_feat->tx_q_cnt);
896 dev_dbg(pdata->dev, " RX DMA channel count : %u\n",
897 hw_feat->rx_ch_cnt);
898 dev_dbg(pdata->dev, " TX DMA channel count : %u\n",
899 hw_feat->rx_ch_cnt);
900 dev_dbg(pdata->dev, " PPS outputs : %u\n",
901 hw_feat->pps_out_num);
902 dev_dbg(pdata->dev, " Auxiliary snapshot inputs : %u\n",
903 hw_feat->aux_snap_num);
904 }
c5aa9e3b
LT		 905}
906
4df587ab
JK		 907static int xgbe_vxlan_set_port(struct net_device *netdev, unsigned int table,
908 unsigned int entry, struct udp_tunnel_info *ti)
1a510ccf 909{
4df587ab 910 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1a510ccf 911
4df587ab
JK		 912 pdata->vxlan_port = be16_to_cpu(ti->port);
913 pdata->hw_if.enable_vxlan(pdata);
1a510ccf 914
4df587ab 915 return 0;
1a510ccf
LT		 916}
917
4df587ab
JK		 918static int xgbe_vxlan_unset_port(struct net_device *netdev, unsigned int table,
919 unsigned int entry, struct udp_tunnel_info *ti)
1a510ccf 920{
4df587ab 921 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1a510ccf
LT		 922
923 pdata->hw_if.disable_vxlan(pdata);
1a510ccf 924 pdata->vxlan_port = 0;
1a510ccf 925
4df587ab 926 return 0;
1a510ccf
LT		 927}
928
4df587ab
JK		 929static const struct udp_tunnel_nic_info xgbe_udp_tunnels = {
930 .set_port = xgbe_vxlan_set_port,
931 .unset_port = xgbe_vxlan_unset_port,
932 .flags = UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
933 .tables = {
934 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
935 },
936};
1a510ccf 937
4df587ab 938const struct udp_tunnel_nic_info *xgbe_get_udp_tunnel_info(void)
1a510ccf 939{
4df587ab 940 return &xgbe_udp_tunnels;
1a510ccf
LT		 941}
942
c5aa9e3b
LT		 943static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
944{
9227dc5e
LT		 945 struct xgbe_channel *channel;
946 unsigned int i;
947
948 if (pdata->per_channel_irq) {
18f9f0ac
LT		 949 for (i = 0; i < pdata->channel_count; i++) {
950 channel = pdata->channel[i];
9227dc5e
LT		 951 if (add)
952 netif_napi_add(pdata->netdev, &channel->napi,
953 xgbe_one_poll, NAPI_POLL_WEIGHT);
954
955 napi_enable(&channel->napi);
956 }
957 } else {
958 if (add)
959 netif_napi_add(pdata->netdev, &pdata->napi,
960 xgbe_all_poll, NAPI_POLL_WEIGHT);
961
962 napi_enable(&pdata->napi);
963 }
c5aa9e3b
LT		 964}
965
ff42606e 966static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
c5aa9e3b 967{
9227dc5e
LT		 968 struct xgbe_channel *channel;
969 unsigned int i;
970
971 if (pdata->per_channel_irq) {
18f9f0ac
LT		 972 for (i = 0; i < pdata->channel_count; i++) {
973 channel = pdata->channel[i];
9227dc5e 974 napi_disable(&channel->napi);
ff42606e 975
9227dc5e
LT		 976 if (del)
977 netif_napi_del(&channel->napi);
978 }
979 } else {
980 napi_disable(&pdata->napi);
981
982 if (del)
983 netif_napi_del(&pdata->napi);
984 }
c5aa9e3b
LT		 985}
986
c30e76a7
LT		 987static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
988{
989 struct xgbe_channel *channel;
990 struct net_device *netdev = pdata->netdev;
991 unsigned int i;
992 int ret;
993
4c58700a
AP		 994 tasklet_setup(&pdata->tasklet_dev, xgbe_isr_task);
995 tasklet_setup(&pdata->tasklet_ecc, xgbe_ecc_isr_task);
85b85c85 996
c30e76a7 997 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
efbaa828 998 netdev_name(netdev), pdata);
c30e76a7
LT		 999 if (ret) {
1000 netdev_alert(netdev, "error requesting irq %d\n",
1001 pdata->dev_irq);
1002 return ret;
1003 }
1004
e78332b2
LT		 1005 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
1006 ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
1007 0, pdata->ecc_name, pdata);
1008 if (ret) {
1009 netdev_alert(netdev, "error requesting ecc irq %d\n",
1010 pdata->ecc_irq);
1011 goto err_dev_irq;
1012 }
1013 }
1014
c30e76a7
LT		 1015 if (!pdata->per_channel_irq)
1016 return 0;
1017
18f9f0ac
LT		 1018 for (i = 0; i < pdata->channel_count; i++) {
1019 channel = pdata->channel[i];
c30e76a7
LT		 1020 snprintf(channel->dma_irq_name,
1021 sizeof(channel->dma_irq_name) - 1,
1022 "%s-TxRx-%u", netdev_name(netdev),
1023 channel->queue_index);
1024
1025 ret = devm_request_irq(pdata->dev, channel->dma_irq,
1026 xgbe_dma_isr, 0,
1027 channel->dma_irq_name, channel);
1028 if (ret) {
1029 netdev_alert(netdev, "error requesting irq %d\n",
1030 channel->dma_irq);
e78332b2 1031 goto err_dma_irq;
c30e76a7 1032 }
f00ba49d
LT		 1033
1034 irq_set_affinity_hint(channel->dma_irq,
1035 &channel->affinity_mask);
c30e76a7
LT		 1036 }
1037
1038 return 0;
1039
e78332b2 1040err_dma_irq:
c30e76a7 1041 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
18f9f0ac
LT		 1042 for (i--; i < pdata->channel_count; i--) {
1043 channel = pdata->channel[i];
1044
f00ba49d 1045 irq_set_affinity_hint(channel->dma_irq, NULL);
c30e76a7 1046 devm_free_irq(pdata->dev, channel->dma_irq, channel);
18f9f0ac 1047 }
c30e76a7 1048
e78332b2
LT		 1049 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1050 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1051
1052err_dev_irq:
c30e76a7
LT		 1053 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1054
1055 return ret;
1056}
1057
1058static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
1059{
1060 struct xgbe_channel *channel;
1061 unsigned int i;
1062
1063 devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1064
e78332b2
LT		 1065 if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
1066 devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
1067
c30e76a7
LT		 1068 if (!pdata->per_channel_irq)
1069 return;
1070
18f9f0ac
LT		 1071 for (i = 0; i < pdata->channel_count; i++) {
1072 channel = pdata->channel[i];
f00ba49d
LT		 1073
1074 irq_set_affinity_hint(channel->dma_irq, NULL);
c30e76a7 1075 devm_free_irq(pdata->dev, channel->dma_irq, channel);
18f9f0ac 1076 }
c30e76a7
LT		 1077}
1078
c5aa9e3b
LT		 1079void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
1080{
1081 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1082
1083 DBGPR("-->xgbe_init_tx_coalesce\n");
1084
1085 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
1086 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
1087
1088 hw_if->config_tx_coalesce(pdata);
1089
1090 DBGPR("<--xgbe_init_tx_coalesce\n");
1091}
1092
1093void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
1094{
1095 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1096
1097 DBGPR("-->xgbe_init_rx_coalesce\n");
1098
1099 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
4a57ebcc 1100 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
c5aa9e3b
LT		 1101 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
1102
1103 hw_if->config_rx_coalesce(pdata);
1104
1105 DBGPR("<--xgbe_init_rx_coalesce\n");
1106}
1107
08dcc47c 1108static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
c5aa9e3b
LT		 1109{
1110 struct xgbe_desc_if *desc_if = &pdata->desc_if;
c5aa9e3b
LT		 1111 struct xgbe_ring *ring;
1112 struct xgbe_ring_data *rdata;
1113 unsigned int i, j;
1114
08dcc47c 1115 DBGPR("-->xgbe_free_tx_data\n");
c5aa9e3b 1116
18f9f0ac
LT		 1117 for (i = 0; i < pdata->channel_count; i++) {
1118 ring = pdata->channel[i]->tx_ring;
c5aa9e3b
LT		 1119 if (!ring)
1120 break;
1121
1122 for (j = 0; j < ring->rdesc_count; j++) {
d0a8ba6c 1123 rdata = XGBE_GET_DESC_DATA(ring, j);
08dcc47c 1124 desc_if->unmap_rdata(pdata, rdata);
c5aa9e3b
LT		 1125 }
1126 }
1127
08dcc47c 1128 DBGPR("<--xgbe_free_tx_data\n");
c5aa9e3b
LT		 1129}
1130
08dcc47c 1131static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
c5aa9e3b
LT		 1132{
1133 struct xgbe_desc_if *desc_if = &pdata->desc_if;
c5aa9e3b
LT		 1134 struct xgbe_ring *ring;
1135 struct xgbe_ring_data *rdata;
1136 unsigned int i, j;
1137
08dcc47c 1138 DBGPR("-->xgbe_free_rx_data\n");
c5aa9e3b 1139
18f9f0ac
LT		 1140 for (i = 0; i < pdata->channel_count; i++) {
1141 ring = pdata->channel[i]->rx_ring;
c5aa9e3b
LT		 1142 if (!ring)
1143 break;
1144
1145 for (j = 0; j < ring->rdesc_count; j++) {
d0a8ba6c 1146 rdata = XGBE_GET_DESC_DATA(ring, j);
08dcc47c 1147 desc_if->unmap_rdata(pdata, rdata);
c5aa9e3b
LT		 1148 }
1149 }
1150
08dcc47c 1151 DBGPR("<--xgbe_free_rx_data\n");
c5aa9e3b
LT		 1152}
1153
e57f7a3f 1154static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
88131a81 1155{
88131a81
LT		 1156 pdata->phy_link = -1;
1157 pdata->phy_speed = SPEED_UNKNOWN;
88131a81 1158
7c12aa08 1159 return pdata->phy_if.phy_reset(pdata);
88131a81
LT		 1160}
1161
c5aa9e3b
LT		 1162int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
1163{
1164 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1165 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1166 unsigned long flags;
1167
1168 DBGPR("-->xgbe_powerdown\n");
1169
1170 if (!netif_running(netdev) ||
1171 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
1172 netdev_alert(netdev, "Device is already powered down\n");
1173 DBGPR("<--xgbe_powerdown\n");
1174 return -EINVAL;
1175 }
1176
c5aa9e3b
LT		 1177 spin_lock_irqsave(&pdata->lock, flags);
1178
1179 if (caller == XGMAC_DRIVER_CONTEXT)
1180 netif_device_detach(netdev);
1181
1182 netif_tx_stop_all_queues(netdev);
c5aa9e3b 1183
7c12aa08
LT		 1184 xgbe_stop_timers(pdata);
1185 flush_workqueue(pdata->dev_workqueue);
1186
c5aa9e3b
LT		 1187 hw_if->powerdown_tx(pdata);
1188 hw_if->powerdown_rx(pdata);
1189
c30e76a7
LT		 1190 xgbe_napi_disable(pdata, 0);
1191
c5aa9e3b
LT		 1192 pdata->power_down = 1;
1193
1194 spin_unlock_irqrestore(&pdata->lock, flags);
1195
1196 DBGPR("<--xgbe_powerdown\n");
1197
1198 return 0;
1199}
1200
1201int xgbe_powerup(struct net_device *netdev, unsigned int caller)
1202{
1203 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1204 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1205 unsigned long flags;
1206
1207 DBGPR("-->xgbe_powerup\n");
1208
1209 if (!netif_running(netdev) ||
1210 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
1211 netdev_alert(netdev, "Device is already powered up\n");
1212 DBGPR("<--xgbe_powerup\n");
1213 return -EINVAL;
1214 }
1215
1216 spin_lock_irqsave(&pdata->lock, flags);
1217
1218 pdata->power_down = 0;
1219
c30e76a7
LT		 1220 xgbe_napi_enable(pdata, 0);
1221
c5aa9e3b
LT		 1222 hw_if->powerup_tx(pdata);
1223 hw_if->powerup_rx(pdata);
1224
1225 if (caller == XGMAC_DRIVER_CONTEXT)
1226 netif_device_attach(netdev);
1227
c5aa9e3b
LT		 1228 netif_tx_start_all_queues(netdev);
1229
7c12aa08
LT		 1230 xgbe_start_timers(pdata);
1231
c5aa9e3b
LT		 1232 spin_unlock_irqrestore(&pdata->lock, flags);
1233
1234 DBGPR("<--xgbe_powerup\n");
1235
1236 return 0;
1237}
1238
22447534
TL		 1239static void xgbe_free_memory(struct xgbe_prv_data *pdata)
1240{
1241 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1242
1243 /* Free the ring descriptors and buffers */
1244 desc_if->free_ring_resources(pdata);
1245
1246 /* Free the channel and ring structures */
1247 xgbe_free_channels(pdata);
1248}
1249
1250static int xgbe_alloc_memory(struct xgbe_prv_data *pdata)
1251{
1252 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1253 struct net_device *netdev = pdata->netdev;
1254 int ret;
1255
01b5277f
TL		 1256 if (pdata->new_tx_ring_count) {
1257 pdata->tx_ring_count = pdata->new_tx_ring_count;
1258 pdata->tx_q_count = pdata->tx_ring_count;
1259 pdata->new_tx_ring_count = 0;
1260 }
1261
1262 if (pdata->new_rx_ring_count) {
1263 pdata->rx_ring_count = pdata->new_rx_ring_count;
1264 pdata->new_rx_ring_count = 0;
1265 }
1266
22447534
TL		 1267 /* Calculate the Rx buffer size before allocating rings */
1268 pdata->rx_buf_size = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1269
1270 /* Allocate the channel and ring structures */
1271 ret = xgbe_alloc_channels(pdata);
1272 if (ret)
1273 return ret;
1274
1275 /* Allocate the ring descriptors and buffers */
1276 ret = desc_if->alloc_ring_resources(pdata);
1277 if (ret)
1278 goto err_channels;
1279
1280 /* Initialize the service and Tx timers */
1281 xgbe_init_timers(pdata);
1282
1283 return 0;
1284
1285err_channels:
1286 xgbe_free_memory(pdata);
1287
1288 return ret;
1289}
1290
c5aa9e3b
LT		 1291static int xgbe_start(struct xgbe_prv_data *pdata)
1292{
1293 struct xgbe_hw_if *hw_if = &pdata->hw_if;
7c12aa08 1294 struct xgbe_phy_if *phy_if = &pdata->phy_if;
c5aa9e3b 1295 struct net_device *netdev = pdata->netdev;
22447534 1296 unsigned int i;
c30e76a7 1297 int ret;
c5aa9e3b 1298
22447534
TL		 1299 /* Set the number of queues */
1300 ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
1301 if (ret) {
1302 netdev_err(netdev, "error setting real tx queue count\n");
1303 return ret;
1304 }
1305
1306 ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
1307 if (ret) {
1308 netdev_err(netdev, "error setting real rx queue count\n");
1309 return ret;
1310 }
1311
1312 /* Set RSS lookup table data for programming */
1313 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1314 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1315 i % pdata->rx_ring_count);
c5aa9e3b 1316
738f7f64
LT		 1317 ret = hw_if->init(pdata);
1318 if (ret)
1319 return ret;
c5aa9e3b 1320
c30e76a7
LT		 1321 xgbe_napi_enable(pdata, 1);
1322
1323 ret = xgbe_request_irqs(pdata);
1324 if (ret)
1325 goto err_napi;
1326
47f164de
LT		 1327 ret = phy_if->phy_start(pdata);
1328 if (ret)
1329 goto err_irqs;
1330
c5aa9e3b
LT		 1331 hw_if->enable_tx(pdata);
1332 hw_if->enable_rx(pdata);
1333
4df587ab 1334 udp_tunnel_nic_reset_ntf(netdev);
1a510ccf 1335
c5aa9e3b
LT		 1336 netif_tx_start_all_queues(netdev);
1337
7c12aa08 1338 xgbe_start_timers(pdata);
afb43e8a 1339 queue_work(pdata->dev_workqueue, &pdata->service_work);
7c12aa08 1340
e78332b2
LT		 1341 clear_bit(XGBE_STOPPED, &pdata->dev_state);
1342
c5aa9e3b 1343 return 0;
c30e76a7 1344
47f164de
LT		 1345err_irqs:
1346 xgbe_free_irqs(pdata);
1347
c30e76a7
LT		 1348err_napi:
1349 xgbe_napi_disable(pdata, 1);
1350
c30e76a7
LT		 1351 hw_if->exit(pdata);
1352
1353 return ret;
c5aa9e3b
LT		 1354}
1355
1356static void xgbe_stop(struct xgbe_prv_data *pdata)
1357{
1358 struct xgbe_hw_if *hw_if = &pdata->hw_if;
7c12aa08 1359 struct xgbe_phy_if *phy_if = &pdata->phy_if;
5fb4b86a 1360 struct xgbe_channel *channel;
c5aa9e3b 1361 struct net_device *netdev = pdata->netdev;
5fb4b86a
LT		 1362 struct netdev_queue *txq;
1363 unsigned int i;
c5aa9e3b
LT		 1364
1365 DBGPR("-->xgbe_stop\n");
1366
e78332b2
LT		 1367 if (test_bit(XGBE_STOPPED, &pdata->dev_state))
1368 return;
1369
c5aa9e3b 1370 netif_tx_stop_all_queues(netdev);
186edbb5 1371 netif_carrier_off(pdata->netdev);
c5aa9e3b 1372
7c12aa08
LT		 1373 xgbe_stop_timers(pdata);
1374 flush_workqueue(pdata->dev_workqueue);
c5aa9e3b 1375
4df587ab 1376 xgbe_vxlan_unset_port(netdev, 0, 0, NULL);
1a510ccf 1377
c5aa9e3b
LT		 1378 hw_if->disable_tx(pdata);
1379 hw_if->disable_rx(pdata);
1380
402168b4
LT		 1381 phy_if->phy_stop(pdata);
1382
c30e76a7
LT		 1383 xgbe_free_irqs(pdata);
1384
1385 xgbe_napi_disable(pdata, 1);
1386
c30e76a7
LT		 1387 hw_if->exit(pdata);
1388
18f9f0ac
LT		 1389 for (i = 0; i < pdata->channel_count; i++) {
1390 channel = pdata->channel[i];
5fb4b86a
LT		 1391 if (!channel->tx_ring)
1392 continue;
1393
1394 txq = netdev_get_tx_queue(netdev, channel->queue_index);
1395 netdev_tx_reset_queue(txq);
1396 }
1397
e78332b2
LT		 1398 set_bit(XGBE_STOPPED, &pdata->dev_state);
1399
c5aa9e3b
LT		 1400 DBGPR("<--xgbe_stop\n");
1401}
1402
e78332b2
LT		 1403static void xgbe_stopdev(struct work_struct *work)
1404{
1405 struct xgbe_prv_data *pdata = container_of(work,
1406 struct xgbe_prv_data,
1407 stopdev_work);
1408
1409 rtnl_lock();
1410
1411 xgbe_stop(pdata);
1412
1413 xgbe_free_tx_data(pdata);
1414 xgbe_free_rx_data(pdata);
1415
1416 rtnl_unlock();
1417
1418 netdev_alert(pdata->netdev, "device stopped\n");
1419}
1420
01b5277f
TL		 1421void xgbe_full_restart_dev(struct xgbe_prv_data *pdata)
1422{
1423 /* If not running, "restart" will happen on open */
1424 if (!netif_running(pdata->netdev))
1425 return;
1426
1427 xgbe_stop(pdata);
1428
1429 xgbe_free_memory(pdata);
1430 xgbe_alloc_memory(pdata);
1431
1432 xgbe_start(pdata);
1433}
1434
bab748de 1435void xgbe_restart_dev(struct xgbe_prv_data *pdata)
c5aa9e3b 1436{
c5aa9e3b
LT		 1437 /* If not running, "restart" will happen on open */
1438 if (!netif_running(pdata->netdev))
1439 return;
1440
1441 xgbe_stop(pdata);
c5aa9e3b 1442
08dcc47c
LT		 1443 xgbe_free_tx_data(pdata);
1444 xgbe_free_rx_data(pdata);
c5aa9e3b 1445
c5aa9e3b 1446 xgbe_start(pdata);
c5aa9e3b
LT		 1447}
1448
1449static void xgbe_restart(struct work_struct *work)
1450{
1451 struct xgbe_prv_data *pdata = container_of(work,
1452 struct xgbe_prv_data,
1453 restart_work);
1454
1455 rtnl_lock();
1456
916102c6 1457 xgbe_restart_dev(pdata);
c5aa9e3b
LT		 1458
1459 rtnl_unlock();
1460}
1461
23e4eef7
LT		 1462static void xgbe_tx_tstamp(struct work_struct *work)
1463{
1464 struct xgbe_prv_data *pdata = container_of(work,
1465 struct xgbe_prv_data,
1466 tx_tstamp_work);
1467 struct skb_shared_hwtstamps hwtstamps;
1468 u64 nsec;
1469 unsigned long flags;
1470
93845d5f
LT		 1471 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1472 if (!pdata->tx_tstamp_skb)
1473 goto unlock;
1474
23e4eef7
LT		 1475 if (pdata->tx_tstamp) {
1476 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1477 pdata->tx_tstamp);
1478
1479 memset(&hwtstamps, 0, sizeof(hwtstamps));
1480 hwtstamps.hwtstamp = ns_to_ktime(nsec);
1481 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1482 }
1483
1484 dev_kfree_skb_any(pdata->tx_tstamp_skb);
1485
23e4eef7 1486 pdata->tx_tstamp_skb = NULL;
93845d5f
LT		 1487
1488unlock:
23e4eef7
LT		 1489 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1490}
1491
1492static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1493 struct ifreq *ifreq)
1494{
1495 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1496 sizeof(pdata->tstamp_config)))
1497 return -EFAULT;
1498
1499 return 0;
1500}
1501
1502static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1503 struct ifreq *ifreq)
1504{
1505 struct hwtstamp_config config;
1506 unsigned int mac_tscr;
1507
1508 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1509 return -EFAULT;
1510
1511 if (config.flags)
1512 return -EINVAL;
1513
1514 mac_tscr = 0;
1515
1516 switch (config.tx_type) {
1517 case HWTSTAMP_TX_OFF:
1518 break;
1519
1520 case HWTSTAMP_TX_ON:
1521 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1522 break;
1523
1524 default:
1525 return -ERANGE;
1526 }
1527
1528 switch (config.rx_filter) {
1529 case HWTSTAMP_FILTER_NONE:
1530 break;
1531
e3412575 1532 case HWTSTAMP_FILTER_NTP_ALL:
23e4eef7
LT		 1533 case HWTSTAMP_FILTER_ALL:
1534 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1535 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1536 break;
1537
1538 /* PTP v2, UDP, any kind of event packet */
1539 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1540 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
df561f66 1541 fallthrough; /* to PTP v1, UDP, any kind of event packet */
23e4eef7
LT		 1542 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1543 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1544 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1545 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1546 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1547 break;
1548
1549 /* PTP v2, UDP, Sync packet */
1550 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1551 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
df561f66 1552 fallthrough; /* to PTP v1, UDP, Sync packet */
23e4eef7
LT		 1553 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1554 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1555 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1556 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1557 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1558 break;
1559
1560 /* PTP v2, UDP, Delay_req packet */
1561 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1562 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
df561f66 1563 fallthrough; /* to PTP v1, UDP, Delay_req packet */
23e4eef7
LT		 1564 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1565 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1566 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1567 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1568 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1569 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1570 break;
1571
1572 /* 802.AS1, Ethernet, any kind of event packet */
1573 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1574 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1575 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1576 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1577 break;
1578
1579 /* 802.AS1, Ethernet, Sync packet */
1580 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1581 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1582 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1583 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1584 break;
1585
1586 /* 802.AS1, Ethernet, Delay_req packet */
1587 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1588 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1589 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1590 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1591 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1592 break;
1593
1594 /* PTP v2/802.AS1, any layer, any kind of event packet */
1595 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1596 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1597 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1598 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1599 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1600 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1601 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1602 break;
1603
1604 /* PTP v2/802.AS1, any layer, Sync packet */
1605 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1606 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1607 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1608 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1609 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1610 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1611 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1612 break;
1613
1614 /* PTP v2/802.AS1, any layer, Delay_req packet */
1615 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1616 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1617 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1618 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1619 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1620 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1621 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1622 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1623 break;
1624
1625 default:
1626 return -ERANGE;
1627 }
1628
1629 pdata->hw_if.config_tstamp(pdata, mac_tscr);
1630
1631 memcpy(&pdata->tstamp_config, &config, sizeof(config));
1632
1633 return 0;
1634}
1635
1636static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1637 struct sk_buff *skb,
1638 struct xgbe_packet_data *packet)
1639{
1640 unsigned long flags;
1641
1642 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1643 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1644 if (pdata->tx_tstamp_skb) {
1645 /* Another timestamp in progress, ignore this one */
1646 XGMAC_SET_BITS(packet->attributes,
1647 TX_PACKET_ATTRIBUTES, PTP, 0);
1648 } else {
1649 pdata->tx_tstamp_skb = skb_get(skb);
1650 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1651 }
1652 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1653 }
1654
74abc9b1 1655 skb_tx_timestamp(skb);
23e4eef7
LT		 1656}
1657
c5aa9e3b
LT		 1658static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1659{
df8a39de
JP		 1660 if (skb_vlan_tag_present(skb))
1661 packet->vlan_ctag = skb_vlan_tag_get(skb);
c5aa9e3b
LT		 1662}
1663
1664static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1665{
1666 int ret;
1667
1668 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1669 TSO_ENABLE))
1670 return 0;
1671
1672 ret = skb_cow_head(skb, 0);
1673 if (ret)
1674 return ret;
1675
1a510ccf
LT		 1676 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, VXLAN)) {
1677 packet->header_len = skb_inner_transport_offset(skb) +
1678 inner_tcp_hdrlen(skb);
1679 packet->tcp_header_len = inner_tcp_hdrlen(skb);
1680 } else {
1681 packet->header_len = skb_transport_offset(skb) +
1682 tcp_hdrlen(skb);
1683 packet->tcp_header_len = tcp_hdrlen(skb);
1684 }
c5aa9e3b
LT		 1685 packet->tcp_payload_len = skb->len - packet->header_len;
1686 packet->mss = skb_shinfo(skb)->gso_size;
1a510ccf 1687
c5aa9e3b
LT		 1688 DBGPR(" packet->header_len=%u\n", packet->header_len);
1689 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1690 packet->tcp_header_len, packet->tcp_payload_len);
1691 DBGPR(" packet->mss=%u\n", packet->mss);
1692
5fb4b86a
LT		 1693 /* Update the number of packets that will ultimately be transmitted
1694 * along with the extra bytes for each extra packet
1695 */
1696 packet->tx_packets = skb_shinfo(skb)->gso_segs;
1697 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
1698
c5aa9e3b
LT		 1699 return 0;
1700}
1701
b5c5f8d0 1702static bool xgbe_is_vxlan(struct sk_buff *skb)
1a510ccf 1703{
1a510ccf
LT		 1704 if (!skb->encapsulation)
1705 return false;
1706
1707 if (skb->ip_summed != CHECKSUM_PARTIAL)
1708 return false;
1709
1710 switch (skb->protocol) {
1711 case htons(ETH_P_IP):
1712 if (ip_hdr(skb)->protocol != IPPROTO_UDP)
1713 return false;
1714 break;
1715
1716 case htons(ETH_P_IPV6):
1717 if (ipv6_hdr(skb)->nexthdr != IPPROTO_UDP)
1718 return false;
1719 break;
1720
1721 default:
1722 return false;
1723 }
1724
b5c5f8d0
JK		 1725 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1726 skb->inner_protocol != htons(ETH_P_TEB) ||
1727 (skb_inner_mac_header(skb) - skb_transport_header(skb) !=
1728 sizeof(struct udphdr) + sizeof(struct vxlanhdr)))
1729 return false;
1a510ccf 1730
b5c5f8d0 1731 return true;
1a510ccf
LT		 1732}
1733
c5aa9e3b
LT		 1734static int xgbe_is_tso(struct sk_buff *skb)
1735{
1736 if (skb->ip_summed != CHECKSUM_PARTIAL)
1737 return 0;
1738
1739 if (!skb_is_gso(skb))
1740 return 0;
1741
1742 DBGPR(" TSO packet to be processed\n");
1743
1744 return 1;
1745}
1746
23e4eef7
LT		 1747static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1748 struct xgbe_ring *ring, struct sk_buff *skb,
c5aa9e3b
LT		 1749 struct xgbe_packet_data *packet)
1750{
d7840976 1751 skb_frag_t *frag;
c5aa9e3b
LT		 1752 unsigned int context_desc;
1753 unsigned int len;
1754 unsigned int i;
1755
16958a2b
LT		 1756 packet->skb = skb;
1757
c5aa9e3b
LT		 1758 context_desc = 0;
1759 packet->rdesc_count = 0;
1760
5fb4b86a
LT		 1761 packet->tx_packets = 1;
1762 packet->tx_bytes = skb->len;
1763
c5aa9e3b 1764 if (xgbe_is_tso(skb)) {
a7beaf23 1765 /* TSO requires an extra descriptor if mss is different */
c5aa9e3b
LT		 1766 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1767 context_desc = 1;
1768 packet->rdesc_count++;
1769 }
1770
a7beaf23 1771 /* TSO requires an extra descriptor for TSO header */
c5aa9e3b
LT		 1772 packet->rdesc_count++;
1773
1774 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1775 TSO_ENABLE, 1);
1776 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1777 CSUM_ENABLE, 1);
1778 } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1779 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1780 CSUM_ENABLE, 1);
1781
b5c5f8d0 1782 if (xgbe_is_vxlan(skb))
1a510ccf
LT		 1783 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1784 VXLAN, 1);
1785
df8a39de 1786 if (skb_vlan_tag_present(skb)) {
c5aa9e3b 1787 /* VLAN requires an extra descriptor if tag is different */
df8a39de 1788 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
c5aa9e3b
LT		 1789 /* We can share with the TSO context descriptor */
1790 if (!context_desc) {
1791 context_desc = 1;
1792 packet->rdesc_count++;
1793 }
1794
1795 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1796 VLAN_CTAG, 1);
1797 }
1798
23e4eef7
LT		 1799 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1800 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1801 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1802 PTP, 1);
1803
c5aa9e3b
LT		 1804 for (len = skb_headlen(skb); len;) {
1805 packet->rdesc_count++;
d0a8ba6c 1806 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
c5aa9e3b
LT		 1807 }
1808
1809 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1810 frag = &skb_shinfo(skb)->frags[i];
1811 for (len = skb_frag_size(frag); len; ) {
1812 packet->rdesc_count++;
d0a8ba6c 1813 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
c5aa9e3b
LT		 1814 }
1815 }
1816}
1817
1818static int xgbe_open(struct net_device *netdev)
1819{
1820 struct xgbe_prv_data *pdata = netdev_priv(netdev);
c5aa9e3b
LT		 1821 int ret;
1822
efbaa828
LT		 1823 /* Create the various names based on netdev name */
1824 snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
1825 netdev_name(netdev));
1826
1827 snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
1828 netdev_name(netdev));
1829
1830 snprintf(pdata->i2c_name, sizeof(pdata->i2c_name) - 1, "%s-i2c",
1831 netdev_name(netdev));
1832
1833 /* Create workqueues */
1834 pdata->dev_workqueue =
1835 create_singlethread_workqueue(netdev_name(netdev));
1836 if (!pdata->dev_workqueue) {
1837 netdev_err(netdev, "device workqueue creation failed\n");
1838 return -ENOMEM;
1839 }
1840
1841 pdata->an_workqueue =
1842 create_singlethread_workqueue(pdata->an_name);
1843 if (!pdata->an_workqueue) {
1844 netdev_err(netdev, "phy workqueue creation failed\n");
1845 ret = -ENOMEM;
1846 goto err_dev_wq;
1847 }
1848
e57f7a3f
LT		 1849 /* Reset the phy settings */
1850 ret = xgbe_phy_reset(pdata);
88131a81 1851 if (ret)
efbaa828 1852 goto err_an_wq;
88131a81 1853
23e4eef7
LT		 1854 /* Enable the clocks */
1855 ret = clk_prepare_enable(pdata->sysclk);
c5aa9e3b 1856 if (ret) {
23e4eef7 1857 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
efbaa828 1858 goto err_an_wq;
c5aa9e3b
LT		 1859 }
1860
23e4eef7
LT		 1861 ret = clk_prepare_enable(pdata->ptpclk);
1862 if (ret) {
1863 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1864 goto err_sysclk;
1865 }
1866
7c12aa08 1867 INIT_WORK(&pdata->service_work, xgbe_service);
c5aa9e3b 1868 INIT_WORK(&pdata->restart_work, xgbe_restart);
e78332b2 1869 INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
23e4eef7 1870 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
22447534
TL		 1871
1872 ret = xgbe_alloc_memory(pdata);
1873 if (ret)
1874 goto err_ptpclk;
c5aa9e3b 1875
c5aa9e3b
LT		 1876 ret = xgbe_start(pdata);
1877 if (ret)
22447534 1878 goto err_mem;
c5aa9e3b 1879
7c12aa08
LT		 1880 clear_bit(XGBE_DOWN, &pdata->dev_state);
1881
c5aa9e3b
LT		 1882 return 0;
1883
22447534
TL		 1884err_mem:
1885 xgbe_free_memory(pdata);
4780b7ca 1886
23e4eef7
LT		 1887err_ptpclk:
1888 clk_disable_unprepare(pdata->ptpclk);
1889
1890err_sysclk:
1891 clk_disable_unprepare(pdata->sysclk);
c5aa9e3b 1892
efbaa828
LT		 1893err_an_wq:
1894 destroy_workqueue(pdata->an_workqueue);
1895
1896err_dev_wq:
1897 destroy_workqueue(pdata->dev_workqueue);
1898
c5aa9e3b
LT		 1899 return ret;
1900}
1901
1902static int xgbe_close(struct net_device *netdev)
1903{
1904 struct xgbe_prv_data *pdata = netdev_priv(netdev);
c5aa9e3b
LT		 1905
1906 /* Stop the device */
1907 xgbe_stop(pdata);
1908
22447534 1909 xgbe_free_memory(pdata);
e98c72c9 1910
23e4eef7
LT		 1911 /* Disable the clocks */
1912 clk_disable_unprepare(pdata->ptpclk);
1913 clk_disable_unprepare(pdata->sysclk);
c5aa9e3b 1914
efbaa828
LT		 1915 flush_workqueue(pdata->an_workqueue);
1916 destroy_workqueue(pdata->an_workqueue);
1917
1918 flush_workqueue(pdata->dev_workqueue);
1919 destroy_workqueue(pdata->dev_workqueue);
1920
7c12aa08 1921 set_bit(XGBE_DOWN, &pdata->dev_state);
88131a81 1922
c5aa9e3b
LT		 1923 return 0;
1924}
1925
fe72352e 1926static netdev_tx_t xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
c5aa9e3b
LT		 1927{
1928 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1929 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1930 struct xgbe_desc_if *desc_if = &pdata->desc_if;
1931 struct xgbe_channel *channel;
1932 struct xgbe_ring *ring;
1933 struct xgbe_packet_data *packet;
5fb4b86a 1934 struct netdev_queue *txq;
fe72352e 1935 netdev_tx_t ret;
c5aa9e3b
LT		 1936
1937 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1938
18f9f0ac 1939 channel = pdata->channel[skb->queue_mapping];
5fb4b86a 1940 txq = netdev_get_tx_queue(netdev, channel->queue_index);
c5aa9e3b
LT		 1941 ring = channel->tx_ring;
1942 packet = &ring->packet_data;
1943
1944 ret = NETDEV_TX_OK;
1945
c5aa9e3b 1946 if (skb->len == 0) {
34bf65df
LT		 1947 netif_err(pdata, tx_err, netdev,
1948 "empty skb received from stack\n");
c5aa9e3b
LT		 1949 dev_kfree_skb_any(skb);
1950 goto tx_netdev_return;
1951 }
1952
1953 /* Calculate preliminary packet info */
1954 memset(packet, 0, sizeof(*packet));
23e4eef7 1955 xgbe_packet_info(pdata, ring, skb, packet);
c5aa9e3b
LT		 1956
1957 /* Check that there are enough descriptors available */
16958a2b
LT		 1958 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
1959 if (ret)
c5aa9e3b 1960 goto tx_netdev_return;
c5aa9e3b
LT		 1961
1962 ret = xgbe_prep_tso(skb, packet);
1963 if (ret) {
34bf65df
LT		 1964 netif_err(pdata, tx_err, netdev,
1965 "error processing TSO packet\n");
c5aa9e3b
LT		 1966 dev_kfree_skb_any(skb);
1967 goto tx_netdev_return;
1968 }
1969 xgbe_prep_vlan(skb, packet);
1970
1971 if (!desc_if->map_tx_skb(channel, skb)) {
1972 dev_kfree_skb_any(skb);
1973 goto tx_netdev_return;
1974 }
1975
23e4eef7
LT		 1976 xgbe_prep_tx_tstamp(pdata, skb, packet);
1977
5fb4b86a
LT		 1978 /* Report on the actual number of bytes (to be) sent */
1979 netdev_tx_sent_queue(txq, packet->tx_bytes);
1980
c5aa9e3b 1981 /* Configure required descriptor fields for transmission */
a9d41981 1982 hw_if->dev_xmit(channel);
c5aa9e3b 1983
34bf65df
LT		 1984 if (netif_msg_pktdata(pdata))
1985 xgbe_print_pkt(netdev, skb, true);
c5aa9e3b 1986
16958a2b
LT		 1987 /* Stop the queue in advance if there may not be enough descriptors */
1988 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
1989
1990 ret = NETDEV_TX_OK;
1991
c5aa9e3b 1992tx_netdev_return:
c5aa9e3b
LT		 1993 return ret;
1994}
1995
1996static void xgbe_set_rx_mode(struct net_device *netdev)
1997{
1998 struct xgbe_prv_data *pdata = netdev_priv(netdev);
1999 struct xgbe_hw_if *hw_if = &pdata->hw_if;
c5aa9e3b
LT		 2000
2001 DBGPR("-->xgbe_set_rx_mode\n");
2002
b876382b 2003 hw_if->config_rx_mode(pdata);
c5aa9e3b
LT		 2004
2005 DBGPR("<--xgbe_set_rx_mode\n");
2006}
2007
2008static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
2009{
2010 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2011 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2012 struct sockaddr *saddr = addr;
2013
2014 DBGPR("-->xgbe_set_mac_address\n");
2015
2016 if (!is_valid_ether_addr(saddr->sa_data))
2017 return -EADDRNOTAVAIL;
2018
a05e4c0a 2019 eth_hw_addr_set(netdev, saddr->sa_data);
c5aa9e3b
LT		 2020
2021 hw_if->set_mac_address(pdata, netdev->dev_addr);
2022
2023 DBGPR("<--xgbe_set_mac_address\n");
2024
2025 return 0;
2026}
2027
23e4eef7
LT		 2028static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
2029{
2030 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2031 int ret;
2032
2033 switch (cmd) {
2034 case SIOCGHWTSTAMP:
2035 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
2036 break;
2037
2038 case SIOCSHWTSTAMP:
2039 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
2040 break;
2041
2042 default:
2043 ret = -EOPNOTSUPP;
2044 }
2045
2046 return ret;
2047}
2048
c5aa9e3b
LT		 2049static int xgbe_change_mtu(struct net_device *netdev, int mtu)
2050{
2051 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2052 int ret;
2053
2054 DBGPR("-->xgbe_change_mtu\n");
2055
2056 ret = xgbe_calc_rx_buf_size(netdev, mtu);
2057 if (ret < 0)
2058 return ret;
2059
2060 pdata->rx_buf_size = ret;
2061 netdev->mtu = mtu;
2062
916102c6 2063 xgbe_restart_dev(pdata);
c5aa9e3b
LT		 2064
2065 DBGPR("<--xgbe_change_mtu\n");
2066
2067 return 0;
2068}
2069
0290bd29 2070static void xgbe_tx_timeout(struct net_device *netdev, unsigned int txqueue)
a8373f1a
LT		 2071{
2072 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2073
2074 netdev_warn(netdev, "tx timeout, device restarting\n");
96aec911 2075 schedule_work(&pdata->restart_work);
a8373f1a
LT		 2076}
2077
bc1f4470 2078static void xgbe_get_stats64(struct net_device *netdev,
2079 struct rtnl_link_stats64 *s)
c5aa9e3b
LT		 2080{
2081 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2082 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2083
2084 DBGPR("-->%s\n", __func__);
2085
2086 pdata->hw_if.read_mmc_stats(pdata);
2087
2088 s->rx_packets = pstats->rxframecount_gb;
2089 s->rx_bytes = pstats->rxoctetcount_gb;
2090 s->rx_errors = pstats->rxframecount_gb -
2091 pstats->rxbroadcastframes_g -
2092 pstats->rxmulticastframes_g -
2093 pstats->rxunicastframes_g;
2094 s->multicast = pstats->rxmulticastframes_g;
2095 s->rx_length_errors = pstats->rxlengtherror;
2096 s->rx_crc_errors = pstats->rxcrcerror;
2097 s->rx_fifo_errors = pstats->rxfifooverflow;
2098
2099 s->tx_packets = pstats->txframecount_gb;
2100 s->tx_bytes = pstats->txoctetcount_gb;
2101 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
2102 s->tx_dropped = netdev->stats.tx_dropped;
2103
2104 DBGPR("<--%s\n", __func__);
c5aa9e3b
LT		 2105}
2106
801c62d9
LT		 2107static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
2108 u16 vid)
2109{
2110 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2111 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2112
2113 DBGPR("-->%s\n", __func__);
2114
2115 set_bit(vid, pdata->active_vlans);
2116 hw_if->update_vlan_hash_table(pdata);
2117
2118 DBGPR("<--%s\n", __func__);
2119
2120 return 0;
2121}
2122
2123static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
2124 u16 vid)
2125{
2126 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2127 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2128
2129 DBGPR("-->%s\n", __func__);
2130
2131 clear_bit(vid, pdata->active_vlans);
2132 hw_if->update_vlan_hash_table(pdata);
2133
2134 DBGPR("<--%s\n", __func__);
2135
2136 return 0;
2137}
2138
c5aa9e3b
LT		 2139#ifdef CONFIG_NET_POLL_CONTROLLER
2140static void xgbe_poll_controller(struct net_device *netdev)
2141{
2142 struct xgbe_prv_data *pdata = netdev_priv(netdev);
9227dc5e
LT		 2143 struct xgbe_channel *channel;
2144 unsigned int i;
c5aa9e3b
LT		 2145
2146 DBGPR("-->xgbe_poll_controller\n");
2147
9227dc5e 2148 if (pdata->per_channel_irq) {
18f9f0ac
LT		 2149 for (i = 0; i < pdata->channel_count; i++) {
2150 channel = pdata->channel[i];
9227dc5e 2151 xgbe_dma_isr(channel->dma_irq, channel);
18f9f0ac 2152 }
9227dc5e
LT		 2153 } else {
2154 disable_irq(pdata->dev_irq);
2155 xgbe_isr(pdata->dev_irq, pdata);
2156 enable_irq(pdata->dev_irq);
2157 }
c5aa9e3b
LT		 2158
2159 DBGPR("<--xgbe_poll_controller\n");
2160}
2161#endif /* End CONFIG_NET_POLL_CONTROLLER */
2162
2572ac53 2163static int xgbe_setup_tc(struct net_device *netdev, enum tc_setup_type type,
de4784ca 2164 void *type_data)
fca2d994
LT		 2165{
2166 struct xgbe_prv_data *pdata = netdev_priv(netdev);
de4784ca 2167 struct tc_mqprio_qopt *mqprio = type_data;
b3b71597 2168 u8 tc;
fca2d994 2169
575ed7d3 2170 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 2171 return -EOPNOTSUPP;
e4c6734e 2172
de4784ca
JP		 2173 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2174 tc = mqprio->num_tc;
16e5cc64 2175
b3b71597 2176 if (tc > pdata->hw_feat.tc_cnt)
fca2d994
LT		 2177 return -EINVAL;
2178
b3b71597
LT		 2179 pdata->num_tcs = tc;
2180 pdata->hw_if.config_tc(pdata);
fca2d994
LT		 2181
2182 return 0;
2183}
2184
1a510ccf
LT		 2185static netdev_features_t xgbe_fix_features(struct net_device *netdev,
2186 netdev_features_t features)
2187{
2188 struct xgbe_prv_data *pdata = netdev_priv(netdev);
4df587ab 2189 netdev_features_t vxlan_base;
1a510ccf
LT		 2190
2191 vxlan_base = NETIF_F_GSO_UDP_TUNNEL | NETIF_F_RX_UDP_TUNNEL_PORT;
1a510ccf 2192
1a510ccf 2193 if (!pdata->hw_feat.vxn)
4df587ab 2194 return features;
1a510ccf
LT		 2195
2196 /* VXLAN CSUM requires VXLAN base */
2197 if ((features & NETIF_F_GSO_UDP_TUNNEL_CSUM) &&
2198 !(features & NETIF_F_GSO_UDP_TUNNEL)) {
2199 netdev_notice(netdev,
2200 "forcing tx udp tunnel support\n");
2201 features |= NETIF_F_GSO_UDP_TUNNEL;
2202 }
2203
2204 /* Can't do one without doing the other */
2205 if ((features & vxlan_base) != vxlan_base) {
2206 netdev_notice(netdev,
2207 "forcing both tx and rx udp tunnel support\n");
2208 features |= vxlan_base;
2209 }
2210
2211 if (features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
2212 if (!(features & NETIF_F_GSO_UDP_TUNNEL_CSUM)) {
2213 netdev_notice(netdev,
2214 "forcing tx udp tunnel checksumming on\n");
2215 features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
2216 }
2217 } else {
2218 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) {
2219 netdev_notice(netdev,
2220 "forcing tx udp tunnel checksumming off\n");
2221 features &= ~NETIF_F_GSO_UDP_TUNNEL_CSUM;
2222 }
2223 }
2224
1a510ccf
LT		 2225 return features;
2226}
2227
c5aa9e3b
LT		 2228static int xgbe_set_features(struct net_device *netdev,
2229 netdev_features_t features)
2230{
2231 struct xgbe_prv_data *pdata = netdev_priv(netdev);
2232 struct xgbe_hw_if *hw_if = &pdata->hw_if;
5b9dfe29
LT		 2233 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
2234 int ret = 0;
c5aa9e3b 2235
5b9dfe29 2236 rxhash = pdata->netdev_features & NETIF_F_RXHASH;
801c62d9
LT		 2237 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
2238 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
2239 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
c5aa9e3b 2240
5b9dfe29
LT		 2241 if ((features & NETIF_F_RXHASH) && !rxhash)
2242 ret = hw_if->enable_rss(pdata);
2243 else if (!(features & NETIF_F_RXHASH) && rxhash)
2244 ret = hw_if->disable_rss(pdata);
2245 if (ret)
2246 return ret;
2247
801c62d9 2248 if ((features & NETIF_F_RXCSUM) && !rxcsum)
c5aa9e3b 2249 hw_if->enable_rx_csum(pdata);
801c62d9 2250 else if (!(features & NETIF_F_RXCSUM) && rxcsum)
c5aa9e3b 2251 hw_if->disable_rx_csum(pdata);
c5aa9e3b 2252
801c62d9 2253 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
c5aa9e3b 2254 hw_if->enable_rx_vlan_stripping(pdata);
801c62d9 2255 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
c5aa9e3b 2256 hw_if->disable_rx_vlan_stripping(pdata);
801c62d9
LT		 2257
2258 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
2259 hw_if->enable_rx_vlan_filtering(pdata);
2260 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
2261 hw_if->disable_rx_vlan_filtering(pdata);
c5aa9e3b
LT		 2262
2263 pdata->netdev_features = features;
2264
2265 DBGPR("<--xgbe_set_features\n");
2266
2267 return 0;
2268}
2269
1a510ccf
LT		 2270static netdev_features_t xgbe_features_check(struct sk_buff *skb,
2271 struct net_device *netdev,
2272 netdev_features_t features)
2273{
2274 features = vlan_features_check(skb, features);
2275 features = vxlan_features_check(skb, features);
2276
2277 return features;
2278}
2279
c5aa9e3b
LT		 2280static const struct net_device_ops xgbe_netdev_ops = {
2281 .ndo_open = xgbe_open,
2282 .ndo_stop = xgbe_close,
2283 .ndo_start_xmit = xgbe_xmit,
2284 .ndo_set_rx_mode = xgbe_set_rx_mode,
2285 .ndo_set_mac_address = xgbe_set_mac_address,
2286 .ndo_validate_addr = eth_validate_addr,
a7605370 2287 .ndo_eth_ioctl = xgbe_ioctl,
c5aa9e3b 2288 .ndo_change_mtu = xgbe_change_mtu,
a8373f1a 2289 .ndo_tx_timeout = xgbe_tx_timeout,
c5aa9e3b 2290 .ndo_get_stats64 = xgbe_get_stats64,
801c62d9
LT		 2291 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
2292 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
c5aa9e3b
LT		 2293#ifdef CONFIG_NET_POLL_CONTROLLER
2294 .ndo_poll_controller = xgbe_poll_controller,
2295#endif
fca2d994 2296 .ndo_setup_tc = xgbe_setup_tc,
1a510ccf 2297 .ndo_fix_features = xgbe_fix_features,
c5aa9e3b 2298 .ndo_set_features = xgbe_set_features,
1a510ccf 2299 .ndo_features_check = xgbe_features_check,
c5aa9e3b
LT		 2300};
2301
ce0b15d1 2302const struct net_device_ops *xgbe_get_netdev_ops(void)
c5aa9e3b 2303{
ce0b15d1 2304 return &xgbe_netdev_ops;
c5aa9e3b
LT		 2305}
2306
9867e8fb
LT		 2307static void xgbe_rx_refresh(struct xgbe_channel *channel)
2308{
2309 struct xgbe_prv_data *pdata = channel->pdata;
270894e7 2310 struct xgbe_hw_if *hw_if = &pdata->hw_if;
9867e8fb
LT		 2311 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2312 struct xgbe_ring *ring = channel->rx_ring;
2313 struct xgbe_ring_data *rdata;
2314
270894e7
LT		 2315 while (ring->dirty != ring->cur) {
2316 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
2317
2318 /* Reset rdata values */
2319 desc_if->unmap_rdata(pdata, rdata);
2320
2321 if (desc_if->map_rx_buffer(pdata, ring, rdata))
2322 break;
2323
8dee19e6 2324 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
270894e7
LT		 2325
2326 ring->dirty++;
2327 }
9867e8fb 2328
ceb8f6be
LT		 2329 /* Make sure everything is written before the register write */
2330 wmb();
2331
9867e8fb
LT		 2332 /* Update the Rx Tail Pointer Register with address of
2333 * the last cleaned entry */
270894e7 2334 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
9867e8fb
LT		 2335 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
2336 lower_32_bits(rdata->rdesc_dma));
2337}
2338
7d9ca345
LT		 2339static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
2340 struct napi_struct *napi,
08dcc47c 2341 struct xgbe_ring_data *rdata,
7d9ca345 2342 unsigned int len)
08dcc47c 2343{
08dcc47c
LT		 2344 struct sk_buff *skb;
2345 u8 *packet;
08dcc47c 2346
385565a1 2347 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
08dcc47c
LT		 2348 if (!skb)
2349 return NULL;
2350
622c36f1 2351 /* Pull in the header buffer which may contain just the header
7d9ca345
LT		 2352 * or the header plus data
2353 */
cfbfd86b
LT		 2354 dma_sync_single_range_for_cpu(pdata->dev, rdata->rx.hdr.dma_base,
2355 rdata->rx.hdr.dma_off,
2356 rdata->rx.hdr.dma_len, DMA_FROM_DEVICE);
7d9ca345 2357
c9f140eb
LT		 2358 packet = page_address(rdata->rx.hdr.pa.pages) +
2359 rdata->rx.hdr.pa.pages_offset;
622c36f1
LT		 2360 skb_copy_to_linear_data(skb, packet, len);
2361 skb_put(skb, len);
08dcc47c
LT		 2362
2363 return skb;
2364}
2365
622c36f1
LT		 2366static unsigned int xgbe_rx_buf1_len(struct xgbe_ring_data *rdata,
2367 struct xgbe_packet_data *packet)
2368{
2369 /* Always zero if not the first descriptor */
2370 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST))
2371 return 0;
2372
2373 /* First descriptor with split header, return header length */
2374 if (rdata->rx.hdr_len)
2375 return rdata->rx.hdr_len;
2376
2377 /* First descriptor but not the last descriptor and no split header,
2378 * so the full buffer was used
2379 */
2380 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2381 return rdata->rx.hdr.dma_len;
2382
2383 /* First descriptor and last descriptor and no split header, so
2384 * calculate how much of the buffer was used
2385 */
2386 return min_t(unsigned int, rdata->rx.hdr.dma_len, rdata->rx.len);
2387}
2388
2389static unsigned int xgbe_rx_buf2_len(struct xgbe_ring_data *rdata,
2390 struct xgbe_packet_data *packet,
2391 unsigned int len)
2392{
2393 /* Always the full buffer if not the last descriptor */
2394 if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST))
2395 return rdata->rx.buf.dma_len;
2396
2397 /* Last descriptor so calculate how much of the buffer was used
2398 * for the last bit of data
2399 */
2400 return rdata->rx.len - len;
2401}
2402
c5aa9e3b
LT		 2403static int xgbe_tx_poll(struct xgbe_channel *channel)
2404{
2405 struct xgbe_prv_data *pdata = channel->pdata;
2406 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2407 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2408 struct xgbe_ring *ring = channel->tx_ring;
2409 struct xgbe_ring_data *rdata;
2410 struct xgbe_ring_desc *rdesc;
2411 struct net_device *netdev = pdata->netdev;
5fb4b86a 2412 struct netdev_queue *txq;
c5aa9e3b 2413 int processed = 0;
5fb4b86a 2414 unsigned int tx_packets = 0, tx_bytes = 0;
20a41fba 2415 unsigned int cur;
c5aa9e3b
LT		 2416
2417 DBGPR("-->xgbe_tx_poll\n");
2418
2419 /* Nothing to do if there isn't a Tx ring for this channel */
2420 if (!ring)
2421 return 0;
2422
20a41fba 2423 cur = ring->cur;
20986ed8
LT		 2424
2425 /* Be sure we get ring->cur before accessing descriptor data */
2426 smp_rmb();
2427
5fb4b86a
LT		 2428 txq = netdev_get_tx_queue(netdev, channel->queue_index);
2429
d0a8ba6c 2430 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
20a41fba 2431 (ring->dirty != cur)) {
d0a8ba6c 2432 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
c5aa9e3b
LT		 2433 rdesc = rdata->rdesc;
2434
2435 if (!hw_if->tx_complete(rdesc))
2436 break;
2437
5449e271
LT		 2438 /* Make sure descriptor fields are read after reading the OWN
2439 * bit */
ceb8f6be 2440 dma_rmb();
5449e271 2441
34bf65df
LT		 2442 if (netif_msg_tx_done(pdata))
2443 xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0);
c5aa9e3b 2444
5fb4b86a
LT		 2445 if (hw_if->is_last_desc(rdesc)) {
2446 tx_packets += rdata->tx.packets;
2447 tx_bytes += rdata->tx.bytes;
2448 }
2449
c5aa9e3b 2450 /* Free the SKB and reset the descriptor for re-use */
08dcc47c 2451 desc_if->unmap_rdata(pdata, rdata);
c5aa9e3b
LT		 2452 hw_if->tx_desc_reset(rdata);
2453
2454 processed++;
2455 ring->dirty++;
2456 }
2457
5fb4b86a 2458 if (!processed)
a83ef427 2459 return 0;
5fb4b86a
LT		 2460
2461 netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
2462
c5aa9e3b 2463 if ((ring->tx.queue_stopped == 1) &&
d0a8ba6c 2464 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
c5aa9e3b 2465 ring->tx.queue_stopped = 0;
5fb4b86a 2466 netif_tx_wake_queue(txq);
c5aa9e3b
LT		 2467 }
2468
2469 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
2470
c5aa9e3b
LT		 2471 return processed;
2472}
2473
2474static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
2475{
2476 struct xgbe_prv_data *pdata = channel->pdata;
2477 struct xgbe_hw_if *hw_if = &pdata->hw_if;
c5aa9e3b
LT		 2478 struct xgbe_ring *ring = channel->rx_ring;
2479 struct xgbe_ring_data *rdata;
2480 struct xgbe_packet_data *packet;
2481 struct net_device *netdev = pdata->netdev;
9227dc5e 2482 struct napi_struct *napi;
c5aa9e3b 2483 struct sk_buff *skb;
23e4eef7 2484 struct skb_shared_hwtstamps *hwtstamps;
622c36f1
LT		 2485 unsigned int last, error, context_next, context;
2486 unsigned int len, buf1_len, buf2_len, max_len;
55ca6bcd
LT		 2487 unsigned int received = 0;
2488 int packet_count = 0;
c5aa9e3b
LT		 2489
2490 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
2491
2492 /* Nothing to do if there isn't a Rx ring for this channel */
2493 if (!ring)
2494 return 0;
2495
622c36f1 2496 last = 0;
7d9ca345
LT		 2497 context_next = 0;
2498
9227dc5e
LT		 2499 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
2500
23e4eef7 2501 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
c5aa9e3b 2502 packet = &ring->packet_data;
55ca6bcd 2503 while (packet_count < budget) {
c5aa9e3b
LT		 2504 DBGPR(" cur = %d\n", ring->cur);
2505
23e4eef7
LT		 2506 /* First time in loop see if we need to restore state */
2507 if (!received && rdata->state_saved) {
23e4eef7
LT		 2508 skb = rdata->state.skb;
2509 error = rdata->state.error;
2510 len = rdata->state.len;
2511 } else {
2512 memset(packet, 0, sizeof(*packet));
23e4eef7
LT		 2513 skb = NULL;
2514 error = 0;
2515 len = 0;
2516 }
c5aa9e3b
LT		 2517
2518read_again:
23e4eef7
LT		 2519 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2520
270894e7 2521 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
9867e8fb
LT		 2522 xgbe_rx_refresh(channel);
2523
c5aa9e3b
LT		 2524 if (hw_if->dev_read(channel))
2525 break;
2526
2527 received++;
2528 ring->cur++;
c5aa9e3b 2529
622c36f1
LT		 2530 last = XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
2531 LAST);
23e4eef7
LT		 2532 context_next = XGMAC_GET_BITS(packet->attributes,
2533 RX_PACKET_ATTRIBUTES,
2534 CONTEXT_NEXT);
2535 context = XGMAC_GET_BITS(packet->attributes,
2536 RX_PACKET_ATTRIBUTES,
2537 CONTEXT);
c5aa9e3b
LT		 2538
2539 /* Earlier error, just drain the remaining data */
622c36f1 2540 if ((!last || context_next) && error)
c5aa9e3b
LT		 2541 goto read_again;
2542
2543 if (error || packet->errors) {
2544 if (packet->errors)
34bf65df
LT		 2545 netif_err(pdata, rx_err, netdev,
2546 "error in received packet\n");
c5aa9e3b 2547 dev_kfree_skb(skb);
55ca6bcd 2548 goto next_packet;
c5aa9e3b
LT		 2549 }
2550
23e4eef7 2551 if (!context) {
622c36f1
LT		 2552 /* Get the data length in the descriptor buffers */
2553 buf1_len = xgbe_rx_buf1_len(rdata, packet);
2554 len += buf1_len;
2555 buf2_len = xgbe_rx_buf2_len(rdata, packet, len);
2556 len += buf2_len;
7d9ca345 2557
622c36f1 2558 if (!skb) {
7d9ca345 2559 skb = xgbe_create_skb(pdata, napi, rdata,
622c36f1
LT		 2560 buf1_len);
2561 if (!skb) {
08dcc47c 2562 error = 1;
622c36f1
LT		 2563 goto skip_data;
2564 }
2565 }
2566
2567 if (buf2_len) {
cfbfd86b
LT		 2568 dma_sync_single_range_for_cpu(pdata->dev,
2569 rdata->rx.buf.dma_base,
2570 rdata->rx.buf.dma_off,
c9f140eb 2571 rdata->rx.buf.dma_len,
174fd259
LT		 2572 DMA_FROM_DEVICE);
2573
2574 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
c9f140eb
LT		 2575 rdata->rx.buf.pa.pages,
2576 rdata->rx.buf.pa.pages_offset,
622c36f1 2577 buf2_len,
7d9ca345 2578 rdata->rx.buf.dma_len);
c9f140eb 2579 rdata->rx.buf.pa.pages = NULL;
174fd259 2580 }
c5aa9e3b 2581 }
c5aa9e3b 2582
622c36f1
LT		 2583skip_data:
2584 if (!last || context_next)
c5aa9e3b
LT		 2585 goto read_again;
2586
23e4eef7 2587 if (!skb)
55ca6bcd 2588 goto next_packet;
23e4eef7 2589
c5aa9e3b
LT		 2590 /* Be sure we don't exceed the configured MTU */
2591 max_len = netdev->mtu + ETH_HLEN;
2592 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
2593 (skb->protocol == htons(ETH_P_8021Q)))
2594 max_len += VLAN_HLEN;
2595
2596 if (skb->len > max_len) {
34bf65df
LT		 2597 netif_err(pdata, rx_err, netdev,
2598 "packet length exceeds configured MTU\n");
c5aa9e3b 2599 dev_kfree_skb(skb);
55ca6bcd 2600 goto next_packet;
c5aa9e3b
LT		 2601 }
2602
34bf65df
LT		 2603 if (netif_msg_pktdata(pdata))
2604 xgbe_print_pkt(netdev, skb, false);
c5aa9e3b
LT		 2605
2606 skb_checksum_none_assert(skb);
2607 if (XGMAC_GET_BITS(packet->attributes,
2608 RX_PACKET_ATTRIBUTES, CSUM_DONE))
2609 skb->ip_summed = CHECKSUM_UNNECESSARY;
2610
1a510ccf
LT		 2611 if (XGMAC_GET_BITS(packet->attributes,
2612 RX_PACKET_ATTRIBUTES, TNP)) {
2613 skb->encapsulation = 1;
2614
2615 if (XGMAC_GET_BITS(packet->attributes,
2616 RX_PACKET_ATTRIBUTES, TNPCSUM_DONE))
2617 skb->csum_level = 1;
2618 }
2619
c5aa9e3b
LT		 2620 if (XGMAC_GET_BITS(packet->attributes,
2621 RX_PACKET_ATTRIBUTES, VLAN_CTAG))
2622 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2623 packet->vlan_ctag);
2624
23e4eef7
LT		 2625 if (XGMAC_GET_BITS(packet->attributes,
2626 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2627 u64 nsec;
2628
2629 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2630 packet->rx_tstamp);
2631 hwtstamps = skb_hwtstamps(skb);
2632 hwtstamps->hwtstamp = ns_to_ktime(nsec);
2633 }
2634
5b9dfe29
LT		 2635 if (XGMAC_GET_BITS(packet->attributes,
2636 RX_PACKET_ATTRIBUTES, RSS_HASH))
2637 skb_set_hash(skb, packet->rss_hash,
2638 packet->rss_hash_type);
2639
c5aa9e3b
LT		 2640 skb->dev = netdev;
2641 skb->protocol = eth_type_trans(skb, netdev);
2642 skb_record_rx_queue(skb, channel->queue_index);
c5aa9e3b 2643
9227dc5e 2644 napi_gro_receive(napi, skb);
55ca6bcd
LT		 2645
2646next_packet:
2647 packet_count++;
c5aa9e3b
LT		 2648 }
2649
23e4eef7 2650 /* Check if we need to save state before leaving */
622c36f1 2651 if (received && (!last || context_next)) {
23e4eef7
LT		 2652 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
2653 rdata->state_saved = 1;
23e4eef7
LT		 2654 rdata->state.skb = skb;
2655 rdata->state.len = len;
2656 rdata->state.error = error;
2657 }
2658
55ca6bcd 2659 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
c5aa9e3b 2660
55ca6bcd 2661 return packet_count;
c5aa9e3b
LT		 2662}
2663
9227dc5e
LT		 2664static int xgbe_one_poll(struct napi_struct *napi, int budget)
2665{
2666 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2667 napi);
4c70dd8a 2668 struct xgbe_prv_data *pdata = channel->pdata;
9227dc5e
LT		 2669 int processed = 0;
2670
2671 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2672
2673 /* Cleanup Tx ring first */
2674 xgbe_tx_poll(channel);
2675
2676 /* Process Rx ring next */
2677 processed = xgbe_rx_poll(channel, budget);
2678
2679 /* If we processed everything, we are done */
d7aba644 2680 if ((processed < budget) && napi_complete_done(napi, processed)) {
9227dc5e 2681 /* Enable Tx and Rx interrupts */
4c70dd8a
LT		 2682 if (pdata->channel_irq_mode)
2683 xgbe_enable_rx_tx_int(pdata, channel);
2684 else
2685 enable_irq(channel->dma_irq);
9227dc5e
LT		 2686 }
2687
2688 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2689
2690 return processed;
2691}
2692
2693static int xgbe_all_poll(struct napi_struct *napi, int budget)
c5aa9e3b
LT		 2694{
2695 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2696 napi);
2697 struct xgbe_channel *channel;
9867e8fb
LT		 2698 int ring_budget;
2699 int processed, last_processed;
c5aa9e3b
LT		 2700 unsigned int i;
2701
9227dc5e 2702 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
c5aa9e3b 2703
c5aa9e3b 2704 processed = 0;
9867e8fb
LT		 2705 ring_budget = budget / pdata->rx_ring_count;
2706 do {
2707 last_processed = processed;
2708
18f9f0ac
LT		 2709 for (i = 0; i < pdata->channel_count; i++) {
2710 channel = pdata->channel[i];
2711
9867e8fb
LT		 2712 /* Cleanup Tx ring first */
2713 xgbe_tx_poll(channel);
2714
2715 /* Process Rx ring next */
2716 if (ring_budget > (budget - processed))
2717 ring_budget = budget - processed;
2718 processed += xgbe_rx_poll(channel, ring_budget);
2719 }
2720 } while ((processed < budget) && (processed != last_processed));
c5aa9e3b
LT		 2721
2722 /* If we processed everything, we are done */
d7aba644 2723 if ((processed < budget) && napi_complete_done(napi, processed)) {
c5aa9e3b
LT		 2724 /* Enable Tx and Rx interrupts */
2725 xgbe_enable_rx_tx_ints(pdata);
2726 }
2727
9227dc5e 2728 DBGPR("<--xgbe_all_poll: received = %d\n", processed);
c5aa9e3b
LT		 2729
2730 return processed;
2731}
2732
34bf65df
LT		 2733void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
2734 unsigned int idx, unsigned int count, unsigned int flag)
c5aa9e3b
LT		 2735{
2736 struct xgbe_ring_data *rdata;
2737 struct xgbe_ring_desc *rdesc;
2738
2739 while (count--) {
d0a8ba6c 2740 rdata = XGBE_GET_DESC_DATA(ring, idx);
c5aa9e3b 2741 rdesc = rdata->rdesc;
34bf65df
LT		 2742 netdev_dbg(pdata->netdev,
2743 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2744 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2745 le32_to_cpu(rdesc->desc0),
2746 le32_to_cpu(rdesc->desc1),
2747 le32_to_cpu(rdesc->desc2),
2748 le32_to_cpu(rdesc->desc3));
c5aa9e3b
LT		 2749 idx++;
2750 }
2751}
2752
34bf65df 2753void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring,
c5aa9e3b
LT		 2754 unsigned int idx)
2755{
34bf65df
LT		 2756 struct xgbe_ring_data *rdata;
2757 struct xgbe_ring_desc *rdesc;
2758
2759 rdata = XGBE_GET_DESC_DATA(ring, idx);
2760 rdesc = rdata->rdesc;
2761 netdev_dbg(pdata->netdev,
2762 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n",
2763 idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2764 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
c5aa9e3b
LT		 2765}
2766
2767void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2768{
2769 struct ethhdr *eth = (struct ethhdr *)skb->data;
c5aa9e3b 2770 unsigned char buffer[128];
9a07ae68 2771 unsigned int i;
c5aa9e3b 2772
34bf65df 2773 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
c5aa9e3b 2774
34bf65df
LT		 2775 netdev_dbg(netdev, "%s packet of %d bytes\n",
2776 (tx_rx ? "TX" : "RX"), skb->len);
c5aa9e3b 2777
34bf65df
LT		 2778 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2779 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source);
2780 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto));
c5aa9e3b 2781
9a07ae68
AS		 2782 for (i = 0; i < skb->len; i += 32) {
2783 unsigned int len = min(skb->len - i, 32U);
2784
2785 hex_dump_to_buffer(&skb->data[i], len, 32, 1,
2786 buffer, sizeof(buffer), false);
2787 netdev_dbg(netdev, " %#06x: %s\n", i, buffer);
c5aa9e3b 2788 }
c5aa9e3b 2789
34bf65df 2790 netdev_dbg(netdev, "\n************** SKB dump ****************\n");
c5aa9e3b 2791}
Linux 6.x block layer and io_uring tree(s)