drivers:net: Remove unnecessary OOM messages after netdev_alloc_skb
[linux-2.6-block.git] / drivers / net / ethernet / amd / au1000_eth.c
CommitLineData
1da177e4
LT
1/*
2 *
3 * Alchemy Au1x00 ethernet driver
4 *
89be0501 5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
1da177e4
LT
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
6aa20a22
JG
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
1da177e4 11 * ioctls (SIOCGMIIPHY)
0638dec0
HVR
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
14 *
1da177e4 15 * Author: MontaVista Software, Inc.
ec7eabdd 16 * ppopov@mvista.com or source@mvista.com
1da177e4
LT
17 *
18 * ########################################################################
19 *
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * for more details.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
32 *
33 * ########################################################################
34 *
6aa20a22 35 *
1da177e4 36 */
215e17be
FF
37#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38
bc36b428 39#include <linux/capability.h>
d791c2bd 40#include <linux/dma-mapping.h>
1da177e4
LT
41#include <linux/module.h>
42#include <linux/kernel.h>
1da177e4
LT
43#include <linux/string.h>
44#include <linux/timer.h>
45#include <linux/errno.h>
46#include <linux/in.h>
47#include <linux/ioport.h>
48#include <linux/bitops.h>
49#include <linux/slab.h>
50#include <linux/interrupt.h>
1da177e4
LT
51#include <linux/init.h>
52#include <linux/netdevice.h>
53#include <linux/etherdevice.h>
54#include <linux/ethtool.h>
55#include <linux/mii.h>
56#include <linux/skbuff.h>
57#include <linux/delay.h>
8cd35da0 58#include <linux/crc32.h>
0638dec0 59#include <linux/phy.h>
bd2302c2 60#include <linux/platform_device.h>
49a42c08
FF
61#include <linux/cpu.h>
62#include <linux/io.h>
25b31cb1 63
1da177e4
LT
64#include <asm/mipsregs.h>
65#include <asm/irq.h>
1da177e4
LT
66#include <asm/processor.h>
67
25b31cb1 68#include <au1000.h>
bd2302c2 69#include <au1xxx_eth.h>
25b31cb1
YY
70#include <prom.h>
71
1da177e4
LT
72#include "au1000_eth.h"
73
74#ifdef AU1000_ETH_DEBUG
75static int au1000_debug = 5;
76#else
77static int au1000_debug = 3;
78#endif
79
7cd2e6e3
FF
80#define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
81 NETIF_MSG_PROBE | \
82 NETIF_MSG_LINK)
83
89be0501 84#define DRV_NAME "au1000_eth"
8020eb82 85#define DRV_VERSION "1.7"
1da177e4
LT
86#define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
87#define DRV_DESC "Au1xxx on-chip Ethernet driver"
88
89MODULE_AUTHOR(DRV_AUTHOR);
90MODULE_DESCRIPTION(DRV_DESC);
91MODULE_LICENSE("GPL");
13130c7a 92MODULE_VERSION(DRV_VERSION);
1da177e4 93
1da177e4
LT
94/*
95 * Theory of operation
96 *
6aa20a22
JG
97 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
98 * There are four receive and four transmit descriptors. These
99 * descriptors are not in memory; rather, they are just a set of
1da177e4
LT
100 * hardware registers.
101 *
102 * Since the Au1000 has a coherent data cache, the receive and
6aa20a22 103 * transmit buffers are allocated from the KSEG0 segment. The
1da177e4
LT
104 * hardware registers, however, are still mapped at KSEG1 to
105 * make sure there's no out-of-order writes, and that all writes
106 * complete immediately.
107 */
108
0638dec0
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109/*
110 * board-specific configurations
111 *
112 * PHY detection algorithm
113 *
bd2302c2 114 * If phy_static_config is undefined, the PHY setup is
0638dec0
HVR
115 * autodetected:
116 *
117 * mii_probe() first searches the current MAC's MII bus for a PHY,
bd2302c2 118 * selecting the first (or last, if phy_search_highest_addr is
0638dec0
HVR
119 * defined) PHY address not already claimed by another netdev.
120 *
121 * If nothing was found that way when searching for the 2nd ethernet
bd2302c2 122 * controller's PHY and phy1_search_mac0 is defined, then
0638dec0
HVR
123 * the first MII bus is searched as well for an unclaimed PHY; this is
124 * needed in case of a dual-PHY accessible only through the MAC0's MII
125 * bus.
126 *
127 * Finally, if no PHY is found, then the corresponding ethernet
128 * controller is not registered to the network subsystem.
1da177e4
LT
129 */
130
bd2302c2 131/* autodetection defaults: phy1_search_mac0 */
1da177e4 132
0638dec0
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133/* static PHY setup
134 *
135 * most boards PHY setup should be detectable properly with the
136 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
137 * you have a switch attached, or want to use the PHY's interrupt
138 * notification capabilities) you can provide a static PHY
139 * configuration here
140 *
141 * IRQs may only be set, if a PHY address was configured
142 * If a PHY address is given, also a bus id is required to be set
143 *
144 * ps: make sure the used irqs are configured properly in the board
145 * specific irq-map
146 */
1da177e4 147
eb049630 148static void au1000_enable_mac(struct net_device *dev, int force_reset)
5ef3041e
FF
149{
150 unsigned long flags;
151 struct au1000_private *aup = netdev_priv(dev);
152
153 spin_lock_irqsave(&aup->lock, flags);
154
ec7eabdd 155 if (force_reset || (!aup->mac_enabled)) {
462ca99c 156 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
5ef3041e 157 au_sync_delay(2);
d0e7cb5d 158 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
462ca99c 159 | MAC_EN_CLOCK_ENABLE), aup->enable);
5ef3041e
FF
160 au_sync_delay(2);
161
162 aup->mac_enabled = 1;
163 }
164
165 spin_unlock_irqrestore(&aup->lock, flags);
166}
167
0638dec0
HVR
168/*
169 * MII operations
170 */
1210dde7 171static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
1da177e4 172{
454d7c9b 173 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d
FF
174 u32 *const mii_control_reg = &aup->mac->mii_control;
175 u32 *const mii_data_reg = &aup->mac->mii_data;
1da177e4
LT
176 u32 timedout = 20;
177 u32 mii_control;
178
d0e7cb5d 179 while (readl(mii_control_reg) & MAC_MII_BUSY) {
1da177e4
LT
180 mdelay(1);
181 if (--timedout == 0) {
5368c726 182 netdev_err(dev, "read_MII busy timeout!!\n");
1da177e4
LT
183 return -1;
184 }
185 }
186
6aa20a22 187 mii_control = MAC_SET_MII_SELECT_REG(reg) |
0638dec0 188 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
1da177e4 189
d0e7cb5d 190 writel(mii_control, mii_control_reg);
1da177e4
LT
191
192 timedout = 20;
d0e7cb5d 193 while (readl(mii_control_reg) & MAC_MII_BUSY) {
1da177e4
LT
194 mdelay(1);
195 if (--timedout == 0) {
5368c726 196 netdev_err(dev, "mdio_read busy timeout!!\n");
1da177e4
LT
197 return -1;
198 }
199 }
d0e7cb5d 200 return readl(mii_data_reg);
1da177e4
LT
201}
202
1210dde7
AB
203static void au1000_mdio_write(struct net_device *dev, int phy_addr,
204 int reg, u16 value)
1da177e4 205{
454d7c9b 206 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d
FF
207 u32 *const mii_control_reg = &aup->mac->mii_control;
208 u32 *const mii_data_reg = &aup->mac->mii_data;
1da177e4
LT
209 u32 timedout = 20;
210 u32 mii_control;
211
d0e7cb5d 212 while (readl(mii_control_reg) & MAC_MII_BUSY) {
1da177e4
LT
213 mdelay(1);
214 if (--timedout == 0) {
5368c726 215 netdev_err(dev, "mdio_write busy timeout!!\n");
1da177e4
LT
216 return;
217 }
218 }
219
6aa20a22 220 mii_control = MAC_SET_MII_SELECT_REG(reg) |
0638dec0 221 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
1da177e4 222
d0e7cb5d
FF
223 writel(value, mii_data_reg);
224 writel(mii_control, mii_control_reg);
1da177e4
LT
225}
226
1210dde7 227static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
0638dec0
HVR
228{
229 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
dc99839c
FF
230 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus)
231 */
0638dec0
HVR
232 struct net_device *const dev = bus->priv;
233
dc99839c
FF
234 /* make sure the MAC associated with this
235 * mii_bus is enabled
236 */
237 au1000_enable_mac(dev, 0);
238
1210dde7 239 return au1000_mdio_read(dev, phy_addr, regnum);
0638dec0 240}
1da177e4 241
1210dde7
AB
242static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
243 u16 value)
1da177e4 244{
0638dec0 245 struct net_device *const dev = bus->priv;
1da177e4 246
dc99839c
FF
247 /* make sure the MAC associated with this
248 * mii_bus is enabled
249 */
250 au1000_enable_mac(dev, 0);
251
1210dde7 252 au1000_mdio_write(dev, phy_addr, regnum, value);
0638dec0 253 return 0;
1da177e4
LT
254}
255
1210dde7 256static int au1000_mdiobus_reset(struct mii_bus *bus)
1da177e4 257{
0638dec0 258 struct net_device *const dev = bus->priv;
1da177e4 259
dc99839c
FF
260 /* make sure the MAC associated with this
261 * mii_bus is enabled
262 */
263 au1000_enable_mac(dev, 0);
264
0638dec0
HVR
265 return 0;
266}
1da177e4 267
eb049630 268static void au1000_hard_stop(struct net_device *dev)
5ef3041e
FF
269{
270 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d 271 u32 reg;
5ef3041e 272
5368c726 273 netif_dbg(aup, drv, dev, "hard stop\n");
5ef3041e 274
d0e7cb5d
FF
275 reg = readl(&aup->mac->control);
276 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
277 writel(reg, &aup->mac->control);
5ef3041e
FF
278 au_sync_delay(10);
279}
280
eb049630 281static void au1000_enable_rx_tx(struct net_device *dev)
5ef3041e
FF
282{
283 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d 284 u32 reg;
5ef3041e 285
5368c726 286 netif_dbg(aup, hw, dev, "enable_rx_tx\n");
5ef3041e 287
d0e7cb5d
FF
288 reg = readl(&aup->mac->control);
289 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
290 writel(reg, &aup->mac->control);
5ef3041e
FF
291 au_sync_delay(10);
292}
293
294static void
295au1000_adjust_link(struct net_device *dev)
296{
297 struct au1000_private *aup = netdev_priv(dev);
298 struct phy_device *phydev = aup->phy_dev;
299 unsigned long flags;
d0e7cb5d 300 u32 reg;
5ef3041e
FF
301
302 int status_change = 0;
303
304 BUG_ON(!aup->phy_dev);
305
306 spin_lock_irqsave(&aup->lock, flags);
307
308 if (phydev->link && (aup->old_speed != phydev->speed)) {
2cc3c6b1 309 /* speed changed */
5ef3041e 310
2cc3c6b1 311 switch (phydev->speed) {
5ef3041e
FF
312 case SPEED_10:
313 case SPEED_100:
314 break;
315 default:
5368c726
FF
316 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
317 phydev->speed);
5ef3041e
FF
318 break;
319 }
320
321 aup->old_speed = phydev->speed;
322
323 status_change = 1;
324 }
325
326 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
2cc3c6b1 327 /* duplex mode changed */
5ef3041e
FF
328
329 /* switching duplex mode requires to disable rx and tx! */
eb049630 330 au1000_hard_stop(dev);
5ef3041e 331
d0e7cb5d
FF
332 reg = readl(&aup->mac->control);
333 if (DUPLEX_FULL == phydev->duplex) {
334 reg |= MAC_FULL_DUPLEX;
335 reg &= ~MAC_DISABLE_RX_OWN;
336 } else {
337 reg &= ~MAC_FULL_DUPLEX;
338 reg |= MAC_DISABLE_RX_OWN;
339 }
340 writel(reg, &aup->mac->control);
5ef3041e
FF
341 au_sync_delay(1);
342
eb049630 343 au1000_enable_rx_tx(dev);
5ef3041e
FF
344 aup->old_duplex = phydev->duplex;
345
346 status_change = 1;
347 }
348
2cc3c6b1
FF
349 if (phydev->link != aup->old_link) {
350 /* link state changed */
5ef3041e
FF
351
352 if (!phydev->link) {
353 /* link went down */
354 aup->old_speed = 0;
355 aup->old_duplex = -1;
356 }
357
358 aup->old_link = phydev->link;
359 status_change = 1;
360 }
361
362 spin_unlock_irqrestore(&aup->lock, flags);
363
364 if (status_change) {
365 if (phydev->link)
5368c726
FF
366 netdev_info(dev, "link up (%d/%s)\n",
367 phydev->speed,
5ef3041e
FF
368 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
369 else
5368c726 370 netdev_info(dev, "link down\n");
5ef3041e
FF
371 }
372}
373
ec7eabdd 374static int au1000_mii_probe(struct net_device *dev)
0638dec0 375{
454d7c9b 376 struct au1000_private *const aup = netdev_priv(dev);
0638dec0 377 struct phy_device *phydev = NULL;
18b8e15b 378 int phy_addr;
0638dec0 379
bd2302c2
FF
380 if (aup->phy_static_config) {
381 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
0638dec0 382
bd2302c2
FF
383 if (aup->phy_addr)
384 phydev = aup->mii_bus->phy_map[aup->phy_addr];
385 else
5368c726 386 netdev_info(dev, "using PHY-less setup\n");
0638dec0 387 return 0;
18b8e15b 388 }
0638dec0 389
18b8e15b 390 /* find the first (lowest address) PHY
dc99839c
FF
391 * on the current MAC's MII bus
392 */
18b8e15b
FF
393 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
394 if (aup->mii_bus->phy_map[phy_addr]) {
395 phydev = aup->mii_bus->phy_map[phy_addr];
396 if (!aup->phy_search_highest_addr)
397 /* break out with first one found */
398 break;
399 }
0638dec0 400
18b8e15b
FF
401 if (aup->phy1_search_mac0) {
402 /* try harder to find a PHY */
403 if (!phydev && (aup->mac_id == 1)) {
404 /* no PHY found, maybe we have a dual PHY? */
405 dev_info(&dev->dev, ": no PHY found on MAC1, "
406 "let's see if it's attached to MAC0...\n");
407
408 /* find the first (lowest address) non-attached
409 * PHY on the MAC0 MII bus
410 */
411 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
412 struct phy_device *const tmp_phydev =
413 aup->mii_bus->phy_map[phy_addr];
414
415 if (aup->mac_id == 1)
416 break;
417
418 /* no PHY here... */
419 if (!tmp_phydev)
420 continue;
421
422 /* already claimed by MAC0 */
423 if (tmp_phydev->attached_dev)
424 continue;
425
426 phydev = tmp_phydev;
427 break; /* found it */
bd2302c2 428 }
1da177e4
LT
429 }
430 }
1da177e4 431
0638dec0 432 if (!phydev) {
5368c726 433 netdev_err(dev, "no PHY found\n");
1da177e4
LT
434 return -1;
435 }
436
0638dec0 437 /* now we are supposed to have a proper phydev, to attach to... */
0638dec0
HVR
438 BUG_ON(phydev->attached_dev);
439
f9a8f83b
FF
440 phydev = phy_connect(dev, dev_name(&phydev->dev),
441 &au1000_adjust_link, PHY_INTERFACE_MODE_MII);
0638dec0
HVR
442
443 if (IS_ERR(phydev)) {
5368c726 444 netdev_err(dev, "Could not attach to PHY\n");
0638dec0
HVR
445 return PTR_ERR(phydev);
446 }
447
448 /* mask with MAC supported features */
449 phydev->supported &= (SUPPORTED_10baseT_Half
450 | SUPPORTED_10baseT_Full
451 | SUPPORTED_100baseT_Half
452 | SUPPORTED_100baseT_Full
453 | SUPPORTED_Autoneg
454 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
455 | SUPPORTED_MII
456 | SUPPORTED_TP);
457
458 phydev->advertising = phydev->supported;
459
460 aup->old_link = 0;
461 aup->old_speed = 0;
462 aup->old_duplex = -1;
463 aup->phy_dev = phydev;
464
5368c726
FF
465 netdev_info(dev, "attached PHY driver [%s] "
466 "(mii_bus:phy_addr=%s, irq=%d)\n",
db1d7bf7 467 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1da177e4
LT
468
469 return 0;
470}
471
472
473/*
474 * Buffer allocation/deallocation routines. The buffer descriptor returned
6aa20a22 475 * has the virtual and dma address of a buffer suitable for
1da177e4
LT
476 * both, receive and transmit operations.
477 */
3441592b 478static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
1da177e4 479{
3441592b 480 struct db_dest *pDB;
1da177e4
LT
481 pDB = aup->pDBfree;
482
ec7eabdd 483 if (pDB)
1da177e4 484 aup->pDBfree = pDB->pnext;
ec7eabdd 485
1da177e4
LT
486 return pDB;
487}
488
3441592b 489void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
1da177e4 490{
3441592b 491 struct db_dest *pDBfree = aup->pDBfree;
1da177e4
LT
492 if (pDBfree)
493 pDBfree->pnext = pDB;
494 aup->pDBfree = pDB;
495}
496
eb049630 497static void au1000_reset_mac_unlocked(struct net_device *dev)
0638dec0 498{
454d7c9b 499 struct au1000_private *const aup = netdev_priv(dev);
0638dec0
HVR
500 int i;
501
eb049630 502 au1000_hard_stop(dev);
0638dec0 503
462ca99c 504 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
0638dec0 505 au_sync_delay(2);
462ca99c 506 writel(0, aup->enable);
0638dec0
HVR
507 au_sync_delay(2);
508
1da177e4
LT
509 aup->tx_full = 0;
510 for (i = 0; i < NUM_RX_DMA; i++) {
511 /* reset control bits */
512 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
513 }
514 for (i = 0; i < NUM_TX_DMA; i++) {
515 /* reset control bits */
516 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
517 }
0638dec0
HVR
518
519 aup->mac_enabled = 0;
520
1da177e4
LT
521}
522
eb049630 523static void au1000_reset_mac(struct net_device *dev)
0638dec0 524{
454d7c9b 525 struct au1000_private *const aup = netdev_priv(dev);
0638dec0
HVR
526 unsigned long flags;
527
5368c726
FF
528 netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
529 (unsigned)aup);
0638dec0
HVR
530
531 spin_lock_irqsave(&aup->lock, flags);
532
ec7eabdd 533 au1000_reset_mac_unlocked(dev);
0638dec0
HVR
534
535 spin_unlock_irqrestore(&aup->lock, flags);
536}
1da177e4 537
6aa20a22 538/*
1da177e4
LT
539 * Setup the receive and transmit "rings". These pointers are the addresses
540 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
541 * these are not descriptors sitting in memory.
542 */
6aa20a22 543static void
553737aa 544au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base)
1da177e4
LT
545{
546 int i;
547
548 for (i = 0; i < NUM_RX_DMA; i++) {
553737aa
ML
549 aup->rx_dma_ring[i] = (struct rx_dma *)
550 (tx_base + 0x100 + sizeof(struct rx_dma) * i);
1da177e4
LT
551 }
552 for (i = 0; i < NUM_TX_DMA; i++) {
553737aa
ML
553 aup->tx_dma_ring[i] = (struct tx_dma *)
554 (tx_base + sizeof(struct tx_dma) * i);
1da177e4
LT
555 }
556}
557
0638dec0
HVR
558/*
559 * ethtool operations
560 */
1da177e4 561
0638dec0 562static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 563{
454d7c9b 564 struct au1000_private *aup = netdev_priv(dev);
1da177e4 565
0638dec0
HVR
566 if (aup->phy_dev)
567 return phy_ethtool_gset(aup->phy_dev, cmd);
1da177e4 568
0638dec0 569 return -EINVAL;
1da177e4
LT
570}
571
0638dec0 572static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 573{
454d7c9b 574 struct au1000_private *aup = netdev_priv(dev);
1da177e4 575
0638dec0
HVR
576 if (!capable(CAP_NET_ADMIN))
577 return -EPERM;
1da177e4 578
0638dec0
HVR
579 if (aup->phy_dev)
580 return phy_ethtool_sset(aup->phy_dev, cmd);
1da177e4 581
0638dec0 582 return -EINVAL;
1da177e4
LT
583}
584
585static void
586au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
587{
454d7c9b 588 struct au1000_private *aup = netdev_priv(dev);
1da177e4 589
7826d43f
JP
590 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
591 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
592 snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME,
593 aup->mac_id);
1da177e4
LT
594 info->regdump_len = 0;
595}
596
7cd2e6e3
FF
597static void au1000_set_msglevel(struct net_device *dev, u32 value)
598{
599 struct au1000_private *aup = netdev_priv(dev);
600 aup->msg_enable = value;
601}
602
603static u32 au1000_get_msglevel(struct net_device *dev)
604{
605 struct au1000_private *aup = netdev_priv(dev);
606 return aup->msg_enable;
607}
608
7282d491 609static const struct ethtool_ops au1000_ethtool_ops = {
1da177e4
LT
610 .get_settings = au1000_get_settings,
611 .set_settings = au1000_set_settings,
612 .get_drvinfo = au1000_get_drvinfo,
0638dec0 613 .get_link = ethtool_op_get_link,
7cd2e6e3
FF
614 .get_msglevel = au1000_get_msglevel,
615 .set_msglevel = au1000_set_msglevel,
1da177e4
LT
616};
617
5ef3041e
FF
618
619/*
620 * Initialize the interface.
621 *
622 * When the device powers up, the clocks are disabled and the
623 * mac is in reset state. When the interface is closed, we
624 * do the same -- reset the device and disable the clocks to
625 * conserve power. Thus, whenever au1000_init() is called,
626 * the device should already be in reset state.
627 */
628static int au1000_init(struct net_device *dev)
1da177e4 629{
5ef3041e
FF
630 struct au1000_private *aup = netdev_priv(dev);
631 unsigned long flags;
632 int i;
633 u32 control;
89be0501 634
5368c726 635 netif_dbg(aup, hw, dev, "au1000_init\n");
1da177e4 636
5ef3041e 637 /* bring the device out of reset */
eb049630 638 au1000_enable_mac(dev, 1);
89be0501 639
5ef3041e 640 spin_lock_irqsave(&aup->lock, flags);
1da177e4 641
d0e7cb5d 642 writel(0, &aup->mac->control);
5ef3041e
FF
643 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
644 aup->tx_tail = aup->tx_head;
645 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
1da177e4 646
d0e7cb5d
FF
647 writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
648 &aup->mac->mac_addr_high);
649 writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
650 dev->dev_addr[1]<<8 | dev->dev_addr[0],
651 &aup->mac->mac_addr_low);
5ef3041e 652
18b8e15b 653
ec7eabdd 654 for (i = 0; i < NUM_RX_DMA; i++)
5ef3041e 655 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
ec7eabdd 656
5ef3041e 657 au_sync();
1da177e4 658
5ef3041e
FF
659 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
660#ifndef CONFIG_CPU_LITTLE_ENDIAN
661 control |= MAC_BIG_ENDIAN;
662#endif
663 if (aup->phy_dev) {
664 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
665 control |= MAC_FULL_DUPLEX;
666 else
667 control |= MAC_DISABLE_RX_OWN;
668 } else { /* PHY-less op, assume full-duplex */
669 control |= MAC_FULL_DUPLEX;
1da177e4
LT
670 }
671
d0e7cb5d
FF
672 writel(control, &aup->mac->control);
673 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
5ef3041e 674 au_sync();
1da177e4 675
5ef3041e
FF
676 spin_unlock_irqrestore(&aup->lock, flags);
677 return 0;
678}
1da177e4 679
eb049630 680static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
5ef3041e 681{
5ef3041e 682 struct net_device_stats *ps = &dev->stats;
1da177e4 683
5ef3041e
FF
684 ps->rx_packets++;
685 if (status & RX_MCAST_FRAME)
686 ps->multicast++;
1da177e4 687
5ef3041e
FF
688 if (status & RX_ERROR) {
689 ps->rx_errors++;
690 if (status & RX_MISSED_FRAME)
691 ps->rx_missed_errors++;
4989ccb2 692 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
5ef3041e
FF
693 ps->rx_length_errors++;
694 if (status & RX_CRC_ERROR)
695 ps->rx_crc_errors++;
696 if (status & RX_COLL)
697 ps->collisions++;
2cc3c6b1 698 } else
5ef3041e 699 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
298cf9be 700
1da177e4
LT
701}
702
6aa20a22 703/*
5ef3041e 704 * Au1000 receive routine.
1da177e4 705 */
5ef3041e 706static int au1000_rx(struct net_device *dev)
1da177e4 707{
454d7c9b 708 struct au1000_private *aup = netdev_priv(dev);
5ef3041e 709 struct sk_buff *skb;
d0e7cb5d 710 struct rx_dma *prxd;
5ef3041e 711 u32 buff_stat, status;
3441592b 712 struct db_dest *pDB;
5ef3041e 713 u32 frmlen;
1da177e4 714
5368c726 715 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
1da177e4 716
5ef3041e
FF
717 prxd = aup->rx_dma_ring[aup->rx_head];
718 buff_stat = prxd->buff_stat;
719 while (buff_stat & RX_T_DONE) {
720 status = prxd->status;
721 pDB = aup->rx_db_inuse[aup->rx_head];
eb049630 722 au1000_update_rx_stats(dev, status);
5ef3041e 723 if (!(status & RX_ERROR)) {
1da177e4 724
5ef3041e
FF
725 /* good frame */
726 frmlen = (status & RX_FRAME_LEN_MASK);
727 frmlen -= 4; /* Remove FCS */
1d266430 728 skb = netdev_alloc_skb(dev, frmlen + 2);
5ef3041e 729 if (skb == NULL) {
5ef3041e
FF
730 dev->stats.rx_dropped++;
731 continue;
732 }
733 skb_reserve(skb, 2); /* 16 byte IP header align */
734 skb_copy_to_linear_data(skb,
735 (unsigned char *)pDB->vaddr, frmlen);
736 skb_put(skb, frmlen);
737 skb->protocol = eth_type_trans(skb, dev);
738 netif_rx(skb); /* pass the packet to upper layers */
2cc3c6b1 739 } else {
5ef3041e 740 if (au1000_debug > 4) {
215e17be 741 pr_err("rx_error(s):");
5ef3041e 742 if (status & RX_MISSED_FRAME)
215e17be 743 pr_cont(" miss");
5ef3041e 744 if (status & RX_WDOG_TIMER)
215e17be 745 pr_cont(" wdog");
5ef3041e 746 if (status & RX_RUNT)
215e17be 747 pr_cont(" runt");
5ef3041e 748 if (status & RX_OVERLEN)
215e17be 749 pr_cont(" overlen");
5ef3041e 750 if (status & RX_COLL)
215e17be 751 pr_cont(" coll");
5ef3041e 752 if (status & RX_MII_ERROR)
215e17be 753 pr_cont(" mii error");
5ef3041e 754 if (status & RX_CRC_ERROR)
215e17be 755 pr_cont(" crc error");
5ef3041e 756 if (status & RX_LEN_ERROR)
215e17be 757 pr_cont(" len error");
5ef3041e 758 if (status & RX_U_CNTRL_FRAME)
215e17be
FF
759 pr_cont(" u control frame");
760 pr_cont("\n");
5ef3041e
FF
761 }
762 }
763 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
764 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
765 au_sync();
1da177e4 766
5ef3041e
FF
767 /* next descriptor */
768 prxd = aup->rx_dma_ring[aup->rx_head];
769 buff_stat = prxd->buff_stat;
1da177e4 770 }
1da177e4
LT
771 return 0;
772}
773
eb049630 774static void au1000_update_tx_stats(struct net_device *dev, u32 status)
1da177e4 775{
454d7c9b 776 struct au1000_private *aup = netdev_priv(dev);
5ef3041e 777 struct net_device_stats *ps = &dev->stats;
0638dec0 778
5ef3041e
FF
779 if (status & TX_FRAME_ABORTED) {
780 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
781 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
782 /* any other tx errors are only valid
dc99839c
FF
783 * in half duplex mode
784 */
5ef3041e
FF
785 ps->tx_errors++;
786 ps->tx_aborted_errors++;
787 }
2cc3c6b1 788 } else {
5ef3041e
FF
789 ps->tx_errors++;
790 ps->tx_aborted_errors++;
791 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
792 ps->tx_carrier_errors++;
793 }
794 }
795}
0638dec0 796
5ef3041e
FF
797/*
798 * Called from the interrupt service routine to acknowledge
799 * the TX DONE bits. This is a must if the irq is setup as
800 * edge triggered.
801 */
802static void au1000_tx_ack(struct net_device *dev)
803{
804 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d 805 struct tx_dma *ptxd;
0638dec0 806
5ef3041e 807 ptxd = aup->tx_dma_ring[aup->tx_tail];
0638dec0 808
5ef3041e 809 while (ptxd->buff_stat & TX_T_DONE) {
eb049630 810 au1000_update_tx_stats(dev, ptxd->status);
5ef3041e
FF
811 ptxd->buff_stat &= ~TX_T_DONE;
812 ptxd->len = 0;
813 au_sync();
0638dec0 814
5ef3041e
FF
815 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
816 ptxd = aup->tx_dma_ring[aup->tx_tail];
0638dec0 817
5ef3041e
FF
818 if (aup->tx_full) {
819 aup->tx_full = 0;
820 netif_wake_queue(dev);
821 }
1da177e4 822 }
5ef3041e 823}
1da177e4 824
5ef3041e
FF
825/*
826 * Au1000 interrupt service routine.
827 */
828static irqreturn_t au1000_interrupt(int irq, void *dev_id)
829{
830 struct net_device *dev = dev_id;
1da177e4 831
5ef3041e
FF
832 /* Handle RX interrupts first to minimize chance of overrun */
833
834 au1000_rx(dev);
835 au1000_tx_ack(dev);
836 return IRQ_RETVAL(1);
1da177e4
LT
837}
838
839static int au1000_open(struct net_device *dev)
840{
841 int retval;
454d7c9b 842 struct au1000_private *aup = netdev_priv(dev);
1da177e4 843
5368c726 844 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
1da177e4 845
2cc3c6b1
FF
846 retval = request_irq(dev->irq, au1000_interrupt, 0,
847 dev->name, dev);
848 if (retval) {
5368c726 849 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
0638dec0
HVR
850 return retval;
851 }
852
2cc3c6b1
FF
853 retval = au1000_init(dev);
854 if (retval) {
5368c726 855 netdev_err(dev, "error in au1000_init\n");
1da177e4
LT
856 free_irq(dev->irq, dev);
857 return retval;
858 }
1da177e4 859
0638dec0
HVR
860 if (aup->phy_dev) {
861 /* cause the PHY state machine to schedule a link state check */
862 aup->phy_dev->state = PHY_CHANGELINK;
863 phy_start(aup->phy_dev);
1da177e4
LT
864 }
865
0638dec0 866 netif_start_queue(dev);
1da177e4 867
5368c726 868 netif_dbg(aup, drv, dev, "open: Initialization done.\n");
1da177e4
LT
869
870 return 0;
871}
872
873static int au1000_close(struct net_device *dev)
874{
0638dec0 875 unsigned long flags;
454d7c9b 876 struct au1000_private *const aup = netdev_priv(dev);
1da177e4 877
5368c726 878 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
1da177e4 879
0638dec0
HVR
880 if (aup->phy_dev)
881 phy_stop(aup->phy_dev);
1da177e4
LT
882
883 spin_lock_irqsave(&aup->lock, flags);
0638dec0 884
ec7eabdd 885 au1000_reset_mac_unlocked(dev);
0638dec0 886
1da177e4
LT
887 /* stop the device */
888 netif_stop_queue(dev);
889
890 /* disable the interrupt */
891 free_irq(dev->irq, dev);
892 spin_unlock_irqrestore(&aup->lock, flags);
893
894 return 0;
895}
896
1da177e4
LT
897/*
898 * Au1000 transmit routine.
899 */
61357325 900static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
1da177e4 901{
454d7c9b 902 struct au1000_private *aup = netdev_priv(dev);
09f75cd7 903 struct net_device_stats *ps = &dev->stats;
d0e7cb5d 904 struct tx_dma *ptxd;
1da177e4 905 u32 buff_stat;
3441592b 906 struct db_dest *pDB;
1da177e4
LT
907 int i;
908
5368c726
FF
909 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
910 (unsigned)aup, skb->len,
1da177e4
LT
911 skb->data, aup->tx_head);
912
913 ptxd = aup->tx_dma_ring[aup->tx_head];
914 buff_stat = ptxd->buff_stat;
915 if (buff_stat & TX_DMA_ENABLE) {
916 /* We've wrapped around and the transmitter is still busy */
917 netif_stop_queue(dev);
918 aup->tx_full = 1;
5b548140 919 return NETDEV_TX_BUSY;
2cc3c6b1 920 } else if (buff_stat & TX_T_DONE) {
eb049630 921 au1000_update_tx_stats(dev, ptxd->status);
1da177e4
LT
922 ptxd->len = 0;
923 }
924
925 if (aup->tx_full) {
926 aup->tx_full = 0;
927 netif_wake_queue(dev);
928 }
929
930 pDB = aup->tx_db_inuse[aup->tx_head];
bd2302c2 931 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
1da177e4 932 if (skb->len < ETH_ZLEN) {
ec7eabdd 933 for (i = skb->len; i < ETH_ZLEN; i++)
1da177e4 934 ((char *)pDB->vaddr)[i] = 0;
ec7eabdd 935
1da177e4 936 ptxd->len = ETH_ZLEN;
2cc3c6b1 937 } else
5ef3041e 938 ptxd->len = skb->len;
1da177e4 939
5ef3041e
FF
940 ps->tx_packets++;
941 ps->tx_bytes += ptxd->len;
1da177e4 942
5ef3041e
FF
943 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
944 au_sync();
945 dev_kfree_skb(skb);
946 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
6ed10654 947 return NETDEV_TX_OK;
1da177e4
LT
948}
949
1da177e4
LT
950/*
951 * The Tx ring has been full longer than the watchdog timeout
952 * value. The transmitter must be hung?
953 */
954static void au1000_tx_timeout(struct net_device *dev)
955{
5368c726 956 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
eb049630 957 au1000_reset_mac(dev);
1da177e4 958 au1000_init(dev);
1ae5dc34 959 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT
960 netif_wake_queue(dev);
961}
962
d9a92cee 963static void au1000_multicast_list(struct net_device *dev)
1da177e4 964{
454d7c9b 965 struct au1000_private *aup = netdev_priv(dev);
d0e7cb5d 966 u32 reg;
1da177e4 967
18b8e15b 968 netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
d0e7cb5d 969 reg = readl(&aup->mac->control);
1da177e4 970 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
d0e7cb5d 971 reg |= MAC_PROMISCUOUS;
1da177e4 972 } else if ((dev->flags & IFF_ALLMULTI) ||
4cd24eaf 973 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
d0e7cb5d
FF
974 reg |= MAC_PASS_ALL_MULTI;
975 reg &= ~MAC_PROMISCUOUS;
5368c726 976 netdev_info(dev, "Pass all multicast\n");
1da177e4 977 } else {
22bedad3 978 struct netdev_hw_addr *ha;
1da177e4
LT
979 u32 mc_filter[2]; /* Multicast hash filter */
980
981 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP
982 netdev_for_each_mc_addr(ha, dev)
983 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1da177e4 984 (long *)mc_filter);
d0e7cb5d
FF
985 writel(mc_filter[1], &aup->mac->multi_hash_high);
986 writel(mc_filter[0], &aup->mac->multi_hash_low);
987 reg &= ~MAC_PROMISCUOUS;
988 reg |= MAC_HASH_MODE;
1da177e4 989 }
d0e7cb5d 990 writel(reg, &aup->mac->control);
1da177e4
LT
991}
992
1da177e4
LT
993static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
994{
454d7c9b 995 struct au1000_private *aup = netdev_priv(dev);
1da177e4 996
2cc3c6b1
FF
997 if (!netif_running(dev))
998 return -EINVAL;
1da177e4 999
2cc3c6b1
FF
1000 if (!aup->phy_dev)
1001 return -EINVAL; /* PHY not controllable */
1da177e4 1002
28b04113 1003 return phy_mii_ioctl(aup->phy_dev, rq, cmd);
1da177e4
LT
1004}
1005
d9a92cee
AB
1006static const struct net_device_ops au1000_netdev_ops = {
1007 .ndo_open = au1000_open,
1008 .ndo_stop = au1000_close,
1009 .ndo_start_xmit = au1000_tx,
afc4b13d 1010 .ndo_set_rx_mode = au1000_multicast_list,
d9a92cee
AB
1011 .ndo_do_ioctl = au1000_ioctl,
1012 .ndo_tx_timeout = au1000_tx_timeout,
1013 .ndo_set_mac_address = eth_mac_addr,
1014 .ndo_validate_addr = eth_validate_addr,
1015 .ndo_change_mtu = eth_change_mtu,
1016};
1017
0cb0568d 1018static int au1000_probe(struct platform_device *pdev)
5ef3041e 1019{
2cc3c6b1 1020 static unsigned version_printed;
5ef3041e 1021 struct au1000_private *aup = NULL;
bd2302c2 1022 struct au1000_eth_platform_data *pd;
5ef3041e 1023 struct net_device *dev = NULL;
3441592b 1024 struct db_dest *pDB, *pDBfree;
bd2302c2 1025 int irq, i, err = 0;
553737aa 1026 struct resource *base, *macen, *macdma;
5ef3041e 1027
bd2302c2
FF
1028 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1029 if (!base) {
5368c726 1030 dev_err(&pdev->dev, "failed to retrieve base register\n");
bd2302c2
FF
1031 err = -ENODEV;
1032 goto out;
1033 }
5ef3041e 1034
bd2302c2
FF
1035 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1036 if (!macen) {
5368c726 1037 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
bd2302c2
FF
1038 err = -ENODEV;
1039 goto out;
1040 }
5ef3041e 1041
bd2302c2
FF
1042 irq = platform_get_irq(pdev, 0);
1043 if (irq < 0) {
5368c726 1044 dev_err(&pdev->dev, "failed to retrieve IRQ\n");
bd2302c2
FF
1045 err = -ENODEV;
1046 goto out;
1047 }
5ef3041e 1048
553737aa
ML
1049 macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1050 if (!macdma) {
1051 dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n");
1052 err = -ENODEV;
1053 goto out;
1054 }
1055
18b8e15b
FF
1056 if (!request_mem_region(base->start, resource_size(base),
1057 pdev->name)) {
5368c726 1058 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
bd2302c2
FF
1059 err = -ENXIO;
1060 goto out;
1061 }
1062
18b8e15b
FF
1063 if (!request_mem_region(macen->start, resource_size(macen),
1064 pdev->name)) {
5368c726 1065 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
bd2302c2
FF
1066 err = -ENXIO;
1067 goto err_request;
1068 }
5ef3041e 1069
553737aa
ML
1070 if (!request_mem_region(macdma->start, resource_size(macdma),
1071 pdev->name)) {
1072 dev_err(&pdev->dev, "failed to request MACDMA memory region\n");
1073 err = -ENXIO;
1074 goto err_macdma;
1075 }
1076
5ef3041e
FF
1077 dev = alloc_etherdev(sizeof(struct au1000_private));
1078 if (!dev) {
bd2302c2
FF
1079 err = -ENOMEM;
1080 goto err_alloc;
5ef3041e
FF
1081 }
1082
bd2302c2
FF
1083 SET_NETDEV_DEV(dev, &pdev->dev);
1084 platform_set_drvdata(pdev, dev);
5ef3041e
FF
1085 aup = netdev_priv(dev);
1086
1087 spin_lock_init(&aup->lock);
18b8e15b
FF
1088 aup->msg_enable = (au1000_debug < 4 ?
1089 AU1000_DEF_MSG_ENABLE : au1000_debug);
5ef3041e 1090
dc99839c
FF
1091 /* Allocate the data buffers
1092 * Snooping works fine with eth on all au1xxx
1093 */
5ef3041e
FF
1094 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1095 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1096 &aup->dma_addr, 0);
1097 if (!aup->vaddr) {
5368c726 1098 dev_err(&pdev->dev, "failed to allocate data buffers\n");
bd2302c2
FF
1099 err = -ENOMEM;
1100 goto err_vaddr;
5ef3041e
FF
1101 }
1102
1103 /* aup->mac is the base address of the MAC's registers */
d0e7cb5d 1104 aup->mac = (struct mac_reg *)
18b8e15b 1105 ioremap_nocache(base->start, resource_size(base));
bd2302c2 1106 if (!aup->mac) {
5368c726 1107 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
bd2302c2
FF
1108 err = -ENXIO;
1109 goto err_remap1;
1110 }
5ef3041e 1111
ec7eabdd 1112 /* Setup some variables for quick register address access */
d0e7cb5d 1113 aup->enable = (u32 *)ioremap_nocache(macen->start,
18b8e15b 1114 resource_size(macen));
bd2302c2 1115 if (!aup->enable) {
5368c726 1116 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
bd2302c2
FF
1117 err = -ENXIO;
1118 goto err_remap2;
1119 }
1120 aup->mac_id = pdev->id;
5ef3041e 1121
553737aa
ML
1122 aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma));
1123 if (!aup->macdma) {
1124 dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n");
1125 err = -ENXIO;
1126 goto err_remap3;
1127 }
1128
1129 au1000_setup_hw_rings(aup, aup->macdma);
5ef3041e 1130
462ca99c 1131 writel(0, aup->enable);
5ef3041e
FF
1132 aup->mac_enabled = 0;
1133
bd2302c2
FF
1134 pd = pdev->dev.platform_data;
1135 if (!pd) {
18b8e15b
FF
1136 dev_info(&pdev->dev, "no platform_data passed,"
1137 " PHY search on MAC0\n");
bd2302c2
FF
1138 aup->phy1_search_mac0 = 1;
1139 } else {
7718f2c2 1140 if (is_valid_ether_addr(pd->mac)) {
f6673653 1141 memcpy(dev->dev_addr, pd->mac, 6);
7718f2c2
DK
1142 } else {
1143 /* Set a random MAC since no valid provided by platform_data. */
1144 eth_hw_addr_random(dev);
1145 }
f6673653 1146
bd2302c2
FF
1147 aup->phy_static_config = pd->phy_static_config;
1148 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1149 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1150 aup->phy_addr = pd->phy_addr;
1151 aup->phy_busid = pd->phy_busid;
1152 aup->phy_irq = pd->phy_irq;
1153 }
1154
1155 if (aup->phy_busid && aup->phy_busid > 0) {
18b8e15b 1156 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
bd2302c2
FF
1157 err = -ENODEV;
1158 goto err_mdiobus_alloc;
1159 }
1160
5ef3041e 1161 aup->mii_bus = mdiobus_alloc();
bd2302c2 1162 if (aup->mii_bus == NULL) {
5368c726 1163 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
bd2302c2
FF
1164 err = -ENOMEM;
1165 goto err_mdiobus_alloc;
1166 }
5ef3041e
FF
1167
1168 aup->mii_bus->priv = dev;
1169 aup->mii_bus->read = au1000_mdiobus_read;
1170 aup->mii_bus->write = au1000_mdiobus_write;
1171 aup->mii_bus->reset = au1000_mdiobus_reset;
1172 aup->mii_bus->name = "au1000_eth_mii";
f74299b6
FF
1173 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1174 pdev->name, aup->mac_id);
5ef3041e 1175 aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
69129920
PST
1176 if (aup->mii_bus->irq == NULL) {
1177 err = -ENOMEM;
dcbfef82 1178 goto err_out;
69129920 1179 }
dcbfef82 1180
2cc3c6b1 1181 for (i = 0; i < PHY_MAX_ADDR; ++i)
5ef3041e 1182 aup->mii_bus->irq[i] = PHY_POLL;
5ef3041e 1183 /* if known, set corresponding PHY IRQs */
bd2302c2
FF
1184 if (aup->phy_static_config)
1185 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1186 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1187
1188 err = mdiobus_register(aup->mii_bus);
1189 if (err) {
5368c726 1190 dev_err(&pdev->dev, "failed to register MDIO bus\n");
bd2302c2
FF
1191 goto err_mdiobus_reg;
1192 }
5ef3041e 1193
69129920
PST
1194 err = au1000_mii_probe(dev);
1195 if (err != 0)
5ef3041e 1196 goto err_out;
5ef3041e
FF
1197
1198 pDBfree = NULL;
1199 /* setup the data buffer descriptors and attach a buffer to each one */
1200 pDB = aup->db;
1201 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1202 pDB->pnext = pDBfree;
1203 pDBfree = pDB;
1204 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1205 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1206 pDB++;
1207 }
1208 aup->pDBfree = pDBfree;
1209
69129920 1210 err = -ENODEV;
5ef3041e 1211 for (i = 0; i < NUM_RX_DMA; i++) {
eb049630 1212 pDB = au1000_GetFreeDB(aup);
ec7eabdd 1213 if (!pDB)
5ef3041e 1214 goto err_out;
ec7eabdd 1215
5ef3041e
FF
1216 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1217 aup->rx_db_inuse[i] = pDB;
1218 }
69129920
PST
1219
1220 err = -ENODEV;
5ef3041e 1221 for (i = 0; i < NUM_TX_DMA; i++) {
eb049630 1222 pDB = au1000_GetFreeDB(aup);
ec7eabdd 1223 if (!pDB)
5ef3041e 1224 goto err_out;
ec7eabdd 1225
5ef3041e
FF
1226 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1227 aup->tx_dma_ring[i]->len = 0;
1228 aup->tx_db_inuse[i] = pDB;
1229 }
1230
bd2302c2
FF
1231 dev->base_addr = base->start;
1232 dev->irq = irq;
1233 dev->netdev_ops = &au1000_netdev_ops;
1234 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
1235 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1236
5ef3041e
FF
1237 /*
1238 * The boot code uses the ethernet controller, so reset it to start
1239 * fresh. au1000_init() expects that the device is in reset state.
1240 */
eb049630 1241 au1000_reset_mac(dev);
5ef3041e 1242
bd2302c2
FF
1243 err = register_netdev(dev);
1244 if (err) {
5368c726 1245 netdev_err(dev, "Cannot register net device, aborting.\n");
bd2302c2
FF
1246 goto err_out;
1247 }
1248
5368c726
FF
1249 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1250 (unsigned long)base->start, irq);
bd2302c2 1251 if (version_printed++ == 0)
215e17be
FF
1252 pr_info("%s version %s %s\n",
1253 DRV_NAME, DRV_VERSION, DRV_AUTHOR);
bd2302c2
FF
1254
1255 return 0;
5ef3041e
FF
1256
1257err_out:
bd2302c2 1258 if (aup->mii_bus != NULL)
5ef3041e 1259 mdiobus_unregister(aup->mii_bus);
5ef3041e
FF
1260
1261 /* here we should have a valid dev plus aup-> register addresses
dc99839c
FF
1262 * so we can reset the mac properly.
1263 */
eb049630 1264 au1000_reset_mac(dev);
5ef3041e
FF
1265
1266 for (i = 0; i < NUM_RX_DMA; i++) {
1267 if (aup->rx_db_inuse[i])
eb049630 1268 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
5ef3041e
FF
1269 }
1270 for (i = 0; i < NUM_TX_DMA; i++) {
1271 if (aup->tx_db_inuse[i])
eb049630 1272 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
5ef3041e 1273 }
bd2302c2
FF
1274err_mdiobus_reg:
1275 mdiobus_free(aup->mii_bus);
1276err_mdiobus_alloc:
553737aa
ML
1277 iounmap(aup->macdma);
1278err_remap3:
bd2302c2
FF
1279 iounmap(aup->enable);
1280err_remap2:
1281 iounmap(aup->mac);
1282err_remap1:
5ef3041e
FF
1283 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1284 (void *)aup->vaddr, aup->dma_addr);
bd2302c2 1285err_vaddr:
5ef3041e 1286 free_netdev(dev);
bd2302c2 1287err_alloc:
553737aa
ML
1288 release_mem_region(macdma->start, resource_size(macdma));
1289err_macdma:
bd2302c2
FF
1290 release_mem_region(macen->start, resource_size(macen));
1291err_request:
1292 release_mem_region(base->start, resource_size(base));
1293out:
1294 return err;
5ef3041e
FF
1295}
1296
0cb0568d 1297static int au1000_remove(struct platform_device *pdev)
5ef3041e 1298{
bd2302c2
FF
1299 struct net_device *dev = platform_get_drvdata(pdev);
1300 struct au1000_private *aup = netdev_priv(dev);
1301 int i;
1302 struct resource *base, *macen;
5ef3041e 1303
bd2302c2
FF
1304 platform_set_drvdata(pdev, NULL);
1305
1306 unregister_netdev(dev);
1307 mdiobus_unregister(aup->mii_bus);
1308 mdiobus_free(aup->mii_bus);
1309
1310 for (i = 0; i < NUM_RX_DMA; i++)
1311 if (aup->rx_db_inuse[i])
eb049630 1312 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
bd2302c2
FF
1313
1314 for (i = 0; i < NUM_TX_DMA; i++)
1315 if (aup->tx_db_inuse[i])
eb049630 1316 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
bd2302c2
FF
1317
1318 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1319 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1320 (void *)aup->vaddr, aup->dma_addr);
1321
553737aa 1322 iounmap(aup->macdma);
bd2302c2
FF
1323 iounmap(aup->mac);
1324 iounmap(aup->enable);
1325
553737aa
ML
1326 base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1327 release_mem_region(base->start, resource_size(base));
1328
bd2302c2
FF
1329 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1330 release_mem_region(base->start, resource_size(base));
1331
1332 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1333 release_mem_region(macen->start, resource_size(macen));
1334
1335 free_netdev(dev);
5ef3041e 1336
5ef3041e
FF
1337 return 0;
1338}
1339
bd2302c2
FF
1340static struct platform_driver au1000_eth_driver = {
1341 .probe = au1000_probe,
0cb0568d 1342 .remove = au1000_remove,
bd2302c2
FF
1343 .driver = {
1344 .name = "au1000-eth",
1345 .owner = THIS_MODULE,
1346 },
1347};
bd2302c2 1348
db62f684 1349module_platform_driver(au1000_eth_driver);
5ef3041e 1350
db62f684 1351MODULE_ALIAS("platform:au1000-eth");