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net: ena: use napi_schedule_irqoff when possible
[linux-block.git] / drivers / net / ethernet / amazon / ena / ena_netdev.c
CommitLineData
1738cd3e
NB		 1/*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35#ifdef CONFIG_RFS_ACCEL
36#include <linux/cpu_rmap.h>
37#endif /* CONFIG_RFS_ACCEL */
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/moduleparam.h>
43#include <linux/numa.h>
44#include <linux/pci.h>
45#include <linux/utsname.h>
46#include <linux/version.h>
47#include <linux/vmalloc.h>
48#include <net/ip.h>
49
50#include "ena_netdev.h"
51#include "ena_pci_id_tbl.h"
52
53static char version[] = DEVICE_NAME " v" DRV_MODULE_VERSION "\n";
54
55MODULE_AUTHOR("Amazon.com, Inc. or its affiliates");
56MODULE_DESCRIPTION(DEVICE_NAME);
57MODULE_LICENSE("GPL");
58MODULE_VERSION(DRV_MODULE_VERSION);
59
60/* Time in jiffies before concluding the transmitter is hung. */
61#define TX_TIMEOUT (5 * HZ)
62
63#define ENA_NAPI_BUDGET 64
64
65#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | \
66 NETIF_MSG_TX_DONE | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR)
67static int debug = -1;
68module_param(debug, int, 0);
69MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71static struct ena_aenq_handlers aenq_handlers;
72
73static struct workqueue_struct *ena_wq;
74
75MODULE_DEVICE_TABLE(pci, ena_pci_tbl);
76
77static int ena_rss_init_default(struct ena_adapter *adapter);
78
79static void ena_tx_timeout(struct net_device *dev)
80{
81 struct ena_adapter *adapter = netdev_priv(dev);
82
3f6159db
NB		 83 /* Change the state of the device to trigger reset
84 * Check that we are not in the middle or a trigger already
85 */
86
87 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
88 return;
89
e2eed0e3 90 adapter->reset_reason = ENA_REGS_RESET_OS_NETDEV_WD;
1738cd3e
NB		 91 u64_stats_update_begin(&adapter->syncp);
92 adapter->dev_stats.tx_timeout++;
93 u64_stats_update_end(&adapter->syncp);
94
95 netif_err(adapter, tx_err, dev, "Transmit time out\n");
1738cd3e
NB		 96}
97
98static void update_rx_ring_mtu(struct ena_adapter *adapter, int mtu)
99{
100 int i;
101
102 for (i = 0; i < adapter->num_queues; i++)
103 adapter->rx_ring[i].mtu = mtu;
104}
105
106static int ena_change_mtu(struct net_device *dev, int new_mtu)
107{
108 struct ena_adapter *adapter = netdev_priv(dev);
109 int ret;
110
1738cd3e
NB		 111 ret = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu);
112 if (!ret) {
113 netif_dbg(adapter, drv, dev, "set MTU to %d\n", new_mtu);
114 update_rx_ring_mtu(adapter, new_mtu);
115 dev->mtu = new_mtu;
116 } else {
117 netif_err(adapter, drv, dev, "Failed to set MTU to %d\n",
118 new_mtu);
119 }
120
121 return ret;
122}
123
124static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter)
125{
126#ifdef CONFIG_RFS_ACCEL
127 u32 i;
128 int rc;
129
130 adapter->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(adapter->num_queues);
131 if (!adapter->netdev->rx_cpu_rmap)
132 return -ENOMEM;
133 for (i = 0; i < adapter->num_queues; i++) {
134 int irq_idx = ENA_IO_IRQ_IDX(i);
135
136 rc = irq_cpu_rmap_add(adapter->netdev->rx_cpu_rmap,
da6f4cf5 137 pci_irq_vector(adapter->pdev, irq_idx));
1738cd3e
NB		 138 if (rc) {
139 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
140 adapter->netdev->rx_cpu_rmap = NULL;
141 return rc;
142 }
143 }
144#endif /* CONFIG_RFS_ACCEL */
145 return 0;
146}
147
148static void ena_init_io_rings_common(struct ena_adapter *adapter,
149 struct ena_ring *ring, u16 qid)
150{
151 ring->qid = qid;
152 ring->pdev = adapter->pdev;
153 ring->dev = &adapter->pdev->dev;
154 ring->netdev = adapter->netdev;
155 ring->napi = &adapter->ena_napi[qid].napi;
156 ring->adapter = adapter;
157 ring->ena_dev = adapter->ena_dev;
158 ring->per_napi_packets = 0;
159 ring->per_napi_bytes = 0;
160 ring->cpu = 0;
161 u64_stats_init(&ring->syncp);
162}
163
164static void ena_init_io_rings(struct ena_adapter *adapter)
165{
166 struct ena_com_dev *ena_dev;
167 struct ena_ring *txr, *rxr;
168 int i;
169
170 ena_dev = adapter->ena_dev;
171
172 for (i = 0; i < adapter->num_queues; i++) {
173 txr = &adapter->tx_ring[i];
174 rxr = &adapter->rx_ring[i];
175
176 /* TX/RX common ring state */
177 ena_init_io_rings_common(adapter, txr, i);
178 ena_init_io_rings_common(adapter, rxr, i);
179
180 /* TX specific ring state */
181 txr->ring_size = adapter->tx_ring_size;
182 txr->tx_max_header_size = ena_dev->tx_max_header_size;
183 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type;
184 txr->sgl_size = adapter->max_tx_sgl_size;
185 txr->smoothed_interval =
186 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev);
187
188 /* RX specific ring state */
189 rxr->ring_size = adapter->rx_ring_size;
190 rxr->rx_copybreak = adapter->rx_copybreak;
191 rxr->sgl_size = adapter->max_rx_sgl_size;
192 rxr->smoothed_interval =
193 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev);
a3af7c18 194 rxr->empty_rx_queue = 0;
1738cd3e
NB		 195 }
196}
197
198/* ena_setup_tx_resources - allocate I/O Tx resources (Descriptors)
199 * @adapter: network interface device structure
200 * @qid: queue index
201 *
202 * Return 0 on success, negative on failure
203 */
204static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid)
205{
206 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
207 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
208 int size, i, node;
209
210 if (tx_ring->tx_buffer_info) {
211 netif_err(adapter, ifup,
212 adapter->netdev, "tx_buffer_info info is not NULL");
213 return -EEXIST;
214 }
215
216 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size;
217 node = cpu_to_node(ena_irq->cpu);
218
219 tx_ring->tx_buffer_info = vzalloc_node(size, node);
220 if (!tx_ring->tx_buffer_info) {
221 tx_ring->tx_buffer_info = vzalloc(size);
222 if (!tx_ring->tx_buffer_info)
223 return -ENOMEM;
224 }
225
226 size = sizeof(u16) * tx_ring->ring_size;
227 tx_ring->free_tx_ids = vzalloc_node(size, node);
228 if (!tx_ring->free_tx_ids) {
229 tx_ring->free_tx_ids = vzalloc(size);
230 if (!tx_ring->free_tx_ids) {
231 vfree(tx_ring->tx_buffer_info);
232 return -ENOMEM;
233 }
234 }
235
236 /* Req id ring for TX out of order completions */
237 for (i = 0; i < tx_ring->ring_size; i++)
238 tx_ring->free_tx_ids[i] = i;
239
240 /* Reset tx statistics */
241 memset(&tx_ring->tx_stats, 0x0, sizeof(tx_ring->tx_stats));
242
243 tx_ring->next_to_use = 0;
244 tx_ring->next_to_clean = 0;
245 tx_ring->cpu = ena_irq->cpu;
246 return 0;
247}
248
249/* ena_free_tx_resources - Free I/O Tx Resources per Queue
250 * @adapter: network interface device structure
251 * @qid: queue index
252 *
253 * Free all transmit software resources
254 */
255static void ena_free_tx_resources(struct ena_adapter *adapter, int qid)
256{
257 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
258
259 vfree(tx_ring->tx_buffer_info);
260 tx_ring->tx_buffer_info = NULL;
261
262 vfree(tx_ring->free_tx_ids);
263 tx_ring->free_tx_ids = NULL;
264}
265
266/* ena_setup_all_tx_resources - allocate I/O Tx queues resources for All queues
267 * @adapter: private structure
268 *
269 * Return 0 on success, negative on failure
270 */
271static int ena_setup_all_tx_resources(struct ena_adapter *adapter)
272{
273 int i, rc = 0;
274
275 for (i = 0; i < adapter->num_queues; i++) {
276 rc = ena_setup_tx_resources(adapter, i);
277 if (rc)
278 goto err_setup_tx;
279 }
280
281 return 0;
282
283err_setup_tx:
284
285 netif_err(adapter, ifup, adapter->netdev,
286 "Tx queue %d: allocation failed\n", i);
287
288 /* rewind the index freeing the rings as we go */
289 while (i--)
290 ena_free_tx_resources(adapter, i);
291 return rc;
292}
293
294/* ena_free_all_io_tx_resources - Free I/O Tx Resources for All Queues
295 * @adapter: board private structure
296 *
297 * Free all transmit software resources
298 */
299static void ena_free_all_io_tx_resources(struct ena_adapter *adapter)
300{
301 int i;
302
303 for (i = 0; i < adapter->num_queues; i++)
304 ena_free_tx_resources(adapter, i);
305}
306
ad974bae
NB		 307static inline int validate_rx_req_id(struct ena_ring *rx_ring, u16 req_id)
308{
309 if (likely(req_id < rx_ring->ring_size))
310 return 0;
311
312 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
313 "Invalid rx req_id: %hu\n", req_id);
314
315 u64_stats_update_begin(&rx_ring->syncp);
316 rx_ring->rx_stats.bad_req_id++;
317 u64_stats_update_end(&rx_ring->syncp);
318
319 /* Trigger device reset */
320 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
321 set_bit(ENA_FLAG_TRIGGER_RESET, &rx_ring->adapter->flags);
322 return -EFAULT;
323}
324
1738cd3e
NB		 325/* ena_setup_rx_resources - allocate I/O Rx resources (Descriptors)
326 * @adapter: network interface device structure
327 * @qid: queue index
328 *
329 * Returns 0 on success, negative on failure
330 */
331static int ena_setup_rx_resources(struct ena_adapter *adapter,
332 u32 qid)
333{
334 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
335 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
ad974bae 336 int size, node, i;
1738cd3e
NB		 337
338 if (rx_ring->rx_buffer_info) {
339 netif_err(adapter, ifup, adapter->netdev,
340 "rx_buffer_info is not NULL");
341 return -EEXIST;
342 }
343
344 /* alloc extra element so in rx path
345 * we can always prefetch rx_info + 1
346 */
347 size = sizeof(struct ena_rx_buffer) * (rx_ring->ring_size + 1);
348 node = cpu_to_node(ena_irq->cpu);
349
350 rx_ring->rx_buffer_info = vzalloc_node(size, node);
351 if (!rx_ring->rx_buffer_info) {
352 rx_ring->rx_buffer_info = vzalloc(size);
353 if (!rx_ring->rx_buffer_info)
354 return -ENOMEM;
355 }
356
ad974bae
NB		 357 size = sizeof(u16) * rx_ring->ring_size;
358 rx_ring->free_rx_ids = vzalloc_node(size, node);
359 if (!rx_ring->free_rx_ids) {
360 rx_ring->free_rx_ids = vzalloc(size);
361 if (!rx_ring->free_rx_ids) {
362 vfree(rx_ring->rx_buffer_info);
363 return -ENOMEM;
364 }
365 }
366
367 /* Req id ring for receiving RX pkts out of order */
368 for (i = 0; i < rx_ring->ring_size; i++)
369 rx_ring->free_rx_ids[i] = i;
370
1738cd3e
NB		 371 /* Reset rx statistics */
372 memset(&rx_ring->rx_stats, 0x0, sizeof(rx_ring->rx_stats));
373
374 rx_ring->next_to_clean = 0;
375 rx_ring->next_to_use = 0;
376 rx_ring->cpu = ena_irq->cpu;
377
378 return 0;
379}
380
381/* ena_free_rx_resources - Free I/O Rx Resources
382 * @adapter: network interface device structure
383 * @qid: queue index
384 *
385 * Free all receive software resources
386 */
387static void ena_free_rx_resources(struct ena_adapter *adapter,
388 u32 qid)
389{
390 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
391
392 vfree(rx_ring->rx_buffer_info);
393 rx_ring->rx_buffer_info = NULL;
ad974bae
NB		 394
395 vfree(rx_ring->free_rx_ids);
396 rx_ring->free_rx_ids = NULL;
1738cd3e
NB		 397}
398
399/* ena_setup_all_rx_resources - allocate I/O Rx queues resources for all queues
400 * @adapter: board private structure
401 *
402 * Return 0 on success, negative on failure
403 */
404static int ena_setup_all_rx_resources(struct ena_adapter *adapter)
405{
406 int i, rc = 0;
407
408 for (i = 0; i < adapter->num_queues; i++) {
409 rc = ena_setup_rx_resources(adapter, i);
410 if (rc)
411 goto err_setup_rx;
412 }
413
414 return 0;
415
416err_setup_rx:
417
418 netif_err(adapter, ifup, adapter->netdev,
419 "Rx queue %d: allocation failed\n", i);
420
421 /* rewind the index freeing the rings as we go */
422 while (i--)
423 ena_free_rx_resources(adapter, i);
424 return rc;
425}
426
427/* ena_free_all_io_rx_resources - Free I/O Rx Resources for All Queues
428 * @adapter: board private structure
429 *
430 * Free all receive software resources
431 */
432static void ena_free_all_io_rx_resources(struct ena_adapter *adapter)
433{
434 int i;
435
436 for (i = 0; i < adapter->num_queues; i++)
437 ena_free_rx_resources(adapter, i);
438}
439
440static inline int ena_alloc_rx_page(struct ena_ring *rx_ring,
441 struct ena_rx_buffer *rx_info, gfp_t gfp)
442{
443 struct ena_com_buf *ena_buf;
444 struct page *page;
445 dma_addr_t dma;
446
447 /* if previous allocated page is not used */
448 if (unlikely(rx_info->page))
449 return 0;
450
451 page = alloc_page(gfp);
452 if (unlikely(!page)) {
453 u64_stats_update_begin(&rx_ring->syncp);
454 rx_ring->rx_stats.page_alloc_fail++;
455 u64_stats_update_end(&rx_ring->syncp);
456 return -ENOMEM;
457 }
458
459 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE,
460 DMA_FROM_DEVICE);
461 if (unlikely(dma_mapping_error(rx_ring->dev, dma))) {
462 u64_stats_update_begin(&rx_ring->syncp);
463 rx_ring->rx_stats.dma_mapping_err++;
464 u64_stats_update_end(&rx_ring->syncp);
465
466 __free_page(page);
467 return -EIO;
468 }
469 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
470 "alloc page %p, rx_info %p\n", page, rx_info);
471
472 rx_info->page = page;
473 rx_info->page_offset = 0;
474 ena_buf = &rx_info->ena_buf;
475 ena_buf->paddr = dma;
476 ena_buf->len = PAGE_SIZE;
477
478 return 0;
479}
480
481static void ena_free_rx_page(struct ena_ring *rx_ring,
482 struct ena_rx_buffer *rx_info)
483{
484 struct page *page = rx_info->page;
485 struct ena_com_buf *ena_buf = &rx_info->ena_buf;
486
487 if (unlikely(!page)) {
488 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
489 "Trying to free unallocated buffer\n");
490 return;
491 }
492
493 dma_unmap_page(rx_ring->dev, ena_buf->paddr, PAGE_SIZE,
494 DMA_FROM_DEVICE);
495
496 __free_page(page);
497 rx_info->page = NULL;
498}
499
500static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num)
501{
ad974bae 502 u16 next_to_use, req_id;
1738cd3e
NB		 503 u32 i;
504 int rc;
505
506 next_to_use = rx_ring->next_to_use;
507
508 for (i = 0; i < num; i++) {
ad974bae
NB		 509 struct ena_rx_buffer *rx_info;
510
511 req_id = rx_ring->free_rx_ids[next_to_use];
512 rc = validate_rx_req_id(rx_ring, req_id);
513 if (unlikely(rc < 0))
514 break;
515
516 rx_info = &rx_ring->rx_buffer_info[req_id];
517
1738cd3e
NB		 518
519 rc = ena_alloc_rx_page(rx_ring, rx_info,
520 __GFP_COLD | GFP_ATOMIC | __GFP_COMP);
521 if (unlikely(rc < 0)) {
522 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
523 "failed to alloc buffer for rx queue %d\n",
524 rx_ring->qid);
525 break;
526 }
527 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq,
528 &rx_info->ena_buf,
ad974bae 529 req_id);
1738cd3e
NB		 530 if (unlikely(rc)) {
531 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
532 "failed to add buffer for rx queue %d\n",
533 rx_ring->qid);
534 break;
535 }
536 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use,
537 rx_ring->ring_size);
538 }
539
540 if (unlikely(i < num)) {
541 u64_stats_update_begin(&rx_ring->syncp);
542 rx_ring->rx_stats.refil_partial++;
543 u64_stats_update_end(&rx_ring->syncp);
544 netdev_warn(rx_ring->netdev,
545 "refilled rx qid %d with only %d buffers (from %d)\n",
546 rx_ring->qid, i, num);
547 }
548
549 if (likely(i)) {
550 /* Add memory barrier to make sure the desc were written before
551 * issue a doorbell
552 */
553 wmb();
554 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq);
555 }
556
557 rx_ring->next_to_use = next_to_use;
558
559 return i;
560}
561
562static void ena_free_rx_bufs(struct ena_adapter *adapter,
563 u32 qid)
564{
565 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
566 u32 i;
567
568 for (i = 0; i < rx_ring->ring_size; i++) {
569 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i];
570
571 if (rx_info->page)
572 ena_free_rx_page(rx_ring, rx_info);
573 }
574}
575
576/* ena_refill_all_rx_bufs - allocate all queues Rx buffers
577 * @adapter: board private structure
578 *
579 */
580static void ena_refill_all_rx_bufs(struct ena_adapter *adapter)
581{
582 struct ena_ring *rx_ring;
583 int i, rc, bufs_num;
584
585 for (i = 0; i < adapter->num_queues; i++) {
586 rx_ring = &adapter->rx_ring[i];
587 bufs_num = rx_ring->ring_size - 1;
588 rc = ena_refill_rx_bufs(rx_ring, bufs_num);
589
590 if (unlikely(rc != bufs_num))
591 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
592 "refilling Queue %d failed. allocated %d buffers from: %d\n",
593 i, rc, bufs_num);
594 }
595}
596
597static void ena_free_all_rx_bufs(struct ena_adapter *adapter)
598{
599 int i;
600
601 for (i = 0; i < adapter->num_queues; i++)
602 ena_free_rx_bufs(adapter, i);
603}
604
605/* ena_free_tx_bufs - Free Tx Buffers per Queue
606 * @tx_ring: TX ring for which buffers be freed
607 */
608static void ena_free_tx_bufs(struct ena_ring *tx_ring)
609{
5add6e4a 610 bool print_once = true;
1738cd3e
NB		 611 u32 i;
612
613 for (i = 0; i < tx_ring->ring_size; i++) {
614 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i];
615 struct ena_com_buf *ena_buf;
616 int nr_frags;
617 int j;
618
619 if (!tx_info->skb)
620 continue;
621
5add6e4a
NB		 622 if (print_once) {
623 netdev_notice(tx_ring->netdev,
624 "free uncompleted tx skb qid %d idx 0x%x\n",
625 tx_ring->qid, i);
626 print_once = false;
627 } else {
628 netdev_dbg(tx_ring->netdev,
629 "free uncompleted tx skb qid %d idx 0x%x\n",
630 tx_ring->qid, i);
631 }
1738cd3e
NB		 632
633 ena_buf = tx_info->bufs;
634 dma_unmap_single(tx_ring->dev,
635 ena_buf->paddr,
636 ena_buf->len,
637 DMA_TO_DEVICE);
638
639 /* unmap remaining mapped pages */
640 nr_frags = tx_info->num_of_bufs - 1;
641 for (j = 0; j < nr_frags; j++) {
642 ena_buf++;
643 dma_unmap_page(tx_ring->dev,
644 ena_buf->paddr,
645 ena_buf->len,
646 DMA_TO_DEVICE);
647 }
648
649 dev_kfree_skb_any(tx_info->skb);
650 }
651 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
652 tx_ring->qid));
653}
654
655static void ena_free_all_tx_bufs(struct ena_adapter *adapter)
656{
657 struct ena_ring *tx_ring;
658 int i;
659
660 for (i = 0; i < adapter->num_queues; i++) {
661 tx_ring = &adapter->tx_ring[i];
662 ena_free_tx_bufs(tx_ring);
663 }
664}
665
666static void ena_destroy_all_tx_queues(struct ena_adapter *adapter)
667{
668 u16 ena_qid;
669 int i;
670
671 for (i = 0; i < adapter->num_queues; i++) {
672 ena_qid = ENA_IO_TXQ_IDX(i);
673 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
674 }
675}
676
677static void ena_destroy_all_rx_queues(struct ena_adapter *adapter)
678{
679 u16 ena_qid;
680 int i;
681
682 for (i = 0; i < adapter->num_queues; i++) {
683 ena_qid = ENA_IO_RXQ_IDX(i);
684 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
685 }
686}
687
688static void ena_destroy_all_io_queues(struct ena_adapter *adapter)
689{
690 ena_destroy_all_tx_queues(adapter);
691 ena_destroy_all_rx_queues(adapter);
692}
693
694static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
695{
696 struct ena_tx_buffer *tx_info = NULL;
697
698 if (likely(req_id < tx_ring->ring_size)) {
699 tx_info = &tx_ring->tx_buffer_info[req_id];
700 if (likely(tx_info->skb))
701 return 0;
702 }
703
704 if (tx_info)
705 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
706 "tx_info doesn't have valid skb\n");
707 else
708 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
709 "Invalid req_id: %hu\n", req_id);
710
711 u64_stats_update_begin(&tx_ring->syncp);
712 tx_ring->tx_stats.bad_req_id++;
713 u64_stats_update_end(&tx_ring->syncp);
714
715 /* Trigger device reset */
e2eed0e3 716 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
1738cd3e
NB		 717 set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags);
718 return -EFAULT;
719}
720
721static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
722{
723 struct netdev_queue *txq;
724 bool above_thresh;
725 u32 tx_bytes = 0;
726 u32 total_done = 0;
727 u16 next_to_clean;
728 u16 req_id;
729 int tx_pkts = 0;
730 int rc;
731
732 next_to_clean = tx_ring->next_to_clean;
733 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->qid);
734
735 while (tx_pkts < budget) {
736 struct ena_tx_buffer *tx_info;
737 struct sk_buff *skb;
738 struct ena_com_buf *ena_buf;
739 int i, nr_frags;
740
741 rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq,
742 &req_id);
743 if (rc)
744 break;
745
746 rc = validate_tx_req_id(tx_ring, req_id);
747 if (rc)
748 break;
749
750 tx_info = &tx_ring->tx_buffer_info[req_id];
751 skb = tx_info->skb;
752
753 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
754 prefetch(&skb->end);
755
756 tx_info->skb = NULL;
757 tx_info->last_jiffies = 0;
758
759 if (likely(tx_info->num_of_bufs != 0)) {
760 ena_buf = tx_info->bufs;
761
762 dma_unmap_single(tx_ring->dev,
763 dma_unmap_addr(ena_buf, paddr),
764 dma_unmap_len(ena_buf, len),
765 DMA_TO_DEVICE);
766
767 /* unmap remaining mapped pages */
768 nr_frags = tx_info->num_of_bufs - 1;
769 for (i = 0; i < nr_frags; i++) {
770 ena_buf++;
771 dma_unmap_page(tx_ring->dev,
772 dma_unmap_addr(ena_buf, paddr),
773 dma_unmap_len(ena_buf, len),
774 DMA_TO_DEVICE);
775 }
776 }
777
778 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
779 "tx_poll: q %d skb %p completed\n", tx_ring->qid,
780 skb);
781
782 tx_bytes += skb->len;
783 dev_kfree_skb(skb);
784 tx_pkts++;
785 total_done += tx_info->tx_descs;
786
787 tx_ring->free_tx_ids[next_to_clean] = req_id;
788 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,
789 tx_ring->ring_size);
790 }
791
792 tx_ring->next_to_clean = next_to_clean;
793 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done);
794 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
795
796 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
797
798 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
799 "tx_poll: q %d done. total pkts: %d\n",
800 tx_ring->qid, tx_pkts);
801
802 /* need to make the rings circular update visible to
803 * ena_start_xmit() before checking for netif_queue_stopped().
804 */
805 smp_mb();
806
807 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
808 ENA_TX_WAKEUP_THRESH;
809 if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) {
810 __netif_tx_lock(txq, smp_processor_id());
811 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
812 ENA_TX_WAKEUP_THRESH;
813 if (netif_tx_queue_stopped(txq) && above_thresh) {
814 netif_tx_wake_queue(txq);
815 u64_stats_update_begin(&tx_ring->syncp);
816 tx_ring->tx_stats.queue_wakeup++;
817 u64_stats_update_end(&tx_ring->syncp);
818 }
819 __netif_tx_unlock(txq);
820 }
821
822 tx_ring->per_napi_bytes += tx_bytes;
823 tx_ring->per_napi_packets += tx_pkts;
824
825 return tx_pkts;
826}
827
828static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,
829 struct ena_com_rx_buf_info *ena_bufs,
830 u32 descs,
831 u16 *next_to_clean)
832{
833 struct sk_buff *skb;
ad974bae
NB		 834 struct ena_rx_buffer *rx_info;
835 u16 len, req_id, buf = 0;
1738cd3e
NB		 836 void *va;
837
ad974bae
NB		 838 len = ena_bufs[buf].len;
839 req_id = ena_bufs[buf].req_id;
840 rx_info = &rx_ring->rx_buffer_info[req_id];
841
1738cd3e
NB		 842 if (unlikely(!rx_info->page)) {
843 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
844 "Page is NULL\n");
845 return NULL;
846 }
847
848 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
849 "rx_info %p page %p\n",
850 rx_info, rx_info->page);
851
852 /* save virt address of first buffer */
853 va = page_address(rx_info->page) + rx_info->page_offset;
854 prefetch(va + NET_IP_ALIGN);
855
856 if (len <= rx_ring->rx_copybreak) {
857 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
858 rx_ring->rx_copybreak);
859 if (unlikely(!skb)) {
860 u64_stats_update_begin(&rx_ring->syncp);
861 rx_ring->rx_stats.skb_alloc_fail++;
862 u64_stats_update_end(&rx_ring->syncp);
863 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
864 "Failed to allocate skb\n");
865 return NULL;
866 }
867
868 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
869 "rx allocated small packet. len %d. data_len %d\n",
870 skb->len, skb->data_len);
871
872 /* sync this buffer for CPU use */
873 dma_sync_single_for_cpu(rx_ring->dev,
874 dma_unmap_addr(&rx_info->ena_buf, paddr),
875 len,
876 DMA_FROM_DEVICE);
877 skb_copy_to_linear_data(skb, va, len);
878 dma_sync_single_for_device(rx_ring->dev,
879 dma_unmap_addr(&rx_info->ena_buf, paddr),
880 len,
881 DMA_FROM_DEVICE);
882
883 skb_put(skb, len);
884 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
885 *next_to_clean = ENA_RX_RING_IDX_ADD(*next_to_clean, descs,
886 rx_ring->ring_size);
887 return skb;
888 }
889
890 skb = napi_get_frags(rx_ring->napi);
891 if (unlikely(!skb)) {
892 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
893 "Failed allocating skb\n");
894 u64_stats_update_begin(&rx_ring->syncp);
895 rx_ring->rx_stats.skb_alloc_fail++;
896 u64_stats_update_end(&rx_ring->syncp);
897 return NULL;
898 }
899
900 do {
901 dma_unmap_page(rx_ring->dev,
902 dma_unmap_addr(&rx_info->ena_buf, paddr),
903 PAGE_SIZE, DMA_FROM_DEVICE);
904
905 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page,
906 rx_info->page_offset, len, PAGE_SIZE);
907
908 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
909 "rx skb updated. len %d. data_len %d\n",
910 skb->len, skb->data_len);
911
912 rx_info->page = NULL;
ad974bae
NB		 913
914 rx_ring->free_rx_ids[*next_to_clean] = req_id;
1738cd3e
NB		 915 *next_to_clean =
916 ENA_RX_RING_IDX_NEXT(*next_to_clean,
917 rx_ring->ring_size);
918 if (likely(--descs == 0))
919 break;
ad974bae
NB		 920
921 buf++;
922 len = ena_bufs[buf].len;
923 req_id = ena_bufs[buf].req_id;
924 rx_info = &rx_ring->rx_buffer_info[req_id];
1738cd3e
NB		 925 } while (1);
926
927 return skb;
928}
929
930/* ena_rx_checksum - indicate in skb if hw indicated a good cksum
931 * @adapter: structure containing adapter specific data
932 * @ena_rx_ctx: received packet context/metadata
933 * @skb: skb currently being received and modified
934 */
935static inline void ena_rx_checksum(struct ena_ring *rx_ring,
936 struct ena_com_rx_ctx *ena_rx_ctx,
937 struct sk_buff *skb)
938{
939 /* Rx csum disabled */
940 if (unlikely(!(rx_ring->netdev->features & NETIF_F_RXCSUM))) {
941 skb->ip_summed = CHECKSUM_NONE;
942 return;
943 }
944
945 /* For fragmented packets the checksum isn't valid */
946 if (ena_rx_ctx->frag) {
947 skb->ip_summed = CHECKSUM_NONE;
948 return;
949 }
950
951 /* if IP and error */
952 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) &&
953 (ena_rx_ctx->l3_csum_err))) {
954 /* ipv4 checksum error */
955 skb->ip_summed = CHECKSUM_NONE;
956 u64_stats_update_begin(&rx_ring->syncp);
957 rx_ring->rx_stats.bad_csum++;
958 u64_stats_update_end(&rx_ring->syncp);
959 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
960 "RX IPv4 header checksum error\n");
961 return;
962 }
963
964 /* if TCP/UDP */
965 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
966 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) {
967 if (unlikely(ena_rx_ctx->l4_csum_err)) {
968 /* TCP/UDP checksum error */
969 u64_stats_update_begin(&rx_ring->syncp);
970 rx_ring->rx_stats.bad_csum++;
971 u64_stats_update_end(&rx_ring->syncp);
972 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
973 "RX L4 checksum error\n");
974 skb->ip_summed = CHECKSUM_NONE;
975 return;
976 }
977
978 skb->ip_summed = CHECKSUM_UNNECESSARY;
979 }
980}
981
982static void ena_set_rx_hash(struct ena_ring *rx_ring,
983 struct ena_com_rx_ctx *ena_rx_ctx,
984 struct sk_buff *skb)
985{
986 enum pkt_hash_types hash_type;
987
988 if (likely(rx_ring->netdev->features & NETIF_F_RXHASH)) {
989 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
990 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)))
991
992 hash_type = PKT_HASH_TYPE_L4;
993 else
994 hash_type = PKT_HASH_TYPE_NONE;
995
996 /* Override hash type if the packet is fragmented */
997 if (ena_rx_ctx->frag)
998 hash_type = PKT_HASH_TYPE_NONE;
999
1000 skb_set_hash(skb, ena_rx_ctx->hash, hash_type);
1001 }
1002}
1003
1004/* ena_clean_rx_irq - Cleanup RX irq
1005 * @rx_ring: RX ring to clean
1006 * @napi: napi handler
1007 * @budget: how many packets driver is allowed to clean
1008 *
1009 * Returns the number of cleaned buffers.
1010 */
1011static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
1012 u32 budget)
1013{
1014 u16 next_to_clean = rx_ring->next_to_clean;
1015 u32 res_budget, work_done;
1016
1017 struct ena_com_rx_ctx ena_rx_ctx;
1018 struct ena_adapter *adapter;
1019 struct sk_buff *skb;
1020 int refill_required;
1021 int refill_threshold;
1022 int rc = 0;
1023 int total_len = 0;
1024 int rx_copybreak_pkt = 0;
ad974bae 1025 int i;
1738cd3e
NB		 1026
1027 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
1028 "%s qid %d\n", __func__, rx_ring->qid);
1029 res_budget = budget;
1030
1031 do {
1032 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1033 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
1034 ena_rx_ctx.descs = 0;
1035 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1036 rx_ring->ena_com_io_sq,
1037 &ena_rx_ctx);
1038 if (unlikely(rc))
1039 goto error;
1040
1041 if (unlikely(ena_rx_ctx.descs == 0))
1042 break;
1043
1044 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
1045 "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",
1046 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
1047 ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
1048
1049 /* allocate skb and fill it */
1050 skb = ena_rx_skb(rx_ring, rx_ring->ena_bufs, ena_rx_ctx.descs,
1051 &next_to_clean);
1052
1053 /* exit if we failed to retrieve a buffer */
1054 if (unlikely(!skb)) {
ad974bae
NB		 1055 for (i = 0; i < ena_rx_ctx.descs; i++) {
1056 rx_ring->free_tx_ids[next_to_clean] =
1057 rx_ring->ena_bufs[i].req_id;
1058 next_to_clean =
1059 ENA_RX_RING_IDX_NEXT(next_to_clean,
1060 rx_ring->ring_size);
1061 }
1738cd3e
NB		 1062 break;
1063 }
1064
1065 ena_rx_checksum(rx_ring, &ena_rx_ctx, skb);
1066
1067 ena_set_rx_hash(rx_ring, &ena_rx_ctx, skb);
1068
1069 skb_record_rx_queue(skb, rx_ring->qid);
1070
1071 if (rx_ring->ena_bufs[0].len <= rx_ring->rx_copybreak) {
1072 total_len += rx_ring->ena_bufs[0].len;
1073 rx_copybreak_pkt++;
1074 napi_gro_receive(napi, skb);
1075 } else {
1076 total_len += skb->len;
1077 napi_gro_frags(napi);
1078 }
1079
1080 res_budget--;
1081 } while (likely(res_budget));
1082
1083 work_done = budget - res_budget;
1084 rx_ring->per_napi_bytes += total_len;
1085 rx_ring->per_napi_packets += work_done;
1086 u64_stats_update_begin(&rx_ring->syncp);
1087 rx_ring->rx_stats.bytes += total_len;
1088 rx_ring->rx_stats.cnt += work_done;
1089 rx_ring->rx_stats.rx_copybreak_pkt += rx_copybreak_pkt;
1090 u64_stats_update_end(&rx_ring->syncp);
1091
1092 rx_ring->next_to_clean = next_to_clean;
1093
1094 refill_required = ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
1095 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER;
1096
1097 /* Optimization, try to batch new rx buffers */
1098 if (refill_required > refill_threshold) {
1099 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
1100 ena_refill_rx_bufs(rx_ring, refill_required);
1101 }
1102
1103 return work_done;
1104
1105error:
1106 adapter = netdev_priv(rx_ring->netdev);
1107
1108 u64_stats_update_begin(&rx_ring->syncp);
1109 rx_ring->rx_stats.bad_desc_num++;
1110 u64_stats_update_end(&rx_ring->syncp);
1111
1112 /* Too many desc from the device. Trigger reset */
e2eed0e3 1113 adapter->reset_reason = ENA_REGS_RESET_TOO_MANY_RX_DESCS;
1738cd3e
NB		 1114 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
1115
1116 return 0;
1117}
1118
1119inline void ena_adjust_intr_moderation(struct ena_ring *rx_ring,
1120 struct ena_ring *tx_ring)
1121{
1122 /* We apply adaptive moderation on Rx path only.
1123 * Tx uses static interrupt moderation.
1124 */
1125 ena_com_calculate_interrupt_delay(rx_ring->ena_dev,
1126 rx_ring->per_napi_packets,
1127 rx_ring->per_napi_bytes,
1128 &rx_ring->smoothed_interval,
1129 &rx_ring->moder_tbl_idx);
1130
1131 /* Reset per napi packets/bytes */
1132 tx_ring->per_napi_packets = 0;
1133 tx_ring->per_napi_bytes = 0;
1134 rx_ring->per_napi_packets = 0;
1135 rx_ring->per_napi_bytes = 0;
1136}
1137
418df30f
NB		 1138static inline void ena_unmask_interrupt(struct ena_ring *tx_ring,
1139 struct ena_ring *rx_ring)
1140{
1141 struct ena_eth_io_intr_reg intr_reg;
1142
1143 /* Update intr register: rx intr delay,
1144 * tx intr delay and interrupt unmask
1145 */
1146 ena_com_update_intr_reg(&intr_reg,
1147 rx_ring->smoothed_interval,
1148 tx_ring->smoothed_interval,
1149 true);
1150
1151 /* It is a shared MSI-X.
1152 * Tx and Rx CQ have pointer to it.
1153 * So we use one of them to reach the intr reg
1154 */
1155 ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg);
1156}
1157
1738cd3e
NB		 1158static inline void ena_update_ring_numa_node(struct ena_ring *tx_ring,
1159 struct ena_ring *rx_ring)
1160{
1161 int cpu = get_cpu();
1162 int numa_node;
1163
1164 /* Check only one ring since the 2 rings are running on the same cpu */
1165 if (likely(tx_ring->cpu == cpu))
1166 goto out;
1167
1168 numa_node = cpu_to_node(cpu);
1169 put_cpu();
1170
1171 if (numa_node != NUMA_NO_NODE) {
1172 ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node);
1173 ena_com_update_numa_node(rx_ring->ena_com_io_cq, numa_node);
1174 }
1175
1176 tx_ring->cpu = cpu;
1177 rx_ring->cpu = cpu;
1178
1179 return;
1180out:
1181 put_cpu();
1182}
1183
1184static int ena_io_poll(struct napi_struct *napi, int budget)
1185{
1186 struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);
1187 struct ena_ring *tx_ring, *rx_ring;
1738cd3e
NB		 1188
1189 u32 tx_work_done;
1190 u32 rx_work_done;
1191 int tx_budget;
1192 int napi_comp_call = 0;
1193 int ret;
1194
1195 tx_ring = ena_napi->tx_ring;
1196 rx_ring = ena_napi->rx_ring;
1197
1198 tx_budget = tx_ring->ring_size / ENA_TX_POLL_BUDGET_DIVIDER;
1199
3f6159db
NB		 1200 if (!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1201 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags)) {
1738cd3e
NB		 1202 napi_complete_done(napi, 0);
1203 return 0;
1204 }
1205
1206 tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget);
1207 rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget);
1208
b1669c9f
NB		 1209 /* If the device is about to reset or down, avoid unmask
1210 * the interrupt and return 0 so NAPI won't reschedule
1211 */
1212 if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1213 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags))) {
1214 napi_complete_done(napi, 0);
1215 ret = 0;
1738cd3e 1216
b1669c9f 1217 } else if ((budget > rx_work_done) && (tx_budget > tx_work_done)) {
1738cd3e 1218 napi_comp_call = 1;
1738cd3e 1219
b1669c9f
NB		 1220 /* Update numa and unmask the interrupt only when schedule
1221 * from the interrupt context (vs from sk_busy_loop)
1738cd3e 1222 */
b1669c9f
NB		 1223 if (napi_complete_done(napi, rx_work_done)) {
1224 /* Tx and Rx share the same interrupt vector */
1225 if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev))
1226 ena_adjust_intr_moderation(rx_ring, tx_ring);
1227
418df30f 1228 ena_unmask_interrupt(tx_ring, rx_ring);
b1669c9f 1229 }
1738cd3e 1230
1738cd3e
NB		 1231 ena_update_ring_numa_node(tx_ring, rx_ring);
1232
1233 ret = rx_work_done;
1234 } else {
1235 ret = budget;
1236 }
1237
1238 u64_stats_update_begin(&tx_ring->syncp);
1239 tx_ring->tx_stats.napi_comp += napi_comp_call;
1240 tx_ring->tx_stats.tx_poll++;
1241 u64_stats_update_end(&tx_ring->syncp);
1242
1243 return ret;
1244}
1245
1246static irqreturn_t ena_intr_msix_mgmnt(int irq, void *data)
1247{
1248 struct ena_adapter *adapter = (struct ena_adapter *)data;
1249
1250 ena_com_admin_q_comp_intr_handler(adapter->ena_dev);
1251
1252 /* Don't call the aenq handler before probe is done */
1253 if (likely(test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)))
1254 ena_com_aenq_intr_handler(adapter->ena_dev, data);
1255
1256 return IRQ_HANDLED;
1257}
1258
1259/* ena_intr_msix_io - MSI-X Interrupt Handler for Tx/Rx
1260 * @irq: interrupt number
1261 * @data: pointer to a network interface private napi device structure
1262 */
1263static irqreturn_t ena_intr_msix_io(int irq, void *data)
1264{
1265 struct ena_napi *ena_napi = data;
1266
e745dafa 1267 napi_schedule_irqoff(&ena_napi->napi);
1738cd3e
NB		 1268
1269 return IRQ_HANDLED;
1270}
1271
06443684
NB		 1272/* Reserve a single MSI-X vector for management (admin + aenq).
1273 * plus reserve one vector for each potential io queue.
1274 * the number of potential io queues is the minimum of what the device
1275 * supports and the number of vCPUs.
1276 */
1738cd3e
NB		 1277static int ena_enable_msix(struct ena_adapter *adapter, int num_queues)
1278{
06443684
NB		 1279 int msix_vecs, irq_cnt;
1280
1281 if (test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) {
1282 netif_err(adapter, probe, adapter->netdev,
1283 "Error, MSI-X is already enabled\n");
1284 return -EPERM;
1285 }
1738cd3e
NB		 1286
1287 /* Reserved the max msix vectors we might need */
1288 msix_vecs = ENA_MAX_MSIX_VEC(num_queues);
1289
1290 netif_dbg(adapter, probe, adapter->netdev,
1291 "trying to enable MSI-X, vectors %d\n", msix_vecs);
1292
06443684
NB		 1293 irq_cnt = pci_alloc_irq_vectors(adapter->pdev, ENA_MIN_MSIX_VEC,
1294 msix_vecs, PCI_IRQ_MSIX);
1295
1296 if (irq_cnt < 0) {
1738cd3e 1297 netif_err(adapter, probe, adapter->netdev,
06443684 1298 "Failed to enable MSI-X. irq_cnt %d\n", irq_cnt);
1738cd3e
NB		 1299 return -ENOSPC;
1300 }
1301
06443684
NB		 1302 if (irq_cnt != msix_vecs) {
1303 netif_notice(adapter, probe, adapter->netdev,
1304 "enable only %d MSI-X (out of %d), reduce the number of queues\n",
1305 irq_cnt, msix_vecs);
1306 adapter->num_queues = irq_cnt - ENA_ADMIN_MSIX_VEC;
1738cd3e
NB		 1307 }
1308
06443684
NB		 1309 if (ena_init_rx_cpu_rmap(adapter))
1310 netif_warn(adapter, probe, adapter->netdev,
1311 "Failed to map IRQs to CPUs\n");
1312
1313 adapter->msix_vecs = irq_cnt;
1314 set_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags);
1738cd3e
NB		 1315
1316 return 0;
1317}
1318
1319static void ena_setup_mgmnt_intr(struct ena_adapter *adapter)
1320{
1321 u32 cpu;
1322
1323 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name,
1324 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s",
1325 pci_name(adapter->pdev));
1326 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler =
1327 ena_intr_msix_mgmnt;
1328 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter;
1329 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector =
da6f4cf5 1330 pci_irq_vector(adapter->pdev, ENA_MGMNT_IRQ_IDX);
1738cd3e
NB		 1331 cpu = cpumask_first(cpu_online_mask);
1332 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].cpu = cpu;
1333 cpumask_set_cpu(cpu,
1334 &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].affinity_hint_mask);
1335}
1336
1337static void ena_setup_io_intr(struct ena_adapter *adapter)
1338{
1339 struct net_device *netdev;
1340 int irq_idx, i, cpu;
1341
1342 netdev = adapter->netdev;
1343
1344 for (i = 0; i < adapter->num_queues; i++) {
1345 irq_idx = ENA_IO_IRQ_IDX(i);
1346 cpu = i % num_online_cpus();
1347
1348 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE,
1349 "%s-Tx-Rx-%d", netdev->name, i);
1350 adapter->irq_tbl[irq_idx].handler = ena_intr_msix_io;
1351 adapter->irq_tbl[irq_idx].data = &adapter->ena_napi[i];
1352 adapter->irq_tbl[irq_idx].vector =
da6f4cf5 1353 pci_irq_vector(adapter->pdev, irq_idx);
1738cd3e
NB		 1354 adapter->irq_tbl[irq_idx].cpu = cpu;
1355
1356 cpumask_set_cpu(cpu,
1357 &adapter->irq_tbl[irq_idx].affinity_hint_mask);
1358 }
1359}
1360
1361static int ena_request_mgmnt_irq(struct ena_adapter *adapter)
1362{
1363 unsigned long flags = 0;
1364 struct ena_irq *irq;
1365 int rc;
1366
1367 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1368 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1369 irq->data);
1370 if (rc) {
1371 netif_err(adapter, probe, adapter->netdev,
1372 "failed to request admin irq\n");
1373 return rc;
1374 }
1375
1376 netif_dbg(adapter, probe, adapter->netdev,
1377 "set affinity hint of mgmnt irq.to 0x%lx (irq vector: %d)\n",
1378 irq->affinity_hint_mask.bits[0], irq->vector);
1379
1380 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1381
1382 return rc;
1383}
1384
1385static int ena_request_io_irq(struct ena_adapter *adapter)
1386{
1387 unsigned long flags = 0;
1388 struct ena_irq *irq;
1389 int rc = 0, i, k;
1390
06443684
NB		 1391 if (!test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) {
1392 netif_err(adapter, ifup, adapter->netdev,
1393 "Failed to request I/O IRQ: MSI-X is not enabled\n");
1394 return -EINVAL;
1395 }
1396
1738cd3e
NB		 1397 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1398 irq = &adapter->irq_tbl[i];
1399 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1400 irq->data);
1401 if (rc) {
1402 netif_err(adapter, ifup, adapter->netdev,
1403 "Failed to request I/O IRQ. index %d rc %d\n",
1404 i, rc);
1405 goto err;
1406 }
1407
1408 netif_dbg(adapter, ifup, adapter->netdev,
1409 "set affinity hint of irq. index %d to 0x%lx (irq vector: %d)\n",
1410 i, irq->affinity_hint_mask.bits[0], irq->vector);
1411
1412 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1413 }
1414
1415 return rc;
1416
1417err:
1418 for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) {
1419 irq = &adapter->irq_tbl[k];
1420 free_irq(irq->vector, irq->data);
1421 }
1422
1423 return rc;
1424}
1425
1426static void ena_free_mgmnt_irq(struct ena_adapter *adapter)
1427{
1428 struct ena_irq *irq;
1429
1430 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1431 synchronize_irq(irq->vector);
1432 irq_set_affinity_hint(irq->vector, NULL);
1433 free_irq(irq->vector, irq->data);
1434}
1435
1436static void ena_free_io_irq(struct ena_adapter *adapter)
1437{
1438 struct ena_irq *irq;
1439 int i;
1440
1441#ifdef CONFIG_RFS_ACCEL
1442 if (adapter->msix_vecs >= 1) {
1443 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
1444 adapter->netdev->rx_cpu_rmap = NULL;
1445 }
1446#endif /* CONFIG_RFS_ACCEL */
1447
1448 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1449 irq = &adapter->irq_tbl[i];
1450 irq_set_affinity_hint(irq->vector, NULL);
1451 free_irq(irq->vector, irq->data);
1452 }
1453}
1454
06443684
NB		 1455static void ena_disable_msix(struct ena_adapter *adapter)
1456{
1457 if (test_and_clear_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags))
1458 pci_free_irq_vectors(adapter->pdev);
1459}
1460
1738cd3e
NB		 1461static void ena_disable_io_intr_sync(struct ena_adapter *adapter)
1462{
1463 int i;
1464
1465 if (!netif_running(adapter->netdev))
1466 return;
1467
1468 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++)
1469 synchronize_irq(adapter->irq_tbl[i].vector);
1470}
1471
1472static void ena_del_napi(struct ena_adapter *adapter)
1473{
1474 int i;
1475
1476 for (i = 0; i < adapter->num_queues; i++)
1477 netif_napi_del(&adapter->ena_napi[i].napi);
1478}
1479
1480static void ena_init_napi(struct ena_adapter *adapter)
1481{
1482 struct ena_napi *napi;
1483 int i;
1484
1485 for (i = 0; i < adapter->num_queues; i++) {
1486 napi = &adapter->ena_napi[i];
1487
1488 netif_napi_add(adapter->netdev,
1489 &adapter->ena_napi[i].napi,
1490 ena_io_poll,
1491 ENA_NAPI_BUDGET);
1492 napi->rx_ring = &adapter->rx_ring[i];
1493 napi->tx_ring = &adapter->tx_ring[i];
1494 napi->qid = i;
1495 }
1496}
1497
1498static void ena_napi_disable_all(struct ena_adapter *adapter)
1499{
1500 int i;
1501
1502 for (i = 0; i < adapter->num_queues; i++)
1503 napi_disable(&adapter->ena_napi[i].napi);
1504}
1505
1506static void ena_napi_enable_all(struct ena_adapter *adapter)
1507{
1508 int i;
1509
1510 for (i = 0; i < adapter->num_queues; i++)
1511 napi_enable(&adapter->ena_napi[i].napi);
1512}
1513
1514static void ena_restore_ethtool_params(struct ena_adapter *adapter)
1515{
1516 adapter->tx_usecs = 0;
1517 adapter->rx_usecs = 0;
1518 adapter->tx_frames = 1;
1519 adapter->rx_frames = 1;
1520}
1521
1522/* Configure the Rx forwarding */
1523static int ena_rss_configure(struct ena_adapter *adapter)
1524{
1525 struct ena_com_dev *ena_dev = adapter->ena_dev;
1526 int rc;
1527
1528 /* In case the RSS table wasn't initialized by probe */
1529 if (!ena_dev->rss.tbl_log_size) {
1530 rc = ena_rss_init_default(adapter);
d1497638 1531 if (rc && (rc != -EOPNOTSUPP)) {
1738cd3e
NB		 1532 netif_err(adapter, ifup, adapter->netdev,
1533 "Failed to init RSS rc: %d\n", rc);
1534 return rc;
1535 }
1536 }
1537
1538 /* Set indirect table */
1539 rc = ena_com_indirect_table_set(ena_dev);
d1497638 1540 if (unlikely(rc && rc != -EOPNOTSUPP))
1738cd3e
NB		 1541 return rc;
1542
1543 /* Configure hash function (if supported) */
1544 rc = ena_com_set_hash_function(ena_dev);
d1497638 1545 if (unlikely(rc && (rc != -EOPNOTSUPP)))
1738cd3e
NB		 1546 return rc;
1547
1548 /* Configure hash inputs (if supported) */
1549 rc = ena_com_set_hash_ctrl(ena_dev);
d1497638 1550 if (unlikely(rc && (rc != -EOPNOTSUPP)))
1738cd3e
NB		 1551 return rc;
1552
1553 return 0;
1554}
1555
1556static int ena_up_complete(struct ena_adapter *adapter)
1557{
1558 int rc, i;
1559
1560 rc = ena_rss_configure(adapter);
1561 if (rc)
1562 return rc;
1563
1564 ena_init_napi(adapter);
1565
1566 ena_change_mtu(adapter->netdev, adapter->netdev->mtu);
1567
1568 ena_refill_all_rx_bufs(adapter);
1569
1570 /* enable transmits */
1571 netif_tx_start_all_queues(adapter->netdev);
1572
1573 ena_restore_ethtool_params(adapter);
1574
1575 ena_napi_enable_all(adapter);
1576
418df30f
NB		 1577 /* Enable completion queues interrupt */
1578 for (i = 0; i < adapter->num_queues; i++)
1579 ena_unmask_interrupt(&adapter->tx_ring[i],
1580 &adapter->rx_ring[i]);
1581
1738cd3e
NB		 1582 /* schedule napi in case we had pending packets
1583 * from the last time we disable napi
1584 */
1585 for (i = 0; i < adapter->num_queues; i++)
1586 napi_schedule(&adapter->ena_napi[i].napi);
1587
1588 return 0;
1589}
1590
1591static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
1592{
1593 struct ena_com_create_io_ctx ctx = { 0 };
1594 struct ena_com_dev *ena_dev;
1595 struct ena_ring *tx_ring;
1596 u32 msix_vector;
1597 u16 ena_qid;
1598 int rc;
1599
1600 ena_dev = adapter->ena_dev;
1601
1602 tx_ring = &adapter->tx_ring[qid];
1603 msix_vector = ENA_IO_IRQ_IDX(qid);
1604 ena_qid = ENA_IO_TXQ_IDX(qid);
1605
1606 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1607 ctx.qid = ena_qid;
1608 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1609 ctx.msix_vector = msix_vector;
1610 ctx.queue_size = adapter->tx_ring_size;
1611 ctx.numa_node = cpu_to_node(tx_ring->cpu);
1612
1613 rc = ena_com_create_io_queue(ena_dev, &ctx);
1614 if (rc) {
1615 netif_err(adapter, ifup, adapter->netdev,
1616 "Failed to create I/O TX queue num %d rc: %d\n",
1617 qid, rc);
1618 return rc;
1619 }
1620
1621 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1622 &tx_ring->ena_com_io_sq,
1623 &tx_ring->ena_com_io_cq);
1624 if (rc) {
1625 netif_err(adapter, ifup, adapter->netdev,
1626 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1627 qid, rc);
1628 ena_com_destroy_io_queue(ena_dev, ena_qid);
2d2c600a 1629 return rc;
1738cd3e
NB		 1630 }
1631
1632 ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node);
1633 return rc;
1634}
1635
1636static int ena_create_all_io_tx_queues(struct ena_adapter *adapter)
1637{
1638 struct ena_com_dev *ena_dev = adapter->ena_dev;
1639 int rc, i;
1640
1641 for (i = 0; i < adapter->num_queues; i++) {
1642 rc = ena_create_io_tx_queue(adapter, i);
1643 if (rc)
1644 goto create_err;
1645 }
1646
1647 return 0;
1648
1649create_err:
1650 while (i--)
1651 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i));
1652
1653 return rc;
1654}
1655
1656static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
1657{
1658 struct ena_com_dev *ena_dev;
1659 struct ena_com_create_io_ctx ctx = { 0 };
1660 struct ena_ring *rx_ring;
1661 u32 msix_vector;
1662 u16 ena_qid;
1663 int rc;
1664
1665 ena_dev = adapter->ena_dev;
1666
1667 rx_ring = &adapter->rx_ring[qid];
1668 msix_vector = ENA_IO_IRQ_IDX(qid);
1669 ena_qid = ENA_IO_RXQ_IDX(qid);
1670
1671 ctx.qid = ena_qid;
1672 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1673 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1674 ctx.msix_vector = msix_vector;
1675 ctx.queue_size = adapter->rx_ring_size;
1676 ctx.numa_node = cpu_to_node(rx_ring->cpu);
1677
1678 rc = ena_com_create_io_queue(ena_dev, &ctx);
1679 if (rc) {
1680 netif_err(adapter, ifup, adapter->netdev,
1681 "Failed to create I/O RX queue num %d rc: %d\n",
1682 qid, rc);
1683 return rc;
1684 }
1685
1686 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1687 &rx_ring->ena_com_io_sq,
1688 &rx_ring->ena_com_io_cq);
1689 if (rc) {
1690 netif_err(adapter, ifup, adapter->netdev,
1691 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1692 qid, rc);
1693 ena_com_destroy_io_queue(ena_dev, ena_qid);
2d2c600a 1694 return rc;
1738cd3e
NB		 1695 }
1696
1697 ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node);
1698
1699 return rc;
1700}
1701
1702static int ena_create_all_io_rx_queues(struct ena_adapter *adapter)
1703{
1704 struct ena_com_dev *ena_dev = adapter->ena_dev;
1705 int rc, i;
1706
1707 for (i = 0; i < adapter->num_queues; i++) {
1708 rc = ena_create_io_rx_queue(adapter, i);
1709 if (rc)
1710 goto create_err;
1711 }
1712
1713 return 0;
1714
1715create_err:
1716 while (i--)
1717 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i));
1718
1719 return rc;
1720}
1721
1722static int ena_up(struct ena_adapter *adapter)
1723{
1724 int rc;
1725
1726 netdev_dbg(adapter->netdev, "%s\n", __func__);
1727
1728 ena_setup_io_intr(adapter);
1729
1730 rc = ena_request_io_irq(adapter);
1731 if (rc)
1732 goto err_req_irq;
1733
1734 /* allocate transmit descriptors */
1735 rc = ena_setup_all_tx_resources(adapter);
1736 if (rc)
1737 goto err_setup_tx;
1738
1739 /* allocate receive descriptors */
1740 rc = ena_setup_all_rx_resources(adapter);
1741 if (rc)
1742 goto err_setup_rx;
1743
1744 /* Create TX queues */
1745 rc = ena_create_all_io_tx_queues(adapter);
1746 if (rc)
1747 goto err_create_tx_queues;
1748
1749 /* Create RX queues */
1750 rc = ena_create_all_io_rx_queues(adapter);
1751 if (rc)
1752 goto err_create_rx_queues;
1753
1754 rc = ena_up_complete(adapter);
1755 if (rc)
1756 goto err_up;
1757
1758 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
1759 netif_carrier_on(adapter->netdev);
1760
1761 u64_stats_update_begin(&adapter->syncp);
1762 adapter->dev_stats.interface_up++;
1763 u64_stats_update_end(&adapter->syncp);
1764
1765 set_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1766
1767 return rc;
1768
1769err_up:
1770 ena_destroy_all_rx_queues(adapter);
1771err_create_rx_queues:
1772 ena_destroy_all_tx_queues(adapter);
1773err_create_tx_queues:
1774 ena_free_all_io_rx_resources(adapter);
1775err_setup_rx:
1776 ena_free_all_io_tx_resources(adapter);
1777err_setup_tx:
1778 ena_free_io_irq(adapter);
1779err_req_irq:
1780
1781 return rc;
1782}
1783
1784static void ena_down(struct ena_adapter *adapter)
1785{
1786 netif_info(adapter, ifdown, adapter->netdev, "%s\n", __func__);
1787
1788 clear_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1789
1790 u64_stats_update_begin(&adapter->syncp);
1791 adapter->dev_stats.interface_down++;
1792 u64_stats_update_end(&adapter->syncp);
1793
1738cd3e
NB		 1794 netif_carrier_off(adapter->netdev);
1795 netif_tx_disable(adapter->netdev);
1796
3f6159db
NB		 1797 /* After this point the napi handler won't enable the tx queue */
1798 ena_napi_disable_all(adapter);
1799
1738cd3e 1800 /* After destroy the queue there won't be any new interrupts */
3f6159db
NB		 1801
1802 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) {
1803 int rc;
1804
e2eed0e3 1805 rc = ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason);
3f6159db
NB		 1806 if (rc)
1807 dev_err(&adapter->pdev->dev, "Device reset failed\n");
1808 }
1809
1738cd3e
NB		 1810 ena_destroy_all_io_queues(adapter);
1811
1812 ena_disable_io_intr_sync(adapter);
1813 ena_free_io_irq(adapter);
1814 ena_del_napi(adapter);
1815
1816 ena_free_all_tx_bufs(adapter);
1817 ena_free_all_rx_bufs(adapter);
1818 ena_free_all_io_tx_resources(adapter);
1819 ena_free_all_io_rx_resources(adapter);
1820}
1821
1822/* ena_open - Called when a network interface is made active
1823 * @netdev: network interface device structure
1824 *
1825 * Returns 0 on success, negative value on failure
1826 *
1827 * The open entry point is called when a network interface is made
1828 * active by the system (IFF_UP). At this point all resources needed
1829 * for transmit and receive operations are allocated, the interrupt
1830 * handler is registered with the OS, the watchdog timer is started,
1831 * and the stack is notified that the interface is ready.
1832 */
1833static int ena_open(struct net_device *netdev)
1834{
1835 struct ena_adapter *adapter = netdev_priv(netdev);
1836 int rc;
1837
1838 /* Notify the stack of the actual queue counts. */
1839 rc = netif_set_real_num_tx_queues(netdev, adapter->num_queues);
1840 if (rc) {
1841 netif_err(adapter, ifup, netdev, "Can't set num tx queues\n");
1842 return rc;
1843 }
1844
1845 rc = netif_set_real_num_rx_queues(netdev, adapter->num_queues);
1846 if (rc) {
1847 netif_err(adapter, ifup, netdev, "Can't set num rx queues\n");
1848 return rc;
1849 }
1850
1851 rc = ena_up(adapter);
1852 if (rc)
1853 return rc;
1854
1855 return rc;
1856}
1857
1858/* ena_close - Disables a network interface
1859 * @netdev: network interface device structure
1860 *
1861 * Returns 0, this is not allowed to fail
1862 *
1863 * The close entry point is called when an interface is de-activated
1864 * by the OS. The hardware is still under the drivers control, but
1865 * needs to be disabled. A global MAC reset is issued to stop the
1866 * hardware, and all transmit and receive resources are freed.
1867 */
1868static int ena_close(struct net_device *netdev)
1869{
1870 struct ena_adapter *adapter = netdev_priv(netdev);
1871
1872 netif_dbg(adapter, ifdown, netdev, "%s\n", __func__);
1873
1874 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
1875 ena_down(adapter);
1876
1877 return 0;
1878}
1879
1880static void ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct sk_buff *skb)
1881{
1882 u32 mss = skb_shinfo(skb)->gso_size;
1883 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
1884 u8 l4_protocol = 0;
1885
1886 if ((skb->ip_summed == CHECKSUM_PARTIAL) || mss) {
1887 ena_tx_ctx->l4_csum_enable = 1;
1888 if (mss) {
1889 ena_tx_ctx->tso_enable = 1;
1890 ena_meta->l4_hdr_len = tcp_hdr(skb)->doff;
1891 ena_tx_ctx->l4_csum_partial = 0;
1892 } else {
1893 ena_tx_ctx->tso_enable = 0;
1894 ena_meta->l4_hdr_len = 0;
1895 ena_tx_ctx->l4_csum_partial = 1;
1896 }
1897
1898 switch (ip_hdr(skb)->version) {
1899 case IPVERSION:
1900 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
1901 if (ip_hdr(skb)->frag_off & htons(IP_DF))
1902 ena_tx_ctx->df = 1;
1903 if (mss)
1904 ena_tx_ctx->l3_csum_enable = 1;
1905 l4_protocol = ip_hdr(skb)->protocol;
1906 break;
1907 case 6:
1908 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
1909 l4_protocol = ipv6_hdr(skb)->nexthdr;
1910 break;
1911 default:
1912 break;
1913 }
1914
1915 if (l4_protocol == IPPROTO_TCP)
1916 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
1917 else
1918 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
1919
1920 ena_meta->mss = mss;
1921 ena_meta->l3_hdr_len = skb_network_header_len(skb);
1922 ena_meta->l3_hdr_offset = skb_network_offset(skb);
1923 ena_tx_ctx->meta_valid = 1;
1924
1925 } else {
1926 ena_tx_ctx->meta_valid = 0;
1927 }
1928}
1929
1930static int ena_check_and_linearize_skb(struct ena_ring *tx_ring,
1931 struct sk_buff *skb)
1932{
1933 int num_frags, header_len, rc;
1934
1935 num_frags = skb_shinfo(skb)->nr_frags;
1936 header_len = skb_headlen(skb);
1937
1938 if (num_frags < tx_ring->sgl_size)
1939 return 0;
1940
1941 if ((num_frags == tx_ring->sgl_size) &&
1942 (header_len < tx_ring->tx_max_header_size))
1943 return 0;
1944
1945 u64_stats_update_begin(&tx_ring->syncp);
1946 tx_ring->tx_stats.linearize++;
1947 u64_stats_update_end(&tx_ring->syncp);
1948
1949 rc = skb_linearize(skb);
1950 if (unlikely(rc)) {
1951 u64_stats_update_begin(&tx_ring->syncp);
1952 tx_ring->tx_stats.linearize_failed++;
1953 u64_stats_update_end(&tx_ring->syncp);
1954 }
1955
1956 return rc;
1957}
1958
1959/* Called with netif_tx_lock. */
1960static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
1961{
1962 struct ena_adapter *adapter = netdev_priv(dev);
1963 struct ena_tx_buffer *tx_info;
1964 struct ena_com_tx_ctx ena_tx_ctx;
1965 struct ena_ring *tx_ring;
1966 struct netdev_queue *txq;
1967 struct ena_com_buf *ena_buf;
1968 void *push_hdr;
1969 u32 len, last_frag;
1970 u16 next_to_use;
1971 u16 req_id;
1972 u16 push_len;
1973 u16 header_len;
1974 dma_addr_t dma;
1975 int qid, rc, nb_hw_desc;
1976 int i = -1;
1977
1978 netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb);
1979 /* Determine which tx ring we will be placed on */
1980 qid = skb_get_queue_mapping(skb);
1981 tx_ring = &adapter->tx_ring[qid];
1982 txq = netdev_get_tx_queue(dev, qid);
1983
1984 rc = ena_check_and_linearize_skb(tx_ring, skb);
1985 if (unlikely(rc))
1986 goto error_drop_packet;
1987
1988 skb_tx_timestamp(skb);
1989 len = skb_headlen(skb);
1990
1991 next_to_use = tx_ring->next_to_use;
1992 req_id = tx_ring->free_tx_ids[next_to_use];
1993 tx_info = &tx_ring->tx_buffer_info[req_id];
1994 tx_info->num_of_bufs = 0;
1995
1996 WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id);
1997 ena_buf = tx_info->bufs;
1998 tx_info->skb = skb;
1999
2000 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2001 /* prepared the push buffer */
2002 push_len = min_t(u32, len, tx_ring->tx_max_header_size);
2003 header_len = push_len;
2004 push_hdr = skb->data;
2005 } else {
2006 push_len = 0;
2007 header_len = min_t(u32, len, tx_ring->tx_max_header_size);
2008 push_hdr = NULL;
2009 }
2010
2011 netif_dbg(adapter, tx_queued, dev,
2012 "skb: %p header_buf->vaddr: %p push_len: %d\n", skb,
2013 push_hdr, push_len);
2014
2015 if (len > push_len) {
2016 dma = dma_map_single(tx_ring->dev, skb->data + push_len,
2017 len - push_len, DMA_TO_DEVICE);
2018 if (dma_mapping_error(tx_ring->dev, dma))
2019 goto error_report_dma_error;
2020
2021 ena_buf->paddr = dma;
2022 ena_buf->len = len - push_len;
2023
2024 ena_buf++;
2025 tx_info->num_of_bufs++;
2026 }
2027
2028 last_frag = skb_shinfo(skb)->nr_frags;
2029
2030 for (i = 0; i < last_frag; i++) {
2031 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2032
2033 len = skb_frag_size(frag);
2034 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len,
2035 DMA_TO_DEVICE);
2036 if (dma_mapping_error(tx_ring->dev, dma))
2037 goto error_report_dma_error;
2038
2039 ena_buf->paddr = dma;
2040 ena_buf->len = len;
2041 ena_buf++;
2042 }
2043
2044 tx_info->num_of_bufs += last_frag;
2045
2046 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2047 ena_tx_ctx.ena_bufs = tx_info->bufs;
2048 ena_tx_ctx.push_header = push_hdr;
2049 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2050 ena_tx_ctx.req_id = req_id;
2051 ena_tx_ctx.header_len = header_len;
2052
2053 /* set flags and meta data */
2054 ena_tx_csum(&ena_tx_ctx, skb);
2055
2056 /* prepare the packet's descriptors to dma engine */
2057 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2058 &nb_hw_desc);
2059
2060 if (unlikely(rc)) {
2061 netif_err(adapter, tx_queued, dev,
2062 "failed to prepare tx bufs\n");
2063 u64_stats_update_begin(&tx_ring->syncp);
2064 tx_ring->tx_stats.queue_stop++;
2065 tx_ring->tx_stats.prepare_ctx_err++;
2066 u64_stats_update_end(&tx_ring->syncp);
2067 netif_tx_stop_queue(txq);
2068 goto error_unmap_dma;
2069 }
2070
2071 netdev_tx_sent_queue(txq, skb->len);
2072
2073 u64_stats_update_begin(&tx_ring->syncp);
2074 tx_ring->tx_stats.cnt++;
2075 tx_ring->tx_stats.bytes += skb->len;
2076 u64_stats_update_end(&tx_ring->syncp);
2077
2078 tx_info->tx_descs = nb_hw_desc;
2079 tx_info->last_jiffies = jiffies;
800c55cb 2080 tx_info->print_once = 0;
1738cd3e
NB		 2081
2082 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use,
2083 tx_ring->ring_size);
2084
2085 /* This WMB is aimed to:
2086 * 1 - perform smp barrier before reading next_to_completion
2087 * 2 - make sure the desc were written before trigger DB
2088 */
2089 wmb();
2090
2091 /* stop the queue when no more space available, the packet can have up
2092 * to sgl_size + 2. one for the meta descriptor and one for header
2093 * (if the header is larger than tx_max_header_size).
2094 */
2095 if (unlikely(ena_com_sq_empty_space(tx_ring->ena_com_io_sq) <
2096 (tx_ring->sgl_size + 2))) {
2097 netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n",
2098 __func__, qid);
2099
2100 netif_tx_stop_queue(txq);
2101 u64_stats_update_begin(&tx_ring->syncp);
2102 tx_ring->tx_stats.queue_stop++;
2103 u64_stats_update_end(&tx_ring->syncp);
2104
2105 /* There is a rare condition where this function decide to
2106 * stop the queue but meanwhile clean_tx_irq updates
2107 * next_to_completion and terminates.
2108 * The queue will remain stopped forever.
2109 * To solve this issue this function perform rmb, check
2110 * the wakeup condition and wake up the queue if needed.
2111 */
2112 smp_rmb();
2113
2114 if (ena_com_sq_empty_space(tx_ring->ena_com_io_sq)
2115 > ENA_TX_WAKEUP_THRESH) {
2116 netif_tx_wake_queue(txq);
2117 u64_stats_update_begin(&tx_ring->syncp);
2118 tx_ring->tx_stats.queue_wakeup++;
2119 u64_stats_update_end(&tx_ring->syncp);
2120 }
2121 }
2122
2123 if (netif_xmit_stopped(txq) || !skb->xmit_more) {
2124 /* trigger the dma engine */
2125 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2126 u64_stats_update_begin(&tx_ring->syncp);
2127 tx_ring->tx_stats.doorbells++;
2128 u64_stats_update_end(&tx_ring->syncp);
2129 }
2130
2131 return NETDEV_TX_OK;
2132
2133error_report_dma_error:
2134 u64_stats_update_begin(&tx_ring->syncp);
2135 tx_ring->tx_stats.dma_mapping_err++;
2136 u64_stats_update_end(&tx_ring->syncp);
2137 netdev_warn(adapter->netdev, "failed to map skb\n");
2138
2139 tx_info->skb = NULL;
2140
2141error_unmap_dma:
2142 if (i >= 0) {
2143 /* save value of frag that failed */
2144 last_frag = i;
2145
2146 /* start back at beginning and unmap skb */
2147 tx_info->skb = NULL;
2148 ena_buf = tx_info->bufs;
2149 dma_unmap_single(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2150 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2151
2152 /* unmap remaining mapped pages */
2153 for (i = 0; i < last_frag; i++) {
2154 ena_buf++;
2155 dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2156 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2157 }
2158 }
2159
2160error_drop_packet:
2161
2162 dev_kfree_skb(skb);
2163 return NETDEV_TX_OK;
2164}
2165
2166#ifdef CONFIG_NET_POLL_CONTROLLER
2167static void ena_netpoll(struct net_device *netdev)
2168{
2169 struct ena_adapter *adapter = netdev_priv(netdev);
2170 int i;
2171
3f6159db
NB		 2172 /* Dont schedule NAPI if the driver is in the middle of reset
2173 * or netdev is down.
2174 */
2175
2176 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags) ||
2177 test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2178 return;
2179
1738cd3e
NB		 2180 for (i = 0; i < adapter->num_queues; i++)
2181 napi_schedule(&adapter->ena_napi[i].napi);
2182}
2183#endif /* CONFIG_NET_POLL_CONTROLLER */
2184
2185static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb,
2186 void *accel_priv, select_queue_fallback_t fallback)
2187{
2188 u16 qid;
2189 /* we suspect that this is good for in--kernel network services that
2190 * want to loop incoming skb rx to tx in normal user generated traffic,
2191 * most probably we will not get to this
2192 */
2193 if (skb_rx_queue_recorded(skb))
2194 qid = skb_get_rx_queue(skb);
2195 else
2196 qid = fallback(dev, skb);
2197
2198 return qid;
2199}
2200
2201static void ena_config_host_info(struct ena_com_dev *ena_dev)
2202{
2203 struct ena_admin_host_info *host_info;
2204 int rc;
2205
2206 /* Allocate only the host info */
2207 rc = ena_com_allocate_host_info(ena_dev);
2208 if (rc) {
2209 pr_err("Cannot allocate host info\n");
2210 return;
2211 }
2212
2213 host_info = ena_dev->host_attr.host_info;
2214
2215 host_info->os_type = ENA_ADMIN_OS_LINUX;
2216 host_info->kernel_ver = LINUX_VERSION_CODE;
2217 strncpy(host_info->kernel_ver_str, utsname()->version,
2218 sizeof(host_info->kernel_ver_str) - 1);
2219 host_info->os_dist = 0;
2220 strncpy(host_info->os_dist_str, utsname()->release,
2221 sizeof(host_info->os_dist_str) - 1);
2222 host_info->driver_version =
2223 (DRV_MODULE_VER_MAJOR) |
2224 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
2225 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
2226
2227 rc = ena_com_set_host_attributes(ena_dev);
2228 if (rc) {
d1497638 2229 if (rc == -EOPNOTSUPP)
1738cd3e
NB		 2230 pr_warn("Cannot set host attributes\n");
2231 else
2232 pr_err("Cannot set host attributes\n");
2233
2234 goto err;
2235 }
2236
2237 return;
2238
2239err:
2240 ena_com_delete_host_info(ena_dev);
2241}
2242
2243static void ena_config_debug_area(struct ena_adapter *adapter)
2244{
2245 u32 debug_area_size;
2246 int rc, ss_count;
2247
2248 ss_count = ena_get_sset_count(adapter->netdev, ETH_SS_STATS);
2249 if (ss_count <= 0) {
2250 netif_err(adapter, drv, adapter->netdev,
2251 "SS count is negative\n");
2252 return;
2253 }
2254
2255 /* allocate 32 bytes for each string and 64bit for the value */
2256 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
2257
2258 rc = ena_com_allocate_debug_area(adapter->ena_dev, debug_area_size);
2259 if (rc) {
2260 pr_err("Cannot allocate debug area\n");
2261 return;
2262 }
2263
2264 rc = ena_com_set_host_attributes(adapter->ena_dev);
2265 if (rc) {
d1497638 2266 if (rc == -EOPNOTSUPP)
1738cd3e
NB		 2267 netif_warn(adapter, drv, adapter->netdev,
2268 "Cannot set host attributes\n");
2269 else
2270 netif_err(adapter, drv, adapter->netdev,
2271 "Cannot set host attributes\n");
2272 goto err;
2273 }
2274
2275 return;
2276err:
2277 ena_com_delete_debug_area(adapter->ena_dev);
2278}
2279
bc1f4470 2280static void ena_get_stats64(struct net_device *netdev,
2281 struct rtnl_link_stats64 *stats)
1738cd3e
NB		 2282{
2283 struct ena_adapter *adapter = netdev_priv(netdev);
d81db240
NB		 2284 struct ena_ring *rx_ring, *tx_ring;
2285 unsigned int start;
2286 u64 rx_drops;
2287 int i;
1738cd3e
NB		 2288
2289 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
bc1f4470 2290 return;
1738cd3e 2291
d81db240
NB		 2292 for (i = 0; i < adapter->num_queues; i++) {
2293 u64 bytes, packets;
2294
2295 tx_ring = &adapter->tx_ring[i];
1738cd3e 2296
d81db240
NB		 2297 do {
2298 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
2299 packets = tx_ring->tx_stats.cnt;
2300 bytes = tx_ring->tx_stats.bytes;
2301 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
1738cd3e 2302
d81db240
NB		 2303 stats->tx_packets += packets;
2304 stats->tx_bytes += bytes;
2305
2306 rx_ring = &adapter->rx_ring[i];
2307
2308 do {
2309 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
2310 packets = rx_ring->rx_stats.cnt;
2311 bytes = rx_ring->rx_stats.bytes;
2312 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
2313
2314 stats->rx_packets += packets;
2315 stats->rx_bytes += bytes;
2316 }
2317
2318 do {
2319 start = u64_stats_fetch_begin_irq(&adapter->syncp);
2320 rx_drops = adapter->dev_stats.rx_drops;
2321 } while (u64_stats_fetch_retry_irq(&adapter->syncp, start));
1738cd3e 2322
d81db240 2323 stats->rx_dropped = rx_drops;
1738cd3e
NB		 2324
2325 stats->multicast = 0;
2326 stats->collisions = 0;
2327
2328 stats->rx_length_errors = 0;
2329 stats->rx_crc_errors = 0;
2330 stats->rx_frame_errors = 0;
2331 stats->rx_fifo_errors = 0;
2332 stats->rx_missed_errors = 0;
2333 stats->tx_window_errors = 0;
2334
2335 stats->rx_errors = 0;
2336 stats->tx_errors = 0;
1738cd3e
NB		 2337}
2338
2339static const struct net_device_ops ena_netdev_ops = {
2340 .ndo_open = ena_open,
2341 .ndo_stop = ena_close,
2342 .ndo_start_xmit = ena_start_xmit,
2343 .ndo_select_queue = ena_select_queue,
2344 .ndo_get_stats64 = ena_get_stats64,
2345 .ndo_tx_timeout = ena_tx_timeout,
2346 .ndo_change_mtu = ena_change_mtu,
2347 .ndo_set_mac_address = NULL,
2348 .ndo_validate_addr = eth_validate_addr,
2349#ifdef CONFIG_NET_POLL_CONTROLLER
2350 .ndo_poll_controller = ena_netpoll,
2351#endif /* CONFIG_NET_POLL_CONTROLLER */
2352};
2353
2354static void ena_device_io_suspend(struct work_struct *work)
2355{
2356 struct ena_adapter *adapter =
2357 container_of(work, struct ena_adapter, suspend_io_task);
2358 struct net_device *netdev = adapter->netdev;
2359
2360 /* ena_napi_disable_all disables only the IO handling.
2361 * We are still subject to AENQ keep alive watchdog.
2362 */
2363 u64_stats_update_begin(&adapter->syncp);
2364 adapter->dev_stats.io_suspend++;
2365 u64_stats_update_begin(&adapter->syncp);
2366 ena_napi_disable_all(adapter);
2367 netif_tx_lock(netdev);
2368 netif_device_detach(netdev);
2369 netif_tx_unlock(netdev);
2370}
2371
2372static void ena_device_io_resume(struct work_struct *work)
2373{
2374 struct ena_adapter *adapter =
2375 container_of(work, struct ena_adapter, resume_io_task);
2376 struct net_device *netdev = adapter->netdev;
2377
2378 u64_stats_update_begin(&adapter->syncp);
2379 adapter->dev_stats.io_resume++;
2380 u64_stats_update_end(&adapter->syncp);
2381
2382 netif_device_attach(netdev);
2383 ena_napi_enable_all(adapter);
2384}
2385
2386static int ena_device_validate_params(struct ena_adapter *adapter,
2387 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2388{
2389 struct net_device *netdev = adapter->netdev;
2390 int rc;
2391
2392 rc = ether_addr_equal(get_feat_ctx->dev_attr.mac_addr,
2393 adapter->mac_addr);
2394 if (!rc) {
2395 netif_err(adapter, drv, netdev,
2396 "Error, mac address are different\n");
2397 return -EINVAL;
2398 }
2399
2400 if ((get_feat_ctx->max_queues.max_cq_num < adapter->num_queues) ||
2401 (get_feat_ctx->max_queues.max_sq_num < adapter->num_queues)) {
2402 netif_err(adapter, drv, netdev,
2403 "Error, device doesn't support enough queues\n");
2404 return -EINVAL;
2405 }
2406
2407 if (get_feat_ctx->dev_attr.max_mtu < netdev->mtu) {
2408 netif_err(adapter, drv, netdev,
2409 "Error, device max mtu is smaller than netdev MTU\n");
2410 return -EINVAL;
2411 }
2412
2413 return 0;
2414}
2415
2416static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
2417 struct ena_com_dev_get_features_ctx *get_feat_ctx,
2418 bool *wd_state)
2419{
2420 struct device *dev = &pdev->dev;
2421 bool readless_supported;
2422 u32 aenq_groups;
2423 int dma_width;
2424 int rc;
2425
2426 rc = ena_com_mmio_reg_read_request_init(ena_dev);
2427 if (rc) {
2428 dev_err(dev, "failed to init mmio read less\n");
2429 return rc;
2430 }
2431
2432 /* The PCIe configuration space revision id indicate if mmio reg
2433 * read is disabled
2434 */
2435 readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ);
2436 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
2437
e2eed0e3 2438 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1738cd3e
NB		 2439 if (rc) {
2440 dev_err(dev, "Can not reset device\n");
2441 goto err_mmio_read_less;
2442 }
2443
2444 rc = ena_com_validate_version(ena_dev);
2445 if (rc) {
2446 dev_err(dev, "device version is too low\n");
2447 goto err_mmio_read_less;
2448 }
2449
2450 dma_width = ena_com_get_dma_width(ena_dev);
2451 if (dma_width < 0) {
2452 dev_err(dev, "Invalid dma width value %d", dma_width);
6e22066f 2453 rc = dma_width;
1738cd3e
NB		 2454 goto err_mmio_read_less;
2455 }
2456
2457 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2458 if (rc) {
2459 dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc);
2460 goto err_mmio_read_less;
2461 }
2462
2463 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2464 if (rc) {
2465 dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n",
2466 rc);
2467 goto err_mmio_read_less;
2468 }
2469
2470 /* ENA admin level init */
2471 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
2472 if (rc) {
2473 dev_err(dev,
2474 "Can not initialize ena admin queue with device\n");
2475 goto err_mmio_read_less;
2476 }
2477
2478 /* To enable the msix interrupts the driver needs to know the number
2479 * of queues. So the driver uses polling mode to retrieve this
2480 * information
2481 */
2482 ena_com_set_admin_polling_mode(ena_dev, true);
2483
dd8427a7
NB		 2484 ena_config_host_info(ena_dev);
2485
1738cd3e
NB		 2486 /* Get Device Attributes*/
2487 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
2488 if (rc) {
2489 dev_err(dev, "Cannot get attribute for ena device rc=%d\n", rc);
2490 goto err_admin_init;
2491 }
2492
2493 /* Try to turn all the available aenq groups */
2494 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
2495 BIT(ENA_ADMIN_FATAL_ERROR) |
2496 BIT(ENA_ADMIN_WARNING) |
2497 BIT(ENA_ADMIN_NOTIFICATION) |
2498 BIT(ENA_ADMIN_KEEP_ALIVE);
2499
2500 aenq_groups &= get_feat_ctx->aenq.supported_groups;
2501
2502 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
2503 if (rc) {
2504 dev_err(dev, "Cannot configure aenq groups rc= %d\n", rc);
2505 goto err_admin_init;
2506 }
2507
2508 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
2509
1738cd3e
NB		 2510 return 0;
2511
2512err_admin_init:
dd8427a7 2513 ena_com_delete_host_info(ena_dev);
1738cd3e
NB		 2514 ena_com_admin_destroy(ena_dev);
2515err_mmio_read_less:
2516 ena_com_mmio_reg_read_request_destroy(ena_dev);
2517
2518 return rc;
2519}
2520
2521static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter,
2522 int io_vectors)
2523{
2524 struct ena_com_dev *ena_dev = adapter->ena_dev;
2525 struct device *dev = &adapter->pdev->dev;
2526 int rc;
2527
2528 rc = ena_enable_msix(adapter, io_vectors);
2529 if (rc) {
2530 dev_err(dev, "Can not reserve msix vectors\n");
2531 return rc;
2532 }
2533
2534 ena_setup_mgmnt_intr(adapter);
2535
2536 rc = ena_request_mgmnt_irq(adapter);
2537 if (rc) {
2538 dev_err(dev, "Can not setup management interrupts\n");
2539 goto err_disable_msix;
2540 }
2541
2542 ena_com_set_admin_polling_mode(ena_dev, false);
2543
2544 ena_com_admin_aenq_enable(ena_dev);
2545
2546 return 0;
2547
2548err_disable_msix:
06443684
NB		 2549 ena_disable_msix(adapter);
2550
1738cd3e
NB		 2551 return rc;
2552}
2553
2554static void ena_fw_reset_device(struct work_struct *work)
2555{
2556 struct ena_com_dev_get_features_ctx get_feat_ctx;
2557 struct ena_adapter *adapter =
2558 container_of(work, struct ena_adapter, reset_task);
2559 struct net_device *netdev = adapter->netdev;
2560 struct ena_com_dev *ena_dev = adapter->ena_dev;
2561 struct pci_dev *pdev = adapter->pdev;
2562 bool dev_up, wd_state;
2563 int rc;
2564
3f6159db
NB		 2565 if (unlikely(!test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2566 dev_err(&pdev->dev,
2567 "device reset schedule while reset bit is off\n");
2568 return;
2569 }
2570
2571 netif_carrier_off(netdev);
2572
1738cd3e
NB		 2573 del_timer_sync(&adapter->timer_service);
2574
2575 rtnl_lock();
2576
2577 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
2578 ena_com_set_admin_running_state(ena_dev, false);
2579
2580 /* After calling ena_close the tx queues and the napi
2581 * are disabled so no one can interfere or touch the
2582 * data structures
2583 */
2584 ena_close(netdev);
2585
1738cd3e
NB		 2586 ena_free_mgmnt_irq(adapter);
2587
06443684 2588 ena_disable_msix(adapter);
1738cd3e
NB		 2589
2590 ena_com_abort_admin_commands(ena_dev);
2591
2592 ena_com_wait_for_abort_completion(ena_dev);
2593
2594 ena_com_admin_destroy(ena_dev);
2595
2596 ena_com_mmio_reg_read_request_destroy(ena_dev);
2597
e2eed0e3 2598 adapter->reset_reason = ENA_REGS_RESET_NORMAL;
3f6159db
NB		 2599 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2600
1738cd3e
NB		 2601 /* Finish with the destroy part. Start the init part */
2602
2603 rc = ena_device_init(ena_dev, adapter->pdev, &get_feat_ctx, &wd_state);
2604 if (rc) {
2605 dev_err(&pdev->dev, "Can not initialize device\n");
2606 goto err;
2607 }
2608 adapter->wd_state = wd_state;
2609
2610 rc = ena_device_validate_params(adapter, &get_feat_ctx);
2611 if (rc) {
2612 dev_err(&pdev->dev, "Validation of device parameters failed\n");
2613 goto err_device_destroy;
2614 }
2615
2616 rc = ena_enable_msix_and_set_admin_interrupts(adapter,
2617 adapter->num_queues);
2618 if (rc) {
2619 dev_err(&pdev->dev, "Enable MSI-X failed\n");
2620 goto err_device_destroy;
2621 }
2622 /* If the interface was up before the reset bring it up */
2623 if (dev_up) {
2624 rc = ena_up(adapter);
2625 if (rc) {
2626 dev_err(&pdev->dev, "Failed to create I/O queues\n");
2627 goto err_disable_msix;
2628 }
2629 }
2630
2631 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
2632
2633 rtnl_unlock();
2634
2635 dev_err(&pdev->dev, "Device reset completed successfully\n");
2636
2637 return;
2638err_disable_msix:
2639 ena_free_mgmnt_irq(adapter);
06443684 2640 ena_disable_msix(adapter);
1738cd3e
NB		 2641err_device_destroy:
2642 ena_com_admin_destroy(ena_dev);
2643err:
2644 rtnl_unlock();
2645
22b331c9
NB		 2646 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
2647
1738cd3e
NB		 2648 dev_err(&pdev->dev,
2649 "Reset attempt failed. Can not reset the device\n");
2650}
2651
800c55cb
NB		 2652static int check_missing_comp_in_queue(struct ena_adapter *adapter,
2653 struct ena_ring *tx_ring)
1738cd3e
NB		 2654{
2655 struct ena_tx_buffer *tx_buf;
2656 unsigned long last_jiffies;
800c55cb
NB		 2657 u32 missed_tx = 0;
2658 int i;
2659
2660 for (i = 0; i < tx_ring->ring_size; i++) {
2661 tx_buf = &tx_ring->tx_buffer_info[i];
2662 last_jiffies = tx_buf->last_jiffies;
2663 if (unlikely(last_jiffies &&
82ef30f1 2664 time_is_before_jiffies(last_jiffies + adapter->missing_tx_completion_to))) {
800c55cb
NB		 2665 if (!tx_buf->print_once)
2666 netif_notice(adapter, tx_err, adapter->netdev,
2667 "Found a Tx that wasn't completed on time, qid %d, index %d.\n",
2668 tx_ring->qid, i);
2669
2670 tx_buf->print_once = 1;
2671 missed_tx++;
2672
82ef30f1 2673 if (unlikely(missed_tx > adapter->missing_tx_completion_threshold)) {
800c55cb
NB		 2674 netif_err(adapter, tx_err, adapter->netdev,
2675 "The number of lost tx completions is above the threshold (%d > %d). Reset the device\n",
82ef30f1
NB		 2676 missed_tx,
2677 adapter->missing_tx_completion_threshold);
e2eed0e3
NB		 2678 adapter->reset_reason =
2679 ENA_REGS_RESET_MISS_TX_CMPL;
800c55cb
NB		 2680 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2681 return -EIO;
2682 }
2683 }
2684 }
2685
2686 return 0;
2687}
2688
2689static void check_for_missing_tx_completions(struct ena_adapter *adapter)
2690{
1738cd3e 2691 struct ena_ring *tx_ring;
800c55cb 2692 int i, budget, rc;
1738cd3e
NB		 2693
2694 /* Make sure the driver doesn't turn the device in other process */
2695 smp_rmb();
2696
2697 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2698 return;
2699
3f6159db
NB		 2700 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2701 return;
2702
82ef30f1
NB		 2703 if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT)
2704 return;
2705
1738cd3e
NB		 2706 budget = ENA_MONITORED_TX_QUEUES;
2707
2708 for (i = adapter->last_monitored_tx_qid; i < adapter->num_queues; i++) {
2709 tx_ring = &adapter->tx_ring[i];
2710
800c55cb
NB		 2711 rc = check_missing_comp_in_queue(adapter, tx_ring);
2712 if (unlikely(rc))
2713 return;
1738cd3e
NB		 2714
2715 budget--;
2716 if (!budget)
2717 break;
2718 }
2719
2720 adapter->last_monitored_tx_qid = i % adapter->num_queues;
2721}
2722
a3af7c18
NB		 2723/* trigger napi schedule after 2 consecutive detections */
2724#define EMPTY_RX_REFILL 2
2725/* For the rare case where the device runs out of Rx descriptors and the
2726 * napi handler failed to refill new Rx descriptors (due to a lack of memory
2727 * for example).
2728 * This case will lead to a deadlock:
2729 * The device won't send interrupts since all the new Rx packets will be dropped
2730 * The napi handler won't allocate new Rx descriptors so the device will be
2731 * able to send new packets.
2732 *
2733 * This scenario can happen when the kernel's vm.min_free_kbytes is too small.
2734 * It is recommended to have at least 512MB, with a minimum of 128MB for
2735 * constrained environment).
2736 *
2737 * When such a situation is detected - Reschedule napi
2738 */
2739static void check_for_empty_rx_ring(struct ena_adapter *adapter)
2740{
2741 struct ena_ring *rx_ring;
2742 int i, refill_required;
2743
2744 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2745 return;
2746
2747 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2748 return;
2749
2750 for (i = 0; i < adapter->num_queues; i++) {
2751 rx_ring = &adapter->rx_ring[i];
2752
2753 refill_required =
2754 ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
2755 if (unlikely(refill_required == (rx_ring->ring_size - 1))) {
2756 rx_ring->empty_rx_queue++;
2757
2758 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) {
2759 u64_stats_update_begin(&rx_ring->syncp);
2760 rx_ring->rx_stats.empty_rx_ring++;
2761 u64_stats_update_end(&rx_ring->syncp);
2762
2763 netif_err(adapter, drv, adapter->netdev,
2764 "trigger refill for ring %d\n", i);
2765
2766 napi_schedule(rx_ring->napi);
2767 rx_ring->empty_rx_queue = 0;
2768 }
2769 } else {
2770 rx_ring->empty_rx_queue = 0;
2771 }
2772 }
2773}
2774
1738cd3e
NB		 2775/* Check for keep alive expiration */
2776static void check_for_missing_keep_alive(struct ena_adapter *adapter)
2777{
2778 unsigned long keep_alive_expired;
2779
2780 if (!adapter->wd_state)
2781 return;
2782
82ef30f1
NB		 2783 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2784 return;
2785
2786 keep_alive_expired = round_jiffies(adapter->last_keep_alive_jiffies +
2787 adapter->keep_alive_timeout);
1738cd3e
NB		 2788 if (unlikely(time_is_before_jiffies(keep_alive_expired))) {
2789 netif_err(adapter, drv, adapter->netdev,
2790 "Keep alive watchdog timeout.\n");
2791 u64_stats_update_begin(&adapter->syncp);
2792 adapter->dev_stats.wd_expired++;
2793 u64_stats_update_end(&adapter->syncp);
e2eed0e3 2794 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1738cd3e
NB		 2795 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2796 }
2797}
2798
2799static void check_for_admin_com_state(struct ena_adapter *adapter)
2800{
2801 if (unlikely(!ena_com_get_admin_running_state(adapter->ena_dev))) {
2802 netif_err(adapter, drv, adapter->netdev,
2803 "ENA admin queue is not in running state!\n");
2804 u64_stats_update_begin(&adapter->syncp);
2805 adapter->dev_stats.admin_q_pause++;
2806 u64_stats_update_end(&adapter->syncp);
e2eed0e3 2807 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1738cd3e
NB		 2808 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2809 }
2810}
2811
82ef30f1
NB		 2812static void ena_update_hints(struct ena_adapter *adapter,
2813 struct ena_admin_ena_hw_hints *hints)
2814{
2815 struct net_device *netdev = adapter->netdev;
2816
2817 if (hints->admin_completion_tx_timeout)
2818 adapter->ena_dev->admin_queue.completion_timeout =
2819 hints->admin_completion_tx_timeout * 1000;
2820
2821 if (hints->mmio_read_timeout)
2822 /* convert to usec */
2823 adapter->ena_dev->mmio_read.reg_read_to =
2824 hints->mmio_read_timeout * 1000;
2825
2826 if (hints->missed_tx_completion_count_threshold_to_reset)
2827 adapter->missing_tx_completion_threshold =
2828 hints->missed_tx_completion_count_threshold_to_reset;
2829
2830 if (hints->missing_tx_completion_timeout) {
2831 if (hints->missing_tx_completion_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2832 adapter->missing_tx_completion_to = ENA_HW_HINTS_NO_TIMEOUT;
2833 else
2834 adapter->missing_tx_completion_to =
2835 msecs_to_jiffies(hints->missing_tx_completion_timeout);
2836 }
2837
2838 if (hints->netdev_wd_timeout)
2839 netdev->watchdog_timeo = msecs_to_jiffies(hints->netdev_wd_timeout);
2840
2841 if (hints->driver_watchdog_timeout) {
2842 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2843 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2844 else
2845 adapter->keep_alive_timeout =
2846 msecs_to_jiffies(hints->driver_watchdog_timeout);
2847 }
2848}
2849
1738cd3e
NB		 2850static void ena_update_host_info(struct ena_admin_host_info *host_info,
2851 struct net_device *netdev)
2852{
2853 host_info->supported_network_features[0] =
2854 netdev->features & GENMASK_ULL(31, 0);
2855 host_info->supported_network_features[1] =
2856 (netdev->features & GENMASK_ULL(63, 32)) >> 32;
2857}
2858
2859static void ena_timer_service(unsigned long data)
2860{
2861 struct ena_adapter *adapter = (struct ena_adapter *)data;
2862 u8 *debug_area = adapter->ena_dev->host_attr.debug_area_virt_addr;
2863 struct ena_admin_host_info *host_info =
2864 adapter->ena_dev->host_attr.host_info;
2865
2866 check_for_missing_keep_alive(adapter);
2867
2868 check_for_admin_com_state(adapter);
2869
2870 check_for_missing_tx_completions(adapter);
2871
a3af7c18
NB		 2872 check_for_empty_rx_ring(adapter);
2873
1738cd3e
NB		 2874 if (debug_area)
2875 ena_dump_stats_to_buf(adapter, debug_area);
2876
2877 if (host_info)
2878 ena_update_host_info(host_info, adapter->netdev);
2879
3f6159db 2880 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
1738cd3e
NB		 2881 netif_err(adapter, drv, adapter->netdev,
2882 "Trigger reset is on\n");
2883 ena_dump_stats_to_dmesg(adapter);
2884 queue_work(ena_wq, &adapter->reset_task);
2885 return;
2886 }
2887
2888 /* Reset the timer */
2889 mod_timer(&adapter->timer_service, jiffies + HZ);
2890}
2891
2892static int ena_calc_io_queue_num(struct pci_dev *pdev,
2893 struct ena_com_dev *ena_dev,
2894 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2895{
2896 int io_sq_num, io_queue_num;
2897
2898 /* In case of LLQ use the llq number in the get feature cmd */
2899 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2900 io_sq_num = get_feat_ctx->max_queues.max_llq_num;
2901
2902 if (io_sq_num == 0) {
2903 dev_err(&pdev->dev,
2904 "Trying to use LLQ but llq_num is 0. Fall back into regular queues\n");
2905
2906 ena_dev->tx_mem_queue_type =
2907 ENA_ADMIN_PLACEMENT_POLICY_HOST;
2908 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2909 }
2910 } else {
2911 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2912 }
2913
6a1ce2fb 2914 io_queue_num = min_t(int, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES);
1738cd3e
NB		 2915 io_queue_num = min_t(int, io_queue_num, io_sq_num);
2916 io_queue_num = min_t(int, io_queue_num,
2917 get_feat_ctx->max_queues.max_cq_num);
2918 /* 1 IRQ for for mgmnt and 1 IRQs for each IO direction */
2919 io_queue_num = min_t(int, io_queue_num, pci_msix_vec_count(pdev) - 1);
2920 if (unlikely(!io_queue_num)) {
2921 dev_err(&pdev->dev, "The device doesn't have io queues\n");
2922 return -EFAULT;
2923 }
2924
2925 return io_queue_num;
2926}
2927
184b49c8
RR		 2928static void ena_set_push_mode(struct pci_dev *pdev, struct ena_com_dev *ena_dev,
2929 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1738cd3e
NB		 2930{
2931 bool has_mem_bar;
2932
2933 has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR);
2934
2935 /* Enable push mode if device supports LLQ */
2936 if (has_mem_bar && (get_feat_ctx->max_queues.max_llq_num > 0))
2937 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2938 else
2939 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1738cd3e
NB		 2940}
2941
2942static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat,
2943 struct net_device *netdev)
2944{
2945 netdev_features_t dev_features = 0;
2946
2947 /* Set offload features */
2948 if (feat->offload.tx &
2949 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2950 dev_features |= NETIF_F_IP_CSUM;
2951
2952 if (feat->offload.tx &
2953 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
2954 dev_features |= NETIF_F_IPV6_CSUM;
2955
2956 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2957 dev_features |= NETIF_F_TSO;
2958
2959 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK)
2960 dev_features |= NETIF_F_TSO6;
2961
2962 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK)
2963 dev_features |= NETIF_F_TSO_ECN;
2964
2965 if (feat->offload.rx_supported &
2966 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2967 dev_features |= NETIF_F_RXCSUM;
2968
2969 if (feat->offload.rx_supported &
2970 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
2971 dev_features |= NETIF_F_RXCSUM;
2972
2973 netdev->features =
2974 dev_features |
2975 NETIF_F_SG |
1738cd3e
NB		 2976 NETIF_F_RXHASH |
2977 NETIF_F_HIGHDMA;
2978
2979 netdev->hw_features |= netdev->features;
2980 netdev->vlan_features |= netdev->features;
2981}
2982
2983static void ena_set_conf_feat_params(struct ena_adapter *adapter,
2984 struct ena_com_dev_get_features_ctx *feat)
2985{
2986 struct net_device *netdev = adapter->netdev;
2987
2988 /* Copy mac address */
2989 if (!is_valid_ether_addr(feat->dev_attr.mac_addr)) {
2990 eth_hw_addr_random(netdev);
2991 ether_addr_copy(adapter->mac_addr, netdev->dev_addr);
2992 } else {
2993 ether_addr_copy(adapter->mac_addr, feat->dev_attr.mac_addr);
2994 ether_addr_copy(netdev->dev_addr, adapter->mac_addr);
2995 }
2996
2997 /* Set offload features */
2998 ena_set_dev_offloads(feat, netdev);
2999
3000 adapter->max_mtu = feat->dev_attr.max_mtu;
d894be57
JW		 3001 netdev->max_mtu = adapter->max_mtu;
3002 netdev->min_mtu = ENA_MIN_MTU;
1738cd3e
NB		 3003}
3004
3005static int ena_rss_init_default(struct ena_adapter *adapter)
3006{
3007 struct ena_com_dev *ena_dev = adapter->ena_dev;
3008 struct device *dev = &adapter->pdev->dev;
3009 int rc, i;
3010 u32 val;
3011
3012 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
3013 if (unlikely(rc)) {
3014 dev_err(dev, "Cannot init indirect table\n");
3015 goto err_rss_init;
3016 }
3017
3018 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
3019 val = ethtool_rxfh_indir_default(i, adapter->num_queues);
3020 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
3021 ENA_IO_RXQ_IDX(val));
d1497638 3022 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
1738cd3e
NB		 3023 dev_err(dev, "Cannot fill indirect table\n");
3024 goto err_fill_indir;
3025 }
3026 }
3027
3028 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
3029 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
d1497638 3030 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
1738cd3e
NB		 3031 dev_err(dev, "Cannot fill hash function\n");
3032 goto err_fill_indir;
3033 }
3034
3035 rc = ena_com_set_default_hash_ctrl(ena_dev);
d1497638 3036 if (unlikely(rc && (rc != -EOPNOTSUPP))) {
1738cd3e
NB		 3037 dev_err(dev, "Cannot fill hash control\n");
3038 goto err_fill_indir;
3039 }
3040
3041 return 0;
3042
3043err_fill_indir:
3044 ena_com_rss_destroy(ena_dev);
3045err_rss_init:
3046
3047 return rc;
3048}
3049
3050static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev)
3051{
3052 int release_bars;
3053
0857d92f
NB		 3054 if (ena_dev->mem_bar)
3055 devm_iounmap(&pdev->dev, ena_dev->mem_bar);
3056
3057 devm_iounmap(&pdev->dev, ena_dev->reg_bar);
3058
1738cd3e
NB		 3059 release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
3060 pci_release_selected_regions(pdev, release_bars);
3061}
3062
3063static int ena_calc_queue_size(struct pci_dev *pdev,
3064 struct ena_com_dev *ena_dev,
3065 u16 *max_tx_sgl_size,
3066 u16 *max_rx_sgl_size,
3067 struct ena_com_dev_get_features_ctx *get_feat_ctx)
3068{
3069 u32 queue_size = ENA_DEFAULT_RING_SIZE;
3070
3071 queue_size = min_t(u32, queue_size,
3072 get_feat_ctx->max_queues.max_cq_depth);
3073 queue_size = min_t(u32, queue_size,
3074 get_feat_ctx->max_queues.max_sq_depth);
3075
3076 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
3077 queue_size = min_t(u32, queue_size,
3078 get_feat_ctx->max_queues.max_llq_depth);
3079
3080 queue_size = rounddown_pow_of_two(queue_size);
3081
3082 if (unlikely(!queue_size)) {
3083 dev_err(&pdev->dev, "Invalid queue size\n");
3084 return -EFAULT;
3085 }
3086
3087 *max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3088 get_feat_ctx->max_queues.max_packet_tx_descs);
3089 *max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
3090 get_feat_ctx->max_queues.max_packet_rx_descs);
3091
3092 return queue_size;
3093}
3094
3095/* ena_probe - Device Initialization Routine
3096 * @pdev: PCI device information struct
3097 * @ent: entry in ena_pci_tbl
3098 *
3099 * Returns 0 on success, negative on failure
3100 *
3101 * ena_probe initializes an adapter identified by a pci_dev structure.
3102 * The OS initialization, configuring of the adapter private structure,
3103 * and a hardware reset occur.
3104 */
3105static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3106{
3107 struct ena_com_dev_get_features_ctx get_feat_ctx;
3108 static int version_printed;
3109 struct net_device *netdev;
3110 struct ena_adapter *adapter;
3111 struct ena_com_dev *ena_dev = NULL;
3112 static int adapters_found;
3113 int io_queue_num, bars, rc;
3114 int queue_size;
3115 u16 tx_sgl_size = 0;
3116 u16 rx_sgl_size = 0;
3117 bool wd_state;
3118
3119 dev_dbg(&pdev->dev, "%s\n", __func__);
3120
3121 if (version_printed++ == 0)
3122 dev_info(&pdev->dev, "%s", version);
3123
3124 rc = pci_enable_device_mem(pdev);
3125 if (rc) {
3126 dev_err(&pdev->dev, "pci_enable_device_mem() failed!\n");
3127 return rc;
3128 }
3129
3130 pci_set_master(pdev);
3131
3132 ena_dev = vzalloc(sizeof(*ena_dev));
3133 if (!ena_dev) {
3134 rc = -ENOMEM;
3135 goto err_disable_device;
3136 }
3137
3138 bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
3139 rc = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME);
3140 if (rc) {
3141 dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n",
3142 rc);
3143 goto err_free_ena_dev;
3144 }
3145
0857d92f
NB		 3146 ena_dev->reg_bar = devm_ioremap(&pdev->dev,
3147 pci_resource_start(pdev, ENA_REG_BAR),
3148 pci_resource_len(pdev, ENA_REG_BAR));
1738cd3e
NB		 3149 if (!ena_dev->reg_bar) {
3150 dev_err(&pdev->dev, "failed to remap regs bar\n");
3151 rc = -EFAULT;
3152 goto err_free_region;
3153 }
3154
3155 ena_dev->dmadev = &pdev->dev;
3156
3157 rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state);
3158 if (rc) {
3159 dev_err(&pdev->dev, "ena device init failed\n");
3160 if (rc == -ETIME)
3161 rc = -EPROBE_DEFER;
3162 goto err_free_region;
3163 }
3164
184b49c8 3165 ena_set_push_mode(pdev, ena_dev, &get_feat_ctx);
1738cd3e
NB		 3166
3167 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
0857d92f
NB		 3168 ena_dev->mem_bar = devm_ioremap_wc(&pdev->dev,
3169 pci_resource_start(pdev, ENA_MEM_BAR),
3170 pci_resource_len(pdev, ENA_MEM_BAR));
1738cd3e
NB		 3171 if (!ena_dev->mem_bar) {
3172 rc = -EFAULT;
3173 goto err_device_destroy;
3174 }
3175 }
3176
3177 /* initial Tx interrupt delay, Assumes 1 usec granularity.
3178 * Updated during device initialization with the real granularity
3179 */
3180 ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS;
3181 io_queue_num = ena_calc_io_queue_num(pdev, ena_dev, &get_feat_ctx);
3182 queue_size = ena_calc_queue_size(pdev, ena_dev, &tx_sgl_size,
3183 &rx_sgl_size, &get_feat_ctx);
3184 if ((queue_size <= 0) || (io_queue_num <= 0)) {
3185 rc = -EFAULT;
3186 goto err_device_destroy;
3187 }
3188
3189 dev_info(&pdev->dev, "creating %d io queues. queue size: %d\n",
3190 io_queue_num, queue_size);
3191
3192 /* dev zeroed in init_etherdev */
3193 netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), io_queue_num);
3194 if (!netdev) {
3195 dev_err(&pdev->dev, "alloc_etherdev_mq failed\n");
3196 rc = -ENOMEM;
3197 goto err_device_destroy;
3198 }
3199
3200 SET_NETDEV_DEV(netdev, &pdev->dev);
3201
3202 adapter = netdev_priv(netdev);
3203 pci_set_drvdata(pdev, adapter);
3204
3205 adapter->ena_dev = ena_dev;
3206 adapter->netdev = netdev;
3207 adapter->pdev = pdev;
3208
3209 ena_set_conf_feat_params(adapter, &get_feat_ctx);
3210
3211 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
e2eed0e3 3212 adapter->reset_reason = ENA_REGS_RESET_NORMAL;
1738cd3e
NB		 3213
3214 adapter->tx_ring_size = queue_size;
3215 adapter->rx_ring_size = queue_size;
3216
3217 adapter->max_tx_sgl_size = tx_sgl_size;
3218 adapter->max_rx_sgl_size = rx_sgl_size;
3219
3220 adapter->num_queues = io_queue_num;
3221 adapter->last_monitored_tx_qid = 0;
3222
3223 adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK;
3224 adapter->wd_state = wd_state;
3225
3226 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapters_found);
3227
3228 rc = ena_com_init_interrupt_moderation(adapter->ena_dev);
3229 if (rc) {
3230 dev_err(&pdev->dev,
3231 "Failed to query interrupt moderation feature\n");
3232 goto err_netdev_destroy;
3233 }
3234 ena_init_io_rings(adapter);
3235
3236 netdev->netdev_ops = &ena_netdev_ops;
3237 netdev->watchdog_timeo = TX_TIMEOUT;
3238 ena_set_ethtool_ops(netdev);
3239
3240 netdev->priv_flags |= IFF_UNICAST_FLT;
3241
3242 u64_stats_init(&adapter->syncp);
3243
3244 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num);
3245 if (rc) {
3246 dev_err(&pdev->dev,
3247 "Failed to enable and set the admin interrupts\n");
3248 goto err_worker_destroy;
3249 }
3250 rc = ena_rss_init_default(adapter);
d1497638 3251 if (rc && (rc != -EOPNOTSUPP)) {
1738cd3e
NB		 3252 dev_err(&pdev->dev, "Cannot init RSS rc: %d\n", rc);
3253 goto err_free_msix;
3254 }
3255
3256 ena_config_debug_area(adapter);
3257
3258 memcpy(adapter->netdev->perm_addr, adapter->mac_addr, netdev->addr_len);
3259
3260 netif_carrier_off(netdev);
3261
3262 rc = register_netdev(netdev);
3263 if (rc) {
3264 dev_err(&pdev->dev, "Cannot register net device\n");
3265 goto err_rss;
3266 }
3267
3268 INIT_WORK(&adapter->suspend_io_task, ena_device_io_suspend);
3269 INIT_WORK(&adapter->resume_io_task, ena_device_io_resume);
3270 INIT_WORK(&adapter->reset_task, ena_fw_reset_device);
3271
3272 adapter->last_keep_alive_jiffies = jiffies;
82ef30f1
NB		 3273 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
3274 adapter->missing_tx_completion_to = TX_TIMEOUT;
3275 adapter->missing_tx_completion_threshold = MAX_NUM_OF_TIMEOUTED_PACKETS;
3276
3277 ena_update_hints(adapter, &get_feat_ctx.hw_hints);
1738cd3e 3278
f850b4a7
WY		 3279 setup_timer(&adapter->timer_service, ena_timer_service,
3280 (unsigned long)adapter);
3281 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
1738cd3e
NB		 3282
3283 dev_info(&pdev->dev, "%s found at mem %lx, mac addr %pM Queues %d\n",
3284 DEVICE_NAME, (long)pci_resource_start(pdev, 0),
3285 netdev->dev_addr, io_queue_num);
3286
3287 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
3288
3289 adapters_found++;
3290
3291 return 0;
3292
3293err_rss:
3294 ena_com_delete_debug_area(ena_dev);
3295 ena_com_rss_destroy(ena_dev);
3296err_free_msix:
e2eed0e3 3297 ena_com_dev_reset(ena_dev, ENA_REGS_RESET_INIT_ERR);
1738cd3e 3298 ena_free_mgmnt_irq(adapter);
06443684 3299 ena_disable_msix(adapter);
1738cd3e
NB		 3300err_worker_destroy:
3301 ena_com_destroy_interrupt_moderation(ena_dev);
3302 del_timer(&adapter->timer_service);
3303 cancel_work_sync(&adapter->suspend_io_task);
3304 cancel_work_sync(&adapter->resume_io_task);
3305err_netdev_destroy:
3306 free_netdev(netdev);
3307err_device_destroy:
3308 ena_com_delete_host_info(ena_dev);
3309 ena_com_admin_destroy(ena_dev);
3310err_free_region:
3311 ena_release_bars(ena_dev, pdev);
3312err_free_ena_dev:
1738cd3e
NB		 3313 vfree(ena_dev);
3314err_disable_device:
3315 pci_disable_device(pdev);
3316 return rc;
3317}
3318
3319/*****************************************************************************/
3320static int ena_sriov_configure(struct pci_dev *dev, int numvfs)
3321{
3322 int rc;
3323
3324 if (numvfs > 0) {
3325 rc = pci_enable_sriov(dev, numvfs);
3326 if (rc != 0) {
3327 dev_err(&dev->dev,
3328 "pci_enable_sriov failed to enable: %d vfs with the error: %d\n",
3329 numvfs, rc);
3330 return rc;
3331 }
3332
3333 return numvfs;
3334 }
3335
3336 if (numvfs == 0) {
3337 pci_disable_sriov(dev);
3338 return 0;
3339 }
3340
3341 return -EINVAL;
3342}
3343
3344/*****************************************************************************/
3345/*****************************************************************************/
3346
3347/* ena_remove - Device Removal Routine
3348 * @pdev: PCI device information struct
3349 *
3350 * ena_remove is called by the PCI subsystem to alert the driver
3351 * that it should release a PCI device.
3352 */
3353static void ena_remove(struct pci_dev *pdev)
3354{
3355 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3356 struct ena_com_dev *ena_dev;
3357 struct net_device *netdev;
3358
1738cd3e
NB		 3359 ena_dev = adapter->ena_dev;
3360 netdev = adapter->netdev;
3361
3362#ifdef CONFIG_RFS_ACCEL
3363 if ((adapter->msix_vecs >= 1) && (netdev->rx_cpu_rmap)) {
3364 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
3365 netdev->rx_cpu_rmap = NULL;
3366 }
3367#endif /* CONFIG_RFS_ACCEL */
3368
3369 unregister_netdev(netdev);
3370 del_timer_sync(&adapter->timer_service);
3371
3372 cancel_work_sync(&adapter->reset_task);
3373
3374 cancel_work_sync(&adapter->suspend_io_task);
3375
3376 cancel_work_sync(&adapter->resume_io_task);
3377
22b331c9
NB		 3378 /* Reset the device only if the device is running. */
3379 if (test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
e2eed0e3 3380 ena_com_dev_reset(ena_dev, adapter->reset_reason);
1738cd3e
NB		 3381
3382 ena_free_mgmnt_irq(adapter);
3383
06443684 3384 ena_disable_msix(adapter);
1738cd3e
NB		 3385
3386 free_netdev(netdev);
3387
3388 ena_com_mmio_reg_read_request_destroy(ena_dev);
3389
3390 ena_com_abort_admin_commands(ena_dev);
3391
3392 ena_com_wait_for_abort_completion(ena_dev);
3393
3394 ena_com_admin_destroy(ena_dev);
3395
3396 ena_com_rss_destroy(ena_dev);
3397
3398 ena_com_delete_debug_area(ena_dev);
3399
3400 ena_com_delete_host_info(ena_dev);
3401
3402 ena_release_bars(ena_dev, pdev);
3403
1738cd3e
NB		 3404 pci_disable_device(pdev);
3405
3406 ena_com_destroy_interrupt_moderation(ena_dev);
3407
3408 vfree(ena_dev);
3409}
3410
3411static struct pci_driver ena_pci_driver = {
3412 .name = DRV_MODULE_NAME,
3413 .id_table = ena_pci_tbl,
3414 .probe = ena_probe,
3415 .remove = ena_remove,
3416 .sriov_configure = ena_sriov_configure,
3417};
3418
3419static int __init ena_init(void)
3420{
3421 pr_info("%s", version);
3422
3423 ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME);
3424 if (!ena_wq) {
3425 pr_err("Failed to create workqueue\n");
3426 return -ENOMEM;
3427 }
3428
3429 return pci_register_driver(&ena_pci_driver);
3430}
3431
3432static void __exit ena_cleanup(void)
3433{
3434 pci_unregister_driver(&ena_pci_driver);
3435
3436 if (ena_wq) {
3437 destroy_workqueue(ena_wq);
3438 ena_wq = NULL;
3439 }
3440}
3441
3442/******************************************************************************
3443 ******************************** AENQ Handlers *******************************
3444 *****************************************************************************/
3445/* ena_update_on_link_change:
3446 * Notify the network interface about the change in link status
3447 */
3448static void ena_update_on_link_change(void *adapter_data,
3449 struct ena_admin_aenq_entry *aenq_e)
3450{
3451 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3452 struct ena_admin_aenq_link_change_desc *aenq_desc =
3453 (struct ena_admin_aenq_link_change_desc *)aenq_e;
3454 int status = aenq_desc->flags &
3455 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
3456
3457 if (status) {
3458 netdev_dbg(adapter->netdev, "%s\n", __func__);
3459 set_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3460 netif_carrier_on(adapter->netdev);
3461 } else {
3462 clear_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3463 netif_carrier_off(adapter->netdev);
3464 }
3465}
3466
3467static void ena_keep_alive_wd(void *adapter_data,
3468 struct ena_admin_aenq_entry *aenq_e)
3469{
3470 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3471
3472 adapter->last_keep_alive_jiffies = jiffies;
3473}
3474
3475static void ena_notification(void *adapter_data,
3476 struct ena_admin_aenq_entry *aenq_e)
3477{
3478 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
82ef30f1 3479 struct ena_admin_ena_hw_hints *hints;
1738cd3e
NB		 3480
3481 WARN(aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION,
3482 "Invalid group(%x) expected %x\n",
3483 aenq_e->aenq_common_desc.group,
3484 ENA_ADMIN_NOTIFICATION);
3485
3486 switch (aenq_e->aenq_common_desc.syndrom) {
3487 case ENA_ADMIN_SUSPEND:
3488 /* Suspend just the IO queues.
3489 * We deliberately don't suspend admin so the timer and
3490 * the keep_alive events should remain.
3491 */
3492 queue_work(ena_wq, &adapter->suspend_io_task);
3493 break;
3494 case ENA_ADMIN_RESUME:
3495 queue_work(ena_wq, &adapter->resume_io_task);
3496 break;
82ef30f1
NB		 3497 case ENA_ADMIN_UPDATE_HINTS:
3498 hints = (struct ena_admin_ena_hw_hints *)
3499 (&aenq_e->inline_data_w4);
3500 ena_update_hints(adapter, hints);
3501 break;
1738cd3e
NB		 3502 default:
3503 netif_err(adapter, drv, adapter->netdev,
3504 "Invalid aenq notification link state %d\n",
3505 aenq_e->aenq_common_desc.syndrom);
3506 }
3507}
3508
3509/* This handler will called for unknown event group or unimplemented handlers*/
3510static void unimplemented_aenq_handler(void *data,
3511 struct ena_admin_aenq_entry *aenq_e)
3512{
3513 struct ena_adapter *adapter = (struct ena_adapter *)data;
3514
3515 netif_err(adapter, drv, adapter->netdev,
3516 "Unknown event was received or event with unimplemented handler\n");
3517}
3518
3519static struct ena_aenq_handlers aenq_handlers = {
3520 .handlers = {
3521 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3522 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3523 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd,
3524 },
3525 .unimplemented_handler = unimplemented_aenq_handler
3526};
3527
3528module_init(ena_init);
3529module_exit(ena_cleanup);
Linux 6.x block layer and io_uring tree(s)