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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless...
[linux-2.6-block.git] / drivers / net / ethernet / alteon / acenic.c
CommitLineData
1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
1da177e4
LT		 53#include <linux/module.h>
54#include <linux/moduleparam.h>
1da177e4
LT		 55#include <linux/types.h>
56#include <linux/errno.h>
57#include <linux/ioport.h>
58#include <linux/pci.h>
1e7f0bd8 59#include <linux/dma-mapping.h>
1da177e4
LT		 60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
1da177e4
LT		 64#include <linux/delay.h>
65#include <linux/mm.h>
66#include <linux/highmem.h>
67#include <linux/sockios.h>
949b4254 68#include <linux/firmware.h>
5a0e3ad6 69#include <linux/slab.h>
268bb0ce 70#include <linux/prefetch.h>
1da177e4 71#include <linux/if_vlan.h>
1da177e4
LT		 72
73#ifdef SIOCETHTOOL
74#include <linux/ethtool.h>
75#endif
76
77#include <net/sock.h>
78#include <net/ip.h>
79
1da177e4
LT		 80#include <asm/io.h>
81#include <asm/irq.h>
82#include <asm/byteorder.h>
83#include <asm/uaccess.h>
84
85
86#define DRV_NAME "acenic"
87
88#undef INDEX_DEBUG
89
90#ifdef CONFIG_ACENIC_OMIT_TIGON_I
91#define ACE_IS_TIGON_I(ap) 0
92#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
93#else
94#define ACE_IS_TIGON_I(ap) (ap->version == 1)
95#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
96#endif
97
98#ifndef PCI_VENDOR_ID_ALTEON
6aa20a22 99#define PCI_VENDOR_ID_ALTEON 0x12ae
1da177e4
LT		 100#endif
101#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
102#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
103#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
104#endif
105#ifndef PCI_DEVICE_ID_3COM_3C985
106#define PCI_DEVICE_ID_3COM_3C985 0x0001
107#endif
108#ifndef PCI_VENDOR_ID_NETGEAR
109#define PCI_VENDOR_ID_NETGEAR 0x1385
110#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
111#endif
112#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
113#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
114#endif
115
116
117/*
118 * Farallon used the DEC vendor ID by mistake and they seem not
119 * to care - stinky!
120 */
121#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
122#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
123#endif
124#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
125#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
126#endif
127#ifndef PCI_VENDOR_ID_SGI
128#define PCI_VENDOR_ID_SGI 0x10a9
129#endif
130#ifndef PCI_DEVICE_ID_SGI_ACENIC
131#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
132#endif
133
9baa3c34 134static const struct pci_device_id acenic_pci_tbl[] = {
1da177e4
LT		 135 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
136 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
137 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
138 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
139 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
141 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
142 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
143 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
144 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
145 /*
146 * Farallon used the DEC vendor ID on their cards incorrectly,
147 * then later Alteon's ID.
148 */
149 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
150 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
151 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
152 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
153 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
154 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
155 { }
156};
157MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
158
1da177e4 159#define ace_sync_irq(irq) synchronize_irq(irq)
1da177e4
LT		 160
161#ifndef offset_in_page
162#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
163#endif
164
165#define ACE_MAX_MOD_PARMS 8
166#define BOARD_IDX_STATIC 0
167#define BOARD_IDX_OVERFLOW -1
168
1da177e4
LT		 169#include "acenic.h"
170
171/*
172 * These must be defined before the firmware is included.
173 */
174#define MAX_TEXT_LEN 96*1024
175#define MAX_RODATA_LEN 8*1024
176#define MAX_DATA_LEN 2*1024
177
1da177e4
LT		 178#ifndef tigon2FwReleaseLocal
179#define tigon2FwReleaseLocal 0
180#endif
181
182/*
183 * This driver currently supports Tigon I and Tigon II based cards
184 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
185 * GA620. The driver should also work on the SGI, DEC and Farallon
186 * versions of the card, however I have not been able to test that
187 * myself.
188 *
189 * This card is really neat, it supports receive hardware checksumming
190 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
191 * firmware. Also the programming interface is quite neat, except for
192 * the parts dealing with the i2c eeprom on the card ;-)
193 *
194 * Using jumbo frames:
195 *
196 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
197 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
198 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
199 * interface number and <MTU> being the MTU value.
200 *
201 * Module parameters:
202 *
203 * When compiled as a loadable module, the driver allows for a number
204 * of module parameters to be specified. The driver supports the
205 * following module parameters:
206 *
207 * trace=<val> - Firmware trace level. This requires special traced
208 * firmware to replace the firmware supplied with
209 * the driver - for debugging purposes only.
210 *
211 * link=<val> - Link state. Normally you want to use the default link
212 * parameters set by the driver. This can be used to
213 * override these in case your switch doesn't negotiate
214 * the link properly. Valid values are:
215 * 0x0001 - Force half duplex link.
216 * 0x0002 - Do not negotiate line speed with the other end.
217 * 0x0010 - 10Mbit/sec link.
218 * 0x0020 - 100Mbit/sec link.
219 * 0x0040 - 1000Mbit/sec link.
220 * 0x0100 - Do not negotiate flow control.
221 * 0x0200 - Enable RX flow control Y
222 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
223 * Default value is 0x0270, ie. enable link+flow
224 * control negotiation. Negotiating the highest
225 * possible link speed with RX flow control enabled.
226 *
227 * When disabling link speed negotiation, only one link
228 * speed is allowed to be specified!
229 *
230 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
231 * to wait for more packets to arive before
232 * interrupting the host, from the time the first
233 * packet arrives.
234 *
235 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
236 * to wait for more packets to arive in the transmit ring,
237 * before interrupting the host, after transmitting the
238 * first packet in the ring.
239 *
240 * max_tx_desc=<val> - maximum number of transmit descriptors
241 * (packets) transmitted before interrupting the host.
242 *
243 * max_rx_desc=<val> - maximum number of receive descriptors
244 * (packets) received before interrupting the host.
245 *
246 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
247 * increments of the NIC's on board memory to be used for
248 * transmit and receive buffers. For the 1MB NIC app. 800KB
249 * is available, on the 1/2MB NIC app. 300KB is available.
250 * 68KB will always be available as a minimum for both
251 * directions. The default value is a 50/50 split.
252 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
253 * operations, default (1) is to always disable this as
254 * that is what Alteon does on NT. I have not been able
255 * to measure any real performance differences with
256 * this on my systems. Set <val>=0 if you want to
257 * enable these operations.
258 *
259 * If you use more than one NIC, specify the parameters for the
260 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
261 * run tracing on NIC #2 but not on NIC #1 and #3.
262 *
263 * TODO:
264 *
265 * - Proper multicast support.
266 * - NIC dump support.
267 * - More tuning parameters.
268 *
269 * The mini ring is not used under Linux and I am not sure it makes sense
270 * to actually use it.
271 *
272 * New interrupt handler strategy:
273 *
274 * The old interrupt handler worked using the traditional method of
275 * replacing an skbuff with a new one when a packet arrives. However
276 * the rx rings do not need to contain a static number of buffer
277 * descriptors, thus it makes sense to move the memory allocation out
278 * of the main interrupt handler and do it in a bottom half handler
279 * and only allocate new buffers when the number of buffers in the
280 * ring is below a certain threshold. In order to avoid starving the
281 * NIC under heavy load it is however necessary to force allocation
282 * when hitting a minimum threshold. The strategy for alloction is as
283 * follows:
284 *
285 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
286 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
287 * the buffers in the interrupt handler
288 * RX_RING_THRES - maximum number of buffers in the rx ring
289 * RX_MINI_THRES - maximum number of buffers in the mini ring
290 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
291 *
292 * One advantagous side effect of this allocation approach is that the
293 * entire rx processing can be done without holding any spin lock
294 * since the rx rings and registers are totally independent of the tx
295 * ring and its registers. This of course includes the kmalloc's of
296 * new skb's. Thus start_xmit can run in parallel with rx processing
297 * and the memory allocation on SMP systems.
298 *
299 * Note that running the skb reallocation in a bottom half opens up
300 * another can of races which needs to be handled properly. In
301 * particular it can happen that the interrupt handler tries to run
302 * the reallocation while the bottom half is either running on another
303 * CPU or was interrupted on the same CPU. To get around this the
304 * driver uses bitops to prevent the reallocation routines from being
305 * reentered.
306 *
307 * TX handling can also be done without holding any spin lock, wheee
308 * this is fun! since tx_ret_csm is only written to by the interrupt
309 * handler. The case to be aware of is when shutting down the device
310 * and cleaning up where it is necessary to make sure that
311 * start_xmit() is not running while this is happening. Well DaveM
312 * informs me that this case is already protected against ... bye bye
313 * Mr. Spin Lock, it was nice to know you.
314 *
315 * TX interrupts are now partly disabled so the NIC will only generate
316 * TX interrupts for the number of coal ticks, not for the number of
317 * TX packets in the queue. This should reduce the number of TX only,
318 * ie. when no RX processing is done, interrupts seen.
319 */
320
321/*
322 * Threshold values for RX buffer allocation - the low water marks for
323 * when to start refilling the rings are set to 75% of the ring
324 * sizes. It seems to make sense to refill the rings entirely from the
325 * intrrupt handler once it gets below the panic threshold, that way
326 * we don't risk that the refilling is moved to another CPU when the
327 * one running the interrupt handler just got the slab code hot in its
328 * cache.
329 */
330#define RX_RING_SIZE 72
331#define RX_MINI_SIZE 64
332#define RX_JUMBO_SIZE 48
333
334#define RX_PANIC_STD_THRES 16
335#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
336#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
337#define RX_PANIC_MINI_THRES 12
338#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
339#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
340#define RX_PANIC_JUMBO_THRES 6
341#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
342#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
343
344
345/*
346 * Size of the mini ring entries, basically these just should be big
347 * enough to take TCP ACKs
348 */
349#define ACE_MINI_SIZE 100
350
351#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
352#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
353#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
354
355/*
356 * There seems to be a magic difference in the effect between 995 and 996
357 * but little difference between 900 and 995 ... no idea why.
358 *
359 * There is now a default set of tuning parameters which is set, depending
360 * on whether or not the user enables Jumbo frames. It's assumed that if
361 * Jumbo frames are enabled, the user wants optimal tuning for that case.
362 */
363#define DEF_TX_COAL 400 /* 996 */
364#define DEF_TX_MAX_DESC 60 /* was 40 */
365#define DEF_RX_COAL 120 /* 1000 */
366#define DEF_RX_MAX_DESC 25
367#define DEF_TX_RATIO 21 /* 24 */
368
369#define DEF_JUMBO_TX_COAL 20
370#define DEF_JUMBO_TX_MAX_DESC 60
371#define DEF_JUMBO_RX_COAL 30
372#define DEF_JUMBO_RX_MAX_DESC 6
373#define DEF_JUMBO_TX_RATIO 21
374
375#if tigon2FwReleaseLocal < 20001118
376/*
377 * Standard firmware and early modifications duplicate
378 * IRQ load without this flag (coal timer is never reset).
379 * Note that with this flag tx_coal should be less than
380 * time to xmit full tx ring.
381 * 400usec is not so bad for tx ring size of 128.
382 */
383#define TX_COAL_INTS_ONLY 1 /* worth it */
384#else
385/*
386 * With modified firmware, this is not necessary, but still useful.
387 */
388#define TX_COAL_INTS_ONLY 1
389#endif
390
391#define DEF_TRACE 0
392#define DEF_STAT (2 * TICKS_PER_SEC)
393
394
ddfce6bb 395static int link_state[ACE_MAX_MOD_PARMS];
1da177e4
LT		 396static int trace[ACE_MAX_MOD_PARMS];
397static int tx_coal_tick[ACE_MAX_MOD_PARMS];
398static int rx_coal_tick[ACE_MAX_MOD_PARMS];
399static int max_tx_desc[ACE_MAX_MOD_PARMS];
400static int max_rx_desc[ACE_MAX_MOD_PARMS];
401static int tx_ratio[ACE_MAX_MOD_PARMS];
402static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
403
404MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
405MODULE_LICENSE("GPL");
406MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
949b4254
JS		 407#ifndef CONFIG_ACENIC_OMIT_TIGON_I
408MODULE_FIRMWARE("acenic/tg1.bin");
409#endif
410MODULE_FIRMWARE("acenic/tg2.bin");
1da177e4 411
ddfce6bb 412module_param_array_named(link, link_state, int, NULL, 0);
1da177e4
LT		 413module_param_array(trace, int, NULL, 0);
414module_param_array(tx_coal_tick, int, NULL, 0);
415module_param_array(max_tx_desc, int, NULL, 0);
416module_param_array(rx_coal_tick, int, NULL, 0);
417module_param_array(max_rx_desc, int, NULL, 0);
418module_param_array(tx_ratio, int, NULL, 0);
419MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
420MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
421MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
422MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
423MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
424MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
425MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
426
427
083abbb7 428static const char version[] =
1da177e4
LT		 429 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
430 " http://home.cern.ch/~jes/gige/acenic.html\n";
431
432static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
433static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
434static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
435
7282d491 436static const struct ethtool_ops ace_ethtool_ops = {
1da177e4
LT		 437 .get_settings = ace_get_settings,
438 .set_settings = ace_set_settings,
439 .get_drvinfo = ace_get_drvinfo,
440};
441
442static void ace_watchdog(struct net_device *dev);
443
d8b83c57
SH		 444static const struct net_device_ops ace_netdev_ops = {
445 .ndo_open = ace_open,
446 .ndo_stop = ace_close,
447 .ndo_tx_timeout = ace_watchdog,
448 .ndo_get_stats = ace_get_stats,
00829823 449 .ndo_start_xmit = ace_start_xmit,
afc4b13d 450 .ndo_set_rx_mode = ace_set_multicast_list,
52255bbe 451 .ndo_validate_addr = eth_validate_addr,
d8b83c57
SH		 452 .ndo_set_mac_address = ace_set_mac_addr,
453 .ndo_change_mtu = ace_change_mtu,
d8b83c57
SH		 454};
455
083abbb7 456static int acenic_probe_one(struct pci_dev *pdev,
1dd06ae8 457 const struct pci_device_id *id)
1da177e4
LT		 458{
459 struct net_device *dev;
460 struct ace_private *ap;
461 static int boards_found;
462
463 dev = alloc_etherdev(sizeof(struct ace_private));
41de8d4c 464 if (dev == NULL)
1da177e4 465 return -ENOMEM;
1da177e4 466
1da177e4
LT		 467 SET_NETDEV_DEV(dev, &pdev->dev);
468
454d7c9b 469 ap = netdev_priv(dev);
1da177e4
LT		 470 ap->pdev = pdev;
471 ap->name = pci_name(pdev);
472
473 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f646968f 474 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
25805dcf 475
25805dcf 476 dev->watchdog_timeo = 5*HZ;
1da177e4 477
d8b83c57 478 dev->netdev_ops = &ace_netdev_ops;
7ad24ea4 479 dev->ethtool_ops = &ace_ethtool_ops;
1da177e4
LT		 480
481 /* we only display this string ONCE */
482 if (!boards_found)
483 printk(version);
484
485 if (pci_enable_device(pdev))
486 goto fail_free_netdev;
487
488 /*
489 * Enable master mode before we start playing with the
490 * pci_command word since pci_set_master() will modify
491 * it.
492 */
493 pci_set_master(pdev);
494
495 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
496
6aa20a22 497 /* OpenFirmware on Mac's does not set this - DOH.. */
1da177e4
LT		 498 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
499 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
500 "access - was not enabled by BIOS/Firmware\n",
501 ap->name);
502 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
503 pci_write_config_word(ap->pdev, PCI_COMMAND,
504 ap->pci_command);
505 wmb();
506 }
507
508 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
509 if (ap->pci_latency <= 0x40) {
510 ap->pci_latency = 0x40;
511 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
512 }
513
514 /*
515 * Remap the regs into kernel space - this is abuse of
516 * dev->base_addr since it was means for I/O port
517 * addresses but who gives a damn.
518 */
519 dev->base_addr = pci_resource_start(pdev, 0);
520 ap->regs = ioremap(dev->base_addr, 0x4000);
521 if (!ap->regs) {
522 printk(KERN_ERR "%s: Unable to map I/O register, "
523 "AceNIC %i will be disabled.\n",
524 ap->name, boards_found);
525 goto fail_free_netdev;
526 }
527
528 switch(pdev->vendor) {
529 case PCI_VENDOR_ID_ALTEON:
530 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
531 printk(KERN_INFO "%s: Farallon PN9100-T ",
532 ap->name);
533 } else {
534 printk(KERN_INFO "%s: Alteon AceNIC ",
535 ap->name);
536 }
537 break;
538 case PCI_VENDOR_ID_3COM:
539 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
540 break;
541 case PCI_VENDOR_ID_NETGEAR:
542 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
543 break;
544 case PCI_VENDOR_ID_DEC:
545 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
546 printk(KERN_INFO "%s: Farallon PN9000-SX ",
547 ap->name);
548 break;
549 }
550 case PCI_VENDOR_ID_SGI:
551 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
552 break;
553 default:
554 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
555 break;
556 }
557
558 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
c6387a48 559 printk("irq %d\n", pdev->irq);
1da177e4
LT		 560
561#ifdef CONFIG_ACENIC_OMIT_TIGON_I
562 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
563 printk(KERN_ERR "%s: Driver compiled without Tigon I"
564 " support - NIC disabled\n", dev->name);
565 goto fail_uninit;
566 }
567#endif
568
569 if (ace_allocate_descriptors(dev))
570 goto fail_free_netdev;
571
572#ifdef MODULE
573 if (boards_found >= ACE_MAX_MOD_PARMS)
574 ap->board_idx = BOARD_IDX_OVERFLOW;
575 else
576 ap->board_idx = boards_found;
577#else
578 ap->board_idx = BOARD_IDX_STATIC;
579#endif
580
581 if (ace_init(dev))
582 goto fail_free_netdev;
583
584 if (register_netdev(dev)) {
585 printk(KERN_ERR "acenic: device registration failed\n");
586 goto fail_uninit;
587 }
588 ap->name = dev->name;
589
590 if (ap->pci_using_dac)
591 dev->features |= NETIF_F_HIGHDMA;
592
593 pci_set_drvdata(pdev, dev);
594
595 boards_found++;
596 return 0;
597
598 fail_uninit:
599 ace_init_cleanup(dev);
600 fail_free_netdev:
601 free_netdev(dev);
602 return -ENODEV;
603}
604
083abbb7 605static void acenic_remove_one(struct pci_dev *pdev)
1da177e4
LT		 606{
607 struct net_device *dev = pci_get_drvdata(pdev);
608 struct ace_private *ap = netdev_priv(dev);
609 struct ace_regs __iomem *regs = ap->regs;
610 short i;
611
612 unregister_netdev(dev);
613
614 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
615 if (ap->version >= 2)
616 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
6aa20a22 617
1da177e4
LT		 618 /*
619 * This clears any pending interrupts
620 */
621 writel(1, &regs->Mb0Lo);
622 readl(&regs->CpuCtrl); /* flush */
623
624 /*
625 * Make sure no other CPUs are processing interrupts
626 * on the card before the buffers are being released.
627 * Otherwise one might experience some `interesting'
628 * effects.
629 *
630 * Then release the RX buffers - jumbo buffers were
631 * already released in ace_close().
632 */
633 ace_sync_irq(dev->irq);
634
635 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
636 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
637
638 if (skb) {
639 struct ring_info *ringp;
640 dma_addr_t mapping;
641
642 ringp = &ap->skb->rx_std_skbuff[i];
430e55b1 643 mapping = dma_unmap_addr(ringp, mapping);
1da177e4
LT		 644 pci_unmap_page(ap->pdev, mapping,
645 ACE_STD_BUFSIZE,
646 PCI_DMA_FROMDEVICE);
647
648 ap->rx_std_ring[i].size = 0;
649 ap->skb->rx_std_skbuff[i].skb = NULL;
650 dev_kfree_skb(skb);
651 }
652 }
653
654 if (ap->version >= 2) {
655 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
656 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
657
658 if (skb) {
659 struct ring_info *ringp;
660 dma_addr_t mapping;
661
662 ringp = &ap->skb->rx_mini_skbuff[i];
430e55b1 663 mapping = dma_unmap_addr(ringp,mapping);
1da177e4
LT		 664 pci_unmap_page(ap->pdev, mapping,
665 ACE_MINI_BUFSIZE,
666 PCI_DMA_FROMDEVICE);
667
668 ap->rx_mini_ring[i].size = 0;
669 ap->skb->rx_mini_skbuff[i].skb = NULL;
670 dev_kfree_skb(skb);
671 }
672 }
673 }
674
675 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
676 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
677 if (skb) {
678 struct ring_info *ringp;
679 dma_addr_t mapping;
680
681 ringp = &ap->skb->rx_jumbo_skbuff[i];
430e55b1 682 mapping = dma_unmap_addr(ringp, mapping);
1da177e4
LT		 683 pci_unmap_page(ap->pdev, mapping,
684 ACE_JUMBO_BUFSIZE,
685 PCI_DMA_FROMDEVICE);
686
687 ap->rx_jumbo_ring[i].size = 0;
688 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
689 dev_kfree_skb(skb);
690 }
691 }
692
693 ace_init_cleanup(dev);
694 free_netdev(dev);
695}
696
697static struct pci_driver acenic_pci_driver = {
698 .name = "acenic",
699 .id_table = acenic_pci_tbl,
700 .probe = acenic_probe_one,
083abbb7 701 .remove = acenic_remove_one,
1da177e4
LT		 702};
703
1da177e4
LT		 704static void ace_free_descriptors(struct net_device *dev)
705{
706 struct ace_private *ap = netdev_priv(dev);
707 int size;
708
709 if (ap->rx_std_ring != NULL) {
710 size = (sizeof(struct rx_desc) *
711 (RX_STD_RING_ENTRIES +
712 RX_JUMBO_RING_ENTRIES +
713 RX_MINI_RING_ENTRIES +
714 RX_RETURN_RING_ENTRIES));
715 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
716 ap->rx_ring_base_dma);
717 ap->rx_std_ring = NULL;
718 ap->rx_jumbo_ring = NULL;
719 ap->rx_mini_ring = NULL;
720 ap->rx_return_ring = NULL;
721 }
722 if (ap->evt_ring != NULL) {
723 size = (sizeof(struct event) * EVT_RING_ENTRIES);
724 pci_free_consistent(ap->pdev, size, ap->evt_ring,
725 ap->evt_ring_dma);
726 ap->evt_ring = NULL;
727 }
728 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
729 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
730 pci_free_consistent(ap->pdev, size, ap->tx_ring,
731 ap->tx_ring_dma);
732 }
733 ap->tx_ring = NULL;
734
735 if (ap->evt_prd != NULL) {
736 pci_free_consistent(ap->pdev, sizeof(u32),
737 (void *)ap->evt_prd, ap->evt_prd_dma);
738 ap->evt_prd = NULL;
739 }
740 if (ap->rx_ret_prd != NULL) {
741 pci_free_consistent(ap->pdev, sizeof(u32),
742 (void *)ap->rx_ret_prd,
743 ap->rx_ret_prd_dma);
744 ap->rx_ret_prd = NULL;
745 }
746 if (ap->tx_csm != NULL) {
747 pci_free_consistent(ap->pdev, sizeof(u32),
748 (void *)ap->tx_csm, ap->tx_csm_dma);
749 ap->tx_csm = NULL;
750 }
751}
752
753
754static int ace_allocate_descriptors(struct net_device *dev)
755{
756 struct ace_private *ap = netdev_priv(dev);
757 int size;
758
759 size = (sizeof(struct rx_desc) *
760 (RX_STD_RING_ENTRIES +
761 RX_JUMBO_RING_ENTRIES +
762 RX_MINI_RING_ENTRIES +
763 RX_RETURN_RING_ENTRIES));
764
765 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
766 &ap->rx_ring_base_dma);
767 if (ap->rx_std_ring == NULL)
768 goto fail;
769
770 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
771 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
772 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
773
774 size = (sizeof(struct event) * EVT_RING_ENTRIES);
775
776 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
777
778 if (ap->evt_ring == NULL)
779 goto fail;
780
781 /*
782 * Only allocate a host TX ring for the Tigon II, the Tigon I
783 * has to use PCI registers for this ;-(
784 */
785 if (!ACE_IS_TIGON_I(ap)) {
786 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
787
788 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
789 &ap->tx_ring_dma);
790
791 if (ap->tx_ring == NULL)
792 goto fail;
793 }
794
795 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
796 &ap->evt_prd_dma);
797 if (ap->evt_prd == NULL)
798 goto fail;
799
800 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
801 &ap->rx_ret_prd_dma);
802 if (ap->rx_ret_prd == NULL)
803 goto fail;
804
805 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
806 &ap->tx_csm_dma);
807 if (ap->tx_csm == NULL)
808 goto fail;
809
810 return 0;
811
812fail:
813 /* Clean up. */
814 ace_init_cleanup(dev);
815 return 1;
816}
817
818
819/*
820 * Generic cleanup handling data allocated during init. Used when the
821 * module is unloaded or if an error occurs during initialization
822 */
823static void ace_init_cleanup(struct net_device *dev)
824{
825 struct ace_private *ap;
826
827 ap = netdev_priv(dev);
828
829 ace_free_descriptors(dev);
830
831 if (ap->info)
832 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
833 ap->info, ap->info_dma);
b4558ea9
JJ		 834 kfree(ap->skb);
835 kfree(ap->trace_buf);
1da177e4
LT		 836
837 if (dev->irq)
838 free_irq(dev->irq, dev);
839
840 iounmap(ap->regs);
841}
842
843
844/*
845 * Commands are considered to be slow.
846 */
847static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
848{
849 u32 idx;
850
851 idx = readl(&regs->CmdPrd);
852
853 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
854 idx = (idx + 1) % CMD_RING_ENTRIES;
855
856 writel(idx, &regs->CmdPrd);
857}
858
859
083abbb7 860static int ace_init(struct net_device *dev)
1da177e4
LT		 861{
862 struct ace_private *ap;
863 struct ace_regs __iomem *regs;
864 struct ace_info *info = NULL;
865 struct pci_dev *pdev;
866 unsigned long myjif;
867 u64 tmp_ptr;
868 u32 tig_ver, mac1, mac2, tmp, pci_state;
869 int board_idx, ecode = 0;
870 short i;
871 unsigned char cache_size;
872
873 ap = netdev_priv(dev);
874 regs = ap->regs;
875
876 board_idx = ap->board_idx;
877
878 /*
879 * aman@sgi.com - its useful to do a NIC reset here to
880 * address the `Firmware not running' problem subsequent
881 * to any crashes involving the NIC
882 */
883 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
884 readl(&regs->HostCtrl); /* PCI write posting */
885 udelay(5);
886
887 /*
888 * Don't access any other registers before this point!
889 */
890#ifdef __BIG_ENDIAN
891 /*
892 * This will most likely need BYTE_SWAP once we switch
893 * to using __raw_writel()
894 */
895 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
896 &regs->HostCtrl);
897#else
898 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
899 &regs->HostCtrl);
900#endif
901 readl(&regs->HostCtrl); /* PCI write posting */
902
903 /*
904 * Stop the NIC CPU and clear pending interrupts
905 */
906 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
907 readl(&regs->CpuCtrl); /* PCI write posting */
908 writel(0, &regs->Mb0Lo);
909
910 tig_ver = readl(&regs->HostCtrl) >> 28;
911
912 switch(tig_ver){
913#ifndef CONFIG_ACENIC_OMIT_TIGON_I
914 case 4:
915 case 5:
916 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 917 tig_ver, ap->firmware_major, ap->firmware_minor,
918 ap->firmware_fix);
1da177e4
LT		 919 writel(0, &regs->LocalCtrl);
920 ap->version = 1;
921 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
922 break;
923#endif
924 case 6:
925 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 926 tig_ver, ap->firmware_major, ap->firmware_minor,
927 ap->firmware_fix);
1da177e4
LT		 928 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
929 readl(&regs->CpuBCtrl); /* PCI write posting */
930 /*
931 * The SRAM bank size does _not_ indicate the amount
932 * of memory on the card, it controls the _bank_ size!
933 * Ie. a 1MB AceNIC will have two banks of 512KB.
934 */
935 writel(SRAM_BANK_512K, &regs->LocalCtrl);
936 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
937 ap->version = 2;
938 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
939 break;
940 default:
941 printk(KERN_WARNING " Unsupported Tigon version detected "
942 "(%i)\n", tig_ver);
943 ecode = -ENODEV;
944 goto init_error;
945 }
946
947 /*
948 * ModeStat _must_ be set after the SRAM settings as this change
949 * seems to corrupt the ModeStat and possible other registers.
950 * The SRAM settings survive resets and setting it to the same
951 * value a second time works as well. This is what caused the
952 * `Firmware not running' problem on the Tigon II.
953 */
954#ifdef __BIG_ENDIAN
955 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
956 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
957#else
958 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
959 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
960#endif
961 readl(&regs->ModeStat); /* PCI write posting */
962
963 mac1 = 0;
964 for(i = 0; i < 4; i++) {
ddfce6bb 965 int t;
6f9d4722 966
1da177e4 967 mac1 = mac1 << 8;
ddfce6bb
SH		 968 t = read_eeprom_byte(dev, 0x8c+i);
969 if (t < 0) {
1da177e4
LT		 970 ecode = -EIO;
971 goto init_error;
972 } else
ddfce6bb 973 mac1 |= (t & 0xff);
1da177e4
LT		 974 }
975 mac2 = 0;
976 for(i = 4; i < 8; i++) {
ddfce6bb 977 int t;
6f9d4722 978
1da177e4 979 mac2 = mac2 << 8;
ddfce6bb
SH		 980 t = read_eeprom_byte(dev, 0x8c+i);
981 if (t < 0) {
1da177e4
LT		 982 ecode = -EIO;
983 goto init_error;
984 } else
ddfce6bb 985 mac2 |= (t & 0xff);
1da177e4
LT		 986 }
987
988 writel(mac1, &regs->MacAddrHi);
989 writel(mac2, &regs->MacAddrLo);
990
1da177e4
LT		 991 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
992 dev->dev_addr[1] = mac1 & 0xff;
993 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
994 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
995 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
996 dev->dev_addr[5] = mac2 & 0xff;
997
e174961c 998 printk("MAC: %pM\n", dev->dev_addr);
0795af57 999
1da177e4
LT		 1000 /*
1001 * Looks like this is necessary to deal with on all architectures,
1002 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1003 * Ie. having two NICs in the machine, one will have the cache
1004 * line set at boot time, the other will not.
1005 */
1006 pdev = ap->pdev;
1007 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1008 cache_size <<= 2;
1009 if (cache_size != SMP_CACHE_BYTES) {
1010 printk(KERN_INFO " PCI cache line size set incorrectly "
1011 "(%i bytes) by BIOS/FW, ", cache_size);
1012 if (cache_size > SMP_CACHE_BYTES)
1013 printk("expecting %i\n", SMP_CACHE_BYTES);
1014 else {
1015 printk("correcting to %i\n", SMP_CACHE_BYTES);
1016 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1017 SMP_CACHE_BYTES >> 2);
1018 }
1019 }
1020
1021 pci_state = readl(&regs->PciState);
1022 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1023 "latency: %i clks\n",
1024 (pci_state & PCI_32BIT) ? 32 : 64,
6aa20a22 1025 (pci_state & PCI_66MHZ) ? 66 : 33,
1da177e4
LT		 1026 ap->pci_latency);
1027
1028 /*
1029 * Set the max DMA transfer size. Seems that for most systems
1030 * the performance is better when no MAX parameter is
1031 * set. However for systems enabling PCI write and invalidate,
1032 * DMA writes must be set to the L1 cache line size to get
1033 * optimal performance.
1034 *
1035 * The default is now to turn the PCI write and invalidate off
1036 * - that is what Alteon does for NT.
1037 */
1038 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1039 if (ap->version >= 2) {
1040 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1041 /*
1042 * Tuning parameters only supported for 8 cards
1043 */
1044 if (board_idx == BOARD_IDX_OVERFLOW ||
1045 dis_pci_mem_inval[board_idx]) {
1046 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1047 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1048 pci_write_config_word(pdev, PCI_COMMAND,
1049 ap->pci_command);
1050 printk(KERN_INFO " Disabling PCI memory "
1051 "write and invalidate\n");
1052 }
1053 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1054 printk(KERN_INFO " PCI memory write & invalidate "
1055 "enabled by BIOS, enabling counter measures\n");
1056
1057 switch(SMP_CACHE_BYTES) {
1058 case 16:
1059 tmp |= DMA_WRITE_MAX_16;
1060 break;
1061 case 32:
1062 tmp |= DMA_WRITE_MAX_32;
1063 break;
1064 case 64:
1065 tmp |= DMA_WRITE_MAX_64;
1066 break;
1067 case 128:
1068 tmp |= DMA_WRITE_MAX_128;
1069 break;
1070 default:
1071 printk(KERN_INFO " Cache line size %i not "
1072 "supported, PCI write and invalidate "
1073 "disabled\n", SMP_CACHE_BYTES);
1074 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1075 pci_write_config_word(pdev, PCI_COMMAND,
1076 ap->pci_command);
1077 }
1078 }
1079 }
1080
1081#ifdef __sparc__
1082 /*
1083 * On this platform, we know what the best dma settings
1084 * are. We use 64-byte maximum bursts, because if we
1085 * burst larger than the cache line size (or even cross
1086 * a 64byte boundary in a single burst) the UltraSparc
1087 * PCI controller will disconnect at 64-byte multiples.
1088 *
1089 * Read-multiple will be properly enabled above, and when
1090 * set will give the PCI controller proper hints about
1091 * prefetching.
1092 */
1093 tmp &= ~DMA_READ_WRITE_MASK;
1094 tmp |= DMA_READ_MAX_64;
1095 tmp |= DMA_WRITE_MAX_64;
1096#endif
1097#ifdef __alpha__
1098 tmp &= ~DMA_READ_WRITE_MASK;
1099 tmp |= DMA_READ_MAX_128;
1100 /*
1101 * All the docs say MUST NOT. Well, I did.
1102 * Nothing terrible happens, if we load wrong size.
1103 * Bit w&i still works better!
1104 */
1105 tmp |= DMA_WRITE_MAX_128;
1106#endif
1107 writel(tmp, &regs->PciState);
1108
1109#if 0
1110 /*
1111 * The Host PCI bus controller driver has to set FBB.
1112 * If all devices on that PCI bus support FBB, then the controller
1113 * can enable FBB support in the Host PCI Bus controller (or on
1114 * the PCI-PCI bridge if that applies).
1115 * -ggg
1116 */
1117 /*
1118 * I have received reports from people having problems when this
1119 * bit is enabled.
1120 */
1121 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1122 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1123 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1124 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1125 }
1126#endif
6aa20a22 1127
1da177e4
LT		 1128 /*
1129 * Configure DMA attributes.
1130 */
6a35528a 1131 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 1132 ap->pci_using_dac = 1;
284901a9 1133 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 1134 ap->pci_using_dac = 0;
1135 } else {
1136 ecode = -ENODEV;
1137 goto init_error;
1138 }
1139
1140 /*
1141 * Initialize the generic info block and the command+event rings
1142 * and the control blocks for the transmit and receive rings
1143 * as they need to be setup once and for all.
1144 */
1145 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1146 &ap->info_dma))) {
1147 ecode = -EAGAIN;
1148 goto init_error;
1149 }
1150 ap->info = info;
1151
1152 /*
1153 * Get the memory for the skb rings.
1154 */
1155 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1156 ecode = -EAGAIN;
1157 goto init_error;
1158 }
1159
1fb9df5d 1160 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1da177e4
LT		 1161 DRV_NAME, dev);
1162 if (ecode) {
1163 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1164 DRV_NAME, pdev->irq);
1165 goto init_error;
1166 } else
1167 dev->irq = pdev->irq;
1168
1169#ifdef INDEX_DEBUG
1170 spin_lock_init(&ap->debug_lock);
1171 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1172 ap->last_std_rx = 0;
1173 ap->last_mini_rx = 0;
1174#endif
1175
1176 memset(ap->info, 0, sizeof(struct ace_info));
1177 memset(ap->skb, 0, sizeof(struct ace_skb));
1178
6c60e0c3
BH		 1179 ecode = ace_load_firmware(dev);
1180 if (ecode)
949b4254
JS		 1181 goto init_error;
1182
1da177e4
LT		 1183 ap->fw_running = 0;
1184
1185 tmp_ptr = ap->info_dma;
1186 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1187 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1188
1189 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1190
1191 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1192 info->evt_ctrl.flags = 0;
1193
1194 *(ap->evt_prd) = 0;
1195 wmb();
1196 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1197 writel(0, &regs->EvtCsm);
1198
1199 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1200 info->cmd_ctrl.flags = 0;
1201 info->cmd_ctrl.max_len = 0;
1202
1203 for (i = 0; i < CMD_RING_ENTRIES; i++)
1204 writel(0, &regs->CmdRng[i]);
1205
1206 writel(0, &regs->CmdPrd);
1207 writel(0, &regs->CmdCsm);
1208
1209 tmp_ptr = ap->info_dma;
1210 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1211 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1212
1213 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1214 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1215 info->rx_std_ctrl.flags =
08dddfc3 1216 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1217
1218 memset(ap->rx_std_ring, 0,
1219 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1220
1221 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1222 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1223
1224 ap->rx_std_skbprd = 0;
1225 atomic_set(&ap->cur_rx_bufs, 0);
1226
1227 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1228 (ap->rx_ring_base_dma +
1229 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1230 info->rx_jumbo_ctrl.max_len = 0;
1231 info->rx_jumbo_ctrl.flags =
08dddfc3 1232 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1233
1234 memset(ap->rx_jumbo_ring, 0,
1235 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1236
1237 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1238 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1239
1240 ap->rx_jumbo_skbprd = 0;
1241 atomic_set(&ap->cur_jumbo_bufs, 0);
1242
1243 memset(ap->rx_mini_ring, 0,
1244 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1245
1246 if (ap->version >= 2) {
1247 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1248 (ap->rx_ring_base_dma +
1249 (sizeof(struct rx_desc) *
1250 (RX_STD_RING_ENTRIES +
1251 RX_JUMBO_RING_ENTRIES))));
1252 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
6aa20a22 1253 info->rx_mini_ctrl.flags =
08dddfc3 1254 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1255
1256 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1257 ap->rx_mini_ring[i].flags =
1258 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1259 } else {
1260 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1261 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1262 info->rx_mini_ctrl.max_len = 0;
1263 }
1264
1265 ap->rx_mini_skbprd = 0;
1266 atomic_set(&ap->cur_mini_bufs, 0);
1267
1268 set_aceaddr(&info->rx_return_ctrl.rngptr,
1269 (ap->rx_ring_base_dma +
1270 (sizeof(struct rx_desc) *
1271 (RX_STD_RING_ENTRIES +
1272 RX_JUMBO_RING_ENTRIES +
1273 RX_MINI_RING_ENTRIES))));
1274 info->rx_return_ctrl.flags = 0;
1275 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1276
1277 memset(ap->rx_return_ring, 0,
1278 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1279
1280 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1281 *(ap->rx_ret_prd) = 0;
1282
1283 writel(TX_RING_BASE, &regs->WinBase);
1284
1285 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 1286 ap->tx_ring = (__force struct tx_desc *) regs->Window;
6aa20a22 1287 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1da177e4 1288 * sizeof(struct tx_desc)) / sizeof(u32); i++)
ddfce6bb 1289 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1da177e4
LT		 1290
1291 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1292 } else {
1293 memset(ap->tx_ring, 0,
1294 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1295
1296 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1297 }
1298
1299 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
08dddfc3 1300 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1301
1302 /*
1303 * The Tigon I does not like having the TX ring in host memory ;-(
1304 */
1305 if (!ACE_IS_TIGON_I(ap))
1306 tmp |= RCB_FLG_TX_HOST_RING;
1307#if TX_COAL_INTS_ONLY
1308 tmp |= RCB_FLG_COAL_INT_ONLY;
1309#endif
1310 info->tx_ctrl.flags = tmp;
1311
1312 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1313
1314 /*
1315 * Potential item for tuning parameter
1316 */
1317#if 0 /* NO */
1318 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1319 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1320#else
1321 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1322 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1323#endif
1324
1325 writel(0, &regs->MaskInt);
1326 writel(1, &regs->IfIdx);
1327#if 0
1328 /*
1329 * McKinley boxes do not like us fiddling with AssistState
1330 * this early
1331 */
1332 writel(1, &regs->AssistState);
1333#endif
1334
1335 writel(DEF_STAT, &regs->TuneStatTicks);
1336 writel(DEF_TRACE, &regs->TuneTrace);
1337
1338 ace_set_rxtx_parms(dev, 0);
1339
1340 if (board_idx == BOARD_IDX_OVERFLOW) {
1341 printk(KERN_WARNING "%s: more than %i NICs detected, "
1342 "ignoring module parameters!\n",
1343 ap->name, ACE_MAX_MOD_PARMS);
1344 } else if (board_idx >= 0) {
1345 if (tx_coal_tick[board_idx])
1346 writel(tx_coal_tick[board_idx],
1347 &regs->TuneTxCoalTicks);
1348 if (max_tx_desc[board_idx])
1349 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1350
1351 if (rx_coal_tick[board_idx])
1352 writel(rx_coal_tick[board_idx],
1353 &regs->TuneRxCoalTicks);
1354 if (max_rx_desc[board_idx])
1355 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1356
1357 if (trace[board_idx])
1358 writel(trace[board_idx], &regs->TuneTrace);
1359
1360 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1361 writel(tx_ratio[board_idx], &regs->TxBufRat);
1362 }
1363
1364 /*
1365 * Default link parameters
1366 */
1367 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1368 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1369 if(ap->version >= 2)
1370 tmp |= LNK_TX_FLOW_CTL_Y;
1371
1372 /*
1373 * Override link default parameters
1374 */
ddfce6bb
SH		 1375 if ((board_idx >= 0) && link_state[board_idx]) {
1376 int option = link_state[board_idx];
1da177e4
LT		 1377
1378 tmp = LNK_ENABLE;
1379
1380 if (option & 0x01) {
1381 printk(KERN_INFO "%s: Setting half duplex link\n",
1382 ap->name);
1383 tmp &= ~LNK_FULL_DUPLEX;
1384 }
1385 if (option & 0x02)
1386 tmp &= ~LNK_NEGOTIATE;
1387 if (option & 0x10)
1388 tmp |= LNK_10MB;
1389 if (option & 0x20)
1390 tmp |= LNK_100MB;
1391 if (option & 0x40)
1392 tmp |= LNK_1000MB;
1393 if ((option & 0x70) == 0) {
1394 printk(KERN_WARNING "%s: No media speed specified, "
1395 "forcing auto negotiation\n", ap->name);
1396 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1397 LNK_100MB | LNK_10MB;
1398 }
1399 if ((option & 0x100) == 0)
1400 tmp |= LNK_NEG_FCTL;
1401 else
1402 printk(KERN_INFO "%s: Disabling flow control "
1403 "negotiation\n", ap->name);
1404 if (option & 0x200)
1405 tmp |= LNK_RX_FLOW_CTL_Y;
1406 if ((option & 0x400) && (ap->version >= 2)) {
1407 printk(KERN_INFO "%s: Enabling TX flow control\n",
1408 ap->name);
1409 tmp |= LNK_TX_FLOW_CTL_Y;
1410 }
1411 }
1412
1413 ap->link = tmp;
1414 writel(tmp, &regs->TuneLink);
1415 if (ap->version >= 2)
1416 writel(tmp, &regs->TuneFastLink);
1417
949b4254 1418 writel(ap->firmware_start, &regs->Pc);
1da177e4
LT		 1419
1420 writel(0, &regs->Mb0Lo);
1421
1422 /*
1423 * Set tx_csm before we start receiving interrupts, otherwise
1424 * the interrupt handler might think it is supposed to process
1425 * tx ints before we are up and running, which may cause a null
1426 * pointer access in the int handler.
1427 */
1428 ap->cur_rx = 0;
1429 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1430
1431 wmb();
1432 ace_set_txprd(regs, ap, 0);
1433 writel(0, &regs->RxRetCsm);
1434
1da177e4
LT		 1435 /*
1436 * Enable DMA engine now.
1437 * If we do this sooner, Mckinley box pukes.
1438 * I assume it's because Tigon II DMA engine wants to check
1439 * *something* even before the CPU is started.
1440 */
1441 writel(1, &regs->AssistState); /* enable DMA */
1442
1443 /*
1444 * Start the NIC CPU
1445 */
1446 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1447 readl(&regs->CpuCtrl);
1448
1449 /*
1450 * Wait for the firmware to spin up - max 3 seconds.
1451 */
1452 myjif = jiffies + 3 * HZ;
1453 while (time_before(jiffies, myjif) && !ap->fw_running)
1454 cpu_relax();
1455
1456 if (!ap->fw_running) {
1457 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1458
1459 ace_dump_trace(ap);
1460 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1461 readl(&regs->CpuCtrl);
1462
1463 /* aman@sgi.com - account for badly behaving firmware/NIC:
1464 * - have observed that the NIC may continue to generate
1465 * interrupts for some reason; attempt to stop it - halt
1466 * second CPU for Tigon II cards, and also clear Mb0
1467 * - if we're a module, we'll fail to load if this was
1468 * the only GbE card in the system => if the kernel does
1469 * see an interrupt from the NIC, code to handle it is
1470 * gone and OOps! - so free_irq also
1471 */
1472 if (ap->version >= 2)
1473 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1474 &regs->CpuBCtrl);
1475 writel(0, &regs->Mb0Lo);
1476 readl(&regs->Mb0Lo);
1477
1478 ecode = -EBUSY;
1479 goto init_error;
1480 }
1481
1482 /*
1483 * We load the ring here as there seem to be no way to tell the
1484 * firmware to wipe the ring without re-initializing it.
1485 */
1486 if (!test_and_set_bit(0, &ap->std_refill_busy))
427e21fa 1487 ace_load_std_rx_ring(dev, RX_RING_SIZE);
1da177e4
LT		 1488 else
1489 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1490 ap->name);
1491 if (ap->version >= 2) {
1492 if (!test_and_set_bit(0, &ap->mini_refill_busy))
427e21fa 1493 ace_load_mini_rx_ring(dev, RX_MINI_SIZE);
1da177e4
LT		 1494 else
1495 printk(KERN_ERR "%s: Someone is busy refilling "
1496 "the RX mini ring\n", ap->name);
1497 }
1498 return 0;
1499
1500 init_error:
1501 ace_init_cleanup(dev);
1502 return ecode;
1503}
1504
1505
1506static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1507{
1508 struct ace_private *ap = netdev_priv(dev);
1509 struct ace_regs __iomem *regs = ap->regs;
1510 int board_idx = ap->board_idx;
1511
1512 if (board_idx >= 0) {
1513 if (!jumbo) {
1514 if (!tx_coal_tick[board_idx])
1515 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1516 if (!max_tx_desc[board_idx])
1517 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1518 if (!rx_coal_tick[board_idx])
1519 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1520 if (!max_rx_desc[board_idx])
1521 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1522 if (!tx_ratio[board_idx])
1523 writel(DEF_TX_RATIO, &regs->TxBufRat);
1524 } else {
1525 if (!tx_coal_tick[board_idx])
1526 writel(DEF_JUMBO_TX_COAL,
1527 &regs->TuneTxCoalTicks);
1528 if (!max_tx_desc[board_idx])
1529 writel(DEF_JUMBO_TX_MAX_DESC,
1530 &regs->TuneMaxTxDesc);
1531 if (!rx_coal_tick[board_idx])
1532 writel(DEF_JUMBO_RX_COAL,
1533 &regs->TuneRxCoalTicks);
1534 if (!max_rx_desc[board_idx])
1535 writel(DEF_JUMBO_RX_MAX_DESC,
1536 &regs->TuneMaxRxDesc);
1537 if (!tx_ratio[board_idx])
1538 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1539 }
1540 }
1541}
1542
1543
1544static void ace_watchdog(struct net_device *data)
1545{
1546 struct net_device *dev = data;
1547 struct ace_private *ap = netdev_priv(dev);
1548 struct ace_regs __iomem *regs = ap->regs;
1549
1550 /*
1551 * We haven't received a stats update event for more than 2.5
1552 * seconds and there is data in the transmit queue, thus we
25985edc 1553 * assume the card is stuck.
1da177e4
LT		 1554 */
1555 if (*ap->tx_csm != ap->tx_ret_csm) {
1556 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1557 dev->name, (unsigned int)readl(&regs->HostCtrl));
1558 /* This can happen due to ieee flow control. */
1559 } else {
1560 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1561 dev->name);
1562#if 0
1563 netif_wake_queue(dev);
1564#endif
1565 }
1566}
1567
1568
427e21fa 1569static void ace_tasklet(unsigned long arg)
1da177e4 1570{
427e21fa 1571 struct net_device *dev = (struct net_device *) arg;
1572 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1573 int cur_size;
1574
1575 cur_size = atomic_read(&ap->cur_rx_bufs);
1576 if ((cur_size < RX_LOW_STD_THRES) &&
1577 !test_and_set_bit(0, &ap->std_refill_busy)) {
1578#ifdef DEBUG
1579 printk("refilling buffers (current %i)\n", cur_size);
1580#endif
427e21fa 1581 ace_load_std_rx_ring(dev, RX_RING_SIZE - cur_size);
1da177e4
LT		 1582 }
1583
1584 if (ap->version >= 2) {
1585 cur_size = atomic_read(&ap->cur_mini_bufs);
1586 if ((cur_size < RX_LOW_MINI_THRES) &&
1587 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1588#ifdef DEBUG
1589 printk("refilling mini buffers (current %i)\n",
1590 cur_size);
1591#endif
427e21fa 1592 ace_load_mini_rx_ring(dev, RX_MINI_SIZE - cur_size);
1da177e4
LT		 1593 }
1594 }
1595
1596 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1597 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1598 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1599#ifdef DEBUG
1600 printk("refilling jumbo buffers (current %i)\n", cur_size);
1601#endif
427e21fa 1602 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE - cur_size);
1da177e4
LT		 1603 }
1604 ap->tasklet_pending = 0;
1605}
1606
1607
1608/*
1609 * Copy the contents of the NIC's trace buffer to kernel memory.
1610 */
1611static void ace_dump_trace(struct ace_private *ap)
1612{
1613#if 0
1614 if (!ap->trace_buf)
1615 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1616 return;
1617#endif
1618}
1619
1620
1621/*
1622 * Load the standard rx ring.
1623 *
1624 * Loading rings is safe without holding the spin lock since this is
1625 * done only before the device is enabled, thus no interrupts are
1626 * generated and by the interrupt handler/tasklet handler.
1627 */
427e21fa 1628static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs)
1da177e4 1629{
427e21fa 1630 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1631 struct ace_regs __iomem *regs = ap->regs;
1632 short i, idx;
6aa20a22 1633
1da177e4
LT		 1634
1635 prefetchw(&ap->cur_rx_bufs);
1636
1637 idx = ap->rx_std_skbprd;
1638
1639 for (i = 0; i < nr_bufs; i++) {
1640 struct sk_buff *skb;
1641 struct rx_desc *rd;
1642 dma_addr_t mapping;
1643
427e21fa 1644 skb = netdev_alloc_skb_ip_align(dev, ACE_STD_BUFSIZE);
1da177e4
LT		 1645 if (!skb)
1646 break;
1647
1da177e4
LT		 1648 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1649 offset_in_page(skb->data),
1650 ACE_STD_BUFSIZE,
1651 PCI_DMA_FROMDEVICE);
1652 ap->skb->rx_std_skbuff[idx].skb = skb;
430e55b1 1653 dma_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1da177e4
LT		 1654 mapping, mapping);
1655
1656 rd = &ap->rx_std_ring[idx];
1657 set_aceaddr(&rd->addr, mapping);
1658 rd->size = ACE_STD_BUFSIZE;
1659 rd->idx = idx;
1660 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1661 }
1662
1663 if (!i)
1664 goto error_out;
1665
1666 atomic_add(i, &ap->cur_rx_bufs);
1667 ap->rx_std_skbprd = idx;
1668
1669 if (ACE_IS_TIGON_I(ap)) {
1670 struct cmd cmd;
1671 cmd.evt = C_SET_RX_PRD_IDX;
1672 cmd.code = 0;
1673 cmd.idx = ap->rx_std_skbprd;
1674 ace_issue_cmd(regs, &cmd);
1675 } else {
1676 writel(idx, &regs->RxStdPrd);
1677 wmb();
1678 }
1679
1680 out:
1681 clear_bit(0, &ap->std_refill_busy);
1682 return;
1683
1684 error_out:
1685 printk(KERN_INFO "Out of memory when allocating "
1686 "standard receive buffers\n");
1687 goto out;
1688}
1689
1690
427e21fa 1691static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs)
1da177e4 1692{
427e21fa 1693 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1694 struct ace_regs __iomem *regs = ap->regs;
1695 short i, idx;
1696
1697 prefetchw(&ap->cur_mini_bufs);
1698
1699 idx = ap->rx_mini_skbprd;
1700 for (i = 0; i < nr_bufs; i++) {
1701 struct sk_buff *skb;
1702 struct rx_desc *rd;
1703 dma_addr_t mapping;
1704
427e21fa 1705 skb = netdev_alloc_skb_ip_align(dev, ACE_MINI_BUFSIZE);
1da177e4
LT		 1706 if (!skb)
1707 break;
1708
1da177e4
LT		 1709 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1710 offset_in_page(skb->data),
1711 ACE_MINI_BUFSIZE,
1712 PCI_DMA_FROMDEVICE);
1713 ap->skb->rx_mini_skbuff[idx].skb = skb;
430e55b1 1714 dma_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1da177e4
LT		 1715 mapping, mapping);
1716
1717 rd = &ap->rx_mini_ring[idx];
1718 set_aceaddr(&rd->addr, mapping);
1719 rd->size = ACE_MINI_BUFSIZE;
1720 rd->idx = idx;
1721 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1722 }
1723
1724 if (!i)
1725 goto error_out;
1726
1727 atomic_add(i, &ap->cur_mini_bufs);
1728
1729 ap->rx_mini_skbprd = idx;
1730
1731 writel(idx, &regs->RxMiniPrd);
1732 wmb();
1733
1734 out:
1735 clear_bit(0, &ap->mini_refill_busy);
1736 return;
1737 error_out:
1738 printk(KERN_INFO "Out of memory when allocating "
1739 "mini receive buffers\n");
1740 goto out;
1741}
1742
1743
1744/*
1745 * Load the jumbo rx ring, this may happen at any time if the MTU
1746 * is changed to a value > 1500.
1747 */
427e21fa 1748static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs)
1da177e4 1749{
427e21fa 1750 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1751 struct ace_regs __iomem *regs = ap->regs;
1752 short i, idx;
1753
1754 idx = ap->rx_jumbo_skbprd;
1755
1756 for (i = 0; i < nr_bufs; i++) {
1757 struct sk_buff *skb;
1758 struct rx_desc *rd;
1759 dma_addr_t mapping;
1760
427e21fa 1761 skb = netdev_alloc_skb_ip_align(dev, ACE_JUMBO_BUFSIZE);
1da177e4
LT		 1762 if (!skb)
1763 break;
1764
1da177e4
LT		 1765 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1766 offset_in_page(skb->data),
1767 ACE_JUMBO_BUFSIZE,
1768 PCI_DMA_FROMDEVICE);
1769 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
430e55b1 1770 dma_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1da177e4
LT		 1771 mapping, mapping);
1772
1773 rd = &ap->rx_jumbo_ring[idx];
1774 set_aceaddr(&rd->addr, mapping);
1775 rd->size = ACE_JUMBO_BUFSIZE;
1776 rd->idx = idx;
1777 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1778 }
1779
1780 if (!i)
1781 goto error_out;
1782
1783 atomic_add(i, &ap->cur_jumbo_bufs);
1784 ap->rx_jumbo_skbprd = idx;
1785
1786 if (ACE_IS_TIGON_I(ap)) {
1787 struct cmd cmd;
1788 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1789 cmd.code = 0;
1790 cmd.idx = ap->rx_jumbo_skbprd;
1791 ace_issue_cmd(regs, &cmd);
1792 } else {
1793 writel(idx, &regs->RxJumboPrd);
1794 wmb();
1795 }
1796
1797 out:
1798 clear_bit(0, &ap->jumbo_refill_busy);
1799 return;
1800 error_out:
1801 if (net_ratelimit())
1802 printk(KERN_INFO "Out of memory when allocating "
1803 "jumbo receive buffers\n");
1804 goto out;
1805}
1806
1807
1808/*
1809 * All events are considered to be slow (RX/TX ints do not generate
1810 * events) and are handled here, outside the main interrupt handler,
1811 * to reduce the size of the handler.
1812 */
1813static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1814{
1815 struct ace_private *ap;
1816
1817 ap = netdev_priv(dev);
1818
1819 while (evtcsm != evtprd) {
1820 switch (ap->evt_ring[evtcsm].evt) {
1821 case E_FW_RUNNING:
1822 printk(KERN_INFO "%s: Firmware up and running\n",
1823 ap->name);
1824 ap->fw_running = 1;
1825 wmb();
1826 break;
1827 case E_STATS_UPDATED:
1828 break;
1829 case E_LNK_STATE:
1830 {
1831 u16 code = ap->evt_ring[evtcsm].code;
1832 switch (code) {
1833 case E_C_LINK_UP:
1834 {
1835 u32 state = readl(&ap->regs->GigLnkState);
1836 printk(KERN_WARNING "%s: Optical link UP "
1837 "(%s Duplex, Flow Control: %s%s)\n",
1838 ap->name,
1839 state & LNK_FULL_DUPLEX ? "Full":"Half",
1840 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1841 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1842 break;
1843 }
1844 case E_C_LINK_DOWN:
1845 printk(KERN_WARNING "%s: Optical link DOWN\n",
1846 ap->name);
1847 break;
1848 case E_C_LINK_10_100:
1849 printk(KERN_WARNING "%s: 10/100BaseT link "
1850 "UP\n", ap->name);
1851 break;
1852 default:
1853 printk(KERN_ERR "%s: Unknown optical link "
1854 "state %02x\n", ap->name, code);
1855 }
1856 break;
1857 }
1858 case E_ERROR:
1859 switch(ap->evt_ring[evtcsm].code) {
1860 case E_C_ERR_INVAL_CMD:
1861 printk(KERN_ERR "%s: invalid command error\n",
1862 ap->name);
1863 break;
1864 case E_C_ERR_UNIMP_CMD:
1865 printk(KERN_ERR "%s: unimplemented command "
1866 "error\n", ap->name);
1867 break;
1868 case E_C_ERR_BAD_CFG:
1869 printk(KERN_ERR "%s: bad config error\n",
1870 ap->name);
1871 break;
1872 default:
1873 printk(KERN_ERR "%s: unknown error %02x\n",
1874 ap->name, ap->evt_ring[evtcsm].code);
1875 }
1876 break;
1877 case E_RESET_JUMBO_RNG:
1878 {
1879 int i;
1880 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1881 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1882 ap->rx_jumbo_ring[i].size = 0;
1883 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1884 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1885 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1886 }
1887 }
1888
1889 if (ACE_IS_TIGON_I(ap)) {
1890 struct cmd cmd;
1891 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1892 cmd.code = 0;
1893 cmd.idx = 0;
1894 ace_issue_cmd(ap->regs, &cmd);
1895 } else {
1896 writel(0, &((ap->regs)->RxJumboPrd));
1897 wmb();
1898 }
1899
1900 ap->jumbo = 0;
1901 ap->rx_jumbo_skbprd = 0;
1902 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1903 ap->name);
1904 clear_bit(0, &ap->jumbo_refill_busy);
1905 break;
1906 }
1907 default:
1908 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1909 ap->name, ap->evt_ring[evtcsm].evt);
1910 }
1911 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1912 }
1913
1914 return evtcsm;
1915}
1916
1917
1918static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1919{
1920 struct ace_private *ap = netdev_priv(dev);
1921 u32 idx;
1922 int mini_count = 0, std_count = 0;
1923
1924 idx = rxretcsm;
1925
1926 prefetchw(&ap->cur_rx_bufs);
1927 prefetchw(&ap->cur_mini_bufs);
6aa20a22 1928
1da177e4
LT		 1929 while (idx != rxretprd) {
1930 struct ring_info *rip;
1931 struct sk_buff *skb;
1932 struct rx_desc *rxdesc, *retdesc;
1933 u32 skbidx;
1934 int bd_flags, desc_type, mapsize;
1935 u16 csum;
1936
1937
1938 /* make sure the rx descriptor isn't read before rxretprd */
6aa20a22 1939 if (idx == rxretcsm)
1da177e4
LT		 1940 rmb();
1941
1942 retdesc = &ap->rx_return_ring[idx];
1943 skbidx = retdesc->idx;
1944 bd_flags = retdesc->flags;
1945 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1946
1947 switch(desc_type) {
1948 /*
1949 * Normal frames do not have any flags set
1950 *
1951 * Mini and normal frames arrive frequently,
1952 * so use a local counter to avoid doing
1953 * atomic operations for each packet arriving.
1954 */
1955 case 0:
1956 rip = &ap->skb->rx_std_skbuff[skbidx];
1957 mapsize = ACE_STD_BUFSIZE;
1958 rxdesc = &ap->rx_std_ring[skbidx];
1959 std_count++;
1960 break;
1961 case BD_FLG_JUMBO:
1962 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1963 mapsize = ACE_JUMBO_BUFSIZE;
1964 rxdesc = &ap->rx_jumbo_ring[skbidx];
1965 atomic_dec(&ap->cur_jumbo_bufs);
1966 break;
1967 case BD_FLG_MINI:
1968 rip = &ap->skb->rx_mini_skbuff[skbidx];
1969 mapsize = ACE_MINI_BUFSIZE;
1970 rxdesc = &ap->rx_mini_ring[skbidx];
6aa20a22 1971 mini_count++;
1da177e4
LT		 1972 break;
1973 default:
1974 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
1975 "returned by NIC\n", dev->name,
1976 retdesc->flags);
1977 goto error;
1978 }
1979
1980 skb = rip->skb;
1981 rip->skb = NULL;
1982 pci_unmap_page(ap->pdev,
430e55b1 1983 dma_unmap_addr(rip, mapping),
1da177e4
LT		 1984 mapsize,
1985 PCI_DMA_FROMDEVICE);
1986 skb_put(skb, retdesc->size);
1987
1988 /*
1989 * Fly baby, fly!
1990 */
1991 csum = retdesc->tcp_udp_csum;
1992
1da177e4
LT		 1993 skb->protocol = eth_type_trans(skb, dev);
1994
1995 /*
1996 * Instead of forcing the poor tigon mips cpu to calculate
1997 * pseudo hdr checksum, we do this ourselves.
1998 */
1999 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2000 skb->csum = htons(csum);
84fa7933 2001 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 2002 } else {
bc8acf2c 2003 skb_checksum_none_assert(skb);
1da177e4
LT		 2004 }
2005
2006 /* send it up */
08dddfc3 2007 if ((bd_flags & BD_FLG_VLAN_TAG))
86a9bad3 2008 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), retdesc->vlan);
08dddfc3 2009 netif_rx(skb);
1da177e4 2010
966e37bc
PZ		 2011 dev->stats.rx_packets++;
2012 dev->stats.rx_bytes += retdesc->size;
1da177e4
LT		 2013
2014 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2015 }
2016
2017 atomic_sub(std_count, &ap->cur_rx_bufs);
2018 if (!ACE_IS_TIGON_I(ap))
2019 atomic_sub(mini_count, &ap->cur_mini_bufs);
2020
2021 out:
2022 /*
2023 * According to the documentation RxRetCsm is obsolete with
2024 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2025 */
2026 if (ACE_IS_TIGON_I(ap)) {
2027 writel(idx, &ap->regs->RxRetCsm);
2028 }
2029 ap->cur_rx = idx;
2030
2031 return;
2032 error:
2033 idx = rxretprd;
2034 goto out;
2035}
2036
2037
2038static inline void ace_tx_int(struct net_device *dev,
2039 u32 txcsm, u32 idx)
2040{
2041 struct ace_private *ap = netdev_priv(dev);
2042
2043 do {
2044 struct sk_buff *skb;
1da177e4
LT		 2045 struct tx_ring_info *info;
2046
2047 info = ap->skb->tx_skbuff + idx;
2048 skb = info->skb;
1da177e4 2049
07e7de8f
FT		 2050 if (dma_unmap_len(info, maplen)) {
2051 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
430e55b1 2052 dma_unmap_len(info, maplen),
1da177e4 2053 PCI_DMA_TODEVICE);
07e7de8f 2054 dma_unmap_len_set(info, maplen, 0);
1da177e4
LT		 2055 }
2056
2057 if (skb) {
966e37bc
PZ		 2058 dev->stats.tx_packets++;
2059 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 2060 dev_kfree_skb_irq(skb);
2061 info->skb = NULL;
2062 }
2063
2064 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2065 } while (idx != txcsm);
2066
2067 if (netif_queue_stopped(dev))
2068 netif_wake_queue(dev);
2069
2070 wmb();
2071 ap->tx_ret_csm = txcsm;
2072
2073 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2074 *
2075 * We could try to make it before. In this case we would get
2076 * the following race condition: hard_start_xmit on other cpu
2077 * enters after we advanced tx_ret_csm and fills space,
2078 * which we have just freed, so that we make illegal device wakeup.
2079 * There is no good way to workaround this (at entry
2080 * to ace_start_xmit detects this condition and prevents
2081 * ring corruption, but it is not a good workaround.)
2082 *
2083 * When tx_ret_csm is advanced after, we wake up device _only_
2084 * if we really have some space in ring (though the core doing
2085 * hard_start_xmit can see full ring for some period and has to
2086 * synchronize.) Superb.
2087 * BUT! We get another subtle race condition. hard_start_xmit
2088 * may think that ring is full between wakeup and advancing
2089 * tx_ret_csm and will stop device instantly! It is not so bad.
2090 * We are guaranteed that there is something in ring, so that
2091 * the next irq will resume transmission. To speedup this we could
2092 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2093 * (see ace_start_xmit).
2094 *
2095 * Well, this dilemma exists in all lock-free devices.
2096 * We, following scheme used in drivers by Donald Becker,
2097 * select the least dangerous.
2098 * --ANK
2099 */
2100}
2101
2102
7d12e780 2103static irqreturn_t ace_interrupt(int irq, void *dev_id)
1da177e4
LT		 2104{
2105 struct net_device *dev = (struct net_device *)dev_id;
2106 struct ace_private *ap = netdev_priv(dev);
2107 struct ace_regs __iomem *regs = ap->regs;
2108 u32 idx;
2109 u32 txcsm, rxretcsm, rxretprd;
2110 u32 evtcsm, evtprd;
2111
2112 /*
2113 * In case of PCI shared interrupts or spurious interrupts,
2114 * we want to make sure it is actually our interrupt before
2115 * spending any time in here.
2116 */
2117 if (!(readl(&regs->HostCtrl) & IN_INT))
2118 return IRQ_NONE;
2119
2120 /*
2121 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2122 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2123 * writel(0, &regs->Mb0Lo).
2124 *
2125 * "IRQ avoidance" recommended in docs applies to IRQs served
2126 * threads and it is wrong even for that case.
2127 */
2128 writel(0, &regs->Mb0Lo);
2129 readl(&regs->Mb0Lo);
2130
2131 /*
2132 * There is no conflict between transmit handling in
2133 * start_xmit and receive processing, thus there is no reason
2134 * to take a spin lock for RX handling. Wait until we start
2135 * working on the other stuff - hey we don't need a spin lock
2136 * anymore.
2137 */
2138 rxretprd = *ap->rx_ret_prd;
2139 rxretcsm = ap->cur_rx;
2140
2141 if (rxretprd != rxretcsm)
2142 ace_rx_int(dev, rxretprd, rxretcsm);
2143
2144 txcsm = *ap->tx_csm;
2145 idx = ap->tx_ret_csm;
2146
2147 if (txcsm != idx) {
2148 /*
2149 * If each skb takes only one descriptor this check degenerates
2150 * to identity, because new space has just been opened.
2151 * But if skbs are fragmented we must check that this index
2152 * update releases enough of space, otherwise we just
2153 * wait for device to make more work.
2154 */
2155 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2156 ace_tx_int(dev, txcsm, idx);
2157 }
2158
2159 evtcsm = readl(&regs->EvtCsm);
2160 evtprd = *ap->evt_prd;
2161
2162 if (evtcsm != evtprd) {
2163 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2164 writel(evtcsm, &regs->EvtCsm);
2165 }
2166
2167 /*
2168 * This has to go last in the interrupt handler and run with
2169 * the spin lock released ... what lock?
2170 */
2171 if (netif_running(dev)) {
2172 int cur_size;
2173 int run_tasklet = 0;
2174
2175 cur_size = atomic_read(&ap->cur_rx_bufs);
2176 if (cur_size < RX_LOW_STD_THRES) {
2177 if ((cur_size < RX_PANIC_STD_THRES) &&
2178 !test_and_set_bit(0, &ap->std_refill_busy)) {
2179#ifdef DEBUG
2180 printk("low on std buffers %i\n", cur_size);
2181#endif
427e21fa 2182 ace_load_std_rx_ring(dev,
1da177e4
LT		 2183 RX_RING_SIZE - cur_size);
2184 } else
2185 run_tasklet = 1;
2186 }
2187
2188 if (!ACE_IS_TIGON_I(ap)) {
2189 cur_size = atomic_read(&ap->cur_mini_bufs);
2190 if (cur_size < RX_LOW_MINI_THRES) {
2191 if ((cur_size < RX_PANIC_MINI_THRES) &&
2192 !test_and_set_bit(0,
2193 &ap->mini_refill_busy)) {
2194#ifdef DEBUG
2195 printk("low on mini buffers %i\n",
2196 cur_size);
2197#endif
427e21fa 2198 ace_load_mini_rx_ring(dev,
2199 RX_MINI_SIZE - cur_size);
1da177e4
LT		 2200 } else
2201 run_tasklet = 1;
2202 }
2203 }
2204
2205 if (ap->jumbo) {
2206 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2207 if (cur_size < RX_LOW_JUMBO_THRES) {
2208 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2209 !test_and_set_bit(0,
2210 &ap->jumbo_refill_busy)){
2211#ifdef DEBUG
2212 printk("low on jumbo buffers %i\n",
2213 cur_size);
2214#endif
427e21fa 2215 ace_load_jumbo_rx_ring(dev,
2216 RX_JUMBO_SIZE - cur_size);
1da177e4
LT		 2217 } else
2218 run_tasklet = 1;
2219 }
2220 }
2221 if (run_tasklet && !ap->tasklet_pending) {
2222 ap->tasklet_pending = 1;
2223 tasklet_schedule(&ap->ace_tasklet);
2224 }
2225 }
2226
2227 return IRQ_HANDLED;
2228}
2229
1da177e4
LT		 2230static int ace_open(struct net_device *dev)
2231{
2232 struct ace_private *ap = netdev_priv(dev);
2233 struct ace_regs __iomem *regs = ap->regs;
2234 struct cmd cmd;
2235
2236 if (!(ap->fw_running)) {
2237 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2238 return -EBUSY;
2239 }
2240
2241 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2242
2243 cmd.evt = C_CLEAR_STATS;
2244 cmd.code = 0;
2245 cmd.idx = 0;
2246 ace_issue_cmd(regs, &cmd);
2247
2248 cmd.evt = C_HOST_STATE;
2249 cmd.code = C_C_STACK_UP;
2250 cmd.idx = 0;
2251 ace_issue_cmd(regs, &cmd);
2252
2253 if (ap->jumbo &&
2254 !test_and_set_bit(0, &ap->jumbo_refill_busy))
427e21fa 2255 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
1da177e4
LT		 2256
2257 if (dev->flags & IFF_PROMISC) {
2258 cmd.evt = C_SET_PROMISC_MODE;
2259 cmd.code = C_C_PROMISC_ENABLE;
2260 cmd.idx = 0;
2261 ace_issue_cmd(regs, &cmd);
2262
2263 ap->promisc = 1;
2264 }else
2265 ap->promisc = 0;
2266 ap->mcast_all = 0;
2267
2268#if 0
2269 cmd.evt = C_LNK_NEGOTIATION;
2270 cmd.code = 0;
2271 cmd.idx = 0;
2272 ace_issue_cmd(regs, &cmd);
2273#endif
2274
2275 netif_start_queue(dev);
2276
2277 /*
2278 * Setup the bottom half rx ring refill handler
2279 */
2280 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2281 return 0;
2282}
2283
2284
2285static int ace_close(struct net_device *dev)
2286{
2287 struct ace_private *ap = netdev_priv(dev);
2288 struct ace_regs __iomem *regs = ap->regs;
2289 struct cmd cmd;
2290 unsigned long flags;
2291 short i;
2292
2293 /*
2294 * Without (or before) releasing irq and stopping hardware, this
2295 * is an absolute non-sense, by the way. It will be reset instantly
2296 * by the first irq.
2297 */
2298 netif_stop_queue(dev);
2299
6aa20a22 2300
1da177e4
LT		 2301 if (ap->promisc) {
2302 cmd.evt = C_SET_PROMISC_MODE;
2303 cmd.code = C_C_PROMISC_DISABLE;
2304 cmd.idx = 0;
2305 ace_issue_cmd(regs, &cmd);
2306 ap->promisc = 0;
2307 }
2308
2309 cmd.evt = C_HOST_STATE;
2310 cmd.code = C_C_STACK_DOWN;
2311 cmd.idx = 0;
2312 ace_issue_cmd(regs, &cmd);
2313
2314 tasklet_kill(&ap->ace_tasklet);
2315
2316 /*
2317 * Make sure one CPU is not processing packets while
2318 * buffers are being released by another.
2319 */
2320
2321 local_irq_save(flags);
2322 ace_mask_irq(dev);
2323
2324 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2325 struct sk_buff *skb;
1da177e4
LT		 2326 struct tx_ring_info *info;
2327
2328 info = ap->skb->tx_skbuff + i;
2329 skb = info->skb;
1da177e4 2330
07e7de8f 2331 if (dma_unmap_len(info, maplen)) {
1da177e4 2332 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb
SH		 2333 /* NB: TIGON_1 is special, tx_ring is in io space */
2334 struct tx_desc __iomem *tx;
2335 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
1da177e4
LT		 2336 writel(0, &tx->addr.addrhi);
2337 writel(0, &tx->addr.addrlo);
2338 writel(0, &tx->flagsize);
2339 } else
2340 memset(ap->tx_ring + i, 0,
2341 sizeof(struct tx_desc));
07e7de8f 2342 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
430e55b1 2343 dma_unmap_len(info, maplen),
1da177e4 2344 PCI_DMA_TODEVICE);
07e7de8f 2345 dma_unmap_len_set(info, maplen, 0);
1da177e4
LT		 2346 }
2347 if (skb) {
2348 dev_kfree_skb(skb);
2349 info->skb = NULL;
2350 }
2351 }
2352
2353 if (ap->jumbo) {
2354 cmd.evt = C_RESET_JUMBO_RNG;
2355 cmd.code = 0;
2356 cmd.idx = 0;
2357 ace_issue_cmd(regs, &cmd);
2358 }
2359
2360 ace_unmask_irq(dev);
2361 local_irq_restore(flags);
2362
2363 return 0;
2364}
2365
2366
2367static inline dma_addr_t
2368ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2369 struct sk_buff *tail, u32 idx)
2370{
2371 dma_addr_t mapping;
2372 struct tx_ring_info *info;
2373
2374 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2375 offset_in_page(skb->data),
2376 skb->len, PCI_DMA_TODEVICE);
2377
2378 info = ap->skb->tx_skbuff + idx;
2379 info->skb = tail;
430e55b1
FT		 2380 dma_unmap_addr_set(info, mapping, mapping);
2381 dma_unmap_len_set(info, maplen, skb->len);
1da177e4
LT		 2382 return mapping;
2383}
2384
2385
2386static inline void
2387ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2388 u32 flagsize, u32 vlan_tag)
2389{
2390#if !USE_TX_COAL_NOW
2391 flagsize &= ~BD_FLG_COAL_NOW;
2392#endif
2393
2394 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 2395 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
1da177e4
LT		 2396 writel(addr >> 32, &io->addr.addrhi);
2397 writel(addr & 0xffffffff, &io->addr.addrlo);
2398 writel(flagsize, &io->flagsize);
1da177e4 2399 writel(vlan_tag, &io->vlanres);
1da177e4
LT		 2400 } else {
2401 desc->addr.addrhi = addr >> 32;
2402 desc->addr.addrlo = addr;
2403 desc->flagsize = flagsize;
1da177e4 2404 desc->vlanres = vlan_tag;
1da177e4
LT		 2405 }
2406}
2407
2408
61357325
SH		 2409static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
2410 struct net_device *dev)
1da177e4
LT		 2411{
2412 struct ace_private *ap = netdev_priv(dev);
2413 struct ace_regs __iomem *regs = ap->regs;
2414 struct tx_desc *desc;
2415 u32 idx, flagsize;
2416 unsigned long maxjiff = jiffies + 3*HZ;
2417
2418restart:
2419 idx = ap->tx_prd;
2420
2421 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2422 goto overflow;
2423
2424 if (!skb_shinfo(skb)->nr_frags) {
2425 dma_addr_t mapping;
2426 u32 vlan_tag = 0;
2427
2428 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2429 flagsize = (skb->len << 16) | (BD_FLG_END);
84fa7933 2430 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 2431 flagsize |= BD_FLG_TCP_UDP_SUM;
df8a39de 2432 if (skb_vlan_tag_present(skb)) {
1da177e4 2433 flagsize |= BD_FLG_VLAN_TAG;
df8a39de 2434 vlan_tag = skb_vlan_tag_get(skb);
1da177e4 2435 }
1da177e4
LT		 2436 desc = ap->tx_ring + idx;
2437 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2438
2439 /* Look at ace_tx_int for explanations. */
2440 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2441 flagsize |= BD_FLG_COAL_NOW;
2442
2443 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2444 } else {
2445 dma_addr_t mapping;
2446 u32 vlan_tag = 0;
2447 int i, len = 0;
2448
2449 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2450 flagsize = (skb_headlen(skb) << 16);
84fa7933 2451 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 2452 flagsize |= BD_FLG_TCP_UDP_SUM;
df8a39de 2453 if (skb_vlan_tag_present(skb)) {
1da177e4 2454 flagsize |= BD_FLG_VLAN_TAG;
df8a39de 2455 vlan_tag = skb_vlan_tag_get(skb);
1da177e4 2456 }
1da177e4
LT		 2457
2458 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2459
2460 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2461
2462 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 2463 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1da177e4
LT		 2464 struct tx_ring_info *info;
2465
9e903e08 2466 len += skb_frag_size(frag);
1da177e4
LT		 2467 info = ap->skb->tx_skbuff + idx;
2468 desc = ap->tx_ring + idx;
2469
c4c8d579 2470 mapping = skb_frag_dma_map(&ap->pdev->dev, frag, 0,
9e903e08 2471 skb_frag_size(frag),
5d6bcdfe 2472 DMA_TO_DEVICE);
1da177e4 2473
9e903e08 2474 flagsize = skb_frag_size(frag) << 16;
84fa7933 2475 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2476 flagsize |= BD_FLG_TCP_UDP_SUM;
2477 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2478
2479 if (i == skb_shinfo(skb)->nr_frags - 1) {
2480 flagsize |= BD_FLG_END;
2481 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2482 flagsize |= BD_FLG_COAL_NOW;
2483
2484 /*
2485 * Only the last fragment frees
2486 * the skb!
2487 */
2488 info->skb = skb;
2489 } else {
2490 info->skb = NULL;
2491 }
430e55b1 2492 dma_unmap_addr_set(info, mapping, mapping);
9e903e08 2493 dma_unmap_len_set(info, maplen, skb_frag_size(frag));
1da177e4
LT		 2494 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2495 }
2496 }
2497
2498 wmb();
2499 ap->tx_prd = idx;
2500 ace_set_txprd(regs, ap, idx);
2501
2502 if (flagsize & BD_FLG_COAL_NOW) {
2503 netif_stop_queue(dev);
2504
2505 /*
2506 * A TX-descriptor producer (an IRQ) might have gotten
25985edc 2507 * between, making the ring free again. Since xmit is
1da177e4
LT		 2508 * serialized, this is the only situation we have to
2509 * re-test.
2510 */
2511 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2512 netif_wake_queue(dev);
2513 }
2514
1da177e4
LT		 2515 return NETDEV_TX_OK;
2516
2517overflow:
2518 /*
2519 * This race condition is unavoidable with lock-free drivers.
2520 * We wake up the queue _before_ tx_prd is advanced, so that we can
2521 * enter hard_start_xmit too early, while tx ring still looks closed.
2522 * This happens ~1-4 times per 100000 packets, so that we can allow
2523 * to loop syncing to other CPU. Probably, we need an additional
2524 * wmb() in ace_tx_intr as well.
2525 *
2526 * Note that this race is relieved by reserving one more entry
2527 * in tx ring than it is necessary (see original non-SG driver).
2528 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2529 * is already overkill.
2530 *
2531 * Alternative is to return with 1 not throttling queue. In this
2532 * case loop becomes longer, no more useful effects.
2533 */
2534 if (time_before(jiffies, maxjiff)) {
2535 barrier();
2536 cpu_relax();
2537 goto restart;
2538 }
6aa20a22 2539
1da177e4
LT		 2540 /* The ring is stuck full. */
2541 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2542 return NETDEV_TX_BUSY;
2543}
2544
2545
2546static int ace_change_mtu(struct net_device *dev, int new_mtu)
2547{
2548 struct ace_private *ap = netdev_priv(dev);
2549 struct ace_regs __iomem *regs = ap->regs;
2550
2551 if (new_mtu > ACE_JUMBO_MTU)
2552 return -EINVAL;
2553
2554 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2555 dev->mtu = new_mtu;
2556
2557 if (new_mtu > ACE_STD_MTU) {
2558 if (!(ap->jumbo)) {
2559 printk(KERN_INFO "%s: Enabling Jumbo frame "
2560 "support\n", dev->name);
2561 ap->jumbo = 1;
2562 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
427e21fa 2563 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
1da177e4
LT		 2564 ace_set_rxtx_parms(dev, 1);
2565 }
2566 } else {
2567 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2568 ace_sync_irq(dev->irq);
2569 ace_set_rxtx_parms(dev, 0);
2570 if (ap->jumbo) {
2571 struct cmd cmd;
2572
2573 cmd.evt = C_RESET_JUMBO_RNG;
2574 cmd.code = 0;
2575 cmd.idx = 0;
2576 ace_issue_cmd(regs, &cmd);
2577 }
2578 }
2579
2580 return 0;
2581}
2582
2583static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2584{
2585 struct ace_private *ap = netdev_priv(dev);
2586 struct ace_regs __iomem *regs = ap->regs;
2587 u32 link;
2588
2589 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2590 ecmd->supported =
2591 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2592 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2593 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2594 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2595
2596 ecmd->port = PORT_FIBRE;
2597 ecmd->transceiver = XCVR_INTERNAL;
2598
2599 link = readl(&regs->GigLnkState);
2600 if (link & LNK_1000MB)
70739497 2601 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1da177e4
LT		 2602 else {
2603 link = readl(&regs->FastLnkState);
2604 if (link & LNK_100MB)
70739497 2605 ethtool_cmd_speed_set(ecmd, SPEED_100);
1da177e4 2606 else if (link & LNK_10MB)
70739497 2607 ethtool_cmd_speed_set(ecmd, SPEED_10);
1da177e4 2608 else
70739497 2609 ethtool_cmd_speed_set(ecmd, 0);
1da177e4
LT		 2610 }
2611 if (link & LNK_FULL_DUPLEX)
2612 ecmd->duplex = DUPLEX_FULL;
2613 else
2614 ecmd->duplex = DUPLEX_HALF;
2615
2616 if (link & LNK_NEGOTIATE)
2617 ecmd->autoneg = AUTONEG_ENABLE;
2618 else
2619 ecmd->autoneg = AUTONEG_DISABLE;
2620
2621#if 0
2622 /*
2623 * Current struct ethtool_cmd is insufficient
2624 */
2625 ecmd->trace = readl(&regs->TuneTrace);
2626
2627 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2628 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2629#endif
2630 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2631 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2632
2633 return 0;
2634}
2635
2636static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2637{
2638 struct ace_private *ap = netdev_priv(dev);
2639 struct ace_regs __iomem *regs = ap->regs;
2640 u32 link, speed;
2641
2642 link = readl(&regs->GigLnkState);
2643 if (link & LNK_1000MB)
2644 speed = SPEED_1000;
2645 else {
2646 link = readl(&regs->FastLnkState);
2647 if (link & LNK_100MB)
2648 speed = SPEED_100;
2649 else if (link & LNK_10MB)
2650 speed = SPEED_10;
2651 else
2652 speed = SPEED_100;
2653 }
2654
2655 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2656 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2657 if (!ACE_IS_TIGON_I(ap))
2658 link |= LNK_TX_FLOW_CTL_Y;
2659 if (ecmd->autoneg == AUTONEG_ENABLE)
2660 link |= LNK_NEGOTIATE;
25db0338 2661 if (ethtool_cmd_speed(ecmd) != speed) {
1da177e4 2662 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
1258c076 2663 switch (ethtool_cmd_speed(ecmd)) {
1da177e4
LT		 2664 case SPEED_1000:
2665 link |= LNK_1000MB;
2666 break;
2667 case SPEED_100:
2668 link |= LNK_100MB;
2669 break;
2670 case SPEED_10:
2671 link |= LNK_10MB;
2672 break;
2673 }
2674 }
2675
2676 if (ecmd->duplex == DUPLEX_FULL)
2677 link |= LNK_FULL_DUPLEX;
2678
2679 if (link != ap->link) {
2680 struct cmd cmd;
2681 printk(KERN_INFO "%s: Renegotiating link state\n",
2682 dev->name);
2683
2684 ap->link = link;
2685 writel(link, &regs->TuneLink);
2686 if (!ACE_IS_TIGON_I(ap))
2687 writel(link, &regs->TuneFastLink);
2688 wmb();
2689
2690 cmd.evt = C_LNK_NEGOTIATION;
2691 cmd.code = 0;
2692 cmd.idx = 0;
2693 ace_issue_cmd(regs, &cmd);
2694 }
2695 return 0;
2696}
2697
6aa20a22 2698static void ace_get_drvinfo(struct net_device *dev,
1da177e4
LT		 2699 struct ethtool_drvinfo *info)
2700{
2701 struct ace_private *ap = netdev_priv(dev);
2702
2703 strlcpy(info->driver, "acenic", sizeof(info->driver));
6aa20a22 2704 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
949b4254
JS		 2705 ap->firmware_major, ap->firmware_minor,
2706 ap->firmware_fix);
1da177e4
LT		 2707
2708 if (ap->pdev)
6aa20a22 2709 strlcpy(info->bus_info, pci_name(ap->pdev),
1da177e4
LT		 2710 sizeof(info->bus_info));
2711
2712}
2713
2714/*
2715 * Set the hardware MAC address.
2716 */
2717static int ace_set_mac_addr(struct net_device *dev, void *p)
2718{
2719 struct ace_private *ap = netdev_priv(dev);
2720 struct ace_regs __iomem *regs = ap->regs;
2721 struct sockaddr *addr=p;
2722 u8 *da;
2723 struct cmd cmd;
2724
2725 if(netif_running(dev))
2726 return -EBUSY;
2727
2728 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2729
2730 da = (u8 *)dev->dev_addr;
2731
2732 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2733 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2734 &regs->MacAddrLo);
2735
2736 cmd.evt = C_SET_MAC_ADDR;
2737 cmd.code = 0;
2738 cmd.idx = 0;
2739 ace_issue_cmd(regs, &cmd);
2740
2741 return 0;
2742}
2743
2744
2745static void ace_set_multicast_list(struct net_device *dev)
2746{
2747 struct ace_private *ap = netdev_priv(dev);
2748 struct ace_regs __iomem *regs = ap->regs;
2749 struct cmd cmd;
2750
2751 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2752 cmd.evt = C_SET_MULTICAST_MODE;
2753 cmd.code = C_C_MCAST_ENABLE;
2754 cmd.idx = 0;
2755 ace_issue_cmd(regs, &cmd);
2756 ap->mcast_all = 1;
2757 } else if (ap->mcast_all) {
2758 cmd.evt = C_SET_MULTICAST_MODE;
2759 cmd.code = C_C_MCAST_DISABLE;
2760 cmd.idx = 0;
2761 ace_issue_cmd(regs, &cmd);
2762 ap->mcast_all = 0;
2763 }
2764
2765 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2766 cmd.evt = C_SET_PROMISC_MODE;
2767 cmd.code = C_C_PROMISC_ENABLE;
2768 cmd.idx = 0;
2769 ace_issue_cmd(regs, &cmd);
2770 ap->promisc = 1;
2771 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2772 cmd.evt = C_SET_PROMISC_MODE;
2773 cmd.code = C_C_PROMISC_DISABLE;
2774 cmd.idx = 0;
2775 ace_issue_cmd(regs, &cmd);
2776 ap->promisc = 0;
2777 }
2778
2779 /*
2780 * For the time being multicast relies on the upper layers
2781 * filtering it properly. The Firmware does not allow one to
2782 * set the entire multicast list at a time and keeping track of
2783 * it here is going to be messy.
2784 */
4cd24eaf 2785 if (!netdev_mc_empty(dev) && !ap->mcast_all) {
1da177e4
LT		 2786 cmd.evt = C_SET_MULTICAST_MODE;
2787 cmd.code = C_C_MCAST_ENABLE;
2788 cmd.idx = 0;
2789 ace_issue_cmd(regs, &cmd);
2790 }else if (!ap->mcast_all) {
2791 cmd.evt = C_SET_MULTICAST_MODE;
2792 cmd.code = C_C_MCAST_DISABLE;
2793 cmd.idx = 0;
2794 ace_issue_cmd(regs, &cmd);
2795 }
2796}
2797
2798
2799static struct net_device_stats *ace_get_stats(struct net_device *dev)
2800{
2801 struct ace_private *ap = netdev_priv(dev);
2802 struct ace_mac_stats __iomem *mac_stats =
2803 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2804
966e37bc
PZ		 2805 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2806 dev->stats.multicast = readl(&mac_stats->kept_mc);
2807 dev->stats.collisions = readl(&mac_stats->coll);
1da177e4 2808
966e37bc 2809 return &dev->stats;
1da177e4
LT		 2810}
2811
2812
083abbb7 2813static void ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
1dd06ae8 2814 u32 dest, int size)
1da177e4
LT		 2815{
2816 void __iomem *tdest;
1da177e4
LT		 2817 short tsize, i;
2818
2819 if (size <= 0)
2820 return;
2821
2822 while (size > 0) {
2823 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2824 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2825 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2826 (dest & (ACE_WINDOW_SIZE - 1));
2827 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
1da177e4 2828 for (i = 0; i < (tsize / 4); i++) {
949b4254
JS		 2829 /* Firmware is big-endian */
2830 writel(be32_to_cpup(src), tdest);
2831 src++;
2832 tdest += 4;
2833 dest += 4;
2834 size -= 4;
1da177e4 2835 }
1da177e4 2836 }
1da177e4
LT		 2837}
2838
2839
083abbb7 2840static void ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
1da177e4
LT		 2841{
2842 void __iomem *tdest;
2843 short tsize = 0, i;
2844
2845 if (size <= 0)
2846 return;
2847
2848 while (size > 0) {
2849 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2850 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2851 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2852 (dest & (ACE_WINDOW_SIZE - 1));
2853 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2854
2855 for (i = 0; i < (tsize / 4); i++) {
2856 writel(0, tdest + i*4);
2857 }
2858
2859 dest += tsize;
2860 size -= tsize;
2861 }
1da177e4
LT		 2862}
2863
2864
2865/*
2866 * Download the firmware into the SRAM on the NIC
2867 *
2868 * This operation requires the NIC to be halted and is performed with
2869 * interrupts disabled and with the spinlock hold.
2870 */
083abbb7 2871static int ace_load_firmware(struct net_device *dev)
1da177e4 2872{
949b4254
JS		 2873 const struct firmware *fw;
2874 const char *fw_name = "acenic/tg2.bin";
1da177e4
LT		 2875 struct ace_private *ap = netdev_priv(dev);
2876 struct ace_regs __iomem *regs = ap->regs;
949b4254
JS		 2877 const __be32 *fw_data;
2878 u32 load_addr;
2879 int ret;
1da177e4
LT		 2880
2881 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2882 printk(KERN_ERR "%s: trying to download firmware while the "
2883 "CPU is running!\n", ap->name);
2884 return -EFAULT;
2885 }
2886
949b4254
JS		 2887 if (ACE_IS_TIGON_I(ap))
2888 fw_name = "acenic/tg1.bin";
2889
2890 ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2891 if (ret) {
2892 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2893 ap->name, fw_name);
2894 return ret;
2895 }
2896
2897 fw_data = (void *)fw->data;
2898
2899 /* Firmware blob starts with version numbers, followed by
2900 load and start address. Remainder is the blob to be loaded
2901 contiguously from load address. We don't bother to represent
2902 the BSS/SBSS sections any more, since we were clearing the
2903 whole thing anyway. */
2904 ap->firmware_major = fw->data[0];
2905 ap->firmware_minor = fw->data[1];
2906 ap->firmware_fix = fw->data[2];
2907
2908 ap->firmware_start = be32_to_cpu(fw_data[1]);
2909 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2910 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2911 ap->name, ap->firmware_start, fw_name);
2912 ret = -EINVAL;
2913 goto out;
2914 }
2915
2916 load_addr = be32_to_cpu(fw_data[2]);
2917 if (load_addr < 0x4000 || load_addr >= 0x80000) {
2918 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2919 ap->name, load_addr, fw_name);
2920 ret = -EINVAL;
2921 goto out;
2922 }
2923
1da177e4 2924 /*
949b4254
JS		 2925 * Do not try to clear more than 512KiB or we end up seeing
2926 * funny things on NICs with only 512KiB SRAM
1da177e4
LT		 2927 */
2928 ace_clear(regs, 0x2000, 0x80000-0x2000);
949b4254
JS		 2929 ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2930 out:
2931 release_firmware(fw);
2932 return ret;
1da177e4
LT		 2933}
2934
2935
2936/*
2937 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
2938 *
2939 * Accessing the EEPROM is `interesting' to say the least - don't read
2940 * this code right after dinner.
2941 *
2942 * This is all about black magic and bit-banging the device .... I
2943 * wonder in what hospital they have put the guy who designed the i2c
2944 * specs.
2945 *
2946 * Oh yes, this is only the beginning!
2947 *
2948 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
2949 * code i2c readout code by beta testing all my hacks.
2950 */
083abbb7 2951static void eeprom_start(struct ace_regs __iomem *regs)
1da177e4
LT		 2952{
2953 u32 local;
2954
2955 readl(&regs->LocalCtrl);
2956 udelay(ACE_SHORT_DELAY);
2957 local = readl(&regs->LocalCtrl);
2958 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
2959 writel(local, &regs->LocalCtrl);
2960 readl(&regs->LocalCtrl);
2961 mb();
2962 udelay(ACE_SHORT_DELAY);
2963 local |= EEPROM_CLK_OUT;
2964 writel(local, &regs->LocalCtrl);
2965 readl(&regs->LocalCtrl);
2966 mb();
2967 udelay(ACE_SHORT_DELAY);
2968 local &= ~EEPROM_DATA_OUT;
2969 writel(local, &regs->LocalCtrl);
2970 readl(&regs->LocalCtrl);
2971 mb();
2972 udelay(ACE_SHORT_DELAY);
2973 local &= ~EEPROM_CLK_OUT;
2974 writel(local, &regs->LocalCtrl);
2975 readl(&regs->LocalCtrl);
2976 mb();
2977}
2978
2979
083abbb7 2980static void eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
1da177e4
LT		 2981{
2982 short i;
2983 u32 local;
2984
2985 udelay(ACE_SHORT_DELAY);
2986 local = readl(&regs->LocalCtrl);
2987 local &= ~EEPROM_DATA_OUT;
2988 local |= EEPROM_WRITE_ENABLE;
2989 writel(local, &regs->LocalCtrl);
2990 readl(&regs->LocalCtrl);
2991 mb();
2992
2993 for (i = 0; i < 8; i++, magic <<= 1) {
2994 udelay(ACE_SHORT_DELAY);
6aa20a22 2995 if (magic & 0x80)
1da177e4
LT		 2996 local |= EEPROM_DATA_OUT;
2997 else
2998 local &= ~EEPROM_DATA_OUT;
2999 writel(local, &regs->LocalCtrl);
3000 readl(&regs->LocalCtrl);
3001 mb();
3002
3003 udelay(ACE_SHORT_DELAY);
3004 local |= EEPROM_CLK_OUT;
3005 writel(local, &regs->LocalCtrl);
3006 readl(&regs->LocalCtrl);
3007 mb();
3008 udelay(ACE_SHORT_DELAY);
3009 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3010 writel(local, &regs->LocalCtrl);
3011 readl(&regs->LocalCtrl);
3012 mb();
3013 }
3014}
3015
3016
083abbb7 3017static int eeprom_check_ack(struct ace_regs __iomem *regs)
1da177e4
LT		 3018{
3019 int state;
3020 u32 local;
3021
3022 local = readl(&regs->LocalCtrl);
3023 local &= ~EEPROM_WRITE_ENABLE;
3024 writel(local, &regs->LocalCtrl);
3025 readl(&regs->LocalCtrl);
3026 mb();
3027 udelay(ACE_LONG_DELAY);
3028 local |= EEPROM_CLK_OUT;
3029 writel(local, &regs->LocalCtrl);
3030 readl(&regs->LocalCtrl);
3031 mb();
3032 udelay(ACE_SHORT_DELAY);
3033 /* sample data in middle of high clk */
3034 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3035 udelay(ACE_SHORT_DELAY);
3036 mb();
3037 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3038 readl(&regs->LocalCtrl);
3039 mb();
3040
3041 return state;
3042}
3043
3044
083abbb7 3045static void eeprom_stop(struct ace_regs __iomem *regs)
1da177e4
LT		 3046{
3047 u32 local;
3048
3049 udelay(ACE_SHORT_DELAY);
3050 local = readl(&regs->LocalCtrl);
3051 local |= EEPROM_WRITE_ENABLE;
3052 writel(local, &regs->LocalCtrl);
3053 readl(&regs->LocalCtrl);
3054 mb();
3055 udelay(ACE_SHORT_DELAY);
3056 local &= ~EEPROM_DATA_OUT;
3057 writel(local, &regs->LocalCtrl);
3058 readl(&regs->LocalCtrl);
3059 mb();
3060 udelay(ACE_SHORT_DELAY);
3061 local |= EEPROM_CLK_OUT;
3062 writel(local, &regs->LocalCtrl);
3063 readl(&regs->LocalCtrl);
3064 mb();
3065 udelay(ACE_SHORT_DELAY);
3066 local |= EEPROM_DATA_OUT;
3067 writel(local, &regs->LocalCtrl);
3068 readl(&regs->LocalCtrl);
3069 mb();
3070 udelay(ACE_LONG_DELAY);
3071 local &= ~EEPROM_CLK_OUT;
3072 writel(local, &regs->LocalCtrl);
3073 mb();
3074}
3075
3076
3077/*
3078 * Read a whole byte from the EEPROM.
3079 */
1dd06ae8 3080static int read_eeprom_byte(struct net_device *dev, unsigned long offset)
1da177e4
LT		 3081{
3082 struct ace_private *ap = netdev_priv(dev);
3083 struct ace_regs __iomem *regs = ap->regs;
3084 unsigned long flags;
3085 u32 local;
3086 int result = 0;
3087 short i;
3088
1da177e4
LT		 3089 /*
3090 * Don't take interrupts on this CPU will bit banging
3091 * the %#%#@$ I2C device
3092 */
3093 local_irq_save(flags);
3094
3095 eeprom_start(regs);
3096
3097 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3098 if (eeprom_check_ack(regs)) {
3099 local_irq_restore(flags);
3100 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3101 result = -EIO;
3102 goto eeprom_read_error;
3103 }
3104
3105 eeprom_prep(regs, (offset >> 8) & 0xff);
3106 if (eeprom_check_ack(regs)) {
3107 local_irq_restore(flags);
3108 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3109 ap->name);
3110 result = -EIO;
3111 goto eeprom_read_error;
3112 }
3113
3114 eeprom_prep(regs, offset & 0xff);
3115 if (eeprom_check_ack(regs)) {
3116 local_irq_restore(flags);
3117 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3118 ap->name);
3119 result = -EIO;
3120 goto eeprom_read_error;
3121 }
3122
3123 eeprom_start(regs);
3124 eeprom_prep(regs, EEPROM_READ_SELECT);
3125 if (eeprom_check_ack(regs)) {
3126 local_irq_restore(flags);
3127 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3128 ap->name);
3129 result = -EIO;
3130 goto eeprom_read_error;
3131 }
3132
3133 for (i = 0; i < 8; i++) {
3134 local = readl(&regs->LocalCtrl);
3135 local &= ~EEPROM_WRITE_ENABLE;
3136 writel(local, &regs->LocalCtrl);
3137 readl(&regs->LocalCtrl);
3138 udelay(ACE_LONG_DELAY);
3139 mb();
3140 local |= EEPROM_CLK_OUT;
3141 writel(local, &regs->LocalCtrl);
3142 readl(&regs->LocalCtrl);
3143 mb();
3144 udelay(ACE_SHORT_DELAY);
3145 /* sample data mid high clk */
3146 result = (result << 1) |
3147 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3148 udelay(ACE_SHORT_DELAY);
3149 mb();
3150 local = readl(&regs->LocalCtrl);
3151 local &= ~EEPROM_CLK_OUT;
3152 writel(local, &regs->LocalCtrl);
3153 readl(&regs->LocalCtrl);
3154 udelay(ACE_SHORT_DELAY);
3155 mb();
3156 if (i == 7) {
3157 local |= EEPROM_WRITE_ENABLE;
3158 writel(local, &regs->LocalCtrl);
3159 readl(&regs->LocalCtrl);
3160 mb();
3161 udelay(ACE_SHORT_DELAY);
3162 }
3163 }
3164
3165 local |= EEPROM_DATA_OUT;
3166 writel(local, &regs->LocalCtrl);
3167 readl(&regs->LocalCtrl);
3168 mb();
3169 udelay(ACE_SHORT_DELAY);
3170 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3171 readl(&regs->LocalCtrl);
3172 udelay(ACE_LONG_DELAY);
3173 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3174 readl(&regs->LocalCtrl);
3175 mb();
3176 udelay(ACE_SHORT_DELAY);
3177 eeprom_stop(regs);
3178
3179 local_irq_restore(flags);
3180 out:
3181 return result;
3182
3183 eeprom_read_error:
3184 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3185 ap->name, offset);
3186 goto out;
3187}
e6d20fca
PH		 3188
3189module_pci_driver(acenic_pci_driver);
Linux 6.x block layer and io_uring tree(s)