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drivers/net: Remove alloc_etherdev error messages
[linux-2.6-block.git] / drivers / net / ethernet / alteon / acenic.c
CommitLineData
1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
1da177e4
LT		 53#include <linux/module.h>
54#include <linux/moduleparam.h>
1da177e4
LT		 55#include <linux/types.h>
56#include <linux/errno.h>
57#include <linux/ioport.h>
58#include <linux/pci.h>
1e7f0bd8 59#include <linux/dma-mapping.h>
1da177e4
LT		 60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
949b4254 69#include <linux/firmware.h>
5a0e3ad6 70#include <linux/slab.h>
268bb0ce 71#include <linux/prefetch.h>
1da177e4 72#include <linux/if_vlan.h>
1da177e4
LT		 73
74#ifdef SIOCETHTOOL
75#include <linux/ethtool.h>
76#endif
77
78#include <net/sock.h>
79#include <net/ip.h>
80
81#include <asm/system.h>
82#include <asm/io.h>
83#include <asm/irq.h>
84#include <asm/byteorder.h>
85#include <asm/uaccess.h>
86
87
88#define DRV_NAME "acenic"
89
90#undef INDEX_DEBUG
91
92#ifdef CONFIG_ACENIC_OMIT_TIGON_I
93#define ACE_IS_TIGON_I(ap) 0
94#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
95#else
96#define ACE_IS_TIGON_I(ap) (ap->version == 1)
97#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
98#endif
99
100#ifndef PCI_VENDOR_ID_ALTEON
6aa20a22 101#define PCI_VENDOR_ID_ALTEON 0x12ae
1da177e4
LT		 102#endif
103#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
104#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
105#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
106#endif
107#ifndef PCI_DEVICE_ID_3COM_3C985
108#define PCI_DEVICE_ID_3COM_3C985 0x0001
109#endif
110#ifndef PCI_VENDOR_ID_NETGEAR
111#define PCI_VENDOR_ID_NETGEAR 0x1385
112#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
113#endif
114#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
115#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
116#endif
117
118
119/*
120 * Farallon used the DEC vendor ID by mistake and they seem not
121 * to care - stinky!
122 */
123#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
124#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
125#endif
126#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
127#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
128#endif
129#ifndef PCI_VENDOR_ID_SGI
130#define PCI_VENDOR_ID_SGI 0x10a9
131#endif
132#ifndef PCI_DEVICE_ID_SGI_ACENIC
133#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
134#endif
135
a3aa1884 136static DEFINE_PCI_DEVICE_TABLE(acenic_pci_tbl) = {
1da177e4
LT		 137 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
138 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
139 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
141 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
142 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
143 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
144 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
145 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
146 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
147 /*
148 * Farallon used the DEC vendor ID on their cards incorrectly,
149 * then later Alteon's ID.
150 */
151 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
152 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
153 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
154 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
155 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
156 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
157 { }
158};
159MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
160
1da177e4 161#define ace_sync_irq(irq) synchronize_irq(irq)
1da177e4
LT		 162
163#ifndef offset_in_page
164#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
165#endif
166
167#define ACE_MAX_MOD_PARMS 8
168#define BOARD_IDX_STATIC 0
169#define BOARD_IDX_OVERFLOW -1
170
1da177e4
LT		 171#include "acenic.h"
172
173/*
174 * These must be defined before the firmware is included.
175 */
176#define MAX_TEXT_LEN 96*1024
177#define MAX_RODATA_LEN 8*1024
178#define MAX_DATA_LEN 2*1024
179
1da177e4
LT		 180#ifndef tigon2FwReleaseLocal
181#define tigon2FwReleaseLocal 0
182#endif
183
184/*
185 * This driver currently supports Tigon I and Tigon II based cards
186 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
187 * GA620. The driver should also work on the SGI, DEC and Farallon
188 * versions of the card, however I have not been able to test that
189 * myself.
190 *
191 * This card is really neat, it supports receive hardware checksumming
192 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
193 * firmware. Also the programming interface is quite neat, except for
194 * the parts dealing with the i2c eeprom on the card ;-)
195 *
196 * Using jumbo frames:
197 *
198 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
199 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
200 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
201 * interface number and <MTU> being the MTU value.
202 *
203 * Module parameters:
204 *
205 * When compiled as a loadable module, the driver allows for a number
206 * of module parameters to be specified. The driver supports the
207 * following module parameters:
208 *
209 * trace=<val> - Firmware trace level. This requires special traced
210 * firmware to replace the firmware supplied with
211 * the driver - for debugging purposes only.
212 *
213 * link=<val> - Link state. Normally you want to use the default link
214 * parameters set by the driver. This can be used to
215 * override these in case your switch doesn't negotiate
216 * the link properly. Valid values are:
217 * 0x0001 - Force half duplex link.
218 * 0x0002 - Do not negotiate line speed with the other end.
219 * 0x0010 - 10Mbit/sec link.
220 * 0x0020 - 100Mbit/sec link.
221 * 0x0040 - 1000Mbit/sec link.
222 * 0x0100 - Do not negotiate flow control.
223 * 0x0200 - Enable RX flow control Y
224 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
225 * Default value is 0x0270, ie. enable link+flow
226 * control negotiation. Negotiating the highest
227 * possible link speed with RX flow control enabled.
228 *
229 * When disabling link speed negotiation, only one link
230 * speed is allowed to be specified!
231 *
232 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
233 * to wait for more packets to arive before
234 * interrupting the host, from the time the first
235 * packet arrives.
236 *
237 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
238 * to wait for more packets to arive in the transmit ring,
239 * before interrupting the host, after transmitting the
240 * first packet in the ring.
241 *
242 * max_tx_desc=<val> - maximum number of transmit descriptors
243 * (packets) transmitted before interrupting the host.
244 *
245 * max_rx_desc=<val> - maximum number of receive descriptors
246 * (packets) received before interrupting the host.
247 *
248 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
249 * increments of the NIC's on board memory to be used for
250 * transmit and receive buffers. For the 1MB NIC app. 800KB
251 * is available, on the 1/2MB NIC app. 300KB is available.
252 * 68KB will always be available as a minimum for both
253 * directions. The default value is a 50/50 split.
254 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
255 * operations, default (1) is to always disable this as
256 * that is what Alteon does on NT. I have not been able
257 * to measure any real performance differences with
258 * this on my systems. Set <val>=0 if you want to
259 * enable these operations.
260 *
261 * If you use more than one NIC, specify the parameters for the
262 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
263 * run tracing on NIC #2 but not on NIC #1 and #3.
264 *
265 * TODO:
266 *
267 * - Proper multicast support.
268 * - NIC dump support.
269 * - More tuning parameters.
270 *
271 * The mini ring is not used under Linux and I am not sure it makes sense
272 * to actually use it.
273 *
274 * New interrupt handler strategy:
275 *
276 * The old interrupt handler worked using the traditional method of
277 * replacing an skbuff with a new one when a packet arrives. However
278 * the rx rings do not need to contain a static number of buffer
279 * descriptors, thus it makes sense to move the memory allocation out
280 * of the main interrupt handler and do it in a bottom half handler
281 * and only allocate new buffers when the number of buffers in the
282 * ring is below a certain threshold. In order to avoid starving the
283 * NIC under heavy load it is however necessary to force allocation
284 * when hitting a minimum threshold. The strategy for alloction is as
285 * follows:
286 *
287 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
288 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
289 * the buffers in the interrupt handler
290 * RX_RING_THRES - maximum number of buffers in the rx ring
291 * RX_MINI_THRES - maximum number of buffers in the mini ring
292 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
293 *
294 * One advantagous side effect of this allocation approach is that the
295 * entire rx processing can be done without holding any spin lock
296 * since the rx rings and registers are totally independent of the tx
297 * ring and its registers. This of course includes the kmalloc's of
298 * new skb's. Thus start_xmit can run in parallel with rx processing
299 * and the memory allocation on SMP systems.
300 *
301 * Note that running the skb reallocation in a bottom half opens up
302 * another can of races which needs to be handled properly. In
303 * particular it can happen that the interrupt handler tries to run
304 * the reallocation while the bottom half is either running on another
305 * CPU or was interrupted on the same CPU. To get around this the
306 * driver uses bitops to prevent the reallocation routines from being
307 * reentered.
308 *
309 * TX handling can also be done without holding any spin lock, wheee
310 * this is fun! since tx_ret_csm is only written to by the interrupt
311 * handler. The case to be aware of is when shutting down the device
312 * and cleaning up where it is necessary to make sure that
313 * start_xmit() is not running while this is happening. Well DaveM
314 * informs me that this case is already protected against ... bye bye
315 * Mr. Spin Lock, it was nice to know you.
316 *
317 * TX interrupts are now partly disabled so the NIC will only generate
318 * TX interrupts for the number of coal ticks, not for the number of
319 * TX packets in the queue. This should reduce the number of TX only,
320 * ie. when no RX processing is done, interrupts seen.
321 */
322
323/*
324 * Threshold values for RX buffer allocation - the low water marks for
325 * when to start refilling the rings are set to 75% of the ring
326 * sizes. It seems to make sense to refill the rings entirely from the
327 * intrrupt handler once it gets below the panic threshold, that way
328 * we don't risk that the refilling is moved to another CPU when the
329 * one running the interrupt handler just got the slab code hot in its
330 * cache.
331 */
332#define RX_RING_SIZE 72
333#define RX_MINI_SIZE 64
334#define RX_JUMBO_SIZE 48
335
336#define RX_PANIC_STD_THRES 16
337#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
338#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
339#define RX_PANIC_MINI_THRES 12
340#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
341#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
342#define RX_PANIC_JUMBO_THRES 6
343#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
344#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
345
346
347/*
348 * Size of the mini ring entries, basically these just should be big
349 * enough to take TCP ACKs
350 */
351#define ACE_MINI_SIZE 100
352
353#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
354#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
355#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
356
357/*
358 * There seems to be a magic difference in the effect between 995 and 996
359 * but little difference between 900 and 995 ... no idea why.
360 *
361 * There is now a default set of tuning parameters which is set, depending
362 * on whether or not the user enables Jumbo frames. It's assumed that if
363 * Jumbo frames are enabled, the user wants optimal tuning for that case.
364 */
365#define DEF_TX_COAL 400 /* 996 */
366#define DEF_TX_MAX_DESC 60 /* was 40 */
367#define DEF_RX_COAL 120 /* 1000 */
368#define DEF_RX_MAX_DESC 25
369#define DEF_TX_RATIO 21 /* 24 */
370
371#define DEF_JUMBO_TX_COAL 20
372#define DEF_JUMBO_TX_MAX_DESC 60
373#define DEF_JUMBO_RX_COAL 30
374#define DEF_JUMBO_RX_MAX_DESC 6
375#define DEF_JUMBO_TX_RATIO 21
376
377#if tigon2FwReleaseLocal < 20001118
378/*
379 * Standard firmware and early modifications duplicate
380 * IRQ load without this flag (coal timer is never reset).
381 * Note that with this flag tx_coal should be less than
382 * time to xmit full tx ring.
383 * 400usec is not so bad for tx ring size of 128.
384 */
385#define TX_COAL_INTS_ONLY 1 /* worth it */
386#else
387/*
388 * With modified firmware, this is not necessary, but still useful.
389 */
390#define TX_COAL_INTS_ONLY 1
391#endif
392
393#define DEF_TRACE 0
394#define DEF_STAT (2 * TICKS_PER_SEC)
395
396
ddfce6bb 397static int link_state[ACE_MAX_MOD_PARMS];
1da177e4
LT		 398static int trace[ACE_MAX_MOD_PARMS];
399static int tx_coal_tick[ACE_MAX_MOD_PARMS];
400static int rx_coal_tick[ACE_MAX_MOD_PARMS];
401static int max_tx_desc[ACE_MAX_MOD_PARMS];
402static int max_rx_desc[ACE_MAX_MOD_PARMS];
403static int tx_ratio[ACE_MAX_MOD_PARMS];
404static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
405
406MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
407MODULE_LICENSE("GPL");
408MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
949b4254
JS		 409#ifndef CONFIG_ACENIC_OMIT_TIGON_I
410MODULE_FIRMWARE("acenic/tg1.bin");
411#endif
412MODULE_FIRMWARE("acenic/tg2.bin");
1da177e4 413
ddfce6bb 414module_param_array_named(link, link_state, int, NULL, 0);
1da177e4
LT		 415module_param_array(trace, int, NULL, 0);
416module_param_array(tx_coal_tick, int, NULL, 0);
417module_param_array(max_tx_desc, int, NULL, 0);
418module_param_array(rx_coal_tick, int, NULL, 0);
419module_param_array(max_rx_desc, int, NULL, 0);
420module_param_array(tx_ratio, int, NULL, 0);
421MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
422MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
423MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
424MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
425MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
426MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
427MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
428
429
da38075c 430static const char version[] __devinitconst =
1da177e4
LT		 431 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
432 " http://home.cern.ch/~jes/gige/acenic.html\n";
433
434static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
435static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
436static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
437
7282d491 438static const struct ethtool_ops ace_ethtool_ops = {
1da177e4
LT		 439 .get_settings = ace_get_settings,
440 .set_settings = ace_set_settings,
441 .get_drvinfo = ace_get_drvinfo,
442};
443
444static void ace_watchdog(struct net_device *dev);
445
d8b83c57
SH		 446static const struct net_device_ops ace_netdev_ops = {
447 .ndo_open = ace_open,
448 .ndo_stop = ace_close,
449 .ndo_tx_timeout = ace_watchdog,
450 .ndo_get_stats = ace_get_stats,
00829823 451 .ndo_start_xmit = ace_start_xmit,
afc4b13d 452 .ndo_set_rx_mode = ace_set_multicast_list,
52255bbe 453 .ndo_validate_addr = eth_validate_addr,
d8b83c57
SH		 454 .ndo_set_mac_address = ace_set_mac_addr,
455 .ndo_change_mtu = ace_change_mtu,
d8b83c57
SH		 456};
457
1da177e4
LT		 458static int __devinit acenic_probe_one(struct pci_dev *pdev,
459 const struct pci_device_id *id)
460{
461 struct net_device *dev;
462 struct ace_private *ap;
463 static int boards_found;
464
465 dev = alloc_etherdev(sizeof(struct ace_private));
41de8d4c 466 if (dev == NULL)
1da177e4 467 return -ENOMEM;
1da177e4 468
1da177e4
LT		 469 SET_NETDEV_DEV(dev, &pdev->dev);
470
454d7c9b 471 ap = netdev_priv(dev);
1da177e4
LT		 472 ap->pdev = pdev;
473 ap->name = pci_name(pdev);
474
475 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 476 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
25805dcf 477
25805dcf 478 dev->watchdog_timeo = 5*HZ;
1da177e4 479
d8b83c57 480 dev->netdev_ops = &ace_netdev_ops;
1da177e4 481 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
1da177e4
LT		 482
483 /* we only display this string ONCE */
484 if (!boards_found)
485 printk(version);
486
487 if (pci_enable_device(pdev))
488 goto fail_free_netdev;
489
490 /*
491 * Enable master mode before we start playing with the
492 * pci_command word since pci_set_master() will modify
493 * it.
494 */
495 pci_set_master(pdev);
496
497 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
498
6aa20a22 499 /* OpenFirmware on Mac's does not set this - DOH.. */
1da177e4
LT		 500 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
501 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
502 "access - was not enabled by BIOS/Firmware\n",
503 ap->name);
504 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
505 pci_write_config_word(ap->pdev, PCI_COMMAND,
506 ap->pci_command);
507 wmb();
508 }
509
510 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
511 if (ap->pci_latency <= 0x40) {
512 ap->pci_latency = 0x40;
513 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
514 }
515
516 /*
517 * Remap the regs into kernel space - this is abuse of
518 * dev->base_addr since it was means for I/O port
519 * addresses but who gives a damn.
520 */
521 dev->base_addr = pci_resource_start(pdev, 0);
522 ap->regs = ioremap(dev->base_addr, 0x4000);
523 if (!ap->regs) {
524 printk(KERN_ERR "%s: Unable to map I/O register, "
525 "AceNIC %i will be disabled.\n",
526 ap->name, boards_found);
527 goto fail_free_netdev;
528 }
529
530 switch(pdev->vendor) {
531 case PCI_VENDOR_ID_ALTEON:
532 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
533 printk(KERN_INFO "%s: Farallon PN9100-T ",
534 ap->name);
535 } else {
536 printk(KERN_INFO "%s: Alteon AceNIC ",
537 ap->name);
538 }
539 break;
540 case PCI_VENDOR_ID_3COM:
541 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
542 break;
543 case PCI_VENDOR_ID_NETGEAR:
544 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
545 break;
546 case PCI_VENDOR_ID_DEC:
547 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
548 printk(KERN_INFO "%s: Farallon PN9000-SX ",
549 ap->name);
550 break;
551 }
552 case PCI_VENDOR_ID_SGI:
553 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
554 break;
555 default:
556 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
557 break;
558 }
559
560 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
c6387a48 561 printk("irq %d\n", pdev->irq);
1da177e4
LT		 562
563#ifdef CONFIG_ACENIC_OMIT_TIGON_I
564 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
565 printk(KERN_ERR "%s: Driver compiled without Tigon I"
566 " support - NIC disabled\n", dev->name);
567 goto fail_uninit;
568 }
569#endif
570
571 if (ace_allocate_descriptors(dev))
572 goto fail_free_netdev;
573
574#ifdef MODULE
575 if (boards_found >= ACE_MAX_MOD_PARMS)
576 ap->board_idx = BOARD_IDX_OVERFLOW;
577 else
578 ap->board_idx = boards_found;
579#else
580 ap->board_idx = BOARD_IDX_STATIC;
581#endif
582
583 if (ace_init(dev))
584 goto fail_free_netdev;
585
586 if (register_netdev(dev)) {
587 printk(KERN_ERR "acenic: device registration failed\n");
588 goto fail_uninit;
589 }
590 ap->name = dev->name;
591
592 if (ap->pci_using_dac)
593 dev->features |= NETIF_F_HIGHDMA;
594
595 pci_set_drvdata(pdev, dev);
596
597 boards_found++;
598 return 0;
599
600 fail_uninit:
601 ace_init_cleanup(dev);
602 fail_free_netdev:
603 free_netdev(dev);
604 return -ENODEV;
605}
606
607static void __devexit acenic_remove_one(struct pci_dev *pdev)
608{
609 struct net_device *dev = pci_get_drvdata(pdev);
610 struct ace_private *ap = netdev_priv(dev);
611 struct ace_regs __iomem *regs = ap->regs;
612 short i;
613
614 unregister_netdev(dev);
615
616 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
617 if (ap->version >= 2)
618 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
6aa20a22 619
1da177e4
LT		 620 /*
621 * This clears any pending interrupts
622 */
623 writel(1, &regs->Mb0Lo);
624 readl(&regs->CpuCtrl); /* flush */
625
626 /*
627 * Make sure no other CPUs are processing interrupts
628 * on the card before the buffers are being released.
629 * Otherwise one might experience some `interesting'
630 * effects.
631 *
632 * Then release the RX buffers - jumbo buffers were
633 * already released in ace_close().
634 */
635 ace_sync_irq(dev->irq);
636
637 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
638 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
639
640 if (skb) {
641 struct ring_info *ringp;
642 dma_addr_t mapping;
643
644 ringp = &ap->skb->rx_std_skbuff[i];
430e55b1 645 mapping = dma_unmap_addr(ringp, mapping);
1da177e4
LT		 646 pci_unmap_page(ap->pdev, mapping,
647 ACE_STD_BUFSIZE,
648 PCI_DMA_FROMDEVICE);
649
650 ap->rx_std_ring[i].size = 0;
651 ap->skb->rx_std_skbuff[i].skb = NULL;
652 dev_kfree_skb(skb);
653 }
654 }
655
656 if (ap->version >= 2) {
657 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
658 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
659
660 if (skb) {
661 struct ring_info *ringp;
662 dma_addr_t mapping;
663
664 ringp = &ap->skb->rx_mini_skbuff[i];
430e55b1 665 mapping = dma_unmap_addr(ringp,mapping);
1da177e4
LT		 666 pci_unmap_page(ap->pdev, mapping,
667 ACE_MINI_BUFSIZE,
668 PCI_DMA_FROMDEVICE);
669
670 ap->rx_mini_ring[i].size = 0;
671 ap->skb->rx_mini_skbuff[i].skb = NULL;
672 dev_kfree_skb(skb);
673 }
674 }
675 }
676
677 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
678 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
679 if (skb) {
680 struct ring_info *ringp;
681 dma_addr_t mapping;
682
683 ringp = &ap->skb->rx_jumbo_skbuff[i];
430e55b1 684 mapping = dma_unmap_addr(ringp, mapping);
1da177e4
LT		 685 pci_unmap_page(ap->pdev, mapping,
686 ACE_JUMBO_BUFSIZE,
687 PCI_DMA_FROMDEVICE);
688
689 ap->rx_jumbo_ring[i].size = 0;
690 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
691 dev_kfree_skb(skb);
692 }
693 }
694
695 ace_init_cleanup(dev);
696 free_netdev(dev);
697}
698
699static struct pci_driver acenic_pci_driver = {
700 .name = "acenic",
701 .id_table = acenic_pci_tbl,
702 .probe = acenic_probe_one,
703 .remove = __devexit_p(acenic_remove_one),
704};
705
706static int __init acenic_init(void)
707{
29917620 708 return pci_register_driver(&acenic_pci_driver);
1da177e4
LT		 709}
710
711static void __exit acenic_exit(void)
712{
713 pci_unregister_driver(&acenic_pci_driver);
714}
715
716module_init(acenic_init);
717module_exit(acenic_exit);
718
719static void ace_free_descriptors(struct net_device *dev)
720{
721 struct ace_private *ap = netdev_priv(dev);
722 int size;
723
724 if (ap->rx_std_ring != NULL) {
725 size = (sizeof(struct rx_desc) *
726 (RX_STD_RING_ENTRIES +
727 RX_JUMBO_RING_ENTRIES +
728 RX_MINI_RING_ENTRIES +
729 RX_RETURN_RING_ENTRIES));
730 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
731 ap->rx_ring_base_dma);
732 ap->rx_std_ring = NULL;
733 ap->rx_jumbo_ring = NULL;
734 ap->rx_mini_ring = NULL;
735 ap->rx_return_ring = NULL;
736 }
737 if (ap->evt_ring != NULL) {
738 size = (sizeof(struct event) * EVT_RING_ENTRIES);
739 pci_free_consistent(ap->pdev, size, ap->evt_ring,
740 ap->evt_ring_dma);
741 ap->evt_ring = NULL;
742 }
743 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
744 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
745 pci_free_consistent(ap->pdev, size, ap->tx_ring,
746 ap->tx_ring_dma);
747 }
748 ap->tx_ring = NULL;
749
750 if (ap->evt_prd != NULL) {
751 pci_free_consistent(ap->pdev, sizeof(u32),
752 (void *)ap->evt_prd, ap->evt_prd_dma);
753 ap->evt_prd = NULL;
754 }
755 if (ap->rx_ret_prd != NULL) {
756 pci_free_consistent(ap->pdev, sizeof(u32),
757 (void *)ap->rx_ret_prd,
758 ap->rx_ret_prd_dma);
759 ap->rx_ret_prd = NULL;
760 }
761 if (ap->tx_csm != NULL) {
762 pci_free_consistent(ap->pdev, sizeof(u32),
763 (void *)ap->tx_csm, ap->tx_csm_dma);
764 ap->tx_csm = NULL;
765 }
766}
767
768
769static int ace_allocate_descriptors(struct net_device *dev)
770{
771 struct ace_private *ap = netdev_priv(dev);
772 int size;
773
774 size = (sizeof(struct rx_desc) *
775 (RX_STD_RING_ENTRIES +
776 RX_JUMBO_RING_ENTRIES +
777 RX_MINI_RING_ENTRIES +
778 RX_RETURN_RING_ENTRIES));
779
780 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
781 &ap->rx_ring_base_dma);
782 if (ap->rx_std_ring == NULL)
783 goto fail;
784
785 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
786 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
787 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
788
789 size = (sizeof(struct event) * EVT_RING_ENTRIES);
790
791 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
792
793 if (ap->evt_ring == NULL)
794 goto fail;
795
796 /*
797 * Only allocate a host TX ring for the Tigon II, the Tigon I
798 * has to use PCI registers for this ;-(
799 */
800 if (!ACE_IS_TIGON_I(ap)) {
801 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
802
803 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
804 &ap->tx_ring_dma);
805
806 if (ap->tx_ring == NULL)
807 goto fail;
808 }
809
810 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
811 &ap->evt_prd_dma);
812 if (ap->evt_prd == NULL)
813 goto fail;
814
815 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
816 &ap->rx_ret_prd_dma);
817 if (ap->rx_ret_prd == NULL)
818 goto fail;
819
820 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
821 &ap->tx_csm_dma);
822 if (ap->tx_csm == NULL)
823 goto fail;
824
825 return 0;
826
827fail:
828 /* Clean up. */
829 ace_init_cleanup(dev);
830 return 1;
831}
832
833
834/*
835 * Generic cleanup handling data allocated during init. Used when the
836 * module is unloaded or if an error occurs during initialization
837 */
838static void ace_init_cleanup(struct net_device *dev)
839{
840 struct ace_private *ap;
841
842 ap = netdev_priv(dev);
843
844 ace_free_descriptors(dev);
845
846 if (ap->info)
847 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
848 ap->info, ap->info_dma);
b4558ea9
JJ		 849 kfree(ap->skb);
850 kfree(ap->trace_buf);
1da177e4
LT		 851
852 if (dev->irq)
853 free_irq(dev->irq, dev);
854
855 iounmap(ap->regs);
856}
857
858
859/*
860 * Commands are considered to be slow.
861 */
862static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
863{
864 u32 idx;
865
866 idx = readl(&regs->CmdPrd);
867
868 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
869 idx = (idx + 1) % CMD_RING_ENTRIES;
870
871 writel(idx, &regs->CmdPrd);
872}
873
874
875static int __devinit ace_init(struct net_device *dev)
876{
877 struct ace_private *ap;
878 struct ace_regs __iomem *regs;
879 struct ace_info *info = NULL;
880 struct pci_dev *pdev;
881 unsigned long myjif;
882 u64 tmp_ptr;
883 u32 tig_ver, mac1, mac2, tmp, pci_state;
884 int board_idx, ecode = 0;
885 short i;
886 unsigned char cache_size;
887
888 ap = netdev_priv(dev);
889 regs = ap->regs;
890
891 board_idx = ap->board_idx;
892
893 /*
894 * aman@sgi.com - its useful to do a NIC reset here to
895 * address the `Firmware not running' problem subsequent
896 * to any crashes involving the NIC
897 */
898 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
899 readl(&regs->HostCtrl); /* PCI write posting */
900 udelay(5);
901
902 /*
903 * Don't access any other registers before this point!
904 */
905#ifdef __BIG_ENDIAN
906 /*
907 * This will most likely need BYTE_SWAP once we switch
908 * to using __raw_writel()
909 */
910 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
911 &regs->HostCtrl);
912#else
913 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
914 &regs->HostCtrl);
915#endif
916 readl(&regs->HostCtrl); /* PCI write posting */
917
918 /*
919 * Stop the NIC CPU and clear pending interrupts
920 */
921 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
922 readl(&regs->CpuCtrl); /* PCI write posting */
923 writel(0, &regs->Mb0Lo);
924
925 tig_ver = readl(&regs->HostCtrl) >> 28;
926
927 switch(tig_ver){
928#ifndef CONFIG_ACENIC_OMIT_TIGON_I
929 case 4:
930 case 5:
931 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 932 tig_ver, ap->firmware_major, ap->firmware_minor,
933 ap->firmware_fix);
1da177e4
LT		 934 writel(0, &regs->LocalCtrl);
935 ap->version = 1;
936 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
937 break;
938#endif
939 case 6:
940 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 941 tig_ver, ap->firmware_major, ap->firmware_minor,
942 ap->firmware_fix);
1da177e4
LT		 943 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
944 readl(&regs->CpuBCtrl); /* PCI write posting */
945 /*
946 * The SRAM bank size does _not_ indicate the amount
947 * of memory on the card, it controls the _bank_ size!
948 * Ie. a 1MB AceNIC will have two banks of 512KB.
949 */
950 writel(SRAM_BANK_512K, &regs->LocalCtrl);
951 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
952 ap->version = 2;
953 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
954 break;
955 default:
956 printk(KERN_WARNING " Unsupported Tigon version detected "
957 "(%i)\n", tig_ver);
958 ecode = -ENODEV;
959 goto init_error;
960 }
961
962 /*
963 * ModeStat _must_ be set after the SRAM settings as this change
964 * seems to corrupt the ModeStat and possible other registers.
965 * The SRAM settings survive resets and setting it to the same
966 * value a second time works as well. This is what caused the
967 * `Firmware not running' problem on the Tigon II.
968 */
969#ifdef __BIG_ENDIAN
970 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
971 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
972#else
973 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
974 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
975#endif
976 readl(&regs->ModeStat); /* PCI write posting */
977
978 mac1 = 0;
979 for(i = 0; i < 4; i++) {
ddfce6bb 980 int t;
6f9d4722 981
1da177e4 982 mac1 = mac1 << 8;
ddfce6bb
SH		 983 t = read_eeprom_byte(dev, 0x8c+i);
984 if (t < 0) {
1da177e4
LT		 985 ecode = -EIO;
986 goto init_error;
987 } else
ddfce6bb 988 mac1 |= (t & 0xff);
1da177e4
LT		 989 }
990 mac2 = 0;
991 for(i = 4; i < 8; i++) {
ddfce6bb 992 int t;
6f9d4722 993
1da177e4 994 mac2 = mac2 << 8;
ddfce6bb
SH		 995 t = read_eeprom_byte(dev, 0x8c+i);
996 if (t < 0) {
1da177e4
LT		 997 ecode = -EIO;
998 goto init_error;
999 } else
ddfce6bb 1000 mac2 |= (t & 0xff);
1da177e4
LT		 1001 }
1002
1003 writel(mac1, &regs->MacAddrHi);
1004 writel(mac2, &regs->MacAddrLo);
1005
1da177e4
LT		 1006 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1007 dev->dev_addr[1] = mac1 & 0xff;
1008 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1009 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1010 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1011 dev->dev_addr[5] = mac2 & 0xff;
1012
e174961c 1013 printk("MAC: %pM\n", dev->dev_addr);
0795af57 1014
1da177e4
LT		 1015 /*
1016 * Looks like this is necessary to deal with on all architectures,
1017 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1018 * Ie. having two NICs in the machine, one will have the cache
1019 * line set at boot time, the other will not.
1020 */
1021 pdev = ap->pdev;
1022 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1023 cache_size <<= 2;
1024 if (cache_size != SMP_CACHE_BYTES) {
1025 printk(KERN_INFO " PCI cache line size set incorrectly "
1026 "(%i bytes) by BIOS/FW, ", cache_size);
1027 if (cache_size > SMP_CACHE_BYTES)
1028 printk("expecting %i\n", SMP_CACHE_BYTES);
1029 else {
1030 printk("correcting to %i\n", SMP_CACHE_BYTES);
1031 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1032 SMP_CACHE_BYTES >> 2);
1033 }
1034 }
1035
1036 pci_state = readl(&regs->PciState);
1037 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1038 "latency: %i clks\n",
1039 (pci_state & PCI_32BIT) ? 32 : 64,
6aa20a22 1040 (pci_state & PCI_66MHZ) ? 66 : 33,
1da177e4
LT		 1041 ap->pci_latency);
1042
1043 /*
1044 * Set the max DMA transfer size. Seems that for most systems
1045 * the performance is better when no MAX parameter is
1046 * set. However for systems enabling PCI write and invalidate,
1047 * DMA writes must be set to the L1 cache line size to get
1048 * optimal performance.
1049 *
1050 * The default is now to turn the PCI write and invalidate off
1051 * - that is what Alteon does for NT.
1052 */
1053 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1054 if (ap->version >= 2) {
1055 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1056 /*
1057 * Tuning parameters only supported for 8 cards
1058 */
1059 if (board_idx == BOARD_IDX_OVERFLOW ||
1060 dis_pci_mem_inval[board_idx]) {
1061 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1062 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1063 pci_write_config_word(pdev, PCI_COMMAND,
1064 ap->pci_command);
1065 printk(KERN_INFO " Disabling PCI memory "
1066 "write and invalidate\n");
1067 }
1068 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1069 printk(KERN_INFO " PCI memory write & invalidate "
1070 "enabled by BIOS, enabling counter measures\n");
1071
1072 switch(SMP_CACHE_BYTES) {
1073 case 16:
1074 tmp |= DMA_WRITE_MAX_16;
1075 break;
1076 case 32:
1077 tmp |= DMA_WRITE_MAX_32;
1078 break;
1079 case 64:
1080 tmp |= DMA_WRITE_MAX_64;
1081 break;
1082 case 128:
1083 tmp |= DMA_WRITE_MAX_128;
1084 break;
1085 default:
1086 printk(KERN_INFO " Cache line size %i not "
1087 "supported, PCI write and invalidate "
1088 "disabled\n", SMP_CACHE_BYTES);
1089 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1090 pci_write_config_word(pdev, PCI_COMMAND,
1091 ap->pci_command);
1092 }
1093 }
1094 }
1095
1096#ifdef __sparc__
1097 /*
1098 * On this platform, we know what the best dma settings
1099 * are. We use 64-byte maximum bursts, because if we
1100 * burst larger than the cache line size (or even cross
1101 * a 64byte boundary in a single burst) the UltraSparc
1102 * PCI controller will disconnect at 64-byte multiples.
1103 *
1104 * Read-multiple will be properly enabled above, and when
1105 * set will give the PCI controller proper hints about
1106 * prefetching.
1107 */
1108 tmp &= ~DMA_READ_WRITE_MASK;
1109 tmp |= DMA_READ_MAX_64;
1110 tmp |= DMA_WRITE_MAX_64;
1111#endif
1112#ifdef __alpha__
1113 tmp &= ~DMA_READ_WRITE_MASK;
1114 tmp |= DMA_READ_MAX_128;
1115 /*
1116 * All the docs say MUST NOT. Well, I did.
1117 * Nothing terrible happens, if we load wrong size.
1118 * Bit w&i still works better!
1119 */
1120 tmp |= DMA_WRITE_MAX_128;
1121#endif
1122 writel(tmp, &regs->PciState);
1123
1124#if 0
1125 /*
1126 * The Host PCI bus controller driver has to set FBB.
1127 * If all devices on that PCI bus support FBB, then the controller
1128 * can enable FBB support in the Host PCI Bus controller (or on
1129 * the PCI-PCI bridge if that applies).
1130 * -ggg
1131 */
1132 /*
1133 * I have received reports from people having problems when this
1134 * bit is enabled.
1135 */
1136 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1137 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1138 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1139 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1140 }
1141#endif
6aa20a22 1142
1da177e4
LT		 1143 /*
1144 * Configure DMA attributes.
1145 */
6a35528a 1146 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 1147 ap->pci_using_dac = 1;
284901a9 1148 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 1149 ap->pci_using_dac = 0;
1150 } else {
1151 ecode = -ENODEV;
1152 goto init_error;
1153 }
1154
1155 /*
1156 * Initialize the generic info block and the command+event rings
1157 * and the control blocks for the transmit and receive rings
1158 * as they need to be setup once and for all.
1159 */
1160 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1161 &ap->info_dma))) {
1162 ecode = -EAGAIN;
1163 goto init_error;
1164 }
1165 ap->info = info;
1166
1167 /*
1168 * Get the memory for the skb rings.
1169 */
1170 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1171 ecode = -EAGAIN;
1172 goto init_error;
1173 }
1174
1fb9df5d 1175 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1da177e4
LT		 1176 DRV_NAME, dev);
1177 if (ecode) {
1178 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1179 DRV_NAME, pdev->irq);
1180 goto init_error;
1181 } else
1182 dev->irq = pdev->irq;
1183
1184#ifdef INDEX_DEBUG
1185 spin_lock_init(&ap->debug_lock);
1186 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1187 ap->last_std_rx = 0;
1188 ap->last_mini_rx = 0;
1189#endif
1190
1191 memset(ap->info, 0, sizeof(struct ace_info));
1192 memset(ap->skb, 0, sizeof(struct ace_skb));
1193
6c60e0c3
BH		 1194 ecode = ace_load_firmware(dev);
1195 if (ecode)
949b4254
JS		 1196 goto init_error;
1197
1da177e4
LT		 1198 ap->fw_running = 0;
1199
1200 tmp_ptr = ap->info_dma;
1201 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1202 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1203
1204 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1205
1206 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1207 info->evt_ctrl.flags = 0;
1208
1209 *(ap->evt_prd) = 0;
1210 wmb();
1211 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1212 writel(0, &regs->EvtCsm);
1213
1214 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1215 info->cmd_ctrl.flags = 0;
1216 info->cmd_ctrl.max_len = 0;
1217
1218 for (i = 0; i < CMD_RING_ENTRIES; i++)
1219 writel(0, &regs->CmdRng[i]);
1220
1221 writel(0, &regs->CmdPrd);
1222 writel(0, &regs->CmdCsm);
1223
1224 tmp_ptr = ap->info_dma;
1225 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1226 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1227
1228 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1229 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1230 info->rx_std_ctrl.flags =
08dddfc3 1231 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1232
1233 memset(ap->rx_std_ring, 0,
1234 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1235
1236 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1237 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1238
1239 ap->rx_std_skbprd = 0;
1240 atomic_set(&ap->cur_rx_bufs, 0);
1241
1242 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1243 (ap->rx_ring_base_dma +
1244 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1245 info->rx_jumbo_ctrl.max_len = 0;
1246 info->rx_jumbo_ctrl.flags =
08dddfc3 1247 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1248
1249 memset(ap->rx_jumbo_ring, 0,
1250 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1251
1252 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1253 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1254
1255 ap->rx_jumbo_skbprd = 0;
1256 atomic_set(&ap->cur_jumbo_bufs, 0);
1257
1258 memset(ap->rx_mini_ring, 0,
1259 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1260
1261 if (ap->version >= 2) {
1262 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1263 (ap->rx_ring_base_dma +
1264 (sizeof(struct rx_desc) *
1265 (RX_STD_RING_ENTRIES +
1266 RX_JUMBO_RING_ENTRIES))));
1267 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
6aa20a22 1268 info->rx_mini_ctrl.flags =
08dddfc3 1269 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1270
1271 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1272 ap->rx_mini_ring[i].flags =
1273 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1274 } else {
1275 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1276 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1277 info->rx_mini_ctrl.max_len = 0;
1278 }
1279
1280 ap->rx_mini_skbprd = 0;
1281 atomic_set(&ap->cur_mini_bufs, 0);
1282
1283 set_aceaddr(&info->rx_return_ctrl.rngptr,
1284 (ap->rx_ring_base_dma +
1285 (sizeof(struct rx_desc) *
1286 (RX_STD_RING_ENTRIES +
1287 RX_JUMBO_RING_ENTRIES +
1288 RX_MINI_RING_ENTRIES))));
1289 info->rx_return_ctrl.flags = 0;
1290 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1291
1292 memset(ap->rx_return_ring, 0,
1293 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1294
1295 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1296 *(ap->rx_ret_prd) = 0;
1297
1298 writel(TX_RING_BASE, &regs->WinBase);
1299
1300 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 1301 ap->tx_ring = (__force struct tx_desc *) regs->Window;
6aa20a22 1302 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1da177e4 1303 * sizeof(struct tx_desc)) / sizeof(u32); i++)
ddfce6bb 1304 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1da177e4
LT		 1305
1306 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1307 } else {
1308 memset(ap->tx_ring, 0,
1309 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1310
1311 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1312 }
1313
1314 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
08dddfc3 1315 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1316
1317 /*
1318 * The Tigon I does not like having the TX ring in host memory ;-(
1319 */
1320 if (!ACE_IS_TIGON_I(ap))
1321 tmp |= RCB_FLG_TX_HOST_RING;
1322#if TX_COAL_INTS_ONLY
1323 tmp |= RCB_FLG_COAL_INT_ONLY;
1324#endif
1325 info->tx_ctrl.flags = tmp;
1326
1327 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1328
1329 /*
1330 * Potential item for tuning parameter
1331 */
1332#if 0 /* NO */
1333 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1334 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1335#else
1336 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1337 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1338#endif
1339
1340 writel(0, &regs->MaskInt);
1341 writel(1, &regs->IfIdx);
1342#if 0
1343 /*
1344 * McKinley boxes do not like us fiddling with AssistState
1345 * this early
1346 */
1347 writel(1, &regs->AssistState);
1348#endif
1349
1350 writel(DEF_STAT, &regs->TuneStatTicks);
1351 writel(DEF_TRACE, &regs->TuneTrace);
1352
1353 ace_set_rxtx_parms(dev, 0);
1354
1355 if (board_idx == BOARD_IDX_OVERFLOW) {
1356 printk(KERN_WARNING "%s: more than %i NICs detected, "
1357 "ignoring module parameters!\n",
1358 ap->name, ACE_MAX_MOD_PARMS);
1359 } else if (board_idx >= 0) {
1360 if (tx_coal_tick[board_idx])
1361 writel(tx_coal_tick[board_idx],
1362 &regs->TuneTxCoalTicks);
1363 if (max_tx_desc[board_idx])
1364 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1365
1366 if (rx_coal_tick[board_idx])
1367 writel(rx_coal_tick[board_idx],
1368 &regs->TuneRxCoalTicks);
1369 if (max_rx_desc[board_idx])
1370 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1371
1372 if (trace[board_idx])
1373 writel(trace[board_idx], &regs->TuneTrace);
1374
1375 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1376 writel(tx_ratio[board_idx], &regs->TxBufRat);
1377 }
1378
1379 /*
1380 * Default link parameters
1381 */
1382 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1383 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1384 if(ap->version >= 2)
1385 tmp |= LNK_TX_FLOW_CTL_Y;
1386
1387 /*
1388 * Override link default parameters
1389 */
ddfce6bb
SH		 1390 if ((board_idx >= 0) && link_state[board_idx]) {
1391 int option = link_state[board_idx];
1da177e4
LT		 1392
1393 tmp = LNK_ENABLE;
1394
1395 if (option & 0x01) {
1396 printk(KERN_INFO "%s: Setting half duplex link\n",
1397 ap->name);
1398 tmp &= ~LNK_FULL_DUPLEX;
1399 }
1400 if (option & 0x02)
1401 tmp &= ~LNK_NEGOTIATE;
1402 if (option & 0x10)
1403 tmp |= LNK_10MB;
1404 if (option & 0x20)
1405 tmp |= LNK_100MB;
1406 if (option & 0x40)
1407 tmp |= LNK_1000MB;
1408 if ((option & 0x70) == 0) {
1409 printk(KERN_WARNING "%s: No media speed specified, "
1410 "forcing auto negotiation\n", ap->name);
1411 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1412 LNK_100MB | LNK_10MB;
1413 }
1414 if ((option & 0x100) == 0)
1415 tmp |= LNK_NEG_FCTL;
1416 else
1417 printk(KERN_INFO "%s: Disabling flow control "
1418 "negotiation\n", ap->name);
1419 if (option & 0x200)
1420 tmp |= LNK_RX_FLOW_CTL_Y;
1421 if ((option & 0x400) && (ap->version >= 2)) {
1422 printk(KERN_INFO "%s: Enabling TX flow control\n",
1423 ap->name);
1424 tmp |= LNK_TX_FLOW_CTL_Y;
1425 }
1426 }
1427
1428 ap->link = tmp;
1429 writel(tmp, &regs->TuneLink);
1430 if (ap->version >= 2)
1431 writel(tmp, &regs->TuneFastLink);
1432
949b4254 1433 writel(ap->firmware_start, &regs->Pc);
1da177e4
LT		 1434
1435 writel(0, &regs->Mb0Lo);
1436
1437 /*
1438 * Set tx_csm before we start receiving interrupts, otherwise
1439 * the interrupt handler might think it is supposed to process
1440 * tx ints before we are up and running, which may cause a null
1441 * pointer access in the int handler.
1442 */
1443 ap->cur_rx = 0;
1444 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1445
1446 wmb();
1447 ace_set_txprd(regs, ap, 0);
1448 writel(0, &regs->RxRetCsm);
1449
1da177e4
LT		 1450 /*
1451 * Enable DMA engine now.
1452 * If we do this sooner, Mckinley box pukes.
1453 * I assume it's because Tigon II DMA engine wants to check
1454 * *something* even before the CPU is started.
1455 */
1456 writel(1, &regs->AssistState); /* enable DMA */
1457
1458 /*
1459 * Start the NIC CPU
1460 */
1461 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1462 readl(&regs->CpuCtrl);
1463
1464 /*
1465 * Wait for the firmware to spin up - max 3 seconds.
1466 */
1467 myjif = jiffies + 3 * HZ;
1468 while (time_before(jiffies, myjif) && !ap->fw_running)
1469 cpu_relax();
1470
1471 if (!ap->fw_running) {
1472 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1473
1474 ace_dump_trace(ap);
1475 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1476 readl(&regs->CpuCtrl);
1477
1478 /* aman@sgi.com - account for badly behaving firmware/NIC:
1479 * - have observed that the NIC may continue to generate
1480 * interrupts for some reason; attempt to stop it - halt
1481 * second CPU for Tigon II cards, and also clear Mb0
1482 * - if we're a module, we'll fail to load if this was
1483 * the only GbE card in the system => if the kernel does
1484 * see an interrupt from the NIC, code to handle it is
1485 * gone and OOps! - so free_irq also
1486 */
1487 if (ap->version >= 2)
1488 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1489 &regs->CpuBCtrl);
1490 writel(0, &regs->Mb0Lo);
1491 readl(&regs->Mb0Lo);
1492
1493 ecode = -EBUSY;
1494 goto init_error;
1495 }
1496
1497 /*
1498 * We load the ring here as there seem to be no way to tell the
1499 * firmware to wipe the ring without re-initializing it.
1500 */
1501 if (!test_and_set_bit(0, &ap->std_refill_busy))
427e21fa 1502 ace_load_std_rx_ring(dev, RX_RING_SIZE);
1da177e4
LT		 1503 else
1504 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1505 ap->name);
1506 if (ap->version >= 2) {
1507 if (!test_and_set_bit(0, &ap->mini_refill_busy))
427e21fa 1508 ace_load_mini_rx_ring(dev, RX_MINI_SIZE);
1da177e4
LT		 1509 else
1510 printk(KERN_ERR "%s: Someone is busy refilling "
1511 "the RX mini ring\n", ap->name);
1512 }
1513 return 0;
1514
1515 init_error:
1516 ace_init_cleanup(dev);
1517 return ecode;
1518}
1519
1520
1521static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1522{
1523 struct ace_private *ap = netdev_priv(dev);
1524 struct ace_regs __iomem *regs = ap->regs;
1525 int board_idx = ap->board_idx;
1526
1527 if (board_idx >= 0) {
1528 if (!jumbo) {
1529 if (!tx_coal_tick[board_idx])
1530 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1531 if (!max_tx_desc[board_idx])
1532 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1533 if (!rx_coal_tick[board_idx])
1534 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1535 if (!max_rx_desc[board_idx])
1536 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1537 if (!tx_ratio[board_idx])
1538 writel(DEF_TX_RATIO, &regs->TxBufRat);
1539 } else {
1540 if (!tx_coal_tick[board_idx])
1541 writel(DEF_JUMBO_TX_COAL,
1542 &regs->TuneTxCoalTicks);
1543 if (!max_tx_desc[board_idx])
1544 writel(DEF_JUMBO_TX_MAX_DESC,
1545 &regs->TuneMaxTxDesc);
1546 if (!rx_coal_tick[board_idx])
1547 writel(DEF_JUMBO_RX_COAL,
1548 &regs->TuneRxCoalTicks);
1549 if (!max_rx_desc[board_idx])
1550 writel(DEF_JUMBO_RX_MAX_DESC,
1551 &regs->TuneMaxRxDesc);
1552 if (!tx_ratio[board_idx])
1553 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1554 }
1555 }
1556}
1557
1558
1559static void ace_watchdog(struct net_device *data)
1560{
1561 struct net_device *dev = data;
1562 struct ace_private *ap = netdev_priv(dev);
1563 struct ace_regs __iomem *regs = ap->regs;
1564
1565 /*
1566 * We haven't received a stats update event for more than 2.5
1567 * seconds and there is data in the transmit queue, thus we
25985edc 1568 * assume the card is stuck.
1da177e4
LT		 1569 */
1570 if (*ap->tx_csm != ap->tx_ret_csm) {
1571 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1572 dev->name, (unsigned int)readl(&regs->HostCtrl));
1573 /* This can happen due to ieee flow control. */
1574 } else {
1575 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1576 dev->name);
1577#if 0
1578 netif_wake_queue(dev);
1579#endif
1580 }
1581}
1582
1583
427e21fa 1584static void ace_tasklet(unsigned long arg)
1da177e4 1585{
427e21fa 1586 struct net_device *dev = (struct net_device *) arg;
1587 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1588 int cur_size;
1589
1590 cur_size = atomic_read(&ap->cur_rx_bufs);
1591 if ((cur_size < RX_LOW_STD_THRES) &&
1592 !test_and_set_bit(0, &ap->std_refill_busy)) {
1593#ifdef DEBUG
1594 printk("refilling buffers (current %i)\n", cur_size);
1595#endif
427e21fa 1596 ace_load_std_rx_ring(dev, RX_RING_SIZE - cur_size);
1da177e4
LT		 1597 }
1598
1599 if (ap->version >= 2) {
1600 cur_size = atomic_read(&ap->cur_mini_bufs);
1601 if ((cur_size < RX_LOW_MINI_THRES) &&
1602 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1603#ifdef DEBUG
1604 printk("refilling mini buffers (current %i)\n",
1605 cur_size);
1606#endif
427e21fa 1607 ace_load_mini_rx_ring(dev, RX_MINI_SIZE - cur_size);
1da177e4
LT		 1608 }
1609 }
1610
1611 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1612 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1613 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1614#ifdef DEBUG
1615 printk("refilling jumbo buffers (current %i)\n", cur_size);
1616#endif
427e21fa 1617 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE - cur_size);
1da177e4
LT		 1618 }
1619 ap->tasklet_pending = 0;
1620}
1621
1622
1623/*
1624 * Copy the contents of the NIC's trace buffer to kernel memory.
1625 */
1626static void ace_dump_trace(struct ace_private *ap)
1627{
1628#if 0
1629 if (!ap->trace_buf)
1630 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1631 return;
1632#endif
1633}
1634
1635
1636/*
1637 * Load the standard rx ring.
1638 *
1639 * Loading rings is safe without holding the spin lock since this is
1640 * done only before the device is enabled, thus no interrupts are
1641 * generated and by the interrupt handler/tasklet handler.
1642 */
427e21fa 1643static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs)
1da177e4 1644{
427e21fa 1645 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1646 struct ace_regs __iomem *regs = ap->regs;
1647 short i, idx;
6aa20a22 1648
1da177e4
LT		 1649
1650 prefetchw(&ap->cur_rx_bufs);
1651
1652 idx = ap->rx_std_skbprd;
1653
1654 for (i = 0; i < nr_bufs; i++) {
1655 struct sk_buff *skb;
1656 struct rx_desc *rd;
1657 dma_addr_t mapping;
1658
427e21fa 1659 skb = netdev_alloc_skb_ip_align(dev, ACE_STD_BUFSIZE);
1da177e4
LT		 1660 if (!skb)
1661 break;
1662
1da177e4
LT		 1663 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1664 offset_in_page(skb->data),
1665 ACE_STD_BUFSIZE,
1666 PCI_DMA_FROMDEVICE);
1667 ap->skb->rx_std_skbuff[idx].skb = skb;
430e55b1 1668 dma_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1da177e4
LT		 1669 mapping, mapping);
1670
1671 rd = &ap->rx_std_ring[idx];
1672 set_aceaddr(&rd->addr, mapping);
1673 rd->size = ACE_STD_BUFSIZE;
1674 rd->idx = idx;
1675 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1676 }
1677
1678 if (!i)
1679 goto error_out;
1680
1681 atomic_add(i, &ap->cur_rx_bufs);
1682 ap->rx_std_skbprd = idx;
1683
1684 if (ACE_IS_TIGON_I(ap)) {
1685 struct cmd cmd;
1686 cmd.evt = C_SET_RX_PRD_IDX;
1687 cmd.code = 0;
1688 cmd.idx = ap->rx_std_skbprd;
1689 ace_issue_cmd(regs, &cmd);
1690 } else {
1691 writel(idx, &regs->RxStdPrd);
1692 wmb();
1693 }
1694
1695 out:
1696 clear_bit(0, &ap->std_refill_busy);
1697 return;
1698
1699 error_out:
1700 printk(KERN_INFO "Out of memory when allocating "
1701 "standard receive buffers\n");
1702 goto out;
1703}
1704
1705
427e21fa 1706static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs)
1da177e4 1707{
427e21fa 1708 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1709 struct ace_regs __iomem *regs = ap->regs;
1710 short i, idx;
1711
1712 prefetchw(&ap->cur_mini_bufs);
1713
1714 idx = ap->rx_mini_skbprd;
1715 for (i = 0; i < nr_bufs; i++) {
1716 struct sk_buff *skb;
1717 struct rx_desc *rd;
1718 dma_addr_t mapping;
1719
427e21fa 1720 skb = netdev_alloc_skb_ip_align(dev, ACE_MINI_BUFSIZE);
1da177e4
LT		 1721 if (!skb)
1722 break;
1723
1da177e4
LT		 1724 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1725 offset_in_page(skb->data),
1726 ACE_MINI_BUFSIZE,
1727 PCI_DMA_FROMDEVICE);
1728 ap->skb->rx_mini_skbuff[idx].skb = skb;
430e55b1 1729 dma_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1da177e4
LT		 1730 mapping, mapping);
1731
1732 rd = &ap->rx_mini_ring[idx];
1733 set_aceaddr(&rd->addr, mapping);
1734 rd->size = ACE_MINI_BUFSIZE;
1735 rd->idx = idx;
1736 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1737 }
1738
1739 if (!i)
1740 goto error_out;
1741
1742 atomic_add(i, &ap->cur_mini_bufs);
1743
1744 ap->rx_mini_skbprd = idx;
1745
1746 writel(idx, &regs->RxMiniPrd);
1747 wmb();
1748
1749 out:
1750 clear_bit(0, &ap->mini_refill_busy);
1751 return;
1752 error_out:
1753 printk(KERN_INFO "Out of memory when allocating "
1754 "mini receive buffers\n");
1755 goto out;
1756}
1757
1758
1759/*
1760 * Load the jumbo rx ring, this may happen at any time if the MTU
1761 * is changed to a value > 1500.
1762 */
427e21fa 1763static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs)
1da177e4 1764{
427e21fa 1765 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1766 struct ace_regs __iomem *regs = ap->regs;
1767 short i, idx;
1768
1769 idx = ap->rx_jumbo_skbprd;
1770
1771 for (i = 0; i < nr_bufs; i++) {
1772 struct sk_buff *skb;
1773 struct rx_desc *rd;
1774 dma_addr_t mapping;
1775
427e21fa 1776 skb = netdev_alloc_skb_ip_align(dev, ACE_JUMBO_BUFSIZE);
1da177e4
LT		 1777 if (!skb)
1778 break;
1779
1da177e4
LT		 1780 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1781 offset_in_page(skb->data),
1782 ACE_JUMBO_BUFSIZE,
1783 PCI_DMA_FROMDEVICE);
1784 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
430e55b1 1785 dma_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1da177e4
LT		 1786 mapping, mapping);
1787
1788 rd = &ap->rx_jumbo_ring[idx];
1789 set_aceaddr(&rd->addr, mapping);
1790 rd->size = ACE_JUMBO_BUFSIZE;
1791 rd->idx = idx;
1792 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1793 }
1794
1795 if (!i)
1796 goto error_out;
1797
1798 atomic_add(i, &ap->cur_jumbo_bufs);
1799 ap->rx_jumbo_skbprd = idx;
1800
1801 if (ACE_IS_TIGON_I(ap)) {
1802 struct cmd cmd;
1803 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1804 cmd.code = 0;
1805 cmd.idx = ap->rx_jumbo_skbprd;
1806 ace_issue_cmd(regs, &cmd);
1807 } else {
1808 writel(idx, &regs->RxJumboPrd);
1809 wmb();
1810 }
1811
1812 out:
1813 clear_bit(0, &ap->jumbo_refill_busy);
1814 return;
1815 error_out:
1816 if (net_ratelimit())
1817 printk(KERN_INFO "Out of memory when allocating "
1818 "jumbo receive buffers\n");
1819 goto out;
1820}
1821
1822
1823/*
1824 * All events are considered to be slow (RX/TX ints do not generate
1825 * events) and are handled here, outside the main interrupt handler,
1826 * to reduce the size of the handler.
1827 */
1828static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1829{
1830 struct ace_private *ap;
1831
1832 ap = netdev_priv(dev);
1833
1834 while (evtcsm != evtprd) {
1835 switch (ap->evt_ring[evtcsm].evt) {
1836 case E_FW_RUNNING:
1837 printk(KERN_INFO "%s: Firmware up and running\n",
1838 ap->name);
1839 ap->fw_running = 1;
1840 wmb();
1841 break;
1842 case E_STATS_UPDATED:
1843 break;
1844 case E_LNK_STATE:
1845 {
1846 u16 code = ap->evt_ring[evtcsm].code;
1847 switch (code) {
1848 case E_C_LINK_UP:
1849 {
1850 u32 state = readl(&ap->regs->GigLnkState);
1851 printk(KERN_WARNING "%s: Optical link UP "
1852 "(%s Duplex, Flow Control: %s%s)\n",
1853 ap->name,
1854 state & LNK_FULL_DUPLEX ? "Full":"Half",
1855 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1856 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1857 break;
1858 }
1859 case E_C_LINK_DOWN:
1860 printk(KERN_WARNING "%s: Optical link DOWN\n",
1861 ap->name);
1862 break;
1863 case E_C_LINK_10_100:
1864 printk(KERN_WARNING "%s: 10/100BaseT link "
1865 "UP\n", ap->name);
1866 break;
1867 default:
1868 printk(KERN_ERR "%s: Unknown optical link "
1869 "state %02x\n", ap->name, code);
1870 }
1871 break;
1872 }
1873 case E_ERROR:
1874 switch(ap->evt_ring[evtcsm].code) {
1875 case E_C_ERR_INVAL_CMD:
1876 printk(KERN_ERR "%s: invalid command error\n",
1877 ap->name);
1878 break;
1879 case E_C_ERR_UNIMP_CMD:
1880 printk(KERN_ERR "%s: unimplemented command "
1881 "error\n", ap->name);
1882 break;
1883 case E_C_ERR_BAD_CFG:
1884 printk(KERN_ERR "%s: bad config error\n",
1885 ap->name);
1886 break;
1887 default:
1888 printk(KERN_ERR "%s: unknown error %02x\n",
1889 ap->name, ap->evt_ring[evtcsm].code);
1890 }
1891 break;
1892 case E_RESET_JUMBO_RNG:
1893 {
1894 int i;
1895 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1896 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1897 ap->rx_jumbo_ring[i].size = 0;
1898 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1899 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1900 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1901 }
1902 }
1903
1904 if (ACE_IS_TIGON_I(ap)) {
1905 struct cmd cmd;
1906 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1907 cmd.code = 0;
1908 cmd.idx = 0;
1909 ace_issue_cmd(ap->regs, &cmd);
1910 } else {
1911 writel(0, &((ap->regs)->RxJumboPrd));
1912 wmb();
1913 }
1914
1915 ap->jumbo = 0;
1916 ap->rx_jumbo_skbprd = 0;
1917 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1918 ap->name);
1919 clear_bit(0, &ap->jumbo_refill_busy);
1920 break;
1921 }
1922 default:
1923 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1924 ap->name, ap->evt_ring[evtcsm].evt);
1925 }
1926 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1927 }
1928
1929 return evtcsm;
1930}
1931
1932
1933static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1934{
1935 struct ace_private *ap = netdev_priv(dev);
1936 u32 idx;
1937 int mini_count = 0, std_count = 0;
1938
1939 idx = rxretcsm;
1940
1941 prefetchw(&ap->cur_rx_bufs);
1942 prefetchw(&ap->cur_mini_bufs);
6aa20a22 1943
1da177e4
LT		 1944 while (idx != rxretprd) {
1945 struct ring_info *rip;
1946 struct sk_buff *skb;
1947 struct rx_desc *rxdesc, *retdesc;
1948 u32 skbidx;
1949 int bd_flags, desc_type, mapsize;
1950 u16 csum;
1951
1952
1953 /* make sure the rx descriptor isn't read before rxretprd */
6aa20a22 1954 if (idx == rxretcsm)
1da177e4
LT		 1955 rmb();
1956
1957 retdesc = &ap->rx_return_ring[idx];
1958 skbidx = retdesc->idx;
1959 bd_flags = retdesc->flags;
1960 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1961
1962 switch(desc_type) {
1963 /*
1964 * Normal frames do not have any flags set
1965 *
1966 * Mini and normal frames arrive frequently,
1967 * so use a local counter to avoid doing
1968 * atomic operations for each packet arriving.
1969 */
1970 case 0:
1971 rip = &ap->skb->rx_std_skbuff[skbidx];
1972 mapsize = ACE_STD_BUFSIZE;
1973 rxdesc = &ap->rx_std_ring[skbidx];
1974 std_count++;
1975 break;
1976 case BD_FLG_JUMBO:
1977 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1978 mapsize = ACE_JUMBO_BUFSIZE;
1979 rxdesc = &ap->rx_jumbo_ring[skbidx];
1980 atomic_dec(&ap->cur_jumbo_bufs);
1981 break;
1982 case BD_FLG_MINI:
1983 rip = &ap->skb->rx_mini_skbuff[skbidx];
1984 mapsize = ACE_MINI_BUFSIZE;
1985 rxdesc = &ap->rx_mini_ring[skbidx];
6aa20a22 1986 mini_count++;
1da177e4
LT		 1987 break;
1988 default:
1989 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
1990 "returned by NIC\n", dev->name,
1991 retdesc->flags);
1992 goto error;
1993 }
1994
1995 skb = rip->skb;
1996 rip->skb = NULL;
1997 pci_unmap_page(ap->pdev,
430e55b1 1998 dma_unmap_addr(rip, mapping),
1da177e4
LT		 1999 mapsize,
2000 PCI_DMA_FROMDEVICE);
2001 skb_put(skb, retdesc->size);
2002
2003 /*
2004 * Fly baby, fly!
2005 */
2006 csum = retdesc->tcp_udp_csum;
2007
1da177e4
LT		 2008 skb->protocol = eth_type_trans(skb, dev);
2009
2010 /*
2011 * Instead of forcing the poor tigon mips cpu to calculate
2012 * pseudo hdr checksum, we do this ourselves.
2013 */
2014 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2015 skb->csum = htons(csum);
84fa7933 2016 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 2017 } else {
bc8acf2c 2018 skb_checksum_none_assert(skb);
1da177e4
LT		 2019 }
2020
2021 /* send it up */
08dddfc3
JP		 2022 if ((bd_flags & BD_FLG_VLAN_TAG))
2023 __vlan_hwaccel_put_tag(skb, retdesc->vlan);
2024 netif_rx(skb);
1da177e4 2025
966e37bc
PZ		 2026 dev->stats.rx_packets++;
2027 dev->stats.rx_bytes += retdesc->size;
1da177e4
LT		 2028
2029 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2030 }
2031
2032 atomic_sub(std_count, &ap->cur_rx_bufs);
2033 if (!ACE_IS_TIGON_I(ap))
2034 atomic_sub(mini_count, &ap->cur_mini_bufs);
2035
2036 out:
2037 /*
2038 * According to the documentation RxRetCsm is obsolete with
2039 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2040 */
2041 if (ACE_IS_TIGON_I(ap)) {
2042 writel(idx, &ap->regs->RxRetCsm);
2043 }
2044 ap->cur_rx = idx;
2045
2046 return;
2047 error:
2048 idx = rxretprd;
2049 goto out;
2050}
2051
2052
2053static inline void ace_tx_int(struct net_device *dev,
2054 u32 txcsm, u32 idx)
2055{
2056 struct ace_private *ap = netdev_priv(dev);
2057
2058 do {
2059 struct sk_buff *skb;
1da177e4
LT		 2060 struct tx_ring_info *info;
2061
2062 info = ap->skb->tx_skbuff + idx;
2063 skb = info->skb;
1da177e4 2064
07e7de8f
FT		 2065 if (dma_unmap_len(info, maplen)) {
2066 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
430e55b1 2067 dma_unmap_len(info, maplen),
1da177e4 2068 PCI_DMA_TODEVICE);
07e7de8f 2069 dma_unmap_len_set(info, maplen, 0);
1da177e4
LT		 2070 }
2071
2072 if (skb) {
966e37bc
PZ		 2073 dev->stats.tx_packets++;
2074 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 2075 dev_kfree_skb_irq(skb);
2076 info->skb = NULL;
2077 }
2078
2079 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2080 } while (idx != txcsm);
2081
2082 if (netif_queue_stopped(dev))
2083 netif_wake_queue(dev);
2084
2085 wmb();
2086 ap->tx_ret_csm = txcsm;
2087
2088 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2089 *
2090 * We could try to make it before. In this case we would get
2091 * the following race condition: hard_start_xmit on other cpu
2092 * enters after we advanced tx_ret_csm and fills space,
2093 * which we have just freed, so that we make illegal device wakeup.
2094 * There is no good way to workaround this (at entry
2095 * to ace_start_xmit detects this condition and prevents
2096 * ring corruption, but it is not a good workaround.)
2097 *
2098 * When tx_ret_csm is advanced after, we wake up device _only_
2099 * if we really have some space in ring (though the core doing
2100 * hard_start_xmit can see full ring for some period and has to
2101 * synchronize.) Superb.
2102 * BUT! We get another subtle race condition. hard_start_xmit
2103 * may think that ring is full between wakeup and advancing
2104 * tx_ret_csm and will stop device instantly! It is not so bad.
2105 * We are guaranteed that there is something in ring, so that
2106 * the next irq will resume transmission. To speedup this we could
2107 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2108 * (see ace_start_xmit).
2109 *
2110 * Well, this dilemma exists in all lock-free devices.
2111 * We, following scheme used in drivers by Donald Becker,
2112 * select the least dangerous.
2113 * --ANK
2114 */
2115}
2116
2117
7d12e780 2118static irqreturn_t ace_interrupt(int irq, void *dev_id)
1da177e4
LT		 2119{
2120 struct net_device *dev = (struct net_device *)dev_id;
2121 struct ace_private *ap = netdev_priv(dev);
2122 struct ace_regs __iomem *regs = ap->regs;
2123 u32 idx;
2124 u32 txcsm, rxretcsm, rxretprd;
2125 u32 evtcsm, evtprd;
2126
2127 /*
2128 * In case of PCI shared interrupts or spurious interrupts,
2129 * we want to make sure it is actually our interrupt before
2130 * spending any time in here.
2131 */
2132 if (!(readl(&regs->HostCtrl) & IN_INT))
2133 return IRQ_NONE;
2134
2135 /*
2136 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2137 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2138 * writel(0, &regs->Mb0Lo).
2139 *
2140 * "IRQ avoidance" recommended in docs applies to IRQs served
2141 * threads and it is wrong even for that case.
2142 */
2143 writel(0, &regs->Mb0Lo);
2144 readl(&regs->Mb0Lo);
2145
2146 /*
2147 * There is no conflict between transmit handling in
2148 * start_xmit and receive processing, thus there is no reason
2149 * to take a spin lock for RX handling. Wait until we start
2150 * working on the other stuff - hey we don't need a spin lock
2151 * anymore.
2152 */
2153 rxretprd = *ap->rx_ret_prd;
2154 rxretcsm = ap->cur_rx;
2155
2156 if (rxretprd != rxretcsm)
2157 ace_rx_int(dev, rxretprd, rxretcsm);
2158
2159 txcsm = *ap->tx_csm;
2160 idx = ap->tx_ret_csm;
2161
2162 if (txcsm != idx) {
2163 /*
2164 * If each skb takes only one descriptor this check degenerates
2165 * to identity, because new space has just been opened.
2166 * But if skbs are fragmented we must check that this index
2167 * update releases enough of space, otherwise we just
2168 * wait for device to make more work.
2169 */
2170 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2171 ace_tx_int(dev, txcsm, idx);
2172 }
2173
2174 evtcsm = readl(&regs->EvtCsm);
2175 evtprd = *ap->evt_prd;
2176
2177 if (evtcsm != evtprd) {
2178 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2179 writel(evtcsm, &regs->EvtCsm);
2180 }
2181
2182 /*
2183 * This has to go last in the interrupt handler and run with
2184 * the spin lock released ... what lock?
2185 */
2186 if (netif_running(dev)) {
2187 int cur_size;
2188 int run_tasklet = 0;
2189
2190 cur_size = atomic_read(&ap->cur_rx_bufs);
2191 if (cur_size < RX_LOW_STD_THRES) {
2192 if ((cur_size < RX_PANIC_STD_THRES) &&
2193 !test_and_set_bit(0, &ap->std_refill_busy)) {
2194#ifdef DEBUG
2195 printk("low on std buffers %i\n", cur_size);
2196#endif
427e21fa 2197 ace_load_std_rx_ring(dev,
1da177e4
LT		 2198 RX_RING_SIZE - cur_size);
2199 } else
2200 run_tasklet = 1;
2201 }
2202
2203 if (!ACE_IS_TIGON_I(ap)) {
2204 cur_size = atomic_read(&ap->cur_mini_bufs);
2205 if (cur_size < RX_LOW_MINI_THRES) {
2206 if ((cur_size < RX_PANIC_MINI_THRES) &&
2207 !test_and_set_bit(0,
2208 &ap->mini_refill_busy)) {
2209#ifdef DEBUG
2210 printk("low on mini buffers %i\n",
2211 cur_size);
2212#endif
427e21fa 2213 ace_load_mini_rx_ring(dev,
2214 RX_MINI_SIZE - cur_size);
1da177e4
LT		 2215 } else
2216 run_tasklet = 1;
2217 }
2218 }
2219
2220 if (ap->jumbo) {
2221 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2222 if (cur_size < RX_LOW_JUMBO_THRES) {
2223 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2224 !test_and_set_bit(0,
2225 &ap->jumbo_refill_busy)){
2226#ifdef DEBUG
2227 printk("low on jumbo buffers %i\n",
2228 cur_size);
2229#endif
427e21fa 2230 ace_load_jumbo_rx_ring(dev,
2231 RX_JUMBO_SIZE - cur_size);
1da177e4
LT		 2232 } else
2233 run_tasklet = 1;
2234 }
2235 }
2236 if (run_tasklet && !ap->tasklet_pending) {
2237 ap->tasklet_pending = 1;
2238 tasklet_schedule(&ap->ace_tasklet);
2239 }
2240 }
2241
2242 return IRQ_HANDLED;
2243}
2244
1da177e4
LT		 2245static int ace_open(struct net_device *dev)
2246{
2247 struct ace_private *ap = netdev_priv(dev);
2248 struct ace_regs __iomem *regs = ap->regs;
2249 struct cmd cmd;
2250
2251 if (!(ap->fw_running)) {
2252 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2253 return -EBUSY;
2254 }
2255
2256 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2257
2258 cmd.evt = C_CLEAR_STATS;
2259 cmd.code = 0;
2260 cmd.idx = 0;
2261 ace_issue_cmd(regs, &cmd);
2262
2263 cmd.evt = C_HOST_STATE;
2264 cmd.code = C_C_STACK_UP;
2265 cmd.idx = 0;
2266 ace_issue_cmd(regs, &cmd);
2267
2268 if (ap->jumbo &&
2269 !test_and_set_bit(0, &ap->jumbo_refill_busy))
427e21fa 2270 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
1da177e4
LT		 2271
2272 if (dev->flags & IFF_PROMISC) {
2273 cmd.evt = C_SET_PROMISC_MODE;
2274 cmd.code = C_C_PROMISC_ENABLE;
2275 cmd.idx = 0;
2276 ace_issue_cmd(regs, &cmd);
2277
2278 ap->promisc = 1;
2279 }else
2280 ap->promisc = 0;
2281 ap->mcast_all = 0;
2282
2283#if 0
2284 cmd.evt = C_LNK_NEGOTIATION;
2285 cmd.code = 0;
2286 cmd.idx = 0;
2287 ace_issue_cmd(regs, &cmd);
2288#endif
2289
2290 netif_start_queue(dev);
2291
2292 /*
2293 * Setup the bottom half rx ring refill handler
2294 */
2295 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2296 return 0;
2297}
2298
2299
2300static int ace_close(struct net_device *dev)
2301{
2302 struct ace_private *ap = netdev_priv(dev);
2303 struct ace_regs __iomem *regs = ap->regs;
2304 struct cmd cmd;
2305 unsigned long flags;
2306 short i;
2307
2308 /*
2309 * Without (or before) releasing irq and stopping hardware, this
2310 * is an absolute non-sense, by the way. It will be reset instantly
2311 * by the first irq.
2312 */
2313 netif_stop_queue(dev);
2314
6aa20a22 2315
1da177e4
LT		 2316 if (ap->promisc) {
2317 cmd.evt = C_SET_PROMISC_MODE;
2318 cmd.code = C_C_PROMISC_DISABLE;
2319 cmd.idx = 0;
2320 ace_issue_cmd(regs, &cmd);
2321 ap->promisc = 0;
2322 }
2323
2324 cmd.evt = C_HOST_STATE;
2325 cmd.code = C_C_STACK_DOWN;
2326 cmd.idx = 0;
2327 ace_issue_cmd(regs, &cmd);
2328
2329 tasklet_kill(&ap->ace_tasklet);
2330
2331 /*
2332 * Make sure one CPU is not processing packets while
2333 * buffers are being released by another.
2334 */
2335
2336 local_irq_save(flags);
2337 ace_mask_irq(dev);
2338
2339 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2340 struct sk_buff *skb;
1da177e4
LT		 2341 struct tx_ring_info *info;
2342
2343 info = ap->skb->tx_skbuff + i;
2344 skb = info->skb;
1da177e4 2345
07e7de8f 2346 if (dma_unmap_len(info, maplen)) {
1da177e4 2347 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb
SH		 2348 /* NB: TIGON_1 is special, tx_ring is in io space */
2349 struct tx_desc __iomem *tx;
2350 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
1da177e4
LT		 2351 writel(0, &tx->addr.addrhi);
2352 writel(0, &tx->addr.addrlo);
2353 writel(0, &tx->flagsize);
2354 } else
2355 memset(ap->tx_ring + i, 0,
2356 sizeof(struct tx_desc));
07e7de8f 2357 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
430e55b1 2358 dma_unmap_len(info, maplen),
1da177e4 2359 PCI_DMA_TODEVICE);
07e7de8f 2360 dma_unmap_len_set(info, maplen, 0);
1da177e4
LT		 2361 }
2362 if (skb) {
2363 dev_kfree_skb(skb);
2364 info->skb = NULL;
2365 }
2366 }
2367
2368 if (ap->jumbo) {
2369 cmd.evt = C_RESET_JUMBO_RNG;
2370 cmd.code = 0;
2371 cmd.idx = 0;
2372 ace_issue_cmd(regs, &cmd);
2373 }
2374
2375 ace_unmask_irq(dev);
2376 local_irq_restore(flags);
2377
2378 return 0;
2379}
2380
2381
2382static inline dma_addr_t
2383ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2384 struct sk_buff *tail, u32 idx)
2385{
2386 dma_addr_t mapping;
2387 struct tx_ring_info *info;
2388
2389 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2390 offset_in_page(skb->data),
2391 skb->len, PCI_DMA_TODEVICE);
2392
2393 info = ap->skb->tx_skbuff + idx;
2394 info->skb = tail;
430e55b1
FT		 2395 dma_unmap_addr_set(info, mapping, mapping);
2396 dma_unmap_len_set(info, maplen, skb->len);
1da177e4
LT		 2397 return mapping;
2398}
2399
2400
2401static inline void
2402ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2403 u32 flagsize, u32 vlan_tag)
2404{
2405#if !USE_TX_COAL_NOW
2406 flagsize &= ~BD_FLG_COAL_NOW;
2407#endif
2408
2409 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 2410 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
1da177e4
LT		 2411 writel(addr >> 32, &io->addr.addrhi);
2412 writel(addr & 0xffffffff, &io->addr.addrlo);
2413 writel(flagsize, &io->flagsize);
1da177e4 2414 writel(vlan_tag, &io->vlanres);
1da177e4
LT		 2415 } else {
2416 desc->addr.addrhi = addr >> 32;
2417 desc->addr.addrlo = addr;
2418 desc->flagsize = flagsize;
1da177e4 2419 desc->vlanres = vlan_tag;
1da177e4
LT		 2420 }
2421}
2422
2423
61357325
SH		 2424static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
2425 struct net_device *dev)
1da177e4
LT		 2426{
2427 struct ace_private *ap = netdev_priv(dev);
2428 struct ace_regs __iomem *regs = ap->regs;
2429 struct tx_desc *desc;
2430 u32 idx, flagsize;
2431 unsigned long maxjiff = jiffies + 3*HZ;
2432
2433restart:
2434 idx = ap->tx_prd;
2435
2436 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2437 goto overflow;
2438
2439 if (!skb_shinfo(skb)->nr_frags) {
2440 dma_addr_t mapping;
2441 u32 vlan_tag = 0;
2442
2443 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2444 flagsize = (skb->len << 16) | (BD_FLG_END);
84fa7933 2445 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 2446 flagsize |= BD_FLG_TCP_UDP_SUM;
1da177e4
LT		 2447 if (vlan_tx_tag_present(skb)) {
2448 flagsize |= BD_FLG_VLAN_TAG;
2449 vlan_tag = vlan_tx_tag_get(skb);
2450 }
1da177e4
LT		 2451 desc = ap->tx_ring + idx;
2452 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2453
2454 /* Look at ace_tx_int for explanations. */
2455 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2456 flagsize |= BD_FLG_COAL_NOW;
2457
2458 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2459 } else {
2460 dma_addr_t mapping;
2461 u32 vlan_tag = 0;
2462 int i, len = 0;
2463
2464 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2465 flagsize = (skb_headlen(skb) << 16);
84fa7933 2466 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 2467 flagsize |= BD_FLG_TCP_UDP_SUM;
1da177e4
LT		 2468 if (vlan_tx_tag_present(skb)) {
2469 flagsize |= BD_FLG_VLAN_TAG;
2470 vlan_tag = vlan_tx_tag_get(skb);
2471 }
1da177e4
LT		 2472
2473 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2474
2475 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2476
2477 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 2478 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1da177e4
LT		 2479 struct tx_ring_info *info;
2480
9e903e08 2481 len += skb_frag_size(frag);
1da177e4
LT		 2482 info = ap->skb->tx_skbuff + idx;
2483 desc = ap->tx_ring + idx;
2484
c4c8d579 2485 mapping = skb_frag_dma_map(&ap->pdev->dev, frag, 0,
9e903e08 2486 skb_frag_size(frag),
5d6bcdfe 2487 DMA_TO_DEVICE);
1da177e4 2488
9e903e08 2489 flagsize = skb_frag_size(frag) << 16;
84fa7933 2490 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2491 flagsize |= BD_FLG_TCP_UDP_SUM;
2492 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2493
2494 if (i == skb_shinfo(skb)->nr_frags - 1) {
2495 flagsize |= BD_FLG_END;
2496 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2497 flagsize |= BD_FLG_COAL_NOW;
2498
2499 /*
2500 * Only the last fragment frees
2501 * the skb!
2502 */
2503 info->skb = skb;
2504 } else {
2505 info->skb = NULL;
2506 }
430e55b1 2507 dma_unmap_addr_set(info, mapping, mapping);
9e903e08 2508 dma_unmap_len_set(info, maplen, skb_frag_size(frag));
1da177e4
LT		 2509 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2510 }
2511 }
2512
2513 wmb();
2514 ap->tx_prd = idx;
2515 ace_set_txprd(regs, ap, idx);
2516
2517 if (flagsize & BD_FLG_COAL_NOW) {
2518 netif_stop_queue(dev);
2519
2520 /*
2521 * A TX-descriptor producer (an IRQ) might have gotten
25985edc 2522 * between, making the ring free again. Since xmit is
1da177e4
LT		 2523 * serialized, this is the only situation we have to
2524 * re-test.
2525 */
2526 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2527 netif_wake_queue(dev);
2528 }
2529
1da177e4
LT		 2530 return NETDEV_TX_OK;
2531
2532overflow:
2533 /*
2534 * This race condition is unavoidable with lock-free drivers.
2535 * We wake up the queue _before_ tx_prd is advanced, so that we can
2536 * enter hard_start_xmit too early, while tx ring still looks closed.
2537 * This happens ~1-4 times per 100000 packets, so that we can allow
2538 * to loop syncing to other CPU. Probably, we need an additional
2539 * wmb() in ace_tx_intr as well.
2540 *
2541 * Note that this race is relieved by reserving one more entry
2542 * in tx ring than it is necessary (see original non-SG driver).
2543 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2544 * is already overkill.
2545 *
2546 * Alternative is to return with 1 not throttling queue. In this
2547 * case loop becomes longer, no more useful effects.
2548 */
2549 if (time_before(jiffies, maxjiff)) {
2550 barrier();
2551 cpu_relax();
2552 goto restart;
2553 }
6aa20a22 2554
1da177e4
LT		 2555 /* The ring is stuck full. */
2556 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2557 return NETDEV_TX_BUSY;
2558}
2559
2560
2561static int ace_change_mtu(struct net_device *dev, int new_mtu)
2562{
2563 struct ace_private *ap = netdev_priv(dev);
2564 struct ace_regs __iomem *regs = ap->regs;
2565
2566 if (new_mtu > ACE_JUMBO_MTU)
2567 return -EINVAL;
2568
2569 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2570 dev->mtu = new_mtu;
2571
2572 if (new_mtu > ACE_STD_MTU) {
2573 if (!(ap->jumbo)) {
2574 printk(KERN_INFO "%s: Enabling Jumbo frame "
2575 "support\n", dev->name);
2576 ap->jumbo = 1;
2577 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
427e21fa 2578 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
1da177e4
LT		 2579 ace_set_rxtx_parms(dev, 1);
2580 }
2581 } else {
2582 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2583 ace_sync_irq(dev->irq);
2584 ace_set_rxtx_parms(dev, 0);
2585 if (ap->jumbo) {
2586 struct cmd cmd;
2587
2588 cmd.evt = C_RESET_JUMBO_RNG;
2589 cmd.code = 0;
2590 cmd.idx = 0;
2591 ace_issue_cmd(regs, &cmd);
2592 }
2593 }
2594
2595 return 0;
2596}
2597
2598static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2599{
2600 struct ace_private *ap = netdev_priv(dev);
2601 struct ace_regs __iomem *regs = ap->regs;
2602 u32 link;
2603
2604 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2605 ecmd->supported =
2606 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2607 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2608 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2609 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2610
2611 ecmd->port = PORT_FIBRE;
2612 ecmd->transceiver = XCVR_INTERNAL;
2613
2614 link = readl(&regs->GigLnkState);
2615 if (link & LNK_1000MB)
70739497 2616 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1da177e4
LT		 2617 else {
2618 link = readl(&regs->FastLnkState);
2619 if (link & LNK_100MB)
70739497 2620 ethtool_cmd_speed_set(ecmd, SPEED_100);
1da177e4 2621 else if (link & LNK_10MB)
70739497 2622 ethtool_cmd_speed_set(ecmd, SPEED_10);
1da177e4 2623 else
70739497 2624 ethtool_cmd_speed_set(ecmd, 0);
1da177e4
LT		 2625 }
2626 if (link & LNK_FULL_DUPLEX)
2627 ecmd->duplex = DUPLEX_FULL;
2628 else
2629 ecmd->duplex = DUPLEX_HALF;
2630
2631 if (link & LNK_NEGOTIATE)
2632 ecmd->autoneg = AUTONEG_ENABLE;
2633 else
2634 ecmd->autoneg = AUTONEG_DISABLE;
2635
2636#if 0
2637 /*
2638 * Current struct ethtool_cmd is insufficient
2639 */
2640 ecmd->trace = readl(&regs->TuneTrace);
2641
2642 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2643 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2644#endif
2645 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2646 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2647
2648 return 0;
2649}
2650
2651static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2652{
2653 struct ace_private *ap = netdev_priv(dev);
2654 struct ace_regs __iomem *regs = ap->regs;
2655 u32 link, speed;
2656
2657 link = readl(&regs->GigLnkState);
2658 if (link & LNK_1000MB)
2659 speed = SPEED_1000;
2660 else {
2661 link = readl(&regs->FastLnkState);
2662 if (link & LNK_100MB)
2663 speed = SPEED_100;
2664 else if (link & LNK_10MB)
2665 speed = SPEED_10;
2666 else
2667 speed = SPEED_100;
2668 }
2669
2670 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2671 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2672 if (!ACE_IS_TIGON_I(ap))
2673 link |= LNK_TX_FLOW_CTL_Y;
2674 if (ecmd->autoneg == AUTONEG_ENABLE)
2675 link |= LNK_NEGOTIATE;
25db0338 2676 if (ethtool_cmd_speed(ecmd) != speed) {
1da177e4 2677 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
1258c076 2678 switch (ethtool_cmd_speed(ecmd)) {
1da177e4
LT		 2679 case SPEED_1000:
2680 link |= LNK_1000MB;
2681 break;
2682 case SPEED_100:
2683 link |= LNK_100MB;
2684 break;
2685 case SPEED_10:
2686 link |= LNK_10MB;
2687 break;
2688 }
2689 }
2690
2691 if (ecmd->duplex == DUPLEX_FULL)
2692 link |= LNK_FULL_DUPLEX;
2693
2694 if (link != ap->link) {
2695 struct cmd cmd;
2696 printk(KERN_INFO "%s: Renegotiating link state\n",
2697 dev->name);
2698
2699 ap->link = link;
2700 writel(link, &regs->TuneLink);
2701 if (!ACE_IS_TIGON_I(ap))
2702 writel(link, &regs->TuneFastLink);
2703 wmb();
2704
2705 cmd.evt = C_LNK_NEGOTIATION;
2706 cmd.code = 0;
2707 cmd.idx = 0;
2708 ace_issue_cmd(regs, &cmd);
2709 }
2710 return 0;
2711}
2712
6aa20a22 2713static void ace_get_drvinfo(struct net_device *dev,
1da177e4
LT		 2714 struct ethtool_drvinfo *info)
2715{
2716 struct ace_private *ap = netdev_priv(dev);
2717
2718 strlcpy(info->driver, "acenic", sizeof(info->driver));
6aa20a22 2719 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
949b4254
JS		 2720 ap->firmware_major, ap->firmware_minor,
2721 ap->firmware_fix);
1da177e4
LT		 2722
2723 if (ap->pdev)
6aa20a22 2724 strlcpy(info->bus_info, pci_name(ap->pdev),
1da177e4
LT		 2725 sizeof(info->bus_info));
2726
2727}
2728
2729/*
2730 * Set the hardware MAC address.
2731 */
2732static int ace_set_mac_addr(struct net_device *dev, void *p)
2733{
2734 struct ace_private *ap = netdev_priv(dev);
2735 struct ace_regs __iomem *regs = ap->regs;
2736 struct sockaddr *addr=p;
2737 u8 *da;
2738 struct cmd cmd;
2739
2740 if(netif_running(dev))
2741 return -EBUSY;
2742
2743 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2744
2745 da = (u8 *)dev->dev_addr;
2746
2747 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2748 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2749 &regs->MacAddrLo);
2750
2751 cmd.evt = C_SET_MAC_ADDR;
2752 cmd.code = 0;
2753 cmd.idx = 0;
2754 ace_issue_cmd(regs, &cmd);
2755
2756 return 0;
2757}
2758
2759
2760static void ace_set_multicast_list(struct net_device *dev)
2761{
2762 struct ace_private *ap = netdev_priv(dev);
2763 struct ace_regs __iomem *regs = ap->regs;
2764 struct cmd cmd;
2765
2766 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2767 cmd.evt = C_SET_MULTICAST_MODE;
2768 cmd.code = C_C_MCAST_ENABLE;
2769 cmd.idx = 0;
2770 ace_issue_cmd(regs, &cmd);
2771 ap->mcast_all = 1;
2772 } else if (ap->mcast_all) {
2773 cmd.evt = C_SET_MULTICAST_MODE;
2774 cmd.code = C_C_MCAST_DISABLE;
2775 cmd.idx = 0;
2776 ace_issue_cmd(regs, &cmd);
2777 ap->mcast_all = 0;
2778 }
2779
2780 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2781 cmd.evt = C_SET_PROMISC_MODE;
2782 cmd.code = C_C_PROMISC_ENABLE;
2783 cmd.idx = 0;
2784 ace_issue_cmd(regs, &cmd);
2785 ap->promisc = 1;
2786 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2787 cmd.evt = C_SET_PROMISC_MODE;
2788 cmd.code = C_C_PROMISC_DISABLE;
2789 cmd.idx = 0;
2790 ace_issue_cmd(regs, &cmd);
2791 ap->promisc = 0;
2792 }
2793
2794 /*
2795 * For the time being multicast relies on the upper layers
2796 * filtering it properly. The Firmware does not allow one to
2797 * set the entire multicast list at a time and keeping track of
2798 * it here is going to be messy.
2799 */
4cd24eaf 2800 if (!netdev_mc_empty(dev) && !ap->mcast_all) {
1da177e4
LT		 2801 cmd.evt = C_SET_MULTICAST_MODE;
2802 cmd.code = C_C_MCAST_ENABLE;
2803 cmd.idx = 0;
2804 ace_issue_cmd(regs, &cmd);
2805 }else if (!ap->mcast_all) {
2806 cmd.evt = C_SET_MULTICAST_MODE;
2807 cmd.code = C_C_MCAST_DISABLE;
2808 cmd.idx = 0;
2809 ace_issue_cmd(regs, &cmd);
2810 }
2811}
2812
2813
2814static struct net_device_stats *ace_get_stats(struct net_device *dev)
2815{
2816 struct ace_private *ap = netdev_priv(dev);
2817 struct ace_mac_stats __iomem *mac_stats =
2818 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2819
966e37bc
PZ		 2820 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2821 dev->stats.multicast = readl(&mac_stats->kept_mc);
2822 dev->stats.collisions = readl(&mac_stats->coll);
1da177e4 2823
966e37bc 2824 return &dev->stats;
1da177e4
LT		 2825}
2826
2827
949b4254
JS		 2828static void __devinit ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
2829 u32 dest, int size)
1da177e4
LT		 2830{
2831 void __iomem *tdest;
1da177e4
LT		 2832 short tsize, i;
2833
2834 if (size <= 0)
2835 return;
2836
2837 while (size > 0) {
2838 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2839 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2840 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2841 (dest & (ACE_WINDOW_SIZE - 1));
2842 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
1da177e4 2843 for (i = 0; i < (tsize / 4); i++) {
949b4254
JS		 2844 /* Firmware is big-endian */
2845 writel(be32_to_cpup(src), tdest);
2846 src++;
2847 tdest += 4;
2848 dest += 4;
2849 size -= 4;
1da177e4 2850 }
1da177e4 2851 }
1da177e4
LT		 2852}
2853
2854
2855static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2856{
2857 void __iomem *tdest;
2858 short tsize = 0, i;
2859
2860 if (size <= 0)
2861 return;
2862
2863 while (size > 0) {
2864 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2865 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2866 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2867 (dest & (ACE_WINDOW_SIZE - 1));
2868 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2869
2870 for (i = 0; i < (tsize / 4); i++) {
2871 writel(0, tdest + i*4);
2872 }
2873
2874 dest += tsize;
2875 size -= tsize;
2876 }
1da177e4
LT		 2877}
2878
2879
2880/*
2881 * Download the firmware into the SRAM on the NIC
2882 *
2883 * This operation requires the NIC to be halted and is performed with
2884 * interrupts disabled and with the spinlock hold.
2885 */
ddfce6bb 2886static int __devinit ace_load_firmware(struct net_device *dev)
1da177e4 2887{
949b4254
JS		 2888 const struct firmware *fw;
2889 const char *fw_name = "acenic/tg2.bin";
1da177e4
LT		 2890 struct ace_private *ap = netdev_priv(dev);
2891 struct ace_regs __iomem *regs = ap->regs;
949b4254
JS		 2892 const __be32 *fw_data;
2893 u32 load_addr;
2894 int ret;
1da177e4
LT		 2895
2896 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2897 printk(KERN_ERR "%s: trying to download firmware while the "
2898 "CPU is running!\n", ap->name);
2899 return -EFAULT;
2900 }
2901
949b4254
JS		 2902 if (ACE_IS_TIGON_I(ap))
2903 fw_name = "acenic/tg1.bin";
2904
2905 ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2906 if (ret) {
2907 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2908 ap->name, fw_name);
2909 return ret;
2910 }
2911
2912 fw_data = (void *)fw->data;
2913
2914 /* Firmware blob starts with version numbers, followed by
2915 load and start address. Remainder is the blob to be loaded
2916 contiguously from load address. We don't bother to represent
2917 the BSS/SBSS sections any more, since we were clearing the
2918 whole thing anyway. */
2919 ap->firmware_major = fw->data[0];
2920 ap->firmware_minor = fw->data[1];
2921 ap->firmware_fix = fw->data[2];
2922
2923 ap->firmware_start = be32_to_cpu(fw_data[1]);
2924 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2925 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2926 ap->name, ap->firmware_start, fw_name);
2927 ret = -EINVAL;
2928 goto out;
2929 }
2930
2931 load_addr = be32_to_cpu(fw_data[2]);
2932 if (load_addr < 0x4000 || load_addr >= 0x80000) {
2933 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2934 ap->name, load_addr, fw_name);
2935 ret = -EINVAL;
2936 goto out;
2937 }
2938
1da177e4 2939 /*
949b4254
JS		 2940 * Do not try to clear more than 512KiB or we end up seeing
2941 * funny things on NICs with only 512KiB SRAM
1da177e4
LT		 2942 */
2943 ace_clear(regs, 0x2000, 0x80000-0x2000);
949b4254
JS		 2944 ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2945 out:
2946 release_firmware(fw);
2947 return ret;
1da177e4
LT		 2948}
2949
2950
2951/*
2952 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
2953 *
2954 * Accessing the EEPROM is `interesting' to say the least - don't read
2955 * this code right after dinner.
2956 *
2957 * This is all about black magic and bit-banging the device .... I
2958 * wonder in what hospital they have put the guy who designed the i2c
2959 * specs.
2960 *
2961 * Oh yes, this is only the beginning!
2962 *
2963 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
2964 * code i2c readout code by beta testing all my hacks.
2965 */
2966static void __devinit eeprom_start(struct ace_regs __iomem *regs)
2967{
2968 u32 local;
2969
2970 readl(&regs->LocalCtrl);
2971 udelay(ACE_SHORT_DELAY);
2972 local = readl(&regs->LocalCtrl);
2973 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
2974 writel(local, &regs->LocalCtrl);
2975 readl(&regs->LocalCtrl);
2976 mb();
2977 udelay(ACE_SHORT_DELAY);
2978 local |= EEPROM_CLK_OUT;
2979 writel(local, &regs->LocalCtrl);
2980 readl(&regs->LocalCtrl);
2981 mb();
2982 udelay(ACE_SHORT_DELAY);
2983 local &= ~EEPROM_DATA_OUT;
2984 writel(local, &regs->LocalCtrl);
2985 readl(&regs->LocalCtrl);
2986 mb();
2987 udelay(ACE_SHORT_DELAY);
2988 local &= ~EEPROM_CLK_OUT;
2989 writel(local, &regs->LocalCtrl);
2990 readl(&regs->LocalCtrl);
2991 mb();
2992}
2993
2994
2995static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
2996{
2997 short i;
2998 u32 local;
2999
3000 udelay(ACE_SHORT_DELAY);
3001 local = readl(&regs->LocalCtrl);
3002 local &= ~EEPROM_DATA_OUT;
3003 local |= EEPROM_WRITE_ENABLE;
3004 writel(local, &regs->LocalCtrl);
3005 readl(&regs->LocalCtrl);
3006 mb();
3007
3008 for (i = 0; i < 8; i++, magic <<= 1) {
3009 udelay(ACE_SHORT_DELAY);
6aa20a22 3010 if (magic & 0x80)
1da177e4
LT		 3011 local |= EEPROM_DATA_OUT;
3012 else
3013 local &= ~EEPROM_DATA_OUT;
3014 writel(local, &regs->LocalCtrl);
3015 readl(&regs->LocalCtrl);
3016 mb();
3017
3018 udelay(ACE_SHORT_DELAY);
3019 local |= EEPROM_CLK_OUT;
3020 writel(local, &regs->LocalCtrl);
3021 readl(&regs->LocalCtrl);
3022 mb();
3023 udelay(ACE_SHORT_DELAY);
3024 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3025 writel(local, &regs->LocalCtrl);
3026 readl(&regs->LocalCtrl);
3027 mb();
3028 }
3029}
3030
3031
3032static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3033{
3034 int state;
3035 u32 local;
3036
3037 local = readl(&regs->LocalCtrl);
3038 local &= ~EEPROM_WRITE_ENABLE;
3039 writel(local, &regs->LocalCtrl);
3040 readl(&regs->LocalCtrl);
3041 mb();
3042 udelay(ACE_LONG_DELAY);
3043 local |= EEPROM_CLK_OUT;
3044 writel(local, &regs->LocalCtrl);
3045 readl(&regs->LocalCtrl);
3046 mb();
3047 udelay(ACE_SHORT_DELAY);
3048 /* sample data in middle of high clk */
3049 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3050 udelay(ACE_SHORT_DELAY);
3051 mb();
3052 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3053 readl(&regs->LocalCtrl);
3054 mb();
3055
3056 return state;
3057}
3058
3059
3060static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3061{
3062 u32 local;
3063
3064 udelay(ACE_SHORT_DELAY);
3065 local = readl(&regs->LocalCtrl);
3066 local |= EEPROM_WRITE_ENABLE;
3067 writel(local, &regs->LocalCtrl);
3068 readl(&regs->LocalCtrl);
3069 mb();
3070 udelay(ACE_SHORT_DELAY);
3071 local &= ~EEPROM_DATA_OUT;
3072 writel(local, &regs->LocalCtrl);
3073 readl(&regs->LocalCtrl);
3074 mb();
3075 udelay(ACE_SHORT_DELAY);
3076 local |= EEPROM_CLK_OUT;
3077 writel(local, &regs->LocalCtrl);
3078 readl(&regs->LocalCtrl);
3079 mb();
3080 udelay(ACE_SHORT_DELAY);
3081 local |= EEPROM_DATA_OUT;
3082 writel(local, &regs->LocalCtrl);
3083 readl(&regs->LocalCtrl);
3084 mb();
3085 udelay(ACE_LONG_DELAY);
3086 local &= ~EEPROM_CLK_OUT;
3087 writel(local, &regs->LocalCtrl);
3088 mb();
3089}
3090
3091
3092/*
3093 * Read a whole byte from the EEPROM.
3094 */
3095static int __devinit read_eeprom_byte(struct net_device *dev,
3096 unsigned long offset)
3097{
3098 struct ace_private *ap = netdev_priv(dev);
3099 struct ace_regs __iomem *regs = ap->regs;
3100 unsigned long flags;
3101 u32 local;
3102 int result = 0;
3103 short i;
3104
1da177e4
LT		 3105 /*
3106 * Don't take interrupts on this CPU will bit banging
3107 * the %#%#@$ I2C device
3108 */
3109 local_irq_save(flags);
3110
3111 eeprom_start(regs);
3112
3113 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3114 if (eeprom_check_ack(regs)) {
3115 local_irq_restore(flags);
3116 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3117 result = -EIO;
3118 goto eeprom_read_error;
3119 }
3120
3121 eeprom_prep(regs, (offset >> 8) & 0xff);
3122 if (eeprom_check_ack(regs)) {
3123 local_irq_restore(flags);
3124 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3125 ap->name);
3126 result = -EIO;
3127 goto eeprom_read_error;
3128 }
3129
3130 eeprom_prep(regs, offset & 0xff);
3131 if (eeprom_check_ack(regs)) {
3132 local_irq_restore(flags);
3133 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3134 ap->name);
3135 result = -EIO;
3136 goto eeprom_read_error;
3137 }
3138
3139 eeprom_start(regs);
3140 eeprom_prep(regs, EEPROM_READ_SELECT);
3141 if (eeprom_check_ack(regs)) {
3142 local_irq_restore(flags);
3143 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3144 ap->name);
3145 result = -EIO;
3146 goto eeprom_read_error;
3147 }
3148
3149 for (i = 0; i < 8; i++) {
3150 local = readl(&regs->LocalCtrl);
3151 local &= ~EEPROM_WRITE_ENABLE;
3152 writel(local, &regs->LocalCtrl);
3153 readl(&regs->LocalCtrl);
3154 udelay(ACE_LONG_DELAY);
3155 mb();
3156 local |= EEPROM_CLK_OUT;
3157 writel(local, &regs->LocalCtrl);
3158 readl(&regs->LocalCtrl);
3159 mb();
3160 udelay(ACE_SHORT_DELAY);
3161 /* sample data mid high clk */
3162 result = (result << 1) |
3163 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3164 udelay(ACE_SHORT_DELAY);
3165 mb();
3166 local = readl(&regs->LocalCtrl);
3167 local &= ~EEPROM_CLK_OUT;
3168 writel(local, &regs->LocalCtrl);
3169 readl(&regs->LocalCtrl);
3170 udelay(ACE_SHORT_DELAY);
3171 mb();
3172 if (i == 7) {
3173 local |= EEPROM_WRITE_ENABLE;
3174 writel(local, &regs->LocalCtrl);
3175 readl(&regs->LocalCtrl);
3176 mb();
3177 udelay(ACE_SHORT_DELAY);
3178 }
3179 }
3180
3181 local |= EEPROM_DATA_OUT;
3182 writel(local, &regs->LocalCtrl);
3183 readl(&regs->LocalCtrl);
3184 mb();
3185 udelay(ACE_SHORT_DELAY);
3186 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3187 readl(&regs->LocalCtrl);
3188 udelay(ACE_LONG_DELAY);
3189 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3190 readl(&regs->LocalCtrl);
3191 mb();
3192 udelay(ACE_SHORT_DELAY);
3193 eeprom_stop(regs);
3194
3195 local_irq_restore(flags);
3196 out:
3197 return result;
3198
3199 eeprom_read_error:
3200 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3201 ap->name, offset);
3202 goto out;
3203}
Linux 6.x block layer and io_uring tree(s)