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MIPS: define ioremap_nocache to ioremap
[linux-2.6-block.git] / drivers / net / ethernet / alacritech / slicoss.c
CommitLineData
2504ba9f 1// SPDX-License-Identifier: GPL-2.0-only
60c140df
LS		 2/*
3 * Driver for Gigabit Ethernet adapters based on the Session Layer
4 * Interface (SLIC) technology by Alacritech. The driver does not
5 * support the hardware acceleration features provided by these cards.
6 *
7 * Copyright (C) 2016 Lino Sanfilippo <LinoSanfilippo@gmx.de>
60c140df
LS		 8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/if_ether.h>
16#include <linux/crc32.h>
17#include <linux/dma-mapping.h>
18#include <linux/ethtool.h>
19#include <linux/mii.h>
20#include <linux/interrupt.h>
21#include <linux/delay.h>
22#include <linux/firmware.h>
23#include <linux/list.h>
24#include <linux/u64_stats_sync.h>
25
26#include "slic.h"
27
28#define DRV_NAME "slicoss"
29#define DRV_VERSION "1.0"
30
31static const struct pci_device_id slic_id_tbl[] = {
32 { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH,
33 PCI_DEVICE_ID_ALACRITECH_MOJAVE) },
34 { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH,
35 PCI_DEVICE_ID_ALACRITECH_OASIS) },
36 { 0 }
37};
38
39static const char slic_stats_strings[][ETH_GSTRING_LEN] = {
40 "rx_packets",
41 "rx_bytes",
42 "rx_multicasts",
43 "rx_errors",
44 "rx_buff_miss",
45 "rx_tp_csum",
46 "rx_tp_oflow",
47 "rx_tp_hlen",
48 "rx_ip_csum",
49 "rx_ip_len",
50 "rx_ip_hdr_len",
51 "rx_early",
52 "rx_buff_oflow",
53 "rx_lcode",
54 "rx_drbl",
55 "rx_crc",
56 "rx_oflow_802",
57 "rx_uflow_802",
58 "tx_packets",
59 "tx_bytes",
60 "tx_carrier",
61 "tx_dropped",
62 "irq_errs",
63};
64
65static inline int slic_next_queue_idx(unsigned int idx, unsigned int qlen)
66{
67 return (idx + 1) & (qlen - 1);
68}
69
70static inline int slic_get_free_queue_descs(unsigned int put_idx,
71 unsigned int done_idx,
72 unsigned int qlen)
73{
74 if (put_idx >= done_idx)
75 return (qlen - (put_idx - done_idx) - 1);
76 return (done_idx - put_idx - 1);
77}
78
79static unsigned int slic_next_compl_idx(struct slic_device *sdev)
80{
81 struct slic_stat_queue *stq = &sdev->stq;
82 unsigned int active = stq->active_array;
83 struct slic_stat_desc *descs;
84 struct slic_stat_desc *stat;
85 unsigned int idx;
86
87 descs = stq->descs[active];
88 stat = &descs[stq->done_idx];
89
90 if (!stat->status)
91 return SLIC_INVALID_STAT_DESC_IDX;
92
93 idx = (le32_to_cpu(stat->hnd) & 0xffff) - 1;
94 /* reset desc */
95 stat->hnd = 0;
96 stat->status = 0;
97
98 stq->done_idx = slic_next_queue_idx(stq->done_idx, stq->len);
99 /* check for wraparound */
100 if (!stq->done_idx) {
101 dma_addr_t paddr = stq->paddr[active];
102
103 slic_write(sdev, SLIC_REG_RBAR, lower_32_bits(paddr) |
104 stq->len);
105 /* make sure new status descriptors are immediately available */
106 slic_flush_write(sdev);
107 active++;
108 active &= (SLIC_NUM_STAT_DESC_ARRAYS - 1);
109 stq->active_array = active;
110 }
111 return idx;
112}
113
114static unsigned int slic_get_free_tx_descs(struct slic_tx_queue *txq)
115{
116 /* ensure tail idx is updated */
117 smp_mb();
118 return slic_get_free_queue_descs(txq->put_idx, txq->done_idx, txq->len);
119}
120
121static unsigned int slic_get_free_rx_descs(struct slic_rx_queue *rxq)
122{
123 return slic_get_free_queue_descs(rxq->put_idx, rxq->done_idx, rxq->len);
124}
125
126static void slic_clear_upr_list(struct slic_upr_list *upr_list)
127{
128 struct slic_upr *upr;
129 struct slic_upr *tmp;
130
131 spin_lock_bh(&upr_list->lock);
132 list_for_each_entry_safe(upr, tmp, &upr_list->list, list) {
133 list_del(&upr->list);
134 kfree(upr);
135 }
136 upr_list->pending = false;
137 spin_unlock_bh(&upr_list->lock);
138}
139
140static void slic_start_upr(struct slic_device *sdev, struct slic_upr *upr)
141{
142 u32 reg;
143
144 reg = (upr->type == SLIC_UPR_CONFIG) ? SLIC_REG_RCONFIG :
145 SLIC_REG_LSTAT;
146 slic_write(sdev, reg, lower_32_bits(upr->paddr));
147 slic_flush_write(sdev);
148}
149
150static void slic_queue_upr(struct slic_device *sdev, struct slic_upr *upr)
151{
152 struct slic_upr_list *upr_list = &sdev->upr_list;
153 bool pending;
154
155 spin_lock_bh(&upr_list->lock);
156 pending = upr_list->pending;
157 INIT_LIST_HEAD(&upr->list);
158 list_add_tail(&upr->list, &upr_list->list);
159 upr_list->pending = true;
160 spin_unlock_bh(&upr_list->lock);
161
162 if (!pending)
163 slic_start_upr(sdev, upr);
164}
165
166static struct slic_upr *slic_dequeue_upr(struct slic_device *sdev)
167{
168 struct slic_upr_list *upr_list = &sdev->upr_list;
169 struct slic_upr *next_upr = NULL;
170 struct slic_upr *upr = NULL;
171
172 spin_lock_bh(&upr_list->lock);
173 if (!list_empty(&upr_list->list)) {
174 upr = list_first_entry(&upr_list->list, struct slic_upr, list);
175 list_del(&upr->list);
176
177 if (list_empty(&upr_list->list))
178 upr_list->pending = false;
179 else
180 next_upr = list_first_entry(&upr_list->list,
181 struct slic_upr, list);
182 }
183 spin_unlock_bh(&upr_list->lock);
184 /* trigger processing of the next upr in list */
185 if (next_upr)
186 slic_start_upr(sdev, next_upr);
187
188 return upr;
189}
190
191static int slic_new_upr(struct slic_device *sdev, unsigned int type,
192 dma_addr_t paddr)
193{
194 struct slic_upr *upr;
195
196 upr = kmalloc(sizeof(*upr), GFP_ATOMIC);
197 if (!upr)
198 return -ENOMEM;
199 upr->type = type;
200 upr->paddr = paddr;
201
202 slic_queue_upr(sdev, upr);
203
204 return 0;
205}
206
207static void slic_set_mcast_bit(u64 *mcmask, unsigned char const *addr)
208{
209 u64 mask = *mcmask;
210 u8 crc;
211 /* Get the CRC polynomial for the mac address: we use bits 1-8 (lsb),
212 * bitwise reversed, msb (= lsb bit 0 before bitrev) is automatically
213 * discarded.
214 */
215 crc = ether_crc(ETH_ALEN, addr) >> 23;
216 /* we only have space on the SLIC for 64 entries */
217 crc &= 0x3F;
218 mask |= (u64)1 << crc;
219 *mcmask = mask;
220}
221
222/* must be called with link_lock held */
223static void slic_configure_rcv(struct slic_device *sdev)
224{
225 u32 val;
226
227 val = SLIC_GRCR_RESET | SLIC_GRCR_ADDRAEN | SLIC_GRCR_RCVEN |
228 SLIC_GRCR_HASHSIZE << SLIC_GRCR_HASHSIZE_SHIFT | SLIC_GRCR_RCVBAD;
229
230 if (sdev->duplex == DUPLEX_FULL)
231 val |= SLIC_GRCR_CTLEN;
232
233 if (sdev->promisc)
234 val |= SLIC_GRCR_RCVALL;
235
236 slic_write(sdev, SLIC_REG_WRCFG, val);
237}
238
239/* must be called with link_lock held */
240static void slic_configure_xmt(struct slic_device *sdev)
241{
242 u32 val;
243
244 val = SLIC_GXCR_RESET | SLIC_GXCR_XMTEN;
245
246 if (sdev->duplex == DUPLEX_FULL)
247 val |= SLIC_GXCR_PAUSEEN;
248
249 slic_write(sdev, SLIC_REG_WXCFG, val);
250}
251
252/* must be called with link_lock held */
253static void slic_configure_mac(struct slic_device *sdev)
254{
255 u32 val;
256
257 if (sdev->speed == SPEED_1000) {
258 val = SLIC_GMCR_GAPBB_1000 << SLIC_GMCR_GAPBB_SHIFT |
259 SLIC_GMCR_GAPR1_1000 << SLIC_GMCR_GAPR1_SHIFT |
260 SLIC_GMCR_GAPR2_1000 << SLIC_GMCR_GAPR2_SHIFT |
261 SLIC_GMCR_GBIT; /* enable GMII */
262 } else {
263 val = SLIC_GMCR_GAPBB_100 << SLIC_GMCR_GAPBB_SHIFT |
264 SLIC_GMCR_GAPR1_100 << SLIC_GMCR_GAPR1_SHIFT |
265 SLIC_GMCR_GAPR2_100 << SLIC_GMCR_GAPR2_SHIFT;
266 }
267
268 if (sdev->duplex == DUPLEX_FULL)
269 val |= SLIC_GMCR_FULLD;
270
271 slic_write(sdev, SLIC_REG_WMCFG, val);
272}
273
274static void slic_configure_link_locked(struct slic_device *sdev, int speed,
275 unsigned int duplex)
276{
277 struct net_device *dev = sdev->netdev;
278
279 if (sdev->speed == speed && sdev->duplex == duplex)
280 return;
281
282 sdev->speed = speed;
283 sdev->duplex = duplex;
284
285 if (sdev->speed == SPEED_UNKNOWN) {
286 if (netif_carrier_ok(dev))
287 netif_carrier_off(dev);
288 } else {
289 /* (re)configure link settings */
290 slic_configure_mac(sdev);
291 slic_configure_xmt(sdev);
292 slic_configure_rcv(sdev);
293 slic_flush_write(sdev);
294
295 if (!netif_carrier_ok(dev))
296 netif_carrier_on(dev);
297 }
298}
299
300static void slic_configure_link(struct slic_device *sdev, int speed,
301 unsigned int duplex)
302{
303 spin_lock_bh(&sdev->link_lock);
304 slic_configure_link_locked(sdev, speed, duplex);
305 spin_unlock_bh(&sdev->link_lock);
306}
307
308static void slic_set_rx_mode(struct net_device *dev)
309{
310 struct slic_device *sdev = netdev_priv(dev);
311 struct netdev_hw_addr *hwaddr;
312 bool set_promisc;
313 u64 mcmask;
314
315 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
316 /* Turn on all multicast addresses. We have to do this for
317 * promiscuous mode as well as ALLMCAST mode (it saves the
318 * microcode from having to keep state about the MAC
319 * configuration).
320 */
321 mcmask = ~(u64)0;
322 } else {
323 mcmask = 0;
324
325 netdev_for_each_mc_addr(hwaddr, dev) {
326 slic_set_mcast_bit(&mcmask, hwaddr->addr);
327 }
328 }
329
330 slic_write(sdev, SLIC_REG_MCASTLOW, lower_32_bits(mcmask));
331 slic_write(sdev, SLIC_REG_MCASTHIGH, upper_32_bits(mcmask));
332
333 set_promisc = !!(dev->flags & IFF_PROMISC);
334
335 spin_lock_bh(&sdev->link_lock);
336 if (sdev->promisc != set_promisc) {
337 sdev->promisc = set_promisc;
338 slic_configure_rcv(sdev);
60c140df
LS		 339 }
340 spin_unlock_bh(&sdev->link_lock);
341}
342
343static void slic_xmit_complete(struct slic_device *sdev)
344{
345 struct slic_tx_queue *txq = &sdev->txq;
346 struct net_device *dev = sdev->netdev;
60c140df
LS		 347 struct slic_tx_buffer *buff;
348 unsigned int frames = 0;
349 unsigned int bytes = 0;
687d4f2b 350 unsigned int idx;
60c140df
LS		 351
352 /* Limit processing to SLIC_MAX_TX_COMPLETIONS frames to avoid that new
353 * completions during processing keeps the loop running endlessly.
354 */
355 do {
356 idx = slic_next_compl_idx(sdev);
357 if (idx == SLIC_INVALID_STAT_DESC_IDX)
358 break;
359
360 txq->done_idx = idx;
361 buff = &txq->txbuffs[idx];
362
363 if (unlikely(!buff->skb)) {
364 netdev_warn(dev,
365 "no skb found for desc idx %i\n", idx);
366 continue;
367 }
368 dma_unmap_single(&sdev->pdev->dev,
369 dma_unmap_addr(buff, map_addr),
370 dma_unmap_len(buff, map_len), DMA_TO_DEVICE);
371
372 bytes += buff->skb->len;
373 frames++;
374
375 dev_kfree_skb_any(buff->skb);
376 buff->skb = NULL;
377 } while (frames < SLIC_MAX_TX_COMPLETIONS);
378 /* make sure xmit sees the new value for done_idx */
379 smp_wmb();
380
381 u64_stats_update_begin(&sdev->stats.syncp);
382 sdev->stats.tx_bytes += bytes;
383 sdev->stats.tx_packets += frames;
384 u64_stats_update_end(&sdev->stats.syncp);
385
386 netif_tx_lock(dev);
387 if (netif_queue_stopped(dev) &&
388 (slic_get_free_tx_descs(txq) >= SLIC_MIN_TX_WAKEUP_DESCS))
389 netif_wake_queue(dev);
390 netif_tx_unlock(dev);
391}
392
393static void slic_refill_rx_queue(struct slic_device *sdev, gfp_t gfp)
394{
395 const unsigned int ALIGN_MASK = SLIC_RX_BUFF_ALIGN - 1;
396 unsigned int maplen = SLIC_RX_BUFF_SIZE;
397 struct slic_rx_queue *rxq = &sdev->rxq;
398 struct net_device *dev = sdev->netdev;
399 struct slic_rx_buffer *buff;
400 struct slic_rx_desc *desc;
401 unsigned int misalign;
402 unsigned int offset;
403 struct sk_buff *skb;
404 dma_addr_t paddr;
405
406 while (slic_get_free_rx_descs(rxq) > SLIC_MAX_REQ_RX_DESCS) {
407 skb = alloc_skb(maplen + ALIGN_MASK, gfp);
408 if (!skb)
409 break;
410
411 paddr = dma_map_single(&sdev->pdev->dev, skb->data, maplen,
412 DMA_FROM_DEVICE);
413 if (dma_mapping_error(&sdev->pdev->dev, paddr)) {
414 netdev_err(dev, "mapping rx packet failed\n");
415 /* drop skb */
416 dev_kfree_skb_any(skb);
417 break;
418 }
419 /* ensure head buffer descriptors are 256 byte aligned */
420 offset = 0;
421 misalign = paddr & ALIGN_MASK;
422 if (misalign) {
423 offset = SLIC_RX_BUFF_ALIGN - misalign;
424 skb_reserve(skb, offset);
425 }
426 /* the HW expects dma chunks for descriptor + frame data */
427 desc = (struct slic_rx_desc *)skb->data;
428 /* temporarily sync descriptor for CPU to clear status */
429 dma_sync_single_for_cpu(&sdev->pdev->dev, paddr,
430 offset + sizeof(*desc),
431 DMA_FROM_DEVICE);
432 desc->status = 0;
433 /* return it to HW again */
434 dma_sync_single_for_device(&sdev->pdev->dev, paddr,
435 offset + sizeof(*desc),
436 DMA_FROM_DEVICE);
437
438 buff = &rxq->rxbuffs[rxq->put_idx];
439 buff->skb = skb;
440 dma_unmap_addr_set(buff, map_addr, paddr);
441 dma_unmap_len_set(buff, map_len, maplen);
442 buff->addr_offset = offset;
443 /* complete write to descriptor before it is handed to HW */
444 wmb();
445 /* head buffer descriptors are placed immediately before skb */
446 slic_write(sdev, SLIC_REG_HBAR, lower_32_bits(paddr) + offset);
447 rxq->put_idx = slic_next_queue_idx(rxq->put_idx, rxq->len);
448 }
449}
450
451static void slic_handle_frame_error(struct slic_device *sdev,
452 struct sk_buff *skb)
453{
454 struct slic_stats *stats = &sdev->stats;
455
456 if (sdev->model == SLIC_MODEL_OASIS) {
457 struct slic_rx_info_oasis *info;
458 u32 status_b;
459 u32 status;
460
461 info = (struct slic_rx_info_oasis *)skb->data;
462 status = le32_to_cpu(info->frame_status);
463 status_b = le32_to_cpu(info->frame_status_b);
464 /* transport layer */
465 if (status_b & SLIC_VRHSTATB_TPCSUM)
466 SLIC_INC_STATS_COUNTER(stats, rx_tpcsum);
467 if (status & SLIC_VRHSTAT_TPOFLO)
468 SLIC_INC_STATS_COUNTER(stats, rx_tpoflow);
469 if (status_b & SLIC_VRHSTATB_TPHLEN)
470 SLIC_INC_STATS_COUNTER(stats, rx_tphlen);
471 /* ip layer */
472 if (status_b & SLIC_VRHSTATB_IPCSUM)
473 SLIC_INC_STATS_COUNTER(stats, rx_ipcsum);
474 if (status_b & SLIC_VRHSTATB_IPLERR)
475 SLIC_INC_STATS_COUNTER(stats, rx_iplen);
476 if (status_b & SLIC_VRHSTATB_IPHERR)
477 SLIC_INC_STATS_COUNTER(stats, rx_iphlen);
478 /* link layer */
479 if (status_b & SLIC_VRHSTATB_RCVE)
480 SLIC_INC_STATS_COUNTER(stats, rx_early);
481 if (status_b & SLIC_VRHSTATB_BUFF)
482 SLIC_INC_STATS_COUNTER(stats, rx_buffoflow);
483 if (status_b & SLIC_VRHSTATB_CODE)
484 SLIC_INC_STATS_COUNTER(stats, rx_lcode);
485 if (status_b & SLIC_VRHSTATB_DRBL)
486 SLIC_INC_STATS_COUNTER(stats, rx_drbl);
487 if (status_b & SLIC_VRHSTATB_CRC)
488 SLIC_INC_STATS_COUNTER(stats, rx_crc);
489 if (status & SLIC_VRHSTAT_802OE)
490 SLIC_INC_STATS_COUNTER(stats, rx_oflow802);
491 if (status_b & SLIC_VRHSTATB_802UE)
492 SLIC_INC_STATS_COUNTER(stats, rx_uflow802);
493 if (status_b & SLIC_VRHSTATB_CARRE)
494 SLIC_INC_STATS_COUNTER(stats, tx_carrier);
495 } else { /* mojave */
496 struct slic_rx_info_mojave *info;
497 u32 status;
498
499 info = (struct slic_rx_info_mojave *)skb->data;
500 status = le32_to_cpu(info->frame_status);
501 /* transport layer */
502 if (status & SLIC_VGBSTAT_XPERR) {
503 u32 xerr = status >> SLIC_VGBSTAT_XERRSHFT;
504
505 if (xerr == SLIC_VGBSTAT_XCSERR)
506 SLIC_INC_STATS_COUNTER(stats, rx_tpcsum);
507 if (xerr == SLIC_VGBSTAT_XUFLOW)
508 SLIC_INC_STATS_COUNTER(stats, rx_tpoflow);
509 if (xerr == SLIC_VGBSTAT_XHLEN)
510 SLIC_INC_STATS_COUNTER(stats, rx_tphlen);
511 }
512 /* ip layer */
513 if (status & SLIC_VGBSTAT_NETERR) {
514 u32 nerr = status >> SLIC_VGBSTAT_NERRSHFT &
515 SLIC_VGBSTAT_NERRMSK;
516
517 if (nerr == SLIC_VGBSTAT_NCSERR)
518 SLIC_INC_STATS_COUNTER(stats, rx_ipcsum);
519 if (nerr == SLIC_VGBSTAT_NUFLOW)
520 SLIC_INC_STATS_COUNTER(stats, rx_iplen);
521 if (nerr == SLIC_VGBSTAT_NHLEN)
522 SLIC_INC_STATS_COUNTER(stats, rx_iphlen);
523 }
524 /* link layer */
525 if (status & SLIC_VGBSTAT_LNKERR) {
526 u32 lerr = status & SLIC_VGBSTAT_LERRMSK;
527
528 if (lerr == SLIC_VGBSTAT_LDEARLY)
529 SLIC_INC_STATS_COUNTER(stats, rx_early);
530 if (lerr == SLIC_VGBSTAT_LBOFLO)
531 SLIC_INC_STATS_COUNTER(stats, rx_buffoflow);
532 if (lerr == SLIC_VGBSTAT_LCODERR)
533 SLIC_INC_STATS_COUNTER(stats, rx_lcode);
534 if (lerr == SLIC_VGBSTAT_LDBLNBL)
535 SLIC_INC_STATS_COUNTER(stats, rx_drbl);
536 if (lerr == SLIC_VGBSTAT_LCRCERR)
537 SLIC_INC_STATS_COUNTER(stats, rx_crc);
538 if (lerr == SLIC_VGBSTAT_LOFLO)
539 SLIC_INC_STATS_COUNTER(stats, rx_oflow802);
540 if (lerr == SLIC_VGBSTAT_LUFLO)
541 SLIC_INC_STATS_COUNTER(stats, rx_uflow802);
542 }
543 }
544 SLIC_INC_STATS_COUNTER(stats, rx_errors);
545}
546
547static void slic_handle_receive(struct slic_device *sdev, unsigned int todo,
548 unsigned int *done)
549{
550 struct slic_rx_queue *rxq = &sdev->rxq;
551 struct net_device *dev = sdev->netdev;
552 struct slic_rx_buffer *buff;
553 struct slic_rx_desc *desc;
554 unsigned int frames = 0;
555 unsigned int bytes = 0;
556 struct sk_buff *skb;
557 u32 status;
558 u32 len;
559
560 while (todo && (rxq->done_idx != rxq->put_idx)) {
561 buff = &rxq->rxbuffs[rxq->done_idx];
562
563 skb = buff->skb;
564 if (!skb)
565 break;
566
567 desc = (struct slic_rx_desc *)skb->data;
568
569 dma_sync_single_for_cpu(&sdev->pdev->dev,
570 dma_unmap_addr(buff, map_addr),
571 buff->addr_offset + sizeof(*desc),
572 DMA_FROM_DEVICE);
573
574 status = le32_to_cpu(desc->status);
575 if (!(status & SLIC_IRHDDR_SVALID)) {
576 dma_sync_single_for_device(&sdev->pdev->dev,
577 dma_unmap_addr(buff,
578 map_addr),
579 buff->addr_offset +
580 sizeof(*desc),
581 DMA_FROM_DEVICE);
582 break;
583 }
584
585 buff->skb = NULL;
586
587 dma_unmap_single(&sdev->pdev->dev,
588 dma_unmap_addr(buff, map_addr),
589 dma_unmap_len(buff, map_len),
590 DMA_FROM_DEVICE);
591
592 /* skip rx descriptor that is placed before the frame data */
593 skb_reserve(skb, SLIC_RX_BUFF_HDR_SIZE);
594
595 if (unlikely(status & SLIC_IRHDDR_ERR)) {
596 slic_handle_frame_error(sdev, skb);
597 dev_kfree_skb_any(skb);
598 } else {
599 struct ethhdr *eh = (struct ethhdr *)skb->data;
600
601 if (is_multicast_ether_addr(eh->h_dest))
602 SLIC_INC_STATS_COUNTER(&sdev->stats, rx_mcasts);
603
604 len = le32_to_cpu(desc->length) & SLIC_IRHDDR_FLEN_MSK;
605 skb_put(skb, len);
606 skb->protocol = eth_type_trans(skb, dev);
607 skb->ip_summed = CHECKSUM_UNNECESSARY;
608
609 napi_gro_receive(&sdev->napi, skb);
610
611 bytes += len;
612 frames++;
613 }
614 rxq->done_idx = slic_next_queue_idx(rxq->done_idx, rxq->len);
615 todo--;
616 }
617
618 u64_stats_update_begin(&sdev->stats.syncp);
619 sdev->stats.rx_bytes += bytes;
620 sdev->stats.rx_packets += frames;
621 u64_stats_update_end(&sdev->stats.syncp);
622
623 slic_refill_rx_queue(sdev, GFP_ATOMIC);
624}
625
626static void slic_handle_link_irq(struct slic_device *sdev)
627{
628 struct slic_shmem *sm = &sdev->shmem;
629 struct slic_shmem_data *sm_data = sm->shmem_data;
630 unsigned int duplex;
631 int speed;
632 u32 link;
633
634 link = le32_to_cpu(sm_data->link);
635
636 if (link & SLIC_GIG_LINKUP) {
637 if (link & SLIC_GIG_SPEED_1000)
638 speed = SPEED_1000;
639 else if (link & SLIC_GIG_SPEED_100)
640 speed = SPEED_100;
641 else
642 speed = SPEED_10;
643
644 duplex = (link & SLIC_GIG_FULLDUPLEX) ? DUPLEX_FULL :
645 DUPLEX_HALF;
646 } else {
647 duplex = DUPLEX_UNKNOWN;
648 speed = SPEED_UNKNOWN;
649 }
650 slic_configure_link(sdev, speed, duplex);
651}
652
653static void slic_handle_upr_irq(struct slic_device *sdev, u32 irqs)
654{
655 struct slic_upr *upr;
656
657 /* remove upr that caused this irq (always the first entry in list) */
658 upr = slic_dequeue_upr(sdev);
659 if (!upr) {
660 netdev_warn(sdev->netdev, "no upr found on list\n");
661 return;
662 }
663
664 if (upr->type == SLIC_UPR_LSTAT) {
665 if (unlikely(irqs & SLIC_ISR_UPCERR_MASK)) {
666 /* try again */
667 slic_queue_upr(sdev, upr);
668 return;
669 }
670 slic_handle_link_irq(sdev);
671 }
672 kfree(upr);
673}
674
675static int slic_handle_link_change(struct slic_device *sdev)
676{
677 return slic_new_upr(sdev, SLIC_UPR_LSTAT, sdev->shmem.link_paddr);
678}
679
680static void slic_handle_err_irq(struct slic_device *sdev, u32 isr)
681{
682 struct slic_stats *stats = &sdev->stats;
683
684 if (isr & SLIC_ISR_RMISS)
685 SLIC_INC_STATS_COUNTER(stats, rx_buff_miss);
686 if (isr & SLIC_ISR_XDROP)
687 SLIC_INC_STATS_COUNTER(stats, tx_dropped);
688 if (!(isr & (SLIC_ISR_RMISS | SLIC_ISR_XDROP)))
689 SLIC_INC_STATS_COUNTER(stats, irq_errs);
690}
691
692static void slic_handle_irq(struct slic_device *sdev, u32 isr,
693 unsigned int todo, unsigned int *done)
694{
695 if (isr & SLIC_ISR_ERR)
696 slic_handle_err_irq(sdev, isr);
697
698 if (isr & SLIC_ISR_LEVENT)
699 slic_handle_link_change(sdev);
700
701 if (isr & SLIC_ISR_UPC_MASK)
702 slic_handle_upr_irq(sdev, isr);
703
704 if (isr & SLIC_ISR_RCV)
705 slic_handle_receive(sdev, todo, done);
706
707 if (isr & SLIC_ISR_CMD)
708 slic_xmit_complete(sdev);
709}
710
711static int slic_poll(struct napi_struct *napi, int todo)
712{
713 struct slic_device *sdev = container_of(napi, struct slic_device, napi);
714 struct slic_shmem *sm = &sdev->shmem;
715 struct slic_shmem_data *sm_data = sm->shmem_data;
716 u32 isr = le32_to_cpu(sm_data->isr);
717 int done = 0;
718
719 slic_handle_irq(sdev, isr, todo, &done);
720
721 if (done < todo) {
722 napi_complete_done(napi, done);
723 /* reenable irqs */
724 sm_data->isr = 0;
725 /* make sure sm_data->isr is cleard before irqs are reenabled */
726 wmb();
727 slic_write(sdev, SLIC_REG_ISR, 0);
728 slic_flush_write(sdev);
729 }
730
731 return done;
732}
733
734static irqreturn_t slic_irq(int irq, void *dev_id)
735{
736 struct slic_device *sdev = dev_id;
737 struct slic_shmem *sm = &sdev->shmem;
738 struct slic_shmem_data *sm_data = sm->shmem_data;
739
740 slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_MASK);
741 slic_flush_write(sdev);
742 /* make sure sm_data->isr is read after ICR_INT_MASK is set */
743 wmb();
744
745 if (!sm_data->isr) {
746 dma_rmb();
747 /* spurious interrupt */
748 slic_write(sdev, SLIC_REG_ISR, 0);
749 slic_flush_write(sdev);
750 return IRQ_NONE;
751 }
752
753 napi_schedule_irqoff(&sdev->napi);
754
755 return IRQ_HANDLED;
756}
757
758static void slic_card_reset(struct slic_device *sdev)
759{
760 u16 cmd;
761
762 slic_write(sdev, SLIC_REG_RESET, SLIC_RESET_MAGIC);
763 /* flush write by means of config space */
764 pci_read_config_word(sdev->pdev, PCI_COMMAND, &cmd);
765 mdelay(1);
766}
767
768static int slic_init_stat_queue(struct slic_device *sdev)
769{
770 const unsigned int DESC_ALIGN_MASK = SLIC_STATS_DESC_ALIGN - 1;
771 struct slic_stat_queue *stq = &sdev->stq;
772 struct slic_stat_desc *descs;
773 unsigned int misalign;
774 unsigned int offset;
775 dma_addr_t paddr;
776 size_t size;
777 int err;
778 int i;
779
780 stq->len = SLIC_NUM_STAT_DESCS;
781 stq->active_array = 0;
782 stq->done_idx = 0;
783
784 size = stq->len * sizeof(*descs) + DESC_ALIGN_MASK;
785
786 for (i = 0; i < SLIC_NUM_STAT_DESC_ARRAYS; i++) {
750afb08
LC		 787 descs = dma_alloc_coherent(&sdev->pdev->dev, size, &paddr,
788 GFP_KERNEL);
60c140df
LS		 789 if (!descs) {
790 netdev_err(sdev->netdev,
791 "failed to allocate status descriptors\n");
792 err = -ENOMEM;
793 goto free_descs;
794 }
795 /* ensure correct alignment */
796 offset = 0;
797 misalign = paddr & DESC_ALIGN_MASK;
798 if (misalign) {
799 offset = SLIC_STATS_DESC_ALIGN - misalign;
800 descs += offset;
801 paddr += offset;
802 }
803
804 slic_write(sdev, SLIC_REG_RBAR, lower_32_bits(paddr) |
805 stq->len);
806 stq->descs[i] = descs;
807 stq->paddr[i] = paddr;
808 stq->addr_offset[i] = offset;
809 }
810
811 stq->mem_size = size;
812
813 return 0;
814
815free_descs:
816 while (i--) {
817 dma_free_coherent(&sdev->pdev->dev, stq->mem_size,
818 stq->descs[i] - stq->addr_offset[i],
819 stq->paddr[i] - stq->addr_offset[i]);
820 }
821
822 return err;
823}
824
825static void slic_free_stat_queue(struct slic_device *sdev)
826{
827 struct slic_stat_queue *stq = &sdev->stq;
828 int i;
829
830 for (i = 0; i < SLIC_NUM_STAT_DESC_ARRAYS; i++) {
831 dma_free_coherent(&sdev->pdev->dev, stq->mem_size,
832 stq->descs[i] - stq->addr_offset[i],
833 stq->paddr[i] - stq->addr_offset[i]);
834 }
835}
836
837static int slic_init_tx_queue(struct slic_device *sdev)
838{
839 struct slic_tx_queue *txq = &sdev->txq;
840 struct slic_tx_buffer *buff;
841 struct slic_tx_desc *desc;
842 unsigned int i;
843 int err;
844
845 txq->len = SLIC_NUM_TX_DESCS;
846 txq->put_idx = 0;
847 txq->done_idx = 0;
848
849 txq->txbuffs = kcalloc(txq->len, sizeof(*buff), GFP_KERNEL);
850 if (!txq->txbuffs)
851 return -ENOMEM;
852
853 txq->dma_pool = dma_pool_create("slic_pool", &sdev->pdev->dev,
854 sizeof(*desc), SLIC_TX_DESC_ALIGN,
855 4096);
856 if (!txq->dma_pool) {
857 err = -ENOMEM;
858 netdev_err(sdev->netdev, "failed to create dma pool\n");
859 goto free_buffs;
860 }
861
862 for (i = 0; i < txq->len; i++) {
863 buff = &txq->txbuffs[i];
864 desc = dma_pool_zalloc(txq->dma_pool, GFP_KERNEL,
865 &buff->desc_paddr);
866 if (!desc) {
867 netdev_err(sdev->netdev,
868 "failed to alloc pool chunk (%i)\n", i);
869 err = -ENOMEM;
870 goto free_descs;
871 }
872
873 desc->hnd = cpu_to_le32((u32)(i + 1));
874 desc->cmd = SLIC_CMD_XMT_REQ;
875 desc->flags = 0;
876 desc->type = cpu_to_le32(SLIC_CMD_TYPE_DUMB);
877 buff->desc = desc;
878 }
879
880 return 0;
881
882free_descs:
883 while (i--) {
884 buff = &txq->txbuffs[i];
885 dma_pool_free(txq->dma_pool, buff->desc, buff->desc_paddr);
886 }
887 dma_pool_destroy(txq->dma_pool);
888
889free_buffs:
890 kfree(txq->txbuffs);
891
892 return err;
893}
894
895static void slic_free_tx_queue(struct slic_device *sdev)
896{
897 struct slic_tx_queue *txq = &sdev->txq;
898 struct slic_tx_buffer *buff;
899 unsigned int i;
900
901 for (i = 0; i < txq->len; i++) {
902 buff = &txq->txbuffs[i];
903 dma_pool_free(txq->dma_pool, buff->desc, buff->desc_paddr);
904 if (!buff->skb)
905 continue;
906
907 dma_unmap_single(&sdev->pdev->dev,
908 dma_unmap_addr(buff, map_addr),
909 dma_unmap_len(buff, map_len), DMA_TO_DEVICE);
910 consume_skb(buff->skb);
911 }
912 dma_pool_destroy(txq->dma_pool);
913
914 kfree(txq->txbuffs);
915}
916
917static int slic_init_rx_queue(struct slic_device *sdev)
918{
919 struct slic_rx_queue *rxq = &sdev->rxq;
920 struct slic_rx_buffer *buff;
921
922 rxq->len = SLIC_NUM_RX_LES;
923 rxq->done_idx = 0;
924 rxq->put_idx = 0;
925
926 buff = kcalloc(rxq->len, sizeof(*buff), GFP_KERNEL);
927 if (!buff)
928 return -ENOMEM;
929
930 rxq->rxbuffs = buff;
931 slic_refill_rx_queue(sdev, GFP_KERNEL);
932
933 return 0;
934}
935
936static void slic_free_rx_queue(struct slic_device *sdev)
937{
938 struct slic_rx_queue *rxq = &sdev->rxq;
939 struct slic_rx_buffer *buff;
940 unsigned int i;
941
942 /* free rx buffers */
943 for (i = 0; i < rxq->len; i++) {
944 buff = &rxq->rxbuffs[i];
945
946 if (!buff->skb)
947 continue;
948
949 dma_unmap_single(&sdev->pdev->dev,
950 dma_unmap_addr(buff, map_addr),
951 dma_unmap_len(buff, map_len),
952 DMA_FROM_DEVICE);
953 consume_skb(buff->skb);
954 }
955 kfree(rxq->rxbuffs);
956}
957
958static void slic_set_link_autoneg(struct slic_device *sdev)
959{
960 unsigned int subid = sdev->pdev->subsystem_device;
961 u32 val;
962
963 if (sdev->is_fiber) {
964 /* We've got a fiber gigabit interface, and register 4 is
965 * different in fiber mode than in copper mode.
966 */
967 /* advertise FD only @1000 Mb */
968 val = MII_ADVERTISE << 16 | ADVERTISE_1000XFULL |
969 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
970 /* enable PAUSE frames */
971 slic_write(sdev, SLIC_REG_WPHY, val);
972 /* reset phy, enable auto-neg */
973 val = MII_BMCR << 16 | BMCR_RESET | BMCR_ANENABLE |
974 BMCR_ANRESTART;
975 slic_write(sdev, SLIC_REG_WPHY, val);
976 } else { /* copper gigabit */
977 /* We've got a copper gigabit interface, and register 4 is
978 * different in copper mode than in fiber mode.
979 */
980 /* advertise 10/100 Mb modes */
981 val = MII_ADVERTISE << 16 | ADVERTISE_100FULL |
982 ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF;
983 /* enable PAUSE frames */
984 val |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
985 /* required by the Cicada PHY */
986 val |= ADVERTISE_CSMA;
987 slic_write(sdev, SLIC_REG_WPHY, val);
988
989 /* advertise FD only @1000 Mb */
990 val = MII_CTRL1000 << 16 | ADVERTISE_1000FULL;
991 slic_write(sdev, SLIC_REG_WPHY, val);
992
993 if (subid != PCI_SUBDEVICE_ID_ALACRITECH_CICADA) {
994 /* if a Marvell PHY enable auto crossover */
995 val = SLIC_MIICR_REG_16 | SLIC_MRV_REG16_XOVERON;
996 slic_write(sdev, SLIC_REG_WPHY, val);
997
998 /* reset phy, enable auto-neg */
999 val = MII_BMCR << 16 | BMCR_RESET | BMCR_ANENABLE |
1000 BMCR_ANRESTART;
1001 slic_write(sdev, SLIC_REG_WPHY, val);
1002 } else {
1003 /* enable and restart auto-neg (don't reset) */
1004 val = MII_BMCR << 16 | BMCR_ANENABLE | BMCR_ANRESTART;
1005 slic_write(sdev, SLIC_REG_WPHY, val);
1006 }
1007 }
1008}
1009
1010static void slic_set_mac_address(struct slic_device *sdev)
1011{
1012 u8 *addr = sdev->netdev->dev_addr;
1013 u32 val;
1014
1015 val = addr[5] | addr[4] << 8 | addr[3] << 16 | addr[2] << 24;
1016
1017 slic_write(sdev, SLIC_REG_WRADDRAL, val);
1018 slic_write(sdev, SLIC_REG_WRADDRBL, val);
1019
1020 val = addr[0] << 8 | addr[1];
1021
1022 slic_write(sdev, SLIC_REG_WRADDRAH, val);
1023 slic_write(sdev, SLIC_REG_WRADDRBH, val);
1024 slic_flush_write(sdev);
1025}
1026
1027static u32 slic_read_dword_from_firmware(const struct firmware *fw, int *offset)
1028{
1029 int idx = *offset;
1030 __le32 val;
1031
1032 memcpy(&val, fw->data + *offset, sizeof(val));
1033 idx += 4;
1034 *offset = idx;
1035
1036 return le32_to_cpu(val);
1037}
1038
1039MODULE_FIRMWARE(SLIC_RCV_FIRMWARE_MOJAVE);
1040MODULE_FIRMWARE(SLIC_RCV_FIRMWARE_OASIS);
1041
1042static int slic_load_rcvseq_firmware(struct slic_device *sdev)
1043{
1044 const struct firmware *fw;
1045 const char *file;
1046 u32 codelen;
1047 int idx = 0;
1048 u32 instr;
1049 u32 addr;
1050 int err;
1051
1052 file = (sdev->model == SLIC_MODEL_OASIS) ? SLIC_RCV_FIRMWARE_OASIS :
1053 SLIC_RCV_FIRMWARE_MOJAVE;
1054 err = request_firmware(&fw, file, &sdev->pdev->dev);
1055 if (err) {
1056 dev_err(&sdev->pdev->dev,
1057 "failed to load receive sequencer firmware %s\n", file);
1058 return err;
1059 }
1060 /* Do an initial sanity check concerning firmware size now. A further
1061 * check follows below.
1062 */
1063 if (fw->size < SLIC_FIRMWARE_MIN_SIZE) {
1064 dev_err(&sdev->pdev->dev,
1065 "invalid firmware size %zu (min %u expected)\n",
1066 fw->size, SLIC_FIRMWARE_MIN_SIZE);
1067 err = -EINVAL;
1068 goto release;
1069 }
1070
1071 codelen = slic_read_dword_from_firmware(fw, &idx);
1072
1073 /* do another sanity check against firmware size */
1074 if ((codelen + 4) > fw->size) {
1075 dev_err(&sdev->pdev->dev,
1076 "invalid rcv-sequencer firmware size %zu\n", fw->size);
1077 err = -EINVAL;
1078 goto release;
1079 }
1080
1081 /* download sequencer code to card */
1082 slic_write(sdev, SLIC_REG_RCV_WCS, SLIC_RCVWCS_BEGIN);
1083 for (addr = 0; addr < codelen; addr++) {
1084 __le32 val;
1085 /* write out instruction address */
1086 slic_write(sdev, SLIC_REG_RCV_WCS, addr);
1087
1088 instr = slic_read_dword_from_firmware(fw, &idx);
1089 /* write out the instruction data low addr */
1090 slic_write(sdev, SLIC_REG_RCV_WCS, instr);
1091
1092 val = (__le32)fw->data[idx];
1093 instr = le32_to_cpu(val);
1094 idx++;
1095 /* write out the instruction data high addr */
1096 slic_write(sdev, SLIC_REG_RCV_WCS, instr);
1097 }
1098 /* finish download */
1099 slic_write(sdev, SLIC_REG_RCV_WCS, SLIC_RCVWCS_FINISH);
1100 slic_flush_write(sdev);
1101release:
1102 release_firmware(fw);
1103
1104 return err;
1105}
1106
1107MODULE_FIRMWARE(SLIC_FIRMWARE_MOJAVE);
1108MODULE_FIRMWARE(SLIC_FIRMWARE_OASIS);
1109
1110static int slic_load_firmware(struct slic_device *sdev)
1111{
1112 u32 sectstart[SLIC_FIRMWARE_MAX_SECTIONS];
1113 u32 sectsize[SLIC_FIRMWARE_MAX_SECTIONS];
1114 const struct firmware *fw;
1115 unsigned int datalen;
1116 const char *file;
1117 int code_start;
1118 unsigned int i;
1119 u32 numsects;
1120 int idx = 0;
1121 u32 sect;
1122 u32 instr;
1123 u32 addr;
1124 u32 base;
1125 int err;
1126
1127 file = (sdev->model == SLIC_MODEL_OASIS) ? SLIC_FIRMWARE_OASIS :
1128 SLIC_FIRMWARE_MOJAVE;
1129 err = request_firmware(&fw, file, &sdev->pdev->dev);
1130 if (err) {
1131 dev_err(&sdev->pdev->dev, "failed to load firmware %s\n", file);
1132 return err;
1133 }
1134 /* Do an initial sanity check concerning firmware size now. A further
1135 * check follows below.
1136 */
1137 if (fw->size < SLIC_FIRMWARE_MIN_SIZE) {
1138 dev_err(&sdev->pdev->dev,
1139 "invalid firmware size %zu (min is %u)\n", fw->size,
1140 SLIC_FIRMWARE_MIN_SIZE);
1141 err = -EINVAL;
1142 goto release;
1143 }
1144
1145 numsects = slic_read_dword_from_firmware(fw, &idx);
1146 if (numsects == 0 || numsects > SLIC_FIRMWARE_MAX_SECTIONS) {
1147 dev_err(&sdev->pdev->dev,
1148 "invalid number of sections in firmware: %u", numsects);
1149 err = -EINVAL;
1150 goto release;
1151 }
1152
1153 datalen = numsects * 8 + 4;
1154 for (i = 0; i < numsects; i++) {
1155 sectsize[i] = slic_read_dword_from_firmware(fw, &idx);
1156 datalen += sectsize[i];
1157 }
1158
1159 /* do another sanity check against firmware size */
1160 if (datalen > fw->size) {
1161 dev_err(&sdev->pdev->dev,
1162 "invalid firmware size %zu (expected >= %u)\n",
1163 fw->size, datalen);
1164 err = -EINVAL;
1165 goto release;
1166 }
1167 /* get sections */
1168 for (i = 0; i < numsects; i++)
1169 sectstart[i] = slic_read_dword_from_firmware(fw, &idx);
1170
1171 code_start = idx;
1172 instr = slic_read_dword_from_firmware(fw, &idx);
1173
1174 for (sect = 0; sect < numsects; sect++) {
1175 unsigned int ssize = sectsize[sect] >> 3;
1176
1177 base = sectstart[sect];
1178
1179 for (addr = 0; addr < ssize; addr++) {
1180 /* write out instruction address */
1181 slic_write(sdev, SLIC_REG_WCS, base + addr);
1182 /* write out instruction to low addr */
1183 slic_write(sdev, SLIC_REG_WCS, instr);
1184 instr = slic_read_dword_from_firmware(fw, &idx);
1185 /* write out instruction to high addr */
1186 slic_write(sdev, SLIC_REG_WCS, instr);
1187 instr = slic_read_dword_from_firmware(fw, &idx);
1188 }
1189 }
1190
1191 idx = code_start;
1192
1193 for (sect = 0; sect < numsects; sect++) {
1194 unsigned int ssize = sectsize[sect] >> 3;
1195
1196 instr = slic_read_dword_from_firmware(fw, &idx);
1197 base = sectstart[sect];
1198 if (base < 0x8000)
1199 continue;
1200
1201 for (addr = 0; addr < ssize; addr++) {
1202 /* write out instruction address */
1203 slic_write(sdev, SLIC_REG_WCS,
1204 SLIC_WCS_COMPARE | (base + addr));
1205 /* write out instruction to low addr */
1206 slic_write(sdev, SLIC_REG_WCS, instr);
1207 instr = slic_read_dword_from_firmware(fw, &idx);
1208 /* write out instruction to high addr */
1209 slic_write(sdev, SLIC_REG_WCS, instr);
1210 instr = slic_read_dword_from_firmware(fw, &idx);
1211 }
1212 }
1213 slic_flush_write(sdev);
1214 mdelay(10);
1215 /* everything OK, kick off the card */
1216 slic_write(sdev, SLIC_REG_WCS, SLIC_WCS_START);
1217 slic_flush_write(sdev);
1218 /* wait long enough for ucode to init card and reach the mainloop */
1219 mdelay(20);
1220release:
1221 release_firmware(fw);
1222
1223 return err;
1224}
1225
1226static int slic_init_shmem(struct slic_device *sdev)
1227{
1228 struct slic_shmem *sm = &sdev->shmem;
1229 struct slic_shmem_data *sm_data;
1230 dma_addr_t paddr;
1231
750afb08
LC		 1232 sm_data = dma_alloc_coherent(&sdev->pdev->dev, sizeof(*sm_data),
1233 &paddr, GFP_KERNEL);
60c140df
LS		 1234 if (!sm_data) {
1235 dev_err(&sdev->pdev->dev, "failed to allocate shared memory\n");
1236 return -ENOMEM;
1237 }
1238
1239 sm->shmem_data = sm_data;
1240 sm->isr_paddr = paddr;
1241 sm->link_paddr = paddr + offsetof(struct slic_shmem_data, link);
1242
1243 return 0;
1244}
1245
1246static void slic_free_shmem(struct slic_device *sdev)
1247{
1248 struct slic_shmem *sm = &sdev->shmem;
1249 struct slic_shmem_data *sm_data = sm->shmem_data;
1250
1251 dma_free_coherent(&sdev->pdev->dev, sizeof(*sm_data), sm_data,
1252 sm->isr_paddr);
1253}
1254
1255static int slic_init_iface(struct slic_device *sdev)
1256{
1257 struct slic_shmem *sm = &sdev->shmem;
1258 int err;
1259
1260 sdev->upr_list.pending = false;
1261
1262 err = slic_init_shmem(sdev);
1263 if (err) {
1264 netdev_err(sdev->netdev, "failed to init shared memory\n");
1265 return err;
1266 }
1267
1268 err = slic_load_firmware(sdev);
1269 if (err) {
1270 netdev_err(sdev->netdev, "failed to load firmware\n");
1271 goto free_sm;
1272 }
1273
1274 err = slic_load_rcvseq_firmware(sdev);
1275 if (err) {
1276 netdev_err(sdev->netdev,
1277 "failed to load firmware for receive sequencer\n");
1278 goto free_sm;
1279 }
1280
1281 slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF);
1282 slic_flush_write(sdev);
1283 mdelay(1);
1284
1285 err = slic_init_rx_queue(sdev);
1286 if (err) {
1287 netdev_err(sdev->netdev, "failed to init rx queue: %u\n", err);
1288 goto free_sm;
1289 }
1290
1291 err = slic_init_tx_queue(sdev);
1292 if (err) {
1293 netdev_err(sdev->netdev, "failed to init tx queue: %u\n", err);
1294 goto free_rxq;
1295 }
1296
1297 err = slic_init_stat_queue(sdev);
1298 if (err) {
1299 netdev_err(sdev->netdev, "failed to init status queue: %u\n",
1300 err);
1301 goto free_txq;
1302 }
1303
1304 slic_write(sdev, SLIC_REG_ISP, lower_32_bits(sm->isr_paddr));
1305 napi_enable(&sdev->napi);
1306 /* disable irq mitigation */
1307 slic_write(sdev, SLIC_REG_INTAGG, 0);
1308 slic_write(sdev, SLIC_REG_ISR, 0);
1309 slic_flush_write(sdev);
1310
1311 slic_set_mac_address(sdev);
1312
1313 spin_lock_bh(&sdev->link_lock);
1314 sdev->duplex = DUPLEX_UNKNOWN;
1315 sdev->speed = SPEED_UNKNOWN;
1316 spin_unlock_bh(&sdev->link_lock);
1317
1318 slic_set_link_autoneg(sdev);
1319
1320 err = request_irq(sdev->pdev->irq, slic_irq, IRQF_SHARED, DRV_NAME,
1321 sdev);
1322 if (err) {
1323 netdev_err(sdev->netdev, "failed to request irq: %u\n", err);
1324 goto disable_napi;
1325 }
1326
1327 slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_ON);
1328 slic_flush_write(sdev);
1329 /* request initial link status */
1330 err = slic_handle_link_change(sdev);
1331 if (err)
1332 netdev_warn(sdev->netdev,
1333 "failed to set initial link state: %u\n", err);
1334 return 0;
1335
1336disable_napi:
1337 napi_disable(&sdev->napi);
1338 slic_free_stat_queue(sdev);
1339free_txq:
1340 slic_free_tx_queue(sdev);
1341free_rxq:
1342 slic_free_rx_queue(sdev);
1343free_sm:
1344 slic_free_shmem(sdev);
1345 slic_card_reset(sdev);
1346
1347 return err;
1348}
1349
1350static int slic_open(struct net_device *dev)
1351{
1352 struct slic_device *sdev = netdev_priv(dev);
1353 int err;
1354
1355 netif_carrier_off(dev);
1356
1357 err = slic_init_iface(sdev);
1358 if (err) {
1359 netdev_err(dev, "failed to initialize interface: %i\n", err);
1360 return err;
1361 }
1362
1363 netif_start_queue(dev);
1364
1365 return 0;
1366}
1367
1368static int slic_close(struct net_device *dev)
1369{
1370 struct slic_device *sdev = netdev_priv(dev);
1371 u32 val;
1372
1373 netif_stop_queue(dev);
1374
1375 /* stop irq handling */
1376 napi_disable(&sdev->napi);
1377 slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF);
1378 slic_write(sdev, SLIC_REG_ISR, 0);
1379 slic_flush_write(sdev);
1380
1381 free_irq(sdev->pdev->irq, sdev);
1382 /* turn off RCV and XMT and power down PHY */
1383 val = SLIC_GXCR_RESET | SLIC_GXCR_PAUSEEN;
1384 slic_write(sdev, SLIC_REG_WXCFG, val);
1385
1386 val = SLIC_GRCR_RESET | SLIC_GRCR_CTLEN | SLIC_GRCR_ADDRAEN |
1387 SLIC_GRCR_HASHSIZE << SLIC_GRCR_HASHSIZE_SHIFT;
1388 slic_write(sdev, SLIC_REG_WRCFG, val);
1389
1390 val = MII_BMCR << 16 | BMCR_PDOWN;
1391 slic_write(sdev, SLIC_REG_WPHY, val);
1392 slic_flush_write(sdev);
1393
1394 slic_clear_upr_list(&sdev->upr_list);
1395 slic_write(sdev, SLIC_REG_QUIESCE, 0);
1396
1397 slic_free_stat_queue(sdev);
1398 slic_free_tx_queue(sdev);
1399 slic_free_rx_queue(sdev);
1400 slic_free_shmem(sdev);
1401
1402 slic_card_reset(sdev);
1403 netif_carrier_off(dev);
1404
1405 return 0;
1406}
1407
1408static netdev_tx_t slic_xmit(struct sk_buff *skb, struct net_device *dev)
1409{
1410 struct slic_device *sdev = netdev_priv(dev);
1411 struct slic_tx_queue *txq = &sdev->txq;
1412 struct slic_tx_buffer *buff;
1413 struct slic_tx_desc *desc;
1414 dma_addr_t paddr;
1415 u32 cbar_val;
1416 u32 maplen;
1417
1418 if (unlikely(slic_get_free_tx_descs(txq) < SLIC_MAX_REQ_TX_DESCS)) {
1419 netdev_err(dev, "BUG! not enough tx LEs left: %u\n",
1420 slic_get_free_tx_descs(txq));
1421 return NETDEV_TX_BUSY;
1422 }
1423
1424 maplen = skb_headlen(skb);
1425 paddr = dma_map_single(&sdev->pdev->dev, skb->data, maplen,
1426 DMA_TO_DEVICE);
1427 if (dma_mapping_error(&sdev->pdev->dev, paddr)) {
1428 netdev_err(dev, "failed to map tx buffer\n");
1429 goto drop_skb;
1430 }
1431
1432 buff = &txq->txbuffs[txq->put_idx];
1433 buff->skb = skb;
1434 dma_unmap_addr_set(buff, map_addr, paddr);
1435 dma_unmap_len_set(buff, map_len, maplen);
1436
1437 desc = buff->desc;
1438 desc->totlen = cpu_to_le32(maplen);
1439 desc->paddrl = cpu_to_le32(lower_32_bits(paddr));
1440 desc->paddrh = cpu_to_le32(upper_32_bits(paddr));
1441 desc->len = cpu_to_le32(maplen);
1442
1443 txq->put_idx = slic_next_queue_idx(txq->put_idx, txq->len);
1444
1445 cbar_val = lower_32_bits(buff->desc_paddr) | 1;
1446 /* complete writes to RAM and DMA before hardware is informed */
1447 wmb();
1448
1449 slic_write(sdev, SLIC_REG_CBAR, cbar_val);
1450
1451 if (slic_get_free_tx_descs(txq) < SLIC_MAX_REQ_TX_DESCS)
1452 netif_stop_queue(dev);
60c140df
LS		 1453
1454 return NETDEV_TX_OK;
1455drop_skb:
1456 dev_kfree_skb_any(skb);
1457
1458 return NETDEV_TX_OK;
1459}
1460
bc1f4470 1461static void slic_get_stats(struct net_device *dev,
1462 struct rtnl_link_stats64 *lst)
60c140df
LS		 1463{
1464 struct slic_device *sdev = netdev_priv(dev);
1465 struct slic_stats *stats = &sdev->stats;
1466
1467 SLIC_GET_STATS_COUNTER(lst->rx_packets, stats, rx_packets);
1468 SLIC_GET_STATS_COUNTER(lst->tx_packets, stats, tx_packets);
1469 SLIC_GET_STATS_COUNTER(lst->rx_bytes, stats, rx_bytes);
1470 SLIC_GET_STATS_COUNTER(lst->tx_bytes, stats, tx_bytes);
1471 SLIC_GET_STATS_COUNTER(lst->rx_errors, stats, rx_errors);
1472 SLIC_GET_STATS_COUNTER(lst->rx_dropped, stats, rx_buff_miss);
1473 SLIC_GET_STATS_COUNTER(lst->tx_dropped, stats, tx_dropped);
1474 SLIC_GET_STATS_COUNTER(lst->multicast, stats, rx_mcasts);
1475 SLIC_GET_STATS_COUNTER(lst->rx_over_errors, stats, rx_buffoflow);
1476 SLIC_GET_STATS_COUNTER(lst->rx_crc_errors, stats, rx_crc);
1477 SLIC_GET_STATS_COUNTER(lst->rx_fifo_errors, stats, rx_oflow802);
1478 SLIC_GET_STATS_COUNTER(lst->tx_carrier_errors, stats, tx_carrier);
60c140df
LS		 1479}
1480
1481static int slic_get_sset_count(struct net_device *dev, int sset)
1482{
1483 switch (sset) {
1484 case ETH_SS_STATS:
1485 return ARRAY_SIZE(slic_stats_strings);
1486 default:
1487 return -EOPNOTSUPP;
1488 }
1489}
1490
1491static void slic_get_ethtool_stats(struct net_device *dev,
1492 struct ethtool_stats *eth_stats, u64 *data)
1493{
1494 struct slic_device *sdev = netdev_priv(dev);
1495 struct slic_stats *stats = &sdev->stats;
1496
1497 SLIC_GET_STATS_COUNTER(data[0], stats, rx_packets);
1498 SLIC_GET_STATS_COUNTER(data[1], stats, rx_bytes);
1499 SLIC_GET_STATS_COUNTER(data[2], stats, rx_mcasts);
1500 SLIC_GET_STATS_COUNTER(data[3], stats, rx_errors);
1501 SLIC_GET_STATS_COUNTER(data[4], stats, rx_buff_miss);
1502 SLIC_GET_STATS_COUNTER(data[5], stats, rx_tpcsum);
1503 SLIC_GET_STATS_COUNTER(data[6], stats, rx_tpoflow);
1504 SLIC_GET_STATS_COUNTER(data[7], stats, rx_tphlen);
1505 SLIC_GET_STATS_COUNTER(data[8], stats, rx_ipcsum);
1506 SLIC_GET_STATS_COUNTER(data[9], stats, rx_iplen);
1507 SLIC_GET_STATS_COUNTER(data[10], stats, rx_iphlen);
1508 SLIC_GET_STATS_COUNTER(data[11], stats, rx_early);
1509 SLIC_GET_STATS_COUNTER(data[12], stats, rx_buffoflow);
1510 SLIC_GET_STATS_COUNTER(data[13], stats, rx_lcode);
1511 SLIC_GET_STATS_COUNTER(data[14], stats, rx_drbl);
1512 SLIC_GET_STATS_COUNTER(data[15], stats, rx_crc);
1513 SLIC_GET_STATS_COUNTER(data[16], stats, rx_oflow802);
1514 SLIC_GET_STATS_COUNTER(data[17], stats, rx_uflow802);
1515 SLIC_GET_STATS_COUNTER(data[18], stats, tx_packets);
1516 SLIC_GET_STATS_COUNTER(data[19], stats, tx_bytes);
1517 SLIC_GET_STATS_COUNTER(data[20], stats, tx_carrier);
1518 SLIC_GET_STATS_COUNTER(data[21], stats, tx_dropped);
1519 SLIC_GET_STATS_COUNTER(data[22], stats, irq_errs);
1520}
1521
1522static void slic_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1523{
1524 if (stringset == ETH_SS_STATS) {
1525 memcpy(data, slic_stats_strings, sizeof(slic_stats_strings));
1526 data += sizeof(slic_stats_strings);
1527 }
1528}
1529
1530static void slic_get_drvinfo(struct net_device *dev,
1531 struct ethtool_drvinfo *info)
1532{
1533 struct slic_device *sdev = netdev_priv(dev);
1534
1535 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1536 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1537 strlcpy(info->bus_info, pci_name(sdev->pdev), sizeof(info->bus_info));
1538}
1539
1540static const struct ethtool_ops slic_ethtool_ops = {
1541 .get_drvinfo = slic_get_drvinfo,
1542 .get_link = ethtool_op_get_link,
1543 .get_strings = slic_get_strings,
1544 .get_ethtool_stats = slic_get_ethtool_stats,
1545 .get_sset_count = slic_get_sset_count,
1546};
1547
1548static const struct net_device_ops slic_netdev_ops = {
1549 .ndo_open = slic_open,
1550 .ndo_stop = slic_close,
1551 .ndo_start_xmit = slic_xmit,
1552 .ndo_set_mac_address = eth_mac_addr,
1553 .ndo_get_stats64 = slic_get_stats,
1554 .ndo_set_rx_mode = slic_set_rx_mode,
60c140df
LS		 1555 .ndo_validate_addr = eth_validate_addr,
1556};
1557
1558static u16 slic_eeprom_csum(unsigned char *eeprom, unsigned int len)
1559{
1560 unsigned char *ptr = eeprom;
1561 u32 csum = 0;
1562 __le16 data;
1563
1564 while (len > 1) {
1565 memcpy(&data, ptr, sizeof(data));
1566 csum += le16_to_cpu(data);
1567 ptr += 2;
1568 len -= 2;
1569 }
1570 if (len > 0)
1571 csum += *(u8 *)ptr;
1572 while (csum >> 16)
1573 csum = (csum & 0xFFFF) + ((csum >> 16) & 0xFFFF);
1574 return ~csum;
1575}
1576
1577/* check eeprom size, magic and checksum */
1578static bool slic_eeprom_valid(unsigned char *eeprom, unsigned int size)
1579{
1580 const unsigned int MAX_SIZE = 128;
1581 const unsigned int MIN_SIZE = 98;
1582 __le16 magic;
1583 __le16 csum;
1584
1585 if (size < MIN_SIZE || size > MAX_SIZE)
1586 return false;
1587 memcpy(&magic, eeprom, sizeof(magic));
1588 if (le16_to_cpu(magic) != SLIC_EEPROM_MAGIC)
1589 return false;
1590 /* cut checksum bytes */
1591 size -= 2;
1592 memcpy(&csum, eeprom + size, sizeof(csum));
1593
1594 return (le16_to_cpu(csum) == slic_eeprom_csum(eeprom, size));
1595}
1596
1597static int slic_read_eeprom(struct slic_device *sdev)
1598{
1599 unsigned int devfn = PCI_FUNC(sdev->pdev->devfn);
1600 struct slic_shmem *sm = &sdev->shmem;
1601 struct slic_shmem_data *sm_data = sm->shmem_data;
1602 const unsigned int MAX_LOOPS = 5000;
1603 unsigned int codesize;
1604 unsigned char *eeprom;
1605 struct slic_upr *upr;
1606 unsigned int i = 0;
1607 dma_addr_t paddr;
1608 int err = 0;
1609 u8 *mac[2];
1610
750afb08
LC		 1611 eeprom = dma_alloc_coherent(&sdev->pdev->dev, SLIC_EEPROM_SIZE,
1612 &paddr, GFP_KERNEL);
60c140df
LS		 1613 if (!eeprom)
1614 return -ENOMEM;
1615
1616 slic_write(sdev, SLIC_REG_ICR, SLIC_ICR_INT_OFF);
1617 /* setup ISP temporarily */
1618 slic_write(sdev, SLIC_REG_ISP, lower_32_bits(sm->isr_paddr));
1619
1620 err = slic_new_upr(sdev, SLIC_UPR_CONFIG, paddr);
1621 if (!err) {
1622 for (i = 0; i < MAX_LOOPS; i++) {
1623 if (le32_to_cpu(sm_data->isr) & SLIC_ISR_UPC)
1624 break;
1625 mdelay(1);
1626 }
1627 if (i == MAX_LOOPS) {
1628 dev_err(&sdev->pdev->dev,
1629 "timed out while waiting for eeprom data\n");
1630 err = -ETIMEDOUT;
1631 }
1632 upr = slic_dequeue_upr(sdev);
1633 kfree(upr);
1634 }
1635
1636 slic_write(sdev, SLIC_REG_ISP, 0);
1637 slic_write(sdev, SLIC_REG_ISR, 0);
1638 slic_flush_write(sdev);
1639
1640 if (err)
1641 goto free_eeprom;
1642
1643 if (sdev->model == SLIC_MODEL_OASIS) {
1644 struct slic_oasis_eeprom *oee;
1645
1646 oee = (struct slic_oasis_eeprom *)eeprom;
1647 mac[0] = oee->mac;
1648 mac[1] = oee->mac2;
1649 codesize = le16_to_cpu(oee->eeprom_code_size);
1650 } else {
1651 struct slic_mojave_eeprom *mee;
1652
1653 mee = (struct slic_mojave_eeprom *)eeprom;
1654 mac[0] = mee->mac;
1655 mac[1] = mee->mac2;
1656 codesize = le16_to_cpu(mee->eeprom_code_size);
1657 }
1658
1659 if (!slic_eeprom_valid(eeprom, codesize)) {
1660 dev_err(&sdev->pdev->dev, "invalid checksum in eeprom\n");
1661 err = -EINVAL;
1662 goto free_eeprom;
1663 }
1664 /* set mac address */
1665 ether_addr_copy(sdev->netdev->dev_addr, mac[devfn]);
1666free_eeprom:
1667 dma_free_coherent(&sdev->pdev->dev, SLIC_EEPROM_SIZE, eeprom, paddr);
1668
1669 return err;
1670}
1671
1672static int slic_init(struct slic_device *sdev)
1673{
1674 int err;
1675
1676 spin_lock_init(&sdev->upper_lock);
1677 spin_lock_init(&sdev->link_lock);
1678 INIT_LIST_HEAD(&sdev->upr_list.list);
1679 spin_lock_init(&sdev->upr_list.lock);
1680 u64_stats_init(&sdev->stats.syncp);
1681
1682 slic_card_reset(sdev);
1683
1684 err = slic_load_firmware(sdev);
1685 if (err) {
1686 dev_err(&sdev->pdev->dev, "failed to load firmware\n");
1687 return err;
1688 }
1689
1690 /* we need the shared memory to read EEPROM so set it up temporarily */
1691 err = slic_init_shmem(sdev);
1692 if (err) {
1693 dev_err(&sdev->pdev->dev, "failed to init shared memory\n");
1694 return err;
1695 }
1696
1697 err = slic_read_eeprom(sdev);
1698 if (err) {
1699 dev_err(&sdev->pdev->dev, "failed to read eeprom\n");
1700 goto free_sm;
1701 }
1702
1703 slic_card_reset(sdev);
1704 slic_free_shmem(sdev);
1705
1706 return 0;
1707free_sm:
1708 slic_free_shmem(sdev);
1709
1710 return err;
1711}
1712
1713static bool slic_is_fiber(unsigned short subdev)
1714{
1715 switch (subdev) {
1716 /* Mojave */
1717 case PCI_SUBDEVICE_ID_ALACRITECH_1000X1F: /* fallthrough */
1718 case PCI_SUBDEVICE_ID_ALACRITECH_SES1001F: /* fallthrough */
1719 /* Oasis */
1720 case PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XF: /* fallthrough */
1721 case PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XF: /* fallthrough */
1722 case PCI_SUBDEVICE_ID_ALACRITECH_SEN2104EF: /* fallthrough */
1723 case PCI_SUBDEVICE_ID_ALACRITECH_SEN2102EF: /* fallthrough */
1724 return true;
1725 }
1726 return false;
1727}
1728
1729static void slic_configure_pci(struct pci_dev *pdev)
1730{
1731 u16 old;
1732 u16 cmd;
1733
1734 pci_read_config_word(pdev, PCI_COMMAND, &old);
1735
1736 cmd = old | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
1737 if (old != cmd)
1738 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1739}
1740
1741static int slic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1742{
1743 struct slic_device *sdev;
1744 struct net_device *dev;
1745 int err;
1746
1747 err = pci_enable_device(pdev);
1748 if (err) {
1749 dev_err(&pdev->dev, "failed to enable PCI device\n");
1750 return err;
1751 }
1752
1753 pci_set_master(pdev);
1754 pci_try_set_mwi(pdev);
1755
1756 slic_configure_pci(pdev);
1757
1758 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1759 if (err) {
1760 dev_err(&pdev->dev, "failed to setup DMA\n");
1761 goto disable;
1762 }
1763
1764 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1765
1766 err = pci_request_regions(pdev, DRV_NAME);
1767 if (err) {
1768 dev_err(&pdev->dev, "failed to obtain PCI regions\n");
1769 goto disable;
1770 }
1771
1772 dev = alloc_etherdev(sizeof(*sdev));
1773 if (!dev) {
1774 dev_err(&pdev->dev, "failed to alloc ethernet device\n");
1775 err = -ENOMEM;
1776 goto free_regions;
1777 }
1778
1779 SET_NETDEV_DEV(dev, &pdev->dev);
1780 pci_set_drvdata(pdev, dev);
1781 dev->irq = pdev->irq;
1782 dev->netdev_ops = &slic_netdev_ops;
1783 dev->hw_features = NETIF_F_RXCSUM;
1784 dev->features |= dev->hw_features;
1785
1786 dev->ethtool_ops = &slic_ethtool_ops;
1787
1788 sdev = netdev_priv(dev);
1789 sdev->model = (pdev->device == PCI_DEVICE_ID_ALACRITECH_OASIS) ?
1790 SLIC_MODEL_OASIS : SLIC_MODEL_MOJAVE;
1791 sdev->is_fiber = slic_is_fiber(pdev->subsystem_device);
1792 sdev->pdev = pdev;
1793 sdev->netdev = dev;
1794 sdev->regs = ioremap_nocache(pci_resource_start(pdev, 0),
1795 pci_resource_len(pdev, 0));
1796 if (!sdev->regs) {
1797 dev_err(&pdev->dev, "failed to map registers\n");
1798 err = -ENOMEM;
1799 goto free_netdev;
1800 }
1801
1802 err = slic_init(sdev);
1803 if (err) {
1804 dev_err(&pdev->dev, "failed to initialize driver\n");
1805 goto unmap;
1806 }
1807
1808 netif_napi_add(dev, &sdev->napi, slic_poll, SLIC_NAPI_WEIGHT);
1809 netif_carrier_off(dev);
1810
1811 err = register_netdev(dev);
1812 if (err) {
1813 dev_err(&pdev->dev, "failed to register net device: %i\n", err);
1814 goto unmap;
1815 }
1816
1817 return 0;
1818
1819unmap:
1820 iounmap(sdev->regs);
1821free_netdev:
1822 free_netdev(dev);
1823free_regions:
1824 pci_release_regions(pdev);
1825disable:
1826 pci_disable_device(pdev);
1827
1828 return err;
1829}
1830
1831static void slic_remove(struct pci_dev *pdev)
1832{
1833 struct net_device *dev = pci_get_drvdata(pdev);
1834 struct slic_device *sdev = netdev_priv(dev);
1835
1836 unregister_netdev(dev);
1837 iounmap(sdev->regs);
1838 free_netdev(dev);
1839 pci_release_regions(pdev);
1840 pci_disable_device(pdev);
1841}
1842
1843static struct pci_driver slic_driver = {
1844 .name = DRV_NAME,
1845 .id_table = slic_id_tbl,
1846 .probe = slic_probe,
1847 .remove = slic_remove,
1848};
1849
3f0dd6b7 1850module_pci_driver(slic_driver);
60c140df
LS		 1851
1852MODULE_DESCRIPTION("Alacritech non-accelerated SLIC driver");
1853MODULE_AUTHOR("Lino Sanfilippo <LinoSanfilippo@gmx.de>");
1854MODULE_LICENSE("GPL");
1855MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)