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e1000e: add support for new 82574L part
[linux-2.6-block.git] / drivers / net / e1000e / phy.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
ad68076e 4 Copyright(c) 1999 - 2008 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/delay.h>
30
31#include "e1000.h"
32
33static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36static s32 e1000_wait_autoneg(struct e1000_hw *hw);
97ac8cae
BA		 37static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
bc7f75fa
AK		 40
41/* Cable length tables */
42static const u16 e1000_m88_cable_length_table[] =
43 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
44
45static const u16 e1000_igp_2_cable_length_table[] =
46 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
47 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
48 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
49 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
50 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
51 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
52 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
53 124};
54#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
c00acf46 55 ARRAY_SIZE(e1000_igp_2_cable_length_table)
bc7f75fa
AK		 56
57/**
58 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
59 * @hw: pointer to the HW structure
60 *
61 * Read the PHY management control register and check whether a PHY reset
62 * is blocked. If a reset is not blocked return 0, otherwise
63 * return E1000_BLK_PHY_RESET (12).
64 **/
65s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
66{
67 u32 manc;
68
69 manc = er32(MANC);
70
71 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
72 E1000_BLK_PHY_RESET : 0;
73}
74
75/**
76 * e1000e_get_phy_id - Retrieve the PHY ID and revision
77 * @hw: pointer to the HW structure
78 *
79 * Reads the PHY registers and stores the PHY ID and possibly the PHY
80 * revision in the hardware structure.
81 **/
82s32 e1000e_get_phy_id(struct e1000_hw *hw)
83{
84 struct e1000_phy_info *phy = &hw->phy;
85 s32 ret_val;
86 u16 phy_id;
87
88 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
89 if (ret_val)
90 return ret_val;
91
92 phy->id = (u32)(phy_id << 16);
93 udelay(20);
94 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
95 if (ret_val)
96 return ret_val;
97
98 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
99 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
100
101 return 0;
102}
103
104/**
105 * e1000e_phy_reset_dsp - Reset PHY DSP
106 * @hw: pointer to the HW structure
107 *
108 * Reset the digital signal processor.
109 **/
110s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
111{
112 s32 ret_val;
113
114 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
115 if (ret_val)
116 return ret_val;
117
118 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
119}
120
121/**
2d9498f3 122 * e1000e_read_phy_reg_mdic - Read MDI control register
bc7f75fa
AK		 123 * @hw: pointer to the HW structure
124 * @offset: register offset to be read
125 * @data: pointer to the read data
126 *
489815ce 127 * Reads the MDI control register in the PHY at offset and stores the
bc7f75fa
AK		 128 * information read to data.
129 **/
2d9498f3 130s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
bc7f75fa
AK		 131{
132 struct e1000_phy_info *phy = &hw->phy;
133 u32 i, mdic = 0;
134
135 if (offset > MAX_PHY_REG_ADDRESS) {
136 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
137 return -E1000_ERR_PARAM;
138 }
139
ad68076e
BA		 140 /*
141 * Set up Op-code, Phy Address, and register offset in the MDI
bc7f75fa
AK		 142 * Control register. The MAC will take care of interfacing with the
143 * PHY to retrieve the desired data.
144 */
145 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
146 (phy->addr << E1000_MDIC_PHY_SHIFT) |
147 (E1000_MDIC_OP_READ));
148
149 ew32(MDIC, mdic);
150
ad68076e
BA		 151 /*
152 * Poll the ready bit to see if the MDI read completed
153 * Increasing the time out as testing showed failures with
154 * the lower time out
155 */
2d9498f3 156 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
bc7f75fa
AK		 157 udelay(50);
158 mdic = er32(MDIC);
159 if (mdic & E1000_MDIC_READY)
160 break;
161 }
162 if (!(mdic & E1000_MDIC_READY)) {
163 hw_dbg(hw, "MDI Read did not complete\n");
164 return -E1000_ERR_PHY;
165 }
166 if (mdic & E1000_MDIC_ERROR) {
167 hw_dbg(hw, "MDI Error\n");
168 return -E1000_ERR_PHY;
169 }
170 *data = (u16) mdic;
171
172 return 0;
173}
174
175/**
2d9498f3 176 * e1000e_write_phy_reg_mdic - Write MDI control register
bc7f75fa
AK		 177 * @hw: pointer to the HW structure
178 * @offset: register offset to write to
179 * @data: data to write to register at offset
180 *
181 * Writes data to MDI control register in the PHY at offset.
182 **/
2d9498f3 183s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
bc7f75fa
AK		 184{
185 struct e1000_phy_info *phy = &hw->phy;
186 u32 i, mdic = 0;
187
188 if (offset > MAX_PHY_REG_ADDRESS) {
189 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
190 return -E1000_ERR_PARAM;
191 }
192
ad68076e
BA		 193 /*
194 * Set up Op-code, Phy Address, and register offset in the MDI
bc7f75fa
AK		 195 * Control register. The MAC will take care of interfacing with the
196 * PHY to retrieve the desired data.
197 */
198 mdic = (((u32)data) |
199 (offset << E1000_MDIC_REG_SHIFT) |
200 (phy->addr << E1000_MDIC_PHY_SHIFT) |
201 (E1000_MDIC_OP_WRITE));
202
203 ew32(MDIC, mdic);
204
2d9498f3
DG		 205 /*
206 * Poll the ready bit to see if the MDI read completed
207 * Increasing the time out as testing showed failures with
208 * the lower time out
209 */
210 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
211 udelay(50);
bc7f75fa
AK		 212 mdic = er32(MDIC);
213 if (mdic & E1000_MDIC_READY)
214 break;
215 }
216 if (!(mdic & E1000_MDIC_READY)) {
217 hw_dbg(hw, "MDI Write did not complete\n");
218 return -E1000_ERR_PHY;
219 }
2d9498f3
DG		 220 if (mdic & E1000_MDIC_ERROR) {
221 hw_dbg(hw, "MDI Error\n");
222 return -E1000_ERR_PHY;
223 }
bc7f75fa
AK		 224
225 return 0;
226}
227
228/**
229 * e1000e_read_phy_reg_m88 - Read m88 PHY register
230 * @hw: pointer to the HW structure
231 * @offset: register offset to be read
232 * @data: pointer to the read data
233 *
234 * Acquires semaphore, if necessary, then reads the PHY register at offset
235 * and storing the retrieved information in data. Release any acquired
236 * semaphores before exiting.
237 **/
238s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
239{
240 s32 ret_val;
241
242 ret_val = hw->phy.ops.acquire_phy(hw);
243 if (ret_val)
244 return ret_val;
245
2d9498f3
DG		 246 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
247 data);
bc7f75fa
AK		 248
249 hw->phy.ops.release_phy(hw);
250
251 return ret_val;
252}
253
254/**
255 * e1000e_write_phy_reg_m88 - Write m88 PHY register
256 * @hw: pointer to the HW structure
257 * @offset: register offset to write to
258 * @data: data to write at register offset
259 *
260 * Acquires semaphore, if necessary, then writes the data to PHY register
261 * at the offset. Release any acquired semaphores before exiting.
262 **/
263s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
264{
265 s32 ret_val;
266
267 ret_val = hw->phy.ops.acquire_phy(hw);
268 if (ret_val)
269 return ret_val;
270
2d9498f3
DG		 271 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
272 data);
bc7f75fa
AK		 273
274 hw->phy.ops.release_phy(hw);
275
276 return ret_val;
277}
278
279/**
280 * e1000e_read_phy_reg_igp - Read igp PHY register
281 * @hw: pointer to the HW structure
282 * @offset: register offset to be read
283 * @data: pointer to the read data
284 *
285 * Acquires semaphore, if necessary, then reads the PHY register at offset
286 * and storing the retrieved information in data. Release any acquired
287 * semaphores before exiting.
288 **/
289s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
290{
291 s32 ret_val;
292
293 ret_val = hw->phy.ops.acquire_phy(hw);
294 if (ret_val)
295 return ret_val;
296
297 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2d9498f3
DG		 298 ret_val = e1000e_write_phy_reg_mdic(hw,
299 IGP01E1000_PHY_PAGE_SELECT,
300 (u16)offset);
bc7f75fa
AK		 301 if (ret_val) {
302 hw->phy.ops.release_phy(hw);
303 return ret_val;
304 }
305 }
306
2d9498f3
DG		 307 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
308 data);
bc7f75fa
AK		 309
310 hw->phy.ops.release_phy(hw);
311
312 return ret_val;
313}
314
315/**
316 * e1000e_write_phy_reg_igp - Write igp PHY register
317 * @hw: pointer to the HW structure
318 * @offset: register offset to write to
319 * @data: data to write at register offset
320 *
321 * Acquires semaphore, if necessary, then writes the data to PHY register
322 * at the offset. Release any acquired semaphores before exiting.
323 **/
324s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
325{
326 s32 ret_val;
327
328 ret_val = hw->phy.ops.acquire_phy(hw);
329 if (ret_val)
330 return ret_val;
331
332 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2d9498f3
DG		 333 ret_val = e1000e_write_phy_reg_mdic(hw,
334 IGP01E1000_PHY_PAGE_SELECT,
335 (u16)offset);
bc7f75fa
AK		 336 if (ret_val) {
337 hw->phy.ops.release_phy(hw);
338 return ret_val;
339 }
340 }
341
2d9498f3
DG		 342 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
343 data);
bc7f75fa
AK		 344
345 hw->phy.ops.release_phy(hw);
346
347 return ret_val;
348}
349
350/**
351 * e1000e_read_kmrn_reg - Read kumeran register
352 * @hw: pointer to the HW structure
353 * @offset: register offset to be read
354 * @data: pointer to the read data
355 *
356 * Acquires semaphore, if necessary. Then reads the PHY register at offset
357 * using the kumeran interface. The information retrieved is stored in data.
358 * Release any acquired semaphores before exiting.
359 **/
360s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
361{
362 u32 kmrnctrlsta;
363 s32 ret_val;
364
365 ret_val = hw->phy.ops.acquire_phy(hw);
366 if (ret_val)
367 return ret_val;
368
369 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
370 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
371 ew32(KMRNCTRLSTA, kmrnctrlsta);
372
373 udelay(2);
374
375 kmrnctrlsta = er32(KMRNCTRLSTA);
376 *data = (u16)kmrnctrlsta;
377
378 hw->phy.ops.release_phy(hw);
379
380 return ret_val;
381}
382
383/**
384 * e1000e_write_kmrn_reg - Write kumeran register
385 * @hw: pointer to the HW structure
386 * @offset: register offset to write to
387 * @data: data to write at register offset
388 *
389 * Acquires semaphore, if necessary. Then write the data to PHY register
390 * at the offset using the kumeran interface. Release any acquired semaphores
391 * before exiting.
392 **/
393s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
394{
395 u32 kmrnctrlsta;
396 s32 ret_val;
397
398 ret_val = hw->phy.ops.acquire_phy(hw);
399 if (ret_val)
400 return ret_val;
401
402 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
403 E1000_KMRNCTRLSTA_OFFSET) | data;
404 ew32(KMRNCTRLSTA, kmrnctrlsta);
405
406 udelay(2);
407 hw->phy.ops.release_phy(hw);
408
409 return ret_val;
410}
411
412/**
413 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
414 * @hw: pointer to the HW structure
415 *
416 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
417 * and downshift values are set also.
418 **/
419s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
420{
421 struct e1000_phy_info *phy = &hw->phy;
422 s32 ret_val;
423 u16 phy_data;
424
ad68076e 425 /* Enable CRS on Tx. This must be set for half-duplex operation. */
bc7f75fa
AK		 426 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
427 if (ret_val)
428 return ret_val;
429
2d9498f3
DG		 430 /* For newer PHYs this bit is downshift enable */
431 if (phy->type == e1000_phy_m88)
432 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
bc7f75fa 433
ad68076e
BA		 434 /*
435 * Options:
bc7f75fa
AK		 436 * MDI/MDI-X = 0 (default)
437 * 0 - Auto for all speeds
438 * 1 - MDI mode
439 * 2 - MDI-X mode
440 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
441 */
442 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
443
444 switch (phy->mdix) {
445 case 1:
446 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
447 break;
448 case 2:
449 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
450 break;
451 case 3:
452 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
453 break;
454 case 0:
455 default:
456 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
457 break;
458 }
459
ad68076e
BA		 460 /*
461 * Options:
bc7f75fa
AK		 462 * disable_polarity_correction = 0 (default)
463 * Automatic Correction for Reversed Cable Polarity
464 * 0 - Disabled
465 * 1 - Enabled
466 */
467 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
468 if (phy->disable_polarity_correction == 1)
469 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
470
97ac8cae
BA		 471 /* Enable downshift on BM (disabled by default) */
472 if (phy->type == e1000_phy_bm)
473 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
474
bc7f75fa
AK		 475 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
476 if (ret_val)
477 return ret_val;
478
4662e82b
BA		 479 if ((phy->type == e1000_phy_m88) &&
480 (phy->revision < E1000_REVISION_4) &&
481 (phy->id != BME1000_E_PHY_ID_R2)) {
ad68076e
BA		 482 /*
483 * Force TX_CLK in the Extended PHY Specific Control Register
bc7f75fa
AK		 484 * to 25MHz clock.
485 */
486 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
487 if (ret_val)
488 return ret_val;
489
490 phy_data |= M88E1000_EPSCR_TX_CLK_25;
491
492 if ((phy->revision == 2) &&
493 (phy->id == M88E1111_I_PHY_ID)) {
494 /* 82573L PHY - set the downshift counter to 5x. */
495 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
496 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
497 } else {
498 /* Configure Master and Slave downshift values */
499 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
500 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
501 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
502 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
503 }
504 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
505 if (ret_val)
506 return ret_val;
507 }
508
4662e82b
BA		 509 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
510 /* Set PHY page 0, register 29 to 0x0003 */
511 ret_val = e1e_wphy(hw, 29, 0x0003);
512 if (ret_val)
513 return ret_val;
514
515 /* Set PHY page 0, register 30 to 0x0000 */
516 ret_val = e1e_wphy(hw, 30, 0x0000);
517 if (ret_val)
518 return ret_val;
519 }
520
bc7f75fa
AK		 521 /* Commit the changes. */
522 ret_val = e1000e_commit_phy(hw);
523 if (ret_val)
524 hw_dbg(hw, "Error committing the PHY changes\n");
525
526 return ret_val;
527}
528
529/**
530 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
531 * @hw: pointer to the HW structure
532 *
533 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
534 * igp PHY's.
535 **/
536s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
537{
538 struct e1000_phy_info *phy = &hw->phy;
539 s32 ret_val;
540 u16 data;
541
542 ret_val = e1000_phy_hw_reset(hw);
543 if (ret_val) {
544 hw_dbg(hw, "Error resetting the PHY.\n");
545 return ret_val;
546 }
547
2d9498f3
DG		 548 /*
549 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
550 * timeout issues when LFS is enabled.
551 */
552 msleep(100);
bc7f75fa
AK		 553
554 /* disable lplu d0 during driver init */
555 ret_val = e1000_set_d0_lplu_state(hw, 0);
556 if (ret_val) {
557 hw_dbg(hw, "Error Disabling LPLU D0\n");
558 return ret_val;
559 }
560 /* Configure mdi-mdix settings */
561 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
562 if (ret_val)
563 return ret_val;
564
565 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
566
567 switch (phy->mdix) {
568 case 1:
569 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
570 break;
571 case 2:
572 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
573 break;
574 case 0:
575 default:
576 data |= IGP01E1000_PSCR_AUTO_MDIX;
577 break;
578 }
579 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
580 if (ret_val)
581 return ret_val;
582
583 /* set auto-master slave resolution settings */
584 if (hw->mac.autoneg) {
ad68076e
BA		 585 /*
586 * when autonegotiation advertisement is only 1000Mbps then we
bc7f75fa 587 * should disable SmartSpeed and enable Auto MasterSlave
ad68076e
BA		 588 * resolution as hardware default.
589 */
bc7f75fa
AK		 590 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
591 /* Disable SmartSpeed */
592 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 593 &data);
bc7f75fa
AK		 594 if (ret_val)
595 return ret_val;
596
597 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
598 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 599 data);
bc7f75fa
AK		 600 if (ret_val)
601 return ret_val;
602
603 /* Set auto Master/Slave resolution process */
604 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
605 if (ret_val)
606 return ret_val;
607
608 data &= ~CR_1000T_MS_ENABLE;
609 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
610 if (ret_val)
611 return ret_val;
612 }
613
614 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
615 if (ret_val)
616 return ret_val;
617
618 /* load defaults for future use */
619 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
620 ((data & CR_1000T_MS_VALUE) ?
621 e1000_ms_force_master :
622 e1000_ms_force_slave) :
623 e1000_ms_auto;
624
625 switch (phy->ms_type) {
626 case e1000_ms_force_master:
627 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
628 break;
629 case e1000_ms_force_slave:
630 data |= CR_1000T_MS_ENABLE;
631 data &= ~(CR_1000T_MS_VALUE);
632 break;
633 case e1000_ms_auto:
634 data &= ~CR_1000T_MS_ENABLE;
635 default:
636 break;
637 }
638 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
639 }
640
641 return ret_val;
642}
643
644/**
645 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
646 * @hw: pointer to the HW structure
647 *
648 * Reads the MII auto-neg advertisement register and/or the 1000T control
649 * register and if the PHY is already setup for auto-negotiation, then
650 * return successful. Otherwise, setup advertisement and flow control to
651 * the appropriate values for the wanted auto-negotiation.
652 **/
653static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
654{
655 struct e1000_phy_info *phy = &hw->phy;
656 s32 ret_val;
657 u16 mii_autoneg_adv_reg;
658 u16 mii_1000t_ctrl_reg = 0;
659
660 phy->autoneg_advertised &= phy->autoneg_mask;
661
662 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
663 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
664 if (ret_val)
665 return ret_val;
666
667 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
668 /* Read the MII 1000Base-T Control Register (Address 9). */
669 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
670 if (ret_val)
671 return ret_val;
672 }
673
ad68076e
BA		 674 /*
675 * Need to parse both autoneg_advertised and fc and set up
bc7f75fa
AK		 676 * the appropriate PHY registers. First we will parse for
677 * autoneg_advertised software override. Since we can advertise
678 * a plethora of combinations, we need to check each bit
679 * individually.
680 */
681
ad68076e
BA		 682 /*
683 * First we clear all the 10/100 mb speed bits in the Auto-Neg
bc7f75fa
AK		 684 * Advertisement Register (Address 4) and the 1000 mb speed bits in
685 * the 1000Base-T Control Register (Address 9).
686 */
687 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
688 NWAY_AR_100TX_HD_CAPS |
689 NWAY_AR_10T_FD_CAPS |
690 NWAY_AR_10T_HD_CAPS);
691 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
692
693 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
694
695 /* Do we want to advertise 10 Mb Half Duplex? */
696 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
697 hw_dbg(hw, "Advertise 10mb Half duplex\n");
698 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
699 }
700
701 /* Do we want to advertise 10 Mb Full Duplex? */
702 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
703 hw_dbg(hw, "Advertise 10mb Full duplex\n");
704 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
705 }
706
707 /* Do we want to advertise 100 Mb Half Duplex? */
708 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
709 hw_dbg(hw, "Advertise 100mb Half duplex\n");
710 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
711 }
712
713 /* Do we want to advertise 100 Mb Full Duplex? */
714 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
715 hw_dbg(hw, "Advertise 100mb Full duplex\n");
716 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
717 }
718
719 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
720 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
721 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
722
723 /* Do we want to advertise 1000 Mb Full Duplex? */
724 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
725 hw_dbg(hw, "Advertise 1000mb Full duplex\n");
726 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
727 }
728
ad68076e
BA		 729 /*
730 * Check for a software override of the flow control settings, and
bc7f75fa
AK		 731 * setup the PHY advertisement registers accordingly. If
732 * auto-negotiation is enabled, then software will have to set the
733 * "PAUSE" bits to the correct value in the Auto-Negotiation
734 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
735 * negotiation.
736 *
737 * The possible values of the "fc" parameter are:
738 * 0: Flow control is completely disabled
739 * 1: Rx flow control is enabled (we can receive pause frames
740 * but not send pause frames).
741 * 2: Tx flow control is enabled (we can send pause frames
742 * but we do not support receiving pause frames).
ad68076e 743 * 3: Both Rx and Tx flow control (symmetric) are enabled.
bc7f75fa
AK		 744 * other: No software override. The flow control configuration
745 * in the EEPROM is used.
746 */
318a94d6 747 switch (hw->fc.type) {
bc7f75fa 748 case e1000_fc_none:
ad68076e
BA		 749 /*
750 * Flow control (Rx & Tx) is completely disabled by a
bc7f75fa
AK		 751 * software over-ride.
752 */
753 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
754 break;
755 case e1000_fc_rx_pause:
ad68076e
BA		 756 /*
757 * Rx Flow control is enabled, and Tx Flow control is
bc7f75fa 758 * disabled, by a software over-ride.
ad68076e
BA		 759 *
760 * Since there really isn't a way to advertise that we are
761 * capable of Rx Pause ONLY, we will advertise that we
762 * support both symmetric and asymmetric Rx PAUSE. Later
bc7f75fa
AK		 763 * (in e1000e_config_fc_after_link_up) we will disable the
764 * hw's ability to send PAUSE frames.
765 */
766 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
767 break;
768 case e1000_fc_tx_pause:
ad68076e
BA		 769 /*
770 * Tx Flow control is enabled, and Rx Flow control is
bc7f75fa
AK		 771 * disabled, by a software over-ride.
772 */
773 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
774 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
775 break;
776 case e1000_fc_full:
ad68076e
BA		 777 /*
778 * Flow control (both Rx and Tx) is enabled by a software
bc7f75fa
AK		 779 * over-ride.
780 */
781 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
782 break;
783 default:
784 hw_dbg(hw, "Flow control param set incorrectly\n");
785 ret_val = -E1000_ERR_CONFIG;
786 return ret_val;
787 }
788
789 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
790 if (ret_val)
791 return ret_val;
792
793 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
794
795 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
796 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
797 }
798
799 return ret_val;
800}
801
802/**
803 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
804 * @hw: pointer to the HW structure
805 *
806 * Performs initial bounds checking on autoneg advertisement parameter, then
807 * configure to advertise the full capability. Setup the PHY to autoneg
808 * and restart the negotiation process between the link partner. If
ad68076e 809 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
bc7f75fa
AK		 810 **/
811static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
812{
813 struct e1000_phy_info *phy = &hw->phy;
814 s32 ret_val;
815 u16 phy_ctrl;
816
ad68076e
BA		 817 /*
818 * Perform some bounds checking on the autoneg advertisement
bc7f75fa
AK		 819 * parameter.
820 */
821 phy->autoneg_advertised &= phy->autoneg_mask;
822
ad68076e
BA		 823 /*
824 * If autoneg_advertised is zero, we assume it was not defaulted
bc7f75fa
AK		 825 * by the calling code so we set to advertise full capability.
826 */
827 if (phy->autoneg_advertised == 0)
828 phy->autoneg_advertised = phy->autoneg_mask;
829
830 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
831 ret_val = e1000_phy_setup_autoneg(hw);
832 if (ret_val) {
833 hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
834 return ret_val;
835 }
836 hw_dbg(hw, "Restarting Auto-Neg\n");
837
ad68076e
BA		 838 /*
839 * Restart auto-negotiation by setting the Auto Neg Enable bit and
bc7f75fa
AK		 840 * the Auto Neg Restart bit in the PHY control register.
841 */
842 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
843 if (ret_val)
844 return ret_val;
845
846 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
847 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
848 if (ret_val)
849 return ret_val;
850
ad68076e
BA		 851 /*
852 * Does the user want to wait for Auto-Neg to complete here, or
bc7f75fa
AK		 853 * check at a later time (for example, callback routine).
854 */
318a94d6 855 if (phy->autoneg_wait_to_complete) {
bc7f75fa
AK		 856 ret_val = e1000_wait_autoneg(hw);
857 if (ret_val) {
858 hw_dbg(hw, "Error while waiting for "
859 "autoneg to complete\n");
860 return ret_val;
861 }
862 }
863
864 hw->mac.get_link_status = 1;
865
866 return ret_val;
867}
868
869/**
870 * e1000e_setup_copper_link - Configure copper link settings
871 * @hw: pointer to the HW structure
872 *
873 * Calls the appropriate function to configure the link for auto-neg or forced
874 * speed and duplex. Then we check for link, once link is established calls
875 * to configure collision distance and flow control are called. If link is
876 * not established, we return -E1000_ERR_PHY (-2).
877 **/
878s32 e1000e_setup_copper_link(struct e1000_hw *hw)
879{
880 s32 ret_val;
881 bool link;
882
883 if (hw->mac.autoneg) {
ad68076e
BA		 884 /*
885 * Setup autoneg and flow control advertisement and perform
886 * autonegotiation.
887 */
bc7f75fa
AK		 888 ret_val = e1000_copper_link_autoneg(hw);
889 if (ret_val)
890 return ret_val;
891 } else {
ad68076e
BA		 892 /*
893 * PHY will be set to 10H, 10F, 100H or 100F
894 * depending on user settings.
895 */
bc7f75fa
AK		 896 hw_dbg(hw, "Forcing Speed and Duplex\n");
897 ret_val = e1000_phy_force_speed_duplex(hw);
898 if (ret_val) {
899 hw_dbg(hw, "Error Forcing Speed and Duplex\n");
900 return ret_val;
901 }
902 }
903
ad68076e
BA		 904 /*
905 * Check link status. Wait up to 100 microseconds for link to become
bc7f75fa
AK		 906 * valid.
907 */
908 ret_val = e1000e_phy_has_link_generic(hw,
909 COPPER_LINK_UP_LIMIT,
910 10,
911 &link);
912 if (ret_val)
913 return ret_val;
914
915 if (link) {
916 hw_dbg(hw, "Valid link established!!!\n");
917 e1000e_config_collision_dist(hw);
918 ret_val = e1000e_config_fc_after_link_up(hw);
919 } else {
920 hw_dbg(hw, "Unable to establish link!!!\n");
921 }
922
923 return ret_val;
924}
925
926/**
927 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
928 * @hw: pointer to the HW structure
929 *
930 * Calls the PHY setup function to force speed and duplex. Clears the
931 * auto-crossover to force MDI manually. Waits for link and returns
932 * successful if link up is successful, else -E1000_ERR_PHY (-2).
933 **/
934s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
935{
936 struct e1000_phy_info *phy = &hw->phy;
937 s32 ret_val;
938 u16 phy_data;
939 bool link;
940
941 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
942 if (ret_val)
943 return ret_val;
944
945 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
946
947 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
948 if (ret_val)
949 return ret_val;
950
ad68076e
BA		 951 /*
952 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
bc7f75fa
AK		 953 * forced whenever speed and duplex are forced.
954 */
955 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
956 if (ret_val)
957 return ret_val;
958
959 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
960 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
961
962 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
963 if (ret_val)
964 return ret_val;
965
966 hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
967
968 udelay(1);
969
318a94d6 970 if (phy->autoneg_wait_to_complete) {
bc7f75fa
AK		 971 hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
972
973 ret_val = e1000e_phy_has_link_generic(hw,
974 PHY_FORCE_LIMIT,
975 100000,
976 &link);
977 if (ret_val)
978 return ret_val;
979
980 if (!link)
981 hw_dbg(hw, "Link taking longer than expected.\n");
982
983 /* Try once more */
984 ret_val = e1000e_phy_has_link_generic(hw,
985 PHY_FORCE_LIMIT,
986 100000,
987 &link);
988 if (ret_val)
989 return ret_val;
990 }
991
992 return ret_val;
993}
994
995/**
996 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
997 * @hw: pointer to the HW structure
998 *
999 * Calls the PHY setup function to force speed and duplex. Clears the
1000 * auto-crossover to force MDI manually. Resets the PHY to commit the
1001 * changes. If time expires while waiting for link up, we reset the DSP.
ad68076e 1002 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
bc7f75fa
AK		 1003 * successful completion, else return corresponding error code.
1004 **/
1005s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1006{
1007 struct e1000_phy_info *phy = &hw->phy;
1008 s32 ret_val;
1009 u16 phy_data;
1010 bool link;
1011
ad68076e
BA		 1012 /*
1013 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
bc7f75fa
AK		 1014 * forced whenever speed and duplex are forced.
1015 */
1016 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1017 if (ret_val)
1018 return ret_val;
1019
1020 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1021 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1022 if (ret_val)
1023 return ret_val;
1024
1025 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
1026
1027 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1028 if (ret_val)
1029 return ret_val;
1030
1031 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1032
1033 /* Reset the phy to commit changes. */
1034 phy_data |= MII_CR_RESET;
1035
1036 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1037 if (ret_val)
1038 return ret_val;
1039
1040 udelay(1);
1041
318a94d6 1042 if (phy->autoneg_wait_to_complete) {
bc7f75fa
AK		 1043 hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
1044
1045 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1046 100000, &link);
1047 if (ret_val)
1048 return ret_val;
1049
1050 if (!link) {
ad68076e
BA		 1051 /*
1052 * We didn't get link.
bc7f75fa
AK		 1053 * Reset the DSP and cross our fingers.
1054 */
ad68076e
BA		 1055 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1056 0x001d);
bc7f75fa
AK		 1057 if (ret_val)
1058 return ret_val;
1059 ret_val = e1000e_phy_reset_dsp(hw);
1060 if (ret_val)
1061 return ret_val;
1062 }
1063
1064 /* Try once more */
1065 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1066 100000, &link);
1067 if (ret_val)
1068 return ret_val;
1069 }
1070
1071 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1072 if (ret_val)
1073 return ret_val;
1074
ad68076e
BA		 1075 /*
1076 * Resetting the phy means we need to re-force TX_CLK in the
bc7f75fa
AK		 1077 * Extended PHY Specific Control Register to 25MHz clock from
1078 * the reset value of 2.5MHz.
1079 */
1080 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1081 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1082 if (ret_val)
1083 return ret_val;
1084
ad68076e
BA		 1085 /*
1086 * In addition, we must re-enable CRS on Tx for both half and full
bc7f75fa
AK		 1087 * duplex.
1088 */
1089 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1090 if (ret_val)
1091 return ret_val;
1092
1093 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1094 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1095
1096 return ret_val;
1097}
1098
1099/**
1100 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1101 * @hw: pointer to the HW structure
1102 * @phy_ctrl: pointer to current value of PHY_CONTROL
1103 *
1104 * Forces speed and duplex on the PHY by doing the following: disable flow
1105 * control, force speed/duplex on the MAC, disable auto speed detection,
1106 * disable auto-negotiation, configure duplex, configure speed, configure
1107 * the collision distance, write configuration to CTRL register. The
1108 * caller must write to the PHY_CONTROL register for these settings to
1109 * take affect.
1110 **/
1111void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1112{
1113 struct e1000_mac_info *mac = &hw->mac;
1114 u32 ctrl;
1115
1116 /* Turn off flow control when forcing speed/duplex */
318a94d6 1117 hw->fc.type = e1000_fc_none;
bc7f75fa
AK		 1118
1119 /* Force speed/duplex on the mac */
1120 ctrl = er32(CTRL);
1121 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1122 ctrl &= ~E1000_CTRL_SPD_SEL;
1123
1124 /* Disable Auto Speed Detection */
1125 ctrl &= ~E1000_CTRL_ASDE;
1126
1127 /* Disable autoneg on the phy */
1128 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1129
1130 /* Forcing Full or Half Duplex? */
1131 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1132 ctrl &= ~E1000_CTRL_FD;
1133 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1134 hw_dbg(hw, "Half Duplex\n");
1135 } else {
1136 ctrl |= E1000_CTRL_FD;
1137 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1138 hw_dbg(hw, "Full Duplex\n");
1139 }
1140
1141 /* Forcing 10mb or 100mb? */
1142 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1143 ctrl |= E1000_CTRL_SPD_100;
1144 *phy_ctrl |= MII_CR_SPEED_100;
1145 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1146 hw_dbg(hw, "Forcing 100mb\n");
1147 } else {
1148 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1149 *phy_ctrl |= MII_CR_SPEED_10;
1150 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1151 hw_dbg(hw, "Forcing 10mb\n");
1152 }
1153
1154 e1000e_config_collision_dist(hw);
1155
1156 ew32(CTRL, ctrl);
1157}
1158
1159/**
1160 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1161 * @hw: pointer to the HW structure
1162 * @active: boolean used to enable/disable lplu
1163 *
1164 * Success returns 0, Failure returns 1
1165 *
1166 * The low power link up (lplu) state is set to the power management level D3
1167 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1168 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1169 * is used during Dx states where the power conservation is most important.
1170 * During driver activity, SmartSpeed should be enabled so performance is
1171 * maintained.
1172 **/
1173s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1174{
1175 struct e1000_phy_info *phy = &hw->phy;
1176 s32 ret_val;
1177 u16 data;
1178
1179 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1180 if (ret_val)
1181 return ret_val;
1182
1183 if (!active) {
1184 data &= ~IGP02E1000_PM_D3_LPLU;
2d9498f3 1185 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
bc7f75fa
AK		 1186 if (ret_val)
1187 return ret_val;
ad68076e
BA		 1188 /*
1189 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1190 * during Dx states where the power conservation is most
1191 * important. During driver activity we should enable
ad68076e
BA		 1192 * SmartSpeed, so performance is maintained.
1193 */
bc7f75fa
AK		 1194 if (phy->smart_speed == e1000_smart_speed_on) {
1195 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1196 &data);
bc7f75fa
AK		 1197 if (ret_val)
1198 return ret_val;
1199
1200 data |= IGP01E1000_PSCFR_SMART_SPEED;
1201 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1202 data);
bc7f75fa
AK		 1203 if (ret_val)
1204 return ret_val;
1205 } else if (phy->smart_speed == e1000_smart_speed_off) {
1206 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1207 &data);
bc7f75fa
AK		 1208 if (ret_val)
1209 return ret_val;
1210
1211 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1212 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1213 data);
bc7f75fa
AK		 1214 if (ret_val)
1215 return ret_val;
1216 }
1217 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1218 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1219 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1220 data |= IGP02E1000_PM_D3_LPLU;
1221 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1222 if (ret_val)
1223 return ret_val;
1224
1225 /* When LPLU is enabled, we should disable SmartSpeed */
1226 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1227 if (ret_val)
1228 return ret_val;
1229
1230 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1231 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1232 }
1233
1234 return ret_val;
1235}
1236
1237/**
489815ce 1238 * e1000e_check_downshift - Checks whether a downshift in speed occurred
bc7f75fa
AK		 1239 * @hw: pointer to the HW structure
1240 *
1241 * Success returns 0, Failure returns 1
1242 *
1243 * A downshift is detected by querying the PHY link health.
1244 **/
1245s32 e1000e_check_downshift(struct e1000_hw *hw)
1246{
1247 struct e1000_phy_info *phy = &hw->phy;
1248 s32 ret_val;
1249 u16 phy_data, offset, mask;
1250
1251 switch (phy->type) {
1252 case e1000_phy_m88:
1253 case e1000_phy_gg82563:
1254 offset = M88E1000_PHY_SPEC_STATUS;
1255 mask = M88E1000_PSSR_DOWNSHIFT;
1256 break;
1257 case e1000_phy_igp_2:
1258 case e1000_phy_igp_3:
1259 offset = IGP01E1000_PHY_LINK_HEALTH;
1260 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1261 break;
1262 default:
1263 /* speed downshift not supported */
1264 phy->speed_downgraded = 0;
1265 return 0;
1266 }
1267
1268 ret_val = e1e_rphy(hw, offset, &phy_data);
1269
1270 if (!ret_val)
1271 phy->speed_downgraded = (phy_data & mask);
1272
1273 return ret_val;
1274}
1275
1276/**
1277 * e1000_check_polarity_m88 - Checks the polarity.
1278 * @hw: pointer to the HW structure
1279 *
1280 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1281 *
1282 * Polarity is determined based on the PHY specific status register.
1283 **/
1284static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1285{
1286 struct e1000_phy_info *phy = &hw->phy;
1287 s32 ret_val;
1288 u16 data;
1289
1290 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1291
1292 if (!ret_val)
1293 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1294 ? e1000_rev_polarity_reversed
1295 : e1000_rev_polarity_normal;
1296
1297 return ret_val;
1298}
1299
1300/**
1301 * e1000_check_polarity_igp - Checks the polarity.
1302 * @hw: pointer to the HW structure
1303 *
1304 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1305 *
1306 * Polarity is determined based on the PHY port status register, and the
1307 * current speed (since there is no polarity at 100Mbps).
1308 **/
1309static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1310{
1311 struct e1000_phy_info *phy = &hw->phy;
1312 s32 ret_val;
1313 u16 data, offset, mask;
1314
ad68076e
BA		 1315 /*
1316 * Polarity is determined based on the speed of
1317 * our connection.
1318 */
bc7f75fa
AK		 1319 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1320 if (ret_val)
1321 return ret_val;
1322
1323 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1324 IGP01E1000_PSSR_SPEED_1000MBPS) {
1325 offset = IGP01E1000_PHY_PCS_INIT_REG;
1326 mask = IGP01E1000_PHY_POLARITY_MASK;
1327 } else {
ad68076e
BA		 1328 /*
1329 * This really only applies to 10Mbps since
bc7f75fa
AK		 1330 * there is no polarity for 100Mbps (always 0).
1331 */
1332 offset = IGP01E1000_PHY_PORT_STATUS;
1333 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1334 }
1335
1336 ret_val = e1e_rphy(hw, offset, &data);
1337
1338 if (!ret_val)
1339 phy->cable_polarity = (data & mask)
1340 ? e1000_rev_polarity_reversed
1341 : e1000_rev_polarity_normal;
1342
1343 return ret_val;
1344}
1345
1346/**
ad68076e 1347 * e1000_wait_autoneg - Wait for auto-neg completion
bc7f75fa
AK		 1348 * @hw: pointer to the HW structure
1349 *
1350 * Waits for auto-negotiation to complete or for the auto-negotiation time
1351 * limit to expire, which ever happens first.
1352 **/
1353static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1354{
1355 s32 ret_val = 0;
1356 u16 i, phy_status;
1357
1358 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1359 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1360 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1361 if (ret_val)
1362 break;
1363 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1364 if (ret_val)
1365 break;
1366 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1367 break;
1368 msleep(100);
1369 }
1370
ad68076e
BA		 1371 /*
1372 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
bc7f75fa
AK		 1373 * has completed.
1374 */
1375 return ret_val;
1376}
1377
1378/**
1379 * e1000e_phy_has_link_generic - Polls PHY for link
1380 * @hw: pointer to the HW structure
1381 * @iterations: number of times to poll for link
1382 * @usec_interval: delay between polling attempts
1383 * @success: pointer to whether polling was successful or not
1384 *
1385 * Polls the PHY status register for link, 'iterations' number of times.
1386 **/
1387s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1388 u32 usec_interval, bool *success)
1389{
1390 s32 ret_val = 0;
1391 u16 i, phy_status;
1392
1393 for (i = 0; i < iterations; i++) {
ad68076e
BA		 1394 /*
1395 * Some PHYs require the PHY_STATUS register to be read
bc7f75fa
AK		 1396 * twice due to the link bit being sticky. No harm doing
1397 * it across the board.
1398 */
1399 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1400 if (ret_val)
1401 break;
1402 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1403 if (ret_val)
1404 break;
1405 if (phy_status & MII_SR_LINK_STATUS)
1406 break;
1407 if (usec_interval >= 1000)
1408 mdelay(usec_interval/1000);
1409 else
1410 udelay(usec_interval);
1411 }
1412
1413 *success = (i < iterations);
1414
1415 return ret_val;
1416}
1417
1418/**
1419 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1420 * @hw: pointer to the HW structure
1421 *
1422 * Reads the PHY specific status register to retrieve the cable length
1423 * information. The cable length is determined by averaging the minimum and
1424 * maximum values to get the "average" cable length. The m88 PHY has four
1425 * possible cable length values, which are:
1426 * Register Value Cable Length
1427 * 0 < 50 meters
1428 * 1 50 - 80 meters
1429 * 2 80 - 110 meters
1430 * 3 110 - 140 meters
1431 * 4 > 140 meters
1432 **/
1433s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1434{
1435 struct e1000_phy_info *phy = &hw->phy;
1436 s32 ret_val;
1437 u16 phy_data, index;
1438
1439 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1440 if (ret_val)
1441 return ret_val;
1442
1443 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1444 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1445 phy->min_cable_length = e1000_m88_cable_length_table[index];
1446 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1447
1448 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1449
1450 return ret_val;
1451}
1452
1453/**
1454 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1455 * @hw: pointer to the HW structure
1456 *
1457 * The automatic gain control (agc) normalizes the amplitude of the
1458 * received signal, adjusting for the attenuation produced by the
489815ce
AK		 1459 * cable. By reading the AGC registers, which represent the
1460 * combination of course and fine gain value, the value can be put
bc7f75fa
AK		 1461 * into a lookup table to obtain the approximate cable length
1462 * for each channel.
1463 **/
1464s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1465{
1466 struct e1000_phy_info *phy = &hw->phy;
1467 s32 ret_val;
1468 u16 phy_data, i, agc_value = 0;
1469 u16 cur_agc_index, max_agc_index = 0;
1470 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1471 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1472 {IGP02E1000_PHY_AGC_A,
1473 IGP02E1000_PHY_AGC_B,
1474 IGP02E1000_PHY_AGC_C,
1475 IGP02E1000_PHY_AGC_D};
1476
1477 /* Read the AGC registers for all channels */
1478 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1479 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1480 if (ret_val)
1481 return ret_val;
1482
ad68076e
BA		 1483 /*
1484 * Getting bits 15:9, which represent the combination of
bc7f75fa
AK		 1485 * course and fine gain values. The result is a number
1486 * that can be put into the lookup table to obtain the
ad68076e
BA		 1487 * approximate cable length.
1488 */
bc7f75fa
AK		 1489 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1490 IGP02E1000_AGC_LENGTH_MASK;
1491
1492 /* Array index bound check. */
1493 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1494 (cur_agc_index == 0))
1495 return -E1000_ERR_PHY;
1496
1497 /* Remove min & max AGC values from calculation. */
1498 if (e1000_igp_2_cable_length_table[min_agc_index] >
1499 e1000_igp_2_cable_length_table[cur_agc_index])
1500 min_agc_index = cur_agc_index;
1501 if (e1000_igp_2_cable_length_table[max_agc_index] <
1502 e1000_igp_2_cable_length_table[cur_agc_index])
1503 max_agc_index = cur_agc_index;
1504
1505 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1506 }
1507
1508 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1509 e1000_igp_2_cable_length_table[max_agc_index]);
1510 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1511
1512 /* Calculate cable length with the error range of +/- 10 meters. */
1513 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1514 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1515 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1516
1517 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1518
1519 return ret_val;
1520}
1521
1522/**
1523 * e1000e_get_phy_info_m88 - Retrieve PHY information
1524 * @hw: pointer to the HW structure
1525 *
1526 * Valid for only copper links. Read the PHY status register (sticky read)
1527 * to verify that link is up. Read the PHY special control register to
1528 * determine the polarity and 10base-T extended distance. Read the PHY
1529 * special status register to determine MDI/MDIx and current speed. If
1530 * speed is 1000, then determine cable length, local and remote receiver.
1531 **/
1532s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1533{
1534 struct e1000_phy_info *phy = &hw->phy;
1535 s32 ret_val;
1536 u16 phy_data;
1537 bool link;
1538
318a94d6 1539 if (hw->phy.media_type != e1000_media_type_copper) {
bc7f75fa
AK		 1540 hw_dbg(hw, "Phy info is only valid for copper media\n");
1541 return -E1000_ERR_CONFIG;
1542 }
1543
1544 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1545 if (ret_val)
1546 return ret_val;
1547
1548 if (!link) {
1549 hw_dbg(hw, "Phy info is only valid if link is up\n");
1550 return -E1000_ERR_CONFIG;
1551 }
1552
1553 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1554 if (ret_val)
1555 return ret_val;
1556
1557 phy->polarity_correction = (phy_data &
1558 M88E1000_PSCR_POLARITY_REVERSAL);
1559
1560 ret_val = e1000_check_polarity_m88(hw);
1561 if (ret_val)
1562 return ret_val;
1563
1564 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1565 if (ret_val)
1566 return ret_val;
1567
1568 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1569
1570 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1571 ret_val = e1000_get_cable_length(hw);
1572 if (ret_val)
1573 return ret_val;
1574
1575 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1576 if (ret_val)
1577 return ret_val;
1578
1579 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1580 ? e1000_1000t_rx_status_ok
1581 : e1000_1000t_rx_status_not_ok;
1582
1583 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1584 ? e1000_1000t_rx_status_ok
1585 : e1000_1000t_rx_status_not_ok;
1586 } else {
1587 /* Set values to "undefined" */
1588 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1589 phy->local_rx = e1000_1000t_rx_status_undefined;
1590 phy->remote_rx = e1000_1000t_rx_status_undefined;
1591 }
1592
1593 return ret_val;
1594}
1595
1596/**
1597 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1598 * @hw: pointer to the HW structure
1599 *
1600 * Read PHY status to determine if link is up. If link is up, then
1601 * set/determine 10base-T extended distance and polarity correction. Read
1602 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1603 * determine on the cable length, local and remote receiver.
1604 **/
1605s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1606{
1607 struct e1000_phy_info *phy = &hw->phy;
1608 s32 ret_val;
1609 u16 data;
1610 bool link;
1611
1612 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1613 if (ret_val)
1614 return ret_val;
1615
1616 if (!link) {
1617 hw_dbg(hw, "Phy info is only valid if link is up\n");
1618 return -E1000_ERR_CONFIG;
1619 }
1620
1621 phy->polarity_correction = 1;
1622
1623 ret_val = e1000_check_polarity_igp(hw);
1624 if (ret_val)
1625 return ret_val;
1626
1627 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1628 if (ret_val)
1629 return ret_val;
1630
1631 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
1632
1633 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1634 IGP01E1000_PSSR_SPEED_1000MBPS) {
1635 ret_val = e1000_get_cable_length(hw);
1636 if (ret_val)
1637 return ret_val;
1638
1639 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
1640 if (ret_val)
1641 return ret_val;
1642
1643 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1644 ? e1000_1000t_rx_status_ok
1645 : e1000_1000t_rx_status_not_ok;
1646
1647 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1648 ? e1000_1000t_rx_status_ok
1649 : e1000_1000t_rx_status_not_ok;
1650 } else {
1651 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1652 phy->local_rx = e1000_1000t_rx_status_undefined;
1653 phy->remote_rx = e1000_1000t_rx_status_undefined;
1654 }
1655
1656 return ret_val;
1657}
1658
1659/**
1660 * e1000e_phy_sw_reset - PHY software reset
1661 * @hw: pointer to the HW structure
1662 *
1663 * Does a software reset of the PHY by reading the PHY control register and
1664 * setting/write the control register reset bit to the PHY.
1665 **/
1666s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
1667{
1668 s32 ret_val;
1669 u16 phy_ctrl;
1670
1671 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1672 if (ret_val)
1673 return ret_val;
1674
1675 phy_ctrl |= MII_CR_RESET;
1676 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1677 if (ret_val)
1678 return ret_val;
1679
1680 udelay(1);
1681
1682 return ret_val;
1683}
1684
1685/**
1686 * e1000e_phy_hw_reset_generic - PHY hardware reset
1687 * @hw: pointer to the HW structure
1688 *
1689 * Verify the reset block is not blocking us from resetting. Acquire
1690 * semaphore (if necessary) and read/set/write the device control reset
1691 * bit in the PHY. Wait the appropriate delay time for the device to
489815ce 1692 * reset and release the semaphore (if necessary).
bc7f75fa
AK		 1693 **/
1694s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1695{
1696 struct e1000_phy_info *phy = &hw->phy;
1697 s32 ret_val;
1698 u32 ctrl;
1699
1700 ret_val = e1000_check_reset_block(hw);
1701 if (ret_val)
1702 return 0;
1703
1704 ret_val = phy->ops.acquire_phy(hw);
1705 if (ret_val)
1706 return ret_val;
1707
1708 ctrl = er32(CTRL);
1709 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
1710 e1e_flush();
1711
1712 udelay(phy->reset_delay_us);
1713
1714 ew32(CTRL, ctrl);
1715 e1e_flush();
1716
1717 udelay(150);
1718
1719 phy->ops.release_phy(hw);
1720
1721 return e1000_get_phy_cfg_done(hw);
1722}
1723
1724/**
1725 * e1000e_get_cfg_done - Generic configuration done
1726 * @hw: pointer to the HW structure
1727 *
1728 * Generic function to wait 10 milli-seconds for configuration to complete
1729 * and return success.
1730 **/
1731s32 e1000e_get_cfg_done(struct e1000_hw *hw)
1732{
1733 mdelay(10);
1734 return 0;
1735}
1736
f4187b56
BA		 1737/**
1738 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
1739 * @hw: pointer to the HW structure
1740 *
1741 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1742 **/
1743s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
1744{
1745 hw_dbg(hw, "Running IGP 3 PHY init script\n");
1746
1747 /* PHY init IGP 3 */
1748 /* Enable rise/fall, 10-mode work in class-A */
1749 e1e_wphy(hw, 0x2F5B, 0x9018);
1750 /* Remove all caps from Replica path filter */
1751 e1e_wphy(hw, 0x2F52, 0x0000);
1752 /* Bias trimming for ADC, AFE and Driver (Default) */
1753 e1e_wphy(hw, 0x2FB1, 0x8B24);
1754 /* Increase Hybrid poly bias */
1755 e1e_wphy(hw, 0x2FB2, 0xF8F0);
1756 /* Add 4% to Tx amplitude in Gig mode */
1757 e1e_wphy(hw, 0x2010, 0x10B0);
1758 /* Disable trimming (TTT) */
1759 e1e_wphy(hw, 0x2011, 0x0000);
1760 /* Poly DC correction to 94.6% + 2% for all channels */
1761 e1e_wphy(hw, 0x20DD, 0x249A);
1762 /* ABS DC correction to 95.9% */
1763 e1e_wphy(hw, 0x20DE, 0x00D3);
1764 /* BG temp curve trim */
1765 e1e_wphy(hw, 0x28B4, 0x04CE);
1766 /* Increasing ADC OPAMP stage 1 currents to max */
1767 e1e_wphy(hw, 0x2F70, 0x29E4);
1768 /* Force 1000 ( required for enabling PHY regs configuration) */
1769 e1e_wphy(hw, 0x0000, 0x0140);
1770 /* Set upd_freq to 6 */
1771 e1e_wphy(hw, 0x1F30, 0x1606);
1772 /* Disable NPDFE */
1773 e1e_wphy(hw, 0x1F31, 0xB814);
1774 /* Disable adaptive fixed FFE (Default) */
1775 e1e_wphy(hw, 0x1F35, 0x002A);
1776 /* Enable FFE hysteresis */
1777 e1e_wphy(hw, 0x1F3E, 0x0067);
1778 /* Fixed FFE for short cable lengths */
1779 e1e_wphy(hw, 0x1F54, 0x0065);
1780 /* Fixed FFE for medium cable lengths */
1781 e1e_wphy(hw, 0x1F55, 0x002A);
1782 /* Fixed FFE for long cable lengths */
1783 e1e_wphy(hw, 0x1F56, 0x002A);
1784 /* Enable Adaptive Clip Threshold */
1785 e1e_wphy(hw, 0x1F72, 0x3FB0);
1786 /* AHT reset limit to 1 */
1787 e1e_wphy(hw, 0x1F76, 0xC0FF);
1788 /* Set AHT master delay to 127 msec */
1789 e1e_wphy(hw, 0x1F77, 0x1DEC);
1790 /* Set scan bits for AHT */
1791 e1e_wphy(hw, 0x1F78, 0xF9EF);
1792 /* Set AHT Preset bits */
1793 e1e_wphy(hw, 0x1F79, 0x0210);
1794 /* Change integ_factor of channel A to 3 */
1795 e1e_wphy(hw, 0x1895, 0x0003);
1796 /* Change prop_factor of channels BCD to 8 */
1797 e1e_wphy(hw, 0x1796, 0x0008);
1798 /* Change cg_icount + enable integbp for channels BCD */
1799 e1e_wphy(hw, 0x1798, 0xD008);
1800 /*
1801 * Change cg_icount + enable integbp + change prop_factor_master
1802 * to 8 for channel A
1803 */
1804 e1e_wphy(hw, 0x1898, 0xD918);
1805 /* Disable AHT in Slave mode on channel A */
1806 e1e_wphy(hw, 0x187A, 0x0800);
1807 /*
1808 * Enable LPLU and disable AN to 1000 in non-D0a states,
1809 * Enable SPD+B2B
1810 */
1811 e1e_wphy(hw, 0x0019, 0x008D);
1812 /* Enable restart AN on an1000_dis change */
1813 e1e_wphy(hw, 0x001B, 0x2080);
1814 /* Enable wh_fifo read clock in 10/100 modes */
1815 e1e_wphy(hw, 0x0014, 0x0045);
1816 /* Restart AN, Speed selection is 1000 */
1817 e1e_wphy(hw, 0x0000, 0x1340);
1818
1819 return 0;
1820}
1821
bc7f75fa
AK		 1822/* Internal function pointers */
1823
1824/**
1825 * e1000_get_phy_cfg_done - Generic PHY configuration done
1826 * @hw: pointer to the HW structure
1827 *
1828 * Return success if silicon family did not implement a family specific
1829 * get_cfg_done function.
1830 **/
1831static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
1832{
1833 if (hw->phy.ops.get_cfg_done)
1834 return hw->phy.ops.get_cfg_done(hw);
1835
1836 return 0;
1837}
1838
1839/**
1840 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1841 * @hw: pointer to the HW structure
1842 *
1843 * When the silicon family has not implemented a forced speed/duplex
1844 * function for the PHY, simply return 0.
1845 **/
1846static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1847{
1848 if (hw->phy.ops.force_speed_duplex)
1849 return hw->phy.ops.force_speed_duplex(hw);
1850
1851 return 0;
1852}
1853
1854/**
1855 * e1000e_get_phy_type_from_id - Get PHY type from id
1856 * @phy_id: phy_id read from the phy
1857 *
1858 * Returns the phy type from the id.
1859 **/
1860enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
1861{
1862 enum e1000_phy_type phy_type = e1000_phy_unknown;
1863
1864 switch (phy_id) {
1865 case M88E1000_I_PHY_ID:
1866 case M88E1000_E_PHY_ID:
1867 case M88E1111_I_PHY_ID:
1868 case M88E1011_I_PHY_ID:
1869 phy_type = e1000_phy_m88;
1870 break;
1871 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
1872 phy_type = e1000_phy_igp_2;
1873 break;
1874 case GG82563_E_PHY_ID:
1875 phy_type = e1000_phy_gg82563;
1876 break;
1877 case IGP03E1000_E_PHY_ID:
1878 phy_type = e1000_phy_igp_3;
1879 break;
1880 case IFE_E_PHY_ID:
1881 case IFE_PLUS_E_PHY_ID:
1882 case IFE_C_E_PHY_ID:
1883 phy_type = e1000_phy_ife;
1884 break;
97ac8cae
BA		 1885 case BME1000_E_PHY_ID:
1886 case BME1000_E_PHY_ID_R2:
1887 phy_type = e1000_phy_bm;
1888 break;
bc7f75fa
AK		 1889 default:
1890 phy_type = e1000_phy_unknown;
1891 break;
1892 }
1893 return phy_type;
1894}
1895
97ac8cae
BA		 1896/**
1897 * e1000e_determine_phy_address - Determines PHY address.
1898 * @hw: pointer to the HW structure
1899 *
1900 * This uses a trial and error method to loop through possible PHY
1901 * addresses. It tests each by reading the PHY ID registers and
1902 * checking for a match.
1903 **/
1904s32 e1000e_determine_phy_address(struct e1000_hw *hw)
1905{
1906 s32 ret_val = -E1000_ERR_PHY_TYPE;
1907 u32 phy_addr= 0;
1908 u32 i = 0;
1909 enum e1000_phy_type phy_type = e1000_phy_unknown;
1910
1911 do {
1912 for (phy_addr = 0; phy_addr < 4; phy_addr++) {
1913 hw->phy.addr = phy_addr;
1914 e1000e_get_phy_id(hw);
1915 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
1916
1917 /*
1918 * If phy_type is valid, break - we found our
1919 * PHY address
1920 */
1921 if (phy_type != e1000_phy_unknown) {
1922 ret_val = 0;
1923 break;
1924 }
1925 }
1926 i++;
1927 } while ((ret_val != 0) && (i < 100));
1928
1929 return ret_val;
1930}
1931
1932/**
1933 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
1934 * @page: page to access
1935 *
1936 * Returns the phy address for the page requested.
1937 **/
1938static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
1939{
1940 u32 phy_addr = 2;
1941
1942 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
1943 phy_addr = 1;
1944
1945 return phy_addr;
1946}
1947
1948/**
1949 * e1000e_write_phy_reg_bm - Write BM PHY register
1950 * @hw: pointer to the HW structure
1951 * @offset: register offset to write to
1952 * @data: data to write at register offset
1953 *
1954 * Acquires semaphore, if necessary, then writes the data to PHY register
1955 * at the offset. Release any acquired semaphores before exiting.
1956 **/
1957s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
1958{
1959 s32 ret_val;
1960 u32 page_select = 0;
1961 u32 page = offset >> IGP_PAGE_SHIFT;
1962 u32 page_shift = 0;
1963
1964 /* Page 800 works differently than the rest so it has its own func */
1965 if (page == BM_WUC_PAGE) {
1966 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
1967 false);
1968 goto out;
1969 }
1970
1971 ret_val = hw->phy.ops.acquire_phy(hw);
1972 if (ret_val)
1973 goto out;
1974
1975 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
1976
1977 if (offset > MAX_PHY_MULTI_PAGE_REG) {
1978 /*
1979 * Page select is register 31 for phy address 1 and 22 for
1980 * phy address 2 and 3. Page select is shifted only for
1981 * phy address 1.
1982 */
1983 if (hw->phy.addr == 1) {
1984 page_shift = IGP_PAGE_SHIFT;
1985 page_select = IGP01E1000_PHY_PAGE_SELECT;
1986 } else {
1987 page_shift = 0;
1988 page_select = BM_PHY_PAGE_SELECT;
1989 }
1990
1991 /* Page is shifted left, PHY expects (page x 32) */
1992 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
1993 (page << page_shift));
1994 if (ret_val) {
1995 hw->phy.ops.release_phy(hw);
1996 goto out;
1997 }
1998 }
1999
2000 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2001 data);
2002
2003 hw->phy.ops.release_phy(hw);
2004
2005out:
2006 return ret_val;
2007}
2008
2009/**
2010 * e1000e_read_phy_reg_bm - Read BM PHY register
2011 * @hw: pointer to the HW structure
2012 * @offset: register offset to be read
2013 * @data: pointer to the read data
2014 *
2015 * Acquires semaphore, if necessary, then reads the PHY register at offset
2016 * and storing the retrieved information in data. Release any acquired
2017 * semaphores before exiting.
2018 **/
2019s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2020{
2021 s32 ret_val;
2022 u32 page_select = 0;
2023 u32 page = offset >> IGP_PAGE_SHIFT;
2024 u32 page_shift = 0;
2025
2026 /* Page 800 works differently than the rest so it has its own func */
2027 if (page == BM_WUC_PAGE) {
2028 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2029 true);
2030 goto out;
2031 }
2032
2033 ret_val = hw->phy.ops.acquire_phy(hw);
2034 if (ret_val)
2035 goto out;
2036
2037 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2038
2039 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2040 /*
2041 * Page select is register 31 for phy address 1 and 22 for
2042 * phy address 2 and 3. Page select is shifted only for
2043 * phy address 1.
2044 */
2045 if (hw->phy.addr == 1) {
2046 page_shift = IGP_PAGE_SHIFT;
2047 page_select = IGP01E1000_PHY_PAGE_SELECT;
2048 } else {
2049 page_shift = 0;
2050 page_select = BM_PHY_PAGE_SELECT;
2051 }
2052
2053 /* Page is shifted left, PHY expects (page x 32) */
2054 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2055 (page << page_shift));
2056 if (ret_val) {
2057 hw->phy.ops.release_phy(hw);
2058 goto out;
2059 }
2060 }
2061
2062 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2063 data);
2064 hw->phy.ops.release_phy(hw);
2065
2066out:
2067 return ret_val;
2068}
2069
4662e82b
BA		 2070/**
2071 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2072 * @hw: pointer to the HW structure
2073 * @offset: register offset to be read
2074 * @data: pointer to the read data
2075 *
2076 * Acquires semaphore, if necessary, then reads the PHY register at offset
2077 * and storing the retrieved information in data. Release any acquired
2078 * semaphores before exiting.
2079 **/
2080s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2081{
2082 s32 ret_val;
2083 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2084
2085 /* Page 800 works differently than the rest so it has its own func */
2086 if (page == BM_WUC_PAGE) {
2087 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2088 true);
2089 return ret_val;
2090 }
2091
2092 ret_val = hw->phy.ops.acquire_phy(hw);
2093 if (ret_val)
2094 return ret_val;
2095
2096 hw->phy.addr = 1;
2097
2098 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2099
2100 /* Page is shifted left, PHY expects (page x 32) */
2101 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2102 page);
2103
2104 if (ret_val) {
2105 hw->phy.ops.release_phy(hw);
2106 return ret_val;
2107 }
2108 }
2109
2110 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2111 data);
2112 hw->phy.ops.release_phy(hw);
2113
2114 return ret_val;
2115}
2116
2117/**
2118 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2119 * @hw: pointer to the HW structure
2120 * @offset: register offset to write to
2121 * @data: data to write at register offset
2122 *
2123 * Acquires semaphore, if necessary, then writes the data to PHY register
2124 * at the offset. Release any acquired semaphores before exiting.
2125 **/
2126s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2127{
2128 s32 ret_val;
2129 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2130
2131 /* Page 800 works differently than the rest so it has its own func */
2132 if (page == BM_WUC_PAGE) {
2133 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2134 false);
2135 return ret_val;
2136 }
2137
2138 ret_val = hw->phy.ops.acquire_phy(hw);
2139 if (ret_val)
2140 return ret_val;
2141
2142 hw->phy.addr = 1;
2143
2144 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2145 /* Page is shifted left, PHY expects (page x 32) */
2146 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2147 page);
2148
2149 if (ret_val) {
2150 hw->phy.ops.release_phy(hw);
2151 return ret_val;
2152 }
2153 }
2154
2155 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2156 data);
2157
2158 hw->phy.ops.release_phy(hw);
2159
2160 return ret_val;
2161}
2162
97ac8cae
BA		 2163/**
2164 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2165 * @hw: pointer to the HW structure
2166 * @offset: register offset to be read or written
2167 * @data: pointer to the data to read or write
2168 * @read: determines if operation is read or write
2169 *
2170 * Acquires semaphore, if necessary, then reads the PHY register at offset
2171 * and storing the retrieved information in data. Release any acquired
2172 * semaphores before exiting. Note that procedure to read the wakeup
2173 * registers are different. It works as such:
2174 * 1) Set page 769, register 17, bit 2 = 1
2175 * 2) Set page to 800 for host (801 if we were manageability)
2176 * 3) Write the address using the address opcode (0x11)
2177 * 4) Read or write the data using the data opcode (0x12)
2178 * 5) Restore 769_17.2 to its original value
2179 **/
2180static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2181 u16 *data, bool read)
2182{
2183 s32 ret_val;
2184 u16 reg = ((u16)offset) & PHY_REG_MASK;
2185 u16 phy_reg = 0;
2186 u8 phy_acquired = 1;
2187
2188
2189 ret_val = hw->phy.ops.acquire_phy(hw);
2190 if (ret_val) {
2191 phy_acquired = 0;
2192 goto out;
2193 }
2194
2195 /* All operations in this function are phy address 1 */
2196 hw->phy.addr = 1;
2197
2198 /* Set page 769 */
2199 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2200 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2201
2202 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2203 if (ret_val)
2204 goto out;
2205
2206 /* First clear bit 4 to avoid a power state change */
2207 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2208 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2209 if (ret_val)
2210 goto out;
2211
2212 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2213 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2214 phy_reg | BM_WUC_ENABLE_BIT);
2215 if (ret_val)
2216 goto out;
2217
2218 /* Select page 800 */
2219 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2220 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2221
2222 /* Write the page 800 offset value using opcode 0x11 */
2223 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2224 if (ret_val)
2225 goto out;
2226
2227 if (read) {
2228 /* Read the page 800 value using opcode 0x12 */
2229 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2230 data);
2231 } else {
2232 /* Read the page 800 value using opcode 0x12 */
2233 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2234 *data);
2235 }
2236
2237 if (ret_val)
2238 goto out;
2239
2240 /*
2241 * Restore 769_17.2 to its original value
2242 * Set page 769
2243 */
2244 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2245 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2246
2247 /* Clear 769_17.2 */
2248 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2249
2250out:
2251 if (phy_acquired == 1)
2252 hw->phy.ops.release_phy(hw);
2253 return ret_val;
2254}
2255
bc7f75fa
AK		 2256/**
2257 * e1000e_commit_phy - Soft PHY reset
2258 * @hw: pointer to the HW structure
2259 *
2260 * Performs a soft PHY reset on those that apply. This is a function pointer
2261 * entry point called by drivers.
2262 **/
2263s32 e1000e_commit_phy(struct e1000_hw *hw)
2264{
2265 if (hw->phy.ops.commit_phy)
2266 return hw->phy.ops.commit_phy(hw);
2267
2268 return 0;
2269}
2270
2271/**
2272 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2273 * @hw: pointer to the HW structure
2274 * @active: boolean used to enable/disable lplu
2275 *
2276 * Success returns 0, Failure returns 1
2277 *
2278 * The low power link up (lplu) state is set to the power management level D0
2279 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2280 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2281 * is used during Dx states where the power conservation is most important.
2282 * During driver activity, SmartSpeed should be enabled so performance is
2283 * maintained. This is a function pointer entry point called by drivers.
2284 **/
2285static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2286{
2287 if (hw->phy.ops.set_d0_lplu_state)
2288 return hw->phy.ops.set_d0_lplu_state(hw, active);
2289
2290 return 0;
2291}
Linux 6.x block layer and io_uring tree(s)