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1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
ad68076e | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82562G-2 10/100 Network Connection | |
31 | * 82562GT 10/100 Network Connection | |
32 | * 82562GT-2 10/100 Network Connection | |
33 | * 82562V 10/100 Network Connection | |
34 | * 82562V-2 10/100 Network Connection | |
35 | * 82566DC-2 Gigabit Network Connection | |
36 | * 82566DC Gigabit Network Connection | |
37 | * 82566DM-2 Gigabit Network Connection | |
38 | * 82566DM Gigabit Network Connection | |
39 | * 82566MC Gigabit Network Connection | |
40 | * 82566MM Gigabit Network Connection | |
41 | */ | |
42 | ||
43 | #include <linux/netdevice.h> | |
44 | #include <linux/ethtool.h> | |
45 | #include <linux/delay.h> | |
46 | #include <linux/pci.h> | |
47 | ||
48 | #include "e1000.h" | |
49 | ||
50 | #define ICH_FLASH_GFPREG 0x0000 | |
51 | #define ICH_FLASH_HSFSTS 0x0004 | |
52 | #define ICH_FLASH_HSFCTL 0x0006 | |
53 | #define ICH_FLASH_FADDR 0x0008 | |
54 | #define ICH_FLASH_FDATA0 0x0010 | |
55 | ||
56 | #define ICH_FLASH_READ_COMMAND_TIMEOUT 500 | |
57 | #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 | |
58 | #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 | |
59 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF | |
60 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 | |
61 | ||
62 | #define ICH_CYCLE_READ 0 | |
63 | #define ICH_CYCLE_WRITE 2 | |
64 | #define ICH_CYCLE_ERASE 3 | |
65 | ||
66 | #define FLASH_GFPREG_BASE_MASK 0x1FFF | |
67 | #define FLASH_SECTOR_ADDR_SHIFT 12 | |
68 | ||
69 | #define ICH_FLASH_SEG_SIZE_256 256 | |
70 | #define ICH_FLASH_SEG_SIZE_4K 4096 | |
71 | #define ICH_FLASH_SEG_SIZE_8K 8192 | |
72 | #define ICH_FLASH_SEG_SIZE_64K 65536 | |
73 | ||
74 | ||
75 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ | |
76 | ||
77 | #define E1000_ICH_MNG_IAMT_MODE 0x2 | |
78 | ||
79 | #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ | |
80 | (ID_LED_DEF1_OFF2 << 8) | \ | |
81 | (ID_LED_DEF1_ON2 << 4) | \ | |
82 | (ID_LED_DEF1_DEF2)) | |
83 | ||
84 | #define E1000_ICH_NVM_SIG_WORD 0x13 | |
85 | #define E1000_ICH_NVM_SIG_MASK 0xC000 | |
86 | ||
87 | #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 | |
88 | ||
89 | #define E1000_FEXTNVM_SW_CONFIG 1 | |
90 | #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ | |
91 | ||
92 | #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL | |
93 | ||
94 | #define E1000_ICH_RAR_ENTRIES 7 | |
95 | ||
96 | #define PHY_PAGE_SHIFT 5 | |
97 | #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ | |
98 | ((reg) & MAX_PHY_REG_ADDRESS)) | |
99 | #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ | |
100 | #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ | |
101 | ||
102 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 | |
103 | #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 | |
104 | #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 | |
105 | ||
106 | /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ | |
107 | /* Offset 04h HSFSTS */ | |
108 | union ich8_hws_flash_status { | |
109 | struct ich8_hsfsts { | |
110 | u16 flcdone :1; /* bit 0 Flash Cycle Done */ | |
111 | u16 flcerr :1; /* bit 1 Flash Cycle Error */ | |
112 | u16 dael :1; /* bit 2 Direct Access error Log */ | |
113 | u16 berasesz :2; /* bit 4:3 Sector Erase Size */ | |
114 | u16 flcinprog :1; /* bit 5 flash cycle in Progress */ | |
115 | u16 reserved1 :2; /* bit 13:6 Reserved */ | |
116 | u16 reserved2 :6; /* bit 13:6 Reserved */ | |
117 | u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ | |
118 | u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ | |
119 | } hsf_status; | |
120 | u16 regval; | |
121 | }; | |
122 | ||
123 | /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ | |
124 | /* Offset 06h FLCTL */ | |
125 | union ich8_hws_flash_ctrl { | |
126 | struct ich8_hsflctl { | |
127 | u16 flcgo :1; /* 0 Flash Cycle Go */ | |
128 | u16 flcycle :2; /* 2:1 Flash Cycle */ | |
129 | u16 reserved :5; /* 7:3 Reserved */ | |
130 | u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ | |
131 | u16 flockdn :6; /* 15:10 Reserved */ | |
132 | } hsf_ctrl; | |
133 | u16 regval; | |
134 | }; | |
135 | ||
136 | /* ICH Flash Region Access Permissions */ | |
137 | union ich8_hws_flash_regacc { | |
138 | struct ich8_flracc { | |
139 | u32 grra :8; /* 0:7 GbE region Read Access */ | |
140 | u32 grwa :8; /* 8:15 GbE region Write Access */ | |
141 | u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ | |
142 | u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ | |
143 | } hsf_flregacc; | |
144 | u16 regval; | |
145 | }; | |
146 | ||
147 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); | |
148 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); | |
149 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); | |
150 | static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw); | |
151 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); | |
152 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
153 | u32 offset, u8 byte); | |
154 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | |
155 | u16 *data); | |
156 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
157 | u8 size, u16 *data); | |
158 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); | |
159 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); | |
160 | ||
161 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) | |
162 | { | |
163 | return readw(hw->flash_address + reg); | |
164 | } | |
165 | ||
166 | static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) | |
167 | { | |
168 | return readl(hw->flash_address + reg); | |
169 | } | |
170 | ||
171 | static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) | |
172 | { | |
173 | writew(val, hw->flash_address + reg); | |
174 | } | |
175 | ||
176 | static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) | |
177 | { | |
178 | writel(val, hw->flash_address + reg); | |
179 | } | |
180 | ||
181 | #define er16flash(reg) __er16flash(hw, (reg)) | |
182 | #define er32flash(reg) __er32flash(hw, (reg)) | |
183 | #define ew16flash(reg,val) __ew16flash(hw, (reg), (val)) | |
184 | #define ew32flash(reg,val) __ew32flash(hw, (reg), (val)) | |
185 | ||
186 | /** | |
187 | * e1000_init_phy_params_ich8lan - Initialize PHY function pointers | |
188 | * @hw: pointer to the HW structure | |
189 | * | |
190 | * Initialize family-specific PHY parameters and function pointers. | |
191 | **/ | |
192 | static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) | |
193 | { | |
194 | struct e1000_phy_info *phy = &hw->phy; | |
195 | s32 ret_val; | |
196 | u16 i = 0; | |
197 | ||
198 | phy->addr = 1; | |
199 | phy->reset_delay_us = 100; | |
200 | ||
201 | phy->id = 0; | |
202 | while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && | |
203 | (i++ < 100)) { | |
204 | msleep(1); | |
205 | ret_val = e1000e_get_phy_id(hw); | |
206 | if (ret_val) | |
207 | return ret_val; | |
208 | } | |
209 | ||
210 | /* Verify phy id */ | |
211 | switch (phy->id) { | |
212 | case IGP03E1000_E_PHY_ID: | |
213 | phy->type = e1000_phy_igp_3; | |
214 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
215 | break; | |
216 | case IFE_E_PHY_ID: | |
217 | case IFE_PLUS_E_PHY_ID: | |
218 | case IFE_C_E_PHY_ID: | |
219 | phy->type = e1000_phy_ife; | |
220 | phy->autoneg_mask = E1000_ALL_NOT_GIG; | |
221 | break; | |
222 | default: | |
223 | return -E1000_ERR_PHY; | |
224 | break; | |
225 | } | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
230 | /** | |
231 | * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers | |
232 | * @hw: pointer to the HW structure | |
233 | * | |
234 | * Initialize family-specific NVM parameters and function | |
235 | * pointers. | |
236 | **/ | |
237 | static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) | |
238 | { | |
239 | struct e1000_nvm_info *nvm = &hw->nvm; | |
240 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
241 | u32 gfpreg; | |
242 | u32 sector_base_addr; | |
243 | u32 sector_end_addr; | |
244 | u16 i; | |
245 | ||
ad68076e | 246 | /* Can't read flash registers if the register set isn't mapped. */ |
bc7f75fa AK |
247 | if (!hw->flash_address) { |
248 | hw_dbg(hw, "ERROR: Flash registers not mapped\n"); | |
249 | return -E1000_ERR_CONFIG; | |
250 | } | |
251 | ||
252 | nvm->type = e1000_nvm_flash_sw; | |
253 | ||
254 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
255 | ||
ad68076e BA |
256 | /* |
257 | * sector_X_addr is a "sector"-aligned address (4096 bytes) | |
bc7f75fa | 258 | * Add 1 to sector_end_addr since this sector is included in |
ad68076e BA |
259 | * the overall size. |
260 | */ | |
bc7f75fa AK |
261 | sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; |
262 | sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; | |
263 | ||
264 | /* flash_base_addr is byte-aligned */ | |
265 | nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; | |
266 | ||
ad68076e BA |
267 | /* |
268 | * find total size of the NVM, then cut in half since the total | |
269 | * size represents two separate NVM banks. | |
270 | */ | |
bc7f75fa AK |
271 | nvm->flash_bank_size = (sector_end_addr - sector_base_addr) |
272 | << FLASH_SECTOR_ADDR_SHIFT; | |
273 | nvm->flash_bank_size /= 2; | |
274 | /* Adjust to word count */ | |
275 | nvm->flash_bank_size /= sizeof(u16); | |
276 | ||
277 | nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; | |
278 | ||
279 | /* Clear shadow ram */ | |
280 | for (i = 0; i < nvm->word_size; i++) { | |
281 | dev_spec->shadow_ram[i].modified = 0; | |
282 | dev_spec->shadow_ram[i].value = 0xFFFF; | |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
288 | /** | |
289 | * e1000_init_mac_params_ich8lan - Initialize MAC function pointers | |
290 | * @hw: pointer to the HW structure | |
291 | * | |
292 | * Initialize family-specific MAC parameters and function | |
293 | * pointers. | |
294 | **/ | |
295 | static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter) | |
296 | { | |
297 | struct e1000_hw *hw = &adapter->hw; | |
298 | struct e1000_mac_info *mac = &hw->mac; | |
299 | ||
300 | /* Set media type function pointer */ | |
318a94d6 | 301 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
302 | |
303 | /* Set mta register count */ | |
304 | mac->mta_reg_count = 32; | |
305 | /* Set rar entry count */ | |
306 | mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; | |
307 | if (mac->type == e1000_ich8lan) | |
308 | mac->rar_entry_count--; | |
309 | /* Set if manageability features are enabled. */ | |
310 | mac->arc_subsystem_valid = 1; | |
311 | ||
312 | /* Enable PCS Lock-loss workaround for ICH8 */ | |
313 | if (mac->type == e1000_ich8lan) | |
314 | e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1); | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
319 | static s32 e1000_get_invariants_ich8lan(struct e1000_adapter *adapter) | |
320 | { | |
321 | struct e1000_hw *hw = &adapter->hw; | |
322 | s32 rc; | |
323 | ||
324 | rc = e1000_init_mac_params_ich8lan(adapter); | |
325 | if (rc) | |
326 | return rc; | |
327 | ||
328 | rc = e1000_init_nvm_params_ich8lan(hw); | |
329 | if (rc) | |
330 | return rc; | |
331 | ||
332 | rc = e1000_init_phy_params_ich8lan(hw); | |
333 | if (rc) | |
334 | return rc; | |
335 | ||
336 | if ((adapter->hw.mac.type == e1000_ich8lan) && | |
337 | (adapter->hw.phy.type == e1000_phy_igp_3)) | |
338 | adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
343 | /** | |
344 | * e1000_acquire_swflag_ich8lan - Acquire software control flag | |
345 | * @hw: pointer to the HW structure | |
346 | * | |
347 | * Acquires the software control flag for performing NVM and PHY | |
348 | * operations. This is a function pointer entry point only called by | |
349 | * read/write routines for the PHY and NVM parts. | |
350 | **/ | |
351 | static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |
352 | { | |
353 | u32 extcnf_ctrl; | |
354 | u32 timeout = PHY_CFG_TIMEOUT; | |
355 | ||
356 | while (timeout) { | |
357 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
358 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; | |
359 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
360 | ||
361 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
362 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) | |
363 | break; | |
364 | mdelay(1); | |
365 | timeout--; | |
366 | } | |
367 | ||
368 | if (!timeout) { | |
369 | hw_dbg(hw, "FW or HW has locked the resource for too long.\n"); | |
370 | return -E1000_ERR_CONFIG; | |
371 | } | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
376 | /** | |
377 | * e1000_release_swflag_ich8lan - Release software control flag | |
378 | * @hw: pointer to the HW structure | |
379 | * | |
380 | * Releases the software control flag for performing NVM and PHY operations. | |
381 | * This is a function pointer entry point only called by read/write | |
382 | * routines for the PHY and NVM parts. | |
383 | **/ | |
384 | static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) | |
385 | { | |
386 | u32 extcnf_ctrl; | |
387 | ||
388 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
389 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | |
390 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
391 | } | |
392 | ||
393 | /** | |
394 | * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked | |
395 | * @hw: pointer to the HW structure | |
396 | * | |
397 | * Checks if firmware is blocking the reset of the PHY. | |
398 | * This is a function pointer entry point only called by | |
399 | * reset routines. | |
400 | **/ | |
401 | static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) | |
402 | { | |
403 | u32 fwsm; | |
404 | ||
405 | fwsm = er32(FWSM); | |
406 | ||
407 | return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; | |
408 | } | |
409 | ||
410 | /** | |
411 | * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex | |
412 | * @hw: pointer to the HW structure | |
413 | * | |
414 | * Forces the speed and duplex settings of the PHY. | |
415 | * This is a function pointer entry point only called by | |
416 | * PHY setup routines. | |
417 | **/ | |
418 | static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw) | |
419 | { | |
420 | struct e1000_phy_info *phy = &hw->phy; | |
421 | s32 ret_val; | |
422 | u16 data; | |
423 | bool link; | |
424 | ||
425 | if (phy->type != e1000_phy_ife) { | |
426 | ret_val = e1000e_phy_force_speed_duplex_igp(hw); | |
427 | return ret_val; | |
428 | } | |
429 | ||
430 | ret_val = e1e_rphy(hw, PHY_CONTROL, &data); | |
431 | if (ret_val) | |
432 | return ret_val; | |
433 | ||
434 | e1000e_phy_force_speed_duplex_setup(hw, &data); | |
435 | ||
436 | ret_val = e1e_wphy(hw, PHY_CONTROL, data); | |
437 | if (ret_val) | |
438 | return ret_val; | |
439 | ||
440 | /* Disable MDI-X support for 10/100 */ | |
441 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
442 | if (ret_val) | |
443 | return ret_val; | |
444 | ||
445 | data &= ~IFE_PMC_AUTO_MDIX; | |
446 | data &= ~IFE_PMC_FORCE_MDIX; | |
447 | ||
448 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); | |
449 | if (ret_val) | |
450 | return ret_val; | |
451 | ||
452 | hw_dbg(hw, "IFE PMC: %X\n", data); | |
453 | ||
454 | udelay(1); | |
455 | ||
318a94d6 | 456 | if (phy->autoneg_wait_to_complete) { |
bc7f75fa AK |
457 | hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n"); |
458 | ||
459 | ret_val = e1000e_phy_has_link_generic(hw, | |
460 | PHY_FORCE_LIMIT, | |
461 | 100000, | |
462 | &link); | |
463 | if (ret_val) | |
464 | return ret_val; | |
465 | ||
466 | if (!link) | |
467 | hw_dbg(hw, "Link taking longer than expected.\n"); | |
468 | ||
469 | /* Try once more */ | |
470 | ret_val = e1000e_phy_has_link_generic(hw, | |
471 | PHY_FORCE_LIMIT, | |
472 | 100000, | |
473 | &link); | |
474 | if (ret_val) | |
475 | return ret_val; | |
476 | } | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
481 | /** | |
482 | * e1000_phy_hw_reset_ich8lan - Performs a PHY reset | |
483 | * @hw: pointer to the HW structure | |
484 | * | |
485 | * Resets the PHY | |
486 | * This is a function pointer entry point called by drivers | |
487 | * or other shared routines. | |
488 | **/ | |
489 | static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |
490 | { | |
491 | struct e1000_phy_info *phy = &hw->phy; | |
492 | u32 i; | |
493 | u32 data, cnf_size, cnf_base_addr, sw_cfg_mask; | |
494 | s32 ret_val; | |
495 | u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT; | |
496 | u16 word_addr, reg_data, reg_addr, phy_page = 0; | |
497 | ||
498 | ret_val = e1000e_phy_hw_reset_generic(hw); | |
499 | if (ret_val) | |
500 | return ret_val; | |
501 | ||
ad68076e BA |
502 | /* |
503 | * Initialize the PHY from the NVM on ICH platforms. This | |
bc7f75fa AK |
504 | * is needed due to an issue where the NVM configuration is |
505 | * not properly autoloaded after power transitions. | |
506 | * Therefore, after each PHY reset, we will load the | |
507 | * configuration data out of the NVM manually. | |
508 | */ | |
509 | if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) { | |
510 | struct e1000_adapter *adapter = hw->adapter; | |
511 | ||
512 | /* Check if SW needs configure the PHY */ | |
513 | if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) || | |
514 | (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M)) | |
515 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; | |
516 | else | |
517 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; | |
518 | ||
519 | data = er32(FEXTNVM); | |
520 | if (!(data & sw_cfg_mask)) | |
521 | return 0; | |
522 | ||
523 | /* Wait for basic configuration completes before proceeding*/ | |
524 | do { | |
525 | data = er32(STATUS); | |
526 | data &= E1000_STATUS_LAN_INIT_DONE; | |
527 | udelay(100); | |
528 | } while ((!data) && --loop); | |
529 | ||
ad68076e BA |
530 | /* |
531 | * If basic configuration is incomplete before the above loop | |
bc7f75fa AK |
532 | * count reaches 0, loading the configuration from NVM will |
533 | * leave the PHY in a bad state possibly resulting in no link. | |
534 | */ | |
535 | if (loop == 0) { | |
536 | hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n"); | |
537 | } | |
538 | ||
539 | /* Clear the Init Done bit for the next init event */ | |
540 | data = er32(STATUS); | |
541 | data &= ~E1000_STATUS_LAN_INIT_DONE; | |
542 | ew32(STATUS, data); | |
543 | ||
ad68076e BA |
544 | /* |
545 | * Make sure HW does not configure LCD from PHY | |
546 | * extended configuration before SW configuration | |
547 | */ | |
bc7f75fa AK |
548 | data = er32(EXTCNF_CTRL); |
549 | if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) | |
550 | return 0; | |
551 | ||
552 | cnf_size = er32(EXTCNF_SIZE); | |
553 | cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; | |
554 | cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; | |
555 | if (!cnf_size) | |
556 | return 0; | |
557 | ||
558 | cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; | |
559 | cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; | |
560 | ||
ad68076e | 561 | /* Configure LCD from extended configuration region. */ |
bc7f75fa AK |
562 | |
563 | /* cnf_base_addr is in DWORD */ | |
564 | word_addr = (u16)(cnf_base_addr << 1); | |
565 | ||
566 | for (i = 0; i < cnf_size; i++) { | |
567 | ret_val = e1000_read_nvm(hw, | |
568 | (word_addr + i * 2), | |
569 | 1, | |
570 | ®_data); | |
571 | if (ret_val) | |
572 | return ret_val; | |
573 | ||
574 | ret_val = e1000_read_nvm(hw, | |
575 | (word_addr + i * 2 + 1), | |
576 | 1, | |
577 | ®_addr); | |
578 | if (ret_val) | |
579 | return ret_val; | |
580 | ||
581 | /* Save off the PHY page for future writes. */ | |
582 | if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { | |
583 | phy_page = reg_data; | |
584 | continue; | |
585 | } | |
586 | ||
587 | reg_addr |= phy_page; | |
588 | ||
589 | ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data); | |
590 | if (ret_val) | |
591 | return ret_val; | |
592 | } | |
593 | } | |
594 | ||
595 | return 0; | |
596 | } | |
597 | ||
598 | /** | |
599 | * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states | |
600 | * @hw: pointer to the HW structure | |
601 | * | |
602 | * Populates "phy" structure with various feature states. | |
603 | * This function is only called by other family-specific | |
604 | * routines. | |
605 | **/ | |
606 | static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw) | |
607 | { | |
608 | struct e1000_phy_info *phy = &hw->phy; | |
609 | s32 ret_val; | |
610 | u16 data; | |
611 | bool link; | |
612 | ||
613 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
614 | if (ret_val) | |
615 | return ret_val; | |
616 | ||
617 | if (!link) { | |
618 | hw_dbg(hw, "Phy info is only valid if link is up\n"); | |
619 | return -E1000_ERR_CONFIG; | |
620 | } | |
621 | ||
622 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); | |
623 | if (ret_val) | |
624 | return ret_val; | |
625 | phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE)); | |
626 | ||
627 | if (phy->polarity_correction) { | |
628 | ret_val = e1000_check_polarity_ife_ich8lan(hw); | |
629 | if (ret_val) | |
630 | return ret_val; | |
631 | } else { | |
632 | /* Polarity is forced */ | |
633 | phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) | |
634 | ? e1000_rev_polarity_reversed | |
635 | : e1000_rev_polarity_normal; | |
636 | } | |
637 | ||
638 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
639 | if (ret_val) | |
640 | return ret_val; | |
641 | ||
642 | phy->is_mdix = (data & IFE_PMC_MDIX_STATUS); | |
643 | ||
644 | /* The following parameters are undefined for 10/100 operation. */ | |
645 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
646 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
647 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
648 | ||
649 | return 0; | |
650 | } | |
651 | ||
652 | /** | |
653 | * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info | |
654 | * @hw: pointer to the HW structure | |
655 | * | |
656 | * Wrapper for calling the get_phy_info routines for the appropriate phy type. | |
657 | * This is a function pointer entry point called by drivers | |
658 | * or other shared routines. | |
659 | **/ | |
660 | static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) | |
661 | { | |
662 | switch (hw->phy.type) { | |
663 | case e1000_phy_ife: | |
664 | return e1000_get_phy_info_ife_ich8lan(hw); | |
665 | break; | |
666 | case e1000_phy_igp_3: | |
667 | return e1000e_get_phy_info_igp(hw); | |
668 | break; | |
669 | default: | |
670 | break; | |
671 | } | |
672 | ||
673 | return -E1000_ERR_PHY_TYPE; | |
674 | } | |
675 | ||
676 | /** | |
677 | * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY | |
678 | * @hw: pointer to the HW structure | |
679 | * | |
489815ce | 680 | * Polarity is determined on the polarity reversal feature being enabled. |
bc7f75fa AK |
681 | * This function is only called by other family-specific |
682 | * routines. | |
683 | **/ | |
684 | static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw) | |
685 | { | |
686 | struct e1000_phy_info *phy = &hw->phy; | |
687 | s32 ret_val; | |
688 | u16 phy_data, offset, mask; | |
689 | ||
ad68076e BA |
690 | /* |
691 | * Polarity is determined based on the reversal feature being enabled. | |
bc7f75fa AK |
692 | */ |
693 | if (phy->polarity_correction) { | |
694 | offset = IFE_PHY_EXTENDED_STATUS_CONTROL; | |
695 | mask = IFE_PESC_POLARITY_REVERSED; | |
696 | } else { | |
697 | offset = IFE_PHY_SPECIAL_CONTROL; | |
698 | mask = IFE_PSC_FORCE_POLARITY; | |
699 | } | |
700 | ||
701 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
702 | ||
703 | if (!ret_val) | |
704 | phy->cable_polarity = (phy_data & mask) | |
705 | ? e1000_rev_polarity_reversed | |
706 | : e1000_rev_polarity_normal; | |
707 | ||
708 | return ret_val; | |
709 | } | |
710 | ||
711 | /** | |
712 | * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state | |
713 | * @hw: pointer to the HW structure | |
714 | * @active: TRUE to enable LPLU, FALSE to disable | |
715 | * | |
716 | * Sets the LPLU D0 state according to the active flag. When | |
717 | * activating LPLU this function also disables smart speed | |
718 | * and vice versa. LPLU will not be activated unless the | |
719 | * device autonegotiation advertisement meets standards of | |
720 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
721 | * This is a function pointer entry point only called by | |
722 | * PHY setup routines. | |
723 | **/ | |
724 | static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
725 | { | |
726 | struct e1000_phy_info *phy = &hw->phy; | |
727 | u32 phy_ctrl; | |
728 | s32 ret_val = 0; | |
729 | u16 data; | |
730 | ||
731 | if (phy->type != e1000_phy_igp_3) | |
732 | return ret_val; | |
733 | ||
734 | phy_ctrl = er32(PHY_CTRL); | |
735 | ||
736 | if (active) { | |
737 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
738 | ew32(PHY_CTRL, phy_ctrl); | |
739 | ||
ad68076e BA |
740 | /* |
741 | * Call gig speed drop workaround on LPLU before accessing | |
742 | * any PHY registers | |
743 | */ | |
bc7f75fa AK |
744 | if ((hw->mac.type == e1000_ich8lan) && |
745 | (hw->phy.type == e1000_phy_igp_3)) | |
746 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
747 | ||
748 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
749 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
750 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
751 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
752 | if (ret_val) | |
753 | return ret_val; | |
754 | } else { | |
755 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
756 | ew32(PHY_CTRL, phy_ctrl); | |
757 | ||
ad68076e BA |
758 | /* |
759 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
760 | * during Dx states where the power conservation is most |
761 | * important. During driver activity we should enable | |
ad68076e BA |
762 | * SmartSpeed, so performance is maintained. |
763 | */ | |
bc7f75fa AK |
764 | if (phy->smart_speed == e1000_smart_speed_on) { |
765 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 766 | &data); |
bc7f75fa AK |
767 | if (ret_val) |
768 | return ret_val; | |
769 | ||
770 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
771 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 772 | data); |
bc7f75fa AK |
773 | if (ret_val) |
774 | return ret_val; | |
775 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
776 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 777 | &data); |
bc7f75fa AK |
778 | if (ret_val) |
779 | return ret_val; | |
780 | ||
781 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
782 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 783 | data); |
bc7f75fa AK |
784 | if (ret_val) |
785 | return ret_val; | |
786 | } | |
787 | } | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
792 | /** | |
793 | * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state | |
794 | * @hw: pointer to the HW structure | |
795 | * @active: TRUE to enable LPLU, FALSE to disable | |
796 | * | |
797 | * Sets the LPLU D3 state according to the active flag. When | |
798 | * activating LPLU this function also disables smart speed | |
799 | * and vice versa. LPLU will not be activated unless the | |
800 | * device autonegotiation advertisement meets standards of | |
801 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
802 | * This is a function pointer entry point only called by | |
803 | * PHY setup routines. | |
804 | **/ | |
805 | static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
806 | { | |
807 | struct e1000_phy_info *phy = &hw->phy; | |
808 | u32 phy_ctrl; | |
809 | s32 ret_val; | |
810 | u16 data; | |
811 | ||
812 | phy_ctrl = er32(PHY_CTRL); | |
813 | ||
814 | if (!active) { | |
815 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
816 | ew32(PHY_CTRL, phy_ctrl); | |
ad68076e BA |
817 | /* |
818 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
819 | * during Dx states where the power conservation is most |
820 | * important. During driver activity we should enable | |
ad68076e BA |
821 | * SmartSpeed, so performance is maintained. |
822 | */ | |
bc7f75fa | 823 | if (phy->smart_speed == e1000_smart_speed_on) { |
ad68076e BA |
824 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
825 | &data); | |
bc7f75fa AK |
826 | if (ret_val) |
827 | return ret_val; | |
828 | ||
829 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e BA |
830 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
831 | data); | |
bc7f75fa AK |
832 | if (ret_val) |
833 | return ret_val; | |
834 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
ad68076e BA |
835 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
836 | &data); | |
bc7f75fa AK |
837 | if (ret_val) |
838 | return ret_val; | |
839 | ||
840 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e BA |
841 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
842 | data); | |
bc7f75fa AK |
843 | if (ret_val) |
844 | return ret_val; | |
845 | } | |
846 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
847 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
848 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
849 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | |
850 | ew32(PHY_CTRL, phy_ctrl); | |
851 | ||
ad68076e BA |
852 | /* |
853 | * Call gig speed drop workaround on LPLU before accessing | |
854 | * any PHY registers | |
855 | */ | |
bc7f75fa AK |
856 | if ((hw->mac.type == e1000_ich8lan) && |
857 | (hw->phy.type == e1000_phy_igp_3)) | |
858 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
859 | ||
860 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
ad68076e | 861 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
bc7f75fa AK |
862 | if (ret_val) |
863 | return ret_val; | |
864 | ||
865 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e | 866 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
bc7f75fa AK |
867 | } |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
872 | /** | |
873 | * e1000_read_nvm_ich8lan - Read word(s) from the NVM | |
874 | * @hw: pointer to the HW structure | |
875 | * @offset: The offset (in bytes) of the word(s) to read. | |
876 | * @words: Size of data to read in words | |
877 | * @data: Pointer to the word(s) to read at offset. | |
878 | * | |
879 | * Reads a word(s) from the NVM using the flash access registers. | |
880 | **/ | |
881 | static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
882 | u16 *data) | |
883 | { | |
884 | struct e1000_nvm_info *nvm = &hw->nvm; | |
885 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
886 | u32 act_offset; | |
887 | s32 ret_val; | |
888 | u16 i, word; | |
889 | ||
890 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
891 | (words == 0)) { | |
892 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
893 | return -E1000_ERR_NVM; | |
894 | } | |
895 | ||
896 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
897 | if (ret_val) | |
898 | return ret_val; | |
899 | ||
900 | /* Start with the bank offset, then add the relative offset. */ | |
901 | act_offset = (er32(EECD) & E1000_EECD_SEC1VAL) | |
902 | ? nvm->flash_bank_size | |
903 | : 0; | |
904 | act_offset += offset; | |
905 | ||
906 | for (i = 0; i < words; i++) { | |
907 | if ((dev_spec->shadow_ram) && | |
908 | (dev_spec->shadow_ram[offset+i].modified)) { | |
909 | data[i] = dev_spec->shadow_ram[offset+i].value; | |
910 | } else { | |
911 | ret_val = e1000_read_flash_word_ich8lan(hw, | |
912 | act_offset + i, | |
913 | &word); | |
914 | if (ret_val) | |
915 | break; | |
916 | data[i] = word; | |
917 | } | |
918 | } | |
919 | ||
920 | e1000_release_swflag_ich8lan(hw); | |
921 | ||
922 | return ret_val; | |
923 | } | |
924 | ||
925 | /** | |
926 | * e1000_flash_cycle_init_ich8lan - Initialize flash | |
927 | * @hw: pointer to the HW structure | |
928 | * | |
929 | * This function does initial flash setup so that a new read/write/erase cycle | |
930 | * can be started. | |
931 | **/ | |
932 | static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) | |
933 | { | |
934 | union ich8_hws_flash_status hsfsts; | |
935 | s32 ret_val = -E1000_ERR_NVM; | |
936 | s32 i = 0; | |
937 | ||
938 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
939 | ||
940 | /* Check if the flash descriptor is valid */ | |
941 | if (hsfsts.hsf_status.fldesvalid == 0) { | |
942 | hw_dbg(hw, "Flash descriptor invalid. " | |
943 | "SW Sequencing must be used."); | |
944 | return -E1000_ERR_NVM; | |
945 | } | |
946 | ||
947 | /* Clear FCERR and DAEL in hw status by writing 1 */ | |
948 | hsfsts.hsf_status.flcerr = 1; | |
949 | hsfsts.hsf_status.dael = 1; | |
950 | ||
951 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
952 | ||
ad68076e BA |
953 | /* |
954 | * Either we should have a hardware SPI cycle in progress | |
bc7f75fa AK |
955 | * bit to check against, in order to start a new cycle or |
956 | * FDONE bit should be changed in the hardware so that it | |
489815ce | 957 | * is 1 after hardware reset, which can then be used as an |
bc7f75fa AK |
958 | * indication whether a cycle is in progress or has been |
959 | * completed. | |
960 | */ | |
961 | ||
962 | if (hsfsts.hsf_status.flcinprog == 0) { | |
ad68076e BA |
963 | /* |
964 | * There is no cycle running at present, | |
965 | * so we can start a cycle | |
966 | * Begin by setting Flash Cycle Done. | |
967 | */ | |
bc7f75fa AK |
968 | hsfsts.hsf_status.flcdone = 1; |
969 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
970 | ret_val = 0; | |
971 | } else { | |
ad68076e BA |
972 | /* |
973 | * otherwise poll for sometime so the current | |
974 | * cycle has a chance to end before giving up. | |
975 | */ | |
bc7f75fa AK |
976 | for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { |
977 | hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS); | |
978 | if (hsfsts.hsf_status.flcinprog == 0) { | |
979 | ret_val = 0; | |
980 | break; | |
981 | } | |
982 | udelay(1); | |
983 | } | |
984 | if (ret_val == 0) { | |
ad68076e BA |
985 | /* |
986 | * Successful in waiting for previous cycle to timeout, | |
987 | * now set the Flash Cycle Done. | |
988 | */ | |
bc7f75fa AK |
989 | hsfsts.hsf_status.flcdone = 1; |
990 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
991 | } else { | |
992 | hw_dbg(hw, "Flash controller busy, cannot get access"); | |
993 | } | |
994 | } | |
995 | ||
996 | return ret_val; | |
997 | } | |
998 | ||
999 | /** | |
1000 | * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) | |
1001 | * @hw: pointer to the HW structure | |
1002 | * @timeout: maximum time to wait for completion | |
1003 | * | |
1004 | * This function starts a flash cycle and waits for its completion. | |
1005 | **/ | |
1006 | static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) | |
1007 | { | |
1008 | union ich8_hws_flash_ctrl hsflctl; | |
1009 | union ich8_hws_flash_status hsfsts; | |
1010 | s32 ret_val = -E1000_ERR_NVM; | |
1011 | u32 i = 0; | |
1012 | ||
1013 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ | |
1014 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1015 | hsflctl.hsf_ctrl.flcgo = 1; | |
1016 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1017 | ||
1018 | /* wait till FDONE bit is set to 1 */ | |
1019 | do { | |
1020 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1021 | if (hsfsts.hsf_status.flcdone == 1) | |
1022 | break; | |
1023 | udelay(1); | |
1024 | } while (i++ < timeout); | |
1025 | ||
1026 | if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) | |
1027 | return 0; | |
1028 | ||
1029 | return ret_val; | |
1030 | } | |
1031 | ||
1032 | /** | |
1033 | * e1000_read_flash_word_ich8lan - Read word from flash | |
1034 | * @hw: pointer to the HW structure | |
1035 | * @offset: offset to data location | |
1036 | * @data: pointer to the location for storing the data | |
1037 | * | |
1038 | * Reads the flash word at offset into data. Offset is converted | |
1039 | * to bytes before read. | |
1040 | **/ | |
1041 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | |
1042 | u16 *data) | |
1043 | { | |
1044 | /* Must convert offset into bytes. */ | |
1045 | offset <<= 1; | |
1046 | ||
1047 | return e1000_read_flash_data_ich8lan(hw, offset, 2, data); | |
1048 | } | |
1049 | ||
1050 | /** | |
1051 | * e1000_read_flash_data_ich8lan - Read byte or word from NVM | |
1052 | * @hw: pointer to the HW structure | |
1053 | * @offset: The offset (in bytes) of the byte or word to read. | |
1054 | * @size: Size of data to read, 1=byte 2=word | |
1055 | * @data: Pointer to the word to store the value read. | |
1056 | * | |
1057 | * Reads a byte or word from the NVM using the flash access registers. | |
1058 | **/ | |
1059 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
1060 | u8 size, u16 *data) | |
1061 | { | |
1062 | union ich8_hws_flash_status hsfsts; | |
1063 | union ich8_hws_flash_ctrl hsflctl; | |
1064 | u32 flash_linear_addr; | |
1065 | u32 flash_data = 0; | |
1066 | s32 ret_val = -E1000_ERR_NVM; | |
1067 | u8 count = 0; | |
1068 | ||
1069 | if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
1070 | return -E1000_ERR_NVM; | |
1071 | ||
1072 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
1073 | hw->nvm.flash_base_addr; | |
1074 | ||
1075 | do { | |
1076 | udelay(1); | |
1077 | /* Steps */ | |
1078 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1079 | if (ret_val != 0) | |
1080 | break; | |
1081 | ||
1082 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1083 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
1084 | hsflctl.hsf_ctrl.fldbcount = size - 1; | |
1085 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; | |
1086 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1087 | ||
1088 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1089 | ||
1090 | ret_val = e1000_flash_cycle_ich8lan(hw, | |
1091 | ICH_FLASH_READ_COMMAND_TIMEOUT); | |
1092 | ||
ad68076e BA |
1093 | /* |
1094 | * Check if FCERR is set to 1, if set to 1, clear it | |
bc7f75fa AK |
1095 | * and try the whole sequence a few more times, else |
1096 | * read in (shift in) the Flash Data0, the order is | |
ad68076e BA |
1097 | * least significant byte first msb to lsb |
1098 | */ | |
bc7f75fa AK |
1099 | if (ret_val == 0) { |
1100 | flash_data = er32flash(ICH_FLASH_FDATA0); | |
1101 | if (size == 1) { | |
1102 | *data = (u8)(flash_data & 0x000000FF); | |
1103 | } else if (size == 2) { | |
1104 | *data = (u16)(flash_data & 0x0000FFFF); | |
1105 | } | |
1106 | break; | |
1107 | } else { | |
ad68076e BA |
1108 | /* |
1109 | * If we've gotten here, then things are probably | |
bc7f75fa AK |
1110 | * completely hosed, but if the error condition is |
1111 | * detected, it won't hurt to give it another try... | |
1112 | * ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
1113 | */ | |
1114 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1115 | if (hsfsts.hsf_status.flcerr == 1) { | |
1116 | /* Repeat for some time before giving up. */ | |
1117 | continue; | |
1118 | } else if (hsfsts.hsf_status.flcdone == 0) { | |
1119 | hw_dbg(hw, "Timeout error - flash cycle " | |
1120 | "did not complete."); | |
1121 | break; | |
1122 | } | |
1123 | } | |
1124 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1125 | ||
1126 | return ret_val; | |
1127 | } | |
1128 | ||
1129 | /** | |
1130 | * e1000_write_nvm_ich8lan - Write word(s) to the NVM | |
1131 | * @hw: pointer to the HW structure | |
1132 | * @offset: The offset (in bytes) of the word(s) to write. | |
1133 | * @words: Size of data to write in words | |
1134 | * @data: Pointer to the word(s) to write at offset. | |
1135 | * | |
1136 | * Writes a byte or word to the NVM using the flash access registers. | |
1137 | **/ | |
1138 | static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
1139 | u16 *data) | |
1140 | { | |
1141 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1142 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
1143 | s32 ret_val; | |
1144 | u16 i; | |
1145 | ||
1146 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
1147 | (words == 0)) { | |
1148 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
1149 | return -E1000_ERR_NVM; | |
1150 | } | |
1151 | ||
1152 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1153 | if (ret_val) | |
1154 | return ret_val; | |
1155 | ||
1156 | for (i = 0; i < words; i++) { | |
1157 | dev_spec->shadow_ram[offset+i].modified = 1; | |
1158 | dev_spec->shadow_ram[offset+i].value = data[i]; | |
1159 | } | |
1160 | ||
1161 | e1000_release_swflag_ich8lan(hw); | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | /** | |
1167 | * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM | |
1168 | * @hw: pointer to the HW structure | |
1169 | * | |
1170 | * The NVM checksum is updated by calling the generic update_nvm_checksum, | |
1171 | * which writes the checksum to the shadow ram. The changes in the shadow | |
1172 | * ram are then committed to the EEPROM by processing each bank at a time | |
1173 | * checking for the modified bit and writing only the pending changes. | |
489815ce | 1174 | * After a successful commit, the shadow ram is cleared and is ready for |
bc7f75fa AK |
1175 | * future writes. |
1176 | **/ | |
1177 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
1178 | { | |
1179 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1180 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
1181 | u32 i, act_offset, new_bank_offset, old_bank_offset; | |
1182 | s32 ret_val; | |
1183 | u16 data; | |
1184 | ||
1185 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
1186 | if (ret_val) | |
ad68076e | 1187 | return ret_val; |
bc7f75fa AK |
1188 | |
1189 | if (nvm->type != e1000_nvm_flash_sw) | |
ad68076e | 1190 | return ret_val; |
bc7f75fa AK |
1191 | |
1192 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1193 | if (ret_val) | |
ad68076e | 1194 | return ret_val; |
bc7f75fa | 1195 | |
ad68076e BA |
1196 | /* |
1197 | * We're writing to the opposite bank so if we're on bank 1, | |
bc7f75fa | 1198 | * write to bank 0 etc. We also need to erase the segment that |
ad68076e BA |
1199 | * is going to be written |
1200 | */ | |
bc7f75fa AK |
1201 | if (!(er32(EECD) & E1000_EECD_SEC1VAL)) { |
1202 | new_bank_offset = nvm->flash_bank_size; | |
1203 | old_bank_offset = 0; | |
1204 | e1000_erase_flash_bank_ich8lan(hw, 1); | |
1205 | } else { | |
1206 | old_bank_offset = nvm->flash_bank_size; | |
1207 | new_bank_offset = 0; | |
1208 | e1000_erase_flash_bank_ich8lan(hw, 0); | |
1209 | } | |
1210 | ||
1211 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
ad68076e BA |
1212 | /* |
1213 | * Determine whether to write the value stored | |
bc7f75fa | 1214 | * in the other NVM bank or a modified value stored |
ad68076e BA |
1215 | * in the shadow RAM |
1216 | */ | |
bc7f75fa AK |
1217 | if (dev_spec->shadow_ram[i].modified) { |
1218 | data = dev_spec->shadow_ram[i].value; | |
1219 | } else { | |
1220 | e1000_read_flash_word_ich8lan(hw, | |
1221 | i + old_bank_offset, | |
1222 | &data); | |
1223 | } | |
1224 | ||
ad68076e BA |
1225 | /* |
1226 | * If the word is 0x13, then make sure the signature bits | |
bc7f75fa AK |
1227 | * (15:14) are 11b until the commit has completed. |
1228 | * This will allow us to write 10b which indicates the | |
1229 | * signature is valid. We want to do this after the write | |
1230 | * has completed so that we don't mark the segment valid | |
ad68076e BA |
1231 | * while the write is still in progress |
1232 | */ | |
bc7f75fa AK |
1233 | if (i == E1000_ICH_NVM_SIG_WORD) |
1234 | data |= E1000_ICH_NVM_SIG_MASK; | |
1235 | ||
1236 | /* Convert offset to bytes. */ | |
1237 | act_offset = (i + new_bank_offset) << 1; | |
1238 | ||
1239 | udelay(100); | |
1240 | /* Write the bytes to the new bank. */ | |
1241 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1242 | act_offset, | |
1243 | (u8)data); | |
1244 | if (ret_val) | |
1245 | break; | |
1246 | ||
1247 | udelay(100); | |
1248 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1249 | act_offset + 1, | |
1250 | (u8)(data >> 8)); | |
1251 | if (ret_val) | |
1252 | break; | |
1253 | } | |
1254 | ||
ad68076e BA |
1255 | /* |
1256 | * Don't bother writing the segment valid bits if sector | |
1257 | * programming failed. | |
1258 | */ | |
bc7f75fa AK |
1259 | if (ret_val) { |
1260 | hw_dbg(hw, "Flash commit failed.\n"); | |
1261 | e1000_release_swflag_ich8lan(hw); | |
1262 | return ret_val; | |
1263 | } | |
1264 | ||
ad68076e BA |
1265 | /* |
1266 | * Finally validate the new segment by setting bit 15:14 | |
bc7f75fa AK |
1267 | * to 10b in word 0x13 , this can be done without an |
1268 | * erase as well since these bits are 11 to start with | |
ad68076e BA |
1269 | * and we need to change bit 14 to 0b |
1270 | */ | |
bc7f75fa AK |
1271 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; |
1272 | e1000_read_flash_word_ich8lan(hw, act_offset, &data); | |
1273 | data &= 0xBFFF; | |
1274 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
1275 | act_offset * 2 + 1, | |
1276 | (u8)(data >> 8)); | |
1277 | if (ret_val) { | |
1278 | e1000_release_swflag_ich8lan(hw); | |
1279 | return ret_val; | |
1280 | } | |
1281 | ||
ad68076e BA |
1282 | /* |
1283 | * And invalidate the previously valid segment by setting | |
bc7f75fa AK |
1284 | * its signature word (0x13) high_byte to 0b. This can be |
1285 | * done without an erase because flash erase sets all bits | |
ad68076e BA |
1286 | * to 1's. We can write 1's to 0's without an erase |
1287 | */ | |
bc7f75fa AK |
1288 | act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; |
1289 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); | |
1290 | if (ret_val) { | |
1291 | e1000_release_swflag_ich8lan(hw); | |
1292 | return ret_val; | |
1293 | } | |
1294 | ||
1295 | /* Great! Everything worked, we can now clear the cached entries. */ | |
1296 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
1297 | dev_spec->shadow_ram[i].modified = 0; | |
1298 | dev_spec->shadow_ram[i].value = 0xFFFF; | |
1299 | } | |
1300 | ||
1301 | e1000_release_swflag_ich8lan(hw); | |
1302 | ||
ad68076e BA |
1303 | /* |
1304 | * Reload the EEPROM, or else modifications will not appear | |
bc7f75fa AK |
1305 | * until after the next adapter reset. |
1306 | */ | |
1307 | e1000e_reload_nvm(hw); | |
1308 | msleep(10); | |
1309 | ||
1310 | return ret_val; | |
1311 | } | |
1312 | ||
1313 | /** | |
1314 | * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum | |
1315 | * @hw: pointer to the HW structure | |
1316 | * | |
1317 | * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. | |
1318 | * If the bit is 0, that the EEPROM had been modified, but the checksum was not | |
1319 | * calculated, in which case we need to calculate the checksum and set bit 6. | |
1320 | **/ | |
1321 | static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
1322 | { | |
1323 | s32 ret_val; | |
1324 | u16 data; | |
1325 | ||
ad68076e BA |
1326 | /* |
1327 | * Read 0x19 and check bit 6. If this bit is 0, the checksum | |
bc7f75fa AK |
1328 | * needs to be fixed. This bit is an indication that the NVM |
1329 | * was prepared by OEM software and did not calculate the | |
1330 | * checksum...a likely scenario. | |
1331 | */ | |
1332 | ret_val = e1000_read_nvm(hw, 0x19, 1, &data); | |
1333 | if (ret_val) | |
1334 | return ret_val; | |
1335 | ||
1336 | if ((data & 0x40) == 0) { | |
1337 | data |= 0x40; | |
1338 | ret_val = e1000_write_nvm(hw, 0x19, 1, &data); | |
1339 | if (ret_val) | |
1340 | return ret_val; | |
1341 | ret_val = e1000e_update_nvm_checksum(hw); | |
1342 | if (ret_val) | |
1343 | return ret_val; | |
1344 | } | |
1345 | ||
1346 | return e1000e_validate_nvm_checksum_generic(hw); | |
1347 | } | |
1348 | ||
1349 | /** | |
1350 | * e1000_write_flash_data_ich8lan - Writes bytes to the NVM | |
1351 | * @hw: pointer to the HW structure | |
1352 | * @offset: The offset (in bytes) of the byte/word to read. | |
1353 | * @size: Size of data to read, 1=byte 2=word | |
1354 | * @data: The byte(s) to write to the NVM. | |
1355 | * | |
1356 | * Writes one/two bytes to the NVM using the flash access registers. | |
1357 | **/ | |
1358 | static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
1359 | u8 size, u16 data) | |
1360 | { | |
1361 | union ich8_hws_flash_status hsfsts; | |
1362 | union ich8_hws_flash_ctrl hsflctl; | |
1363 | u32 flash_linear_addr; | |
1364 | u32 flash_data = 0; | |
1365 | s32 ret_val; | |
1366 | u8 count = 0; | |
1367 | ||
1368 | if (size < 1 || size > 2 || data > size * 0xff || | |
1369 | offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
1370 | return -E1000_ERR_NVM; | |
1371 | ||
1372 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
1373 | hw->nvm.flash_base_addr; | |
1374 | ||
1375 | do { | |
1376 | udelay(1); | |
1377 | /* Steps */ | |
1378 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1379 | if (ret_val) | |
1380 | break; | |
1381 | ||
1382 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
1383 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
1384 | hsflctl.hsf_ctrl.fldbcount = size -1; | |
1385 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; | |
1386 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1387 | ||
1388 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1389 | ||
1390 | if (size == 1) | |
1391 | flash_data = (u32)data & 0x00FF; | |
1392 | else | |
1393 | flash_data = (u32)data; | |
1394 | ||
1395 | ew32flash(ICH_FLASH_FDATA0, flash_data); | |
1396 | ||
ad68076e BA |
1397 | /* |
1398 | * check if FCERR is set to 1 , if set to 1, clear it | |
1399 | * and try the whole sequence a few more times else done | |
1400 | */ | |
bc7f75fa AK |
1401 | ret_val = e1000_flash_cycle_ich8lan(hw, |
1402 | ICH_FLASH_WRITE_COMMAND_TIMEOUT); | |
1403 | if (!ret_val) | |
1404 | break; | |
1405 | ||
ad68076e BA |
1406 | /* |
1407 | * If we're here, then things are most likely | |
bc7f75fa AK |
1408 | * completely hosed, but if the error condition |
1409 | * is detected, it won't hurt to give it another | |
1410 | * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
1411 | */ | |
1412 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1413 | if (hsfsts.hsf_status.flcerr == 1) | |
1414 | /* Repeat for some time before giving up. */ | |
1415 | continue; | |
1416 | if (hsfsts.hsf_status.flcdone == 0) { | |
1417 | hw_dbg(hw, "Timeout error - flash cycle " | |
1418 | "did not complete."); | |
1419 | break; | |
1420 | } | |
1421 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1422 | ||
1423 | return ret_val; | |
1424 | } | |
1425 | ||
1426 | /** | |
1427 | * e1000_write_flash_byte_ich8lan - Write a single byte to NVM | |
1428 | * @hw: pointer to the HW structure | |
1429 | * @offset: The index of the byte to read. | |
1430 | * @data: The byte to write to the NVM. | |
1431 | * | |
1432 | * Writes a single byte to the NVM using the flash access registers. | |
1433 | **/ | |
1434 | static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
1435 | u8 data) | |
1436 | { | |
1437 | u16 word = (u16)data; | |
1438 | ||
1439 | return e1000_write_flash_data_ich8lan(hw, offset, 1, word); | |
1440 | } | |
1441 | ||
1442 | /** | |
1443 | * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM | |
1444 | * @hw: pointer to the HW structure | |
1445 | * @offset: The offset of the byte to write. | |
1446 | * @byte: The byte to write to the NVM. | |
1447 | * | |
1448 | * Writes a single byte to the NVM using the flash access registers. | |
1449 | * Goes through a retry algorithm before giving up. | |
1450 | **/ | |
1451 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
1452 | u32 offset, u8 byte) | |
1453 | { | |
1454 | s32 ret_val; | |
1455 | u16 program_retries; | |
1456 | ||
1457 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
1458 | if (!ret_val) | |
1459 | return ret_val; | |
1460 | ||
1461 | for (program_retries = 0; program_retries < 100; program_retries++) { | |
1462 | hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset); | |
1463 | udelay(100); | |
1464 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
1465 | if (!ret_val) | |
1466 | break; | |
1467 | } | |
1468 | if (program_retries == 100) | |
1469 | return -E1000_ERR_NVM; | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | /** | |
1475 | * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM | |
1476 | * @hw: pointer to the HW structure | |
1477 | * @bank: 0 for first bank, 1 for second bank, etc. | |
1478 | * | |
1479 | * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. | |
1480 | * bank N is 4096 * N + flash_reg_addr. | |
1481 | **/ | |
1482 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) | |
1483 | { | |
1484 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1485 | union ich8_hws_flash_status hsfsts; | |
1486 | union ich8_hws_flash_ctrl hsflctl; | |
1487 | u32 flash_linear_addr; | |
1488 | /* bank size is in 16bit words - adjust to bytes */ | |
1489 | u32 flash_bank_size = nvm->flash_bank_size * 2; | |
1490 | s32 ret_val; | |
1491 | s32 count = 0; | |
1492 | s32 iteration; | |
1493 | s32 sector_size; | |
1494 | s32 j; | |
1495 | ||
1496 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
1497 | ||
ad68076e BA |
1498 | /* |
1499 | * Determine HW Sector size: Read BERASE bits of hw flash status | |
1500 | * register | |
1501 | * 00: The Hw sector is 256 bytes, hence we need to erase 16 | |
bc7f75fa AK |
1502 | * consecutive sectors. The start index for the nth Hw sector |
1503 | * can be calculated as = bank * 4096 + n * 256 | |
1504 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. | |
1505 | * The start index for the nth Hw sector can be calculated | |
1506 | * as = bank * 4096 | |
1507 | * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 | |
1508 | * (ich9 only, otherwise error condition) | |
1509 | * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 | |
1510 | */ | |
1511 | switch (hsfsts.hsf_status.berasesz) { | |
1512 | case 0: | |
1513 | /* Hw sector size 256 */ | |
1514 | sector_size = ICH_FLASH_SEG_SIZE_256; | |
1515 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; | |
1516 | break; | |
1517 | case 1: | |
1518 | sector_size = ICH_FLASH_SEG_SIZE_4K; | |
1519 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K; | |
1520 | break; | |
1521 | case 2: | |
1522 | if (hw->mac.type == e1000_ich9lan) { | |
1523 | sector_size = ICH_FLASH_SEG_SIZE_8K; | |
1524 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K; | |
1525 | } else { | |
1526 | return -E1000_ERR_NVM; | |
1527 | } | |
1528 | break; | |
1529 | case 3: | |
1530 | sector_size = ICH_FLASH_SEG_SIZE_64K; | |
1531 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K; | |
1532 | break; | |
1533 | default: | |
1534 | return -E1000_ERR_NVM; | |
1535 | } | |
1536 | ||
1537 | /* Start with the base address, then add the sector offset. */ | |
1538 | flash_linear_addr = hw->nvm.flash_base_addr; | |
1539 | flash_linear_addr += (bank) ? (sector_size * iteration) : 0; | |
1540 | ||
1541 | for (j = 0; j < iteration ; j++) { | |
1542 | do { | |
1543 | /* Steps */ | |
1544 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
1545 | if (ret_val) | |
1546 | return ret_val; | |
1547 | ||
ad68076e BA |
1548 | /* |
1549 | * Write a value 11 (block Erase) in Flash | |
1550 | * Cycle field in hw flash control | |
1551 | */ | |
bc7f75fa AK |
1552 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
1553 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; | |
1554 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
1555 | ||
ad68076e BA |
1556 | /* |
1557 | * Write the last 24 bits of an index within the | |
bc7f75fa AK |
1558 | * block into Flash Linear address field in Flash |
1559 | * Address. | |
1560 | */ | |
1561 | flash_linear_addr += (j * sector_size); | |
1562 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
1563 | ||
1564 | ret_val = e1000_flash_cycle_ich8lan(hw, | |
1565 | ICH_FLASH_ERASE_COMMAND_TIMEOUT); | |
1566 | if (ret_val == 0) | |
1567 | break; | |
1568 | ||
ad68076e BA |
1569 | /* |
1570 | * Check if FCERR is set to 1. If 1, | |
bc7f75fa | 1571 | * clear it and try the whole sequence |
ad68076e BA |
1572 | * a few more times else Done |
1573 | */ | |
bc7f75fa AK |
1574 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
1575 | if (hsfsts.hsf_status.flcerr == 1) | |
ad68076e | 1576 | /* repeat for some time before giving up */ |
bc7f75fa AK |
1577 | continue; |
1578 | else if (hsfsts.hsf_status.flcdone == 0) | |
1579 | return ret_val; | |
1580 | } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
1581 | } | |
1582 | ||
1583 | return 0; | |
1584 | } | |
1585 | ||
1586 | /** | |
1587 | * e1000_valid_led_default_ich8lan - Set the default LED settings | |
1588 | * @hw: pointer to the HW structure | |
1589 | * @data: Pointer to the LED settings | |
1590 | * | |
1591 | * Reads the LED default settings from the NVM to data. If the NVM LED | |
1592 | * settings is all 0's or F's, set the LED default to a valid LED default | |
1593 | * setting. | |
1594 | **/ | |
1595 | static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) | |
1596 | { | |
1597 | s32 ret_val; | |
1598 | ||
1599 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1600 | if (ret_val) { | |
1601 | hw_dbg(hw, "NVM Read Error\n"); | |
1602 | return ret_val; | |
1603 | } | |
1604 | ||
1605 | if (*data == ID_LED_RESERVED_0000 || | |
1606 | *data == ID_LED_RESERVED_FFFF) | |
1607 | *data = ID_LED_DEFAULT_ICH8LAN; | |
1608 | ||
1609 | return 0; | |
1610 | } | |
1611 | ||
1612 | /** | |
1613 | * e1000_get_bus_info_ich8lan - Get/Set the bus type and width | |
1614 | * @hw: pointer to the HW structure | |
1615 | * | |
1616 | * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability | |
1617 | * register, so the the bus width is hard coded. | |
1618 | **/ | |
1619 | static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) | |
1620 | { | |
1621 | struct e1000_bus_info *bus = &hw->bus; | |
1622 | s32 ret_val; | |
1623 | ||
1624 | ret_val = e1000e_get_bus_info_pcie(hw); | |
1625 | ||
ad68076e BA |
1626 | /* |
1627 | * ICH devices are "PCI Express"-ish. They have | |
bc7f75fa AK |
1628 | * a configuration space, but do not contain |
1629 | * PCI Express Capability registers, so bus width | |
1630 | * must be hardcoded. | |
1631 | */ | |
1632 | if (bus->width == e1000_bus_width_unknown) | |
1633 | bus->width = e1000_bus_width_pcie_x1; | |
1634 | ||
1635 | return ret_val; | |
1636 | } | |
1637 | ||
1638 | /** | |
1639 | * e1000_reset_hw_ich8lan - Reset the hardware | |
1640 | * @hw: pointer to the HW structure | |
1641 | * | |
1642 | * Does a full reset of the hardware which includes a reset of the PHY and | |
1643 | * MAC. | |
1644 | **/ | |
1645 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |
1646 | { | |
1647 | u32 ctrl, icr, kab; | |
1648 | s32 ret_val; | |
1649 | ||
ad68076e BA |
1650 | /* |
1651 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
1652 | * on the last TLP read/write transaction when MAC is reset. |
1653 | */ | |
1654 | ret_val = e1000e_disable_pcie_master(hw); | |
1655 | if (ret_val) { | |
1656 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
1657 | } | |
1658 | ||
1659 | hw_dbg(hw, "Masking off all interrupts\n"); | |
1660 | ew32(IMC, 0xffffffff); | |
1661 | ||
ad68076e BA |
1662 | /* |
1663 | * Disable the Transmit and Receive units. Then delay to allow | |
bc7f75fa AK |
1664 | * any pending transactions to complete before we hit the MAC |
1665 | * with the global reset. | |
1666 | */ | |
1667 | ew32(RCTL, 0); | |
1668 | ew32(TCTL, E1000_TCTL_PSP); | |
1669 | e1e_flush(); | |
1670 | ||
1671 | msleep(10); | |
1672 | ||
1673 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ | |
1674 | if (hw->mac.type == e1000_ich8lan) { | |
1675 | /* Set Tx and Rx buffer allocation to 8k apiece. */ | |
1676 | ew32(PBA, E1000_PBA_8K); | |
1677 | /* Set Packet Buffer Size to 16k. */ | |
1678 | ew32(PBS, E1000_PBS_16K); | |
1679 | } | |
1680 | ||
1681 | ctrl = er32(CTRL); | |
1682 | ||
1683 | if (!e1000_check_reset_block(hw)) { | |
ad68076e BA |
1684 | /* |
1685 | * PHY HW reset requires MAC CORE reset at the same | |
bc7f75fa AK |
1686 | * time to make sure the interface between MAC and the |
1687 | * external PHY is reset. | |
1688 | */ | |
1689 | ctrl |= E1000_CTRL_PHY_RST; | |
1690 | } | |
1691 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1692 | hw_dbg(hw, "Issuing a global reset to ich8lan"); | |
1693 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); | |
1694 | msleep(20); | |
1695 | ||
1696 | ret_val = e1000e_get_auto_rd_done(hw); | |
1697 | if (ret_val) { | |
1698 | /* | |
1699 | * When auto config read does not complete, do not | |
1700 | * return with an error. This can happen in situations | |
1701 | * where there is no eeprom and prevents getting link. | |
1702 | */ | |
1703 | hw_dbg(hw, "Auto Read Done did not complete\n"); | |
1704 | } | |
1705 | ||
1706 | ew32(IMC, 0xffffffff); | |
1707 | icr = er32(ICR); | |
1708 | ||
1709 | kab = er32(KABGTXD); | |
1710 | kab |= E1000_KABGTXD_BGSQLBIAS; | |
1711 | ew32(KABGTXD, kab); | |
1712 | ||
1713 | return ret_val; | |
1714 | } | |
1715 | ||
1716 | /** | |
1717 | * e1000_init_hw_ich8lan - Initialize the hardware | |
1718 | * @hw: pointer to the HW structure | |
1719 | * | |
1720 | * Prepares the hardware for transmit and receive by doing the following: | |
1721 | * - initialize hardware bits | |
1722 | * - initialize LED identification | |
1723 | * - setup receive address registers | |
1724 | * - setup flow control | |
489815ce | 1725 | * - setup transmit descriptors |
bc7f75fa AK |
1726 | * - clear statistics |
1727 | **/ | |
1728 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) | |
1729 | { | |
1730 | struct e1000_mac_info *mac = &hw->mac; | |
1731 | u32 ctrl_ext, txdctl, snoop; | |
1732 | s32 ret_val; | |
1733 | u16 i; | |
1734 | ||
1735 | e1000_initialize_hw_bits_ich8lan(hw); | |
1736 | ||
1737 | /* Initialize identification LED */ | |
1738 | ret_val = e1000e_id_led_init(hw); | |
1739 | if (ret_val) { | |
1740 | hw_dbg(hw, "Error initializing identification LED\n"); | |
1741 | return ret_val; | |
1742 | } | |
1743 | ||
1744 | /* Setup the receive address. */ | |
1745 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
1746 | ||
1747 | /* Zero out the Multicast HASH table */ | |
1748 | hw_dbg(hw, "Zeroing the MTA\n"); | |
1749 | for (i = 0; i < mac->mta_reg_count; i++) | |
1750 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
1751 | ||
1752 | /* Setup link and flow control */ | |
1753 | ret_val = e1000_setup_link_ich8lan(hw); | |
1754 | ||
1755 | /* Set the transmit descriptor write-back policy for both queues */ | |
e9ec2c0f | 1756 | txdctl = er32(TXDCTL(0)); |
bc7f75fa AK |
1757 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
1758 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
1759 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | |
1760 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | |
e9ec2c0f JK |
1761 | ew32(TXDCTL(0), txdctl); |
1762 | txdctl = er32(TXDCTL(1)); | |
bc7f75fa AK |
1763 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
1764 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
1765 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | |
1766 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | |
e9ec2c0f | 1767 | ew32(TXDCTL(1), txdctl); |
bc7f75fa | 1768 | |
ad68076e BA |
1769 | /* |
1770 | * ICH8 has opposite polarity of no_snoop bits. | |
1771 | * By default, we should use snoop behavior. | |
1772 | */ | |
bc7f75fa AK |
1773 | if (mac->type == e1000_ich8lan) |
1774 | snoop = PCIE_ICH8_SNOOP_ALL; | |
1775 | else | |
1776 | snoop = (u32) ~(PCIE_NO_SNOOP_ALL); | |
1777 | e1000e_set_pcie_no_snoop(hw, snoop); | |
1778 | ||
1779 | ctrl_ext = er32(CTRL_EXT); | |
1780 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
1781 | ew32(CTRL_EXT, ctrl_ext); | |
1782 | ||
ad68076e BA |
1783 | /* |
1784 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1785 | * important that we do this after we have tried to establish link |
1786 | * because the symbol error count will increment wildly if there | |
1787 | * is no link. | |
1788 | */ | |
1789 | e1000_clear_hw_cntrs_ich8lan(hw); | |
1790 | ||
1791 | return 0; | |
1792 | } | |
1793 | /** | |
1794 | * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits | |
1795 | * @hw: pointer to the HW structure | |
1796 | * | |
1797 | * Sets/Clears required hardware bits necessary for correctly setting up the | |
1798 | * hardware for transmit and receive. | |
1799 | **/ | |
1800 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) | |
1801 | { | |
1802 | u32 reg; | |
1803 | ||
1804 | /* Extended Device Control */ | |
1805 | reg = er32(CTRL_EXT); | |
1806 | reg |= (1 << 22); | |
1807 | ew32(CTRL_EXT, reg); | |
1808 | ||
1809 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1810 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1811 | reg |= (1 << 22); |
e9ec2c0f | 1812 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1813 | |
1814 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1815 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1816 | reg |= (1 << 22); |
e9ec2c0f | 1817 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1818 | |
1819 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1820 | reg = er32(TARC(0)); |
bc7f75fa AK |
1821 | if (hw->mac.type == e1000_ich8lan) |
1822 | reg |= (1 << 28) | (1 << 29); | |
1823 | reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); | |
e9ec2c0f | 1824 | ew32(TARC(0), reg); |
bc7f75fa AK |
1825 | |
1826 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1827 | reg = er32(TARC(1)); |
bc7f75fa AK |
1828 | if (er32(TCTL) & E1000_TCTL_MULR) |
1829 | reg &= ~(1 << 28); | |
1830 | else | |
1831 | reg |= (1 << 28); | |
1832 | reg |= (1 << 24) | (1 << 26) | (1 << 30); | |
e9ec2c0f | 1833 | ew32(TARC(1), reg); |
bc7f75fa AK |
1834 | |
1835 | /* Device Status */ | |
1836 | if (hw->mac.type == e1000_ich8lan) { | |
1837 | reg = er32(STATUS); | |
1838 | reg &= ~(1 << 31); | |
1839 | ew32(STATUS, reg); | |
1840 | } | |
1841 | } | |
1842 | ||
1843 | /** | |
1844 | * e1000_setup_link_ich8lan - Setup flow control and link settings | |
1845 | * @hw: pointer to the HW structure | |
1846 | * | |
1847 | * Determines which flow control settings to use, then configures flow | |
1848 | * control. Calls the appropriate media-specific link configuration | |
1849 | * function. Assuming the adapter has a valid link partner, a valid link | |
1850 | * should be established. Assumes the hardware has previously been reset | |
1851 | * and the transmitter and receiver are not enabled. | |
1852 | **/ | |
1853 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) | |
1854 | { | |
bc7f75fa AK |
1855 | s32 ret_val; |
1856 | ||
1857 | if (e1000_check_reset_block(hw)) | |
1858 | return 0; | |
1859 | ||
ad68076e BA |
1860 | /* |
1861 | * ICH parts do not have a word in the NVM to determine | |
bc7f75fa AK |
1862 | * the default flow control setting, so we explicitly |
1863 | * set it to full. | |
1864 | */ | |
318a94d6 JK |
1865 | if (hw->fc.type == e1000_fc_default) |
1866 | hw->fc.type = e1000_fc_full; | |
bc7f75fa | 1867 | |
318a94d6 | 1868 | hw->fc.original_type = hw->fc.type; |
bc7f75fa | 1869 | |
318a94d6 | 1870 | hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type); |
bc7f75fa AK |
1871 | |
1872 | /* Continue to configure the copper link. */ | |
1873 | ret_val = e1000_setup_copper_link_ich8lan(hw); | |
1874 | if (ret_val) | |
1875 | return ret_val; | |
1876 | ||
318a94d6 | 1877 | ew32(FCTTV, hw->fc.pause_time); |
bc7f75fa AK |
1878 | |
1879 | return e1000e_set_fc_watermarks(hw); | |
1880 | } | |
1881 | ||
1882 | /** | |
1883 | * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface | |
1884 | * @hw: pointer to the HW structure | |
1885 | * | |
1886 | * Configures the kumeran interface to the PHY to wait the appropriate time | |
1887 | * when polling the PHY, then call the generic setup_copper_link to finish | |
1888 | * configuring the copper link. | |
1889 | **/ | |
1890 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) | |
1891 | { | |
1892 | u32 ctrl; | |
1893 | s32 ret_val; | |
1894 | u16 reg_data; | |
1895 | ||
1896 | ctrl = er32(CTRL); | |
1897 | ctrl |= E1000_CTRL_SLU; | |
1898 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1899 | ew32(CTRL, ctrl); | |
1900 | ||
ad68076e BA |
1901 | /* |
1902 | * Set the mac to wait the maximum time between each iteration | |
bc7f75fa | 1903 | * and increase the max iterations when polling the phy; |
ad68076e BA |
1904 | * this fixes erroneous timeouts at 10Mbps. |
1905 | */ | |
bc7f75fa AK |
1906 | ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); |
1907 | if (ret_val) | |
1908 | return ret_val; | |
1909 | ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); | |
1910 | if (ret_val) | |
1911 | return ret_val; | |
1912 | reg_data |= 0x3F; | |
1913 | ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); | |
1914 | if (ret_val) | |
1915 | return ret_val; | |
1916 | ||
1917 | if (hw->phy.type == e1000_phy_igp_3) { | |
1918 | ret_val = e1000e_copper_link_setup_igp(hw); | |
1919 | if (ret_val) | |
1920 | return ret_val; | |
1921 | } | |
1922 | ||
1923 | return e1000e_setup_copper_link(hw); | |
1924 | } | |
1925 | ||
1926 | /** | |
1927 | * e1000_get_link_up_info_ich8lan - Get current link speed and duplex | |
1928 | * @hw: pointer to the HW structure | |
1929 | * @speed: pointer to store current link speed | |
1930 | * @duplex: pointer to store the current link duplex | |
1931 | * | |
ad68076e | 1932 | * Calls the generic get_speed_and_duplex to retrieve the current link |
bc7f75fa AK |
1933 | * information and then calls the Kumeran lock loss workaround for links at |
1934 | * gigabit speeds. | |
1935 | **/ | |
1936 | static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, | |
1937 | u16 *duplex) | |
1938 | { | |
1939 | s32 ret_val; | |
1940 | ||
1941 | ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); | |
1942 | if (ret_val) | |
1943 | return ret_val; | |
1944 | ||
1945 | if ((hw->mac.type == e1000_ich8lan) && | |
1946 | (hw->phy.type == e1000_phy_igp_3) && | |
1947 | (*speed == SPEED_1000)) { | |
1948 | ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); | |
1949 | } | |
1950 | ||
1951 | return ret_val; | |
1952 | } | |
1953 | ||
1954 | /** | |
1955 | * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround | |
1956 | * @hw: pointer to the HW structure | |
1957 | * | |
1958 | * Work-around for 82566 Kumeran PCS lock loss: | |
1959 | * On link status change (i.e. PCI reset, speed change) and link is up and | |
1960 | * speed is gigabit- | |
1961 | * 0) if workaround is optionally disabled do nothing | |
1962 | * 1) wait 1ms for Kumeran link to come up | |
1963 | * 2) check Kumeran Diagnostic register PCS lock loss bit | |
1964 | * 3) if not set the link is locked (all is good), otherwise... | |
1965 | * 4) reset the PHY | |
1966 | * 5) repeat up to 10 times | |
1967 | * Note: this is only called for IGP3 copper when speed is 1gb. | |
1968 | **/ | |
1969 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) | |
1970 | { | |
1971 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
1972 | u32 phy_ctrl; | |
1973 | s32 ret_val; | |
1974 | u16 i, data; | |
1975 | bool link; | |
1976 | ||
1977 | if (!dev_spec->kmrn_lock_loss_workaround_enabled) | |
1978 | return 0; | |
1979 | ||
ad68076e BA |
1980 | /* |
1981 | * Make sure link is up before proceeding. If not just return. | |
bc7f75fa | 1982 | * Attempting this while link is negotiating fouled up link |
ad68076e BA |
1983 | * stability |
1984 | */ | |
bc7f75fa AK |
1985 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
1986 | if (!link) | |
1987 | return 0; | |
1988 | ||
1989 | for (i = 0; i < 10; i++) { | |
1990 | /* read once to clear */ | |
1991 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
1992 | if (ret_val) | |
1993 | return ret_val; | |
1994 | /* and again to get new status */ | |
1995 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
1996 | if (ret_val) | |
1997 | return ret_val; | |
1998 | ||
1999 | /* check for PCS lock */ | |
2000 | if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) | |
2001 | return 0; | |
2002 | ||
2003 | /* Issue PHY reset */ | |
2004 | e1000_phy_hw_reset(hw); | |
2005 | mdelay(5); | |
2006 | } | |
2007 | /* Disable GigE link negotiation */ | |
2008 | phy_ctrl = er32(PHY_CTRL); | |
2009 | phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | | |
2010 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
2011 | ew32(PHY_CTRL, phy_ctrl); | |
2012 | ||
ad68076e BA |
2013 | /* |
2014 | * Call gig speed drop workaround on Gig disable before accessing | |
2015 | * any PHY registers | |
2016 | */ | |
bc7f75fa AK |
2017 | e1000e_gig_downshift_workaround_ich8lan(hw); |
2018 | ||
2019 | /* unable to acquire PCS lock */ | |
2020 | return -E1000_ERR_PHY; | |
2021 | } | |
2022 | ||
2023 | /** | |
ad68076e | 2024 | * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state |
bc7f75fa | 2025 | * @hw: pointer to the HW structure |
489815ce | 2026 | * @state: boolean value used to set the current Kumeran workaround state |
bc7f75fa AK |
2027 | * |
2028 | * If ICH8, set the current Kumeran workaround state (enabled - TRUE | |
2029 | * /disabled - FALSE). | |
2030 | **/ | |
2031 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, | |
2032 | bool state) | |
2033 | { | |
2034 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
2035 | ||
2036 | if (hw->mac.type != e1000_ich8lan) { | |
2037 | hw_dbg(hw, "Workaround applies to ICH8 only.\n"); | |
2038 | return; | |
2039 | } | |
2040 | ||
2041 | dev_spec->kmrn_lock_loss_workaround_enabled = state; | |
2042 | } | |
2043 | ||
2044 | /** | |
2045 | * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 | |
2046 | * @hw: pointer to the HW structure | |
2047 | * | |
2048 | * Workaround for 82566 power-down on D3 entry: | |
2049 | * 1) disable gigabit link | |
2050 | * 2) write VR power-down enable | |
2051 | * 3) read it back | |
2052 | * Continue if successful, else issue LCD reset and repeat | |
2053 | **/ | |
2054 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) | |
2055 | { | |
2056 | u32 reg; | |
2057 | u16 data; | |
2058 | u8 retry = 0; | |
2059 | ||
2060 | if (hw->phy.type != e1000_phy_igp_3) | |
2061 | return; | |
2062 | ||
2063 | /* Try the workaround twice (if needed) */ | |
2064 | do { | |
2065 | /* Disable link */ | |
2066 | reg = er32(PHY_CTRL); | |
2067 | reg |= (E1000_PHY_CTRL_GBE_DISABLE | | |
2068 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
2069 | ew32(PHY_CTRL, reg); | |
2070 | ||
ad68076e BA |
2071 | /* |
2072 | * Call gig speed drop workaround on Gig disable before | |
2073 | * accessing any PHY registers | |
2074 | */ | |
bc7f75fa AK |
2075 | if (hw->mac.type == e1000_ich8lan) |
2076 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
2077 | ||
2078 | /* Write VR power-down enable */ | |
2079 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
2080 | data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
2081 | e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); | |
2082 | ||
2083 | /* Read it back and test */ | |
2084 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
2085 | data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
2086 | if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) | |
2087 | break; | |
2088 | ||
2089 | /* Issue PHY reset and repeat at most one more time */ | |
2090 | reg = er32(CTRL); | |
2091 | ew32(CTRL, reg | E1000_CTRL_PHY_RST); | |
2092 | retry++; | |
2093 | } while (retry); | |
2094 | } | |
2095 | ||
2096 | /** | |
2097 | * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working | |
2098 | * @hw: pointer to the HW structure | |
2099 | * | |
2100 | * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), | |
489815ce | 2101 | * LPLU, Gig disable, MDIC PHY reset): |
bc7f75fa AK |
2102 | * 1) Set Kumeran Near-end loopback |
2103 | * 2) Clear Kumeran Near-end loopback | |
2104 | * Should only be called for ICH8[m] devices with IGP_3 Phy. | |
2105 | **/ | |
2106 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) | |
2107 | { | |
2108 | s32 ret_val; | |
2109 | u16 reg_data; | |
2110 | ||
2111 | if ((hw->mac.type != e1000_ich8lan) || | |
2112 | (hw->phy.type != e1000_phy_igp_3)) | |
2113 | return; | |
2114 | ||
2115 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2116 | ®_data); | |
2117 | if (ret_val) | |
2118 | return; | |
2119 | reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
2120 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2121 | reg_data); | |
2122 | if (ret_val) | |
2123 | return; | |
2124 | reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
2125 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
2126 | reg_data); | |
2127 | } | |
2128 | ||
2129 | /** | |
2130 | * e1000_cleanup_led_ich8lan - Restore the default LED operation | |
2131 | * @hw: pointer to the HW structure | |
2132 | * | |
2133 | * Return the LED back to the default configuration. | |
2134 | **/ | |
2135 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) | |
2136 | { | |
2137 | if (hw->phy.type == e1000_phy_ife) | |
2138 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); | |
2139 | ||
2140 | ew32(LEDCTL, hw->mac.ledctl_default); | |
2141 | return 0; | |
2142 | } | |
2143 | ||
2144 | /** | |
489815ce | 2145 | * e1000_led_on_ich8lan - Turn LEDs on |
bc7f75fa AK |
2146 | * @hw: pointer to the HW structure |
2147 | * | |
489815ce | 2148 | * Turn on the LEDs. |
bc7f75fa AK |
2149 | **/ |
2150 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) | |
2151 | { | |
2152 | if (hw->phy.type == e1000_phy_ife) | |
2153 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
2154 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); | |
2155 | ||
2156 | ew32(LEDCTL, hw->mac.ledctl_mode2); | |
2157 | return 0; | |
2158 | } | |
2159 | ||
2160 | /** | |
489815ce | 2161 | * e1000_led_off_ich8lan - Turn LEDs off |
bc7f75fa AK |
2162 | * @hw: pointer to the HW structure |
2163 | * | |
489815ce | 2164 | * Turn off the LEDs. |
bc7f75fa AK |
2165 | **/ |
2166 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) | |
2167 | { | |
2168 | if (hw->phy.type == e1000_phy_ife) | |
2169 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
2170 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); | |
2171 | ||
2172 | ew32(LEDCTL, hw->mac.ledctl_mode1); | |
2173 | return 0; | |
2174 | } | |
2175 | ||
2176 | /** | |
2177 | * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters | |
2178 | * @hw: pointer to the HW structure | |
2179 | * | |
2180 | * Clears hardware counters specific to the silicon family and calls | |
2181 | * clear_hw_cntrs_generic to clear all general purpose counters. | |
2182 | **/ | |
2183 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) | |
2184 | { | |
2185 | u32 temp; | |
2186 | ||
2187 | e1000e_clear_hw_cntrs_base(hw); | |
2188 | ||
2189 | temp = er32(ALGNERRC); | |
2190 | temp = er32(RXERRC); | |
2191 | temp = er32(TNCRS); | |
2192 | temp = er32(CEXTERR); | |
2193 | temp = er32(TSCTC); | |
2194 | temp = er32(TSCTFC); | |
2195 | ||
2196 | temp = er32(MGTPRC); | |
2197 | temp = er32(MGTPDC); | |
2198 | temp = er32(MGTPTC); | |
2199 | ||
2200 | temp = er32(IAC); | |
2201 | temp = er32(ICRXOC); | |
2202 | ||
2203 | } | |
2204 | ||
2205 | static struct e1000_mac_operations ich8_mac_ops = { | |
2206 | .mng_mode_enab = E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT, | |
2207 | .check_for_link = e1000e_check_for_copper_link, | |
2208 | .cleanup_led = e1000_cleanup_led_ich8lan, | |
2209 | .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, | |
2210 | .get_bus_info = e1000_get_bus_info_ich8lan, | |
2211 | .get_link_up_info = e1000_get_link_up_info_ich8lan, | |
2212 | .led_on = e1000_led_on_ich8lan, | |
2213 | .led_off = e1000_led_off_ich8lan, | |
e2de3eb6 | 2214 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
bc7f75fa AK |
2215 | .reset_hw = e1000_reset_hw_ich8lan, |
2216 | .init_hw = e1000_init_hw_ich8lan, | |
2217 | .setup_link = e1000_setup_link_ich8lan, | |
2218 | .setup_physical_interface= e1000_setup_copper_link_ich8lan, | |
2219 | }; | |
2220 | ||
2221 | static struct e1000_phy_operations ich8_phy_ops = { | |
2222 | .acquire_phy = e1000_acquire_swflag_ich8lan, | |
2223 | .check_reset_block = e1000_check_reset_block_ich8lan, | |
2224 | .commit_phy = NULL, | |
2225 | .force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan, | |
2226 | .get_cfg_done = e1000e_get_cfg_done, | |
2227 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
2228 | .get_phy_info = e1000_get_phy_info_ich8lan, | |
2229 | .read_phy_reg = e1000e_read_phy_reg_igp, | |
2230 | .release_phy = e1000_release_swflag_ich8lan, | |
2231 | .reset_phy = e1000_phy_hw_reset_ich8lan, | |
2232 | .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, | |
2233 | .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, | |
2234 | .write_phy_reg = e1000e_write_phy_reg_igp, | |
2235 | }; | |
2236 | ||
2237 | static struct e1000_nvm_operations ich8_nvm_ops = { | |
2238 | .acquire_nvm = e1000_acquire_swflag_ich8lan, | |
2239 | .read_nvm = e1000_read_nvm_ich8lan, | |
2240 | .release_nvm = e1000_release_swflag_ich8lan, | |
2241 | .update_nvm = e1000_update_nvm_checksum_ich8lan, | |
2242 | .valid_led_default = e1000_valid_led_default_ich8lan, | |
2243 | .validate_nvm = e1000_validate_nvm_checksum_ich8lan, | |
2244 | .write_nvm = e1000_write_nvm_ich8lan, | |
2245 | }; | |
2246 | ||
2247 | struct e1000_info e1000_ich8_info = { | |
2248 | .mac = e1000_ich8lan, | |
2249 | .flags = FLAG_HAS_WOL | |
2250 | | FLAG_RX_CSUM_ENABLED | |
2251 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
2252 | | FLAG_HAS_AMT | |
2253 | | FLAG_HAS_FLASH | |
2254 | | FLAG_APME_IN_WUC, | |
2255 | .pba = 8, | |
2256 | .get_invariants = e1000_get_invariants_ich8lan, | |
2257 | .mac_ops = &ich8_mac_ops, | |
2258 | .phy_ops = &ich8_phy_ops, | |
2259 | .nvm_ops = &ich8_nvm_ops, | |
2260 | }; | |
2261 | ||
2262 | struct e1000_info e1000_ich9_info = { | |
2263 | .mac = e1000_ich9lan, | |
2264 | .flags = FLAG_HAS_JUMBO_FRAMES | |
2265 | | FLAG_HAS_WOL | |
2266 | | FLAG_RX_CSUM_ENABLED | |
2267 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
2268 | | FLAG_HAS_AMT | |
2269 | | FLAG_HAS_ERT | |
2270 | | FLAG_HAS_FLASH | |
2271 | | FLAG_APME_IN_WUC, | |
2272 | .pba = 10, | |
2273 | .get_invariants = e1000_get_invariants_ich8lan, | |
2274 | .mac_ops = &ich8_mac_ops, | |
2275 | .phy_ops = &ich8_phy_ops, | |
2276 | .nvm_ops = &ich8_nvm_ops, | |
2277 | }; | |
2278 |