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Merge branch 'urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia-2.6
[linux-2.6-block.git] / drivers / net / e1000e / ich8lan.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
c7e54b1b 4 Copyright(c) 1999 - 2009 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
1605927f 30 * 82562G 10/100 Network Connection
bc7f75fa
AK		 31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
97ac8cae
BA		 42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
1605927f 44 * 82567V Gigabit Network Connection
97ac8cae
BA		 45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
2f15f9d6 50 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
bc7f75fa
AK		 55 */
56
bc7f75fa
AK		 57#include "e1000.h"
58
59#define ICH_FLASH_GFPREG 0x0000
60#define ICH_FLASH_HSFSTS 0x0004
61#define ICH_FLASH_HSFCTL 0x0006
62#define ICH_FLASH_FADDR 0x0008
63#define ICH_FLASH_FDATA0 0x0010
4a770358 64#define ICH_FLASH_PR0 0x0074
bc7f75fa
AK		 65
66#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
71
72#define ICH_CYCLE_READ 0
73#define ICH_CYCLE_WRITE 2
74#define ICH_CYCLE_ERASE 3
75
76#define FLASH_GFPREG_BASE_MASK 0x1FFF
77#define FLASH_SECTOR_ADDR_SHIFT 12
78
79#define ICH_FLASH_SEG_SIZE_256 256
80#define ICH_FLASH_SEG_SIZE_4K 4096
81#define ICH_FLASH_SEG_SIZE_8K 8192
82#define ICH_FLASH_SEG_SIZE_64K 65536
83
84
85#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
86
87#define E1000_ICH_MNG_IAMT_MODE 0x2
88
89#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
90 (ID_LED_DEF1_OFF2 << 8) | \
91 (ID_LED_DEF1_ON2 << 4) | \
92 (ID_LED_DEF1_DEF2))
93
94#define E1000_ICH_NVM_SIG_WORD 0x13
95#define E1000_ICH_NVM_SIG_MASK 0xC000
e243455d
BA		 96#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
97#define E1000_ICH_NVM_SIG_VALUE 0x80
bc7f75fa
AK		 98
99#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
100
101#define E1000_FEXTNVM_SW_CONFIG 1
102#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
103
104#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
105
106#define E1000_ICH_RAR_ENTRIES 7
107
108#define PHY_PAGE_SHIFT 5
109#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
110 ((reg) & MAX_PHY_REG_ADDRESS))
111#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
112#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
113
114#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
115#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
116#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
117
a4f58f54
BA		 118#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
119
53ac5a88
BA		 120#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
121
f523d211
BA		 122/* SMBus Address Phy Register */
123#define HV_SMB_ADDR PHY_REG(768, 26)
124#define HV_SMB_ADDR_PEC_EN 0x0200
125#define HV_SMB_ADDR_VALID 0x0080
126
127/* Strapping Option Register - RO */
128#define E1000_STRAP 0x0000C
129#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
130#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
131
fa2ce13c
BA		 132/* OEM Bits Phy Register */
133#define HV_OEM_BITS PHY_REG(768, 25)
134#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
f523d211 135#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
fa2ce13c
BA		 136#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
137
1d5846b9
BA		 138#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
139#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
140
fddaa1af
BA		 141/* KMRN Mode Control */
142#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
143#define HV_KMRN_MDIO_SLOW 0x0400
144
bc7f75fa
AK		 145/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
146/* Offset 04h HSFSTS */
147union ich8_hws_flash_status {
148 struct ich8_hsfsts {
149 u16 flcdone :1; /* bit 0 Flash Cycle Done */
150 u16 flcerr :1; /* bit 1 Flash Cycle Error */
151 u16 dael :1; /* bit 2 Direct Access error Log */
152 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
153 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
154 u16 reserved1 :2; /* bit 13:6 Reserved */
155 u16 reserved2 :6; /* bit 13:6 Reserved */
156 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
157 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
158 } hsf_status;
159 u16 regval;
160};
161
162/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
163/* Offset 06h FLCTL */
164union ich8_hws_flash_ctrl {
165 struct ich8_hsflctl {
166 u16 flcgo :1; /* 0 Flash Cycle Go */
167 u16 flcycle :2; /* 2:1 Flash Cycle */
168 u16 reserved :5; /* 7:3 Reserved */
169 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
170 u16 flockdn :6; /* 15:10 Reserved */
171 } hsf_ctrl;
172 u16 regval;
173};
174
175/* ICH Flash Region Access Permissions */
176union ich8_hws_flash_regacc {
177 struct ich8_flracc {
178 u32 grra :8; /* 0:7 GbE region Read Access */
179 u32 grwa :8; /* 8:15 GbE region Write Access */
180 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
181 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
182 } hsf_flregacc;
183 u16 regval;
184};
185
4a770358
BA		 186/* ICH Flash Protected Region */
187union ich8_flash_protected_range {
188 struct ich8_pr {
189 u32 base:13; /* 0:12 Protected Range Base */
190 u32 reserved1:2; /* 13:14 Reserved */
191 u32 rpe:1; /* 15 Read Protection Enable */
192 u32 limit:13; /* 16:28 Protected Range Limit */
193 u32 reserved2:2; /* 29:30 Reserved */
194 u32 wpe:1; /* 31 Write Protection Enable */
195 } range;
196 u32 regval;
197};
198
bc7f75fa
AK		 199static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
200static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
201static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 202static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
203static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
204 u32 offset, u8 byte);
f4187b56
BA		 205static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
206 u8 *data);
bc7f75fa
AK		 207static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
208 u16 *data);
209static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
210 u8 size, u16 *data);
211static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
212static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
f4187b56 213static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 214static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
215static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
216static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
217static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
218static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
219static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
220static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
221static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 222static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
17f208de 223static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
f523d211 224static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1d5846b9 225static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fddaa1af 226static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
bc7f75fa
AK		 227
228static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
229{
230 return readw(hw->flash_address + reg);
231}
232
233static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
234{
235 return readl(hw->flash_address + reg);
236}
237
238static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
239{
240 writew(val, hw->flash_address + reg);
241}
242
243static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
244{
245 writel(val, hw->flash_address + reg);
246}
247
248#define er16flash(reg) __er16flash(hw, (reg))
249#define er32flash(reg) __er32flash(hw, (reg))
250#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
251#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
252
a4f58f54
BA		 253/**
254 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
255 * @hw: pointer to the HW structure
256 *
257 * Initialize family-specific PHY parameters and function pointers.
258 **/
259static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
260{
261 struct e1000_phy_info *phy = &hw->phy;
262 s32 ret_val = 0;
263
264 phy->addr = 1;
265 phy->reset_delay_us = 100;
266
94d8186a
BA		 267 phy->ops.read_reg = e1000_read_phy_reg_hv;
268 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
fa2ce13c
BA		 269 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
270 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
94d8186a
BA		 271 phy->ops.write_reg = e1000_write_phy_reg_hv;
272 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
17f208de
BA		 273 phy->ops.power_up = e1000_power_up_phy_copper;
274 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
a4f58f54
BA		 275 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
276
277 phy->id = e1000_phy_unknown;
fddaa1af
BA		 278 ret_val = e1000e_get_phy_id(hw);
279 if (ret_val)
280 goto out;
281 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
282 /*
283 * In case the PHY needs to be in mdio slow mode (eg. 82577),
284 * set slow mode and try to get the PHY id again.
285 */
286 ret_val = e1000_set_mdio_slow_mode_hv(hw);
287 if (ret_val)
288 goto out;
289 ret_val = e1000e_get_phy_id(hw);
290 if (ret_val)
291 goto out;
292 }
a4f58f54
BA		 293 phy->type = e1000e_get_phy_type_from_id(phy->id);
294
0be84010
BA		 295 switch (phy->type) {
296 case e1000_phy_82577:
a4f58f54
BA		 297 phy->ops.check_polarity = e1000_check_polarity_82577;
298 phy->ops.force_speed_duplex =
299 e1000_phy_force_speed_duplex_82577;
0be84010 300 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 301 phy->ops.get_info = e1000_get_phy_info_82577;
302 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 303 case e1000_phy_82578:
304 phy->ops.check_polarity = e1000_check_polarity_m88;
305 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
306 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
307 phy->ops.get_info = e1000e_get_phy_info_m88;
308 break;
309 default:
310 ret_val = -E1000_ERR_PHY;
311 break;
a4f58f54
BA		 312 }
313
fddaa1af 314out:
a4f58f54
BA		 315 return ret_val;
316}
317
bc7f75fa
AK		 318/**
319 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
320 * @hw: pointer to the HW structure
321 *
322 * Initialize family-specific PHY parameters and function pointers.
323 **/
324static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
325{
326 struct e1000_phy_info *phy = &hw->phy;
327 s32 ret_val;
328 u16 i = 0;
329
330 phy->addr = 1;
331 phy->reset_delay_us = 100;
332
17f208de
BA		 333 phy->ops.power_up = e1000_power_up_phy_copper;
334 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
335
97ac8cae
BA		 336 /*
337 * We may need to do this twice - once for IGP and if that fails,
338 * we'll set BM func pointers and try again
339 */
340 ret_val = e1000e_determine_phy_address(hw);
341 if (ret_val) {
94d8186a
BA		 342 phy->ops.write_reg = e1000e_write_phy_reg_bm;
343 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae 344 ret_val = e1000e_determine_phy_address(hw);
9b71b419
BA		 345 if (ret_val) {
346 e_dbg("Cannot determine PHY addr. Erroring out\n");
97ac8cae 347 return ret_val;
9b71b419 348 }
97ac8cae
BA		 349 }
350
bc7f75fa
AK		 351 phy->id = 0;
352 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
353 (i++ < 100)) {
354 msleep(1);
355 ret_val = e1000e_get_phy_id(hw);
356 if (ret_val)
357 return ret_val;
358 }
359
360 /* Verify phy id */
361 switch (phy->id) {
362 case IGP03E1000_E_PHY_ID:
363 phy->type = e1000_phy_igp_3;
364 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 365 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
366 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
0be84010
BA		 367 phy->ops.get_info = e1000e_get_phy_info_igp;
368 phy->ops.check_polarity = e1000_check_polarity_igp;
369 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
bc7f75fa
AK		 370 break;
371 case IFE_E_PHY_ID:
372 case IFE_PLUS_E_PHY_ID:
373 case IFE_C_E_PHY_ID:
374 phy->type = e1000_phy_ife;
375 phy->autoneg_mask = E1000_ALL_NOT_GIG;
0be84010
BA		 376 phy->ops.get_info = e1000_get_phy_info_ife;
377 phy->ops.check_polarity = e1000_check_polarity_ife;
378 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
bc7f75fa 379 break;
97ac8cae
BA		 380 case BME1000_E_PHY_ID:
381 phy->type = e1000_phy_bm;
382 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 383 phy->ops.read_reg = e1000e_read_phy_reg_bm;
384 phy->ops.write_reg = e1000e_write_phy_reg_bm;
385 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 386 phy->ops.get_info = e1000e_get_phy_info_m88;
387 phy->ops.check_polarity = e1000_check_polarity_m88;
388 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
97ac8cae 389 break;
bc7f75fa
AK		 390 default:
391 return -E1000_ERR_PHY;
392 break;
393 }
394
395 return 0;
396}
397
398/**
399 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
400 * @hw: pointer to the HW structure
401 *
402 * Initialize family-specific NVM parameters and function
403 * pointers.
404 **/
405static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
406{
407 struct e1000_nvm_info *nvm = &hw->nvm;
408 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 409 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa
AK		 410 u16 i;
411
ad68076e 412 /* Can't read flash registers if the register set isn't mapped. */
bc7f75fa 413 if (!hw->flash_address) {
3bb99fe2 414 e_dbg("ERROR: Flash registers not mapped\n");
bc7f75fa
AK		 415 return -E1000_ERR_CONFIG;
416 }
417
418 nvm->type = e1000_nvm_flash_sw;
419
420 gfpreg = er32flash(ICH_FLASH_GFPREG);
421
ad68076e
BA		 422 /*
423 * sector_X_addr is a "sector"-aligned address (4096 bytes)
bc7f75fa 424 * Add 1 to sector_end_addr since this sector is included in
ad68076e
BA		 425 * the overall size.
426 */
bc7f75fa
AK		 427 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
428 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
429
430 /* flash_base_addr is byte-aligned */
431 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
432
ad68076e
BA		 433 /*
434 * find total size of the NVM, then cut in half since the total
435 * size represents two separate NVM banks.
436 */
bc7f75fa
AK		 437 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
438 << FLASH_SECTOR_ADDR_SHIFT;
439 nvm->flash_bank_size /= 2;
440 /* Adjust to word count */
441 nvm->flash_bank_size /= sizeof(u16);
442
443 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
444
445 /* Clear shadow ram */
446 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 447 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 448 dev_spec->shadow_ram[i].value = 0xFFFF;
449 }
450
451 return 0;
452}
453
454/**
455 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
456 * @hw: pointer to the HW structure
457 *
458 * Initialize family-specific MAC parameters and function
459 * pointers.
460 **/
461static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
462{
463 struct e1000_hw *hw = &adapter->hw;
464 struct e1000_mac_info *mac = &hw->mac;
465
466 /* Set media type function pointer */
318a94d6 467 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 468
469 /* Set mta register count */
470 mac->mta_reg_count = 32;
471 /* Set rar entry count */
472 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
473 if (mac->type == e1000_ich8lan)
474 mac->rar_entry_count--;
475 /* Set if manageability features are enabled. */
564ea9bb 476 mac->arc_subsystem_valid = true;
f464ba87
BA		 477 /* Adaptive IFS supported */
478 mac->adaptive_ifs = true;
bc7f75fa 479
a4f58f54
BA		 480 /* LED operations */
481 switch (mac->type) {
482 case e1000_ich8lan:
483 case e1000_ich9lan:
484 case e1000_ich10lan:
485 /* ID LED init */
486 mac->ops.id_led_init = e1000e_id_led_init;
487 /* setup LED */
488 mac->ops.setup_led = e1000e_setup_led_generic;
489 /* cleanup LED */
490 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
491 /* turn on/off LED */
492 mac->ops.led_on = e1000_led_on_ich8lan;
493 mac->ops.led_off = e1000_led_off_ich8lan;
494 break;
495 case e1000_pchlan:
496 /* ID LED init */
497 mac->ops.id_led_init = e1000_id_led_init_pchlan;
498 /* setup LED */
499 mac->ops.setup_led = e1000_setup_led_pchlan;
500 /* cleanup LED */
501 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
502 /* turn on/off LED */
503 mac->ops.led_on = e1000_led_on_pchlan;
504 mac->ops.led_off = e1000_led_off_pchlan;
505 break;
506 default:
507 break;
508 }
509
bc7f75fa
AK		 510 /* Enable PCS Lock-loss workaround for ICH8 */
511 if (mac->type == e1000_ich8lan)
564ea9bb 512 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa
AK		 513
514 return 0;
515}
516
7d3cabbc
BA		 517/**
518 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
519 * @hw: pointer to the HW structure
520 *
521 * Checks to see of the link status of the hardware has changed. If a
522 * change in link status has been detected, then we read the PHY registers
523 * to get the current speed/duplex if link exists.
524 **/
525static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
526{
527 struct e1000_mac_info *mac = &hw->mac;
528 s32 ret_val;
529 bool link;
530
531 /*
532 * We only want to go out to the PHY registers to see if Auto-Neg
533 * has completed and/or if our link status has changed. The
534 * get_link_status flag is set upon receiving a Link Status
535 * Change or Rx Sequence Error interrupt.
536 */
537 if (!mac->get_link_status) {
538 ret_val = 0;
539 goto out;
540 }
541
7d3cabbc
BA		 542 /*
543 * First we want to see if the MII Status Register reports
544 * link. If so, then we want to get the current speed/duplex
545 * of the PHY.
546 */
547 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
548 if (ret_val)
549 goto out;
550
1d5846b9
BA		 551 if (hw->mac.type == e1000_pchlan) {
552 ret_val = e1000_k1_gig_workaround_hv(hw, link);
553 if (ret_val)
554 goto out;
555 }
556
7d3cabbc
BA		 557 if (!link)
558 goto out; /* No link detected */
559
560 mac->get_link_status = false;
561
562 if (hw->phy.type == e1000_phy_82578) {
563 ret_val = e1000_link_stall_workaround_hv(hw);
564 if (ret_val)
565 goto out;
566 }
567
568 /*
569 * Check if there was DownShift, must be checked
570 * immediately after link-up
571 */
572 e1000e_check_downshift(hw);
573
574 /*
575 * If we are forcing speed/duplex, then we simply return since
576 * we have already determined whether we have link or not.
577 */
578 if (!mac->autoneg) {
579 ret_val = -E1000_ERR_CONFIG;
580 goto out;
581 }
582
583 /*
584 * Auto-Neg is enabled. Auto Speed Detection takes care
585 * of MAC speed/duplex configuration. So we only need to
586 * configure Collision Distance in the MAC.
587 */
588 e1000e_config_collision_dist(hw);
589
590 /*
591 * Configure Flow Control now that Auto-Neg has completed.
592 * First, we need to restore the desired flow control
593 * settings because we may have had to re-autoneg with a
594 * different link partner.
595 */
596 ret_val = e1000e_config_fc_after_link_up(hw);
597 if (ret_val)
3bb99fe2 598 e_dbg("Error configuring flow control\n");
7d3cabbc
BA		 599
600out:
601 return ret_val;
602}
603
69e3fd8c 604static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 605{
606 struct e1000_hw *hw = &adapter->hw;
607 s32 rc;
608
609 rc = e1000_init_mac_params_ich8lan(adapter);
610 if (rc)
611 return rc;
612
613 rc = e1000_init_nvm_params_ich8lan(hw);
614 if (rc)
615 return rc;
616
a4f58f54
BA		 617 if (hw->mac.type == e1000_pchlan)
618 rc = e1000_init_phy_params_pchlan(hw);
619 else
620 rc = e1000_init_phy_params_ich8lan(hw);
bc7f75fa
AK		 621 if (rc)
622 return rc;
623
2adc55c9
BA		 624 if (adapter->hw.phy.type == e1000_phy_ife) {
625 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
626 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
627 }
628
bc7f75fa
AK		 629 if ((adapter->hw.mac.type == e1000_ich8lan) &&
630 (adapter->hw.phy.type == e1000_phy_igp_3))
631 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
632
633 return 0;
634}
635
717d438d 636static DEFINE_MUTEX(nvm_mutex);
717d438d 637
ca15df58
BA		 638/**
639 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
640 * @hw: pointer to the HW structure
641 *
642 * Acquires the mutex for performing NVM operations.
643 **/
644static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
645{
646 mutex_lock(&nvm_mutex);
647
648 return 0;
649}
650
651/**
652 * e1000_release_nvm_ich8lan - Release NVM mutex
653 * @hw: pointer to the HW structure
654 *
655 * Releases the mutex used while performing NVM operations.
656 **/
657static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
658{
659 mutex_unlock(&nvm_mutex);
660
661 return;
662}
663
664static DEFINE_MUTEX(swflag_mutex);
665
bc7f75fa
AK		 666/**
667 * e1000_acquire_swflag_ich8lan - Acquire software control flag
668 * @hw: pointer to the HW structure
669 *
ca15df58
BA		 670 * Acquires the software control flag for performing PHY and select
671 * MAC CSR accesses.
bc7f75fa
AK		 672 **/
673static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
674{
373a88d7
BA		 675 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
676 s32 ret_val = 0;
bc7f75fa 677
ca15df58 678 mutex_lock(&swflag_mutex);
717d438d 679
bc7f75fa
AK		 680 while (timeout) {
681 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 682 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
683 break;
bc7f75fa 684
373a88d7
BA		 685 mdelay(1);
686 timeout--;
687 }
688
689 if (!timeout) {
3bb99fe2 690 e_dbg("SW/FW/HW has locked the resource for too long.\n");
373a88d7
BA		 691 ret_val = -E1000_ERR_CONFIG;
692 goto out;
693 }
694
53ac5a88 695 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 696
697 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
698 ew32(EXTCNF_CTRL, extcnf_ctrl);
699
700 while (timeout) {
701 extcnf_ctrl = er32(EXTCNF_CTRL);
702 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
703 break;
a4f58f54 704
bc7f75fa
AK		 705 mdelay(1);
706 timeout--;
707 }
708
709 if (!timeout) {
3bb99fe2 710 e_dbg("Failed to acquire the semaphore.\n");
2e2e8d53
BA		 711 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
712 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 713 ret_val = -E1000_ERR_CONFIG;
714 goto out;
bc7f75fa
AK		 715 }
716
373a88d7
BA		 717out:
718 if (ret_val)
ca15df58 719 mutex_unlock(&swflag_mutex);
373a88d7
BA		 720
721 return ret_val;
bc7f75fa
AK		 722}
723
724/**
725 * e1000_release_swflag_ich8lan - Release software control flag
726 * @hw: pointer to the HW structure
727 *
ca15df58
BA		 728 * Releases the software control flag for performing PHY and select
729 * MAC CSR accesses.
bc7f75fa
AK		 730 **/
731static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
732{
733 u32 extcnf_ctrl;
734
735 extcnf_ctrl = er32(EXTCNF_CTRL);
736 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
737 ew32(EXTCNF_CTRL, extcnf_ctrl);
717d438d 738
ca15df58
BA		 739 mutex_unlock(&swflag_mutex);
740
741 return;
bc7f75fa
AK		 742}
743
4662e82b
BA		 744/**
745 * e1000_check_mng_mode_ich8lan - Checks management mode
746 * @hw: pointer to the HW structure
747 *
748 * This checks if the adapter has manageability enabled.
749 * This is a function pointer entry point only called by read/write
750 * routines for the PHY and NVM parts.
751 **/
752static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
753{
a708dd88
BA		 754 u32 fwsm;
755
756 fwsm = er32(FWSM);
4662e82b
BA		 757
758 return (fwsm & E1000_FWSM_MODE_MASK) ==
759 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
760}
761
bc7f75fa
AK		 762/**
763 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
764 * @hw: pointer to the HW structure
765 *
766 * Checks if firmware is blocking the reset of the PHY.
767 * This is a function pointer entry point only called by
768 * reset routines.
769 **/
770static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
771{
772 u32 fwsm;
773
774 fwsm = er32(FWSM);
775
776 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
777}
778
f523d211
BA		 779/**
780 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
781 * @hw: pointer to the HW structure
782 *
783 * SW should configure the LCD from the NVM extended configuration region
784 * as a workaround for certain parts.
785 **/
786static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
787{
788 struct e1000_phy_info *phy = &hw->phy;
789 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
790 s32 ret_val;
791 u16 word_addr, reg_data, reg_addr, phy_page = 0;
792
94d8186a 793 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 794 if (ret_val)
795 return ret_val;
796
797 /*
798 * Initialize the PHY from the NVM on ICH platforms. This
799 * is needed due to an issue where the NVM configuration is
800 * not properly autoloaded after power transitions.
801 * Therefore, after each PHY reset, we will load the
802 * configuration data out of the NVM manually.
803 */
804 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
805 (hw->mac.type == e1000_pchlan)) {
806 struct e1000_adapter *adapter = hw->adapter;
807
808 /* Check if SW needs to configure the PHY */
809 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
810 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
811 (hw->mac.type == e1000_pchlan))
812 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
813 else
814 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
815
816 data = er32(FEXTNVM);
817 if (!(data & sw_cfg_mask))
818 goto out;
819
820 /* Wait for basic configuration completes before proceeding */
821 e1000_lan_init_done_ich8lan(hw);
822
823 /*
824 * Make sure HW does not configure LCD from PHY
825 * extended configuration before SW configuration
826 */
827 data = er32(EXTCNF_CTRL);
828 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
829 goto out;
830
831 cnf_size = er32(EXTCNF_SIZE);
832 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
833 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
834 if (!cnf_size)
835 goto out;
836
837 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
838 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
839
840 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
841 (hw->mac.type == e1000_pchlan)) {
842 /*
843 * HW configures the SMBus address and LEDs when the
844 * OEM and LCD Write Enable bits are set in the NVM.
845 * When both NVM bits are cleared, SW will configure
846 * them instead.
847 */
848 data = er32(STRAP);
849 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
850 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
851 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
852 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
853 reg_data);
854 if (ret_val)
855 goto out;
856
857 data = er32(LEDCTL);
858 ret_val = e1000_write_phy_reg_hv_locked(hw,
859 HV_LED_CONFIG,
860 (u16)data);
861 if (ret_val)
862 goto out;
863 }
864 /* Configure LCD from extended configuration region. */
865
866 /* cnf_base_addr is in DWORD */
867 word_addr = (u16)(cnf_base_addr << 1);
868
869 for (i = 0; i < cnf_size; i++) {
870 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
871 &reg_data);
872 if (ret_val)
873 goto out;
874
875 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
876 1, &reg_addr);
877 if (ret_val)
878 goto out;
879
880 /* Save off the PHY page for future writes. */
881 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
882 phy_page = reg_data;
883 continue;
884 }
885
886 reg_addr &= PHY_REG_MASK;
887 reg_addr |= phy_page;
888
94d8186a 889 ret_val = phy->ops.write_reg_locked(hw,
f523d211
BA		 890 (u32)reg_addr,
891 reg_data);
892 if (ret_val)
893 goto out;
894 }
895 }
896
897out:
94d8186a 898 hw->phy.ops.release(hw);
f523d211
BA		 899 return ret_val;
900}
901
1d5846b9
BA		 902/**
903 * e1000_k1_gig_workaround_hv - K1 Si workaround
904 * @hw: pointer to the HW structure
905 * @link: link up bool flag
906 *
907 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
908 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
909 * If link is down, the function will restore the default K1 setting located
910 * in the NVM.
911 **/
912static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
913{
914 s32 ret_val = 0;
915 u16 status_reg = 0;
916 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
917
918 if (hw->mac.type != e1000_pchlan)
919 goto out;
920
921 /* Wrap the whole flow with the sw flag */
94d8186a 922 ret_val = hw->phy.ops.acquire(hw);
1d5846b9
BA		 923 if (ret_val)
924 goto out;
925
926 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
927 if (link) {
928 if (hw->phy.type == e1000_phy_82578) {
94d8186a 929 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1d5846b9
BA		 930 &status_reg);
931 if (ret_val)
932 goto release;
933
934 status_reg &= BM_CS_STATUS_LINK_UP |
935 BM_CS_STATUS_RESOLVED |
936 BM_CS_STATUS_SPEED_MASK;
937
938 if (status_reg == (BM_CS_STATUS_LINK_UP |
939 BM_CS_STATUS_RESOLVED |
940 BM_CS_STATUS_SPEED_1000))
941 k1_enable = false;
942 }
943
944 if (hw->phy.type == e1000_phy_82577) {
94d8186a 945 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1d5846b9
BA		 946 &status_reg);
947 if (ret_val)
948 goto release;
949
950 status_reg &= HV_M_STATUS_LINK_UP |
951 HV_M_STATUS_AUTONEG_COMPLETE |
952 HV_M_STATUS_SPEED_MASK;
953
954 if (status_reg == (HV_M_STATUS_LINK_UP |
955 HV_M_STATUS_AUTONEG_COMPLETE |
956 HV_M_STATUS_SPEED_1000))
957 k1_enable = false;
958 }
959
960 /* Link stall fix for link up */
94d8186a 961 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 962 0x0100);
963 if (ret_val)
964 goto release;
965
966 } else {
967 /* Link stall fix for link down */
94d8186a 968 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 969 0x4100);
970 if (ret_val)
971 goto release;
972 }
973
974 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
975
976release:
94d8186a 977 hw->phy.ops.release(hw);
1d5846b9
BA		 978out:
979 return ret_val;
980}
981
982/**
983 * e1000_configure_k1_ich8lan - Configure K1 power state
984 * @hw: pointer to the HW structure
985 * @enable: K1 state to configure
986 *
987 * Configure the K1 power state based on the provided parameter.
988 * Assumes semaphore already acquired.
989 *
990 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
991 **/
bb436b20 992s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9
BA		 993{
994 s32 ret_val = 0;
995 u32 ctrl_reg = 0;
996 u32 ctrl_ext = 0;
997 u32 reg = 0;
998 u16 kmrn_reg = 0;
999
1000 ret_val = e1000e_read_kmrn_reg_locked(hw,
1001 E1000_KMRNCTRLSTA_K1_CONFIG,
1002 &kmrn_reg);
1003 if (ret_val)
1004 goto out;
1005
1006 if (k1_enable)
1007 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1008 else
1009 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1010
1011 ret_val = e1000e_write_kmrn_reg_locked(hw,
1012 E1000_KMRNCTRLSTA_K1_CONFIG,
1013 kmrn_reg);
1014 if (ret_val)
1015 goto out;
1016
1017 udelay(20);
1018 ctrl_ext = er32(CTRL_EXT);
1019 ctrl_reg = er32(CTRL);
1020
1021 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1022 reg |= E1000_CTRL_FRCSPD;
1023 ew32(CTRL, reg);
1024
1025 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1026 udelay(20);
1027 ew32(CTRL, ctrl_reg);
1028 ew32(CTRL_EXT, ctrl_ext);
1029 udelay(20);
1030
1031out:
1032 return ret_val;
1033}
1034
f523d211
BA		 1035/**
1036 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1037 * @hw: pointer to the HW structure
1038 * @d0_state: boolean if entering d0 or d3 device state
1039 *
1040 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1041 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1042 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1043 **/
1044static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1045{
1046 s32 ret_val = 0;
1047 u32 mac_reg;
1048 u16 oem_reg;
1049
1050 if (hw->mac.type != e1000_pchlan)
1051 return ret_val;
1052
94d8186a 1053 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 1054 if (ret_val)
1055 return ret_val;
1056
1057 mac_reg = er32(EXTCNF_CTRL);
1058 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1059 goto out;
1060
1061 mac_reg = er32(FEXTNVM);
1062 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1063 goto out;
1064
1065 mac_reg = er32(PHY_CTRL);
1066
94d8186a 1067 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211
BA		 1068 if (ret_val)
1069 goto out;
1070
1071 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1072
1073 if (d0_state) {
1074 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1075 oem_reg |= HV_OEM_BITS_GBE_DIS;
1076
1077 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1078 oem_reg |= HV_OEM_BITS_LPLU;
1079 } else {
1080 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1081 oem_reg |= HV_OEM_BITS_GBE_DIS;
1082
1083 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1084 oem_reg |= HV_OEM_BITS_LPLU;
1085 }
1086 /* Restart auto-neg to activate the bits */
818f3331
BA		 1087 if (!e1000_check_reset_block(hw))
1088 oem_reg |= HV_OEM_BITS_RESTART_AN;
94d8186a 1089 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
f523d211
BA		 1090
1091out:
94d8186a 1092 hw->phy.ops.release(hw);
f523d211
BA		 1093
1094 return ret_val;
1095}
1096
1097
fddaa1af
BA		 1098/**
1099 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1100 * @hw: pointer to the HW structure
1101 **/
1102static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1103{
1104 s32 ret_val;
1105 u16 data;
1106
1107 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1108 if (ret_val)
1109 return ret_val;
1110
1111 data |= HV_KMRN_MDIO_SLOW;
1112
1113 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1114
1115 return ret_val;
1116}
1117
a4f58f54
BA		 1118/**
1119 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1120 * done after every PHY reset.
1121 **/
1122static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1123{
1124 s32 ret_val = 0;
baf86c9d 1125 u16 phy_data;
a4f58f54
BA		 1126
1127 if (hw->mac.type != e1000_pchlan)
1128 return ret_val;
1129
fddaa1af
BA		 1130 /* Set MDIO slow mode before any other MDIO access */
1131 if (hw->phy.type == e1000_phy_82577) {
1132 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1133 if (ret_val)
1134 goto out;
1135 }
1136
a4f58f54
BA		 1137 if (((hw->phy.type == e1000_phy_82577) &&
1138 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1139 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1140 /* Disable generation of early preamble */
1141 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1142 if (ret_val)
1143 return ret_val;
1144
1145 /* Preamble tuning for SSC */
1146 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1147 if (ret_val)
1148 return ret_val;
1149 }
1150
1151 if (hw->phy.type == e1000_phy_82578) {
1152 /*
1153 * Return registers to default by doing a soft reset then
1154 * writing 0x3140 to the control register.
1155 */
1156 if (hw->phy.revision < 2) {
1157 e1000e_phy_sw_reset(hw);
1158 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1159 }
1160 }
1161
1162 /* Select page 0 */
94d8186a 1163 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 1164 if (ret_val)
1165 return ret_val;
1d5846b9 1166
a4f58f54 1167 hw->phy.addr = 1;
1d5846b9 1168 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
baf86c9d 1169 hw->phy.ops.release(hw);
1d5846b9
BA		 1170 if (ret_val)
1171 goto out;
a4f58f54 1172
1d5846b9
BA		 1173 /*
1174 * Configure the K1 Si workaround during phy reset assuming there is
1175 * link so that it disables K1 if link is in 1Gbps.
1176 */
1177 ret_val = e1000_k1_gig_workaround_hv(hw, true);
baf86c9d
BA		 1178 if (ret_val)
1179 goto out;
1d5846b9 1180
baf86c9d
BA		 1181 /* Workaround for link disconnects on a busy hub in half duplex */
1182 ret_val = hw->phy.ops.acquire(hw);
1183 if (ret_val)
1184 goto out;
1185 ret_val = hw->phy.ops.read_reg_locked(hw,
1186 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1187 &phy_data);
1188 if (ret_val)
1189 goto release;
1190 ret_val = hw->phy.ops.write_reg_locked(hw,
1191 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1192 phy_data & 0x00FF);
1193release:
1194 hw->phy.ops.release(hw);
1d5846b9 1195out:
a4f58f54
BA		 1196 return ret_val;
1197}
1198
fc0c7760
BA		 1199/**
1200 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1201 * @hw: pointer to the HW structure
1202 *
1203 * Check the appropriate indication the MAC has finished configuring the
1204 * PHY after a software reset.
1205 **/
1206static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1207{
1208 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1209
1210 /* Wait for basic configuration completes before proceeding */
1211 do {
1212 data = er32(STATUS);
1213 data &= E1000_STATUS_LAN_INIT_DONE;
1214 udelay(100);
1215 } while ((!data) && --loop);
1216
1217 /*
1218 * If basic configuration is incomplete before the above loop
1219 * count reaches 0, loading the configuration from NVM will
1220 * leave the PHY in a bad state possibly resulting in no link.
1221 */
1222 if (loop == 0)
3bb99fe2 1223 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 1224
1225 /* Clear the Init Done bit for the next init event */
1226 data = er32(STATUS);
1227 data &= ~E1000_STATUS_LAN_INIT_DONE;
1228 ew32(STATUS, data);
1229}
1230
bc7f75fa
AK		 1231/**
1232 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1233 * @hw: pointer to the HW structure
1234 *
1235 * Resets the PHY
1236 * This is a function pointer entry point called by drivers
1237 * or other shared routines.
1238 **/
1239static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1240{
f523d211
BA		 1241 s32 ret_val = 0;
1242 u16 reg;
bc7f75fa
AK		 1243
1244 ret_val = e1000e_phy_hw_reset_generic(hw);
1245 if (ret_val)
1246 return ret_val;
1247
fc0c7760
BA		 1248 /* Allow time for h/w to get to a quiescent state after reset */
1249 mdelay(10);
1250
fddaa1af 1251 /* Perform any necessary post-reset workarounds */
a4f58f54
BA		 1252 if (hw->mac.type == e1000_pchlan) {
1253 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1254 if (ret_val)
1255 return ret_val;
1256 }
1257
db2932ec
BA		 1258 /* Dummy read to clear the phy wakeup bit after lcd reset */
1259 if (hw->mac.type == e1000_pchlan)
1260 e1e_rphy(hw, BM_WUC, &reg);
1261
f523d211
BA		 1262 /* Configure the LCD with the extended configuration region in NVM */
1263 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1264 if (ret_val)
1265 goto out;
bc7f75fa 1266
f523d211
BA		 1267 /* Configure the LCD with the OEM bits in NVM */
1268 if (hw->mac.type == e1000_pchlan)
1269 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 1270
f523d211 1271out:
bc7f75fa
AK		 1272 return 0;
1273}
1274
fa2ce13c
BA		 1275/**
1276 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1277 * @hw: pointer to the HW structure
1278 * @active: true to enable LPLU, false to disable
1279 *
1280 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1281 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1282 * the phy speed. This function will manually set the LPLU bit and restart
1283 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1284 * since it configures the same bit.
1285 **/
1286static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1287{
1288 s32 ret_val = 0;
1289 u16 oem_reg;
1290
1291 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1292 if (ret_val)
1293 goto out;
1294
1295 if (active)
1296 oem_reg |= HV_OEM_BITS_LPLU;
1297 else
1298 oem_reg &= ~HV_OEM_BITS_LPLU;
1299
1300 oem_reg |= HV_OEM_BITS_RESTART_AN;
1301 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1302
1303out:
1304 return ret_val;
1305}
1306
bc7f75fa
AK		 1307/**
1308 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1309 * @hw: pointer to the HW structure
564ea9bb 1310 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1311 *
1312 * Sets the LPLU D0 state according to the active flag. When
1313 * activating LPLU this function also disables smart speed
1314 * and vice versa. LPLU will not be activated unless the
1315 * device autonegotiation advertisement meets standards of
1316 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1317 * This is a function pointer entry point only called by
1318 * PHY setup routines.
1319 **/
1320static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1321{
1322 struct e1000_phy_info *phy = &hw->phy;
1323 u32 phy_ctrl;
1324 s32 ret_val = 0;
1325 u16 data;
1326
97ac8cae 1327 if (phy->type == e1000_phy_ife)
bc7f75fa
AK		 1328 return ret_val;
1329
1330 phy_ctrl = er32(PHY_CTRL);
1331
1332 if (active) {
1333 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1334 ew32(PHY_CTRL, phy_ctrl);
1335
60f1292f
BA		 1336 if (phy->type != e1000_phy_igp_3)
1337 return 0;
1338
ad68076e
BA		 1339 /*
1340 * Call gig speed drop workaround on LPLU before accessing
1341 * any PHY registers
1342 */
60f1292f 1343 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1344 e1000e_gig_downshift_workaround_ich8lan(hw);
1345
1346 /* When LPLU is enabled, we should disable SmartSpeed */
1347 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1348 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1349 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1350 if (ret_val)
1351 return ret_val;
1352 } else {
1353 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1354 ew32(PHY_CTRL, phy_ctrl);
1355
60f1292f
BA		 1356 if (phy->type != e1000_phy_igp_3)
1357 return 0;
1358
ad68076e
BA		 1359 /*
1360 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1361 * during Dx states where the power conservation is most
1362 * important. During driver activity we should enable
ad68076e
BA		 1363 * SmartSpeed, so performance is maintained.
1364 */
bc7f75fa
AK		 1365 if (phy->smart_speed == e1000_smart_speed_on) {
1366 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1367 &data);
bc7f75fa
AK		 1368 if (ret_val)
1369 return ret_val;
1370
1371 data |= IGP01E1000_PSCFR_SMART_SPEED;
1372 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1373 data);
bc7f75fa
AK		 1374 if (ret_val)
1375 return ret_val;
1376 } else if (phy->smart_speed == e1000_smart_speed_off) {
1377 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1378 &data);
bc7f75fa
AK		 1379 if (ret_val)
1380 return ret_val;
1381
1382 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1383 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1384 data);
bc7f75fa
AK		 1385 if (ret_val)
1386 return ret_val;
1387 }
1388 }
1389
1390 return 0;
1391}
1392
1393/**
1394 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1395 * @hw: pointer to the HW structure
564ea9bb 1396 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1397 *
1398 * Sets the LPLU D3 state according to the active flag. When
1399 * activating LPLU this function also disables smart speed
1400 * and vice versa. LPLU will not be activated unless the
1401 * device autonegotiation advertisement meets standards of
1402 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1403 * This is a function pointer entry point only called by
1404 * PHY setup routines.
1405 **/
1406static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1407{
1408 struct e1000_phy_info *phy = &hw->phy;
1409 u32 phy_ctrl;
1410 s32 ret_val;
1411 u16 data;
1412
1413 phy_ctrl = er32(PHY_CTRL);
1414
1415 if (!active) {
1416 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1417 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 1418
1419 if (phy->type != e1000_phy_igp_3)
1420 return 0;
1421
ad68076e
BA		 1422 /*
1423 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1424 * during Dx states where the power conservation is most
1425 * important. During driver activity we should enable
ad68076e
BA		 1426 * SmartSpeed, so performance is maintained.
1427 */
bc7f75fa 1428 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 1429 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1430 &data);
bc7f75fa
AK		 1431 if (ret_val)
1432 return ret_val;
1433
1434 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1435 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1436 data);
bc7f75fa
AK		 1437 if (ret_val)
1438 return ret_val;
1439 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 1440 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1441 &data);
bc7f75fa
AK		 1442 if (ret_val)
1443 return ret_val;
1444
1445 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1446 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1447 data);
bc7f75fa
AK		 1448 if (ret_val)
1449 return ret_val;
1450 }
1451 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1452 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1453 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1454 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1455 ew32(PHY_CTRL, phy_ctrl);
1456
60f1292f
BA		 1457 if (phy->type != e1000_phy_igp_3)
1458 return 0;
1459
ad68076e
BA		 1460 /*
1461 * Call gig speed drop workaround on LPLU before accessing
1462 * any PHY registers
1463 */
60f1292f 1464 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1465 e1000e_gig_downshift_workaround_ich8lan(hw);
1466
1467 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 1468 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 1469 if (ret_val)
1470 return ret_val;
1471
1472 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 1473 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 1474 }
1475
1476 return 0;
1477}
1478
f4187b56
BA		 1479/**
1480 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1481 * @hw: pointer to the HW structure
1482 * @bank: pointer to the variable that returns the active bank
1483 *
1484 * Reads signature byte from the NVM using the flash access registers.
e243455d 1485 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 1486 **/
1487static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1488{
e243455d 1489 u32 eecd;
f4187b56 1490 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 1491 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1492 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
e243455d
BA		 1493 u8 sig_byte = 0;
1494 s32 ret_val = 0;
f4187b56 1495
e243455d
BA		 1496 switch (hw->mac.type) {
1497 case e1000_ich8lan:
1498 case e1000_ich9lan:
1499 eecd = er32(EECD);
1500 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1501 E1000_EECD_SEC1VAL_VALID_MASK) {
1502 if (eecd & E1000_EECD_SEC1VAL)
1503 *bank = 1;
1504 else
1505 *bank = 0;
1506
1507 return 0;
1508 }
3bb99fe2 1509 e_dbg("Unable to determine valid NVM bank via EEC - "
e243455d
BA		 1510 "reading flash signature\n");
1511 /* fall-thru */
1512 default:
1513 /* set bank to 0 in case flash read fails */
1514 *bank = 0;
1515
1516 /* Check bank 0 */
1517 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1518 &sig_byte);
1519 if (ret_val)
1520 return ret_val;
1521 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1522 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 1523 *bank = 0;
e243455d
BA		 1524 return 0;
1525 }
f4187b56 1526
e243455d
BA		 1527 /* Check bank 1 */
1528 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1529 bank1_offset,
1530 &sig_byte);
1531 if (ret_val)
1532 return ret_val;
1533 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1534 E1000_ICH_NVM_SIG_VALUE) {
1535 *bank = 1;
1536 return 0;
f4187b56 1537 }
e243455d 1538
3bb99fe2 1539 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 1540 return -E1000_ERR_NVM;
f4187b56
BA		 1541 }
1542
1543 return 0;
1544}
1545
bc7f75fa
AK		 1546/**
1547 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1548 * @hw: pointer to the HW structure
1549 * @offset: The offset (in bytes) of the word(s) to read.
1550 * @words: Size of data to read in words
1551 * @data: Pointer to the word(s) to read at offset.
1552 *
1553 * Reads a word(s) from the NVM using the flash access registers.
1554 **/
1555static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1556 u16 *data)
1557{
1558 struct e1000_nvm_info *nvm = &hw->nvm;
1559 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1560 u32 act_offset;
148675a7 1561 s32 ret_val = 0;
f4187b56 1562 u32 bank = 0;
bc7f75fa
AK		 1563 u16 i, word;
1564
1565 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1566 (words == 0)) {
3bb99fe2 1567 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 1568 ret_val = -E1000_ERR_NVM;
1569 goto out;
bc7f75fa
AK		 1570 }
1571
94d8186a 1572 nvm->ops.acquire(hw);
bc7f75fa 1573
f4187b56 1574 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 1575 if (ret_val) {
3bb99fe2 1576 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 1577 bank = 0;
1578 }
f4187b56
BA		 1579
1580 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 1581 act_offset += offset;
1582
148675a7 1583 ret_val = 0;
bc7f75fa
AK		 1584 for (i = 0; i < words; i++) {
1585 if ((dev_spec->shadow_ram) &&
1586 (dev_spec->shadow_ram[offset+i].modified)) {
1587 data[i] = dev_spec->shadow_ram[offset+i].value;
1588 } else {
1589 ret_val = e1000_read_flash_word_ich8lan(hw,
1590 act_offset + i,
1591 &word);
1592 if (ret_val)
1593 break;
1594 data[i] = word;
1595 }
1596 }
1597
94d8186a 1598 nvm->ops.release(hw);
bc7f75fa 1599
e243455d
BA		 1600out:
1601 if (ret_val)
3bb99fe2 1602 e_dbg("NVM read error: %d\n", ret_val);
e243455d 1603
bc7f75fa
AK		 1604 return ret_val;
1605}
1606
1607/**
1608 * e1000_flash_cycle_init_ich8lan - Initialize flash
1609 * @hw: pointer to the HW structure
1610 *
1611 * This function does initial flash setup so that a new read/write/erase cycle
1612 * can be started.
1613 **/
1614static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1615{
1616 union ich8_hws_flash_status hsfsts;
1617 s32 ret_val = -E1000_ERR_NVM;
1618 s32 i = 0;
1619
1620 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1621
1622 /* Check if the flash descriptor is valid */
1623 if (hsfsts.hsf_status.fldesvalid == 0) {
3bb99fe2 1624 e_dbg("Flash descriptor invalid. "
bc7f75fa
AK		 1625 "SW Sequencing must be used.");
1626 return -E1000_ERR_NVM;
1627 }
1628
1629 /* Clear FCERR and DAEL in hw status by writing 1 */
1630 hsfsts.hsf_status.flcerr = 1;
1631 hsfsts.hsf_status.dael = 1;
1632
1633 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1634
ad68076e
BA		 1635 /*
1636 * Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 1637 * bit to check against, in order to start a new cycle or
1638 * FDONE bit should be changed in the hardware so that it
489815ce 1639 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 1640 * indication whether a cycle is in progress or has been
1641 * completed.
1642 */
1643
1644 if (hsfsts.hsf_status.flcinprog == 0) {
ad68076e
BA		 1645 /*
1646 * There is no cycle running at present,
5ff5b664 1647 * so we can start a cycle.
ad68076e
BA		 1648 * Begin by setting Flash Cycle Done.
1649 */
bc7f75fa
AK		 1650 hsfsts.hsf_status.flcdone = 1;
1651 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1652 ret_val = 0;
1653 } else {
ad68076e 1654 /*
5ff5b664 1655 * Otherwise poll for sometime so the current
ad68076e
BA		 1656 * cycle has a chance to end before giving up.
1657 */
bc7f75fa
AK		 1658 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1659 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1660 if (hsfsts.hsf_status.flcinprog == 0) {
1661 ret_val = 0;
1662 break;
1663 }
1664 udelay(1);
1665 }
1666 if (ret_val == 0) {
ad68076e
BA		 1667 /*
1668 * Successful in waiting for previous cycle to timeout,
1669 * now set the Flash Cycle Done.
1670 */
bc7f75fa
AK		 1671 hsfsts.hsf_status.flcdone = 1;
1672 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1673 } else {
3bb99fe2 1674 e_dbg("Flash controller busy, cannot get access");
bc7f75fa
AK		 1675 }
1676 }
1677
1678 return ret_val;
1679}
1680
1681/**
1682 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1683 * @hw: pointer to the HW structure
1684 * @timeout: maximum time to wait for completion
1685 *
1686 * This function starts a flash cycle and waits for its completion.
1687 **/
1688static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1689{
1690 union ich8_hws_flash_ctrl hsflctl;
1691 union ich8_hws_flash_status hsfsts;
1692 s32 ret_val = -E1000_ERR_NVM;
1693 u32 i = 0;
1694
1695 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1696 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1697 hsflctl.hsf_ctrl.flcgo = 1;
1698 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1699
1700 /* wait till FDONE bit is set to 1 */
1701 do {
1702 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1703 if (hsfsts.hsf_status.flcdone == 1)
1704 break;
1705 udelay(1);
1706 } while (i++ < timeout);
1707
1708 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1709 return 0;
1710
1711 return ret_val;
1712}
1713
1714/**
1715 * e1000_read_flash_word_ich8lan - Read word from flash
1716 * @hw: pointer to the HW structure
1717 * @offset: offset to data location
1718 * @data: pointer to the location for storing the data
1719 *
1720 * Reads the flash word at offset into data. Offset is converted
1721 * to bytes before read.
1722 **/
1723static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1724 u16 *data)
1725{
1726 /* Must convert offset into bytes. */
1727 offset <<= 1;
1728
1729 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1730}
1731
f4187b56
BA		 1732/**
1733 * e1000_read_flash_byte_ich8lan - Read byte from flash
1734 * @hw: pointer to the HW structure
1735 * @offset: The offset of the byte to read.
1736 * @data: Pointer to a byte to store the value read.
1737 *
1738 * Reads a single byte from the NVM using the flash access registers.
1739 **/
1740static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1741 u8 *data)
1742{
1743 s32 ret_val;
1744 u16 word = 0;
1745
1746 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1747 if (ret_val)
1748 return ret_val;
1749
1750 *data = (u8)word;
1751
1752 return 0;
1753}
1754
bc7f75fa
AK		 1755/**
1756 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1757 * @hw: pointer to the HW structure
1758 * @offset: The offset (in bytes) of the byte or word to read.
1759 * @size: Size of data to read, 1=byte 2=word
1760 * @data: Pointer to the word to store the value read.
1761 *
1762 * Reads a byte or word from the NVM using the flash access registers.
1763 **/
1764static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1765 u8 size, u16 *data)
1766{
1767 union ich8_hws_flash_status hsfsts;
1768 union ich8_hws_flash_ctrl hsflctl;
1769 u32 flash_linear_addr;
1770 u32 flash_data = 0;
1771 s32 ret_val = -E1000_ERR_NVM;
1772 u8 count = 0;
1773
1774 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1775 return -E1000_ERR_NVM;
1776
1777 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1778 hw->nvm.flash_base_addr;
1779
1780 do {
1781 udelay(1);
1782 /* Steps */
1783 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1784 if (ret_val != 0)
1785 break;
1786
1787 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1788 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1789 hsflctl.hsf_ctrl.fldbcount = size - 1;
1790 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1791 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1792
1793 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1794
1795 ret_val = e1000_flash_cycle_ich8lan(hw,
1796 ICH_FLASH_READ_COMMAND_TIMEOUT);
1797
ad68076e
BA		 1798 /*
1799 * Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 1800 * and try the whole sequence a few more times, else
1801 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 1802 * least significant byte first msb to lsb
1803 */
bc7f75fa
AK		 1804 if (ret_val == 0) {
1805 flash_data = er32flash(ICH_FLASH_FDATA0);
1806 if (size == 1) {
1807 *data = (u8)(flash_data & 0x000000FF);
1808 } else if (size == 2) {
1809 *data = (u16)(flash_data & 0x0000FFFF);
1810 }
1811 break;
1812 } else {
ad68076e
BA		 1813 /*
1814 * If we've gotten here, then things are probably
bc7f75fa
AK		 1815 * completely hosed, but if the error condition is
1816 * detected, it won't hurt to give it another try...
1817 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1818 */
1819 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1820 if (hsfsts.hsf_status.flcerr == 1) {
1821 /* Repeat for some time before giving up. */
1822 continue;
1823 } else if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 1824 e_dbg("Timeout error - flash cycle "
bc7f75fa
AK		 1825 "did not complete.");
1826 break;
1827 }
1828 }
1829 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1830
1831 return ret_val;
1832}
1833
1834/**
1835 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1836 * @hw: pointer to the HW structure
1837 * @offset: The offset (in bytes) of the word(s) to write.
1838 * @words: Size of data to write in words
1839 * @data: Pointer to the word(s) to write at offset.
1840 *
1841 * Writes a byte or word to the NVM using the flash access registers.
1842 **/
1843static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1844 u16 *data)
1845{
1846 struct e1000_nvm_info *nvm = &hw->nvm;
1847 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 1848 u16 i;
1849
1850 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1851 (words == 0)) {
3bb99fe2 1852 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 1853 return -E1000_ERR_NVM;
1854 }
1855
94d8186a 1856 nvm->ops.acquire(hw);
ca15df58 1857
bc7f75fa 1858 for (i = 0; i < words; i++) {
564ea9bb 1859 dev_spec->shadow_ram[offset+i].modified = true;
bc7f75fa
AK		 1860 dev_spec->shadow_ram[offset+i].value = data[i];
1861 }
1862
94d8186a 1863 nvm->ops.release(hw);
ca15df58 1864
bc7f75fa
AK		 1865 return 0;
1866}
1867
1868/**
1869 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1870 * @hw: pointer to the HW structure
1871 *
1872 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1873 * which writes the checksum to the shadow ram. The changes in the shadow
1874 * ram are then committed to the EEPROM by processing each bank at a time
1875 * checking for the modified bit and writing only the pending changes.
489815ce 1876 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 1877 * future writes.
1878 **/
1879static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1880{
1881 struct e1000_nvm_info *nvm = &hw->nvm;
1882 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 1883 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa
AK		 1884 s32 ret_val;
1885 u16 data;
1886
1887 ret_val = e1000e_update_nvm_checksum_generic(hw);
1888 if (ret_val)
e243455d 1889 goto out;
bc7f75fa
AK		 1890
1891 if (nvm->type != e1000_nvm_flash_sw)
e243455d 1892 goto out;
bc7f75fa 1893
94d8186a 1894 nvm->ops.acquire(hw);
bc7f75fa 1895
ad68076e
BA		 1896 /*
1897 * We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 1898 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 1899 * is going to be written
1900 */
f4187b56 1901 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 1902 if (ret_val) {
3bb99fe2 1903 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 1904 bank = 0;
e243455d 1905 }
f4187b56
BA		 1906
1907 if (bank == 0) {
bc7f75fa
AK		 1908 new_bank_offset = nvm->flash_bank_size;
1909 old_bank_offset = 0;
e243455d
BA		 1910 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1911 if (ret_val) {
94d8186a 1912 nvm->ops.release(hw);
e243455d
BA		 1913 goto out;
1914 }
bc7f75fa
AK		 1915 } else {
1916 old_bank_offset = nvm->flash_bank_size;
1917 new_bank_offset = 0;
e243455d
BA		 1918 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1919 if (ret_val) {
94d8186a 1920 nvm->ops.release(hw);
e243455d
BA		 1921 goto out;
1922 }
bc7f75fa
AK		 1923 }
1924
1925 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
ad68076e
BA		 1926 /*
1927 * Determine whether to write the value stored
bc7f75fa 1928 * in the other NVM bank or a modified value stored
ad68076e
BA		 1929 * in the shadow RAM
1930 */
bc7f75fa
AK		 1931 if (dev_spec->shadow_ram[i].modified) {
1932 data = dev_spec->shadow_ram[i].value;
1933 } else {
e243455d
BA		 1934 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1935 old_bank_offset,
1936 &data);
1937 if (ret_val)
1938 break;
bc7f75fa
AK		 1939 }
1940
ad68076e
BA		 1941 /*
1942 * If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 1943 * (15:14) are 11b until the commit has completed.
1944 * This will allow us to write 10b which indicates the
1945 * signature is valid. We want to do this after the write
1946 * has completed so that we don't mark the segment valid
ad68076e
BA		 1947 * while the write is still in progress
1948 */
bc7f75fa
AK		 1949 if (i == E1000_ICH_NVM_SIG_WORD)
1950 data |= E1000_ICH_NVM_SIG_MASK;
1951
1952 /* Convert offset to bytes. */
1953 act_offset = (i + new_bank_offset) << 1;
1954
1955 udelay(100);
1956 /* Write the bytes to the new bank. */
1957 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1958 act_offset,
1959 (u8)data);
1960 if (ret_val)
1961 break;
1962
1963 udelay(100);
1964 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1965 act_offset + 1,
1966 (u8)(data >> 8));
1967 if (ret_val)
1968 break;
1969 }
1970
ad68076e
BA		 1971 /*
1972 * Don't bother writing the segment valid bits if sector
1973 * programming failed.
1974 */
bc7f75fa 1975 if (ret_val) {
4a770358 1976 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 1977 e_dbg("Flash commit failed.\n");
94d8186a 1978 nvm->ops.release(hw);
e243455d 1979 goto out;
bc7f75fa
AK		 1980 }
1981
ad68076e
BA		 1982 /*
1983 * Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 1984 * to 10b in word 0x13 , this can be done without an
1985 * erase as well since these bits are 11 to start with
ad68076e
BA		 1986 * and we need to change bit 14 to 0b
1987 */
bc7f75fa 1988 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d
BA		 1989 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1990 if (ret_val) {
94d8186a 1991 nvm->ops.release(hw);
e243455d
BA		 1992 goto out;
1993 }
bc7f75fa
AK		 1994 data &= 0xBFFF;
1995 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1996 act_offset * 2 + 1,
1997 (u8)(data >> 8));
1998 if (ret_val) {
94d8186a 1999 nvm->ops.release(hw);
e243455d 2000 goto out;
bc7f75fa
AK		 2001 }
2002
ad68076e
BA		 2003 /*
2004 * And invalidate the previously valid segment by setting
bc7f75fa
AK		 2005 * its signature word (0x13) high_byte to 0b. This can be
2006 * done without an erase because flash erase sets all bits
ad68076e
BA		 2007 * to 1's. We can write 1's to 0's without an erase
2008 */
bc7f75fa
AK		 2009 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2010 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2011 if (ret_val) {
94d8186a 2012 nvm->ops.release(hw);
e243455d 2013 goto out;
bc7f75fa
AK		 2014 }
2015
2016 /* Great! Everything worked, we can now clear the cached entries. */
2017 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 2018 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 2019 dev_spec->shadow_ram[i].value = 0xFFFF;
2020 }
2021
94d8186a 2022 nvm->ops.release(hw);
bc7f75fa 2023
ad68076e
BA		 2024 /*
2025 * Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 2026 * until after the next adapter reset.
2027 */
2028 e1000e_reload_nvm(hw);
2029 msleep(10);
2030
e243455d
BA		 2031out:
2032 if (ret_val)
3bb99fe2 2033 e_dbg("NVM update error: %d\n", ret_val);
e243455d 2034
bc7f75fa
AK		 2035 return ret_val;
2036}
2037
2038/**
2039 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2040 * @hw: pointer to the HW structure
2041 *
2042 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2043 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2044 * calculated, in which case we need to calculate the checksum and set bit 6.
2045 **/
2046static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2047{
2048 s32 ret_val;
2049 u16 data;
2050
ad68076e
BA		 2051 /*
2052 * Read 0x19 and check bit 6. If this bit is 0, the checksum
bc7f75fa
AK		 2053 * needs to be fixed. This bit is an indication that the NVM
2054 * was prepared by OEM software and did not calculate the
2055 * checksum...a likely scenario.
2056 */
2057 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2058 if (ret_val)
2059 return ret_val;
2060
2061 if ((data & 0x40) == 0) {
2062 data |= 0x40;
2063 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2064 if (ret_val)
2065 return ret_val;
2066 ret_val = e1000e_update_nvm_checksum(hw);
2067 if (ret_val)
2068 return ret_val;
2069 }
2070
2071 return e1000e_validate_nvm_checksum_generic(hw);
2072}
2073
4a770358
BA		 2074/**
2075 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2076 * @hw: pointer to the HW structure
2077 *
2078 * To prevent malicious write/erase of the NVM, set it to be read-only
2079 * so that the hardware ignores all write/erase cycles of the NVM via
2080 * the flash control registers. The shadow-ram copy of the NVM will
2081 * still be updated, however any updates to this copy will not stick
2082 * across driver reloads.
2083 **/
2084void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2085{
ca15df58 2086 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 2087 union ich8_flash_protected_range pr0;
2088 union ich8_hws_flash_status hsfsts;
2089 u32 gfpreg;
4a770358 2090
94d8186a 2091 nvm->ops.acquire(hw);
4a770358
BA		 2092
2093 gfpreg = er32flash(ICH_FLASH_GFPREG);
2094
2095 /* Write-protect GbE Sector of NVM */
2096 pr0.regval = er32flash(ICH_FLASH_PR0);
2097 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2098 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2099 pr0.range.wpe = true;
2100 ew32flash(ICH_FLASH_PR0, pr0.regval);
2101
2102 /*
2103 * Lock down a subset of GbE Flash Control Registers, e.g.
2104 * PR0 to prevent the write-protection from being lifted.
2105 * Once FLOCKDN is set, the registers protected by it cannot
2106 * be written until FLOCKDN is cleared by a hardware reset.
2107 */
2108 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2109 hsfsts.hsf_status.flockdn = true;
2110 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2111
94d8186a 2112 nvm->ops.release(hw);
4a770358
BA		 2113}
2114
bc7f75fa
AK		 2115/**
2116 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2117 * @hw: pointer to the HW structure
2118 * @offset: The offset (in bytes) of the byte/word to read.
2119 * @size: Size of data to read, 1=byte 2=word
2120 * @data: The byte(s) to write to the NVM.
2121 *
2122 * Writes one/two bytes to the NVM using the flash access registers.
2123 **/
2124static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2125 u8 size, u16 data)
2126{
2127 union ich8_hws_flash_status hsfsts;
2128 union ich8_hws_flash_ctrl hsflctl;
2129 u32 flash_linear_addr;
2130 u32 flash_data = 0;
2131 s32 ret_val;
2132 u8 count = 0;
2133
2134 if (size < 1 || size > 2 || data > size * 0xff ||
2135 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2136 return -E1000_ERR_NVM;
2137
2138 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2139 hw->nvm.flash_base_addr;
2140
2141 do {
2142 udelay(1);
2143 /* Steps */
2144 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2145 if (ret_val)
2146 break;
2147
2148 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2149 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2150 hsflctl.hsf_ctrl.fldbcount = size -1;
2151 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2152 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2153
2154 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2155
2156 if (size == 1)
2157 flash_data = (u32)data & 0x00FF;
2158 else
2159 flash_data = (u32)data;
2160
2161 ew32flash(ICH_FLASH_FDATA0, flash_data);
2162
ad68076e
BA		 2163 /*
2164 * check if FCERR is set to 1 , if set to 1, clear it
2165 * and try the whole sequence a few more times else done
2166 */
bc7f75fa
AK		 2167 ret_val = e1000_flash_cycle_ich8lan(hw,
2168 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2169 if (!ret_val)
2170 break;
2171
ad68076e
BA		 2172 /*
2173 * If we're here, then things are most likely
bc7f75fa
AK		 2174 * completely hosed, but if the error condition
2175 * is detected, it won't hurt to give it another
2176 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2177 */
2178 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2179 if (hsfsts.hsf_status.flcerr == 1)
2180 /* Repeat for some time before giving up. */
2181 continue;
2182 if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 2183 e_dbg("Timeout error - flash cycle "
bc7f75fa
AK		 2184 "did not complete.");
2185 break;
2186 }
2187 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2188
2189 return ret_val;
2190}
2191
2192/**
2193 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2194 * @hw: pointer to the HW structure
2195 * @offset: The index of the byte to read.
2196 * @data: The byte to write to the NVM.
2197 *
2198 * Writes a single byte to the NVM using the flash access registers.
2199 **/
2200static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2201 u8 data)
2202{
2203 u16 word = (u16)data;
2204
2205 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2206}
2207
2208/**
2209 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2210 * @hw: pointer to the HW structure
2211 * @offset: The offset of the byte to write.
2212 * @byte: The byte to write to the NVM.
2213 *
2214 * Writes a single byte to the NVM using the flash access registers.
2215 * Goes through a retry algorithm before giving up.
2216 **/
2217static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2218 u32 offset, u8 byte)
2219{
2220 s32 ret_val;
2221 u16 program_retries;
2222
2223 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2224 if (!ret_val)
2225 return ret_val;
2226
2227 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 2228 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
bc7f75fa
AK		 2229 udelay(100);
2230 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2231 if (!ret_val)
2232 break;
2233 }
2234 if (program_retries == 100)
2235 return -E1000_ERR_NVM;
2236
2237 return 0;
2238}
2239
2240/**
2241 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2242 * @hw: pointer to the HW structure
2243 * @bank: 0 for first bank, 1 for second bank, etc.
2244 *
2245 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2246 * bank N is 4096 * N + flash_reg_addr.
2247 **/
2248static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2249{
2250 struct e1000_nvm_info *nvm = &hw->nvm;
2251 union ich8_hws_flash_status hsfsts;
2252 union ich8_hws_flash_ctrl hsflctl;
2253 u32 flash_linear_addr;
2254 /* bank size is in 16bit words - adjust to bytes */
2255 u32 flash_bank_size = nvm->flash_bank_size * 2;
2256 s32 ret_val;
2257 s32 count = 0;
a708dd88 2258 s32 j, iteration, sector_size;
bc7f75fa
AK		 2259
2260 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2261
ad68076e
BA		 2262 /*
2263 * Determine HW Sector size: Read BERASE bits of hw flash status
2264 * register
2265 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 2266 * consecutive sectors. The start index for the nth Hw sector
2267 * can be calculated as = bank * 4096 + n * 256
2268 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2269 * The start index for the nth Hw sector can be calculated
2270 * as = bank * 4096
2271 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2272 * (ich9 only, otherwise error condition)
2273 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2274 */
2275 switch (hsfsts.hsf_status.berasesz) {
2276 case 0:
2277 /* Hw sector size 256 */
2278 sector_size = ICH_FLASH_SEG_SIZE_256;
2279 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2280 break;
2281 case 1:
2282 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 2283 iteration = 1;
bc7f75fa
AK		 2284 break;
2285 case 2:
148675a7
BA		 2286 sector_size = ICH_FLASH_SEG_SIZE_8K;
2287 iteration = 1;
bc7f75fa
AK		 2288 break;
2289 case 3:
2290 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 2291 iteration = 1;
bc7f75fa
AK		 2292 break;
2293 default:
2294 return -E1000_ERR_NVM;
2295 }
2296
2297 /* Start with the base address, then add the sector offset. */
2298 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 2299 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa
AK		 2300
2301 for (j = 0; j < iteration ; j++) {
2302 do {
2303 /* Steps */
2304 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2305 if (ret_val)
2306 return ret_val;
2307
ad68076e
BA		 2308 /*
2309 * Write a value 11 (block Erase) in Flash
2310 * Cycle field in hw flash control
2311 */
bc7f75fa
AK		 2312 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2313 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2314 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2315
ad68076e
BA		 2316 /*
2317 * Write the last 24 bits of an index within the
bc7f75fa
AK		 2318 * block into Flash Linear address field in Flash
2319 * Address.
2320 */
2321 flash_linear_addr += (j * sector_size);
2322 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2323
2324 ret_val = e1000_flash_cycle_ich8lan(hw,
2325 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2326 if (ret_val == 0)
2327 break;
2328
ad68076e
BA		 2329 /*
2330 * Check if FCERR is set to 1. If 1,
bc7f75fa 2331 * clear it and try the whole sequence
ad68076e
BA		 2332 * a few more times else Done
2333 */
bc7f75fa
AK		 2334 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2335 if (hsfsts.hsf_status.flcerr == 1)
ad68076e 2336 /* repeat for some time before giving up */
bc7f75fa
AK		 2337 continue;
2338 else if (hsfsts.hsf_status.flcdone == 0)
2339 return ret_val;
2340 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2341 }
2342
2343 return 0;
2344}
2345
2346/**
2347 * e1000_valid_led_default_ich8lan - Set the default LED settings
2348 * @hw: pointer to the HW structure
2349 * @data: Pointer to the LED settings
2350 *
2351 * Reads the LED default settings from the NVM to data. If the NVM LED
2352 * settings is all 0's or F's, set the LED default to a valid LED default
2353 * setting.
2354 **/
2355static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2356{
2357 s32 ret_val;
2358
2359 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2360 if (ret_val) {
3bb99fe2 2361 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 2362 return ret_val;
2363 }
2364
2365 if (*data == ID_LED_RESERVED_0000 ||
2366 *data == ID_LED_RESERVED_FFFF)
2367 *data = ID_LED_DEFAULT_ICH8LAN;
2368
2369 return 0;
2370}
2371
a4f58f54
BA		 2372/**
2373 * e1000_id_led_init_pchlan - store LED configurations
2374 * @hw: pointer to the HW structure
2375 *
2376 * PCH does not control LEDs via the LEDCTL register, rather it uses
2377 * the PHY LED configuration register.
2378 *
2379 * PCH also does not have an "always on" or "always off" mode which
2380 * complicates the ID feature. Instead of using the "on" mode to indicate
2381 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2382 * use "link_up" mode. The LEDs will still ID on request if there is no
2383 * link based on logic in e1000_led_[on|off]_pchlan().
2384 **/
2385static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2386{
2387 struct e1000_mac_info *mac = &hw->mac;
2388 s32 ret_val;
2389 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2390 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2391 u16 data, i, temp, shift;
2392
2393 /* Get default ID LED modes */
2394 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2395 if (ret_val)
2396 goto out;
2397
2398 mac->ledctl_default = er32(LEDCTL);
2399 mac->ledctl_mode1 = mac->ledctl_default;
2400 mac->ledctl_mode2 = mac->ledctl_default;
2401
2402 for (i = 0; i < 4; i++) {
2403 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2404 shift = (i * 5);
2405 switch (temp) {
2406 case ID_LED_ON1_DEF2:
2407 case ID_LED_ON1_ON2:
2408 case ID_LED_ON1_OFF2:
2409 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2410 mac->ledctl_mode1 |= (ledctl_on << shift);
2411 break;
2412 case ID_LED_OFF1_DEF2:
2413 case ID_LED_OFF1_ON2:
2414 case ID_LED_OFF1_OFF2:
2415 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2416 mac->ledctl_mode1 |= (ledctl_off << shift);
2417 break;
2418 default:
2419 /* Do nothing */
2420 break;
2421 }
2422 switch (temp) {
2423 case ID_LED_DEF1_ON2:
2424 case ID_LED_ON1_ON2:
2425 case ID_LED_OFF1_ON2:
2426 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2427 mac->ledctl_mode2 |= (ledctl_on << shift);
2428 break;
2429 case ID_LED_DEF1_OFF2:
2430 case ID_LED_ON1_OFF2:
2431 case ID_LED_OFF1_OFF2:
2432 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2433 mac->ledctl_mode2 |= (ledctl_off << shift);
2434 break;
2435 default:
2436 /* Do nothing */
2437 break;
2438 }
2439 }
2440
2441out:
2442 return ret_val;
2443}
2444
bc7f75fa
AK		 2445/**
2446 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2447 * @hw: pointer to the HW structure
2448 *
2449 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2450 * register, so the the bus width is hard coded.
2451 **/
2452static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2453{
2454 struct e1000_bus_info *bus = &hw->bus;
2455 s32 ret_val;
2456
2457 ret_val = e1000e_get_bus_info_pcie(hw);
2458
ad68076e
BA		 2459 /*
2460 * ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 2461 * a configuration space, but do not contain
2462 * PCI Express Capability registers, so bus width
2463 * must be hardcoded.
2464 */
2465 if (bus->width == e1000_bus_width_unknown)
2466 bus->width = e1000_bus_width_pcie_x1;
2467
2468 return ret_val;
2469}
2470
2471/**
2472 * e1000_reset_hw_ich8lan - Reset the hardware
2473 * @hw: pointer to the HW structure
2474 *
2475 * Does a full reset of the hardware which includes a reset of the PHY and
2476 * MAC.
2477 **/
2478static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2479{
1d5846b9 2480 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
db2932ec 2481 u16 reg;
bc7f75fa
AK		 2482 u32 ctrl, icr, kab;
2483 s32 ret_val;
2484
ad68076e
BA		 2485 /*
2486 * Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 2487 * on the last TLP read/write transaction when MAC is reset.
2488 */
2489 ret_val = e1000e_disable_pcie_master(hw);
2490 if (ret_val) {
3bb99fe2 2491 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa
AK		 2492 }
2493
3bb99fe2 2494 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 2495 ew32(IMC, 0xffffffff);
2496
ad68076e
BA		 2497 /*
2498 * Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 2499 * any pending transactions to complete before we hit the MAC
2500 * with the global reset.
2501 */
2502 ew32(RCTL, 0);
2503 ew32(TCTL, E1000_TCTL_PSP);
2504 e1e_flush();
2505
2506 msleep(10);
2507
2508 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2509 if (hw->mac.type == e1000_ich8lan) {
2510 /* Set Tx and Rx buffer allocation to 8k apiece. */
2511 ew32(PBA, E1000_PBA_8K);
2512 /* Set Packet Buffer Size to 16k. */
2513 ew32(PBS, E1000_PBS_16K);
2514 }
2515
1d5846b9
BA		 2516 if (hw->mac.type == e1000_pchlan) {
2517 /* Save the NVM K1 bit setting*/
2518 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2519 if (ret_val)
2520 return ret_val;
2521
2522 if (reg & E1000_NVM_K1_ENABLE)
2523 dev_spec->nvm_k1_enabled = true;
2524 else
2525 dev_spec->nvm_k1_enabled = false;
2526 }
2527
bc7f75fa
AK		 2528 ctrl = er32(CTRL);
2529
2530 if (!e1000_check_reset_block(hw)) {
fc0c7760
BA		 2531 /* Clear PHY Reset Asserted bit */
2532 if (hw->mac.type >= e1000_pchlan) {
2533 u32 status = er32(STATUS);
2534 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2535 }
2536
ad68076e
BA		 2537 /*
2538 * PHY HW reset requires MAC CORE reset at the same
bc7f75fa
AK		 2539 * time to make sure the interface between MAC and the
2540 * external PHY is reset.
2541 */
2542 ctrl |= E1000_CTRL_PHY_RST;
2543 }
2544 ret_val = e1000_acquire_swflag_ich8lan(hw);
3bb99fe2 2545 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa
AK		 2546 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2547 msleep(20);
2548
fc0c7760 2549 if (!ret_val)
30bb0e0d 2550 e1000_release_swflag_ich8lan(hw);
37f40239 2551
fddaa1af
BA		 2552 /* Perform any necessary post-reset workarounds */
2553 if (hw->mac.type == e1000_pchlan)
2554 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2555
fc0c7760
BA		 2556 if (ctrl & E1000_CTRL_PHY_RST)
2557 ret_val = hw->phy.ops.get_cfg_done(hw);
2558
2559 if (hw->mac.type >= e1000_ich10lan) {
2560 e1000_lan_init_done_ich8lan(hw);
2561 } else {
2562 ret_val = e1000e_get_auto_rd_done(hw);
2563 if (ret_val) {
2564 /*
2565 * When auto config read does not complete, do not
2566 * return with an error. This can happen in situations
2567 * where there is no eeprom and prevents getting link.
2568 */
3bb99fe2 2569 e_dbg("Auto Read Done did not complete\n");
fc0c7760 2570 }
bc7f75fa 2571 }
db2932ec
BA		 2572 /* Dummy read to clear the phy wakeup bit after lcd reset */
2573 if (hw->mac.type == e1000_pchlan)
2574 e1e_rphy(hw, BM_WUC, &reg);
bc7f75fa 2575
f523d211
BA		 2576 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2577 if (ret_val)
2578 goto out;
2579
2580 if (hw->mac.type == e1000_pchlan) {
2581 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2582 if (ret_val)
2583 goto out;
2584 }
7d3cabbc
BA		 2585 /*
2586 * For PCH, this write will make sure that any noise
2587 * will be detected as a CRC error and be dropped rather than show up
2588 * as a bad packet to the DMA engine.
2589 */
2590 if (hw->mac.type == e1000_pchlan)
2591 ew32(CRC_OFFSET, 0x65656565);
2592
bc7f75fa
AK		 2593 ew32(IMC, 0xffffffff);
2594 icr = er32(ICR);
2595
2596 kab = er32(KABGTXD);
2597 kab |= E1000_KABGTXD_BGSQLBIAS;
2598 ew32(KABGTXD, kab);
2599
f523d211 2600out:
bc7f75fa
AK		 2601 return ret_val;
2602}
2603
2604/**
2605 * e1000_init_hw_ich8lan - Initialize the hardware
2606 * @hw: pointer to the HW structure
2607 *
2608 * Prepares the hardware for transmit and receive by doing the following:
2609 * - initialize hardware bits
2610 * - initialize LED identification
2611 * - setup receive address registers
2612 * - setup flow control
489815ce 2613 * - setup transmit descriptors
bc7f75fa
AK		 2614 * - clear statistics
2615 **/
2616static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2617{
2618 struct e1000_mac_info *mac = &hw->mac;
2619 u32 ctrl_ext, txdctl, snoop;
2620 s32 ret_val;
2621 u16 i;
2622
2623 e1000_initialize_hw_bits_ich8lan(hw);
2624
2625 /* Initialize identification LED */
a4f58f54 2626 ret_val = mac->ops.id_led_init(hw);
de39b752 2627 if (ret_val)
3bb99fe2 2628 e_dbg("Error initializing identification LED\n");
de39b752 2629 /* This is not fatal and we should not stop init due to this */
bc7f75fa
AK		 2630
2631 /* Setup the receive address. */
2632 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2633
2634 /* Zero out the Multicast HASH table */
3bb99fe2 2635 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 2636 for (i = 0; i < mac->mta_reg_count; i++)
2637 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2638
fc0c7760
BA		 2639 /*
2640 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2641 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2642 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2643 */
2644 if (hw->phy.type == e1000_phy_82578) {
94d8186a 2645 hw->phy.ops.read_reg(hw, BM_WUC, &i);
fc0c7760
BA		 2646 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2647 if (ret_val)
2648 return ret_val;
2649 }
2650
bc7f75fa
AK		 2651 /* Setup link and flow control */
2652 ret_val = e1000_setup_link_ich8lan(hw);
2653
2654 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 2655 txdctl = er32(TXDCTL(0));
bc7f75fa
AK		 2656 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2657 E1000_TXDCTL_FULL_TX_DESC_WB;
2658 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2659 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f
JK		 2660 ew32(TXDCTL(0), txdctl);
2661 txdctl = er32(TXDCTL(1));
bc7f75fa
AK		 2662 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2663 E1000_TXDCTL_FULL_TX_DESC_WB;
2664 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2665 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f 2666 ew32(TXDCTL(1), txdctl);
bc7f75fa 2667
ad68076e
BA		 2668 /*
2669 * ICH8 has opposite polarity of no_snoop bits.
2670 * By default, we should use snoop behavior.
2671 */
bc7f75fa
AK		 2672 if (mac->type == e1000_ich8lan)
2673 snoop = PCIE_ICH8_SNOOP_ALL;
2674 else
2675 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2676 e1000e_set_pcie_no_snoop(hw, snoop);
2677
2678 ctrl_ext = er32(CTRL_EXT);
2679 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2680 ew32(CTRL_EXT, ctrl_ext);
2681
ad68076e
BA		 2682 /*
2683 * Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 2684 * important that we do this after we have tried to establish link
2685 * because the symbol error count will increment wildly if there
2686 * is no link.
2687 */
2688 e1000_clear_hw_cntrs_ich8lan(hw);
2689
2690 return 0;
2691}
2692/**
2693 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2694 * @hw: pointer to the HW structure
2695 *
2696 * Sets/Clears required hardware bits necessary for correctly setting up the
2697 * hardware for transmit and receive.
2698 **/
2699static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2700{
2701 u32 reg;
2702
2703 /* Extended Device Control */
2704 reg = er32(CTRL_EXT);
2705 reg |= (1 << 22);
a4f58f54
BA		 2706 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2707 if (hw->mac.type >= e1000_pchlan)
2708 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 2709 ew32(CTRL_EXT, reg);
2710
2711 /* Transmit Descriptor Control 0 */
e9ec2c0f 2712 reg = er32(TXDCTL(0));
bc7f75fa 2713 reg |= (1 << 22);
e9ec2c0f 2714 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 2715
2716 /* Transmit Descriptor Control 1 */
e9ec2c0f 2717 reg = er32(TXDCTL(1));
bc7f75fa 2718 reg |= (1 << 22);
e9ec2c0f 2719 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 2720
2721 /* Transmit Arbitration Control 0 */
e9ec2c0f 2722 reg = er32(TARC(0));
bc7f75fa
AK		 2723 if (hw->mac.type == e1000_ich8lan)
2724 reg |= (1 << 28) | (1 << 29);
2725 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
e9ec2c0f 2726 ew32(TARC(0), reg);
bc7f75fa
AK		 2727
2728 /* Transmit Arbitration Control 1 */
e9ec2c0f 2729 reg = er32(TARC(1));
bc7f75fa
AK		 2730 if (er32(TCTL) & E1000_TCTL_MULR)
2731 reg &= ~(1 << 28);
2732 else
2733 reg |= (1 << 28);
2734 reg |= (1 << 24) | (1 << 26) | (1 << 30);
e9ec2c0f 2735 ew32(TARC(1), reg);
bc7f75fa
AK		 2736
2737 /* Device Status */
2738 if (hw->mac.type == e1000_ich8lan) {
2739 reg = er32(STATUS);
2740 reg &= ~(1 << 31);
2741 ew32(STATUS, reg);
2742 }
a80483d3
JB		 2743
2744 /*
2745 * work-around descriptor data corruption issue during nfs v2 udp
2746 * traffic, just disable the nfs filtering capability
2747 */
2748 reg = er32(RFCTL);
2749 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
2750 ew32(RFCTL, reg);
2751
2752 return;
bc7f75fa
AK		 2753}
2754
2755/**
2756 * e1000_setup_link_ich8lan - Setup flow control and link settings
2757 * @hw: pointer to the HW structure
2758 *
2759 * Determines which flow control settings to use, then configures flow
2760 * control. Calls the appropriate media-specific link configuration
2761 * function. Assuming the adapter has a valid link partner, a valid link
2762 * should be established. Assumes the hardware has previously been reset
2763 * and the transmitter and receiver are not enabled.
2764 **/
2765static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2766{
bc7f75fa
AK		 2767 s32 ret_val;
2768
2769 if (e1000_check_reset_block(hw))
2770 return 0;
2771
ad68076e
BA		 2772 /*
2773 * ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 2774 * the default flow control setting, so we explicitly
2775 * set it to full.
2776 */
37289d9c
BA		 2777 if (hw->fc.requested_mode == e1000_fc_default) {
2778 /* Workaround h/w hang when Tx flow control enabled */
2779 if (hw->mac.type == e1000_pchlan)
2780 hw->fc.requested_mode = e1000_fc_rx_pause;
2781 else
2782 hw->fc.requested_mode = e1000_fc_full;
2783 }
bc7f75fa 2784
5c48ef3e
BA		 2785 /*
2786 * Save off the requested flow control mode for use later. Depending
2787 * on the link partner's capabilities, we may or may not use this mode.
2788 */
2789 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 2790
3bb99fe2 2791 e_dbg("After fix-ups FlowControl is now = %x\n",
5c48ef3e 2792 hw->fc.current_mode);
bc7f75fa
AK		 2793
2794 /* Continue to configure the copper link. */
2795 ret_val = e1000_setup_copper_link_ich8lan(hw);
2796 if (ret_val)
2797 return ret_val;
2798
318a94d6 2799 ew32(FCTTV, hw->fc.pause_time);
a4f58f54
BA		 2800 if ((hw->phy.type == e1000_phy_82578) ||
2801 (hw->phy.type == e1000_phy_82577)) {
94d8186a 2802 ret_val = hw->phy.ops.write_reg(hw,
a4f58f54
BA		 2803 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2804 hw->fc.pause_time);
2805 if (ret_val)
2806 return ret_val;
2807 }
bc7f75fa
AK		 2808
2809 return e1000e_set_fc_watermarks(hw);
2810}
2811
2812/**
2813 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2814 * @hw: pointer to the HW structure
2815 *
2816 * Configures the kumeran interface to the PHY to wait the appropriate time
2817 * when polling the PHY, then call the generic setup_copper_link to finish
2818 * configuring the copper link.
2819 **/
2820static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2821{
2822 u32 ctrl;
2823 s32 ret_val;
2824 u16 reg_data;
2825
2826 ctrl = er32(CTRL);
2827 ctrl |= E1000_CTRL_SLU;
2828 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2829 ew32(CTRL, ctrl);
2830
ad68076e
BA		 2831 /*
2832 * Set the mac to wait the maximum time between each iteration
bc7f75fa 2833 * and increase the max iterations when polling the phy;
ad68076e
BA		 2834 * this fixes erroneous timeouts at 10Mbps.
2835 */
07818950 2836 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
bc7f75fa
AK		 2837 if (ret_val)
2838 return ret_val;
07818950
BA		 2839 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2840 &reg_data);
bc7f75fa
AK		 2841 if (ret_val)
2842 return ret_val;
2843 reg_data |= 0x3F;
07818950
BA		 2844 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2845 reg_data);
bc7f75fa
AK		 2846 if (ret_val)
2847 return ret_val;
2848
a4f58f54
BA		 2849 switch (hw->phy.type) {
2850 case e1000_phy_igp_3:
bc7f75fa
AK		 2851 ret_val = e1000e_copper_link_setup_igp(hw);
2852 if (ret_val)
2853 return ret_val;
a4f58f54
BA		 2854 break;
2855 case e1000_phy_bm:
2856 case e1000_phy_82578:
97ac8cae
BA		 2857 ret_val = e1000e_copper_link_setup_m88(hw);
2858 if (ret_val)
2859 return ret_val;
a4f58f54
BA		 2860 break;
2861 case e1000_phy_82577:
2862 ret_val = e1000_copper_link_setup_82577(hw);
2863 if (ret_val)
2864 return ret_val;
2865 break;
2866 case e1000_phy_ife:
94d8186a 2867 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 2868 &reg_data);
97ac8cae
BA		 2869 if (ret_val)
2870 return ret_val;
2871
2872 reg_data &= ~IFE_PMC_AUTO_MDIX;
2873
2874 switch (hw->phy.mdix) {
2875 case 1:
2876 reg_data &= ~IFE_PMC_FORCE_MDIX;
2877 break;
2878 case 2:
2879 reg_data |= IFE_PMC_FORCE_MDIX;
2880 break;
2881 case 0:
2882 default:
2883 reg_data |= IFE_PMC_AUTO_MDIX;
2884 break;
2885 }
94d8186a 2886 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 2887 reg_data);
97ac8cae
BA		 2888 if (ret_val)
2889 return ret_val;
a4f58f54
BA		 2890 break;
2891 default:
2892 break;
97ac8cae 2893 }
bc7f75fa
AK		 2894 return e1000e_setup_copper_link(hw);
2895}
2896
2897/**
2898 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2899 * @hw: pointer to the HW structure
2900 * @speed: pointer to store current link speed
2901 * @duplex: pointer to store the current link duplex
2902 *
ad68076e 2903 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 2904 * information and then calls the Kumeran lock loss workaround for links at
2905 * gigabit speeds.
2906 **/
2907static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2908 u16 *duplex)
2909{
2910 s32 ret_val;
2911
2912 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2913 if (ret_val)
2914 return ret_val;
2915
2916 if ((hw->mac.type == e1000_ich8lan) &&
2917 (hw->phy.type == e1000_phy_igp_3) &&
2918 (*speed == SPEED_1000)) {
2919 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2920 }
2921
2922 return ret_val;
2923}
2924
2925/**
2926 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2927 * @hw: pointer to the HW structure
2928 *
2929 * Work-around for 82566 Kumeran PCS lock loss:
2930 * On link status change (i.e. PCI reset, speed change) and link is up and
2931 * speed is gigabit-
2932 * 0) if workaround is optionally disabled do nothing
2933 * 1) wait 1ms for Kumeran link to come up
2934 * 2) check Kumeran Diagnostic register PCS lock loss bit
2935 * 3) if not set the link is locked (all is good), otherwise...
2936 * 4) reset the PHY
2937 * 5) repeat up to 10 times
2938 * Note: this is only called for IGP3 copper when speed is 1gb.
2939 **/
2940static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2941{
2942 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2943 u32 phy_ctrl;
2944 s32 ret_val;
2945 u16 i, data;
2946 bool link;
2947
2948 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2949 return 0;
2950
ad68076e
BA		 2951 /*
2952 * Make sure link is up before proceeding. If not just return.
bc7f75fa 2953 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 2954 * stability
2955 */
bc7f75fa
AK		 2956 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2957 if (!link)
2958 return 0;
2959
2960 for (i = 0; i < 10; i++) {
2961 /* read once to clear */
2962 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2963 if (ret_val)
2964 return ret_val;
2965 /* and again to get new status */
2966 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2967 if (ret_val)
2968 return ret_val;
2969
2970 /* check for PCS lock */
2971 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2972 return 0;
2973
2974 /* Issue PHY reset */
2975 e1000_phy_hw_reset(hw);
2976 mdelay(5);
2977 }
2978 /* Disable GigE link negotiation */
2979 phy_ctrl = er32(PHY_CTRL);
2980 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2981 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2982 ew32(PHY_CTRL, phy_ctrl);
2983
ad68076e
BA		 2984 /*
2985 * Call gig speed drop workaround on Gig disable before accessing
2986 * any PHY registers
2987 */
bc7f75fa
AK		 2988 e1000e_gig_downshift_workaround_ich8lan(hw);
2989
2990 /* unable to acquire PCS lock */
2991 return -E1000_ERR_PHY;
2992}
2993
2994/**
ad68076e 2995 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 2996 * @hw: pointer to the HW structure
489815ce 2997 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 2998 *
564ea9bb
BA		 2999 * If ICH8, set the current Kumeran workaround state (enabled - true
3000 * /disabled - false).
bc7f75fa
AK		 3001 **/
3002void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3003 bool state)
3004{
3005 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3006
3007 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 3008 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 3009 return;
3010 }
3011
3012 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3013}
3014
3015/**
3016 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3017 * @hw: pointer to the HW structure
3018 *
3019 * Workaround for 82566 power-down on D3 entry:
3020 * 1) disable gigabit link
3021 * 2) write VR power-down enable
3022 * 3) read it back
3023 * Continue if successful, else issue LCD reset and repeat
3024 **/
3025void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3026{
3027 u32 reg;
3028 u16 data;
3029 u8 retry = 0;
3030
3031 if (hw->phy.type != e1000_phy_igp_3)
3032 return;
3033
3034 /* Try the workaround twice (if needed) */
3035 do {
3036 /* Disable link */
3037 reg = er32(PHY_CTRL);
3038 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3039 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3040 ew32(PHY_CTRL, reg);
3041
ad68076e
BA		 3042 /*
3043 * Call gig speed drop workaround on Gig disable before
3044 * accessing any PHY registers
3045 */
bc7f75fa
AK		 3046 if (hw->mac.type == e1000_ich8lan)
3047 e1000e_gig_downshift_workaround_ich8lan(hw);
3048
3049 /* Write VR power-down enable */
3050 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3051 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3052 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3053
3054 /* Read it back and test */
3055 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3056 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3057 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3058 break;
3059
3060 /* Issue PHY reset and repeat at most one more time */
3061 reg = er32(CTRL);
3062 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3063 retry++;
3064 } while (retry);
3065}
3066
3067/**
3068 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3069 * @hw: pointer to the HW structure
3070 *
3071 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 3072 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 3073 * 1) Set Kumeran Near-end loopback
3074 * 2) Clear Kumeran Near-end loopback
3075 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3076 **/
3077void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3078{
3079 s32 ret_val;
3080 u16 reg_data;
3081
3082 if ((hw->mac.type != e1000_ich8lan) ||
3083 (hw->phy.type != e1000_phy_igp_3))
3084 return;
3085
3086 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3087 &reg_data);
3088 if (ret_val)
3089 return;
3090 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3091 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3092 reg_data);
3093 if (ret_val)
3094 return;
3095 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3096 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3097 reg_data);
3098}
3099
97ac8cae
BA		 3100/**
3101 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3102 * @hw: pointer to the HW structure
3103 *
3104 * During S0 to Sx transition, it is possible the link remains at gig
3105 * instead of negotiating to a lower speed. Before going to Sx, set
3106 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3107 * to a lower speed.
3108 *
a4f58f54 3109 * Should only be called for applicable parts.
97ac8cae
BA		 3110 **/
3111void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3112{
3113 u32 phy_ctrl;
3114
a4f58f54 3115 switch (hw->mac.type) {
9e135a2e 3116 case e1000_ich8lan:
a4f58f54
BA		 3117 case e1000_ich9lan:
3118 case e1000_ich10lan:
3119 case e1000_pchlan:
97ac8cae
BA		 3120 phy_ctrl = er32(PHY_CTRL);
3121 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3122 E1000_PHY_CTRL_GBE_DISABLE;
3123 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 3124
a4f58f54 3125 if (hw->mac.type == e1000_pchlan)
74eee2e8 3126 e1000_phy_hw_reset_ich8lan(hw);
a4f58f54
BA		 3127 default:
3128 break;
97ac8cae
BA		 3129 }
3130
3131 return;
3132}
3133
bc7f75fa
AK		 3134/**
3135 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3136 * @hw: pointer to the HW structure
3137 *
3138 * Return the LED back to the default configuration.
3139 **/
3140static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3141{
3142 if (hw->phy.type == e1000_phy_ife)
3143 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3144
3145 ew32(LEDCTL, hw->mac.ledctl_default);
3146 return 0;
3147}
3148
3149/**
489815ce 3150 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 3151 * @hw: pointer to the HW structure
3152 *
489815ce 3153 * Turn on the LEDs.
bc7f75fa
AK		 3154 **/
3155static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3156{
3157 if (hw->phy.type == e1000_phy_ife)
3158 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3159 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3160
3161 ew32(LEDCTL, hw->mac.ledctl_mode2);
3162 return 0;
3163}
3164
3165/**
489815ce 3166 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 3167 * @hw: pointer to the HW structure
3168 *
489815ce 3169 * Turn off the LEDs.
bc7f75fa
AK		 3170 **/
3171static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3172{
3173 if (hw->phy.type == e1000_phy_ife)
3174 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3175 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3176
3177 ew32(LEDCTL, hw->mac.ledctl_mode1);
3178 return 0;
3179}
3180
a4f58f54
BA		 3181/**
3182 * e1000_setup_led_pchlan - Configures SW controllable LED
3183 * @hw: pointer to the HW structure
3184 *
3185 * This prepares the SW controllable LED for use.
3186 **/
3187static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3188{
94d8186a 3189 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3190 (u16)hw->mac.ledctl_mode1);
3191}
3192
3193/**
3194 * e1000_cleanup_led_pchlan - Restore the default LED operation
3195 * @hw: pointer to the HW structure
3196 *
3197 * Return the LED back to the default configuration.
3198 **/
3199static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3200{
94d8186a 3201 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3202 (u16)hw->mac.ledctl_default);
3203}
3204
3205/**
3206 * e1000_led_on_pchlan - Turn LEDs on
3207 * @hw: pointer to the HW structure
3208 *
3209 * Turn on the LEDs.
3210 **/
3211static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3212{
3213 u16 data = (u16)hw->mac.ledctl_mode2;
3214 u32 i, led;
3215
3216 /*
3217 * If no link, then turn LED on by setting the invert bit
3218 * for each LED that's mode is "link_up" in ledctl_mode2.
3219 */
3220 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3221 for (i = 0; i < 3; i++) {
3222 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3223 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3224 E1000_LEDCTL_MODE_LINK_UP)
3225 continue;
3226 if (led & E1000_PHY_LED0_IVRT)
3227 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3228 else
3229 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3230 }
3231 }
3232
94d8186a 3233 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3234}
3235
3236/**
3237 * e1000_led_off_pchlan - Turn LEDs off
3238 * @hw: pointer to the HW structure
3239 *
3240 * Turn off the LEDs.
3241 **/
3242static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3243{
3244 u16 data = (u16)hw->mac.ledctl_mode1;
3245 u32 i, led;
3246
3247 /*
3248 * If no link, then turn LED off by clearing the invert bit
3249 * for each LED that's mode is "link_up" in ledctl_mode1.
3250 */
3251 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3252 for (i = 0; i < 3; i++) {
3253 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3254 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3255 E1000_LEDCTL_MODE_LINK_UP)
3256 continue;
3257 if (led & E1000_PHY_LED0_IVRT)
3258 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3259 else
3260 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3261 }
3262 }
3263
94d8186a 3264 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3265}
3266
f4187b56
BA		 3267/**
3268 * e1000_get_cfg_done_ich8lan - Read config done bit
3269 * @hw: pointer to the HW structure
3270 *
3271 * Read the management control register for the config done bit for
3272 * completion status. NOTE: silicon which is EEPROM-less will fail trying
3273 * to read the config done bit, so an error is *ONLY* logged and returns
a4f58f54 3274 * 0. If we were to return with error, EEPROM-less silicon
f4187b56
BA		 3275 * would not be able to be reset or change link.
3276 **/
3277static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3278{
3279 u32 bank = 0;
3280
fc0c7760
BA		 3281 if (hw->mac.type >= e1000_pchlan) {
3282 u32 status = er32(STATUS);
3283
3284 if (status & E1000_STATUS_PHYRA)
3285 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3286 else
3bb99fe2 3287 e_dbg("PHY Reset Asserted not set - needs delay\n");
fc0c7760
BA		 3288 }
3289
f4187b56
BA		 3290 e1000e_get_cfg_done(hw);
3291
3292 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
a4f58f54
BA		 3293 if ((hw->mac.type != e1000_ich10lan) &&
3294 (hw->mac.type != e1000_pchlan)) {
f4187b56
BA		 3295 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3296 (hw->phy.type == e1000_phy_igp_3)) {
3297 e1000e_phy_init_script_igp3(hw);
3298 }
3299 } else {
3300 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3301 /* Maybe we should do a basic PHY config */
3bb99fe2 3302 e_dbg("EEPROM not present\n");
f4187b56
BA		 3303 return -E1000_ERR_CONFIG;
3304 }
3305 }
3306
3307 return 0;
3308}
3309
17f208de
BA		 3310/**
3311 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3312 * @hw: pointer to the HW structure
3313 *
3314 * In the case of a PHY power down to save power, or to turn off link during a
3315 * driver unload, or wake on lan is not enabled, remove the link.
3316 **/
3317static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3318{
3319 /* If the management interface is not enabled, then power down */
3320 if (!(hw->mac.ops.check_mng_mode(hw) ||
3321 hw->phy.ops.check_reset_block(hw)))
3322 e1000_power_down_phy_copper(hw);
3323
3324 return;
3325}
3326
bc7f75fa
AK		 3327/**
3328 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3329 * @hw: pointer to the HW structure
3330 *
3331 * Clears hardware counters specific to the silicon family and calls
3332 * clear_hw_cntrs_generic to clear all general purpose counters.
3333 **/
3334static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3335{
a4f58f54 3336 u16 phy_data;
bc7f75fa
AK		 3337
3338 e1000e_clear_hw_cntrs_base(hw);
3339
99673d9b
BA		 3340 er32(ALGNERRC);
3341 er32(RXERRC);
3342 er32(TNCRS);
3343 er32(CEXTERR);
3344 er32(TSCTC);
3345 er32(TSCTFC);
bc7f75fa 3346
99673d9b
BA		 3347 er32(MGTPRC);
3348 er32(MGTPDC);
3349 er32(MGTPTC);
bc7f75fa 3350
99673d9b
BA		 3351 er32(IAC);
3352 er32(ICRXOC);
bc7f75fa 3353
a4f58f54
BA		 3354 /* Clear PHY statistics registers */
3355 if ((hw->phy.type == e1000_phy_82578) ||
3356 (hw->phy.type == e1000_phy_82577)) {
94d8186a
BA		 3357 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3358 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3359 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3360 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3361 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3362 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3363 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3364 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3365 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3366 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3367 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3368 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3369 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3370 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
a4f58f54 3371 }
bc7f75fa
AK		 3372}
3373
3374static struct e1000_mac_operations ich8_mac_ops = {
a4f58f54 3375 .id_led_init = e1000e_id_led_init,
4662e82b 3376 .check_mng_mode = e1000_check_mng_mode_ich8lan,
7d3cabbc 3377 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 3378 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 3379 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3380 .get_bus_info = e1000_get_bus_info_ich8lan,
f4d2dd4c 3381 .set_lan_id = e1000_set_lan_id_single_port,
bc7f75fa 3382 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 3383 /* led_on dependent on mac type */
3384 /* led_off dependent on mac type */
e2de3eb6 3385 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 3386 .reset_hw = e1000_reset_hw_ich8lan,
3387 .init_hw = e1000_init_hw_ich8lan,
3388 .setup_link = e1000_setup_link_ich8lan,
3389 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
a4f58f54 3390 /* id_led_init dependent on mac type */
bc7f75fa
AK		 3391};
3392
3393static struct e1000_phy_operations ich8_phy_ops = {
94d8186a 3394 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 3395 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 3396 .commit = NULL,
f4187b56 3397 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 3398 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 3399 .read_reg = e1000e_read_phy_reg_igp,
3400 .release = e1000_release_swflag_ich8lan,
3401 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 3402 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3403 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 3404 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 3405};
3406
3407static struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a
BA		 3408 .acquire = e1000_acquire_nvm_ich8lan,
3409 .read = e1000_read_nvm_ich8lan,
3410 .release = e1000_release_nvm_ich8lan,
3411 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 3412 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 3413 .validate = e1000_validate_nvm_checksum_ich8lan,
3414 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 3415};
3416
3417struct e1000_info e1000_ich8_info = {
3418 .mac = e1000_ich8lan,
3419 .flags = FLAG_HAS_WOL
97ac8cae 3420 | FLAG_IS_ICH
bc7f75fa
AK		 3421 | FLAG_RX_CSUM_ENABLED
3422 | FLAG_HAS_CTRLEXT_ON_LOAD
3423 | FLAG_HAS_AMT
3424 | FLAG_HAS_FLASH
3425 | FLAG_APME_IN_WUC,
3426 .pba = 8,
2adc55c9 3427 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 3428 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3429 .mac_ops = &ich8_mac_ops,
3430 .phy_ops = &ich8_phy_ops,
3431 .nvm_ops = &ich8_nvm_ops,
3432};
3433
3434struct e1000_info e1000_ich9_info = {
3435 .mac = e1000_ich9lan,
3436 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 3437 | FLAG_IS_ICH
bc7f75fa
AK		 3438 | FLAG_HAS_WOL
3439 | FLAG_RX_CSUM_ENABLED
3440 | FLAG_HAS_CTRLEXT_ON_LOAD
3441 | FLAG_HAS_AMT
3442 | FLAG_HAS_ERT
3443 | FLAG_HAS_FLASH
3444 | FLAG_APME_IN_WUC,
3445 .pba = 10,
2adc55c9 3446 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 3447 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3448 .mac_ops = &ich8_mac_ops,
3449 .phy_ops = &ich8_phy_ops,
3450 .nvm_ops = &ich8_nvm_ops,
3451};
3452
f4187b56
BA		 3453struct e1000_info e1000_ich10_info = {
3454 .mac = e1000_ich10lan,
3455 .flags = FLAG_HAS_JUMBO_FRAMES
3456 | FLAG_IS_ICH
3457 | FLAG_HAS_WOL
3458 | FLAG_RX_CSUM_ENABLED
3459 | FLAG_HAS_CTRLEXT_ON_LOAD
3460 | FLAG_HAS_AMT
3461 | FLAG_HAS_ERT
3462 | FLAG_HAS_FLASH
3463 | FLAG_APME_IN_WUC,
3464 .pba = 10,
2adc55c9 3465 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 3466 .get_variants = e1000_get_variants_ich8lan,
3467 .mac_ops = &ich8_mac_ops,
3468 .phy_ops = &ich8_phy_ops,
3469 .nvm_ops = &ich8_nvm_ops,
3470};
a4f58f54
BA		 3471
3472struct e1000_info e1000_pch_info = {
3473 .mac = e1000_pchlan,
3474 .flags = FLAG_IS_ICH
3475 | FLAG_HAS_WOL
3476 | FLAG_RX_CSUM_ENABLED
3477 | FLAG_HAS_CTRLEXT_ON_LOAD
3478 | FLAG_HAS_AMT
3479 | FLAG_HAS_FLASH
3480 | FLAG_HAS_JUMBO_FRAMES
38eb394e 3481 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
a4f58f54
BA		 3482 | FLAG_APME_IN_WUC,
3483 .pba = 26,
3484 .max_hw_frame_size = 4096,
3485 .get_variants = e1000_get_variants_ich8lan,
3486 .mac_ops = &ich8_mac_ops,
3487 .phy_ops = &ich8_phy_ops,
3488 .nvm_ops = &ich8_nvm_ops,
3489};
Linux 6.x block layer and io_uring tree(s)