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e1000e: move settting of flow control refresh timer to link setup code
[linux-2.6-block.git] / drivers / net / e1000e / hw.h
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
c7e54b1b 4 Copyright(c) 1999 - 2009 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000_HW_H_
30#define _E1000_HW_H_
31
32#include <linux/types.h>
33
34struct e1000_hw;
35struct e1000_adapter;
36
37#include "defines.h"
38
39#define er32(reg) __er32(hw, E1000_##reg)
40#define ew32(reg,val) __ew32(hw, E1000_##reg, (val))
41#define e1e_flush() er32(STATUS)
42
43#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
44 (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
45
46#define E1000_READ_REG_ARRAY(a, reg, offset) \
47 (readl((a)->hw_addr + reg + ((offset) << 2)))
48
49enum e1e_registers {
50 E1000_CTRL = 0x00000, /* Device Control - RW */
51 E1000_STATUS = 0x00008, /* Device Status - RO */
52 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
53 E1000_EERD = 0x00014, /* EEPROM Read - RW */
54 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
55 E1000_FLA = 0x0001C, /* Flash Access - RW */
56 E1000_MDIC = 0x00020, /* MDI Control - RW */
57 E1000_SCTL = 0x00024, /* SerDes Control - RW */
58 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
59 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
60 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
61 E1000_FCT = 0x00030, /* Flow Control Type - RW */
62 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
63 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
64 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
65 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
66 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
67 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
4662e82b 68 E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
bc7f75fa 69 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
4662e82b
BA		 70 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
71 E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
72#define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
ad68076e 73 E1000_RCTL = 0x00100, /* Rx Control - RW */
bc7f75fa 74 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
ad68076e
BA		 75 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
76 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
77 E1000_TCTL = 0x00400, /* Tx Control - RW */
78 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
79 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
80 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
bc7f75fa
AK		 81 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
82 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
83 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
84 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
85 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
86 E1000_PBS = 0x01008, /* Packet Buffer Size */
87 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
88 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
89 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
6ea7ae1d 90 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
bc7f75fa
AK		 91 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
92 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
93 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
94 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
ad68076e
BA		 95 E1000_RDBAL = 0x02800, /* Rx Descriptor Base Address Low - RW */
96 E1000_RDBAH = 0x02804, /* Rx Descriptor Base Address High - RW */
97 E1000_RDLEN = 0x02808, /* Rx Descriptor Length - RW */
98 E1000_RDH = 0x02810, /* Rx Descriptor Head - RW */
99 E1000_RDT = 0x02818, /* Rx Descriptor Tail - RW */
100 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
e9ec2c0f
JK		 101 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
102#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
bc7f75fa
AK		 103 E1000_RADV = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
104
105/* Convenience macros
106 *
107 * Note: "_n" is the queue number of the register to be written to.
108 *
109 * Example usage:
110 * E1000_RDBAL_REG(current_rx_queue)
111 *
112 */
113#define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
114 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
ad68076e
BA		 115 E1000_TDBAL = 0x03800, /* Tx Descriptor Base Address Low - RW */
116 E1000_TDBAH = 0x03804, /* Tx Descriptor Base Address High - RW */
117 E1000_TDLEN = 0x03808, /* Tx Descriptor Length - RW */
118 E1000_TDH = 0x03810, /* Tx Descriptor Head - RW */
119 E1000_TDT = 0x03818, /* Tx Descriptor Tail - RW */
120 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
e9ec2c0f
JK		 121 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
122#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
ad68076e 123 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
e9ec2c0f
JK		 124 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
125#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
bc7f75fa
AK		 126 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
127 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
128 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
129 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
130 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
131 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
132 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
133 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
134 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
135 E1000_COLC = 0x04028, /* Collision Count - R/clr */
136 E1000_DC = 0x04030, /* Defer Count - R/clr */
ad68076e 137 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
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AK		 138 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
139 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
140 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
ad68076e
BA		 141 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
142 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
143 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
144 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
145 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
146 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
147 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
148 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
149 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
150 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
151 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
152 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
153 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
154 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
155 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
156 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
157 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
158 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
159 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
160 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
161 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
162 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
163 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
164 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
165 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
bc7f75fa 166 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
ad68076e
BA		 167 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
168 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
169 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
170 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
171 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
172 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
173 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
174 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
175 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
176 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
177 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
178 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
179 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
180 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
181 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
182 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
183 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
bc7f75fa
AK		 184 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
185 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
186 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
187 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
188 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
189 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
190 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
191 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
192 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
ad68076e 193 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
489815ce 194 E1000_RFCTL = 0x05008, /* Receive Filter Control */
bc7f75fa 195 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
a4f58f54
BA		 196 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
197#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
198#define E1000_RA (E1000_RAL(0))
199 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
200#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
bc7f75fa
AK		 201 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
202 E1000_WUC = 0x05800, /* Wakeup Control - RW */
203 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
204 E1000_WUS = 0x05810, /* Wakeup Status - RO */
205 E1000_MANC = 0x05820, /* Management Control - RW */
206 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
207 E1000_HOST_IF = 0x08800, /* Host Interface */
208
209 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
210 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
cd791618
BA		 211 E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
212#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
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AK		 213 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
214 E1000_GCR = 0x05B00, /* PCI-Ex Control */
78272bba 215 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
bc7f75fa
AK		 216 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
217 E1000_SWSM = 0x05B50, /* SW Semaphore */
218 E1000_FWSM = 0x05B54, /* FW Semaphore */
23a2d1b2 219 E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
7d3cabbc 220 E1000_CRC_OFFSET = 0x05F50, /* CRC Offset register */
489815ce 221 E1000_HICR = 0x08F00, /* Host Interface Control */
bc7f75fa
AK		 222};
223
5eb6f3c7 224#define E1000_MAX_PHY_ADDR 4
bc7f75fa
AK		 225
226/* IGP01E1000 Specific Registers */
227#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
228#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
229#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
230#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
231#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
232#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
97ac8cae
BA		 233#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
234#define IGP_PAGE_SHIFT 5
235#define PHY_REG_MASK 0x1F
236
237#define BM_WUC_PAGE 800
238#define BM_WUC_ADDRESS_OPCODE 0x11
239#define BM_WUC_DATA_OPCODE 0x12
240#define BM_WUC_ENABLE_PAGE 769
241#define BM_WUC_ENABLE_REG 17
242#define BM_WUC_ENABLE_BIT (1 << 2)
243#define BM_WUC_HOST_WU_BIT (1 << 4)
244
245#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
246#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
247#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
bc7f75fa
AK		 248
249#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
250#define IGP01E1000_PHY_POLARITY_MASK 0x0078
251
252#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
253#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
254
255#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
256
257#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
258#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
259#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
260
261#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
262
263#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
cbe7a81a 264#define IGP01E1000_PSSR_MDIX 0x0800
bc7f75fa
AK		 265#define IGP01E1000_PSSR_SPEED_MASK 0xC000
266#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
267
268#define IGP02E1000_PHY_CHANNEL_NUM 4
269#define IGP02E1000_PHY_AGC_A 0x11B1
270#define IGP02E1000_PHY_AGC_B 0x12B1
271#define IGP02E1000_PHY_AGC_C 0x14B1
272#define IGP02E1000_PHY_AGC_D 0x18B1
273
274#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
275#define IGP02E1000_AGC_LENGTH_MASK 0x7F
276#define IGP02E1000_AGC_RANGE 15
277
278/* manage.c */
279#define E1000_VFTA_ENTRY_SHIFT 5
280#define E1000_VFTA_ENTRY_MASK 0x7F
281#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
282
283#define E1000_HICR_EN 0x01 /* Enable bit - RO */
ad68076e
BA		 284/* Driver sets this bit when done to put command in RAM */
285#define E1000_HICR_C 0x02
bc7f75fa
AK		 286#define E1000_HICR_FW_RESET_ENABLE 0x40
287#define E1000_HICR_FW_RESET 0x80
288
289#define E1000_FWSM_MODE_MASK 0xE
290#define E1000_FWSM_MODE_SHIFT 1
291
292#define E1000_MNG_IAMT_MODE 0x3
293#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
294#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
295#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
296#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
297#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
298#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
299
300/* nvm.c */
301#define E1000_STM_OPCODE 0xDB00
302
303#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
304#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
305#define E1000_KMRNCTRLSTA_REN 0x00200000
306#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
07818950
BA		 307#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
308#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
bc7f75fa 309#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
7d3cabbc
BA		 310#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
311#define E1000_KMRNCTRLSTA_K1_ENABLE 0x140E
312#define E1000_KMRNCTRLSTA_K1_DISABLE 0x1400
bc7f75fa
AK		 313
314#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
315#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
316#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
317#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
318
319/* IFE PHY Extended Status Control */
320#define IFE_PESC_POLARITY_REVERSED 0x0100
321
322/* IFE PHY Special Control */
323#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
324#define IFE_PSC_FORCE_POLARITY 0x0020
325
326/* IFE PHY Special Control and LED Control */
327#define IFE_PSCL_PROBE_MODE 0x0020
328#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
329#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
330
331/* IFE PHY MDIX Control */
332#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
333#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
334#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
335
336#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
337
338#define E1000_DEV_ID_82571EB_COPPER 0x105E
339#define E1000_DEV_ID_82571EB_FIBER 0x105F
340#define E1000_DEV_ID_82571EB_SERDES 0x1060
341#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
040babf9 342#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
bc7f75fa
AK		 343#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
344#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
040babf9
AK		 345#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
346#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
bc7f75fa
AK		 347#define E1000_DEV_ID_82572EI_COPPER 0x107D
348#define E1000_DEV_ID_82572EI_FIBER 0x107E
349#define E1000_DEV_ID_82572EI_SERDES 0x107F
350#define E1000_DEV_ID_82572EI 0x10B9
351#define E1000_DEV_ID_82573E 0x108B
352#define E1000_DEV_ID_82573E_IAMT 0x108C
353#define E1000_DEV_ID_82573L 0x109A
4662e82b 354#define E1000_DEV_ID_82574L 0x10D3
bef28b11 355#define E1000_DEV_ID_82574LA 0x10F6
8c81c9c3 356#define E1000_DEV_ID_82583V 0x150C
bc7f75fa
AK		 357
358#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
359#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
360#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
361#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
362
9e135a2e 363#define E1000_DEV_ID_ICH8_82567V_3 0x1501
bc7f75fa
AK		 364#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
365#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
366#define E1000_DEV_ID_ICH8_IGP_C 0x104B
367#define E1000_DEV_ID_ICH8_IFE 0x104C
368#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
369#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
370#define E1000_DEV_ID_ICH8_IGP_M 0x104D
371#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
2f15f9d6 372#define E1000_DEV_ID_ICH9_BM 0x10E5
97ac8cae
BA		 373#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
374#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
375#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
bc7f75fa
AK		 376#define E1000_DEV_ID_ICH9_IGP_C 0x294C
377#define E1000_DEV_ID_ICH9_IFE 0x10C0
378#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
379#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
97ac8cae
BA		 380#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
381#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
382#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
f4187b56
BA		 383#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
384#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
a4f58f54
BA		 385#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
386#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
387#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
388#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
bc7f75fa 389
4662e82b
BA		 390#define E1000_REVISION_4 4
391
bc7f75fa
AK		 392#define E1000_FUNC_1 1
393
608f8a0d
BA		 394#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
395#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
396
bc7f75fa
AK		 397enum e1000_mac_type {
398 e1000_82571,
399 e1000_82572,
400 e1000_82573,
4662e82b 401 e1000_82574,
8c81c9c3 402 e1000_82583,
bc7f75fa
AK		 403 e1000_80003es2lan,
404 e1000_ich8lan,
405 e1000_ich9lan,
f4187b56 406 e1000_ich10lan,
a4f58f54 407 e1000_pchlan,
bc7f75fa
AK		 408};
409
410enum e1000_media_type {
411 e1000_media_type_unknown = 0,
412 e1000_media_type_copper = 1,
413 e1000_media_type_fiber = 2,
414 e1000_media_type_internal_serdes = 3,
415 e1000_num_media_types
416};
417
418enum e1000_nvm_type {
419 e1000_nvm_unknown = 0,
420 e1000_nvm_none,
421 e1000_nvm_eeprom_spi,
422 e1000_nvm_flash_hw,
423 e1000_nvm_flash_sw
424};
425
426enum e1000_nvm_override {
427 e1000_nvm_override_none = 0,
428 e1000_nvm_override_spi_small,
429 e1000_nvm_override_spi_large
430};
431
432enum e1000_phy_type {
433 e1000_phy_unknown = 0,
434 e1000_phy_none,
435 e1000_phy_m88,
436 e1000_phy_igp,
437 e1000_phy_igp_2,
438 e1000_phy_gg82563,
439 e1000_phy_igp_3,
440 e1000_phy_ife,
97ac8cae 441 e1000_phy_bm,
a4f58f54
BA		 442 e1000_phy_82578,
443 e1000_phy_82577,
bc7f75fa
AK		 444};
445
446enum e1000_bus_width {
447 e1000_bus_width_unknown = 0,
448 e1000_bus_width_pcie_x1,
449 e1000_bus_width_pcie_x2,
450 e1000_bus_width_pcie_x4 = 4,
451 e1000_bus_width_32,
452 e1000_bus_width_64,
453 e1000_bus_width_reserved
454};
455
456enum e1000_1000t_rx_status {
457 e1000_1000t_rx_status_not_ok = 0,
458 e1000_1000t_rx_status_ok,
459 e1000_1000t_rx_status_undefined = 0xFF
460};
461
462enum e1000_rev_polarity{
463 e1000_rev_polarity_normal = 0,
464 e1000_rev_polarity_reversed,
465 e1000_rev_polarity_undefined = 0xFF
466};
467
5c48ef3e 468enum e1000_fc_mode {
bc7f75fa
AK		 469 e1000_fc_none = 0,
470 e1000_fc_rx_pause,
471 e1000_fc_tx_pause,
472 e1000_fc_full,
473 e1000_fc_default = 0xFF
474};
475
476enum e1000_ms_type {
477 e1000_ms_hw_default = 0,
478 e1000_ms_force_master,
479 e1000_ms_force_slave,
480 e1000_ms_auto
481};
482
483enum e1000_smart_speed {
484 e1000_smart_speed_default = 0,
485 e1000_smart_speed_on,
486 e1000_smart_speed_off
487};
488
c9523379 489enum e1000_serdes_link_state {
490 e1000_serdes_link_down = 0,
491 e1000_serdes_link_autoneg_progress,
492 e1000_serdes_link_autoneg_complete,
493 e1000_serdes_link_forced_up
494};
495
bc7f75fa
AK		 496/* Receive Descriptor */
497struct e1000_rx_desc {
a39fe742
AV		 498 __le64 buffer_addr; /* Address of the descriptor's data buffer */
499 __le16 length; /* Length of data DMAed into data buffer */
500 __le16 csum; /* Packet checksum */
bc7f75fa
AK		 501 u8 status; /* Descriptor status */
502 u8 errors; /* Descriptor Errors */
a39fe742 503 __le16 special;
bc7f75fa
AK		 504};
505
506/* Receive Descriptor - Extended */
507union e1000_rx_desc_extended {
508 struct {
a39fe742
AV		 509 __le64 buffer_addr;
510 __le64 reserved;
bc7f75fa
AK		 511 } read;
512 struct {
513 struct {
a39fe742 514 __le32 mrq; /* Multiple Rx Queues */
bc7f75fa 515 union {
a39fe742 516 __le32 rss; /* RSS Hash */
bc7f75fa 517 struct {
a39fe742
AV		 518 __le16 ip_id; /* IP id */
519 __le16 csum; /* Packet Checksum */
bc7f75fa
AK		 520 } csum_ip;
521 } hi_dword;
522 } lower;
523 struct {
a39fe742
AV		 524 __le32 status_error; /* ext status/error */
525 __le16 length;
526 __le16 vlan; /* VLAN tag */
bc7f75fa
AK		 527 } upper;
528 } wb; /* writeback */
529};
530
531#define MAX_PS_BUFFERS 4
532/* Receive Descriptor - Packet Split */
533union e1000_rx_desc_packet_split {
534 struct {
535 /* one buffer for protocol header(s), three data buffers */
a39fe742 536 __le64 buffer_addr[MAX_PS_BUFFERS];
bc7f75fa
AK		 537 } read;
538 struct {
539 struct {
a39fe742 540 __le32 mrq; /* Multiple Rx Queues */
bc7f75fa 541 union {
a39fe742 542 __le32 rss; /* RSS Hash */
bc7f75fa 543 struct {
a39fe742
AV		 544 __le16 ip_id; /* IP id */
545 __le16 csum; /* Packet Checksum */
bc7f75fa
AK		 546 } csum_ip;
547 } hi_dword;
548 } lower;
549 struct {
a39fe742
AV		 550 __le32 status_error; /* ext status/error */
551 __le16 length0; /* length of buffer 0 */
552 __le16 vlan; /* VLAN tag */
bc7f75fa
AK		 553 } middle;
554 struct {
a39fe742
AV		 555 __le16 header_status;
556 __le16 length[3]; /* length of buffers 1-3 */
bc7f75fa 557 } upper;
a39fe742 558 __le64 reserved;
bc7f75fa
AK		 559 } wb; /* writeback */
560};
561
562/* Transmit Descriptor */
563struct e1000_tx_desc {
a39fe742 564 __le64 buffer_addr; /* Address of the descriptor's data buffer */
bc7f75fa 565 union {
a39fe742 566 __le32 data;
bc7f75fa 567 struct {
a39fe742 568 __le16 length; /* Data buffer length */
bc7f75fa
AK		 569 u8 cso; /* Checksum offset */
570 u8 cmd; /* Descriptor control */
571 } flags;
572 } lower;
573 union {
a39fe742 574 __le32 data;
bc7f75fa
AK		 575 struct {
576 u8 status; /* Descriptor status */
577 u8 css; /* Checksum start */
a39fe742 578 __le16 special;
bc7f75fa
AK		 579 } fields;
580 } upper;
581};
582
583/* Offload Context Descriptor */
584struct e1000_context_desc {
585 union {
a39fe742 586 __le32 ip_config;
bc7f75fa
AK		 587 struct {
588 u8 ipcss; /* IP checksum start */
589 u8 ipcso; /* IP checksum offset */
a39fe742 590 __le16 ipcse; /* IP checksum end */
bc7f75fa
AK		 591 } ip_fields;
592 } lower_setup;
593 union {
a39fe742 594 __le32 tcp_config;
bc7f75fa
AK		 595 struct {
596 u8 tucss; /* TCP checksum start */
597 u8 tucso; /* TCP checksum offset */
a39fe742 598 __le16 tucse; /* TCP checksum end */
bc7f75fa
AK		 599 } tcp_fields;
600 } upper_setup;
a39fe742 601 __le32 cmd_and_length;
bc7f75fa 602 union {
a39fe742 603 __le32 data;
bc7f75fa
AK		 604 struct {
605 u8 status; /* Descriptor status */
606 u8 hdr_len; /* Header length */
a39fe742 607 __le16 mss; /* Maximum segment size */
bc7f75fa
AK		 608 } fields;
609 } tcp_seg_setup;
610};
611
612/* Offload data descriptor */
613struct e1000_data_desc {
a39fe742 614 __le64 buffer_addr; /* Address of the descriptor's buffer address */
bc7f75fa 615 union {
a39fe742 616 __le32 data;
bc7f75fa 617 struct {
a39fe742 618 __le16 length; /* Data buffer length */
bc7f75fa
AK		 619 u8 typ_len_ext;
620 u8 cmd;
621 } flags;
622 } lower;
623 union {
a39fe742 624 __le32 data;
bc7f75fa
AK		 625 struct {
626 u8 status; /* Descriptor status */
627 u8 popts; /* Packet Options */
a39fe742 628 __le16 special; /* */
bc7f75fa
AK		 629 } fields;
630 } upper;
631};
632
633/* Statistics counters collected by the MAC */
634struct e1000_hw_stats {
635 u64 crcerrs;
636 u64 algnerrc;
637 u64 symerrs;
638 u64 rxerrc;
639 u64 mpc;
640 u64 scc;
641 u64 ecol;
642 u64 mcc;
643 u64 latecol;
644 u64 colc;
645 u64 dc;
646 u64 tncrs;
647 u64 sec;
648 u64 cexterr;
649 u64 rlec;
650 u64 xonrxc;
651 u64 xontxc;
652 u64 xoffrxc;
653 u64 xofftxc;
654 u64 fcruc;
655 u64 prc64;
656 u64 prc127;
657 u64 prc255;
658 u64 prc511;
659 u64 prc1023;
660 u64 prc1522;
661 u64 gprc;
662 u64 bprc;
663 u64 mprc;
664 u64 gptc;
7c25769f
BA		 665 u64 gorc;
666 u64 gotc;
bc7f75fa
AK		 667 u64 rnbc;
668 u64 ruc;
669 u64 rfc;
670 u64 roc;
671 u64 rjc;
672 u64 mgprc;
673 u64 mgpdc;
674 u64 mgptc;
7c25769f
BA		 675 u64 tor;
676 u64 tot;
bc7f75fa
AK		 677 u64 tpr;
678 u64 tpt;
679 u64 ptc64;
680 u64 ptc127;
681 u64 ptc255;
682 u64 ptc511;
683 u64 ptc1023;
684 u64 ptc1522;
685 u64 mptc;
686 u64 bptc;
687 u64 tsctc;
688 u64 tsctfc;
689 u64 iac;
690 u64 icrxptc;
691 u64 icrxatc;
692 u64 ictxptc;
693 u64 ictxatc;
694 u64 ictxqec;
695 u64 ictxqmtc;
696 u64 icrxdmtc;
697 u64 icrxoc;
698};
699
700struct e1000_phy_stats {
701 u32 idle_errors;
702 u32 receive_errors;
703};
704
705struct e1000_host_mng_dhcp_cookie {
706 u32 signature;
707 u8 status;
708 u8 reserved0;
709 u16 vlan_id;
710 u32 reserved1;
711 u16 reserved2;
712 u8 reserved3;
713 u8 checksum;
714};
715
716/* Host Interface "Rev 1" */
717struct e1000_host_command_header {
718 u8 command_id;
719 u8 command_length;
720 u8 command_options;
721 u8 checksum;
722};
723
724#define E1000_HI_MAX_DATA_LENGTH 252
725struct e1000_host_command_info {
726 struct e1000_host_command_header command_header;
727 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
728};
729
730/* Host Interface "Rev 2" */
731struct e1000_host_mng_command_header {
732 u8 command_id;
733 u8 checksum;
734 u16 reserved1;
735 u16 reserved2;
736 u16 command_length;
737};
738
739#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
740struct e1000_host_mng_command_info {
741 struct e1000_host_mng_command_header command_header;
742 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
743};
744
745/* Function pointers and static data for the MAC. */
746struct e1000_mac_operations {
a4f58f54 747 s32 (*id_led_init)(struct e1000_hw *);
4662e82b 748 bool (*check_mng_mode)(struct e1000_hw *);
bc7f75fa
AK		 749 s32 (*check_for_link)(struct e1000_hw *);
750 s32 (*cleanup_led)(struct e1000_hw *);
751 void (*clear_hw_cntrs)(struct e1000_hw *);
caaddaf8 752 void (*clear_vfta)(struct e1000_hw *);
bc7f75fa 753 s32 (*get_bus_info)(struct e1000_hw *);
f4d2dd4c 754 void (*set_lan_id)(struct e1000_hw *);
bc7f75fa
AK		 755 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
756 s32 (*led_on)(struct e1000_hw *);
757 s32 (*led_off)(struct e1000_hw *);
ab8932f3 758 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
bc7f75fa
AK		 759 s32 (*reset_hw)(struct e1000_hw *);
760 s32 (*init_hw)(struct e1000_hw *);
761 s32 (*setup_link)(struct e1000_hw *);
762 s32 (*setup_physical_interface)(struct e1000_hw *);
a4f58f54 763 s32 (*setup_led)(struct e1000_hw *);
caaddaf8 764 void (*write_vfta)(struct e1000_hw *, u32, u32);
608f8a0d 765 s32 (*read_mac_addr)(struct e1000_hw *);
bc7f75fa
AK		 766};
767
768/* Function pointers for the PHY. */
769struct e1000_phy_operations {
94d8186a
BA		 770 s32 (*acquire)(struct e1000_hw *);
771 s32 (*cfg_on_link_up)(struct e1000_hw *);
a4f58f54 772 s32 (*check_polarity)(struct e1000_hw *);
bc7f75fa 773 s32 (*check_reset_block)(struct e1000_hw *);
94d8186a 774 s32 (*commit)(struct e1000_hw *);
bc7f75fa
AK		 775 s32 (*force_speed_duplex)(struct e1000_hw *);
776 s32 (*get_cfg_done)(struct e1000_hw *hw);
777 s32 (*get_cable_length)(struct e1000_hw *);
94d8186a
BA		 778 s32 (*get_info)(struct e1000_hw *);
779 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
780 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
781 void (*release)(struct e1000_hw *);
782 s32 (*reset)(struct e1000_hw *);
bc7f75fa
AK		 783 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
784 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
94d8186a
BA		 785 s32 (*write_reg)(struct e1000_hw *, u32, u16);
786 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
17f208de
BA		 787 void (*power_up)(struct e1000_hw *);
788 void (*power_down)(struct e1000_hw *);
bc7f75fa
AK		 789};
790
791/* Function pointers for the NVM. */
792struct e1000_nvm_operations {
94d8186a
BA		 793 s32 (*acquire)(struct e1000_hw *);
794 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
795 void (*release)(struct e1000_hw *);
796 s32 (*update)(struct e1000_hw *);
bc7f75fa 797 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
94d8186a
BA		 798 s32 (*validate)(struct e1000_hw *);
799 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
bc7f75fa
AK		 800};
801
802struct e1000_mac_info {
803 struct e1000_mac_operations ops;
804
805 u8 addr[6];
806 u8 perm_addr[6];
807
808 enum e1000_mac_type type;
bc7f75fa
AK		 809
810 u32 collision_delta;
811 u32 ledctl_default;
812 u32 ledctl_mode1;
813 u32 ledctl_mode2;
bc7f75fa 814 u32 mc_filter_type;
bc7f75fa
AK		 815 u32 tx_packet_delta;
816 u32 txcw;
817
818 u16 current_ifs_val;
819 u16 ifs_max_val;
820 u16 ifs_min_val;
821 u16 ifs_ratio;
822 u16 ifs_step_size;
823 u16 mta_reg_count;
ab8932f3
BA		 824
825 /* Maximum size of the MTA register table in all supported adapters */
826 #define MAX_MTA_REG 128
827 u32 mta_shadow[MAX_MTA_REG];
bc7f75fa 828 u16 rar_entry_count;
bc7f75fa
AK		 829
830 u8 forced_speed_duplex;
831
f464ba87 832 bool adaptive_ifs;
a65a4a0d 833 bool has_fwsm;
bc7f75fa
AK		 834 bool arc_subsystem_valid;
835 bool autoneg;
836 bool autoneg_failed;
837 bool get_link_status;
838 bool in_ifs_mode;
839 bool serdes_has_link;
840 bool tx_pkt_filtering;
c9523379 841 enum e1000_serdes_link_state serdes_link_state;
bc7f75fa
AK		 842};
843
844struct e1000_phy_info {
845 struct e1000_phy_operations ops;
846
847 enum e1000_phy_type type;
848
849 enum e1000_1000t_rx_status local_rx;
850 enum e1000_1000t_rx_status remote_rx;
851 enum e1000_ms_type ms_type;
852 enum e1000_ms_type original_ms_type;
853 enum e1000_rev_polarity cable_polarity;
854 enum e1000_smart_speed smart_speed;
855
856 u32 addr;
857 u32 id;
858 u32 reset_delay_us; /* in usec */
859 u32 revision;
860
318a94d6
JK		 861 enum e1000_media_type media_type;
862
bc7f75fa
AK		 863 u16 autoneg_advertised;
864 u16 autoneg_mask;
865 u16 cable_length;
866 u16 max_cable_length;
867 u16 min_cable_length;
868
869 u8 mdix;
870
871 bool disable_polarity_correction;
872 bool is_mdix;
873 bool polarity_correction;
874 bool speed_downgraded;
318a94d6 875 bool autoneg_wait_to_complete;
bc7f75fa
AK		 876};
877
878struct e1000_nvm_info {
879 struct e1000_nvm_operations ops;
880
881 enum e1000_nvm_type type;
882 enum e1000_nvm_override override;
883
884 u32 flash_bank_size;
885 u32 flash_base_addr;
886
887 u16 word_size;
888 u16 delay_usec;
889 u16 address_bits;
890 u16 opcode_bits;
891 u16 page_size;
892};
893
894struct e1000_bus_info {
895 enum e1000_bus_width width;
896
897 u16 func;
898};
899
318a94d6
JK		 900struct e1000_fc_info {
901 u32 high_water; /* Flow control high-water mark */
902 u32 low_water; /* Flow control low-water mark */
903 u16 pause_time; /* Flow control pause timer */
a305595b 904 u16 refresh_time; /* Flow control refresh timer */
318a94d6
JK		 905 bool send_xon; /* Flow control send XON */
906 bool strict_ieee; /* Strict IEEE mode */
5c48ef3e
BA		 907 enum e1000_fc_mode current_mode; /* FC mode in effect */
908 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
318a94d6
JK		 909};
910
bc7f75fa
AK		 911struct e1000_dev_spec_82571 {
912 bool laa_is_present;
23a2d1b2 913 u32 smb_counter;
bc7f75fa
AK		 914};
915
3421eecd
BA		 916struct e1000_dev_spec_80003es2lan {
917 bool mdic_wa_enable;
918};
919
bc7f75fa
AK		 920struct e1000_shadow_ram {
921 u16 value;
922 bool modified;
923};
924
925#define E1000_ICH8_SHADOW_RAM_WORDS 2048
926
927struct e1000_dev_spec_ich8lan {
928 bool kmrn_lock_loss_workaround_enabled;
929 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
1d5846b9 930 bool nvm_k1_enabled;
bc7f75fa
AK		 931};
932
933struct e1000_hw {
934 struct e1000_adapter *adapter;
935
936 u8 __iomem *hw_addr;
937 u8 __iomem *flash_address;
938
939 struct e1000_mac_info mac;
318a94d6 940 struct e1000_fc_info fc;
bc7f75fa
AK		 941 struct e1000_phy_info phy;
942 struct e1000_nvm_info nvm;
943 struct e1000_bus_info bus;
944 struct e1000_host_mng_dhcp_cookie mng_cookie;
945
946 union {
947 struct e1000_dev_spec_82571 e82571;
3421eecd 948 struct e1000_dev_spec_80003es2lan e80003es2lan;
bc7f75fa
AK		 949 struct e1000_dev_spec_ich8lan ich8lan;
950 } dev_spec;
bc7f75fa
AK		 951};
952
bc7f75fa 953#endif
Linux 6.x block layer and io_uring tree(s)