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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
ad68076e | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 80003ES2LAN Gigabit Ethernet Controller (Copper) | |
31 | * 80003ES2LAN Gigabit Ethernet Controller (Serdes) | |
32 | */ | |
33 | ||
34 | #include <linux/netdevice.h> | |
35 | #include <linux/ethtool.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/pci.h> | |
38 | ||
39 | #include "e1000.h" | |
40 | ||
41 | #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 | |
42 | #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 | |
43 | #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 | |
2d9498f3 | 44 | #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F |
bc7f75fa AK |
45 | |
46 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 | |
47 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 | |
48 | #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 | |
49 | ||
50 | #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 | |
51 | #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 | |
2d9498f3 | 52 | #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 |
bc7f75fa AK |
53 | |
54 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ | |
55 | #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 | |
56 | ||
57 | #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 | |
58 | #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 | |
59 | ||
60 | /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ | |
61 | #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */ | |
62 | #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 | |
63 | #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ | |
64 | #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ | |
65 | #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ | |
66 | ||
67 | /* PHY Specific Control Register 2 (Page 0, Register 26) */ | |
68 | #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 | |
69 | /* 1=Reverse Auto-Negotiation */ | |
70 | ||
71 | /* MAC Specific Control Register (Page 2, Register 21) */ | |
72 | /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ | |
73 | #define GG82563_MSCR_TX_CLK_MASK 0x0007 | |
74 | #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 | |
75 | #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 | |
76 | #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 | |
77 | ||
78 | #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ | |
79 | ||
80 | /* DSP Distance Register (Page 5, Register 26) */ | |
81 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M | |
82 | 1 = 50-80M | |
83 | 2 = 80-110M | |
84 | 3 = 110-140M | |
85 | 4 = >140M */ | |
86 | ||
87 | /* Kumeran Mode Control Register (Page 193, Register 16) */ | |
88 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 | |
89 | ||
2d9498f3 DG |
90 | /* Max number of times Kumeran read/write should be validated */ |
91 | #define GG82563_MAX_KMRN_RETRY 0x5 | |
92 | ||
bc7f75fa AK |
93 | /* Power Management Control Register (Page 193, Register 20) */ |
94 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 | |
95 | /* 1=Enable SERDES Electrical Idle */ | |
96 | ||
97 | /* In-Band Control Register (Page 194, Register 18) */ | |
98 | #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ | |
99 | ||
ad68076e BA |
100 | /* |
101 | * A table for the GG82563 cable length where the range is defined | |
bc7f75fa AK |
102 | * with a lower bound at "index" and the upper bound at |
103 | * "index + 5". | |
104 | */ | |
105 | static const u16 e1000_gg82563_cable_length_table[] = | |
106 | { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; | |
107 | ||
108 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); | |
109 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
110 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
111 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); | |
112 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); | |
113 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); | |
114 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); | |
75eb0fad BA |
115 | static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); |
116 | static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, | |
117 | u16 *data); | |
118 | static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, | |
119 | u16 data); | |
bc7f75fa AK |
120 | |
121 | /** | |
122 | * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. | |
123 | * @hw: pointer to the HW structure | |
124 | * | |
125 | * This is a function pointer entry point called by the api module. | |
126 | **/ | |
127 | static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) | |
128 | { | |
129 | struct e1000_phy_info *phy = &hw->phy; | |
130 | s32 ret_val; | |
131 | ||
318a94d6 | 132 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
133 | phy->type = e1000_phy_none; |
134 | return 0; | |
135 | } | |
136 | ||
137 | phy->addr = 1; | |
138 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
139 | phy->reset_delay_us = 100; | |
140 | phy->type = e1000_phy_gg82563; | |
141 | ||
142 | /* This can only be done after all function pointers are setup. */ | |
143 | ret_val = e1000e_get_phy_id(hw); | |
144 | ||
145 | /* Verify phy id */ | |
146 | if (phy->id != GG82563_E_PHY_ID) | |
147 | return -E1000_ERR_PHY; | |
148 | ||
149 | return ret_val; | |
150 | } | |
151 | ||
152 | /** | |
153 | * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. | |
154 | * @hw: pointer to the HW structure | |
155 | * | |
156 | * This is a function pointer entry point called by the api module. | |
157 | **/ | |
158 | static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) | |
159 | { | |
160 | struct e1000_nvm_info *nvm = &hw->nvm; | |
161 | u32 eecd = er32(EECD); | |
162 | u16 size; | |
163 | ||
164 | nvm->opcode_bits = 8; | |
165 | nvm->delay_usec = 1; | |
166 | switch (nvm->override) { | |
167 | case e1000_nvm_override_spi_large: | |
168 | nvm->page_size = 32; | |
169 | nvm->address_bits = 16; | |
170 | break; | |
171 | case e1000_nvm_override_spi_small: | |
172 | nvm->page_size = 8; | |
173 | nvm->address_bits = 8; | |
174 | break; | |
175 | default: | |
176 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
177 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
178 | break; | |
179 | } | |
180 | ||
ad68076e | 181 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
182 | |
183 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
184 | E1000_EECD_SIZE_EX_SHIFT); | |
185 | ||
ad68076e BA |
186 | /* |
187 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
188 | * for setting word_size. |
189 | */ | |
190 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
191 | |
192 | /* EEPROM access above 16k is unsupported */ | |
193 | if (size > 14) | |
194 | size = 14; | |
bc7f75fa AK |
195 | nvm->word_size = 1 << size; |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | /** | |
201 | * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. | |
202 | * @hw: pointer to the HW structure | |
203 | * | |
204 | * This is a function pointer entry point called by the api module. | |
205 | **/ | |
206 | static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) | |
207 | { | |
208 | struct e1000_hw *hw = &adapter->hw; | |
209 | struct e1000_mac_info *mac = &hw->mac; | |
210 | struct e1000_mac_operations *func = &mac->ops; | |
211 | ||
212 | /* Set media type */ | |
213 | switch (adapter->pdev->device) { | |
214 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
318a94d6 | 215 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
216 | break; |
217 | default: | |
318a94d6 | 218 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
219 | break; |
220 | } | |
221 | ||
222 | /* Set mta register count */ | |
223 | mac->mta_reg_count = 128; | |
224 | /* Set rar entry count */ | |
225 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
226 | /* Set if manageability features are enabled. */ | |
ad68076e | 227 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; |
bc7f75fa AK |
228 | |
229 | /* check for link */ | |
318a94d6 | 230 | switch (hw->phy.media_type) { |
bc7f75fa AK |
231 | case e1000_media_type_copper: |
232 | func->setup_physical_interface = e1000_setup_copper_link_80003es2lan; | |
233 | func->check_for_link = e1000e_check_for_copper_link; | |
234 | break; | |
235 | case e1000_media_type_fiber: | |
236 | func->setup_physical_interface = e1000e_setup_fiber_serdes_link; | |
237 | func->check_for_link = e1000e_check_for_fiber_link; | |
238 | break; | |
239 | case e1000_media_type_internal_serdes: | |
240 | func->setup_physical_interface = e1000e_setup_fiber_serdes_link; | |
241 | func->check_for_link = e1000e_check_for_serdes_link; | |
242 | break; | |
243 | default: | |
244 | return -E1000_ERR_CONFIG; | |
245 | break; | |
246 | } | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
69e3fd8c | 251 | static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter) |
bc7f75fa AK |
252 | { |
253 | struct e1000_hw *hw = &adapter->hw; | |
254 | s32 rc; | |
255 | ||
256 | rc = e1000_init_mac_params_80003es2lan(adapter); | |
257 | if (rc) | |
258 | return rc; | |
259 | ||
260 | rc = e1000_init_nvm_params_80003es2lan(hw); | |
261 | if (rc) | |
262 | return rc; | |
263 | ||
264 | rc = e1000_init_phy_params_80003es2lan(hw); | |
265 | if (rc) | |
266 | return rc; | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
271 | /** | |
272 | * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY | |
273 | * @hw: pointer to the HW structure | |
274 | * | |
275 | * A wrapper to acquire access rights to the correct PHY. This is a | |
276 | * function pointer entry point called by the api module. | |
277 | **/ | |
278 | static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) | |
279 | { | |
280 | u16 mask; | |
281 | ||
282 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
bc7f75fa AK |
283 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); |
284 | } | |
285 | ||
286 | /** | |
287 | * e1000_release_phy_80003es2lan - Release rights to access PHY | |
288 | * @hw: pointer to the HW structure | |
289 | * | |
290 | * A wrapper to release access rights to the correct PHY. This is a | |
291 | * function pointer entry point called by the api module. | |
292 | **/ | |
293 | static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) | |
294 | { | |
295 | u16 mask; | |
296 | ||
297 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
75eb0fad BA |
298 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
299 | } | |
300 | ||
301 | /** | |
302 | * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register | |
303 | * @hw: pointer to the HW structure | |
304 | * | |
305 | * Acquire the semaphore to access the Kumeran interface. | |
306 | * | |
307 | **/ | |
308 | static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) | |
309 | { | |
310 | u16 mask; | |
311 | ||
312 | mask = E1000_SWFW_CSR_SM; | |
313 | ||
314 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); | |
315 | } | |
316 | ||
317 | /** | |
318 | * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register | |
319 | * @hw: pointer to the HW structure | |
320 | * | |
321 | * Release the semaphore used to access the Kumeran interface | |
322 | **/ | |
323 | static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) | |
324 | { | |
325 | u16 mask; | |
326 | ||
327 | mask = E1000_SWFW_CSR_SM; | |
2d9498f3 | 328 | |
bc7f75fa AK |
329 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
330 | } | |
331 | ||
332 | /** | |
333 | * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM | |
334 | * @hw: pointer to the HW structure | |
335 | * | |
336 | * Acquire the semaphore to access the EEPROM. This is a function | |
337 | * pointer entry point called by the api module. | |
338 | **/ | |
339 | static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) | |
340 | { | |
341 | s32 ret_val; | |
342 | ||
343 | ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
344 | if (ret_val) | |
345 | return ret_val; | |
346 | ||
347 | ret_val = e1000e_acquire_nvm(hw); | |
348 | ||
349 | if (ret_val) | |
350 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
351 | ||
352 | return ret_val; | |
353 | } | |
354 | ||
355 | /** | |
356 | * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM | |
357 | * @hw: pointer to the HW structure | |
358 | * | |
359 | * Release the semaphore used to access the EEPROM. This is a | |
360 | * function pointer entry point called by the api module. | |
361 | **/ | |
362 | static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) | |
363 | { | |
364 | e1000e_release_nvm(hw); | |
365 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
366 | } | |
367 | ||
368 | /** | |
369 | * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore | |
370 | * @hw: pointer to the HW structure | |
371 | * @mask: specifies which semaphore to acquire | |
372 | * | |
373 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
374 | * will also specify which port we're acquiring the lock for. | |
375 | **/ | |
376 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
377 | { | |
378 | u32 swfw_sync; | |
379 | u32 swmask = mask; | |
380 | u32 fwmask = mask << 16; | |
381 | s32 i = 0; | |
75eb0fad | 382 | s32 timeout = 50; |
bc7f75fa AK |
383 | |
384 | while (i < timeout) { | |
385 | if (e1000e_get_hw_semaphore(hw)) | |
386 | return -E1000_ERR_SWFW_SYNC; | |
387 | ||
388 | swfw_sync = er32(SW_FW_SYNC); | |
389 | if (!(swfw_sync & (fwmask | swmask))) | |
390 | break; | |
391 | ||
ad68076e BA |
392 | /* |
393 | * Firmware currently using resource (fwmask) | |
394 | * or other software thread using resource (swmask) | |
395 | */ | |
bc7f75fa AK |
396 | e1000e_put_hw_semaphore(hw); |
397 | mdelay(5); | |
398 | i++; | |
399 | } | |
400 | ||
401 | if (i == timeout) { | |
402 | hw_dbg(hw, | |
403 | "Driver can't access resource, SW_FW_SYNC timeout.\n"); | |
404 | return -E1000_ERR_SWFW_SYNC; | |
405 | } | |
406 | ||
407 | swfw_sync |= swmask; | |
408 | ew32(SW_FW_SYNC, swfw_sync); | |
409 | ||
410 | e1000e_put_hw_semaphore(hw); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | /** | |
416 | * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore | |
417 | * @hw: pointer to the HW structure | |
418 | * @mask: specifies which semaphore to acquire | |
419 | * | |
420 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
421 | * will also specify which port we're releasing the lock for. | |
422 | **/ | |
423 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
424 | { | |
425 | u32 swfw_sync; | |
426 | ||
427 | while (e1000e_get_hw_semaphore(hw) != 0); | |
428 | /* Empty */ | |
429 | ||
430 | swfw_sync = er32(SW_FW_SYNC); | |
431 | swfw_sync &= ~mask; | |
432 | ew32(SW_FW_SYNC, swfw_sync); | |
433 | ||
434 | e1000e_put_hw_semaphore(hw); | |
435 | } | |
436 | ||
437 | /** | |
438 | * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register | |
439 | * @hw: pointer to the HW structure | |
440 | * @offset: offset of the register to read | |
441 | * @data: pointer to the data returned from the operation | |
442 | * | |
443 | * Read the GG82563 PHY register. This is a function pointer entry | |
444 | * point called by the api module. | |
445 | **/ | |
446 | static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
447 | u32 offset, u16 *data) | |
448 | { | |
449 | s32 ret_val; | |
450 | u32 page_select; | |
451 | u16 temp; | |
452 | ||
2d9498f3 DG |
453 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
454 | if (ret_val) | |
455 | return ret_val; | |
456 | ||
bc7f75fa | 457 | /* Select Configuration Page */ |
2d9498f3 | 458 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 459 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 460 | } else { |
ad68076e BA |
461 | /* |
462 | * Use Alternative Page Select register to access | |
bc7f75fa AK |
463 | * registers 30 and 31 |
464 | */ | |
465 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 466 | } |
bc7f75fa AK |
467 | |
468 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
469 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
470 | if (ret_val) { | |
471 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 472 | return ret_val; |
2d9498f3 | 473 | } |
bc7f75fa | 474 | |
ad68076e BA |
475 | /* |
476 | * The "ready" bit in the MDIC register may be incorrectly set | |
bc7f75fa AK |
477 | * before the device has completed the "Page Select" MDI |
478 | * transaction. So we wait 200us after each MDI command... | |
479 | */ | |
480 | udelay(200); | |
481 | ||
482 | /* ...and verify the command was successful. */ | |
2d9498f3 | 483 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
bc7f75fa AK |
484 | |
485 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { | |
486 | ret_val = -E1000_ERR_PHY; | |
2d9498f3 | 487 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
488 | return ret_val; |
489 | } | |
490 | ||
491 | udelay(200); | |
492 | ||
2d9498f3 DG |
493 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
494 | data); | |
bc7f75fa AK |
495 | |
496 | udelay(200); | |
2d9498f3 | 497 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
498 | |
499 | return ret_val; | |
500 | } | |
501 | ||
502 | /** | |
503 | * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register | |
504 | * @hw: pointer to the HW structure | |
505 | * @offset: offset of the register to read | |
506 | * @data: value to write to the register | |
507 | * | |
508 | * Write to the GG82563 PHY register. This is a function pointer entry | |
509 | * point called by the api module. | |
510 | **/ | |
511 | static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
512 | u32 offset, u16 data) | |
513 | { | |
514 | s32 ret_val; | |
515 | u32 page_select; | |
516 | u16 temp; | |
517 | ||
2d9498f3 DG |
518 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
519 | if (ret_val) | |
520 | return ret_val; | |
521 | ||
bc7f75fa | 522 | /* Select Configuration Page */ |
2d9498f3 | 523 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 524 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 525 | } else { |
ad68076e BA |
526 | /* |
527 | * Use Alternative Page Select register to access | |
bc7f75fa AK |
528 | * registers 30 and 31 |
529 | */ | |
530 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 531 | } |
bc7f75fa AK |
532 | |
533 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
534 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
535 | if (ret_val) { | |
536 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 537 | return ret_val; |
2d9498f3 | 538 | } |
bc7f75fa AK |
539 | |
540 | ||
ad68076e BA |
541 | /* |
542 | * The "ready" bit in the MDIC register may be incorrectly set | |
bc7f75fa AK |
543 | * before the device has completed the "Page Select" MDI |
544 | * transaction. So we wait 200us after each MDI command... | |
545 | */ | |
546 | udelay(200); | |
547 | ||
548 | /* ...and verify the command was successful. */ | |
2d9498f3 | 549 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
bc7f75fa | 550 | |
2d9498f3 DG |
551 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
552 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 553 | return -E1000_ERR_PHY; |
2d9498f3 | 554 | } |
bc7f75fa AK |
555 | |
556 | udelay(200); | |
557 | ||
2d9498f3 DG |
558 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
559 | data); | |
bc7f75fa AK |
560 | |
561 | udelay(200); | |
2d9498f3 | 562 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
563 | |
564 | return ret_val; | |
565 | } | |
566 | ||
567 | /** | |
568 | * e1000_write_nvm_80003es2lan - Write to ESB2 NVM | |
569 | * @hw: pointer to the HW structure | |
570 | * @offset: offset of the register to read | |
571 | * @words: number of words to write | |
572 | * @data: buffer of data to write to the NVM | |
573 | * | |
574 | * Write "words" of data to the ESB2 NVM. This is a function | |
575 | * pointer entry point called by the api module. | |
576 | **/ | |
577 | static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, | |
578 | u16 words, u16 *data) | |
579 | { | |
580 | return e1000e_write_nvm_spi(hw, offset, words, data); | |
581 | } | |
582 | ||
583 | /** | |
584 | * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete | |
585 | * @hw: pointer to the HW structure | |
586 | * | |
587 | * Wait a specific amount of time for manageability processes to complete. | |
588 | * This is a function pointer entry point called by the phy module. | |
589 | **/ | |
590 | static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) | |
591 | { | |
592 | s32 timeout = PHY_CFG_TIMEOUT; | |
593 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
594 | ||
595 | if (hw->bus.func == 1) | |
596 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
597 | ||
598 | while (timeout) { | |
599 | if (er32(EEMNGCTL) & mask) | |
600 | break; | |
601 | msleep(1); | |
602 | timeout--; | |
603 | } | |
604 | if (!timeout) { | |
605 | hw_dbg(hw, "MNG configuration cycle has not completed.\n"); | |
606 | return -E1000_ERR_RESET; | |
607 | } | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
612 | /** | |
613 | * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex | |
614 | * @hw: pointer to the HW structure | |
615 | * | |
616 | * Force the speed and duplex settings onto the PHY. This is a | |
617 | * function pointer entry point called by the phy module. | |
618 | **/ | |
619 | static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) | |
620 | { | |
621 | s32 ret_val; | |
622 | u16 phy_data; | |
623 | bool link; | |
624 | ||
ad68076e BA |
625 | /* |
626 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
bc7f75fa AK |
627 | * forced whenever speed and duplex are forced. |
628 | */ | |
629 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
630 | if (ret_val) | |
631 | return ret_val; | |
632 | ||
633 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
634 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); | |
635 | if (ret_val) | |
636 | return ret_val; | |
637 | ||
638 | hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data); | |
639 | ||
640 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
641 | if (ret_val) | |
642 | return ret_val; | |
643 | ||
644 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
645 | ||
646 | /* Reset the phy to commit changes. */ | |
647 | phy_data |= MII_CR_RESET; | |
648 | ||
649 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); | |
650 | if (ret_val) | |
651 | return ret_val; | |
652 | ||
653 | udelay(1); | |
654 | ||
318a94d6 | 655 | if (hw->phy.autoneg_wait_to_complete) { |
bc7f75fa AK |
656 | hw_dbg(hw, "Waiting for forced speed/duplex link " |
657 | "on GG82563 phy.\n"); | |
658 | ||
659 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
660 | 100000, &link); | |
661 | if (ret_val) | |
662 | return ret_val; | |
663 | ||
664 | if (!link) { | |
ad68076e BA |
665 | /* |
666 | * We didn't get link. | |
bc7f75fa AK |
667 | * Reset the DSP and cross our fingers. |
668 | */ | |
669 | ret_val = e1000e_phy_reset_dsp(hw); | |
670 | if (ret_val) | |
671 | return ret_val; | |
672 | } | |
673 | ||
674 | /* Try once more */ | |
675 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
676 | 100000, &link); | |
677 | if (ret_val) | |
678 | return ret_val; | |
679 | } | |
680 | ||
681 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
682 | if (ret_val) | |
683 | return ret_val; | |
684 | ||
ad68076e BA |
685 | /* |
686 | * Resetting the phy means we need to verify the TX_CLK corresponds | |
bc7f75fa AK |
687 | * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. |
688 | */ | |
689 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; | |
690 | if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) | |
691 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; | |
692 | else | |
693 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; | |
694 | ||
ad68076e BA |
695 | /* |
696 | * In addition, we must re-enable CRS on Tx for both half and full | |
bc7f75fa AK |
697 | * duplex. |
698 | */ | |
699 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
700 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
701 | ||
702 | return ret_val; | |
703 | } | |
704 | ||
705 | /** | |
706 | * e1000_get_cable_length_80003es2lan - Set approximate cable length | |
707 | * @hw: pointer to the HW structure | |
708 | * | |
709 | * Find the approximate cable length as measured by the GG82563 PHY. | |
710 | * This is a function pointer entry point called by the phy module. | |
711 | **/ | |
712 | static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) | |
713 | { | |
714 | struct e1000_phy_info *phy = &hw->phy; | |
715 | s32 ret_val; | |
716 | u16 phy_data; | |
717 | u16 index; | |
718 | ||
719 | ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); | |
720 | if (ret_val) | |
721 | return ret_val; | |
722 | ||
723 | index = phy_data & GG82563_DSPD_CABLE_LENGTH; | |
724 | phy->min_cable_length = e1000_gg82563_cable_length_table[index]; | |
725 | phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; | |
726 | ||
727 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
732 | /** | |
733 | * e1000_get_link_up_info_80003es2lan - Report speed and duplex | |
734 | * @hw: pointer to the HW structure | |
735 | * @speed: pointer to speed buffer | |
736 | * @duplex: pointer to duplex buffer | |
737 | * | |
738 | * Retrieve the current speed and duplex configuration. | |
739 | * This is a function pointer entry point called by the api module. | |
740 | **/ | |
741 | static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, | |
742 | u16 *duplex) | |
743 | { | |
744 | s32 ret_val; | |
745 | ||
318a94d6 | 746 | if (hw->phy.media_type == e1000_media_type_copper) { |
bc7f75fa AK |
747 | ret_val = e1000e_get_speed_and_duplex_copper(hw, |
748 | speed, | |
749 | duplex); | |
75eb0fad | 750 | hw->phy.ops.cfg_on_link_up(hw); |
bc7f75fa AK |
751 | } else { |
752 | ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, | |
753 | speed, | |
754 | duplex); | |
755 | } | |
756 | ||
757 | return ret_val; | |
758 | } | |
759 | ||
760 | /** | |
761 | * e1000_reset_hw_80003es2lan - Reset the ESB2 controller | |
762 | * @hw: pointer to the HW structure | |
763 | * | |
764 | * Perform a global reset to the ESB2 controller. | |
765 | * This is a function pointer entry point called by the api module. | |
766 | **/ | |
767 | static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) | |
768 | { | |
769 | u32 ctrl; | |
770 | u32 icr; | |
771 | s32 ret_val; | |
772 | ||
ad68076e BA |
773 | /* |
774 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
775 | * on the last TLP read/write transaction when MAC is reset. |
776 | */ | |
777 | ret_val = e1000e_disable_pcie_master(hw); | |
778 | if (ret_val) | |
779 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
780 | ||
781 | hw_dbg(hw, "Masking off all interrupts\n"); | |
782 | ew32(IMC, 0xffffffff); | |
783 | ||
784 | ew32(RCTL, 0); | |
785 | ew32(TCTL, E1000_TCTL_PSP); | |
786 | e1e_flush(); | |
787 | ||
788 | msleep(10); | |
789 | ||
790 | ctrl = er32(CTRL); | |
791 | ||
75eb0fad | 792 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
bc7f75fa AK |
793 | hw_dbg(hw, "Issuing a global reset to MAC\n"); |
794 | ew32(CTRL, ctrl | E1000_CTRL_RST); | |
75eb0fad | 795 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
796 | |
797 | ret_val = e1000e_get_auto_rd_done(hw); | |
798 | if (ret_val) | |
799 | /* We don't want to continue accessing MAC registers. */ | |
800 | return ret_val; | |
801 | ||
802 | /* Clear any pending interrupt events. */ | |
803 | ew32(IMC, 0xffffffff); | |
804 | icr = er32(ICR); | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | /** | |
810 | * e1000_init_hw_80003es2lan - Initialize the ESB2 controller | |
811 | * @hw: pointer to the HW structure | |
812 | * | |
813 | * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. | |
814 | * This is a function pointer entry point called by the api module. | |
815 | **/ | |
816 | static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) | |
817 | { | |
818 | struct e1000_mac_info *mac = &hw->mac; | |
819 | u32 reg_data; | |
820 | s32 ret_val; | |
821 | u16 i; | |
822 | ||
823 | e1000_initialize_hw_bits_80003es2lan(hw); | |
824 | ||
825 | /* Initialize identification LED */ | |
826 | ret_val = e1000e_id_led_init(hw); | |
827 | if (ret_val) { | |
828 | hw_dbg(hw, "Error initializing identification LED\n"); | |
829 | return ret_val; | |
830 | } | |
831 | ||
832 | /* Disabling VLAN filtering */ | |
833 | hw_dbg(hw, "Initializing the IEEE VLAN\n"); | |
834 | e1000e_clear_vfta(hw); | |
835 | ||
836 | /* Setup the receive address. */ | |
837 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
838 | ||
839 | /* Zero out the Multicast HASH table */ | |
840 | hw_dbg(hw, "Zeroing the MTA\n"); | |
841 | for (i = 0; i < mac->mta_reg_count; i++) | |
842 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
843 | ||
844 | /* Setup link and flow control */ | |
845 | ret_val = e1000e_setup_link(hw); | |
846 | ||
847 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 848 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
849 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
850 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 851 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
852 | |
853 | /* ...for both queues. */ | |
e9ec2c0f | 854 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
855 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
856 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 857 | ew32(TXDCTL(1), reg_data); |
bc7f75fa AK |
858 | |
859 | /* Enable retransmit on late collisions */ | |
860 | reg_data = er32(TCTL); | |
861 | reg_data |= E1000_TCTL_RTLC; | |
862 | ew32(TCTL, reg_data); | |
863 | ||
864 | /* Configure Gigabit Carry Extend Padding */ | |
865 | reg_data = er32(TCTL_EXT); | |
866 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | |
867 | reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; | |
868 | ew32(TCTL_EXT, reg_data); | |
869 | ||
870 | /* Configure Transmit Inter-Packet Gap */ | |
871 | reg_data = er32(TIPG); | |
872 | reg_data &= ~E1000_TIPG_IPGT_MASK; | |
873 | reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
874 | ew32(TIPG, reg_data); | |
875 | ||
876 | reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); | |
877 | reg_data &= ~0x00100000; | |
878 | E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); | |
879 | ||
ad68076e BA |
880 | /* |
881 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
882 | * important that we do this after we have tried to establish link |
883 | * because the symbol error count will increment wildly if there | |
884 | * is no link. | |
885 | */ | |
886 | e1000_clear_hw_cntrs_80003es2lan(hw); | |
887 | ||
888 | return ret_val; | |
889 | } | |
890 | ||
891 | /** | |
892 | * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 | |
893 | * @hw: pointer to the HW structure | |
894 | * | |
895 | * Initializes required hardware-dependent bits needed for normal operation. | |
896 | **/ | |
897 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) | |
898 | { | |
899 | u32 reg; | |
900 | ||
901 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 902 | reg = er32(TXDCTL(0)); |
bc7f75fa | 903 | reg |= (1 << 22); |
e9ec2c0f | 904 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
905 | |
906 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 907 | reg = er32(TXDCTL(1)); |
bc7f75fa | 908 | reg |= (1 << 22); |
e9ec2c0f | 909 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
910 | |
911 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 912 | reg = er32(TARC(0)); |
bc7f75fa | 913 | reg &= ~(0xF << 27); /* 30:27 */ |
318a94d6 | 914 | if (hw->phy.media_type != e1000_media_type_copper) |
bc7f75fa | 915 | reg &= ~(1 << 20); |
e9ec2c0f | 916 | ew32(TARC(0), reg); |
bc7f75fa AK |
917 | |
918 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 919 | reg = er32(TARC(1)); |
bc7f75fa AK |
920 | if (er32(TCTL) & E1000_TCTL_MULR) |
921 | reg &= ~(1 << 28); | |
922 | else | |
923 | reg |= (1 << 28); | |
e9ec2c0f | 924 | ew32(TARC(1), reg); |
bc7f75fa AK |
925 | } |
926 | ||
927 | /** | |
928 | * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link | |
929 | * @hw: pointer to the HW structure | |
930 | * | |
931 | * Setup some GG82563 PHY registers for obtaining link | |
932 | **/ | |
933 | static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) | |
934 | { | |
935 | struct e1000_phy_info *phy = &hw->phy; | |
936 | s32 ret_val; | |
937 | u32 ctrl_ext; | |
75eb0fad | 938 | u16 data; |
bc7f75fa | 939 | |
2d9498f3 | 940 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); |
bc7f75fa AK |
941 | if (ret_val) |
942 | return ret_val; | |
943 | ||
944 | data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
945 | /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ | |
946 | data |= GG82563_MSCR_TX_CLK_1000MBPS_25; | |
947 | ||
2d9498f3 | 948 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); |
bc7f75fa AK |
949 | if (ret_val) |
950 | return ret_val; | |
951 | ||
ad68076e BA |
952 | /* |
953 | * Options: | |
bc7f75fa AK |
954 | * MDI/MDI-X = 0 (default) |
955 | * 0 - Auto for all speeds | |
956 | * 1 - MDI mode | |
957 | * 2 - MDI-X mode | |
958 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
959 | */ | |
960 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); | |
961 | if (ret_val) | |
962 | return ret_val; | |
963 | ||
964 | data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
965 | ||
966 | switch (phy->mdix) { | |
967 | case 1: | |
968 | data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
969 | break; | |
970 | case 2: | |
971 | data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
972 | break; | |
973 | case 0: | |
974 | default: | |
975 | data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
976 | break; | |
977 | } | |
978 | ||
ad68076e BA |
979 | /* |
980 | * Options: | |
bc7f75fa AK |
981 | * disable_polarity_correction = 0 (default) |
982 | * Automatic Correction for Reversed Cable Polarity | |
983 | * 0 - Disabled | |
984 | * 1 - Enabled | |
985 | */ | |
986 | data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
987 | if (phy->disable_polarity_correction) | |
988 | data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
989 | ||
990 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); | |
991 | if (ret_val) | |
992 | return ret_val; | |
993 | ||
994 | /* SW Reset the PHY so all changes take effect */ | |
995 | ret_val = e1000e_commit_phy(hw); | |
996 | if (ret_val) { | |
997 | hw_dbg(hw, "Error Resetting the PHY\n"); | |
998 | return ret_val; | |
999 | } | |
1000 | ||
ad68076e | 1001 | /* Bypass Rx and Tx FIFO's */ |
75eb0fad BA |
1002 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1003 | E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, | |
ad68076e | 1004 | E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | |
bc7f75fa AK |
1005 | E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); |
1006 | if (ret_val) | |
1007 | return ret_val; | |
1008 | ||
75eb0fad | 1009 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, |
2d9498f3 DG |
1010 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, |
1011 | &data); | |
1012 | if (ret_val) | |
1013 | return ret_val; | |
1014 | data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; | |
75eb0fad | 1015 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
2d9498f3 DG |
1016 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, |
1017 | data); | |
1018 | if (ret_val) | |
1019 | return ret_val; | |
1020 | ||
bc7f75fa AK |
1021 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); |
1022 | if (ret_val) | |
1023 | return ret_val; | |
1024 | ||
1025 | data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
1026 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); | |
1027 | if (ret_val) | |
1028 | return ret_val; | |
1029 | ||
1030 | ctrl_ext = er32(CTRL_EXT); | |
1031 | ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | |
1032 | ew32(CTRL_EXT, ctrl_ext); | |
1033 | ||
1034 | ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); | |
1035 | if (ret_val) | |
1036 | return ret_val; | |
1037 | ||
ad68076e BA |
1038 | /* |
1039 | * Do not init these registers when the HW is in IAMT mode, since the | |
bc7f75fa AK |
1040 | * firmware will have already initialized them. We only initialize |
1041 | * them if the HW is not in IAMT mode. | |
1042 | */ | |
1043 | if (!e1000e_check_mng_mode(hw)) { | |
1044 | /* Enable Electrical Idle on the PHY */ | |
1045 | data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
1046 | ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); | |
1047 | if (ret_val) | |
1048 | return ret_val; | |
1049 | ||
75eb0fad BA |
1050 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); |
1051 | if (ret_val) | |
1052 | return ret_val; | |
bc7f75fa AK |
1053 | |
1054 | data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1055 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); | |
1056 | if (ret_val) | |
1057 | return ret_val; | |
1058 | } | |
1059 | ||
ad68076e BA |
1060 | /* |
1061 | * Workaround: Disable padding in Kumeran interface in the MAC | |
bc7f75fa AK |
1062 | * and in the PHY to avoid CRC errors. |
1063 | */ | |
1064 | ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); | |
1065 | if (ret_val) | |
1066 | return ret_val; | |
1067 | ||
1068 | data |= GG82563_ICR_DIS_PADDING; | |
1069 | ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); | |
1070 | if (ret_val) | |
1071 | return ret_val; | |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | /** | |
1077 | * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 | |
1078 | * @hw: pointer to the HW structure | |
1079 | * | |
1080 | * Essentially a wrapper for setting up all things "copper" related. | |
1081 | * This is a function pointer entry point called by the mac module. | |
1082 | **/ | |
1083 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) | |
1084 | { | |
1085 | u32 ctrl; | |
1086 | s32 ret_val; | |
1087 | u16 reg_data; | |
1088 | ||
1089 | ctrl = er32(CTRL); | |
1090 | ctrl |= E1000_CTRL_SLU; | |
1091 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1092 | ew32(CTRL, ctrl); | |
1093 | ||
ad68076e BA |
1094 | /* |
1095 | * Set the mac to wait the maximum time between each | |
bc7f75fa | 1096 | * iteration and increase the max iterations when |
ad68076e BA |
1097 | * polling the phy; this fixes erroneous timeouts at 10Mbps. |
1098 | */ | |
75eb0fad BA |
1099 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), |
1100 | 0xFFFF); | |
bc7f75fa AK |
1101 | if (ret_val) |
1102 | return ret_val; | |
75eb0fad BA |
1103 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
1104 | ®_data); | |
bc7f75fa AK |
1105 | if (ret_val) |
1106 | return ret_val; | |
1107 | reg_data |= 0x3F; | |
75eb0fad BA |
1108 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
1109 | reg_data); | |
bc7f75fa AK |
1110 | if (ret_val) |
1111 | return ret_val; | |
75eb0fad | 1112 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, |
bc7f75fa AK |
1113 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, |
1114 | ®_data); | |
1115 | if (ret_val) | |
1116 | return ret_val; | |
1117 | reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; | |
75eb0fad BA |
1118 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1119 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, | |
ad68076e | 1120 | reg_data); |
bc7f75fa AK |
1121 | if (ret_val) |
1122 | return ret_val; | |
1123 | ||
1124 | ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); | |
1125 | if (ret_val) | |
1126 | return ret_val; | |
1127 | ||
1128 | ret_val = e1000e_setup_copper_link(hw); | |
1129 | ||
1130 | return 0; | |
1131 | } | |
1132 | ||
75eb0fad BA |
1133 | /** |
1134 | * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up | |
1135 | * @hw: pointer to the HW structure | |
1136 | * @duplex: current duplex setting | |
1137 | * | |
1138 | * Configure the KMRN interface by applying last minute quirks for | |
1139 | * 10/100 operation. | |
1140 | **/ | |
1141 | static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) | |
1142 | { | |
1143 | s32 ret_val = 0; | |
1144 | u16 speed; | |
1145 | u16 duplex; | |
1146 | ||
1147 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1148 | ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed, | |
1149 | &duplex); | |
1150 | if (ret_val) | |
1151 | return ret_val; | |
1152 | ||
1153 | if (speed == SPEED_1000) | |
1154 | ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); | |
1155 | else | |
1156 | ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); | |
1157 | } | |
1158 | ||
1159 | return ret_val; | |
1160 | } | |
1161 | ||
bc7f75fa AK |
1162 | /** |
1163 | * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation | |
1164 | * @hw: pointer to the HW structure | |
1165 | * @duplex: current duplex setting | |
1166 | * | |
1167 | * Configure the KMRN interface by applying last minute quirks for | |
1168 | * 10/100 operation. | |
1169 | **/ | |
1170 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) | |
1171 | { | |
1172 | s32 ret_val; | |
1173 | u32 tipg; | |
2d9498f3 DG |
1174 | u32 i = 0; |
1175 | u16 reg_data, reg_data2; | |
bc7f75fa AK |
1176 | |
1177 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
75eb0fad BA |
1178 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1179 | E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | |
1180 | reg_data); | |
bc7f75fa AK |
1181 | if (ret_val) |
1182 | return ret_val; | |
1183 | ||
1184 | /* Configure Transmit Inter-Packet Gap */ | |
1185 | tipg = er32(TIPG); | |
1186 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1187 | tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; | |
1188 | ew32(TIPG, tipg); | |
1189 | ||
2d9498f3 DG |
1190 | do { |
1191 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1192 | if (ret_val) | |
1193 | return ret_val; | |
1194 | ||
1195 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1196 | if (ret_val) | |
1197 | return ret_val; | |
1198 | i++; | |
1199 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1200 | |
1201 | if (duplex == HALF_DUPLEX) | |
1202 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
1203 | else | |
1204 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1205 | ||
1206 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | /** | |
1212 | * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation | |
1213 | * @hw: pointer to the HW structure | |
1214 | * | |
1215 | * Configure the KMRN interface by applying last minute quirks for | |
1216 | * gigabit operation. | |
1217 | **/ | |
1218 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) | |
1219 | { | |
1220 | s32 ret_val; | |
2d9498f3 | 1221 | u16 reg_data, reg_data2; |
bc7f75fa | 1222 | u32 tipg; |
2d9498f3 | 1223 | u32 i = 0; |
bc7f75fa AK |
1224 | |
1225 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; | |
75eb0fad BA |
1226 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1227 | E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | |
1228 | reg_data); | |
bc7f75fa AK |
1229 | if (ret_val) |
1230 | return ret_val; | |
1231 | ||
1232 | /* Configure Transmit Inter-Packet Gap */ | |
1233 | tipg = er32(TIPG); | |
1234 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1235 | tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
1236 | ew32(TIPG, tipg); | |
1237 | ||
2d9498f3 DG |
1238 | do { |
1239 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1240 | if (ret_val) | |
1241 | return ret_val; | |
1242 | ||
1243 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1244 | if (ret_val) | |
1245 | return ret_val; | |
1246 | i++; | |
1247 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1248 | |
1249 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1250 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
1251 | ||
1252 | return ret_val; | |
1253 | } | |
1254 | ||
75eb0fad BA |
1255 | /** |
1256 | * e1000_read_kmrn_reg_80003es2lan - Read kumeran register | |
1257 | * @hw: pointer to the HW structure | |
1258 | * @offset: register offset to be read | |
1259 | * @data: pointer to the read data | |
1260 | * | |
1261 | * Acquire semaphore, then read the PHY register at offset | |
1262 | * using the kumeran interface. The information retrieved is stored in data. | |
1263 | * Release the semaphore before exiting. | |
1264 | **/ | |
fa4c16da HE |
1265 | static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
1266 | u16 *data) | |
75eb0fad BA |
1267 | { |
1268 | u32 kmrnctrlsta; | |
1269 | s32 ret_val = 0; | |
1270 | ||
1271 | ret_val = e1000_acquire_mac_csr_80003es2lan(hw); | |
1272 | if (ret_val) | |
1273 | return ret_val; | |
1274 | ||
1275 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
1276 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; | |
1277 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
1278 | ||
1279 | udelay(2); | |
1280 | ||
1281 | kmrnctrlsta = er32(KMRNCTRLSTA); | |
1282 | *data = (u16)kmrnctrlsta; | |
1283 | ||
1284 | e1000_release_mac_csr_80003es2lan(hw); | |
1285 | ||
1286 | return ret_val; | |
1287 | } | |
1288 | ||
1289 | /** | |
1290 | * e1000_write_kmrn_reg_80003es2lan - Write kumeran register | |
1291 | * @hw: pointer to the HW structure | |
1292 | * @offset: register offset to write to | |
1293 | * @data: data to write at register offset | |
1294 | * | |
1295 | * Acquire semaphore, then write the data to PHY register | |
1296 | * at the offset using the kumeran interface. Release semaphore | |
1297 | * before exiting. | |
1298 | **/ | |
fa4c16da HE |
1299 | static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
1300 | u16 data) | |
75eb0fad BA |
1301 | { |
1302 | u32 kmrnctrlsta; | |
1303 | s32 ret_val = 0; | |
1304 | ||
1305 | ret_val = e1000_acquire_mac_csr_80003es2lan(hw); | |
1306 | if (ret_val) | |
1307 | return ret_val; | |
1308 | ||
1309 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
1310 | E1000_KMRNCTRLSTA_OFFSET) | data; | |
1311 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
1312 | ||
1313 | udelay(2); | |
1314 | ||
1315 | e1000_release_mac_csr_80003es2lan(hw); | |
1316 | ||
1317 | return ret_val; | |
1318 | } | |
1319 | ||
bc7f75fa AK |
1320 | /** |
1321 | * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters | |
1322 | * @hw: pointer to the HW structure | |
1323 | * | |
1324 | * Clears the hardware counters by reading the counter registers. | |
1325 | **/ | |
1326 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) | |
1327 | { | |
1328 | u32 temp; | |
1329 | ||
1330 | e1000e_clear_hw_cntrs_base(hw); | |
1331 | ||
1332 | temp = er32(PRC64); | |
1333 | temp = er32(PRC127); | |
1334 | temp = er32(PRC255); | |
1335 | temp = er32(PRC511); | |
1336 | temp = er32(PRC1023); | |
1337 | temp = er32(PRC1522); | |
1338 | temp = er32(PTC64); | |
1339 | temp = er32(PTC127); | |
1340 | temp = er32(PTC255); | |
1341 | temp = er32(PTC511); | |
1342 | temp = er32(PTC1023); | |
1343 | temp = er32(PTC1522); | |
1344 | ||
1345 | temp = er32(ALGNERRC); | |
1346 | temp = er32(RXERRC); | |
1347 | temp = er32(TNCRS); | |
1348 | temp = er32(CEXTERR); | |
1349 | temp = er32(TSCTC); | |
1350 | temp = er32(TSCTFC); | |
1351 | ||
1352 | temp = er32(MGTPRC); | |
1353 | temp = er32(MGTPDC); | |
1354 | temp = er32(MGTPTC); | |
1355 | ||
1356 | temp = er32(IAC); | |
1357 | temp = er32(ICRXOC); | |
1358 | ||
1359 | temp = er32(ICRXPTC); | |
1360 | temp = er32(ICRXATC); | |
1361 | temp = er32(ICTXPTC); | |
1362 | temp = er32(ICTXATC); | |
1363 | temp = er32(ICTXQEC); | |
1364 | temp = er32(ICTXQMTC); | |
1365 | temp = er32(ICRXDMTC); | |
1366 | } | |
1367 | ||
1368 | static struct e1000_mac_operations es2_mac_ops = { | |
4662e82b | 1369 | .check_mng_mode = e1000e_check_mng_mode_generic, |
bc7f75fa AK |
1370 | /* check_for_link dependent on media type */ |
1371 | .cleanup_led = e1000e_cleanup_led_generic, | |
1372 | .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, | |
1373 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1374 | .get_link_up_info = e1000_get_link_up_info_80003es2lan, | |
1375 | .led_on = e1000e_led_on_generic, | |
1376 | .led_off = e1000e_led_off_generic, | |
e2de3eb6 | 1377 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
bc7f75fa AK |
1378 | .reset_hw = e1000_reset_hw_80003es2lan, |
1379 | .init_hw = e1000_init_hw_80003es2lan, | |
1380 | .setup_link = e1000e_setup_link, | |
1381 | /* setup_physical_interface dependent on media type */ | |
1382 | }; | |
1383 | ||
1384 | static struct e1000_phy_operations es2_phy_ops = { | |
1385 | .acquire_phy = e1000_acquire_phy_80003es2lan, | |
1386 | .check_reset_block = e1000e_check_reset_block_generic, | |
1387 | .commit_phy = e1000e_phy_sw_reset, | |
1388 | .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, | |
1389 | .get_cfg_done = e1000_get_cfg_done_80003es2lan, | |
1390 | .get_cable_length = e1000_get_cable_length_80003es2lan, | |
1391 | .get_phy_info = e1000e_get_phy_info_m88, | |
1392 | .read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan, | |
1393 | .release_phy = e1000_release_phy_80003es2lan, | |
1394 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1395 | .set_d0_lplu_state = NULL, | |
1396 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1397 | .write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan, | |
75eb0fad | 1398 | .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan, |
bc7f75fa AK |
1399 | }; |
1400 | ||
1401 | static struct e1000_nvm_operations es2_nvm_ops = { | |
1402 | .acquire_nvm = e1000_acquire_nvm_80003es2lan, | |
1403 | .read_nvm = e1000e_read_nvm_eerd, | |
1404 | .release_nvm = e1000_release_nvm_80003es2lan, | |
1405 | .update_nvm = e1000e_update_nvm_checksum_generic, | |
1406 | .valid_led_default = e1000e_valid_led_default, | |
1407 | .validate_nvm = e1000e_validate_nvm_checksum_generic, | |
1408 | .write_nvm = e1000_write_nvm_80003es2lan, | |
1409 | }; | |
1410 | ||
1411 | struct e1000_info e1000_es2_info = { | |
1412 | .mac = e1000_80003es2lan, | |
1413 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1414 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1415 | | FLAG_HAS_WOL |
1416 | | FLAG_APME_IN_CTRL3 | |
1417 | | FLAG_RX_CSUM_ENABLED | |
1418 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1419 | | FLAG_RX_NEEDS_RESTART /* errata */ |
1420 | | FLAG_TARC_SET_BIT_ZERO /* errata */ | |
1421 | | FLAG_APME_CHECK_PORT_B | |
1422 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ | |
1423 | | FLAG_TIPG_MEDIUM_FOR_80003ESLAN, | |
1424 | .pba = 38, | |
2adc55c9 | 1425 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1426 | .get_variants = e1000_get_variants_80003es2lan, |
bc7f75fa AK |
1427 | .mac_ops = &es2_mac_ops, |
1428 | .phy_ops = &es2_phy_ops, | |
1429 | .nvm_ops = &es2_nvm_ops, | |
1430 | }; | |
1431 |