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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
c7e54b1b | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* Linux PRO/1000 Ethernet Driver main header file */ | |
30 | ||
31 | #ifndef _E1000_H_ | |
32 | #define _E1000_H_ | |
33 | ||
34 | #include <linux/types.h> | |
35 | #include <linux/timer.h> | |
36 | #include <linux/workqueue.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/netdevice.h> | |
d8014dbc | 39 | #include <linux/pci.h> |
bc7f75fa AK |
40 | |
41 | #include "hw.h" | |
42 | ||
43 | struct e1000_info; | |
44 | ||
44defeb3 JK |
45 | #define e_printk(level, adapter, format, arg...) \ |
46 | printk(level "%s: %s: " format, pci_name(adapter->pdev), \ | |
47 | adapter->netdev->name, ## arg) | |
bc7f75fa AK |
48 | |
49 | #ifdef DEBUG | |
44defeb3 | 50 | #define e_dbg(format, arg...) \ |
3bb99fe2 | 51 | e_printk(KERN_DEBUG , hw->adapter, format, ## arg) |
bc7f75fa | 52 | #else |
3bb99fe2 | 53 | #define e_dbg(format, arg...) do { (void)(hw); } while (0) |
bc7f75fa AK |
54 | #endif |
55 | ||
44defeb3 JK |
56 | #define e_err(format, arg...) \ |
57 | e_printk(KERN_ERR, adapter, format, ## arg) | |
58 | #define e_info(format, arg...) \ | |
59 | e_printk(KERN_INFO, adapter, format, ## arg) | |
60 | #define e_warn(format, arg...) \ | |
61 | e_printk(KERN_WARNING, adapter, format, ## arg) | |
62 | #define e_notice(format, arg...) \ | |
63 | e_printk(KERN_NOTICE, adapter, format, ## arg) | |
bc7f75fa AK |
64 | |
65 | ||
98a1708d | 66 | /* Interrupt modes, as used by the IntMode parameter */ |
4662e82b BA |
67 | #define E1000E_INT_MODE_LEGACY 0 |
68 | #define E1000E_INT_MODE_MSI 1 | |
69 | #define E1000E_INT_MODE_MSIX 2 | |
70 | ||
ad68076e | 71 | /* Tx/Rx descriptor defines */ |
bc7f75fa AK |
72 | #define E1000_DEFAULT_TXD 256 |
73 | #define E1000_MAX_TXD 4096 | |
7b1be198 | 74 | #define E1000_MIN_TXD 64 |
bc7f75fa AK |
75 | |
76 | #define E1000_DEFAULT_RXD 256 | |
77 | #define E1000_MAX_RXD 4096 | |
7b1be198 | 78 | #define E1000_MIN_RXD 64 |
bc7f75fa | 79 | |
de5b3077 AK |
80 | #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */ |
81 | #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */ | |
82 | ||
bc7f75fa AK |
83 | /* Early Receive defines */ |
84 | #define E1000_ERT_2048 0x100 | |
85 | ||
86 | #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ | |
87 | ||
88 | /* How many Tx Descriptors do we need to call netif_wake_queue ? */ | |
89 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | |
90 | #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
91 | ||
92 | #define AUTO_ALL_MODES 0 | |
93 | #define E1000_EEPROM_APME 0x0400 | |
94 | ||
95 | #define E1000_MNG_VLAN_NONE (-1) | |
96 | ||
97 | /* Number of packet split data buffers (not including the header buffer) */ | |
98 | #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) | |
99 | ||
2adc55c9 BA |
100 | #define DEFAULT_JUMBO 9234 |
101 | ||
a4f58f54 BA |
102 | /* BM/HV Specific Registers */ |
103 | #define BM_PORT_CTRL_PAGE 769 | |
104 | ||
105 | #define PHY_UPPER_SHIFT 21 | |
106 | #define BM_PHY_REG(page, reg) \ | |
107 | (((reg) & MAX_PHY_REG_ADDRESS) |\ | |
108 | (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ | |
109 | (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) | |
110 | ||
111 | /* PHY Wakeup Registers and defines */ | |
112 | #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) | |
113 | #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) | |
114 | #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) | |
115 | #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) | |
116 | #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) | |
117 | #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) | |
118 | #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) | |
119 | #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) | |
120 | #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) | |
121 | ||
122 | #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ | |
123 | #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ | |
124 | #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ | |
125 | #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ | |
126 | #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ | |
127 | #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ | |
128 | #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ | |
129 | ||
130 | #define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */ | |
131 | #define HV_SCC_LOWER PHY_REG(778, 17) | |
132 | #define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */ | |
133 | #define HV_ECOL_LOWER PHY_REG(778, 19) | |
134 | #define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */ | |
135 | #define HV_MCC_LOWER PHY_REG(778, 21) | |
136 | #define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */ | |
137 | #define HV_LATECOL_LOWER PHY_REG(778, 24) | |
138 | #define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ | |
139 | #define HV_COLC_LOWER PHY_REG(778, 26) | |
140 | #define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ | |
141 | #define HV_DC_LOWER PHY_REG(778, 28) | |
142 | #define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ | |
143 | #define HV_TNCRS_LOWER PHY_REG(778, 30) | |
144 | ||
38eb394e BA |
145 | #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ |
146 | ||
1d5846b9 BA |
147 | /* BM PHY Copper Specific Status */ |
148 | #define BM_CS_STATUS 17 | |
149 | #define BM_CS_STATUS_LINK_UP 0x0400 | |
150 | #define BM_CS_STATUS_RESOLVED 0x0800 | |
151 | #define BM_CS_STATUS_SPEED_MASK 0xC000 | |
152 | #define BM_CS_STATUS_SPEED_1000 0x8000 | |
153 | ||
154 | /* 82577 Mobile Phy Status Register */ | |
155 | #define HV_M_STATUS 26 | |
156 | #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 | |
157 | #define HV_M_STATUS_SPEED_MASK 0x0300 | |
158 | #define HV_M_STATUS_SPEED_1000 0x0200 | |
159 | #define HV_M_STATUS_LINK_UP 0x0040 | |
160 | ||
bc7f75fa AK |
161 | enum e1000_boards { |
162 | board_82571, | |
163 | board_82572, | |
164 | board_82573, | |
4662e82b | 165 | board_82574, |
8c81c9c3 | 166 | board_82583, |
bc7f75fa AK |
167 | board_80003es2lan, |
168 | board_ich8lan, | |
169 | board_ich9lan, | |
f4187b56 | 170 | board_ich10lan, |
a4f58f54 | 171 | board_pchlan, |
bc7f75fa AK |
172 | }; |
173 | ||
174 | struct e1000_queue_stats { | |
175 | u64 packets; | |
176 | u64 bytes; | |
177 | }; | |
178 | ||
179 | struct e1000_ps_page { | |
180 | struct page *page; | |
181 | u64 dma; /* must be u64 - written to hw */ | |
182 | }; | |
183 | ||
184 | /* | |
185 | * wrappers around a pointer to a socket buffer, | |
186 | * so a DMA handle can be stored along with the buffer | |
187 | */ | |
188 | struct e1000_buffer { | |
189 | dma_addr_t dma; | |
190 | struct sk_buff *skb; | |
191 | union { | |
ad68076e | 192 | /* Tx */ |
bc7f75fa AK |
193 | struct { |
194 | unsigned long time_stamp; | |
195 | u16 length; | |
196 | u16 next_to_watch; | |
197 | }; | |
ad68076e | 198 | /* Rx */ |
47f44e40 AK |
199 | /* arrays of page information for packet split */ |
200 | struct e1000_ps_page *ps_pages; | |
bc7f75fa | 201 | }; |
97ac8cae | 202 | struct page *page; |
bc7f75fa AK |
203 | }; |
204 | ||
205 | struct e1000_ring { | |
206 | void *desc; /* pointer to ring memory */ | |
207 | dma_addr_t dma; /* phys address of ring */ | |
208 | unsigned int size; /* length of ring in bytes */ | |
209 | unsigned int count; /* number of desc. in ring */ | |
210 | ||
211 | u16 next_to_use; | |
212 | u16 next_to_clean; | |
213 | ||
214 | u16 head; | |
215 | u16 tail; | |
216 | ||
217 | /* array of buffer information structs */ | |
218 | struct e1000_buffer *buffer_info; | |
219 | ||
4662e82b BA |
220 | char name[IFNAMSIZ + 5]; |
221 | u32 ims_val; | |
222 | u32 itr_val; | |
223 | u16 itr_register; | |
224 | int set_itr; | |
225 | ||
bc7f75fa AK |
226 | struct sk_buff *rx_skb_top; |
227 | ||
228 | struct e1000_queue_stats stats; | |
229 | }; | |
230 | ||
7c25769f BA |
231 | /* PHY register snapshot values */ |
232 | struct e1000_phy_regs { | |
233 | u16 bmcr; /* basic mode control register */ | |
234 | u16 bmsr; /* basic mode status register */ | |
235 | u16 advertise; /* auto-negotiation advertisement */ | |
236 | u16 lpa; /* link partner ability register */ | |
237 | u16 expansion; /* auto-negotiation expansion reg */ | |
238 | u16 ctrl1000; /* 1000BASE-T control register */ | |
239 | u16 stat1000; /* 1000BASE-T status register */ | |
240 | u16 estatus; /* extended status register */ | |
241 | }; | |
242 | ||
bc7f75fa AK |
243 | /* board specific private data structure */ |
244 | struct e1000_adapter { | |
245 | struct timer_list watchdog_timer; | |
246 | struct timer_list phy_info_timer; | |
247 | struct timer_list blink_timer; | |
248 | ||
249 | struct work_struct reset_task; | |
250 | struct work_struct watchdog_task; | |
251 | ||
252 | const struct e1000_info *ei; | |
253 | ||
254 | struct vlan_group *vlgrp; | |
255 | u32 bd_number; | |
256 | u32 rx_buffer_len; | |
257 | u16 mng_vlan_id; | |
258 | u16 link_speed; | |
259 | u16 link_duplex; | |
84527590 | 260 | u16 eeprom_vers; |
bc7f75fa | 261 | |
bc7f75fa AK |
262 | /* track device up/down/testing state */ |
263 | unsigned long state; | |
264 | ||
265 | /* Interrupt Throttle Rate */ | |
266 | u32 itr; | |
267 | u32 itr_setting; | |
268 | u16 tx_itr; | |
269 | u16 rx_itr; | |
270 | ||
271 | /* | |
ad68076e | 272 | * Tx |
bc7f75fa AK |
273 | */ |
274 | struct e1000_ring *tx_ring /* One per active queue */ | |
275 | ____cacheline_aligned_in_smp; | |
276 | ||
277 | struct napi_struct napi; | |
278 | ||
279 | unsigned long tx_queue_len; | |
280 | unsigned int restart_queue; | |
281 | u32 txd_cmd; | |
282 | ||
283 | bool detect_tx_hung; | |
284 | u8 tx_timeout_factor; | |
285 | ||
286 | u32 tx_int_delay; | |
287 | u32 tx_abs_int_delay; | |
288 | ||
289 | unsigned int total_tx_bytes; | |
290 | unsigned int total_tx_packets; | |
291 | unsigned int total_rx_bytes; | |
292 | unsigned int total_rx_packets; | |
293 | ||
ad68076e | 294 | /* Tx stats */ |
bc7f75fa AK |
295 | u64 tpt_old; |
296 | u64 colc_old; | |
7c25769f BA |
297 | u32 gotc; |
298 | u64 gotc_old; | |
bc7f75fa AK |
299 | u32 tx_timeout_count; |
300 | u32 tx_fifo_head; | |
301 | u32 tx_head_addr; | |
302 | u32 tx_fifo_size; | |
303 | u32 tx_dma_failed; | |
304 | ||
305 | /* | |
ad68076e | 306 | * Rx |
bc7f75fa AK |
307 | */ |
308 | bool (*clean_rx) (struct e1000_adapter *adapter, | |
309 | int *work_done, int work_to_do) | |
310 | ____cacheline_aligned_in_smp; | |
311 | void (*alloc_rx_buf) (struct e1000_adapter *adapter, | |
312 | int cleaned_count); | |
313 | struct e1000_ring *rx_ring; | |
314 | ||
315 | u32 rx_int_delay; | |
316 | u32 rx_abs_int_delay; | |
317 | ||
ad68076e | 318 | /* Rx stats */ |
bc7f75fa AK |
319 | u64 hw_csum_err; |
320 | u64 hw_csum_good; | |
321 | u64 rx_hdr_split; | |
7c25769f BA |
322 | u32 gorc; |
323 | u64 gorc_old; | |
bc7f75fa AK |
324 | u32 alloc_rx_buff_failed; |
325 | u32 rx_dma_failed; | |
326 | ||
327 | unsigned int rx_ps_pages; | |
328 | u16 rx_ps_bsize0; | |
318a94d6 JK |
329 | u32 max_frame_size; |
330 | u32 min_frame_size; | |
bc7f75fa AK |
331 | |
332 | /* OS defined structs */ | |
333 | struct net_device *netdev; | |
334 | struct pci_dev *pdev; | |
bc7f75fa AK |
335 | |
336 | /* structs defined in e1000_hw.h */ | |
337 | struct e1000_hw hw; | |
338 | ||
339 | struct e1000_hw_stats stats; | |
340 | struct e1000_phy_info phy_info; | |
341 | struct e1000_phy_stats phy_stats; | |
342 | ||
7c25769f BA |
343 | /* Snapshot of PHY registers */ |
344 | struct e1000_phy_regs phy_regs; | |
345 | ||
bc7f75fa AK |
346 | struct e1000_ring test_tx_ring; |
347 | struct e1000_ring test_rx_ring; | |
348 | u32 test_icr; | |
349 | ||
350 | u32 msg_enable; | |
4662e82b BA |
351 | struct msix_entry *msix_entries; |
352 | int int_mode; | |
353 | u32 eiac_mask; | |
bc7f75fa AK |
354 | |
355 | u32 eeprom_wol; | |
356 | u32 wol; | |
357 | u32 pba; | |
2adc55c9 | 358 | u32 max_hw_frame_size; |
bc7f75fa | 359 | |
318a94d6 | 360 | bool fc_autoneg; |
bc7f75fa AK |
361 | |
362 | unsigned long led_status; | |
363 | ||
364 | unsigned int flags; | |
eb7c3adb | 365 | unsigned int flags2; |
a8f88ff5 JB |
366 | struct work_struct downshift_task; |
367 | struct work_struct update_phy_task; | |
a4f58f54 | 368 | struct work_struct led_blink_task; |
41cec6f1 | 369 | struct work_struct print_hang_task; |
bc7f75fa AK |
370 | }; |
371 | ||
372 | struct e1000_info { | |
373 | enum e1000_mac_type mac; | |
374 | unsigned int flags; | |
eb7c3adb | 375 | unsigned int flags2; |
bc7f75fa | 376 | u32 pba; |
2adc55c9 | 377 | u32 max_hw_frame_size; |
69e3fd8c | 378 | s32 (*get_variants)(struct e1000_adapter *); |
bc7f75fa AK |
379 | struct e1000_mac_operations *mac_ops; |
380 | struct e1000_phy_operations *phy_ops; | |
381 | struct e1000_nvm_operations *nvm_ops; | |
382 | }; | |
383 | ||
384 | /* hardware capability, feature, and workaround flags */ | |
385 | #define FLAG_HAS_AMT (1 << 0) | |
386 | #define FLAG_HAS_FLASH (1 << 1) | |
387 | #define FLAG_HAS_HW_VLAN_FILTER (1 << 2) | |
388 | #define FLAG_HAS_WOL (1 << 3) | |
389 | #define FLAG_HAS_ERT (1 << 4) | |
390 | #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) | |
391 | #define FLAG_HAS_SWSM_ON_LOAD (1 << 6) | |
392 | #define FLAG_HAS_JUMBO_FRAMES (1 << 7) | |
4a770358 | 393 | #define FLAG_READ_ONLY_NVM (1 << 8) |
97ac8cae | 394 | #define FLAG_IS_ICH (1 << 9) |
4662e82b | 395 | #define FLAG_HAS_MSIX (1 << 10) |
bc7f75fa AK |
396 | #define FLAG_HAS_SMART_POWER_DOWN (1 << 11) |
397 | #define FLAG_IS_QUAD_PORT_A (1 << 12) | |
398 | #define FLAG_IS_QUAD_PORT (1 << 13) | |
399 | #define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14) | |
400 | #define FLAG_APME_IN_WUC (1 << 15) | |
401 | #define FLAG_APME_IN_CTRL3 (1 << 16) | |
402 | #define FLAG_APME_CHECK_PORT_B (1 << 17) | |
403 | #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) | |
404 | #define FLAG_NO_WAKE_UCAST (1 << 19) | |
405 | #define FLAG_MNG_PT_ENABLED (1 << 20) | |
406 | #define FLAG_RESET_OVERWRITES_LAA (1 << 21) | |
407 | #define FLAG_TARC_SPEED_MODE_BIT (1 << 22) | |
408 | #define FLAG_TARC_SET_BIT_ZERO (1 << 23) | |
409 | #define FLAG_RX_NEEDS_RESTART (1 << 24) | |
410 | #define FLAG_LSC_GIG_SPEED_DROP (1 << 25) | |
411 | #define FLAG_SMART_POWER_DOWN (1 << 26) | |
412 | #define FLAG_MSI_ENABLED (1 << 27) | |
413 | #define FLAG_RX_CSUM_ENABLED (1 << 28) | |
414 | #define FLAG_TSO_FORCE (1 << 29) | |
318a94d6 | 415 | #define FLAG_RX_RESTART_NOW (1 << 30) |
f8d59f78 | 416 | #define FLAG_MSI_TEST_FAILED (1 << 31) |
bc7f75fa | 417 | |
eb7c3adb JK |
418 | /* CRC Stripping defines */ |
419 | #define FLAG2_CRC_STRIPPING (1 << 0) | |
a4f58f54 | 420 | #define FLAG2_HAS_PHY_WAKEUP (1 << 1) |
eb7c3adb | 421 | |
bc7f75fa AK |
422 | #define E1000_RX_DESC_PS(R, i) \ |
423 | (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) | |
424 | #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) | |
425 | #define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) | |
426 | #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) | |
427 | #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) | |
428 | ||
429 | enum e1000_state_t { | |
430 | __E1000_TESTING, | |
431 | __E1000_RESETTING, | |
432 | __E1000_DOWN | |
433 | }; | |
434 | ||
435 | enum latency_range { | |
436 | lowest_latency = 0, | |
437 | low_latency = 1, | |
438 | bulk_latency = 2, | |
439 | latency_invalid = 255 | |
440 | }; | |
441 | ||
442 | extern char e1000e_driver_name[]; | |
443 | extern const char e1000e_driver_version[]; | |
444 | ||
445 | extern void e1000e_check_options(struct e1000_adapter *adapter); | |
446 | extern void e1000e_set_ethtool_ops(struct net_device *netdev); | |
447 | ||
448 | extern int e1000e_up(struct e1000_adapter *adapter); | |
449 | extern void e1000e_down(struct e1000_adapter *adapter); | |
450 | extern void e1000e_reinit_locked(struct e1000_adapter *adapter); | |
451 | extern void e1000e_reset(struct e1000_adapter *adapter); | |
452 | extern void e1000e_power_up_phy(struct e1000_adapter *adapter); | |
453 | extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter); | |
454 | extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter); | |
455 | extern void e1000e_free_rx_resources(struct e1000_adapter *adapter); | |
456 | extern void e1000e_free_tx_resources(struct e1000_adapter *adapter); | |
457 | extern void e1000e_update_stats(struct e1000_adapter *adapter); | |
a20e4cf9 | 458 | extern bool e1000_has_link(struct e1000_adapter *adapter); |
4662e82b BA |
459 | extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter); |
460 | extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter); | |
bc7f75fa AK |
461 | |
462 | extern unsigned int copybreak; | |
463 | ||
464 | extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw); | |
465 | ||
466 | extern struct e1000_info e1000_82571_info; | |
467 | extern struct e1000_info e1000_82572_info; | |
468 | extern struct e1000_info e1000_82573_info; | |
4662e82b | 469 | extern struct e1000_info e1000_82574_info; |
8c81c9c3 | 470 | extern struct e1000_info e1000_82583_info; |
bc7f75fa AK |
471 | extern struct e1000_info e1000_ich8_info; |
472 | extern struct e1000_info e1000_ich9_info; | |
f4187b56 | 473 | extern struct e1000_info e1000_ich10_info; |
a4f58f54 | 474 | extern struct e1000_info e1000_pch_info; |
bc7f75fa AK |
475 | extern struct e1000_info e1000_es2_info; |
476 | ||
69e3fd8c | 477 | extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num); |
bc7f75fa AK |
478 | |
479 | extern s32 e1000e_commit_phy(struct e1000_hw *hw); | |
480 | ||
481 | extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); | |
482 | ||
483 | extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw); | |
484 | extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); | |
485 | ||
4a770358 | 486 | extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw); |
bc7f75fa AK |
487 | extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, |
488 | bool state); | |
489 | extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); | |
490 | extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); | |
97ac8cae | 491 | extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw); |
bb436b20 | 492 | extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); |
bc7f75fa AK |
493 | |
494 | extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw); | |
495 | extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw); | |
496 | extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw); | |
a4f58f54 | 497 | extern s32 e1000e_setup_led_generic(struct e1000_hw *hw); |
bc7f75fa AK |
498 | extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw); |
499 | extern s32 e1000e_led_on_generic(struct e1000_hw *hw); | |
500 | extern s32 e1000e_led_off_generic(struct e1000_hw *hw); | |
501 | extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw); | |
502 | extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex); | |
503 | extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex); | |
504 | extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw); | |
505 | extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw); | |
506 | extern s32 e1000e_id_led_init(struct e1000_hw *hw); | |
507 | extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw); | |
508 | extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw); | |
509 | extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); | |
510 | extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); | |
511 | extern s32 e1000e_setup_link(struct e1000_hw *hw); | |
512 | extern void e1000e_clear_vfta(struct e1000_hw *hw); | |
513 | extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); | |
e2de3eb6 JK |
514 | extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, |
515 | u8 *mc_addr_list, | |
516 | u32 mc_addr_count, | |
517 | u32 rar_used_count, | |
518 | u32 rar_count); | |
bc7f75fa AK |
519 | extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); |
520 | extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); | |
521 | extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); | |
522 | extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw); | |
523 | extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data); | |
524 | extern void e1000e_config_collision_dist(struct e1000_hw *hw); | |
525 | extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw); | |
526 | extern s32 e1000e_force_mac_fc(struct e1000_hw *hw); | |
527 | extern s32 e1000e_blink_led(struct e1000_hw *hw); | |
528 | extern void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); | |
529 | extern void e1000e_reset_adaptive(struct e1000_hw *hw); | |
530 | extern void e1000e_update_adaptive(struct e1000_hw *hw); | |
531 | ||
532 | extern s32 e1000e_setup_copper_link(struct e1000_hw *hw); | |
533 | extern s32 e1000e_get_phy_id(struct e1000_hw *hw); | |
534 | extern void e1000e_put_hw_semaphore(struct e1000_hw *hw); | |
535 | extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw); | |
536 | extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); | |
537 | extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); | |
538 | extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw); | |
539 | extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); | |
5ccdcecb BA |
540 | extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, |
541 | u16 *data); | |
bc7f75fa AK |
542 | extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); |
543 | extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); | |
544 | extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); | |
5ccdcecb BA |
545 | extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, |
546 | u16 data); | |
bc7f75fa AK |
547 | extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw); |
548 | extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); | |
549 | extern s32 e1000e_get_cfg_done(struct e1000_hw *hw); | |
550 | extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw); | |
551 | extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw); | |
552 | extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); | |
553 | extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); | |
f4187b56 | 554 | extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); |
bc7f75fa | 555 | extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); |
97ac8cae BA |
556 | extern s32 e1000e_determine_phy_address(struct e1000_hw *hw); |
557 | extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); | |
558 | extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); | |
4662e82b BA |
559 | extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); |
560 | extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); | |
bc7f75fa AK |
561 | extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); |
562 | extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); | |
5ccdcecb BA |
563 | extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, |
564 | u16 data); | |
bc7f75fa | 565 | extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); |
5ccdcecb BA |
566 | extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, |
567 | u16 *data); | |
bc7f75fa AK |
568 | extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
569 | u32 usec_interval, bool *success); | |
570 | extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); | |
2d9498f3 DG |
571 | extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); |
572 | extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); | |
bc7f75fa | 573 | extern s32 e1000e_check_downshift(struct e1000_hw *hw); |
a4f58f54 | 574 | extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); |
5ccdcecb BA |
575 | extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, |
576 | u16 *data); | |
a4f58f54 | 577 | extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); |
5ccdcecb BA |
578 | extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, |
579 | u16 data); | |
a4f58f54 BA |
580 | extern s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow); |
581 | extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); | |
582 | extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); | |
583 | extern s32 e1000_check_polarity_82577(struct e1000_hw *hw); | |
584 | extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw); | |
585 | extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); | |
586 | extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw); | |
bc7f75fa AK |
587 | |
588 | static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) | |
589 | { | |
94d8186a | 590 | return hw->phy.ops.reset(hw); |
bc7f75fa AK |
591 | } |
592 | ||
593 | static inline s32 e1000_check_reset_block(struct e1000_hw *hw) | |
594 | { | |
595 | return hw->phy.ops.check_reset_block(hw); | |
596 | } | |
597 | ||
598 | static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data) | |
599 | { | |
94d8186a | 600 | return hw->phy.ops.read_reg(hw, offset, data); |
bc7f75fa AK |
601 | } |
602 | ||
603 | static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data) | |
604 | { | |
94d8186a | 605 | return hw->phy.ops.write_reg(hw, offset, data); |
bc7f75fa AK |
606 | } |
607 | ||
608 | static inline s32 e1000_get_cable_length(struct e1000_hw *hw) | |
609 | { | |
610 | return hw->phy.ops.get_cable_length(hw); | |
611 | } | |
612 | ||
613 | extern s32 e1000e_acquire_nvm(struct e1000_hw *hw); | |
614 | extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); | |
615 | extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw); | |
616 | extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg); | |
bc7f75fa AK |
617 | extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); |
618 | extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw); | |
619 | extern void e1000e_release_nvm(struct e1000_hw *hw); | |
620 | extern void e1000e_reload_nvm(struct e1000_hw *hw); | |
621 | extern s32 e1000e_read_mac_addr(struct e1000_hw *hw); | |
622 | ||
623 | static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw) | |
624 | { | |
94d8186a | 625 | return hw->nvm.ops.validate(hw); |
bc7f75fa AK |
626 | } |
627 | ||
628 | static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw) | |
629 | { | |
94d8186a | 630 | return hw->nvm.ops.update(hw); |
bc7f75fa AK |
631 | } |
632 | ||
633 | static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
634 | { | |
94d8186a | 635 | return hw->nvm.ops.read(hw, offset, words, data); |
bc7f75fa AK |
636 | } |
637 | ||
638 | static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
639 | { | |
94d8186a | 640 | return hw->nvm.ops.write(hw, offset, words, data); |
bc7f75fa AK |
641 | } |
642 | ||
643 | static inline s32 e1000_get_phy_info(struct e1000_hw *hw) | |
644 | { | |
94d8186a | 645 | return hw->phy.ops.get_info(hw); |
bc7f75fa AK |
646 | } |
647 | ||
4662e82b BA |
648 | static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw) |
649 | { | |
650 | return hw->mac.ops.check_mng_mode(hw); | |
651 | } | |
652 | ||
653 | extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw); | |
bc7f75fa AK |
654 | extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); |
655 | extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); | |
656 | ||
657 | static inline u32 __er32(struct e1000_hw *hw, unsigned long reg) | |
658 | { | |
659 | return readl(hw->hw_addr + reg); | |
660 | } | |
661 | ||
662 | static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) | |
663 | { | |
664 | writel(val, hw->hw_addr + reg); | |
665 | } | |
666 | ||
667 | #endif /* _E1000_H_ */ |