Commit | Line | Data |
---|---|---|
bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
c7e54b1b | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
8c81c9c3 | 43 | * 82583V Gigabit Network Connection |
bc7f75fa AK |
44 | */ |
45 | ||
bc7f75fa AK |
46 | #include "e1000.h" |
47 | ||
48 | #define ID_LED_RESERVED_F746 0xF746 | |
49 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
50 | (ID_LED_OFF1_ON2 << 8) | \ | |
51 | (ID_LED_DEF1_DEF2 << 4) | \ | |
52 | (ID_LED_DEF1_DEF2)) | |
53 | ||
54 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
55 | ||
4662e82b BA |
56 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
57 | ||
bc7f75fa AK |
58 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
59 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
60 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
c9523379 | 61 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
bc7f75fa AK |
62 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
63 | u16 words, u16 *data); | |
64 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
65 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
66 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
67 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
4662e82b BA |
68 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
69 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
23a2d1b2 | 70 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
bc7f75fa AK |
71 | |
72 | /** | |
73 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
74 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
75 | **/ |
76 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
77 | { | |
78 | struct e1000_phy_info *phy = &hw->phy; | |
79 | s32 ret_val; | |
80 | ||
318a94d6 | 81 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
82 | phy->type = e1000_phy_none; |
83 | return 0; | |
84 | } | |
85 | ||
86 | phy->addr = 1; | |
87 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
88 | phy->reset_delay_us = 100; | |
89 | ||
90 | switch (hw->mac.type) { | |
91 | case e1000_82571: | |
92 | case e1000_82572: | |
93 | phy->type = e1000_phy_igp_2; | |
94 | break; | |
95 | case e1000_82573: | |
96 | phy->type = e1000_phy_m88; | |
97 | break; | |
4662e82b | 98 | case e1000_82574: |
8c81c9c3 | 99 | case e1000_82583: |
4662e82b BA |
100 | phy->type = e1000_phy_bm; |
101 | break; | |
bc7f75fa AK |
102 | default: |
103 | return -E1000_ERR_PHY; | |
104 | break; | |
105 | } | |
106 | ||
107 | /* This can only be done after all function pointers are setup. */ | |
108 | ret_val = e1000_get_phy_id_82571(hw); | |
109 | ||
110 | /* Verify phy id */ | |
111 | switch (hw->mac.type) { | |
112 | case e1000_82571: | |
113 | case e1000_82572: | |
114 | if (phy->id != IGP01E1000_I_PHY_ID) | |
115 | return -E1000_ERR_PHY; | |
116 | break; | |
117 | case e1000_82573: | |
118 | if (phy->id != M88E1111_I_PHY_ID) | |
119 | return -E1000_ERR_PHY; | |
120 | break; | |
4662e82b | 121 | case e1000_82574: |
8c81c9c3 | 122 | case e1000_82583: |
4662e82b BA |
123 | if (phy->id != BME1000_E_PHY_ID_R2) |
124 | return -E1000_ERR_PHY; | |
125 | break; | |
bc7f75fa AK |
126 | default: |
127 | return -E1000_ERR_PHY; | |
128 | break; | |
129 | } | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | /** | |
135 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
136 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
137 | **/ |
138 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
139 | { | |
140 | struct e1000_nvm_info *nvm = &hw->nvm; | |
141 | u32 eecd = er32(EECD); | |
142 | u16 size; | |
143 | ||
144 | nvm->opcode_bits = 8; | |
145 | nvm->delay_usec = 1; | |
146 | switch (nvm->override) { | |
147 | case e1000_nvm_override_spi_large: | |
148 | nvm->page_size = 32; | |
149 | nvm->address_bits = 16; | |
150 | break; | |
151 | case e1000_nvm_override_spi_small: | |
152 | nvm->page_size = 8; | |
153 | nvm->address_bits = 8; | |
154 | break; | |
155 | default: | |
156 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
157 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
158 | break; | |
159 | } | |
160 | ||
161 | switch (hw->mac.type) { | |
162 | case e1000_82573: | |
4662e82b | 163 | case e1000_82574: |
8c81c9c3 | 164 | case e1000_82583: |
bc7f75fa AK |
165 | if (((eecd >> 15) & 0x3) == 0x3) { |
166 | nvm->type = e1000_nvm_flash_hw; | |
167 | nvm->word_size = 2048; | |
ad68076e BA |
168 | /* |
169 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
170 | * to Flash update issue. |
171 | */ | |
172 | eecd &= ~E1000_EECD_AUPDEN; | |
173 | ew32(EECD, eecd); | |
174 | break; | |
175 | } | |
176 | /* Fall Through */ | |
177 | default: | |
ad68076e | 178 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
179 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
180 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
181 | /* |
182 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
183 | * for setting word_size. |
184 | */ | |
185 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
186 | |
187 | /* EEPROM access above 16k is unsupported */ | |
188 | if (size > 14) | |
189 | size = 14; | |
bc7f75fa AK |
190 | nvm->word_size = 1 << size; |
191 | break; | |
192 | } | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | /** | |
198 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
199 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
200 | **/ |
201 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
202 | { | |
203 | struct e1000_hw *hw = &adapter->hw; | |
204 | struct e1000_mac_info *mac = &hw->mac; | |
205 | struct e1000_mac_operations *func = &mac->ops; | |
23a2d1b2 DG |
206 | u32 swsm = 0; |
207 | u32 swsm2 = 0; | |
208 | bool force_clear_smbi = false; | |
bc7f75fa AK |
209 | |
210 | /* Set media type */ | |
211 | switch (adapter->pdev->device) { | |
212 | case E1000_DEV_ID_82571EB_FIBER: | |
213 | case E1000_DEV_ID_82572EI_FIBER: | |
214 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 215 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
216 | break; |
217 | case E1000_DEV_ID_82571EB_SERDES: | |
218 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
219 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
220 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 221 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
222 | break; |
223 | default: | |
318a94d6 | 224 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
225 | break; |
226 | } | |
227 | ||
228 | /* Set mta register count */ | |
229 | mac->mta_reg_count = 128; | |
230 | /* Set rar entry count */ | |
231 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
232 | /* Set if manageability features are enabled. */ | |
564ea9bb BA |
233 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) |
234 | ? true : false; | |
bc7f75fa AK |
235 | |
236 | /* check for link */ | |
318a94d6 | 237 | switch (hw->phy.media_type) { |
bc7f75fa AK |
238 | case e1000_media_type_copper: |
239 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
240 | func->check_for_link = e1000e_check_for_copper_link; | |
241 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
242 | break; | |
243 | case e1000_media_type_fiber: | |
ad68076e BA |
244 | func->setup_physical_interface = |
245 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 246 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
247 | func->get_link_up_info = |
248 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
249 | break; |
250 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
251 | func->setup_physical_interface = |
252 | e1000_setup_fiber_serdes_link_82571; | |
c9523379 | 253 | func->check_for_link = e1000_check_for_serdes_link_82571; |
ad68076e BA |
254 | func->get_link_up_info = |
255 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
256 | break; |
257 | default: | |
258 | return -E1000_ERR_CONFIG; | |
259 | break; | |
260 | } | |
261 | ||
4662e82b BA |
262 | switch (hw->mac.type) { |
263 | case e1000_82574: | |
8c81c9c3 | 264 | case e1000_82583: |
4662e82b BA |
265 | func->check_mng_mode = e1000_check_mng_mode_82574; |
266 | func->led_on = e1000_led_on_82574; | |
267 | break; | |
268 | default: | |
269 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
270 | func->led_on = e1000e_led_on_generic; | |
271 | break; | |
272 | } | |
273 | ||
23a2d1b2 DG |
274 | /* |
275 | * Ensure that the inter-port SWSM.SMBI lock bit is clear before | |
276 | * first NVM or PHY acess. This should be done for single-port | |
277 | * devices, and for one port only on dual-port devices so that | |
278 | * for those devices we can still use the SMBI lock to synchronize | |
279 | * inter-port accesses to the PHY & NVM. | |
280 | */ | |
281 | switch (hw->mac.type) { | |
282 | case e1000_82571: | |
283 | case e1000_82572: | |
284 | swsm2 = er32(SWSM2); | |
285 | ||
286 | if (!(swsm2 & E1000_SWSM2_LOCK)) { | |
287 | /* Only do this for the first interface on this card */ | |
288 | ew32(SWSM2, | |
289 | swsm2 | E1000_SWSM2_LOCK); | |
290 | force_clear_smbi = true; | |
291 | } else | |
292 | force_clear_smbi = false; | |
293 | break; | |
294 | default: | |
295 | force_clear_smbi = true; | |
296 | break; | |
297 | } | |
298 | ||
299 | if (force_clear_smbi) { | |
300 | /* Make sure SWSM.SMBI is clear */ | |
301 | swsm = er32(SWSM); | |
302 | if (swsm & E1000_SWSM_SMBI) { | |
303 | /* This bit should not be set on a first interface, and | |
304 | * indicates that the bootagent or EFI code has | |
305 | * improperly left this bit enabled | |
306 | */ | |
3bb99fe2 | 307 | e_dbg("Please update your 82571 Bootagent\n"); |
23a2d1b2 DG |
308 | } |
309 | ew32(SWSM, swsm & ~E1000_SWSM_SMBI); | |
310 | } | |
311 | ||
312 | /* | |
313 | * Initialze device specific counter of SMBI acquisition | |
314 | * timeouts. | |
315 | */ | |
316 | hw->dev_spec.e82571.smb_counter = 0; | |
317 | ||
bc7f75fa AK |
318 | return 0; |
319 | } | |
320 | ||
69e3fd8c | 321 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
322 | { |
323 | struct e1000_hw *hw = &adapter->hw; | |
324 | static int global_quad_port_a; /* global port a indication */ | |
325 | struct pci_dev *pdev = adapter->pdev; | |
326 | u16 eeprom_data = 0; | |
327 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; | |
328 | s32 rc; | |
329 | ||
330 | rc = e1000_init_mac_params_82571(adapter); | |
331 | if (rc) | |
332 | return rc; | |
333 | ||
334 | rc = e1000_init_nvm_params_82571(hw); | |
335 | if (rc) | |
336 | return rc; | |
337 | ||
338 | rc = e1000_init_phy_params_82571(hw); | |
339 | if (rc) | |
340 | return rc; | |
341 | ||
342 | /* tag quad port adapters first, it's used below */ | |
343 | switch (pdev->device) { | |
344 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
345 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
346 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 347 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
348 | adapter->flags |= FLAG_IS_QUAD_PORT; |
349 | /* mark the first port */ | |
350 | if (global_quad_port_a == 0) | |
351 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
352 | /* Reset for multiple quad port adapters */ | |
353 | global_quad_port_a++; | |
354 | if (global_quad_port_a == 4) | |
355 | global_quad_port_a = 0; | |
356 | break; | |
357 | default: | |
358 | break; | |
359 | } | |
360 | ||
361 | switch (adapter->hw.mac.type) { | |
362 | case e1000_82571: | |
363 | /* these dual ports don't have WoL on port B at all */ | |
364 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
365 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
366 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
367 | (is_port_b)) | |
368 | adapter->flags &= ~FLAG_HAS_WOL; | |
369 | /* quad ports only support WoL on port A */ | |
370 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 371 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 372 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
373 | /* Does not support WoL on any port */ |
374 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
375 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa AK |
376 | break; |
377 | ||
378 | case e1000_82573: | |
379 | if (pdev->device == E1000_DEV_ID_82573L) { | |
e243455d BA |
380 | if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, |
381 | &eeprom_data) < 0) | |
382 | break; | |
2adc55c9 BA |
383 | if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) { |
384 | adapter->flags |= FLAG_HAS_JUMBO_FRAMES; | |
385 | adapter->max_hw_frame_size = DEFAULT_JUMBO; | |
386 | } | |
bc7f75fa AK |
387 | } |
388 | break; | |
389 | default: | |
390 | break; | |
391 | } | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
396 | /** | |
397 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
398 | * @hw: pointer to the HW structure | |
399 | * | |
400 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
401 | * revision in the hardware structure. | |
402 | **/ | |
403 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
404 | { | |
405 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
406 | s32 ret_val; |
407 | u16 phy_id = 0; | |
bc7f75fa AK |
408 | |
409 | switch (hw->mac.type) { | |
410 | case e1000_82571: | |
411 | case e1000_82572: | |
ad68076e BA |
412 | /* |
413 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
414 | * In this case, we cannot access the PHY until the |
415 | * configuration is done. So we explicitly set the | |
ad68076e BA |
416 | * PHY ID. |
417 | */ | |
bc7f75fa AK |
418 | phy->id = IGP01E1000_I_PHY_ID; |
419 | break; | |
420 | case e1000_82573: | |
421 | return e1000e_get_phy_id(hw); | |
422 | break; | |
4662e82b | 423 | case e1000_82574: |
8c81c9c3 | 424 | case e1000_82583: |
4662e82b BA |
425 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
426 | if (ret_val) | |
427 | return ret_val; | |
428 | ||
429 | phy->id = (u32)(phy_id << 16); | |
430 | udelay(20); | |
431 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
432 | if (ret_val) | |
433 | return ret_val; | |
434 | ||
435 | phy->id |= (u32)(phy_id); | |
436 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
437 | break; | |
bc7f75fa AK |
438 | default: |
439 | return -E1000_ERR_PHY; | |
440 | break; | |
441 | } | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
446 | /** | |
447 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
448 | * @hw: pointer to the HW structure | |
449 | * | |
450 | * Acquire the HW semaphore to access the PHY or NVM | |
451 | **/ | |
452 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
453 | { | |
454 | u32 swsm; | |
23a2d1b2 DG |
455 | s32 sw_timeout = hw->nvm.word_size + 1; |
456 | s32 fw_timeout = hw->nvm.word_size + 1; | |
bc7f75fa AK |
457 | s32 i = 0; |
458 | ||
23a2d1b2 DG |
459 | /* |
460 | * If we have timedout 3 times on trying to acquire | |
461 | * the inter-port SMBI semaphore, there is old code | |
462 | * operating on the other port, and it is not | |
463 | * releasing SMBI. Modify the number of times that | |
464 | * we try for the semaphore to interwork with this | |
465 | * older code. | |
466 | */ | |
467 | if (hw->dev_spec.e82571.smb_counter > 2) | |
468 | sw_timeout = 1; | |
469 | ||
470 | /* Get the SW semaphore */ | |
471 | while (i < sw_timeout) { | |
472 | swsm = er32(SWSM); | |
473 | if (!(swsm & E1000_SWSM_SMBI)) | |
474 | break; | |
475 | ||
476 | udelay(50); | |
477 | i++; | |
478 | } | |
479 | ||
480 | if (i == sw_timeout) { | |
3bb99fe2 | 481 | e_dbg("Driver can't access device - SMBI bit is set.\n"); |
23a2d1b2 DG |
482 | hw->dev_spec.e82571.smb_counter++; |
483 | } | |
bc7f75fa | 484 | /* Get the FW semaphore. */ |
23a2d1b2 | 485 | for (i = 0; i < fw_timeout; i++) { |
bc7f75fa AK |
486 | swsm = er32(SWSM); |
487 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
488 | ||
489 | /* Semaphore acquired if bit latched */ | |
490 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
491 | break; | |
492 | ||
493 | udelay(50); | |
494 | } | |
495 | ||
23a2d1b2 | 496 | if (i == fw_timeout) { |
bc7f75fa | 497 | /* Release semaphores */ |
23a2d1b2 | 498 | e1000_put_hw_semaphore_82571(hw); |
3bb99fe2 | 499 | e_dbg("Driver can't access the NVM\n"); |
bc7f75fa AK |
500 | return -E1000_ERR_NVM; |
501 | } | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | /** | |
507 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
508 | * @hw: pointer to the HW structure | |
509 | * | |
510 | * Release hardware semaphore used to access the PHY or NVM | |
511 | **/ | |
512 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
513 | { | |
514 | u32 swsm; | |
515 | ||
516 | swsm = er32(SWSM); | |
23a2d1b2 | 517 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
bc7f75fa AK |
518 | ew32(SWSM, swsm); |
519 | } | |
520 | ||
521 | /** | |
522 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
523 | * @hw: pointer to the HW structure | |
524 | * | |
525 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
526 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
527 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
528 | * hardware semaphore. | |
529 | **/ | |
530 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
531 | { | |
532 | s32 ret_val; | |
533 | ||
534 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
535 | if (ret_val) | |
536 | return ret_val; | |
537 | ||
8c81c9c3 AD |
538 | switch (hw->mac.type) { |
539 | case e1000_82573: | |
540 | case e1000_82574: | |
541 | case e1000_82583: | |
542 | break; | |
543 | default: | |
bc7f75fa | 544 | ret_val = e1000e_acquire_nvm(hw); |
8c81c9c3 AD |
545 | break; |
546 | } | |
bc7f75fa AK |
547 | |
548 | if (ret_val) | |
549 | e1000_put_hw_semaphore_82571(hw); | |
550 | ||
551 | return ret_val; | |
552 | } | |
553 | ||
554 | /** | |
555 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
556 | * @hw: pointer to the HW structure | |
557 | * | |
558 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
559 | **/ | |
560 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
561 | { | |
562 | e1000e_release_nvm(hw); | |
563 | e1000_put_hw_semaphore_82571(hw); | |
564 | } | |
565 | ||
566 | /** | |
567 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
568 | * @hw: pointer to the HW structure | |
569 | * @offset: offset within the EEPROM to be written to | |
570 | * @words: number of words to write | |
571 | * @data: 16 bit word(s) to be written to the EEPROM | |
572 | * | |
573 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
574 | * | |
575 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 576 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
577 | **/ |
578 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
579 | u16 *data) | |
580 | { | |
581 | s32 ret_val; | |
582 | ||
583 | switch (hw->mac.type) { | |
584 | case e1000_82573: | |
4662e82b | 585 | case e1000_82574: |
8c81c9c3 | 586 | case e1000_82583: |
bc7f75fa AK |
587 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
588 | break; | |
589 | case e1000_82571: | |
590 | case e1000_82572: | |
591 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
592 | break; | |
593 | default: | |
594 | ret_val = -E1000_ERR_NVM; | |
595 | break; | |
596 | } | |
597 | ||
598 | return ret_val; | |
599 | } | |
600 | ||
601 | /** | |
602 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
603 | * @hw: pointer to the HW structure | |
604 | * | |
605 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
606 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
607 | * value to the EEPROM. | |
608 | **/ | |
609 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
610 | { | |
611 | u32 eecd; | |
612 | s32 ret_val; | |
613 | u16 i; | |
614 | ||
615 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
616 | if (ret_val) | |
617 | return ret_val; | |
618 | ||
ad68076e BA |
619 | /* |
620 | * If our nvm is an EEPROM, then we're done | |
621 | * otherwise, commit the checksum to the flash NVM. | |
622 | */ | |
bc7f75fa AK |
623 | if (hw->nvm.type != e1000_nvm_flash_hw) |
624 | return ret_val; | |
625 | ||
626 | /* Check for pending operations. */ | |
627 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
628 | msleep(1); | |
629 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
630 | break; | |
631 | } | |
632 | ||
633 | if (i == E1000_FLASH_UPDATES) | |
634 | return -E1000_ERR_NVM; | |
635 | ||
636 | /* Reset the firmware if using STM opcode. */ | |
637 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
638 | /* |
639 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
640 | * in two write cycles. |
641 | */ | |
642 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
643 | e1e_flush(); | |
644 | ew32(HICR, E1000_HICR_FW_RESET); | |
645 | } | |
646 | ||
647 | /* Commit the write to flash */ | |
648 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
649 | ew32(EECD, eecd); | |
650 | ||
651 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
652 | msleep(1); | |
653 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
654 | break; | |
655 | } | |
656 | ||
657 | if (i == E1000_FLASH_UPDATES) | |
658 | return -E1000_ERR_NVM; | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
663 | /** | |
664 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
665 | * @hw: pointer to the HW structure | |
666 | * | |
667 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
668 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
669 | **/ | |
670 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
671 | { | |
672 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
673 | e1000_fix_nvm_checksum_82571(hw); | |
674 | ||
675 | return e1000e_validate_nvm_checksum_generic(hw); | |
676 | } | |
677 | ||
678 | /** | |
679 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
680 | * @hw: pointer to the HW structure | |
681 | * @offset: offset within the EEPROM to be written to | |
682 | * @words: number of words to write | |
683 | * @data: 16 bit word(s) to be written to the EEPROM | |
684 | * | |
685 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
686 | * command has completed before trying to write the next word. After write | |
687 | * poll for completion. | |
688 | * | |
689 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 690 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
691 | **/ |
692 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
693 | u16 words, u16 *data) | |
694 | { | |
695 | struct e1000_nvm_info *nvm = &hw->nvm; | |
a708dd88 | 696 | u32 i, eewr = 0; |
bc7f75fa AK |
697 | s32 ret_val = 0; |
698 | ||
ad68076e BA |
699 | /* |
700 | * A check for invalid values: offset too large, too many words, | |
701 | * and not enough words. | |
702 | */ | |
bc7f75fa AK |
703 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
704 | (words == 0)) { | |
3bb99fe2 | 705 | e_dbg("nvm parameter(s) out of bounds\n"); |
bc7f75fa AK |
706 | return -E1000_ERR_NVM; |
707 | } | |
708 | ||
709 | for (i = 0; i < words; i++) { | |
710 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
711 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
712 | E1000_NVM_RW_REG_START; | |
713 | ||
714 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
715 | if (ret_val) | |
716 | break; | |
717 | ||
718 | ew32(EEWR, eewr); | |
719 | ||
720 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
721 | if (ret_val) | |
722 | break; | |
723 | } | |
724 | ||
725 | return ret_val; | |
726 | } | |
727 | ||
728 | /** | |
729 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
730 | * @hw: pointer to the HW structure | |
731 | * | |
732 | * Reads the management control register for the config done bit to be set. | |
733 | **/ | |
734 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
735 | { | |
736 | s32 timeout = PHY_CFG_TIMEOUT; | |
737 | ||
738 | while (timeout) { | |
739 | if (er32(EEMNGCTL) & | |
740 | E1000_NVM_CFG_DONE_PORT_0) | |
741 | break; | |
742 | msleep(1); | |
743 | timeout--; | |
744 | } | |
745 | if (!timeout) { | |
3bb99fe2 | 746 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
747 | return -E1000_ERR_RESET; |
748 | } | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | /** | |
754 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
755 | * @hw: pointer to the HW structure | |
564ea9bb | 756 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
757 | * |
758 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
759 | * this function also disables smart speed and vice versa. LPLU will not be | |
760 | * activated unless the device autonegotiation advertisement meets standards | |
761 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
762 | * pointer entry point only called by PHY setup routines. | |
763 | **/ | |
764 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
765 | { | |
766 | struct e1000_phy_info *phy = &hw->phy; | |
767 | s32 ret_val; | |
768 | u16 data; | |
769 | ||
770 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
771 | if (ret_val) | |
772 | return ret_val; | |
773 | ||
774 | if (active) { | |
775 | data |= IGP02E1000_PM_D0_LPLU; | |
776 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
777 | if (ret_val) | |
778 | return ret_val; | |
779 | ||
780 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
781 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
782 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
783 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
784 | if (ret_val) | |
785 | return ret_val; | |
786 | } else { | |
787 | data &= ~IGP02E1000_PM_D0_LPLU; | |
788 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
789 | /* |
790 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
791 | * during Dx states where the power conservation is most |
792 | * important. During driver activity we should enable | |
ad68076e BA |
793 | * SmartSpeed, so performance is maintained. |
794 | */ | |
bc7f75fa AK |
795 | if (phy->smart_speed == e1000_smart_speed_on) { |
796 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 797 | &data); |
bc7f75fa AK |
798 | if (ret_val) |
799 | return ret_val; | |
800 | ||
801 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
802 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 803 | data); |
bc7f75fa AK |
804 | if (ret_val) |
805 | return ret_val; | |
806 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
807 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 808 | &data); |
bc7f75fa AK |
809 | if (ret_val) |
810 | return ret_val; | |
811 | ||
812 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
813 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 814 | data); |
bc7f75fa AK |
815 | if (ret_val) |
816 | return ret_val; | |
817 | } | |
818 | } | |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
823 | /** | |
824 | * e1000_reset_hw_82571 - Reset hardware | |
825 | * @hw: pointer to the HW structure | |
826 | * | |
fe401674 | 827 | * This resets the hardware into a known state. |
bc7f75fa AK |
828 | **/ |
829 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
830 | { | |
a708dd88 | 831 | u32 ctrl, extcnf_ctrl, ctrl_ext, icr; |
bc7f75fa AK |
832 | s32 ret_val; |
833 | u16 i = 0; | |
834 | ||
ad68076e BA |
835 | /* |
836 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
837 | * on the last TLP read/write transaction when MAC is reset. |
838 | */ | |
839 | ret_val = e1000e_disable_pcie_master(hw); | |
840 | if (ret_val) | |
3bb99fe2 | 841 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 842 | |
3bb99fe2 | 843 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
844 | ew32(IMC, 0xffffffff); |
845 | ||
846 | ew32(RCTL, 0); | |
847 | ew32(TCTL, E1000_TCTL_PSP); | |
848 | e1e_flush(); | |
849 | ||
850 | msleep(10); | |
851 | ||
ad68076e BA |
852 | /* |
853 | * Must acquire the MDIO ownership before MAC reset. | |
854 | * Ownership defaults to firmware after a reset. | |
855 | */ | |
8c81c9c3 AD |
856 | switch (hw->mac.type) { |
857 | case e1000_82573: | |
858 | case e1000_82574: | |
859 | case e1000_82583: | |
bc7f75fa AK |
860 | extcnf_ctrl = er32(EXTCNF_CTRL); |
861 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
862 | ||
863 | do { | |
864 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
865 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
866 | ||
867 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
868 | break; | |
869 | ||
870 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
871 | ||
872 | msleep(2); | |
873 | i++; | |
874 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
8c81c9c3 AD |
875 | break; |
876 | default: | |
877 | break; | |
bc7f75fa AK |
878 | } |
879 | ||
880 | ctrl = er32(CTRL); | |
881 | ||
3bb99fe2 | 882 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa AK |
883 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
884 | ||
885 | if (hw->nvm.type == e1000_nvm_flash_hw) { | |
886 | udelay(10); | |
887 | ctrl_ext = er32(CTRL_EXT); | |
888 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
889 | ew32(CTRL_EXT, ctrl_ext); | |
890 | e1e_flush(); | |
891 | } | |
892 | ||
893 | ret_val = e1000e_get_auto_rd_done(hw); | |
894 | if (ret_val) | |
895 | /* We don't want to continue accessing MAC registers. */ | |
896 | return ret_val; | |
897 | ||
ad68076e BA |
898 | /* |
899 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
900 | * Need to wait for Phy configuration completion before accessing |
901 | * NVM and Phy. | |
902 | */ | |
8c81c9c3 AD |
903 | |
904 | switch (hw->mac.type) { | |
905 | case e1000_82573: | |
906 | case e1000_82574: | |
907 | case e1000_82583: | |
bc7f75fa | 908 | msleep(25); |
8c81c9c3 AD |
909 | break; |
910 | default: | |
911 | break; | |
912 | } | |
bc7f75fa AK |
913 | |
914 | /* Clear any pending interrupt events. */ | |
915 | ew32(IMC, 0xffffffff); | |
916 | icr = er32(ICR); | |
917 | ||
93ca1610 BH |
918 | if (hw->mac.type == e1000_82571 && |
919 | hw->dev_spec.e82571.alt_mac_addr_is_present) | |
920 | e1000e_set_laa_state_82571(hw, true); | |
921 | ||
c9523379 | 922 | /* Reinitialize the 82571 serdes link state machine */ |
923 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
924 | hw->mac.serdes_link_state = e1000_serdes_link_down; | |
925 | ||
bc7f75fa AK |
926 | return 0; |
927 | } | |
928 | ||
929 | /** | |
930 | * e1000_init_hw_82571 - Initialize hardware | |
931 | * @hw: pointer to the HW structure | |
932 | * | |
933 | * This inits the hardware readying it for operation. | |
934 | **/ | |
935 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
936 | { | |
937 | struct e1000_mac_info *mac = &hw->mac; | |
938 | u32 reg_data; | |
939 | s32 ret_val; | |
a708dd88 | 940 | u16 i, rar_count = mac->rar_entry_count; |
bc7f75fa AK |
941 | |
942 | e1000_initialize_hw_bits_82571(hw); | |
943 | ||
944 | /* Initialize identification LED */ | |
945 | ret_val = e1000e_id_led_init(hw); | |
de39b752 | 946 | if (ret_val) |
3bb99fe2 | 947 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 948 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
949 | |
950 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 951 | e_dbg("Initializing the IEEE VLAN\n"); |
bc7f75fa AK |
952 | e1000e_clear_vfta(hw); |
953 | ||
954 | /* Setup the receive address. */ | |
ad68076e BA |
955 | /* |
956 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
957 | * 82571, we must reserve a RAR for it to work around an issue where |
958 | * resetting one port will reload the MAC on the other port. | |
959 | */ | |
960 | if (e1000e_get_laa_state_82571(hw)) | |
961 | rar_count--; | |
962 | e1000e_init_rx_addrs(hw, rar_count); | |
963 | ||
964 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 965 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
966 | for (i = 0; i < mac->mta_reg_count; i++) |
967 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
968 | ||
969 | /* Setup link and flow control */ | |
970 | ret_val = e1000_setup_link_82571(hw); | |
971 | ||
972 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 973 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
974 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
975 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
976 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 977 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
978 | |
979 | /* ...for both queues. */ | |
8c81c9c3 AD |
980 | switch (mac->type) { |
981 | case e1000_82573: | |
982 | case e1000_82574: | |
983 | case e1000_82583: | |
984 | e1000e_enable_tx_pkt_filtering(hw); | |
985 | reg_data = er32(GCR); | |
986 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
987 | ew32(GCR, reg_data); | |
988 | break; | |
989 | default: | |
e9ec2c0f | 990 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
991 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
992 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
993 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 994 | ew32(TXDCTL(1), reg_data); |
8c81c9c3 | 995 | break; |
bc7f75fa AK |
996 | } |
997 | ||
ad68076e BA |
998 | /* |
999 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1000 | * important that we do this after we have tried to establish link |
1001 | * because the symbol error count will increment wildly if there | |
1002 | * is no link. | |
1003 | */ | |
1004 | e1000_clear_hw_cntrs_82571(hw); | |
1005 | ||
1006 | return ret_val; | |
1007 | } | |
1008 | ||
1009 | /** | |
1010 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
1011 | * @hw: pointer to the HW structure | |
1012 | * | |
1013 | * Initializes required hardware-dependent bits needed for normal operation. | |
1014 | **/ | |
1015 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
1016 | { | |
1017 | u32 reg; | |
1018 | ||
1019 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1020 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1021 | reg |= (1 << 22); |
e9ec2c0f | 1022 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1023 | |
1024 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1025 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1026 | reg |= (1 << 22); |
e9ec2c0f | 1027 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1028 | |
1029 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1030 | reg = er32(TARC(0)); |
bc7f75fa AK |
1031 | reg &= ~(0xF << 27); /* 30:27 */ |
1032 | switch (hw->mac.type) { | |
1033 | case e1000_82571: | |
1034 | case e1000_82572: | |
1035 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
1036 | break; | |
1037 | default: | |
1038 | break; | |
1039 | } | |
e9ec2c0f | 1040 | ew32(TARC(0), reg); |
bc7f75fa AK |
1041 | |
1042 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1043 | reg = er32(TARC(1)); |
bc7f75fa AK |
1044 | switch (hw->mac.type) { |
1045 | case e1000_82571: | |
1046 | case e1000_82572: | |
1047 | reg &= ~((1 << 29) | (1 << 30)); | |
1048 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
1049 | if (er32(TCTL) & E1000_TCTL_MULR) | |
1050 | reg &= ~(1 << 28); | |
1051 | else | |
1052 | reg |= (1 << 28); | |
e9ec2c0f | 1053 | ew32(TARC(1), reg); |
bc7f75fa AK |
1054 | break; |
1055 | default: | |
1056 | break; | |
1057 | } | |
1058 | ||
1059 | /* Device Control */ | |
8c81c9c3 AD |
1060 | switch (hw->mac.type) { |
1061 | case e1000_82573: | |
1062 | case e1000_82574: | |
1063 | case e1000_82583: | |
bc7f75fa AK |
1064 | reg = er32(CTRL); |
1065 | reg &= ~(1 << 29); | |
1066 | ew32(CTRL, reg); | |
8c81c9c3 AD |
1067 | break; |
1068 | default: | |
1069 | break; | |
bc7f75fa AK |
1070 | } |
1071 | ||
1072 | /* Extended Device Control */ | |
8c81c9c3 AD |
1073 | switch (hw->mac.type) { |
1074 | case e1000_82573: | |
1075 | case e1000_82574: | |
1076 | case e1000_82583: | |
bc7f75fa AK |
1077 | reg = er32(CTRL_EXT); |
1078 | reg &= ~(1 << 23); | |
1079 | reg |= (1 << 22); | |
1080 | ew32(CTRL_EXT, reg); | |
8c81c9c3 AD |
1081 | break; |
1082 | default: | |
1083 | break; | |
bc7f75fa | 1084 | } |
4662e82b | 1085 | |
6ea7ae1d AD |
1086 | if (hw->mac.type == e1000_82571) { |
1087 | reg = er32(PBA_ECC); | |
1088 | reg |= E1000_PBA_ECC_CORR_EN; | |
1089 | ew32(PBA_ECC, reg); | |
1090 | } | |
5df3f0ea | 1091 | /* |
1092 | * Workaround for hardware errata. | |
1093 | * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 | |
1094 | */ | |
1095 | ||
1096 | if ((hw->mac.type == e1000_82571) || | |
1097 | (hw->mac.type == e1000_82572)) { | |
1098 | reg = er32(CTRL_EXT); | |
1099 | reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; | |
1100 | ew32(CTRL_EXT, reg); | |
1101 | } | |
1102 | ||
6ea7ae1d | 1103 | |
78272bba | 1104 | /* PCI-Ex Control Registers */ |
8c81c9c3 AD |
1105 | switch (hw->mac.type) { |
1106 | case e1000_82574: | |
1107 | case e1000_82583: | |
4662e82b BA |
1108 | reg = er32(GCR); |
1109 | reg |= (1 << 22); | |
1110 | ew32(GCR, reg); | |
78272bba | 1111 | |
84efb7b9 BA |
1112 | /* |
1113 | * Workaround for hardware errata. | |
1114 | * apply workaround for hardware errata documented in errata | |
1115 | * docs Fixes issue where some error prone or unreliable PCIe | |
1116 | * completions are occurring, particularly with ASPM enabled. | |
1117 | * Without fix, issue can cause tx timeouts. | |
1118 | */ | |
78272bba JB |
1119 | reg = er32(GCR2); |
1120 | reg |= 1; | |
1121 | ew32(GCR2, reg); | |
8c81c9c3 AD |
1122 | break; |
1123 | default: | |
1124 | break; | |
4662e82b BA |
1125 | } |
1126 | ||
1127 | return; | |
bc7f75fa AK |
1128 | } |
1129 | ||
1130 | /** | |
1131 | * e1000e_clear_vfta - Clear VLAN filter table | |
1132 | * @hw: pointer to the HW structure | |
1133 | * | |
1134 | * Clears the register array which contains the VLAN filter table by | |
1135 | * setting all the values to 0. | |
1136 | **/ | |
1137 | void e1000e_clear_vfta(struct e1000_hw *hw) | |
1138 | { | |
1139 | u32 offset; | |
1140 | u32 vfta_value = 0; | |
1141 | u32 vfta_offset = 0; | |
1142 | u32 vfta_bit_in_reg = 0; | |
1143 | ||
8c81c9c3 AD |
1144 | switch (hw->mac.type) { |
1145 | case e1000_82573: | |
1146 | case e1000_82574: | |
1147 | case e1000_82583: | |
bc7f75fa | 1148 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1149 | /* |
1150 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1151 | * a single VLAN ID. The following operations |
1152 | * determine which 32b entry (i.e. offset) into the | |
1153 | * array we want to set the VLAN ID (i.e. bit) of | |
1154 | * the manageability unit. | |
1155 | */ | |
1156 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1157 | E1000_VFTA_ENTRY_SHIFT) & | |
1158 | E1000_VFTA_ENTRY_MASK; | |
1159 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1160 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1161 | } | |
8c81c9c3 AD |
1162 | break; |
1163 | default: | |
1164 | break; | |
bc7f75fa AK |
1165 | } |
1166 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1167 | /* |
1168 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1169 | * manageability VLAN ID, then clear all bits except that of |
1170 | * the manageability unit. | |
1171 | */ | |
1172 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1173 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1174 | e1e_flush(); | |
1175 | } | |
1176 | } | |
1177 | ||
4662e82b BA |
1178 | /** |
1179 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1180 | * @hw: pointer to the HW structure | |
1181 | * | |
1182 | * Reads the NVM Initialization Control Word 2 and returns true | |
1183 | * (>0) if any manageability is enabled, else false (0). | |
1184 | **/ | |
1185 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1186 | { | |
1187 | u16 data; | |
1188 | ||
1189 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1190 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1191 | } | |
1192 | ||
1193 | /** | |
1194 | * e1000_led_on_82574 - Turn LED on | |
1195 | * @hw: pointer to the HW structure | |
1196 | * | |
1197 | * Turn LED on. | |
1198 | **/ | |
1199 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1200 | { | |
1201 | u32 ctrl; | |
1202 | u32 i; | |
1203 | ||
1204 | ctrl = hw->mac.ledctl_mode2; | |
1205 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1206 | /* | |
1207 | * If no link, then turn LED on by setting the invert bit | |
1208 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1209 | */ | |
1210 | for (i = 0; i < 4; i++) | |
1211 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1212 | E1000_LEDCTL_MODE_LED_ON) | |
1213 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1214 | } | |
1215 | ew32(LEDCTL, ctrl); | |
1216 | ||
1217 | return 0; | |
1218 | } | |
1219 | ||
bc7f75fa | 1220 | /** |
e2de3eb6 | 1221 | * e1000_update_mc_addr_list_82571 - Update Multicast addresses |
bc7f75fa AK |
1222 | * @hw: pointer to the HW structure |
1223 | * @mc_addr_list: array of multicast addresses to program | |
1224 | * @mc_addr_count: number of multicast addresses to program | |
1225 | * @rar_used_count: the first RAR register free to program | |
1226 | * @rar_count: total number of supported Receive Address Registers | |
1227 | * | |
1228 | * Updates the Receive Address Registers and Multicast Table Array. | |
1229 | * The caller must have a packed mc_addr_list of multicast addresses. | |
1230 | * The parameter rar_count will usually be hw->mac.rar_entry_count | |
1231 | * unless there are workarounds that change this. | |
1232 | **/ | |
e2de3eb6 | 1233 | static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, |
bc7f75fa AK |
1234 | u8 *mc_addr_list, |
1235 | u32 mc_addr_count, | |
1236 | u32 rar_used_count, | |
1237 | u32 rar_count) | |
1238 | { | |
1239 | if (e1000e_get_laa_state_82571(hw)) | |
1240 | rar_count--; | |
1241 | ||
e2de3eb6 JK |
1242 | e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, |
1243 | rar_used_count, rar_count); | |
bc7f75fa AK |
1244 | } |
1245 | ||
1246 | /** | |
1247 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1248 | * @hw: pointer to the HW structure | |
1249 | * | |
1250 | * Determines which flow control settings to use, then configures flow | |
1251 | * control. Calls the appropriate media-specific link configuration | |
1252 | * function. Assuming the adapter has a valid link partner, a valid link | |
1253 | * should be established. Assumes the hardware has previously been reset | |
1254 | * and the transmitter and receiver are not enabled. | |
1255 | **/ | |
1256 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1257 | { | |
ad68076e BA |
1258 | /* |
1259 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1260 | * the default flow control setting, so we explicitly |
1261 | * set it to full. | |
1262 | */ | |
8c81c9c3 AD |
1263 | switch (hw->mac.type) { |
1264 | case e1000_82573: | |
1265 | case e1000_82574: | |
1266 | case e1000_82583: | |
1267 | if (hw->fc.requested_mode == e1000_fc_default) | |
1268 | hw->fc.requested_mode = e1000_fc_full; | |
1269 | break; | |
1270 | default: | |
1271 | break; | |
1272 | } | |
bc7f75fa AK |
1273 | |
1274 | return e1000e_setup_link(hw); | |
1275 | } | |
1276 | ||
1277 | /** | |
1278 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1279 | * @hw: pointer to the HW structure | |
1280 | * | |
1281 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1282 | * for link, once link is established calls to configure collision distance | |
1283 | * and flow control are called. | |
1284 | **/ | |
1285 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1286 | { | |
1287 | u32 ctrl; | |
1288 | u32 led_ctrl; | |
1289 | s32 ret_val; | |
1290 | ||
1291 | ctrl = er32(CTRL); | |
1292 | ctrl |= E1000_CTRL_SLU; | |
1293 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1294 | ew32(CTRL, ctrl); | |
1295 | ||
1296 | switch (hw->phy.type) { | |
1297 | case e1000_phy_m88: | |
4662e82b | 1298 | case e1000_phy_bm: |
bc7f75fa AK |
1299 | ret_val = e1000e_copper_link_setup_m88(hw); |
1300 | break; | |
1301 | case e1000_phy_igp_2: | |
1302 | ret_val = e1000e_copper_link_setup_igp(hw); | |
1303 | /* Setup activity LED */ | |
1304 | led_ctrl = er32(LEDCTL); | |
1305 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
1306 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1307 | ew32(LEDCTL, led_ctrl); | |
1308 | break; | |
1309 | default: | |
1310 | return -E1000_ERR_PHY; | |
1311 | break; | |
1312 | } | |
1313 | ||
1314 | if (ret_val) | |
1315 | return ret_val; | |
1316 | ||
1317 | ret_val = e1000e_setup_copper_link(hw); | |
1318 | ||
1319 | return ret_val; | |
1320 | } | |
1321 | ||
1322 | /** | |
1323 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1324 | * @hw: pointer to the HW structure | |
1325 | * | |
1326 | * Configures collision distance and flow control for fiber and serdes links. | |
1327 | * Upon successful setup, poll for link. | |
1328 | **/ | |
1329 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1330 | { | |
1331 | switch (hw->mac.type) { | |
1332 | case e1000_82571: | |
1333 | case e1000_82572: | |
ad68076e BA |
1334 | /* |
1335 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1336 | * of reset to take the adapter out of that mode. So we |
1337 | * have to explicitly take the adapter out of loopback | |
489815ce | 1338 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1339 | * if another tool failed to take it out of loopback mode. |
1340 | */ | |
ad68076e | 1341 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1342 | break; |
1343 | default: | |
1344 | break; | |
1345 | } | |
1346 | ||
1347 | return e1000e_setup_fiber_serdes_link(hw); | |
1348 | } | |
1349 | ||
c9523379 | 1350 | /** |
1351 | * e1000_check_for_serdes_link_82571 - Check for link (Serdes) | |
1352 | * @hw: pointer to the HW structure | |
1353 | * | |
1354 | * Checks for link up on the hardware. If link is not up and we have | |
1355 | * a signal, then we need to force link up. | |
1356 | **/ | |
f6370117 | 1357 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
c9523379 | 1358 | { |
1359 | struct e1000_mac_info *mac = &hw->mac; | |
1360 | u32 rxcw; | |
1361 | u32 ctrl; | |
1362 | u32 status; | |
1363 | s32 ret_val = 0; | |
1364 | ||
1365 | ctrl = er32(CTRL); | |
1366 | status = er32(STATUS); | |
1367 | rxcw = er32(RXCW); | |
1368 | ||
1369 | if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { | |
1370 | ||
1371 | /* Receiver is synchronized with no invalid bits. */ | |
1372 | switch (mac->serdes_link_state) { | |
1373 | case e1000_serdes_link_autoneg_complete: | |
1374 | if (!(status & E1000_STATUS_LU)) { | |
1375 | /* | |
1376 | * We have lost link, retry autoneg before | |
1377 | * reporting link failure | |
1378 | */ | |
1379 | mac->serdes_link_state = | |
1380 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1381 | e_dbg("AN_UP -> AN_PROG\n"); |
c9523379 | 1382 | } |
1383 | break; | |
1384 | ||
1385 | case e1000_serdes_link_forced_up: | |
1386 | /* | |
1387 | * If we are receiving /C/ ordered sets, re-enable | |
1388 | * auto-negotiation in the TXCW register and disable | |
1389 | * forced link in the Device Control register in an | |
1390 | * attempt to auto-negotiate with our link partner. | |
1391 | */ | |
1392 | if (rxcw & E1000_RXCW_C) { | |
1393 | /* Enable autoneg, and unforce link up */ | |
1394 | ew32(TXCW, mac->txcw); | |
1395 | ew32(CTRL, | |
1396 | (ctrl & ~E1000_CTRL_SLU)); | |
1397 | mac->serdes_link_state = | |
1398 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1399 | e_dbg("FORCED_UP -> AN_PROG\n"); |
c9523379 | 1400 | } |
1401 | break; | |
1402 | ||
1403 | case e1000_serdes_link_autoneg_progress: | |
1404 | /* | |
1405 | * If the LU bit is set in the STATUS register, | |
1406 | * autoneg has completed sucessfully. If not, | |
1407 | * try foring the link because the far end may be | |
1408 | * available but not capable of autonegotiation. | |
1409 | */ | |
1410 | if (status & E1000_STATUS_LU) { | |
1411 | mac->serdes_link_state = | |
1412 | e1000_serdes_link_autoneg_complete; | |
3bb99fe2 | 1413 | e_dbg("AN_PROG -> AN_UP\n"); |
c9523379 | 1414 | } else { |
1415 | /* | |
1416 | * Disable autoneg, force link up and | |
1417 | * full duplex, and change state to forced | |
1418 | */ | |
1419 | ew32(TXCW, | |
1420 | (mac->txcw & ~E1000_TXCW_ANE)); | |
1421 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
1422 | ew32(CTRL, ctrl); | |
1423 | ||
1424 | /* Configure Flow Control after link up. */ | |
1425 | ret_val = | |
1426 | e1000e_config_fc_after_link_up(hw); | |
1427 | if (ret_val) { | |
3bb99fe2 | 1428 | e_dbg("Error config flow control\n"); |
c9523379 | 1429 | break; |
1430 | } | |
1431 | mac->serdes_link_state = | |
1432 | e1000_serdes_link_forced_up; | |
3bb99fe2 | 1433 | e_dbg("AN_PROG -> FORCED_UP\n"); |
c9523379 | 1434 | } |
1435 | mac->serdes_has_link = true; | |
1436 | break; | |
1437 | ||
1438 | case e1000_serdes_link_down: | |
1439 | default: | |
1440 | /* The link was down but the receiver has now gained | |
1441 | * valid sync, so lets see if we can bring the link | |
1442 | * up. */ | |
1443 | ew32(TXCW, mac->txcw); | |
1444 | ew32(CTRL, | |
1445 | (ctrl & ~E1000_CTRL_SLU)); | |
1446 | mac->serdes_link_state = | |
1447 | e1000_serdes_link_autoneg_progress; | |
3bb99fe2 | 1448 | e_dbg("DOWN -> AN_PROG\n"); |
c9523379 | 1449 | break; |
1450 | } | |
1451 | } else { | |
1452 | if (!(rxcw & E1000_RXCW_SYNCH)) { | |
1453 | mac->serdes_has_link = false; | |
1454 | mac->serdes_link_state = e1000_serdes_link_down; | |
3bb99fe2 | 1455 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1456 | } else { |
1457 | /* | |
1458 | * We have sync, and can tolerate one | |
1459 | * invalid (IV) codeword before declaring | |
1460 | * link down, so reread to look again | |
1461 | */ | |
1462 | udelay(10); | |
1463 | rxcw = er32(RXCW); | |
1464 | if (rxcw & E1000_RXCW_IV) { | |
1465 | mac->serdes_link_state = e1000_serdes_link_down; | |
1466 | mac->serdes_has_link = false; | |
3bb99fe2 | 1467 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1468 | } |
1469 | } | |
1470 | } | |
1471 | ||
1472 | return ret_val; | |
1473 | } | |
1474 | ||
bc7f75fa AK |
1475 | /** |
1476 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1477 | * @hw: pointer to the HW structure | |
1478 | * @data: pointer to the NVM (EEPROM) | |
1479 | * | |
1480 | * Read the EEPROM for the current default LED configuration. If the | |
1481 | * LED configuration is not valid, set to a valid LED configuration. | |
1482 | **/ | |
1483 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1484 | { | |
1485 | s32 ret_val; | |
1486 | ||
1487 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1488 | if (ret_val) { | |
3bb99fe2 | 1489 | e_dbg("NVM Read Error\n"); |
bc7f75fa AK |
1490 | return ret_val; |
1491 | } | |
1492 | ||
8c81c9c3 AD |
1493 | switch (hw->mac.type) { |
1494 | case e1000_82573: | |
1495 | case e1000_82574: | |
1496 | case e1000_82583: | |
1497 | if (*data == ID_LED_RESERVED_F746) | |
1498 | *data = ID_LED_DEFAULT_82573; | |
1499 | break; | |
1500 | default: | |
1501 | if (*data == ID_LED_RESERVED_0000 || | |
1502 | *data == ID_LED_RESERVED_FFFF) | |
1503 | *data = ID_LED_DEFAULT; | |
1504 | break; | |
1505 | } | |
bc7f75fa AK |
1506 | |
1507 | return 0; | |
1508 | } | |
1509 | ||
1510 | /** | |
1511 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1512 | * @hw: pointer to the HW structure | |
1513 | * | |
489815ce | 1514 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1515 | **/ |
1516 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1517 | { | |
1518 | if (hw->mac.type != e1000_82571) | |
564ea9bb | 1519 | return false; |
bc7f75fa AK |
1520 | |
1521 | return hw->dev_spec.e82571.laa_is_present; | |
1522 | } | |
1523 | ||
1524 | /** | |
1525 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1526 | * @hw: pointer to the HW structure | |
1527 | * @state: enable/disable locally administered address | |
1528 | * | |
489815ce | 1529 | * Enable/Disable the current locally administers address state. |
bc7f75fa AK |
1530 | **/ |
1531 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1532 | { | |
1533 | if (hw->mac.type != e1000_82571) | |
1534 | return; | |
1535 | ||
1536 | hw->dev_spec.e82571.laa_is_present = state; | |
1537 | ||
1538 | /* If workaround is activated... */ | |
1539 | if (state) | |
ad68076e BA |
1540 | /* |
1541 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1542 | * between the time RAR[0] gets clobbered and the time it |
1543 | * gets fixed, the actual LAA is in one of the RARs and no | |
1544 | * incoming packets directed to this port are dropped. | |
1545 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1546 | */ | |
1547 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1548 | } | |
1549 | ||
1550 | /** | |
1551 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1552 | * @hw: pointer to the HW structure | |
1553 | * | |
1554 | * Verifies that the EEPROM has completed the update. After updating the | |
1555 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1556 | * the checksum fix is not implemented, we need to set the bit and update | |
1557 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1558 | * we need to return bad checksum. | |
1559 | **/ | |
1560 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1561 | { | |
1562 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1563 | s32 ret_val; | |
1564 | u16 data; | |
1565 | ||
1566 | if (nvm->type != e1000_nvm_flash_hw) | |
1567 | return 0; | |
1568 | ||
ad68076e BA |
1569 | /* |
1570 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1571 | * 10h-12h. Checksum may need to be fixed. |
1572 | */ | |
1573 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1574 | if (ret_val) | |
1575 | return ret_val; | |
1576 | ||
1577 | if (!(data & 0x10)) { | |
ad68076e BA |
1578 | /* |
1579 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1580 | * when the checksum has already been fixed. If |
1581 | * the checksum is still wrong and this bit is a | |
1582 | * 1, we need to return bad checksum. Otherwise, | |
1583 | * we need to set this bit to a 1 and update the | |
1584 | * checksum. | |
1585 | */ | |
1586 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1587 | if (ret_val) | |
1588 | return ret_val; | |
1589 | ||
1590 | if (!(data & 0x8000)) { | |
1591 | data |= 0x8000; | |
1592 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1593 | if (ret_val) | |
1594 | return ret_val; | |
1595 | ret_val = e1000e_update_nvm_checksum(hw); | |
1596 | } | |
1597 | } | |
1598 | ||
1599 | return 0; | |
1600 | } | |
1601 | ||
1602 | /** | |
1603 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1604 | * @hw: pointer to the HW structure | |
1605 | * | |
1606 | * Clears the hardware counters by reading the counter registers. | |
1607 | **/ | |
1608 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1609 | { | |
bc7f75fa AK |
1610 | e1000e_clear_hw_cntrs_base(hw); |
1611 | ||
99673d9b BA |
1612 | er32(PRC64); |
1613 | er32(PRC127); | |
1614 | er32(PRC255); | |
1615 | er32(PRC511); | |
1616 | er32(PRC1023); | |
1617 | er32(PRC1522); | |
1618 | er32(PTC64); | |
1619 | er32(PTC127); | |
1620 | er32(PTC255); | |
1621 | er32(PTC511); | |
1622 | er32(PTC1023); | |
1623 | er32(PTC1522); | |
1624 | ||
1625 | er32(ALGNERRC); | |
1626 | er32(RXERRC); | |
1627 | er32(TNCRS); | |
1628 | er32(CEXTERR); | |
1629 | er32(TSCTC); | |
1630 | er32(TSCTFC); | |
1631 | ||
1632 | er32(MGTPRC); | |
1633 | er32(MGTPDC); | |
1634 | er32(MGTPTC); | |
1635 | ||
1636 | er32(IAC); | |
1637 | er32(ICRXOC); | |
1638 | ||
1639 | er32(ICRXPTC); | |
1640 | er32(ICRXATC); | |
1641 | er32(ICTXPTC); | |
1642 | er32(ICTXATC); | |
1643 | er32(ICTXQEC); | |
1644 | er32(ICTXQMTC); | |
1645 | er32(ICRXDMTC); | |
bc7f75fa AK |
1646 | } |
1647 | ||
1648 | static struct e1000_mac_operations e82571_mac_ops = { | |
4662e82b | 1649 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa | 1650 | /* .check_for_link: media type dependent */ |
a4f58f54 | 1651 | .id_led_init = e1000e_id_led_init, |
bc7f75fa AK |
1652 | .cleanup_led = e1000e_cleanup_led_generic, |
1653 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1654 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1655 | /* .get_link_up_info: media type dependent */ | |
4662e82b | 1656 | /* .led_on: mac type dependent */ |
bc7f75fa | 1657 | .led_off = e1000e_led_off_generic, |
e2de3eb6 | 1658 | .update_mc_addr_list = e1000_update_mc_addr_list_82571, |
bc7f75fa AK |
1659 | .reset_hw = e1000_reset_hw_82571, |
1660 | .init_hw = e1000_init_hw_82571, | |
1661 | .setup_link = e1000_setup_link_82571, | |
1662 | /* .setup_physical_interface: media type dependent */ | |
a4f58f54 | 1663 | .setup_led = e1000e_setup_led_generic, |
bc7f75fa AK |
1664 | }; |
1665 | ||
1666 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
94d8186a | 1667 | .acquire = e1000_get_hw_semaphore_82571, |
bc7f75fa | 1668 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1669 | .commit = NULL, |
bc7f75fa AK |
1670 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
1671 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1672 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
94d8186a BA |
1673 | .get_info = e1000e_get_phy_info_igp, |
1674 | .read_reg = e1000e_read_phy_reg_igp, | |
1675 | .release = e1000_put_hw_semaphore_82571, | |
1676 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1677 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1678 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1679 | .write_reg = e1000e_write_phy_reg_igp, |
75eb0fad | 1680 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1681 | }; |
1682 | ||
1683 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
94d8186a | 1684 | .acquire = e1000_get_hw_semaphore_82571, |
bc7f75fa | 1685 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1686 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1687 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1688 | .get_cfg_done = e1000e_get_cfg_done, | |
1689 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1690 | .get_info = e1000e_get_phy_info_m88, |
1691 | .read_reg = e1000e_read_phy_reg_m88, | |
1692 | .release = e1000_put_hw_semaphore_82571, | |
1693 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1694 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1695 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1696 | .write_reg = e1000e_write_phy_reg_m88, |
75eb0fad | 1697 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1698 | }; |
1699 | ||
4662e82b | 1700 | static struct e1000_phy_operations e82_phy_ops_bm = { |
94d8186a | 1701 | .acquire = e1000_get_hw_semaphore_82571, |
4662e82b | 1702 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1703 | .commit = e1000e_phy_sw_reset, |
4662e82b BA |
1704 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1705 | .get_cfg_done = e1000e_get_cfg_done, | |
1706 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1707 | .get_info = e1000e_get_phy_info_m88, |
1708 | .read_reg = e1000e_read_phy_reg_bm2, | |
1709 | .release = e1000_put_hw_semaphore_82571, | |
1710 | .reset = e1000e_phy_hw_reset_generic, | |
4662e82b BA |
1711 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1712 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1713 | .write_reg = e1000e_write_phy_reg_bm2, |
75eb0fad | 1714 | .cfg_on_link_up = NULL, |
4662e82b BA |
1715 | }; |
1716 | ||
bc7f75fa | 1717 | static struct e1000_nvm_operations e82571_nvm_ops = { |
94d8186a BA |
1718 | .acquire = e1000_acquire_nvm_82571, |
1719 | .read = e1000e_read_nvm_eerd, | |
1720 | .release = e1000_release_nvm_82571, | |
1721 | .update = e1000_update_nvm_checksum_82571, | |
bc7f75fa | 1722 | .valid_led_default = e1000_valid_led_default_82571, |
94d8186a BA |
1723 | .validate = e1000_validate_nvm_checksum_82571, |
1724 | .write = e1000_write_nvm_82571, | |
bc7f75fa AK |
1725 | }; |
1726 | ||
1727 | struct e1000_info e1000_82571_info = { | |
1728 | .mac = e1000_82571, | |
1729 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1730 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1731 | | FLAG_HAS_WOL |
1732 | | FLAG_APME_IN_CTRL3 | |
1733 | | FLAG_RX_CSUM_ENABLED | |
1734 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1735 | | FLAG_HAS_SMART_POWER_DOWN |
1736 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1737 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1738 | | FLAG_APME_CHECK_PORT_B, | |
1739 | .pba = 38, | |
2adc55c9 | 1740 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1741 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1742 | .mac_ops = &e82571_mac_ops, |
1743 | .phy_ops = &e82_phy_ops_igp, | |
1744 | .nvm_ops = &e82571_nvm_ops, | |
1745 | }; | |
1746 | ||
1747 | struct e1000_info e1000_82572_info = { | |
1748 | .mac = e1000_82572, | |
1749 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1750 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1751 | | FLAG_HAS_WOL |
1752 | | FLAG_APME_IN_CTRL3 | |
1753 | | FLAG_RX_CSUM_ENABLED | |
1754 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1755 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
1756 | .pba = 38, | |
2adc55c9 | 1757 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1758 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1759 | .mac_ops = &e82571_mac_ops, |
1760 | .phy_ops = &e82_phy_ops_igp, | |
1761 | .nvm_ops = &e82571_nvm_ops, | |
1762 | }; | |
1763 | ||
1764 | struct e1000_info e1000_82573_info = { | |
1765 | .mac = e1000_82573, | |
1766 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1767 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1768 | | FLAG_HAS_WOL |
1769 | | FLAG_APME_IN_CTRL3 | |
1770 | | FLAG_RX_CSUM_ENABLED | |
bc7f75fa AK |
1771 | | FLAG_HAS_SMART_POWER_DOWN |
1772 | | FLAG_HAS_AMT | |
bc7f75fa AK |
1773 | | FLAG_HAS_ERT |
1774 | | FLAG_HAS_SWSM_ON_LOAD, | |
1775 | .pba = 20, | |
2adc55c9 | 1776 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 1777 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1778 | .mac_ops = &e82571_mac_ops, |
1779 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 1780 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
1781 | }; |
1782 | ||
4662e82b BA |
1783 | struct e1000_info e1000_82574_info = { |
1784 | .mac = e1000_82574, | |
1785 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1786 | | FLAG_HAS_MSIX | |
1787 | | FLAG_HAS_JUMBO_FRAMES | |
1788 | | FLAG_HAS_WOL | |
1789 | | FLAG_APME_IN_CTRL3 | |
1790 | | FLAG_RX_CSUM_ENABLED | |
1791 | | FLAG_HAS_SMART_POWER_DOWN | |
1792 | | FLAG_HAS_AMT | |
1793 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1794 | .pba = 20, | |
a825e00c | 1795 | .max_hw_frame_size = DEFAULT_JUMBO, |
4662e82b BA |
1796 | .get_variants = e1000_get_variants_82571, |
1797 | .mac_ops = &e82571_mac_ops, | |
1798 | .phy_ops = &e82_phy_ops_bm, | |
1799 | .nvm_ops = &e82571_nvm_ops, | |
1800 | }; | |
1801 | ||
8c81c9c3 AD |
1802 | struct e1000_info e1000_82583_info = { |
1803 | .mac = e1000_82583, | |
1804 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1805 | | FLAG_HAS_WOL | |
1806 | | FLAG_APME_IN_CTRL3 | |
1807 | | FLAG_RX_CSUM_ENABLED | |
1808 | | FLAG_HAS_SMART_POWER_DOWN | |
1809 | | FLAG_HAS_AMT | |
1810 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1811 | .pba = 20, | |
a825e00c | 1812 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
8c81c9c3 AD |
1813 | .get_variants = e1000_get_variants_82571, |
1814 | .mac_ops = &e82571_mac_ops, | |
1815 | .phy_ops = &e82_phy_ops_bm, | |
1816 | .nvm_ops = &e82571_nvm_ops, | |
1817 | }; | |
1818 |