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e1000: FIX: firmware handover bits
[linux-2.6-block.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
d0bb53e1 30#include <net/ip6_checksum.h>
1da177e4 31
1da177e4 32char e1000_driver_name[] = "e1000";
3ad2cc67 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 34#ifndef CONFIG_E1000_NAPI
35#define DRIVERNAPI
36#else
37#define DRIVERNAPI "-NAPI"
38#endif
7e721579 39#define DRV_VERSION "7.3.20-k2"DRIVERNAPI
1da177e4 40char e1000_driver_version[] = DRV_VERSION;
3d41e30a 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
1da177e4
LT		 42
43/* e1000_pci_tbl - PCI Device ID Table
44 *
45 * Last entry must be all 0s
46 *
47 * Macro expands to...
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */
50static struct pci_device_id e1000_pci_tbl[] = {
51 INTEL_E1000_ETHERNET_DEVICE(0x1000),
52 INTEL_E1000_ETHERNET_DEVICE(0x1001),
53 INTEL_E1000_ETHERNET_DEVICE(0x1004),
54 INTEL_E1000_ETHERNET_DEVICE(0x1008),
55 INTEL_E1000_ETHERNET_DEVICE(0x1009),
56 INTEL_E1000_ETHERNET_DEVICE(0x100C),
57 INTEL_E1000_ETHERNET_DEVICE(0x100D),
58 INTEL_E1000_ETHERNET_DEVICE(0x100E),
59 INTEL_E1000_ETHERNET_DEVICE(0x100F),
60 INTEL_E1000_ETHERNET_DEVICE(0x1010),
61 INTEL_E1000_ETHERNET_DEVICE(0x1011),
62 INTEL_E1000_ETHERNET_DEVICE(0x1012),
63 INTEL_E1000_ETHERNET_DEVICE(0x1013),
64 INTEL_E1000_ETHERNET_DEVICE(0x1014),
65 INTEL_E1000_ETHERNET_DEVICE(0x1015),
66 INTEL_E1000_ETHERNET_DEVICE(0x1016),
67 INTEL_E1000_ETHERNET_DEVICE(0x1017),
68 INTEL_E1000_ETHERNET_DEVICE(0x1018),
69 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 70 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 71 INTEL_E1000_ETHERNET_DEVICE(0x101D),
72 INTEL_E1000_ETHERNET_DEVICE(0x101E),
73 INTEL_E1000_ETHERNET_DEVICE(0x1026),
74 INTEL_E1000_ETHERNET_DEVICE(0x1027),
75 INTEL_E1000_ETHERNET_DEVICE(0x1028),
ae2c3860
AK		 76 INTEL_E1000_ETHERNET_DEVICE(0x1049),
77 INTEL_E1000_ETHERNET_DEVICE(0x104A),
78 INTEL_E1000_ETHERNET_DEVICE(0x104B),
79 INTEL_E1000_ETHERNET_DEVICE(0x104C),
80 INTEL_E1000_ETHERNET_DEVICE(0x104D),
07b8fede
MC		 81 INTEL_E1000_ETHERNET_DEVICE(0x105E),
82 INTEL_E1000_ETHERNET_DEVICE(0x105F),
83 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 84 INTEL_E1000_ETHERNET_DEVICE(0x1075),
85 INTEL_E1000_ETHERNET_DEVICE(0x1076),
86 INTEL_E1000_ETHERNET_DEVICE(0x1077),
87 INTEL_E1000_ETHERNET_DEVICE(0x1078),
88 INTEL_E1000_ETHERNET_DEVICE(0x1079),
89 INTEL_E1000_ETHERNET_DEVICE(0x107A),
90 INTEL_E1000_ETHERNET_DEVICE(0x107B),
91 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 92 INTEL_E1000_ETHERNET_DEVICE(0x107D),
93 INTEL_E1000_ETHERNET_DEVICE(0x107E),
94 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 95 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 96 INTEL_E1000_ETHERNET_DEVICE(0x108B),
97 INTEL_E1000_ETHERNET_DEVICE(0x108C),
6418ecc6
JK		 98 INTEL_E1000_ETHERNET_DEVICE(0x1096),
99 INTEL_E1000_ETHERNET_DEVICE(0x1098),
b7ee49db 100 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 101 INTEL_E1000_ETHERNET_DEVICE(0x109A),
5881cde8 102 INTEL_E1000_ETHERNET_DEVICE(0x10A4),
b7ee49db 103 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
6418ecc6 104 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
ae2c3860
AK		 105 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
106 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
fc2307d0
AK		 107 INTEL_E1000_ETHERNET_DEVICE(0x10BC),
108 INTEL_E1000_ETHERNET_DEVICE(0x10C4),
109 INTEL_E1000_ETHERNET_DEVICE(0x10C5),
1da177e4
LT		 110 /* required last entry */
111 {0,}
112};
113
114MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
115
35574764
NN		 116int e1000_up(struct e1000_adapter *adapter);
117void e1000_down(struct e1000_adapter *adapter);
118void e1000_reinit_locked(struct e1000_adapter *adapter);
119void e1000_reset(struct e1000_adapter *adapter);
120int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
121int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
122int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
123void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
124void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67 125static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
35574764 126 struct e1000_tx_ring *txdr);
3ad2cc67 127static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
35574764 128 struct e1000_rx_ring *rxdr);
3ad2cc67 129static void e1000_free_tx_resources(struct e1000_adapter *adapter,
35574764 130 struct e1000_tx_ring *tx_ring);
3ad2cc67 131static void e1000_free_rx_resources(struct e1000_adapter *adapter,
35574764
NN		 132 struct e1000_rx_ring *rx_ring);
133void e1000_update_stats(struct e1000_adapter *adapter);
1da177e4
LT		 134
135static int e1000_init_module(void);
136static void e1000_exit_module(void);
137static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
138static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 139static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 140static int e1000_sw_init(struct e1000_adapter *adapter);
141static int e1000_open(struct net_device *netdev);
142static int e1000_close(struct net_device *netdev);
143static void e1000_configure_tx(struct e1000_adapter *adapter);
144static void e1000_configure_rx(struct e1000_adapter *adapter);
145static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 146static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
147static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
148static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
149 struct e1000_tx_ring *tx_ring);
150static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
151 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 152static void e1000_set_multi(struct net_device *netdev);
153static void e1000_update_phy_info(unsigned long data);
154static void e1000_watchdog(unsigned long data);
1da177e4
LT		 155static void e1000_82547_tx_fifo_stall(unsigned long data);
156static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
157static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
158static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
159static int e1000_set_mac(struct net_device *netdev, void *p);
7d12e780 160static irqreturn_t e1000_intr(int irq, void *data);
9ac98284
JB		 161#ifdef CONFIG_PCI_MSI
162static irqreturn_t e1000_intr_msi(int irq, void *data);
163#endif
581d708e
MC		 164static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
165 struct e1000_tx_ring *tx_ring);
1da177e4 166#ifdef CONFIG_E1000_NAPI
581d708e 167static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 168static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 169 struct e1000_rx_ring *rx_ring,
1da177e4 170 int *work_done, int work_to_do);
2d7edb92 171static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 172 struct e1000_rx_ring *rx_ring,
2d7edb92 173 int *work_done, int work_to_do);
1da177e4 174#else
581d708e
MC		 175static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
176 struct e1000_rx_ring *rx_ring);
177static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
178 struct e1000_rx_ring *rx_ring);
1da177e4 179#endif
581d708e 180static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 181 struct e1000_rx_ring *rx_ring,
182 int cleaned_count);
581d708e 183static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 184 struct e1000_rx_ring *rx_ring,
185 int cleaned_count);
1da177e4
LT		 186static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
187static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
188 int cmd);
35574764 189void e1000_set_ethtool_ops(struct net_device *netdev);
1da177e4
LT		 190static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
191static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
192static void e1000_tx_timeout(struct net_device *dev);
65f27f38 193static void e1000_reset_task(struct work_struct *work);
1da177e4 194static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 195static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
196 struct sk_buff *skb);
1da177e4
LT		 197
198static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
199static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
200static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
201static void e1000_restore_vlan(struct e1000_adapter *adapter);
202
977e74b5 203static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
6fdfef16 204#ifdef CONFIG_PM
1da177e4
LT		 205static int e1000_resume(struct pci_dev *pdev);
206#endif
c653e635 207static void e1000_shutdown(struct pci_dev *pdev);
1da177e4
LT		 208
209#ifdef CONFIG_NET_POLL_CONTROLLER
210/* for netdump / net console */
211static void e1000_netpoll (struct net_device *netdev);
212#endif
213
35574764
NN		 214extern void e1000_check_options(struct e1000_adapter *adapter);
215
1f753861
JB		 216#define COPYBREAK_DEFAULT 256
217static unsigned int copybreak __read_mostly = COPYBREAK_DEFAULT;
218module_param(copybreak, uint, 0644);
219MODULE_PARM_DESC(copybreak,
220 "Maximum size of packet that is copied to a new buffer on receive");
221
9026729b
AK		 222static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
223 pci_channel_state_t state);
224static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
225static void e1000_io_resume(struct pci_dev *pdev);
226
227static struct pci_error_handlers e1000_err_handler = {
228 .error_detected = e1000_io_error_detected,
229 .slot_reset = e1000_io_slot_reset,
230 .resume = e1000_io_resume,
231};
24025e4e 232
1da177e4
LT		 233static struct pci_driver e1000_driver = {
234 .name = e1000_driver_name,
235 .id_table = e1000_pci_tbl,
236 .probe = e1000_probe,
237 .remove = __devexit_p(e1000_remove),
c4e24f01 238#ifdef CONFIG_PM
1da177e4 239 /* Power Managment Hooks */
1da177e4 240 .suspend = e1000_suspend,
c653e635 241 .resume = e1000_resume,
1da177e4 242#endif
9026729b
AK		 243 .shutdown = e1000_shutdown,
244 .err_handler = &e1000_err_handler
1da177e4
LT		 245};
246
247MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
248MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
249MODULE_LICENSE("GPL");
250MODULE_VERSION(DRV_VERSION);
251
252static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
256/**
257 * e1000_init_module - Driver Registration Routine
258 *
259 * e1000_init_module is the first routine called when the driver is
260 * loaded. All it does is register with the PCI subsystem.
261 **/
262
263static int __init
264e1000_init_module(void)
265{
266 int ret;
267 printk(KERN_INFO "%s - version %s\n",
268 e1000_driver_string, e1000_driver_version);
269
270 printk(KERN_INFO "%s\n", e1000_copyright);
271
29917620 272 ret = pci_register_driver(&e1000_driver);
1f753861
JB		 273 if (copybreak != COPYBREAK_DEFAULT) {
274 if (copybreak == 0)
275 printk(KERN_INFO "e1000: copybreak disabled\n");
276 else
277 printk(KERN_INFO "e1000: copybreak enabled for "
278 "packets <= %u bytes\n", copybreak);
279 }
1da177e4
LT		 280 return ret;
281}
282
283module_init(e1000_init_module);
284
285/**
286 * e1000_exit_module - Driver Exit Cleanup Routine
287 *
288 * e1000_exit_module is called just before the driver is removed
289 * from memory.
290 **/
291
292static void __exit
293e1000_exit_module(void)
294{
1da177e4
LT		 295 pci_unregister_driver(&e1000_driver);
296}
297
298module_exit(e1000_exit_module);
299
2db10a08
AK		 300static int e1000_request_irq(struct e1000_adapter *adapter)
301{
302 struct net_device *netdev = adapter->netdev;
303 int flags, err = 0;
304
c0bc8721 305 flags = IRQF_SHARED;
2db10a08 306#ifdef CONFIG_PCI_MSI
9ac98284 307 if (adapter->hw.mac_type >= e1000_82571) {
2db10a08
AK		 308 adapter->have_msi = TRUE;
309 if ((err = pci_enable_msi(adapter->pdev))) {
310 DPRINTK(PROBE, ERR,
311 "Unable to allocate MSI interrupt Error: %d\n", err);
312 adapter->have_msi = FALSE;
313 }
314 }
9ac98284 315 if (adapter->have_msi) {
61ef5c00 316 flags &= ~IRQF_SHARED;
9ac98284
JB		 317 err = request_irq(adapter->pdev->irq, &e1000_intr_msi, flags,
318 netdev->name, netdev);
319 if (err)
320 DPRINTK(PROBE, ERR,
321 "Unable to allocate interrupt Error: %d\n", err);
322 } else
2db10a08
AK		 323#endif
324 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags,
325 netdev->name, netdev)))
326 DPRINTK(PROBE, ERR,
327 "Unable to allocate interrupt Error: %d\n", err);
328
329 return err;
330}
331
332static void e1000_free_irq(struct e1000_adapter *adapter)
333{
334 struct net_device *netdev = adapter->netdev;
335
336 free_irq(adapter->pdev->irq, netdev);
337
338#ifdef CONFIG_PCI_MSI
339 if (adapter->have_msi)
340 pci_disable_msi(adapter->pdev);
341#endif
342}
343
1da177e4
LT		 344/**
345 * e1000_irq_disable - Mask off interrupt generation on the NIC
346 * @adapter: board private structure
347 **/
348
e619d523 349static void
1da177e4
LT		 350e1000_irq_disable(struct e1000_adapter *adapter)
351{
352 atomic_inc(&adapter->irq_sem);
353 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
354 E1000_WRITE_FLUSH(&adapter->hw);
355 synchronize_irq(adapter->pdev->irq);
356}
357
358/**
359 * e1000_irq_enable - Enable default interrupt generation settings
360 * @adapter: board private structure
361 **/
362
e619d523 363static void
1da177e4
LT		 364e1000_irq_enable(struct e1000_adapter *adapter)
365{
96838a40 366 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 367 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
368 E1000_WRITE_FLUSH(&adapter->hw);
369 }
370}
3ad2cc67
AB		 371
372static void
2d7edb92
MC		 373e1000_update_mng_vlan(struct e1000_adapter *adapter)
374{
375 struct net_device *netdev = adapter->netdev;
376 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
377 uint16_t old_vid = adapter->mng_vlan_id;
96838a40 378 if (adapter->vlgrp) {
5c15bdec 379 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
96838a40 380 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 381 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
382 e1000_vlan_rx_add_vid(netdev, vid);
383 adapter->mng_vlan_id = vid;
384 } else
385 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 386
387 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
388 (vid != old_vid) &&
5c15bdec 389 !vlan_group_get_device(adapter->vlgrp, old_vid))
2d7edb92 390 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 391 } else
392 adapter->mng_vlan_id = vid;
2d7edb92
MC		 393 }
394}
b55ccb35
JK		 395
396/**
397 * e1000_release_hw_control - release control of the h/w to f/w
398 * @adapter: address of board private structure
399 *
400 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
401 * For ASF and Pass Through versions of f/w this means that the
402 * driver is no longer loaded. For AMT version (only with 82573) i
90fb5135 403 * of the f/w this means that the network i/f is closed.
76c224bc 404 *
b55ccb35
JK		 405 **/
406
e619d523 407static void
b55ccb35
JK		 408e1000_release_hw_control(struct e1000_adapter *adapter)
409{
410 uint32_t ctrl_ext;
411 uint32_t swsm;
412
413 /* Let firmware taken over control of h/w */
414 switch (adapter->hw.mac_type) {
b55ccb35
JK		 415 case e1000_82573:
416 swsm = E1000_READ_REG(&adapter->hw, SWSM);
417 E1000_WRITE_REG(&adapter->hw, SWSM,
418 swsm & ~E1000_SWSM_DRV_LOAD);
31d76442
BA		 419 break;
420 case e1000_82571:
421 case e1000_82572:
422 case e1000_80003es2lan:
cd94dd0b 423 case e1000_ich8lan:
31d76442 424 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
cd94dd0b 425 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
31d76442 426 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
cd94dd0b 427 break;
b55ccb35
JK		 428 default:
429 break;
430 }
431}
432
433/**
434 * e1000_get_hw_control - get control of the h/w from f/w
435 * @adapter: address of board private structure
436 *
437 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
76c224bc
AK		 438 * For ASF and Pass Through versions of f/w this means that
439 * the driver is loaded. For AMT version (only with 82573)
90fb5135 440 * of the f/w this means that the network i/f is open.
76c224bc 441 *
b55ccb35
JK		 442 **/
443
e619d523 444static void
b55ccb35
JK		 445e1000_get_hw_control(struct e1000_adapter *adapter)
446{
447 uint32_t ctrl_ext;
448 uint32_t swsm;
90fb5135 449
b55ccb35
JK		 450 /* Let firmware know the driver has taken over */
451 switch (adapter->hw.mac_type) {
b55ccb35
JK		 452 case e1000_82573:
453 swsm = E1000_READ_REG(&adapter->hw, SWSM);
454 E1000_WRITE_REG(&adapter->hw, SWSM,
455 swsm | E1000_SWSM_DRV_LOAD);
456 break;
31d76442
BA		 457 case e1000_82571:
458 case e1000_82572:
459 case e1000_80003es2lan:
cd94dd0b 460 case e1000_ich8lan:
31d76442
BA		 461 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
462 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
463 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
cd94dd0b 464 break;
b55ccb35
JK		 465 default:
466 break;
467 }
468}
469
0fccd0e9
JG		 470static void
471e1000_init_manageability(struct e1000_adapter *adapter)
472{
473 if (adapter->en_mng_pt) {
474 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC);
475
476 /* disable hardware interception of ARP */
477 manc &= ~(E1000_MANC_ARP_EN);
478
479 /* enable receiving management packets to the host */
480 /* this will probably generate destination unreachable messages
481 * from the host OS, but the packets will be handled on SMBUS */
482 if (adapter->hw.has_manc2h) {
483 uint32_t manc2h = E1000_READ_REG(&adapter->hw, MANC2H);
484
485 manc |= E1000_MANC_EN_MNG2HOST;
486#define E1000_MNG2HOST_PORT_623 (1 << 5)
487#define E1000_MNG2HOST_PORT_664 (1 << 6)
488 manc2h |= E1000_MNG2HOST_PORT_623;
489 manc2h |= E1000_MNG2HOST_PORT_664;
490 E1000_WRITE_REG(&adapter->hw, MANC2H, manc2h);
491 }
492
493 E1000_WRITE_REG(&adapter->hw, MANC, manc);
494 }
495}
496
497static void
498e1000_release_manageability(struct e1000_adapter *adapter)
499{
500 if (adapter->en_mng_pt) {
501 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC);
502
503 /* re-enable hardware interception of ARP */
504 manc |= E1000_MANC_ARP_EN;
505
506 if (adapter->hw.has_manc2h)
507 manc &= ~E1000_MANC_EN_MNG2HOST;
508
509 /* don't explicitly have to mess with MANC2H since
510 * MANC has an enable disable that gates MANC2H */
511
512 E1000_WRITE_REG(&adapter->hw, MANC, manc);
513 }
514}
515
e0aac5a2
AK		 516/**
517 * e1000_configure - configure the hardware for RX and TX
518 * @adapter = private board structure
519 **/
520static void e1000_configure(struct e1000_adapter *adapter)
1da177e4
LT		 521{
522 struct net_device *netdev = adapter->netdev;
2db10a08 523 int i;
1da177e4 524
1da177e4
LT		 525 e1000_set_multi(netdev);
526
527 e1000_restore_vlan(adapter);
0fccd0e9 528 e1000_init_manageability(adapter);
1da177e4
LT		 529
530 e1000_configure_tx(adapter);
531 e1000_setup_rctl(adapter);
532 e1000_configure_rx(adapter);
72d64a43
JK		 533 /* call E1000_DESC_UNUSED which always leaves
534 * at least 1 descriptor unused to make sure
535 * next_to_use != next_to_clean */
f56799ea 536 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 537 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 538 adapter->alloc_rx_buf(adapter, ring,
539 E1000_DESC_UNUSED(ring));
f56799ea 540 }
1da177e4 541
7bfa4816 542 adapter->tx_queue_len = netdev->tx_queue_len;
e0aac5a2
AK		 543}
544
545int e1000_up(struct e1000_adapter *adapter)
546{
547 /* hardware has been reset, we need to reload some things */
548 e1000_configure(adapter);
549
550 clear_bit(__E1000_DOWN, &adapter->flags);
7bfa4816 551
1da177e4 552#ifdef CONFIG_E1000_NAPI
e0aac5a2 553 netif_poll_enable(adapter->netdev);
1da177e4 554#endif
5de55624
MC		 555 e1000_irq_enable(adapter);
556
79f3d399
JB		 557 /* fire a link change interrupt to start the watchdog */
558 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1da177e4
LT		 559 return 0;
560}
561
79f05bf0
AK		 562/**
563 * e1000_power_up_phy - restore link in case the phy was powered down
564 * @adapter: address of board private structure
565 *
566 * The phy may be powered down to save power and turn off link when the
567 * driver is unloaded and wake on lan is not enabled (among others)
568 * *** this routine MUST be followed by a call to e1000_reset ***
569 *
570 **/
571
d658266e 572void e1000_power_up_phy(struct e1000_adapter *adapter)
79f05bf0
AK		 573{
574 uint16_t mii_reg = 0;
575
576 /* Just clear the power down bit to wake the phy back up */
577 if (adapter->hw.media_type == e1000_media_type_copper) {
578 /* according to the manual, the phy will retain its
579 * settings across a power-down/up cycle */
580 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
581 mii_reg &= ~MII_CR_POWER_DOWN;
582 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
583 }
584}
585
586static void e1000_power_down_phy(struct e1000_adapter *adapter)
587{
61c2505f
BA		 588 /* Power down the PHY so no link is implied when interface is down *
589 * The PHY cannot be powered down if any of the following is TRUE *
79f05bf0
AK		 590 * (a) WoL is enabled
591 * (b) AMT is active
592 * (c) SoL/IDER session is active */
593 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
61c2505f 594 adapter->hw.media_type == e1000_media_type_copper) {
79f05bf0 595 uint16_t mii_reg = 0;
61c2505f
BA		 596
597 switch (adapter->hw.mac_type) {
598 case e1000_82540:
599 case e1000_82545:
600 case e1000_82545_rev_3:
601 case e1000_82546:
602 case e1000_82546_rev_3:
603 case e1000_82541:
604 case e1000_82541_rev_2:
605 case e1000_82547:
606 case e1000_82547_rev_2:
607 if (E1000_READ_REG(&adapter->hw, MANC) &
608 E1000_MANC_SMBUS_EN)
609 goto out;
610 break;
611 case e1000_82571:
612 case e1000_82572:
613 case e1000_82573:
614 case e1000_80003es2lan:
615 case e1000_ich8lan:
616 if (e1000_check_mng_mode(&adapter->hw) ||
617 e1000_check_phy_reset_block(&adapter->hw))
618 goto out;
619 break;
620 default:
621 goto out;
622 }
79f05bf0
AK		 623 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
624 mii_reg |= MII_CR_POWER_DOWN;
625 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
626 mdelay(1);
627 }
61c2505f
BA		 628out:
629 return;
79f05bf0
AK		 630}
631
1da177e4
LT		 632void
633e1000_down(struct e1000_adapter *adapter)
634{
635 struct net_device *netdev = adapter->netdev;
636
1314bbf3
AK		 637 /* signal that we're down so the interrupt handler does not
638 * reschedule our watchdog timer */
639 set_bit(__E1000_DOWN, &adapter->flags);
640
e0aac5a2
AK		 641#ifdef CONFIG_E1000_NAPI
642 netif_poll_disable(netdev);
643#endif
1da177e4 644 e1000_irq_disable(adapter);
c1605eb3 645
1da177e4
LT		 646 del_timer_sync(&adapter->tx_fifo_stall_timer);
647 del_timer_sync(&adapter->watchdog_timer);
648 del_timer_sync(&adapter->phy_info_timer);
649
7bfa4816 650 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 651 adapter->link_speed = 0;
652 adapter->link_duplex = 0;
653 netif_carrier_off(netdev);
654 netif_stop_queue(netdev);
655
656 e1000_reset(adapter);
581d708e
MC		 657 e1000_clean_all_tx_rings(adapter);
658 e1000_clean_all_rx_rings(adapter);
1da177e4 659}
1da177e4 660
2db10a08
AK		 661void
662e1000_reinit_locked(struct e1000_adapter *adapter)
663{
664 WARN_ON(in_interrupt());
665 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
666 msleep(1);
667 e1000_down(adapter);
668 e1000_up(adapter);
669 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 670}
671
672void
673e1000_reset(struct e1000_adapter *adapter)
674{
018ea44e 675 uint32_t pba = 0, tx_space, min_tx_space, min_rx_space;
1125ecbc 676 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
018ea44e 677 boolean_t legacy_pba_adjust = FALSE;
1da177e4
LT		 678
679 /* Repartition Pba for greater than 9k mtu
680 * To take effect CTRL.RST is required.
681 */
682
2d7edb92 683 switch (adapter->hw.mac_type) {
018ea44e
BA		 684 case e1000_82542_rev2_0:
685 case e1000_82542_rev2_1:
686 case e1000_82543:
687 case e1000_82544:
688 case e1000_82540:
689 case e1000_82541:
690 case e1000_82541_rev_2:
691 legacy_pba_adjust = TRUE;
692 pba = E1000_PBA_48K;
693 break;
694 case e1000_82545:
695 case e1000_82545_rev_3:
696 case e1000_82546:
697 case e1000_82546_rev_3:
698 pba = E1000_PBA_48K;
699 break;
2d7edb92 700 case e1000_82547:
0e6ef3e0 701 case e1000_82547_rev_2:
018ea44e 702 legacy_pba_adjust = TRUE;
2d7edb92
MC		 703 pba = E1000_PBA_30K;
704 break;
868d5309
MC		 705 case e1000_82571:
706 case e1000_82572:
6418ecc6 707 case e1000_80003es2lan:
868d5309
MC		 708 pba = E1000_PBA_38K;
709 break;
2d7edb92 710 case e1000_82573:
018ea44e 711 pba = E1000_PBA_20K;
2d7edb92 712 break;
cd94dd0b
AK		 713 case e1000_ich8lan:
714 pba = E1000_PBA_8K;
018ea44e
BA		 715 case e1000_undefined:
716 case e1000_num_macs:
2d7edb92
MC		 717 break;
718 }
719
018ea44e
BA		 720 if (legacy_pba_adjust == TRUE) {
721 if (adapter->netdev->mtu > E1000_RXBUFFER_8192)
722 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92 723
018ea44e
BA		 724 if (adapter->hw.mac_type == e1000_82547) {
725 adapter->tx_fifo_head = 0;
726 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
727 adapter->tx_fifo_size =
728 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
729 atomic_set(&adapter->tx_fifo_stall, 0);
730 }
731 } else if (adapter->hw.max_frame_size > MAXIMUM_ETHERNET_FRAME_SIZE) {
732 /* adjust PBA for jumbo frames */
733 E1000_WRITE_REG(&adapter->hw, PBA, pba);
734
735 /* To maintain wire speed transmits, the Tx FIFO should be
736 * large enough to accomodate two full transmit packets,
737 * rounded up to the next 1KB and expressed in KB. Likewise,
738 * the Rx FIFO should be large enough to accomodate at least
739 * one full receive packet and is similarly rounded up and
740 * expressed in KB. */
741 pba = E1000_READ_REG(&adapter->hw, PBA);
742 /* upper 16 bits has Tx packet buffer allocation size in KB */
743 tx_space = pba >> 16;
744 /* lower 16 bits has Rx packet buffer allocation size in KB */
745 pba &= 0xffff;
746 /* don't include ethernet FCS because hardware appends/strips */
747 min_rx_space = adapter->netdev->mtu + ENET_HEADER_SIZE +
748 VLAN_TAG_SIZE;
749 min_tx_space = min_rx_space;
750 min_tx_space *= 2;
751 E1000_ROUNDUP(min_tx_space, 1024);
752 min_tx_space >>= 10;
753 E1000_ROUNDUP(min_rx_space, 1024);
754 min_rx_space >>= 10;
755
756 /* If current Tx allocation is less than the min Tx FIFO size,
757 * and the min Tx FIFO size is less than the current Rx FIFO
758 * allocation, take space away from current Rx allocation */
759 if (tx_space < min_tx_space &&
760 ((min_tx_space - tx_space) < pba)) {
761 pba = pba - (min_tx_space - tx_space);
762
763 /* PCI/PCIx hardware has PBA alignment constraints */
764 switch (adapter->hw.mac_type) {
765 case e1000_82545 ... e1000_82546_rev_3:
766 pba &= ~(E1000_PBA_8K - 1);
767 break;
768 default:
769 break;
770 }
771
772 /* if short on rx space, rx wins and must trump tx
773 * adjustment or use Early Receive if available */
774 if (pba < min_rx_space) {
775 switch (adapter->hw.mac_type) {
776 case e1000_82573:
777 /* ERT enabled in e1000_configure_rx */
778 break;
779 default:
780 pba = min_rx_space;
781 break;
782 }
783 }
784 }
1da177e4 785 }
2d7edb92 786
1da177e4
LT		 787 E1000_WRITE_REG(&adapter->hw, PBA, pba);
788
789 /* flow control settings */
f11b7f85
JK		 790 /* Set the FC high water mark to 90% of the FIFO size.
791 * Required to clear last 3 LSB */
792 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
cd94dd0b
AK		 793 /* We can't use 90% on small FIFOs because the remainder
794 * would be less than 1 full frame. In this case, we size
795 * it to allow at least a full frame above the high water
796 * mark. */
797 if (pba < E1000_PBA_16K)
798 fc_high_water_mark = (pba * 1024) - 1600;
f11b7f85
JK		 799
800 adapter->hw.fc_high_water = fc_high_water_mark;
801 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 802 if (adapter->hw.mac_type == e1000_80003es2lan)
803 adapter->hw.fc_pause_time = 0xFFFF;
804 else
805 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 806 adapter->hw.fc_send_xon = 1;
807 adapter->hw.fc = adapter->hw.original_fc;
808
2d7edb92 809 /* Allow time for pending master requests to run */
1da177e4 810 e1000_reset_hw(&adapter->hw);
96838a40 811 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 812 E1000_WRITE_REG(&adapter->hw, WUC, 0);
09ae3e88 813
96838a40 814 if (e1000_init_hw(&adapter->hw))
1da177e4 815 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 816 e1000_update_mng_vlan(adapter);
3d5460a0
JB		 817
818 /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */
819 if (adapter->hw.mac_type >= e1000_82544 &&
820 adapter->hw.mac_type <= e1000_82547_rev_2 &&
821 adapter->hw.autoneg == 1 &&
822 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) {
823 uint32_t ctrl = E1000_READ_REG(&adapter->hw, CTRL);
824 /* clear phy power management bit if we are in gig only mode,
825 * which if enabled will attempt negotiation to 100Mb, which
826 * can cause a loss of link at power off or driver unload */
827 ctrl &= ~E1000_CTRL_SWDPIN3;
828 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
829 }
830
1da177e4
LT		 831 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
832 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
833
834 e1000_reset_adaptive(&adapter->hw);
835 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
9a53a202
AK		 836
837 if (!adapter->smart_power_down &&
838 (adapter->hw.mac_type == e1000_82571 ||
839 adapter->hw.mac_type == e1000_82572)) {
840 uint16_t phy_data = 0;
841 /* speed up time to link by disabling smart power down, ignore
842 * the return value of this function because there is nothing
843 * different we would do if it failed */
844 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
845 &phy_data);
846 phy_data &= ~IGP02E1000_PM_SPD;
847 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
848 phy_data);
849 }
850
0fccd0e9 851 e1000_release_manageability(adapter);
1da177e4
LT		 852}
853
854/**
855 * e1000_probe - Device Initialization Routine
856 * @pdev: PCI device information struct
857 * @ent: entry in e1000_pci_tbl
858 *
859 * Returns 0 on success, negative on failure
860 *
861 * e1000_probe initializes an adapter identified by a pci_dev structure.
862 * The OS initialization, configuring of the adapter private structure,
863 * and a hardware reset occur.
864 **/
865
866static int __devinit
867e1000_probe(struct pci_dev *pdev,
868 const struct pci_device_id *ent)
869{
870 struct net_device *netdev;
871 struct e1000_adapter *adapter;
2d7edb92 872 unsigned long mmio_start, mmio_len;
cd94dd0b 873 unsigned long flash_start, flash_len;
2d7edb92 874
1da177e4 875 static int cards_found = 0;
120cd576 876 static int global_quad_port_a = 0; /* global ksp3 port a indication */
2d7edb92 877 int i, err, pci_using_dac;
120cd576 878 uint16_t eeprom_data = 0;
1da177e4 879 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 880 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 881 return err;
882
cd94dd0b
AK		 883 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
884 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 885 pci_using_dac = 1;
886 } else {
cd94dd0b
AK		 887 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
888 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4 889 E1000_ERR("No usable DMA configuration, aborting\n");
6dd62ab0 890 goto err_dma;
1da177e4
LT		 891 }
892 pci_using_dac = 0;
893 }
894
96838a40 895 if ((err = pci_request_regions(pdev, e1000_driver_name)))
6dd62ab0 896 goto err_pci_reg;
1da177e4
LT		 897
898 pci_set_master(pdev);
899
6dd62ab0 900 err = -ENOMEM;
1da177e4 901 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6dd62ab0 902 if (!netdev)
1da177e4 903 goto err_alloc_etherdev;
1da177e4
LT		 904
905 SET_MODULE_OWNER(netdev);
906 SET_NETDEV_DEV(netdev, &pdev->dev);
907
908 pci_set_drvdata(pdev, netdev);
60490fe0 909 adapter = netdev_priv(netdev);
1da177e4
LT		 910 adapter->netdev = netdev;
911 adapter->pdev = pdev;
912 adapter->hw.back = adapter;
913 adapter->msg_enable = (1 << debug) - 1;
914
915 mmio_start = pci_resource_start(pdev, BAR_0);
916 mmio_len = pci_resource_len(pdev, BAR_0);
917
6dd62ab0 918 err = -EIO;
1da177e4 919 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6dd62ab0 920 if (!adapter->hw.hw_addr)
1da177e4 921 goto err_ioremap;
1da177e4 922
96838a40
JB		 923 for (i = BAR_1; i <= BAR_5; i++) {
924 if (pci_resource_len(pdev, i) == 0)
1da177e4 925 continue;
96838a40 926 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 927 adapter->hw.io_base = pci_resource_start(pdev, i);
928 break;
929 }
930 }
931
932 netdev->open = &e1000_open;
933 netdev->stop = &e1000_close;
934 netdev->hard_start_xmit = &e1000_xmit_frame;
935 netdev->get_stats = &e1000_get_stats;
936 netdev->set_multicast_list = &e1000_set_multi;
937 netdev->set_mac_address = &e1000_set_mac;
938 netdev->change_mtu = &e1000_change_mtu;
939 netdev->do_ioctl = &e1000_ioctl;
940 e1000_set_ethtool_ops(netdev);
941 netdev->tx_timeout = &e1000_tx_timeout;
942 netdev->watchdog_timeo = 5 * HZ;
943#ifdef CONFIG_E1000_NAPI
944 netdev->poll = &e1000_clean;
945 netdev->weight = 64;
946#endif
947 netdev->vlan_rx_register = e1000_vlan_rx_register;
948 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
949 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
950#ifdef CONFIG_NET_POLL_CONTROLLER
951 netdev->poll_controller = e1000_netpoll;
952#endif
0eb5a34c 953 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1da177e4
LT		 954
955 netdev->mem_start = mmio_start;
956 netdev->mem_end = mmio_start + mmio_len;
957 netdev->base_addr = adapter->hw.io_base;
958
959 adapter->bd_number = cards_found;
960
961 /* setup the private structure */
962
96838a40 963 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 964 goto err_sw_init;
965
6dd62ab0 966 err = -EIO;
cd94dd0b
AK		 967 /* Flash BAR mapping must happen after e1000_sw_init
968 * because it depends on mac_type */
969 if ((adapter->hw.mac_type == e1000_ich8lan) &&
970 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
971 flash_start = pci_resource_start(pdev, 1);
972 flash_len = pci_resource_len(pdev, 1);
973 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6dd62ab0 974 if (!adapter->hw.flash_address)
cd94dd0b 975 goto err_flashmap;
cd94dd0b
AK		 976 }
977
6dd62ab0 978 if (e1000_check_phy_reset_block(&adapter->hw))
2d7edb92
MC		 979 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
980
96838a40 981 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 982 netdev->features = NETIF_F_SG |
983 NETIF_F_HW_CSUM |
984 NETIF_F_HW_VLAN_TX |
985 NETIF_F_HW_VLAN_RX |
986 NETIF_F_HW_VLAN_FILTER;
cd94dd0b
AK		 987 if (adapter->hw.mac_type == e1000_ich8lan)
988 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
1da177e4
LT		 989 }
990
96838a40 991 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 992 (adapter->hw.mac_type != e1000_82547))
993 netdev->features |= NETIF_F_TSO;
2d7edb92 994
96838a40 995 if (adapter->hw.mac_type > e1000_82547_rev_2)
87ca4e5b 996 netdev->features |= NETIF_F_TSO6;
96838a40 997 if (pci_using_dac)
1da177e4
LT		 998 netdev->features |= NETIF_F_HIGHDMA;
999
76c224bc
AK		 1000 netdev->features |= NETIF_F_LLTX;
1001
2d7edb92
MC		 1002 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
1003
cd94dd0b
AK		 1004 /* initialize eeprom parameters */
1005
1006 if (e1000_init_eeprom_params(&adapter->hw)) {
1007 E1000_ERR("EEPROM initialization failed\n");
6dd62ab0 1008 goto err_eeprom;
cd94dd0b
AK		 1009 }
1010
96838a40 1011 /* before reading the EEPROM, reset the controller to
1da177e4 1012 * put the device in a known good starting state */
96838a40 1013
1da177e4
LT		 1014 e1000_reset_hw(&adapter->hw);
1015
1016 /* make sure the EEPROM is good */
1017
96838a40 1018 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4 1019 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
1da177e4
LT		 1020 goto err_eeprom;
1021 }
1022
1023 /* copy the MAC address out of the EEPROM */
1024
96838a40 1025 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 1026 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
1027 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 1028 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 1029
96838a40 1030 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4 1031 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
1da177e4
LT		 1032 goto err_eeprom;
1033 }
1034
1da177e4
LT		 1035 e1000_get_bus_info(&adapter->hw);
1036
1037 init_timer(&adapter->tx_fifo_stall_timer);
1038 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
1039 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
1040
1041 init_timer(&adapter->watchdog_timer);
1042 adapter->watchdog_timer.function = &e1000_watchdog;
1043 adapter->watchdog_timer.data = (unsigned long) adapter;
1044
1da177e4
LT		 1045 init_timer(&adapter->phy_info_timer);
1046 adapter->phy_info_timer.function = &e1000_update_phy_info;
1047 adapter->phy_info_timer.data = (unsigned long) adapter;
1048
65f27f38 1049 INIT_WORK(&adapter->reset_task, e1000_reset_task);
1da177e4 1050
1da177e4
LT		 1051 e1000_check_options(adapter);
1052
1053 /* Initial Wake on LAN setting
1054 * If APM wake is enabled in the EEPROM,
1055 * enable the ACPI Magic Packet filter
1056 */
1057
96838a40 1058 switch (adapter->hw.mac_type) {
1da177e4
LT		 1059 case e1000_82542_rev2_0:
1060 case e1000_82542_rev2_1:
1061 case e1000_82543:
1062 break;
1063 case e1000_82544:
1064 e1000_read_eeprom(&adapter->hw,
1065 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1066 eeprom_apme_mask = E1000_EEPROM_82544_APM;
1067 break;
cd94dd0b
AK		 1068 case e1000_ich8lan:
1069 e1000_read_eeprom(&adapter->hw,
1070 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
1071 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
1072 break;
1da177e4
LT		 1073 case e1000_82546:
1074 case e1000_82546_rev_3:
fd803241 1075 case e1000_82571:
6418ecc6 1076 case e1000_80003es2lan:
96838a40 1077 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 1078 e1000_read_eeprom(&adapter->hw,
1079 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1080 break;
1081 }
1082 /* Fall Through */
1083 default:
1084 e1000_read_eeprom(&adapter->hw,
1085 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1086 break;
1087 }
96838a40 1088 if (eeprom_data & eeprom_apme_mask)
120cd576
JB		 1089 adapter->eeprom_wol |= E1000_WUFC_MAG;
1090
1091 /* now that we have the eeprom settings, apply the special cases
1092 * where the eeprom may be wrong or the board simply won't support
1093 * wake on lan on a particular port */
1094 switch (pdev->device) {
1095 case E1000_DEV_ID_82546GB_PCIE:
1096 adapter->eeprom_wol = 0;
1097 break;
1098 case E1000_DEV_ID_82546EB_FIBER:
1099 case E1000_DEV_ID_82546GB_FIBER:
1100 case E1000_DEV_ID_82571EB_FIBER:
1101 /* Wake events only supported on port A for dual fiber
1102 * regardless of eeprom setting */
1103 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
1104 adapter->eeprom_wol = 0;
1105 break;
1106 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
5881cde8 1107 case E1000_DEV_ID_82571EB_QUAD_COPPER:
fc2307d0 1108 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
120cd576
JB		 1109 /* if quad port adapter, disable WoL on all but port A */
1110 if (global_quad_port_a != 0)
1111 adapter->eeprom_wol = 0;
1112 else
1113 adapter->quad_port_a = 1;
1114 /* Reset for multiple quad port adapters */
1115 if (++global_quad_port_a == 4)
1116 global_quad_port_a = 0;
1117 break;
1118 }
1119
1120 /* initialize the wol settings based on the eeprom settings */
1121 adapter->wol = adapter->eeprom_wol;
1da177e4 1122
fb3d47d4
JK		 1123 /* print bus type/speed/width info */
1124 {
1125 struct e1000_hw *hw = &adapter->hw;
1126 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
1127 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
1128 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
1129 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
1130 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
1131 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
1132 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
1133 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
1134 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
1135 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
1136 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
1137 "32-bit"));
1138 }
1139
1140 for (i = 0; i < 6; i++)
1141 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
1142
1da177e4
LT		 1143 /* reset the hardware with the new settings */
1144 e1000_reset(adapter);
1145
b55ccb35
JK		 1146 /* If the controller is 82573 and f/w is AMT, do not set
1147 * DRV_LOAD until the interface is up. For all other cases,
1148 * let the f/w know that the h/w is now under the control
1149 * of the driver. */
1150 if (adapter->hw.mac_type != e1000_82573 ||
1151 !e1000_check_mng_mode(&adapter->hw))
1152 e1000_get_hw_control(adapter);
2d7edb92 1153
1da177e4 1154 strcpy(netdev->name, "eth%d");
96838a40 1155 if ((err = register_netdev(netdev)))
1da177e4
LT		 1156 goto err_register;
1157
1314bbf3
AK		 1158 /* tell the stack to leave us alone until e1000_open() is called */
1159 netif_carrier_off(netdev);
1160 netif_stop_queue(netdev);
1161
1da177e4
LT		 1162 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
1163
1164 cards_found++;
1165 return 0;
1166
1167err_register:
6dd62ab0
VA		 1168 e1000_release_hw_control(adapter);
1169err_eeprom:
1170 if (!e1000_check_phy_reset_block(&adapter->hw))
1171 e1000_phy_hw_reset(&adapter->hw);
1172
cd94dd0b
AK		 1173 if (adapter->hw.flash_address)
1174 iounmap(adapter->hw.flash_address);
1175err_flashmap:
6dd62ab0
VA		 1176#ifdef CONFIG_E1000_NAPI
1177 for (i = 0; i < adapter->num_rx_queues; i++)
1178 dev_put(&adapter->polling_netdev[i]);
1179#endif
1180
1181 kfree(adapter->tx_ring);
1182 kfree(adapter->rx_ring);
1183#ifdef CONFIG_E1000_NAPI
1184 kfree(adapter->polling_netdev);
1185#endif
1da177e4 1186err_sw_init:
1da177e4
LT		 1187 iounmap(adapter->hw.hw_addr);
1188err_ioremap:
1189 free_netdev(netdev);
1190err_alloc_etherdev:
1191 pci_release_regions(pdev);
6dd62ab0
VA		 1192err_pci_reg:
1193err_dma:
1194 pci_disable_device(pdev);
1da177e4
LT		 1195 return err;
1196}
1197
1198/**
1199 * e1000_remove - Device Removal Routine
1200 * @pdev: PCI device information struct
1201 *
1202 * e1000_remove is called by the PCI subsystem to alert the driver
1203 * that it should release a PCI device. The could be caused by a
1204 * Hot-Plug event, or because the driver is going to be removed from
1205 * memory.
1206 **/
1207
1208static void __devexit
1209e1000_remove(struct pci_dev *pdev)
1210{
1211 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 1212 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e
MC		 1213#ifdef CONFIG_E1000_NAPI
1214 int i;
1215#endif
1da177e4 1216
be2b28ed
JG		 1217 flush_scheduled_work();
1218
0fccd0e9 1219 e1000_release_manageability(adapter);
1da177e4 1220
b55ccb35
JK		 1221 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1222 * would have already happened in close and is redundant. */
1223 e1000_release_hw_control(adapter);
2d7edb92 1224
1da177e4 1225 unregister_netdev(netdev);
581d708e 1226#ifdef CONFIG_E1000_NAPI
f56799ea 1227 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 1228 dev_put(&adapter->polling_netdev[i]);
581d708e 1229#endif
1da177e4 1230
96838a40 1231 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 1232 e1000_phy_hw_reset(&adapter->hw);
1da177e4 1233
24025e4e
MC		 1234 kfree(adapter->tx_ring);
1235 kfree(adapter->rx_ring);
1236#ifdef CONFIG_E1000_NAPI
1237 kfree(adapter->polling_netdev);
1238#endif
1239
1da177e4 1240 iounmap(adapter->hw.hw_addr);
cd94dd0b
AK		 1241 if (adapter->hw.flash_address)
1242 iounmap(adapter->hw.flash_address);
1da177e4
LT		 1243 pci_release_regions(pdev);
1244
1245 free_netdev(netdev);
1246
1247 pci_disable_device(pdev);
1248}
1249
1250/**
1251 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
1252 * @adapter: board private structure to initialize
1253 *
1254 * e1000_sw_init initializes the Adapter private data structure.
1255 * Fields are initialized based on PCI device information and
1256 * OS network device settings (MTU size).
1257 **/
1258
1259static int __devinit
1260e1000_sw_init(struct e1000_adapter *adapter)
1261{
1262 struct e1000_hw *hw = &adapter->hw;
1263 struct net_device *netdev = adapter->netdev;
1264 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 1265#ifdef CONFIG_E1000_NAPI
1266 int i;
1267#endif
1da177e4
LT		 1268
1269 /* PCI config space info */
1270
1271 hw->vendor_id = pdev->vendor;
1272 hw->device_id = pdev->device;
1273 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1274 hw->subsystem_id = pdev->subsystem_device;
1275
1276 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
1277
1278 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
1279
eb0f8054 1280 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9e2feace 1281 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 1282 hw->max_frame_size = netdev->mtu +
1283 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1284 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
1285
1286 /* identify the MAC */
1287
96838a40 1288 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 1289 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
1290 return -EIO;
1291 }
1292
96838a40 1293 switch (hw->mac_type) {
1da177e4
LT		 1294 default:
1295 break;
1296 case e1000_82541:
1297 case e1000_82547:
1298 case e1000_82541_rev_2:
1299 case e1000_82547_rev_2:
1300 hw->phy_init_script = 1;
1301 break;
1302 }
1303
1304 e1000_set_media_type(hw);
1305
1306 hw->wait_autoneg_complete = FALSE;
1307 hw->tbi_compatibility_en = TRUE;
1308 hw->adaptive_ifs = TRUE;
1309
1310 /* Copper options */
1311
96838a40 1312 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1313 hw->mdix = AUTO_ALL_MODES;
1314 hw->disable_polarity_correction = FALSE;
1315 hw->master_slave = E1000_MASTER_SLAVE;
1316 }
1317
f56799ea
JK		 1318 adapter->num_tx_queues = 1;
1319 adapter->num_rx_queues = 1;
581d708e
MC		 1320
1321 if (e1000_alloc_queues(adapter)) {
1322 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1323 return -ENOMEM;
1324 }
1325
1326#ifdef CONFIG_E1000_NAPI
f56799ea 1327 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1328 adapter->polling_netdev[i].priv = adapter;
1329 adapter->polling_netdev[i].poll = &e1000_clean;
1330 adapter->polling_netdev[i].weight = 64;
1331 dev_hold(&adapter->polling_netdev[i]);
1332 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1333 }
7bfa4816 1334 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1335#endif
1336
1da177e4
LT		 1337 atomic_set(&adapter->irq_sem, 1);
1338 spin_lock_init(&adapter->stats_lock);
1da177e4 1339
1314bbf3
AK		 1340 set_bit(__E1000_DOWN, &adapter->flags);
1341
1da177e4
LT		 1342 return 0;
1343}
1344
581d708e
MC		 1345/**
1346 * e1000_alloc_queues - Allocate memory for all rings
1347 * @adapter: board private structure to initialize
1348 *
1349 * We allocate one ring per queue at run-time since we don't know the
1350 * number of queues at compile-time. The polling_netdev array is
1351 * intended for Multiqueue, but should work fine with a single queue.
1352 **/
1353
1354static int __devinit
1355e1000_alloc_queues(struct e1000_adapter *adapter)
1356{
1357 int size;
1358
f56799ea 1359 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1360 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1361 if (!adapter->tx_ring)
1362 return -ENOMEM;
1363 memset(adapter->tx_ring, 0, size);
1364
f56799ea 1365 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1366 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1367 if (!adapter->rx_ring) {
1368 kfree(adapter->tx_ring);
1369 return -ENOMEM;
1370 }
1371 memset(adapter->rx_ring, 0, size);
1372
1373#ifdef CONFIG_E1000_NAPI
f56799ea 1374 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1375 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1376 if (!adapter->polling_netdev) {
1377 kfree(adapter->tx_ring);
1378 kfree(adapter->rx_ring);
1379 return -ENOMEM;
1380 }
1381 memset(adapter->polling_netdev, 0, size);
1382#endif
1383
1384 return E1000_SUCCESS;
1385}
1386
1da177e4
LT		 1387/**
1388 * e1000_open - Called when a network interface is made active
1389 * @netdev: network interface device structure
1390 *
1391 * Returns 0 on success, negative value on failure
1392 *
1393 * The open entry point is called when a network interface is made
1394 * active by the system (IFF_UP). At this point all resources needed
1395 * for transmit and receive operations are allocated, the interrupt
1396 * handler is registered with the OS, the watchdog timer is started,
1397 * and the stack is notified that the interface is ready.
1398 **/
1399
1400static int
1401e1000_open(struct net_device *netdev)
1402{
60490fe0 1403 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1404 int err;
1405
2db10a08 1406 /* disallow open during test */
1314bbf3 1407 if (test_bit(__E1000_TESTING, &adapter->flags))
2db10a08
AK		 1408 return -EBUSY;
1409
1da177e4 1410 /* allocate transmit descriptors */
e0aac5a2
AK		 1411 err = e1000_setup_all_tx_resources(adapter);
1412 if (err)
1da177e4
LT		 1413 goto err_setup_tx;
1414
1415 /* allocate receive descriptors */
e0aac5a2 1416 err = e1000_setup_all_rx_resources(adapter);
b5bf28cd 1417 if (err)
e0aac5a2 1418 goto err_setup_rx;
b5bf28cd 1419
79f05bf0
AK		 1420 e1000_power_up_phy(adapter);
1421
2d7edb92 1422 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1423 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1424 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1425 e1000_update_mng_vlan(adapter);
1426 }
1da177e4 1427
b55ccb35
JK		 1428 /* If AMT is enabled, let the firmware know that the network
1429 * interface is now open */
1430 if (adapter->hw.mac_type == e1000_82573 &&
1431 e1000_check_mng_mode(&adapter->hw))
1432 e1000_get_hw_control(adapter);
1433
e0aac5a2
AK		 1434 /* before we allocate an interrupt, we must be ready to handle it.
1435 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1436 * as soon as we call pci_request_irq, so we have to setup our
1437 * clean_rx handler before we do so. */
1438 e1000_configure(adapter);
1439
1440 err = e1000_request_irq(adapter);
1441 if (err)
1442 goto err_req_irq;
1443
1444 /* From here on the code is the same as e1000_up() */
1445 clear_bit(__E1000_DOWN, &adapter->flags);
1446
1447#ifdef CONFIG_E1000_NAPI
1448 netif_poll_enable(netdev);
1449#endif
1450
1451 e1000_irq_enable(adapter);
1452
1453 /* fire a link status change interrupt to start the watchdog */
1454 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1455
1da177e4
LT		 1456 return E1000_SUCCESS;
1457
b5bf28cd 1458err_req_irq:
e0aac5a2
AK		 1459 e1000_release_hw_control(adapter);
1460 e1000_power_down_phy(adapter);
581d708e 1461 e1000_free_all_rx_resources(adapter);
1da177e4 1462err_setup_rx:
581d708e 1463 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1464err_setup_tx:
1465 e1000_reset(adapter);
1466
1467 return err;
1468}
1469
1470/**
1471 * e1000_close - Disables a network interface
1472 * @netdev: network interface device structure
1473 *
1474 * Returns 0, this is not allowed to fail
1475 *
1476 * The close entry point is called when an interface is de-activated
1477 * by the OS. The hardware is still under the drivers control, but
1478 * needs to be disabled. A global MAC reset is issued to stop the
1479 * hardware, and all transmit and receive resources are freed.
1480 **/
1481
1482static int
1483e1000_close(struct net_device *netdev)
1484{
60490fe0 1485 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 1486
2db10a08 1487 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 1488 e1000_down(adapter);
79f05bf0 1489 e1000_power_down_phy(adapter);
2db10a08 1490 e1000_free_irq(adapter);
1da177e4 1491
581d708e
MC		 1492 e1000_free_all_tx_resources(adapter);
1493 e1000_free_all_rx_resources(adapter);
1da177e4 1494
4666560a
BA		 1495 /* kill manageability vlan ID if supported, but not if a vlan with
1496 * the same ID is registered on the host OS (let 8021q kill it) */
96838a40 1497 if ((adapter->hw.mng_cookie.status &
4666560a
BA		 1498 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
1499 !(adapter->vlgrp &&
5c15bdec 1500 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) {
2d7edb92
MC		 1501 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1502 }
b55ccb35
JK		 1503
1504 /* If AMT is enabled, let the firmware know that the network
1505 * interface is now closed */
1506 if (adapter->hw.mac_type == e1000_82573 &&
1507 e1000_check_mng_mode(&adapter->hw))
1508 e1000_release_hw_control(adapter);
1509
1da177e4
LT		 1510 return 0;
1511}
1512
1513/**
1514 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1515 * @adapter: address of board private structure
2d7edb92
MC		 1516 * @start: address of beginning of memory
1517 * @len: length of memory
1da177e4 1518 **/
e619d523 1519static boolean_t
1da177e4
LT		 1520e1000_check_64k_bound(struct e1000_adapter *adapter,
1521 void *start, unsigned long len)
1522{
1523 unsigned long begin = (unsigned long) start;
1524 unsigned long end = begin + len;
1525
2648345f
MC		 1526 /* First rev 82545 and 82546 need to not allow any memory
1527 * write location to cross 64k boundary due to errata 23 */
1da177e4 1528 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1529 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1530 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1531 }
1532
1533 return TRUE;
1534}
1535
1536/**
1537 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1538 * @adapter: board private structure
581d708e 1539 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1540 *
1541 * Return 0 on success, negative on failure
1542 **/
1543
3ad2cc67 1544static int
581d708e
MC		 1545e1000_setup_tx_resources(struct e1000_adapter *adapter,
1546 struct e1000_tx_ring *txdr)
1da177e4 1547{
1da177e4
LT		 1548 struct pci_dev *pdev = adapter->pdev;
1549 int size;
1550
1551 size = sizeof(struct e1000_buffer) * txdr->count;
cd94dd0b 1552 txdr->buffer_info = vmalloc(size);
96838a40 1553 if (!txdr->buffer_info) {
2648345f
MC		 1554 DPRINTK(PROBE, ERR,
1555 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1556 return -ENOMEM;
1557 }
1558 memset(txdr->buffer_info, 0, size);
1559
1560 /* round up to nearest 4K */
1561
1562 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1563 E1000_ROUNDUP(txdr->size, 4096);
1564
1565 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1566 if (!txdr->desc) {
1da177e4 1567setup_tx_desc_die:
1da177e4 1568 vfree(txdr->buffer_info);
2648345f
MC		 1569 DPRINTK(PROBE, ERR,
1570 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1571 return -ENOMEM;
1572 }
1573
2648345f 1574 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1575 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1576 void *olddesc = txdr->desc;
1577 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1578 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1579 "at %p\n", txdr->size, txdr->desc);
1580 /* Try again, without freeing the previous */
1da177e4 1581 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1582 /* Failed allocation, critical failure */
96838a40 1583 if (!txdr->desc) {
1da177e4
LT		 1584 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1585 goto setup_tx_desc_die;
1586 }
1587
1588 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1589 /* give up */
2648345f
MC		 1590 pci_free_consistent(pdev, txdr->size, txdr->desc,
1591 txdr->dma);
1da177e4
LT		 1592 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1593 DPRINTK(PROBE, ERR,
2648345f
MC		 1594 "Unable to allocate aligned memory "
1595 "for the transmit descriptor ring\n");
1da177e4
LT		 1596 vfree(txdr->buffer_info);
1597 return -ENOMEM;
1598 } else {
2648345f 1599 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1600 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1601 }
1602 }
1603 memset(txdr->desc, 0, txdr->size);
1604
1605 txdr->next_to_use = 0;
1606 txdr->next_to_clean = 0;
2ae76d98 1607 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1608
1609 return 0;
1610}
1611
581d708e
MC		 1612/**
1613 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1614 * (Descriptors) for all queues
1615 * @adapter: board private structure
1616 *
581d708e
MC		 1617 * Return 0 on success, negative on failure
1618 **/
1619
1620int
1621e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1622{
1623 int i, err = 0;
1624
f56799ea 1625 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1626 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1627 if (err) {
1628 DPRINTK(PROBE, ERR,
1629 "Allocation for Tx Queue %u failed\n", i);
3fbbc72e
VA		 1630 for (i-- ; i >= 0; i--)
1631 e1000_free_tx_resources(adapter,
1632 &adapter->tx_ring[i]);
581d708e
MC		 1633 break;
1634 }
1635 }
1636
1637 return err;
1638}
1639
1da177e4
LT		 1640/**
1641 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1642 * @adapter: board private structure
1643 *
1644 * Configure the Tx unit of the MAC after a reset.
1645 **/
1646
1647static void
1648e1000_configure_tx(struct e1000_adapter *adapter)
1649{
581d708e
MC		 1650 uint64_t tdba;
1651 struct e1000_hw *hw = &adapter->hw;
1652 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1653 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1654
1655 /* Setup the HW Tx Head and Tail descriptor pointers */
1656
f56799ea 1657 switch (adapter->num_tx_queues) {
24025e4e
MC		 1658 case 1:
1659 default:
581d708e
MC		 1660 tdba = adapter->tx_ring[0].dma;
1661 tdlen = adapter->tx_ring[0].count *
1662 sizeof(struct e1000_tx_desc);
581d708e 1663 E1000_WRITE_REG(hw, TDLEN, tdlen);
4ca213a6
AK		 1664 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1665 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
581d708e 1666 E1000_WRITE_REG(hw, TDT, 0);
4ca213a6 1667 E1000_WRITE_REG(hw, TDH, 0);
6a951698
AK		 1668 adapter->tx_ring[0].tdh = ((hw->mac_type >= e1000_82543) ? E1000_TDH : E1000_82542_TDH);
1669 adapter->tx_ring[0].tdt = ((hw->mac_type >= e1000_82543) ? E1000_TDT : E1000_82542_TDT);
24025e4e
MC		 1670 break;
1671 }
1da177e4
LT		 1672
1673 /* Set the default values for the Tx Inter Packet Gap timer */
d89b6c67
JB		 1674 if (adapter->hw.mac_type <= e1000_82547_rev_2 &&
1675 (hw->media_type == e1000_media_type_fiber ||
1676 hw->media_type == e1000_media_type_internal_serdes))
0fadb059
JK		 1677 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1678 else
1679 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1680
581d708e 1681 switch (hw->mac_type) {
1da177e4
LT		 1682 case e1000_82542_rev2_0:
1683 case e1000_82542_rev2_1:
1684 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1685 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1686 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1687 break;
87041639
JK		 1688 case e1000_80003es2lan:
1689 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1690 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1691 break;
1da177e4 1692 default:
0fadb059
JK		 1693 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1694 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1695 break;
1da177e4 1696 }
0fadb059
JK		 1697 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1698 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1699 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1700
1701 /* Set the Tx Interrupt Delay register */
1702
581d708e
MC		 1703 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1704 if (hw->mac_type >= e1000_82540)
1705 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1706
1707 /* Program the Transmit Control Register */
1708
581d708e 1709 tctl = E1000_READ_REG(hw, TCTL);
1da177e4 1710 tctl &= ~E1000_TCTL_CT;
7e6c9861 1711 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1712 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1713
2ae76d98
MC		 1714 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1715 tarc = E1000_READ_REG(hw, TARC0);
90fb5135
AK		 1716 /* set the speed mode bit, we'll clear it if we're not at
1717 * gigabit link later */
09ae3e88 1718 tarc |= (1 << 21);
2ae76d98 1719 E1000_WRITE_REG(hw, TARC0, tarc);
87041639
JK		 1720 } else if (hw->mac_type == e1000_80003es2lan) {
1721 tarc = E1000_READ_REG(hw, TARC0);
1722 tarc |= 1;
87041639
JK		 1723 E1000_WRITE_REG(hw, TARC0, tarc);
1724 tarc = E1000_READ_REG(hw, TARC1);
1725 tarc |= 1;
1726 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1727 }
1728
581d708e 1729 e1000_config_collision_dist(hw);
1da177e4
LT		 1730
1731 /* Setup Transmit Descriptor Settings for eop descriptor */
6a042dab
JB		 1732 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
1733
1734 /* only set IDE if we are delaying interrupts using the timers */
1735 if (adapter->tx_int_delay)
1736 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
1da177e4 1737
581d708e 1738 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1739 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1740 else
1741 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1742
1743 /* Cache if we're 82544 running in PCI-X because we'll
1744 * need this to apply a workaround later in the send path. */
581d708e
MC		 1745 if (hw->mac_type == e1000_82544 &&
1746 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1747 adapter->pcix_82544 = 1;
7e6c9861
JK		 1748
1749 E1000_WRITE_REG(hw, TCTL, tctl);
1750
1da177e4
LT		 1751}
1752
1753/**
1754 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1755 * @adapter: board private structure
581d708e 1756 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1757 *
1758 * Returns 0 on success, negative on failure
1759 **/
1760
3ad2cc67 1761static int
581d708e
MC		 1762e1000_setup_rx_resources(struct e1000_adapter *adapter,
1763 struct e1000_rx_ring *rxdr)
1da177e4 1764{
1da177e4 1765 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1766 int size, desc_len;
1da177e4
LT		 1767
1768 size = sizeof(struct e1000_buffer) * rxdr->count;
cd94dd0b 1769 rxdr->buffer_info = vmalloc(size);
581d708e 1770 if (!rxdr->buffer_info) {
2648345f
MC		 1771 DPRINTK(PROBE, ERR,
1772 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1773 return -ENOMEM;
1774 }
1775 memset(rxdr->buffer_info, 0, size);
1776
2d7edb92
MC		 1777 size = sizeof(struct e1000_ps_page) * rxdr->count;
1778 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
96838a40 1779 if (!rxdr->ps_page) {
2d7edb92
MC		 1780 vfree(rxdr->buffer_info);
1781 DPRINTK(PROBE, ERR,
1782 "Unable to allocate memory for the receive descriptor ring\n");
1783 return -ENOMEM;
1784 }
1785 memset(rxdr->ps_page, 0, size);
1786
1787 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1788 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
96838a40 1789 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1790 vfree(rxdr->buffer_info);
1791 kfree(rxdr->ps_page);
1792 DPRINTK(PROBE, ERR,
1793 "Unable to allocate memory for the receive descriptor ring\n");
1794 return -ENOMEM;
1795 }
1796 memset(rxdr->ps_page_dma, 0, size);
1797
96838a40 1798 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1799 desc_len = sizeof(struct e1000_rx_desc);
1800 else
1801 desc_len = sizeof(union e1000_rx_desc_packet_split);
1802
1da177e4
LT		 1803 /* Round up to nearest 4K */
1804
2d7edb92 1805 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1806 E1000_ROUNDUP(rxdr->size, 4096);
1807
1808 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1809
581d708e
MC		 1810 if (!rxdr->desc) {
1811 DPRINTK(PROBE, ERR,
1812 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1813setup_rx_desc_die:
1da177e4 1814 vfree(rxdr->buffer_info);
2d7edb92
MC		 1815 kfree(rxdr->ps_page);
1816 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1817 return -ENOMEM;
1818 }
1819
2648345f 1820 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1821 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1822 void *olddesc = rxdr->desc;
1823 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1824 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1825 "at %p\n", rxdr->size, rxdr->desc);
1826 /* Try again, without freeing the previous */
1da177e4 1827 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1828 /* Failed allocation, critical failure */
581d708e 1829 if (!rxdr->desc) {
1da177e4 1830 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1831 DPRINTK(PROBE, ERR,
1832 "Unable to allocate memory "
1833 "for the receive descriptor ring\n");
1da177e4
LT		 1834 goto setup_rx_desc_die;
1835 }
1836
1837 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1838 /* give up */
2648345f
MC		 1839 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1840 rxdr->dma);
1da177e4 1841 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1842 DPRINTK(PROBE, ERR,
1843 "Unable to allocate aligned memory "
1844 "for the receive descriptor ring\n");
581d708e 1845 goto setup_rx_desc_die;
1da177e4 1846 } else {
2648345f 1847 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1848 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1849 }
1850 }
1851 memset(rxdr->desc, 0, rxdr->size);
1852
1853 rxdr->next_to_clean = 0;
1854 rxdr->next_to_use = 0;
1855
1856 return 0;
1857}
1858
581d708e
MC		 1859/**
1860 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1861 * (Descriptors) for all queues
1862 * @adapter: board private structure
1863 *
581d708e
MC		 1864 * Return 0 on success, negative on failure
1865 **/
1866
1867int
1868e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1869{
1870 int i, err = 0;
1871
f56799ea 1872 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1873 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1874 if (err) {
1875 DPRINTK(PROBE, ERR,
1876 "Allocation for Rx Queue %u failed\n", i);
3fbbc72e
VA		 1877 for (i-- ; i >= 0; i--)
1878 e1000_free_rx_resources(adapter,
1879 &adapter->rx_ring[i]);
581d708e
MC		 1880 break;
1881 }
1882 }
1883
1884 return err;
1885}
1886
1da177e4 1887/**
2648345f 1888 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1889 * @adapter: Board private structure
1890 **/
e4c811c9
MC		 1891#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1892 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1893static void
1894e1000_setup_rctl(struct e1000_adapter *adapter)
1895{
2d7edb92
MC		 1896 uint32_t rctl, rfctl;
1897 uint32_t psrctl = 0;
35ec56bb 1898#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1899 uint32_t pages = 0;
1900#endif
1da177e4
LT		 1901
1902 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1903
1904 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1905
1906 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1907 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1908 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1909
0fadb059 1910 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1911 rctl |= E1000_RCTL_SBP;
1912 else
1913 rctl &= ~E1000_RCTL_SBP;
1914
2d7edb92
MC		 1915 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1916 rctl &= ~E1000_RCTL_LPE;
1917 else
1918 rctl |= E1000_RCTL_LPE;
1919
1da177e4 1920 /* Setup buffer sizes */
9e2feace
AK		 1921 rctl &= ~E1000_RCTL_SZ_4096;
1922 rctl |= E1000_RCTL_BSEX;
1923 switch (adapter->rx_buffer_len) {
1924 case E1000_RXBUFFER_256:
1925 rctl |= E1000_RCTL_SZ_256;
1926 rctl &= ~E1000_RCTL_BSEX;
1927 break;
1928 case E1000_RXBUFFER_512:
1929 rctl |= E1000_RCTL_SZ_512;
1930 rctl &= ~E1000_RCTL_BSEX;
1931 break;
1932 case E1000_RXBUFFER_1024:
1933 rctl |= E1000_RCTL_SZ_1024;
1934 rctl &= ~E1000_RCTL_BSEX;
1935 break;
a1415ee6
JK		 1936 case E1000_RXBUFFER_2048:
1937 default:
1938 rctl |= E1000_RCTL_SZ_2048;
1939 rctl &= ~E1000_RCTL_BSEX;
1940 break;
1941 case E1000_RXBUFFER_4096:
1942 rctl |= E1000_RCTL_SZ_4096;
1943 break;
1944 case E1000_RXBUFFER_8192:
1945 rctl |= E1000_RCTL_SZ_8192;
1946 break;
1947 case E1000_RXBUFFER_16384:
1948 rctl |= E1000_RCTL_SZ_16384;
1949 break;
2d7edb92
MC		 1950 }
1951
35ec56bb 1952#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1953 /* 82571 and greater support packet-split where the protocol
1954 * header is placed in skb->data and the packet data is
1955 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1956 * In the case of a non-split, skb->data is linearly filled,
1957 * followed by the page buffers. Therefore, skb->data is
1958 * sized to hold the largest protocol header.
1959 */
e64d7d02
JB		 1960 /* allocations using alloc_page take too long for regular MTU
1961 * so only enable packet split for jumbo frames */
e4c811c9 1962 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
e64d7d02
JB		 1963 if ((adapter->hw.mac_type >= e1000_82571) && (pages <= 3) &&
1964 PAGE_SIZE <= 16384 && (rctl & E1000_RCTL_LPE))
e4c811c9
MC		 1965 adapter->rx_ps_pages = pages;
1966 else
1967 adapter->rx_ps_pages = 0;
2d7edb92 1968#endif
e4c811c9 1969 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1970 /* Configure extra packet-split registers */
1971 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1972 rfctl |= E1000_RFCTL_EXTEN;
87ca4e5b
AK		 1973 /* disable packet split support for IPv6 extension headers,
1974 * because some malformed IPv6 headers can hang the RX */
1975 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
1976 E1000_RFCTL_NEW_IPV6_EXT_DIS);
1977
2d7edb92
MC		 1978 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1979
7dfee0cb 1980 rctl |= E1000_RCTL_DTYP_PS;
96838a40 1981
2d7edb92
MC		 1982 psrctl |= adapter->rx_ps_bsize0 >>
1983 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1984
1985 switch (adapter->rx_ps_pages) {
1986 case 3:
1987 psrctl |= PAGE_SIZE <<
1988 E1000_PSRCTL_BSIZE3_SHIFT;
1989 case 2:
1990 psrctl |= PAGE_SIZE <<
1991 E1000_PSRCTL_BSIZE2_SHIFT;
1992 case 1:
1993 psrctl |= PAGE_SIZE >>
1994 E1000_PSRCTL_BSIZE1_SHIFT;
1995 break;
1996 }
2d7edb92
MC		 1997
1998 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1999 }
2000
2001 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2002}
2003
2004/**
2005 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
2006 * @adapter: board private structure
2007 *
2008 * Configure the Rx unit of the MAC after a reset.
2009 **/
2010
2011static void
2012e1000_configure_rx(struct e1000_adapter *adapter)
2013{
581d708e
MC		 2014 uint64_t rdba;
2015 struct e1000_hw *hw = &adapter->hw;
2016 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 2017
e4c811c9 2018 if (adapter->rx_ps_pages) {
0f15a8fa 2019 /* this is a 32 byte descriptor */
581d708e 2020 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 2021 sizeof(union e1000_rx_desc_packet_split);
2022 adapter->clean_rx = e1000_clean_rx_irq_ps;
2023 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
2024 } else {
581d708e
MC		 2025 rdlen = adapter->rx_ring[0].count *
2026 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 2027 adapter->clean_rx = e1000_clean_rx_irq;
2028 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
2029 }
1da177e4
LT		 2030
2031 /* disable receives while setting up the descriptors */
581d708e
MC		 2032 rctl = E1000_READ_REG(hw, RCTL);
2033 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 2034
2035 /* set the Receive Delay Timer Register */
581d708e 2036 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 2037
581d708e
MC		 2038 if (hw->mac_type >= e1000_82540) {
2039 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
835bb129 2040 if (adapter->itr_setting != 0)
581d708e 2041 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 2042 1000000000 / (adapter->itr * 256));
2043 }
2044
2ae76d98 2045 if (hw->mac_type >= e1000_82571) {
2ae76d98 2046 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 2047 /* Reset delay timers after every interrupt */
6fc7a7ec 2048 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9 2049#ifdef CONFIG_E1000_NAPI
835bb129 2050 /* Auto-Mask interrupts upon ICR access */
1e613fd9 2051 ctrl_ext |= E1000_CTRL_EXT_IAME;
835bb129 2052 E1000_WRITE_REG(hw, IAM, 0xffffffff);
1e613fd9 2053#endif
2ae76d98
MC		 2054 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2055 E1000_WRITE_FLUSH(hw);
2056 }
2057
581d708e
MC		 2058 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2059 * the Base and Length of the Rx Descriptor Ring */
f56799ea 2060 switch (adapter->num_rx_queues) {
24025e4e
MC		 2061 case 1:
2062 default:
581d708e 2063 rdba = adapter->rx_ring[0].dma;
581d708e 2064 E1000_WRITE_REG(hw, RDLEN, rdlen);
4ca213a6
AK		 2065 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
2066 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
581d708e 2067 E1000_WRITE_REG(hw, RDT, 0);
4ca213a6 2068 E1000_WRITE_REG(hw, RDH, 0);
6a951698
AK		 2069 adapter->rx_ring[0].rdh = ((hw->mac_type >= e1000_82543) ? E1000_RDH : E1000_82542_RDH);
2070 adapter->rx_ring[0].rdt = ((hw->mac_type >= e1000_82543) ? E1000_RDT : E1000_82542_RDT);
581d708e 2071 break;
24025e4e
MC		 2072 }
2073
1da177e4 2074 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 2075 if (hw->mac_type >= e1000_82543) {
2076 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 2077 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 2078 rxcsum |= E1000_RXCSUM_TUOFL;
2079
868d5309 2080 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 2081 * Must be used in conjunction with packet-split. */
96838a40
JB		 2082 if ((hw->mac_type >= e1000_82571) &&
2083 (adapter->rx_ps_pages)) {
2d7edb92
MC		 2084 rxcsum |= E1000_RXCSUM_IPPCSE;
2085 }
2086 } else {
2087 rxcsum &= ~E1000_RXCSUM_TUOFL;
2088 /* don't need to clear IPPCSE as it defaults to 0 */
2089 }
581d708e 2090 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 2091 }
2092
21c4d5e0
AK		 2093 /* enable early receives on 82573, only takes effect if using > 2048
2094 * byte total frame size. for example only for jumbo frames */
2095#define E1000_ERT_2048 0x100
2096 if (hw->mac_type == e1000_82573)
2097 E1000_WRITE_REG(hw, ERT, E1000_ERT_2048);
2098
1da177e4 2099 /* Enable Receives */
581d708e 2100 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 2101}
2102
2103/**
581d708e 2104 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 2105 * @adapter: board private structure
581d708e 2106 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 2107 *
2108 * Free all transmit software resources
2109 **/
2110
3ad2cc67 2111static void
581d708e
MC		 2112e1000_free_tx_resources(struct e1000_adapter *adapter,
2113 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 2114{
2115 struct pci_dev *pdev = adapter->pdev;
2116
581d708e 2117 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 2118
581d708e
MC		 2119 vfree(tx_ring->buffer_info);
2120 tx_ring->buffer_info = NULL;
1da177e4 2121
581d708e 2122 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 2123
581d708e
MC		 2124 tx_ring->desc = NULL;
2125}
2126
2127/**
2128 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
2129 * @adapter: board private structure
2130 *
2131 * Free all transmit software resources
2132 **/
2133
2134void
2135e1000_free_all_tx_resources(struct e1000_adapter *adapter)
2136{
2137 int i;
2138
f56799ea 2139 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2140 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2141}
2142
e619d523 2143static void
1da177e4
LT		 2144e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
2145 struct e1000_buffer *buffer_info)
2146{
96838a40 2147 if (buffer_info->dma) {
2648345f
MC		 2148 pci_unmap_page(adapter->pdev,
2149 buffer_info->dma,
2150 buffer_info->length,
2151 PCI_DMA_TODEVICE);
a9ebadd6 2152 buffer_info->dma = 0;
1da177e4 2153 }
a9ebadd6 2154 if (buffer_info->skb) {
1da177e4 2155 dev_kfree_skb_any(buffer_info->skb);
a9ebadd6
JB		 2156 buffer_info->skb = NULL;
2157 }
2158 /* buffer_info must be completely set up in the transmit path */
1da177e4
LT		 2159}
2160
2161/**
2162 * e1000_clean_tx_ring - Free Tx Buffers
2163 * @adapter: board private structure
581d708e 2164 * @tx_ring: ring to be cleaned
1da177e4
LT		 2165 **/
2166
2167static void
581d708e
MC		 2168e1000_clean_tx_ring(struct e1000_adapter *adapter,
2169 struct e1000_tx_ring *tx_ring)
1da177e4 2170{
1da177e4
LT		 2171 struct e1000_buffer *buffer_info;
2172 unsigned long size;
2173 unsigned int i;
2174
2175 /* Free all the Tx ring sk_buffs */
2176
96838a40 2177 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 2178 buffer_info = &tx_ring->buffer_info[i];
2179 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
2180 }
2181
2182 size = sizeof(struct e1000_buffer) * tx_ring->count;
2183 memset(tx_ring->buffer_info, 0, size);
2184
2185 /* Zero out the descriptor ring */
2186
2187 memset(tx_ring->desc, 0, tx_ring->size);
2188
2189 tx_ring->next_to_use = 0;
2190 tx_ring->next_to_clean = 0;
fd803241 2191 tx_ring->last_tx_tso = 0;
1da177e4 2192
581d708e
MC		 2193 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
2194 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
2195}
2196
2197/**
2198 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
2199 * @adapter: board private structure
2200 **/
2201
2202static void
2203e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
2204{
2205 int i;
2206
f56799ea 2207 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2208 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2209}
2210
2211/**
2212 * e1000_free_rx_resources - Free Rx Resources
2213 * @adapter: board private structure
581d708e 2214 * @rx_ring: ring to clean the resources from
1da177e4
LT		 2215 *
2216 * Free all receive software resources
2217 **/
2218
3ad2cc67 2219static void
581d708e
MC		 2220e1000_free_rx_resources(struct e1000_adapter *adapter,
2221 struct e1000_rx_ring *rx_ring)
1da177e4 2222{
1da177e4
LT		 2223 struct pci_dev *pdev = adapter->pdev;
2224
581d708e 2225 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 2226
2227 vfree(rx_ring->buffer_info);
2228 rx_ring->buffer_info = NULL;
2d7edb92
MC		 2229 kfree(rx_ring->ps_page);
2230 rx_ring->ps_page = NULL;
2231 kfree(rx_ring->ps_page_dma);
2232 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 2233
2234 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2235
2236 rx_ring->desc = NULL;
2237}
2238
2239/**
581d708e 2240 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2241 * @adapter: board private structure
581d708e
MC		 2242 *
2243 * Free all receive software resources
2244 **/
2245
2246void
2247e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2248{
2249 int i;
2250
f56799ea 2251 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2252 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2253}
2254
2255/**
2256 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2257 * @adapter: board private structure
2258 * @rx_ring: ring to free buffers from
1da177e4
LT		 2259 **/
2260
2261static void
581d708e
MC		 2262e1000_clean_rx_ring(struct e1000_adapter *adapter,
2263 struct e1000_rx_ring *rx_ring)
1da177e4 2264{
1da177e4 2265 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2266 struct e1000_ps_page *ps_page;
2267 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2268 struct pci_dev *pdev = adapter->pdev;
2269 unsigned long size;
2d7edb92 2270 unsigned int i, j;
1da177e4
LT		 2271
2272 /* Free all the Rx ring sk_buffs */
96838a40 2273 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2274 buffer_info = &rx_ring->buffer_info[i];
96838a40 2275 if (buffer_info->skb) {
1da177e4
LT		 2276 pci_unmap_single(pdev,
2277 buffer_info->dma,
2278 buffer_info->length,
2279 PCI_DMA_FROMDEVICE);
2280
2281 dev_kfree_skb(buffer_info->skb);
2282 buffer_info->skb = NULL;
997f5cbd
JK		 2283 }
2284 ps_page = &rx_ring->ps_page[i];
2285 ps_page_dma = &rx_ring->ps_page_dma[i];
2286 for (j = 0; j < adapter->rx_ps_pages; j++) {
2287 if (!ps_page->ps_page[j]) break;
2288 pci_unmap_page(pdev,
2289 ps_page_dma->ps_page_dma[j],
2290 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2291 ps_page_dma->ps_page_dma[j] = 0;
2292 put_page(ps_page->ps_page[j]);
2293 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2294 }
2295 }
2296
2297 size = sizeof(struct e1000_buffer) * rx_ring->count;
2298 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2299 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2300 memset(rx_ring->ps_page, 0, size);
2301 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2302 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2303
2304 /* Zero out the descriptor ring */
2305
2306 memset(rx_ring->desc, 0, rx_ring->size);
2307
2308 rx_ring->next_to_clean = 0;
2309 rx_ring->next_to_use = 0;
2310
581d708e
MC		 2311 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2312 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2313}
2314
2315/**
2316 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2317 * @adapter: board private structure
2318 **/
2319
2320static void
2321e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2322{
2323 int i;
2324
f56799ea 2325 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2326 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2327}
2328
2329/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2330 * and memory write and invalidate disabled for certain operations
2331 */
2332static void
2333e1000_enter_82542_rst(struct e1000_adapter *adapter)
2334{
2335 struct net_device *netdev = adapter->netdev;
2336 uint32_t rctl;
2337
2338 e1000_pci_clear_mwi(&adapter->hw);
2339
2340 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2341 rctl |= E1000_RCTL_RST;
2342 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2343 E1000_WRITE_FLUSH(&adapter->hw);
2344 mdelay(5);
2345
96838a40 2346 if (netif_running(netdev))
581d708e 2347 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2348}
2349
2350static void
2351e1000_leave_82542_rst(struct e1000_adapter *adapter)
2352{
2353 struct net_device *netdev = adapter->netdev;
2354 uint32_t rctl;
2355
2356 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2357 rctl &= ~E1000_RCTL_RST;
2358 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2359 E1000_WRITE_FLUSH(&adapter->hw);
2360 mdelay(5);
2361
96838a40 2362 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2363 e1000_pci_set_mwi(&adapter->hw);
2364
96838a40 2365 if (netif_running(netdev)) {
72d64a43
JK		 2366 /* No need to loop, because 82542 supports only 1 queue */
2367 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2368 e1000_configure_rx(adapter);
72d64a43 2369 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2370 }
2371}
2372
2373/**
2374 * e1000_set_mac - Change the Ethernet Address of the NIC
2375 * @netdev: network interface device structure
2376 * @p: pointer to an address structure
2377 *
2378 * Returns 0 on success, negative on failure
2379 **/
2380
2381static int
2382e1000_set_mac(struct net_device *netdev, void *p)
2383{
60490fe0 2384 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2385 struct sockaddr *addr = p;
2386
96838a40 2387 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2388 return -EADDRNOTAVAIL;
2389
2390 /* 82542 2.0 needs to be in reset to write receive address registers */
2391
96838a40 2392 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2393 e1000_enter_82542_rst(adapter);
2394
2395 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2396 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2397
2398 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2399
868d5309
MC		 2400 /* With 82571 controllers, LAA may be overwritten (with the default)
2401 * due to controller reset from the other port. */
2402 if (adapter->hw.mac_type == e1000_82571) {
2403 /* activate the work around */
2404 adapter->hw.laa_is_present = 1;
2405
96838a40
JB		 2406 /* Hold a copy of the LAA in RAR[14] This is done so that
2407 * between the time RAR[0] gets clobbered and the time it
2408 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2409 * of the RARs and no incoming packets directed to this port
96838a40 2410 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2411 * RAR[14] */
96838a40 2412 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2413 E1000_RAR_ENTRIES - 1);
2414 }
2415
96838a40 2416 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2417 e1000_leave_82542_rst(adapter);
2418
2419 return 0;
2420}
2421
2422/**
2423 * e1000_set_multi - Multicast and Promiscuous mode set
2424 * @netdev: network interface device structure
2425 *
2426 * The set_multi entry point is called whenever the multicast address
2427 * list or the network interface flags are updated. This routine is
2428 * responsible for configuring the hardware for proper multicast,
2429 * promiscuous mode, and all-multi behavior.
2430 **/
2431
2432static void
2433e1000_set_multi(struct net_device *netdev)
2434{
60490fe0 2435 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2436 struct e1000_hw *hw = &adapter->hw;
2437 struct dev_mc_list *mc_ptr;
2438 uint32_t rctl;
2439 uint32_t hash_value;
868d5309 2440 int i, rar_entries = E1000_RAR_ENTRIES;
cd94dd0b
AK		 2441 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2442 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2443 E1000_NUM_MTA_REGISTERS;
2444
2445 if (adapter->hw.mac_type == e1000_ich8lan)
2446 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
1da177e4 2447
868d5309
MC		 2448 /* reserve RAR[14] for LAA over-write work-around */
2449 if (adapter->hw.mac_type == e1000_82571)
2450 rar_entries--;
1da177e4 2451
2648345f
MC		 2452 /* Check for Promiscuous and All Multicast modes */
2453
1da177e4
LT		 2454 rctl = E1000_READ_REG(hw, RCTL);
2455
96838a40 2456 if (netdev->flags & IFF_PROMISC) {
1da177e4 2457 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2458 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2459 rctl |= E1000_RCTL_MPE;
2460 rctl &= ~E1000_RCTL_UPE;
2461 } else {
2462 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2463 }
2464
2465 E1000_WRITE_REG(hw, RCTL, rctl);
2466
2467 /* 82542 2.0 needs to be in reset to write receive address registers */
2468
96838a40 2469 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2470 e1000_enter_82542_rst(adapter);
2471
2472 /* load the first 14 multicast address into the exact filters 1-14
2473 * RAR 0 is used for the station MAC adddress
2474 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2475 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2476 */
2477 mc_ptr = netdev->mc_list;
2478
96838a40 2479 for (i = 1; i < rar_entries; i++) {
868d5309 2480 if (mc_ptr) {
1da177e4
LT		 2481 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2482 mc_ptr = mc_ptr->next;
2483 } else {
2484 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
4ca213a6 2485 E1000_WRITE_FLUSH(hw);
1da177e4 2486 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
4ca213a6 2487 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 2488 }
2489 }
2490
2491 /* clear the old settings from the multicast hash table */
2492
cd94dd0b 2493 for (i = 0; i < mta_reg_count; i++) {
1da177e4 2494 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 2495 E1000_WRITE_FLUSH(hw);
2496 }
1da177e4
LT		 2497
2498 /* load any remaining addresses into the hash table */
2499
96838a40 2500 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2501 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2502 e1000_mta_set(hw, hash_value);
2503 }
2504
96838a40 2505 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2506 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2507}
2508
2509/* Need to wait a few seconds after link up to get diagnostic information from
2510 * the phy */
2511
2512static void
2513e1000_update_phy_info(unsigned long data)
2514{
2515 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2516 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2517}
2518
2519/**
2520 * e1000_82547_tx_fifo_stall - Timer Call-back
2521 * @data: pointer to adapter cast into an unsigned long
2522 **/
2523
2524static void
2525e1000_82547_tx_fifo_stall(unsigned long data)
2526{
2527 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2528 struct net_device *netdev = adapter->netdev;
2529 uint32_t tctl;
2530
96838a40
JB		 2531 if (atomic_read(&adapter->tx_fifo_stall)) {
2532 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2533 E1000_READ_REG(&adapter->hw, TDH)) &&
2534 (E1000_READ_REG(&adapter->hw, TDFT) ==
2535 E1000_READ_REG(&adapter->hw, TDFH)) &&
2536 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2537 E1000_READ_REG(&adapter->hw, TDFHS))) {
2538 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2539 E1000_WRITE_REG(&adapter->hw, TCTL,
2540 tctl & ~E1000_TCTL_EN);
2541 E1000_WRITE_REG(&adapter->hw, TDFT,
2542 adapter->tx_head_addr);
2543 E1000_WRITE_REG(&adapter->hw, TDFH,
2544 adapter->tx_head_addr);
2545 E1000_WRITE_REG(&adapter->hw, TDFTS,
2546 adapter->tx_head_addr);
2547 E1000_WRITE_REG(&adapter->hw, TDFHS,
2548 adapter->tx_head_addr);
2549 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2550 E1000_WRITE_FLUSH(&adapter->hw);
2551
2552 adapter->tx_fifo_head = 0;
2553 atomic_set(&adapter->tx_fifo_stall, 0);
2554 netif_wake_queue(netdev);
2555 } else {
2556 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2557 }
2558 }
2559}
2560
2561/**
2562 * e1000_watchdog - Timer Call-back
2563 * @data: pointer to adapter cast into an unsigned long
2564 **/
2565static void
2566e1000_watchdog(unsigned long data)
2567{
2568 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1da177e4 2569 struct net_device *netdev = adapter->netdev;
545c67c0 2570 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2571 uint32_t link, tctl;
cd94dd0b
AK		 2572 int32_t ret_val;
2573
2574 ret_val = e1000_check_for_link(&adapter->hw);
2575 if ((ret_val == E1000_ERR_PHY) &&
2576 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2577 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2578 /* See e1000_kumeran_lock_loss_workaround() */
2579 DPRINTK(LINK, INFO,
2580 "Gigabit has been disabled, downgrading speed\n");
2581 }
90fb5135 2582
2d7edb92
MC		 2583 if (adapter->hw.mac_type == e1000_82573) {
2584 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2585 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2586 e1000_update_mng_vlan(adapter);
96838a40 2587 }
1da177e4 2588
96838a40 2589 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2590 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2591 link = !adapter->hw.serdes_link_down;
2592 else
2593 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2594
96838a40
JB		 2595 if (link) {
2596 if (!netif_carrier_ok(netdev)) {
9669f53b 2597 uint32_t ctrl;
fe7fe28e 2598 boolean_t txb2b = 1;
1da177e4
LT		 2599 e1000_get_speed_and_duplex(&adapter->hw,
2600 &adapter->link_speed,
2601 &adapter->link_duplex);
2602
9669f53b
AK		 2603 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
2604 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s, "
2605 "Flow Control: %s\n",
2606 adapter->link_speed,
2607 adapter->link_duplex == FULL_DUPLEX ?
2608 "Full Duplex" : "Half Duplex",
2609 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2610 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2611 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2612 E1000_CTRL_TFCE) ? "TX" : "None" )));
1da177e4 2613
7e6c9861
JK		 2614 /* tweak tx_queue_len according to speed/duplex
2615 * and adjust the timeout factor */
66a2b0a3
JK		 2616 netdev->tx_queue_len = adapter->tx_queue_len;
2617 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2618 switch (adapter->link_speed) {
2619 case SPEED_10:
fe7fe28e 2620 txb2b = 0;
7e6c9861
JK		 2621 netdev->tx_queue_len = 10;
2622 adapter->tx_timeout_factor = 8;
2623 break;
2624 case SPEED_100:
fe7fe28e 2625 txb2b = 0;
7e6c9861
JK		 2626 netdev->tx_queue_len = 100;
2627 /* maybe add some timeout factor ? */
2628 break;
2629 }
2630
fe7fe28e 2631 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2632 adapter->hw.mac_type == e1000_82572) &&
fe7fe28e 2633 txb2b == 0) {
7e6c9861
JK		 2634 uint32_t tarc0;
2635 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
90fb5135 2636 tarc0 &= ~(1 << 21);
7e6c9861
JK		 2637 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2638 }
90fb5135 2639
7e6c9861
JK		 2640 /* disable TSO for pcie and 10/100 speeds, to avoid
2641 * some hardware issues */
2642 if (!adapter->tso_force &&
2643 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2644 switch (adapter->link_speed) {
2645 case SPEED_10:
66a2b0a3 2646 case SPEED_100:
7e6c9861
JK		 2647 DPRINTK(PROBE,INFO,
2648 "10/100 speed: disabling TSO\n");
2649 netdev->features &= ~NETIF_F_TSO;
87ca4e5b 2650 netdev->features &= ~NETIF_F_TSO6;
7e6c9861
JK		 2651 break;
2652 case SPEED_1000:
2653 netdev->features |= NETIF_F_TSO;
87ca4e5b 2654 netdev->features |= NETIF_F_TSO6;
7e6c9861
JK		 2655 break;
2656 default:
2657 /* oops */
66a2b0a3
JK		 2658 break;
2659 }
2660 }
7e6c9861
JK		 2661
2662 /* enable transmits in the hardware, need to do this
2663 * after setting TARC0 */
2664 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2665 tctl |= E1000_TCTL_EN;
2666 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2667
1da177e4
LT		 2668 netif_carrier_on(netdev);
2669 netif_wake_queue(netdev);
2670 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2671 adapter->smartspeed = 0;
bb8e3311
JG		 2672 } else {
2673 /* make sure the receive unit is started */
2674 if (adapter->hw.rx_needs_kicking) {
2675 struct e1000_hw *hw = &adapter->hw;
2676 uint32_t rctl = E1000_READ_REG(hw, RCTL);
2677 E1000_WRITE_REG(hw, RCTL, rctl | E1000_RCTL_EN);
2678 }
1da177e4
LT		 2679 }
2680 } else {
96838a40 2681 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2682 adapter->link_speed = 0;
2683 adapter->link_duplex = 0;
2684 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2685 netif_carrier_off(netdev);
2686 netif_stop_queue(netdev);
2687 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
87041639
JK		 2688
2689 /* 80003ES2LAN workaround--
2690 * For packet buffer work-around on link down event;
2691 * disable receives in the ISR and
2692 * reset device here in the watchdog
2693 */
8fc897b0 2694 if (adapter->hw.mac_type == e1000_80003es2lan)
87041639
JK		 2695 /* reset device */
2696 schedule_work(&adapter->reset_task);
1da177e4
LT		 2697 }
2698
2699 e1000_smartspeed(adapter);
2700 }
2701
2702 e1000_update_stats(adapter);
2703
2704 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2705 adapter->tpt_old = adapter->stats.tpt;
2706 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2707 adapter->colc_old = adapter->stats.colc;
2708
2709 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2710 adapter->gorcl_old = adapter->stats.gorcl;
2711 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2712 adapter->gotcl_old = adapter->stats.gotcl;
2713
2714 e1000_update_adaptive(&adapter->hw);
2715
f56799ea 2716 if (!netif_carrier_ok(netdev)) {
581d708e 2717 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2718 /* We've lost link, so the controller stops DMA,
2719 * but we've got queued Tx work that's never going
2720 * to get done, so reset controller to flush Tx.
2721 * (Do the reset outside of interrupt context). */
87041639
JK		 2722 adapter->tx_timeout_count++;
2723 schedule_work(&adapter->reset_task);
1da177e4
LT		 2724 }
2725 }
2726
1da177e4
LT		 2727 /* Cause software interrupt to ensure rx ring is cleaned */
2728 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2729
2648345f 2730 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2731 adapter->detect_tx_hung = TRUE;
2732
96838a40 2733 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2734 * reset from the other port. Set the appropriate LAA in RAR[0] */
2735 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2736 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2737
1da177e4
LT		 2738 /* Reset the timer */
2739 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2740}
2741
835bb129
JB		 2742enum latency_range {
2743 lowest_latency = 0,
2744 low_latency = 1,
2745 bulk_latency = 2,
2746 latency_invalid = 255
2747};
2748
2749/**
2750 * e1000_update_itr - update the dynamic ITR value based on statistics
2751 * Stores a new ITR value based on packets and byte
2752 * counts during the last interrupt. The advantage of per interrupt
2753 * computation is faster updates and more accurate ITR for the current
2754 * traffic pattern. Constants in this function were computed
2755 * based on theoretical maximum wire speed and thresholds were set based
2756 * on testing data as well as attempting to minimize response time
2757 * while increasing bulk throughput.
2758 * this functionality is controlled by the InterruptThrottleRate module
2759 * parameter (see e1000_param.c)
2760 * @adapter: pointer to adapter
2761 * @itr_setting: current adapter->itr
2762 * @packets: the number of packets during this measurement interval
2763 * @bytes: the number of bytes during this measurement interval
2764 **/
2765static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2766 uint16_t itr_setting,
2767 int packets,
2768 int bytes)
2769{
2770 unsigned int retval = itr_setting;
2771 struct e1000_hw *hw = &adapter->hw;
2772
2773 if (unlikely(hw->mac_type < e1000_82540))
2774 goto update_itr_done;
2775
2776 if (packets == 0)
2777 goto update_itr_done;
2778
835bb129
JB		 2779 switch (itr_setting) {
2780 case lowest_latency:
2b65326e
JB		 2781 /* jumbo frames get bulk treatment*/
2782 if (bytes/packets > 8000)
2783 retval = bulk_latency;
2784 else if ((packets < 5) && (bytes > 512))
835bb129
JB		 2785 retval = low_latency;
2786 break;
2787 case low_latency: /* 50 usec aka 20000 ints/s */
2788 if (bytes > 10000) {
2b65326e
JB		 2789 /* jumbo frames need bulk latency setting */
2790 if (bytes/packets > 8000)
2791 retval = bulk_latency;
2792 else if ((packets < 10) || ((bytes/packets) > 1200))
835bb129
JB		 2793 retval = bulk_latency;
2794 else if ((packets > 35))
2795 retval = lowest_latency;
2b65326e
JB		 2796 } else if (bytes/packets > 2000)
2797 retval = bulk_latency;
2798 else if (packets <= 2 && bytes < 512)
835bb129
JB		 2799 retval = lowest_latency;
2800 break;
2801 case bulk_latency: /* 250 usec aka 4000 ints/s */
2802 if (bytes > 25000) {
2803 if (packets > 35)
2804 retval = low_latency;
2b65326e
JB		 2805 } else if (bytes < 6000) {
2806 retval = low_latency;
835bb129
JB		 2807 }
2808 break;
2809 }
2810
2811update_itr_done:
2812 return retval;
2813}
2814
2815static void e1000_set_itr(struct e1000_adapter *adapter)
2816{
2817 struct e1000_hw *hw = &adapter->hw;
2818 uint16_t current_itr;
2819 uint32_t new_itr = adapter->itr;
2820
2821 if (unlikely(hw->mac_type < e1000_82540))
2822 return;
2823
2824 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2825 if (unlikely(adapter->link_speed != SPEED_1000)) {
2826 current_itr = 0;
2827 new_itr = 4000;
2828 goto set_itr_now;
2829 }
2830
2831 adapter->tx_itr = e1000_update_itr(adapter,
2832 adapter->tx_itr,
2833 adapter->total_tx_packets,
2834 adapter->total_tx_bytes);
2b65326e
JB		 2835 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2836 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2837 adapter->tx_itr = low_latency;
2838
835bb129
JB		 2839 adapter->rx_itr = e1000_update_itr(adapter,
2840 adapter->rx_itr,
2841 adapter->total_rx_packets,
2842 adapter->total_rx_bytes);
2b65326e
JB		 2843 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2844 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2845 adapter->rx_itr = low_latency;
835bb129
JB		 2846
2847 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2848
835bb129
JB		 2849 switch (current_itr) {
2850 /* counts and packets in update_itr are dependent on these numbers */
2851 case lowest_latency:
2852 new_itr = 70000;
2853 break;
2854 case low_latency:
2855 new_itr = 20000; /* aka hwitr = ~200 */
2856 break;
2857 case bulk_latency:
2858 new_itr = 4000;
2859 break;
2860 default:
2861 break;
2862 }
2863
2864set_itr_now:
2865 if (new_itr != adapter->itr) {
2866 /* this attempts to bias the interrupt rate towards Bulk
2867 * by adding intermediate steps when interrupt rate is
2868 * increasing */
2869 new_itr = new_itr > adapter->itr ?
2870 min(adapter->itr + (new_itr >> 2), new_itr) :
2871 new_itr;
2872 adapter->itr = new_itr;
2873 E1000_WRITE_REG(hw, ITR, 1000000000 / (new_itr * 256));
2874 }
2875
2876 return;
2877}
2878
1da177e4
LT		 2879#define E1000_TX_FLAGS_CSUM 0x00000001
2880#define E1000_TX_FLAGS_VLAN 0x00000002
2881#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2882#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2883#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2884#define E1000_TX_FLAGS_VLAN_SHIFT 16
2885
e619d523 2886static int
581d708e
MC		 2887e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2888 struct sk_buff *skb)
1da177e4 2889{
1da177e4 2890 struct e1000_context_desc *context_desc;
545c67c0 2891 struct e1000_buffer *buffer_info;
1da177e4
LT		 2892 unsigned int i;
2893 uint32_t cmd_length = 0;
2d7edb92 2894 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2895 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2896 int err;
2897
89114afd 2898 if (skb_is_gso(skb)) {
1da177e4
LT		 2899 if (skb_header_cloned(skb)) {
2900 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2901 if (err)
2902 return err;
2903 }
2904
2905 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
7967168c 2906 mss = skb_shinfo(skb)->gso_size;
60828236 2907 if (skb->protocol == htons(ETH_P_IP)) {
2d7edb92
MC		 2908 skb->nh.iph->tot_len = 0;
2909 skb->nh.iph->check = 0;
2910 skb->h.th->check =
2911 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2912 skb->nh.iph->daddr,
2913 0,
2914 IPPROTO_TCP,
2915 0);
2916 cmd_length = E1000_TXD_CMD_IP;
2917 ipcse = skb->h.raw - skb->data - 1;
e15fdd03 2918 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2d7edb92
MC		 2919 skb->nh.ipv6h->payload_len = 0;
2920 skb->h.th->check =
2921 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2922 &skb->nh.ipv6h->daddr,
2923 0,
2924 IPPROTO_TCP,
2925 0);
2926 ipcse = 0;
2d7edb92 2927 }
1da177e4
LT		 2928 ipcss = skb->nh.raw - skb->data;
2929 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2930 tucss = skb->h.raw - skb->data;
2931 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2932 tucse = 0;
2933
2934 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2935 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2936
581d708e
MC		 2937 i = tx_ring->next_to_use;
2938 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2939 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2940
2941 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2942 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2943 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2944 context_desc->upper_setup.tcp_fields.tucss = tucss;
2945 context_desc->upper_setup.tcp_fields.tucso = tucso;
2946 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2947 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2948 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2949 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2950
545c67c0 2951 buffer_info->time_stamp = jiffies;
a9ebadd6 2952 buffer_info->next_to_watch = i;
545c67c0 2953
581d708e
MC		 2954 if (++i == tx_ring->count) i = 0;
2955 tx_ring->next_to_use = i;
1da177e4 2956
8241e35e 2957 return TRUE;
1da177e4 2958 }
8241e35e 2959 return FALSE;
1da177e4
LT		 2960}
2961
e619d523 2962static boolean_t
581d708e
MC		 2963e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2964 struct sk_buff *skb)
1da177e4
LT		 2965{
2966 struct e1000_context_desc *context_desc;
545c67c0 2967 struct e1000_buffer *buffer_info;
1da177e4
LT		 2968 unsigned int i;
2969 uint8_t css;
2970
84fa7933 2971 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1da177e4
LT		 2972 css = skb->h.raw - skb->data;
2973
581d708e 2974 i = tx_ring->next_to_use;
545c67c0 2975 buffer_info = &tx_ring->buffer_info[i];
581d708e 2976 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4 2977
f6c57baf 2978 context_desc->lower_setup.ip_config = 0;
1da177e4 2979 context_desc->upper_setup.tcp_fields.tucss = css;
f6c57baf 2980 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
1da177e4
LT		 2981 context_desc->upper_setup.tcp_fields.tucse = 0;
2982 context_desc->tcp_seg_setup.data = 0;
2983 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2984
545c67c0 2985 buffer_info->time_stamp = jiffies;
a9ebadd6 2986 buffer_info->next_to_watch = i;
545c67c0 2987
581d708e
MC		 2988 if (unlikely(++i == tx_ring->count)) i = 0;
2989 tx_ring->next_to_use = i;
1da177e4
LT		 2990
2991 return TRUE;
2992 }
2993
2994 return FALSE;
2995}
2996
2997#define E1000_MAX_TXD_PWR 12
2998#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2999
e619d523 3000static int
581d708e
MC		 3001e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
3002 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
3003 unsigned int nr_frags, unsigned int mss)
1da177e4 3004{
1da177e4
LT		 3005 struct e1000_buffer *buffer_info;
3006 unsigned int len = skb->len;
3007 unsigned int offset = 0, size, count = 0, i;
3008 unsigned int f;
3009 len -= skb->data_len;
3010
3011 i = tx_ring->next_to_use;
3012
96838a40 3013 while (len) {
1da177e4
LT		 3014 buffer_info = &tx_ring->buffer_info[i];
3015 size = min(len, max_per_txd);
fd803241
JK		 3016 /* Workaround for Controller erratum --
3017 * descriptor for non-tso packet in a linear SKB that follows a
3018 * tso gets written back prematurely before the data is fully
0f15a8fa 3019 * DMA'd to the controller */
fd803241 3020 if (!skb->data_len && tx_ring->last_tx_tso &&
89114afd 3021 !skb_is_gso(skb)) {
fd803241
JK		 3022 tx_ring->last_tx_tso = 0;
3023 size -= 4;
3024 }
3025
1da177e4
LT		 3026 /* Workaround for premature desc write-backs
3027 * in TSO mode. Append 4-byte sentinel desc */
96838a40 3028 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4 3029 size -= 4;
97338bde
MC		 3030 /* work-around for errata 10 and it applies
3031 * to all controllers in PCI-X mode
3032 * The fix is to make sure that the first descriptor of a
3033 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
3034 */
96838a40 3035 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3036 (size > 2015) && count == 0))
3037 size = 2015;
96838a40 3038
1da177e4
LT		 3039 /* Workaround for potential 82544 hang in PCI-X. Avoid
3040 * terminating buffers within evenly-aligned dwords. */
96838a40 3041 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 3042 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
3043 size > 4))
3044 size -= 4;
3045
3046 buffer_info->length = size;
3047 buffer_info->dma =
3048 pci_map_single(adapter->pdev,
3049 skb->data + offset,
3050 size,
3051 PCI_DMA_TODEVICE);
3052 buffer_info->time_stamp = jiffies;
a9ebadd6 3053 buffer_info->next_to_watch = i;
1da177e4
LT		 3054
3055 len -= size;
3056 offset += size;
3057 count++;
96838a40 3058 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3059 }
3060
96838a40 3061 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 3062 struct skb_frag_struct *frag;
3063
3064 frag = &skb_shinfo(skb)->frags[f];
3065 len = frag->size;
3066 offset = frag->page_offset;
3067
96838a40 3068 while (len) {
1da177e4
LT		 3069 buffer_info = &tx_ring->buffer_info[i];
3070 size = min(len, max_per_txd);
1da177e4
LT		 3071 /* Workaround for premature desc write-backs
3072 * in TSO mode. Append 4-byte sentinel desc */
96838a40 3073 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4 3074 size -= 4;
1da177e4
LT		 3075 /* Workaround for potential 82544 hang in PCI-X.
3076 * Avoid terminating buffers within evenly-aligned
3077 * dwords. */
96838a40 3078 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 3079 !((unsigned long)(frag->page+offset+size-1) & 4) &&
3080 size > 4))
3081 size -= 4;
3082
3083 buffer_info->length = size;
3084 buffer_info->dma =
3085 pci_map_page(adapter->pdev,
3086 frag->page,
3087 offset,
3088 size,
3089 PCI_DMA_TODEVICE);
3090 buffer_info->time_stamp = jiffies;
a9ebadd6 3091 buffer_info->next_to_watch = i;
1da177e4
LT		 3092
3093 len -= size;
3094 offset += size;
3095 count++;
96838a40 3096 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3097 }
3098 }
3099
3100 i = (i == 0) ? tx_ring->count - 1 : i - 1;
3101 tx_ring->buffer_info[i].skb = skb;
3102 tx_ring->buffer_info[first].next_to_watch = i;
3103
3104 return count;
3105}
3106
e619d523 3107static void
581d708e
MC		 3108e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
3109 int tx_flags, int count)
1da177e4 3110{
1da177e4
LT		 3111 struct e1000_tx_desc *tx_desc = NULL;
3112 struct e1000_buffer *buffer_info;
3113 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
3114 unsigned int i;
3115
96838a40 3116 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 3117 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
3118 E1000_TXD_CMD_TSE;
2d7edb92
MC		 3119 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
3120
96838a40 3121 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 3122 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 3123 }
3124
96838a40 3125 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 3126 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
3127 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
3128 }
3129
96838a40 3130 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 3131 txd_lower |= E1000_TXD_CMD_VLE;
3132 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
3133 }
3134
3135 i = tx_ring->next_to_use;
3136
96838a40 3137 while (count--) {
1da177e4
LT		 3138 buffer_info = &tx_ring->buffer_info[i];
3139 tx_desc = E1000_TX_DESC(*tx_ring, i);
3140 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3141 tx_desc->lower.data =
3142 cpu_to_le32(txd_lower | buffer_info->length);
3143 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 3144 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3145 }
3146
3147 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
3148
3149 /* Force memory writes to complete before letting h/w
3150 * know there are new descriptors to fetch. (Only
3151 * applicable for weak-ordered memory model archs,
3152 * such as IA-64). */
3153 wmb();
3154
3155 tx_ring->next_to_use = i;
581d708e 3156 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
2ce9047f
JB		 3157 /* we need this if more than one processor can write to our tail
3158 * at a time, it syncronizes IO on IA64/Altix systems */
3159 mmiowb();
1da177e4
LT		 3160}
3161
3162/**
3163 * 82547 workaround to avoid controller hang in half-duplex environment.
3164 * The workaround is to avoid queuing a large packet that would span
3165 * the internal Tx FIFO ring boundary by notifying the stack to resend
3166 * the packet at a later time. This gives the Tx FIFO an opportunity to
3167 * flush all packets. When that occurs, we reset the Tx FIFO pointers
3168 * to the beginning of the Tx FIFO.
3169 **/
3170
3171#define E1000_FIFO_HDR 0x10
3172#define E1000_82547_PAD_LEN 0x3E0
3173
e619d523 3174static int
1da177e4
LT		 3175e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
3176{
3177 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
3178 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
3179
3180 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
3181
96838a40 3182 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 3183 goto no_fifo_stall_required;
3184
96838a40 3185 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 3186 return 1;
3187
96838a40 3188 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 3189 atomic_set(&adapter->tx_fifo_stall, 1);
3190 return 1;
3191 }
3192
3193no_fifo_stall_required:
3194 adapter->tx_fifo_head += skb_fifo_len;
96838a40 3195 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 3196 adapter->tx_fifo_head -= adapter->tx_fifo_size;
3197 return 0;
3198}
3199
2d7edb92 3200#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 3201static int
2d7edb92
MC		 3202e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
3203{
3204 struct e1000_hw *hw = &adapter->hw;
3205 uint16_t length, offset;
96838a40
JB		 3206 if (vlan_tx_tag_present(skb)) {
3207 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 3208 ( adapter->hw.mng_cookie.status &
3209 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
3210 return 0;
3211 }
20a44028 3212 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 3213 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 3214 if ((htons(ETH_P_IP) == eth->h_proto)) {
3215 const struct iphdr *ip =
2d7edb92 3216 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 3217 if (IPPROTO_UDP == ip->protocol) {
3218 struct udphdr *udp =
3219 (struct udphdr *)((uint8_t *)ip +
2d7edb92 3220 (ip->ihl << 2));
96838a40 3221 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 3222 offset = (uint8_t *)udp + 8 - skb->data;
3223 length = skb->len - offset;
3224
3225 return e1000_mng_write_dhcp_info(hw,
96838a40 3226 (uint8_t *)udp + 8,
2d7edb92
MC		 3227 length);
3228 }
3229 }
3230 }
3231 }
3232 return 0;
3233}
3234
65c7973f
JB		 3235static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
3236{
3237 struct e1000_adapter *adapter = netdev_priv(netdev);
3238 struct e1000_tx_ring *tx_ring = adapter->tx_ring;
3239
3240 netif_stop_queue(netdev);
3241 /* Herbert's original patch had:
3242 * smp_mb__after_netif_stop_queue();
3243 * but since that doesn't exist yet, just open code it. */
3244 smp_mb();
3245
3246 /* We need to check again in a case another CPU has just
3247 * made room available. */
3248 if (likely(E1000_DESC_UNUSED(tx_ring) < size))
3249 return -EBUSY;
3250
3251 /* A reprieve! */
3252 netif_start_queue(netdev);
fcfb1224 3253 ++adapter->restart_queue;
65c7973f
JB		 3254 return 0;
3255}
3256
3257static int e1000_maybe_stop_tx(struct net_device *netdev,
3258 struct e1000_tx_ring *tx_ring, int size)
3259{
3260 if (likely(E1000_DESC_UNUSED(tx_ring) >= size))
3261 return 0;
3262 return __e1000_maybe_stop_tx(netdev, size);
3263}
3264
1da177e4
LT		 3265#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
3266static int
3267e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3268{
60490fe0 3269 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 3270 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 3271 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
3272 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
3273 unsigned int tx_flags = 0;
3274 unsigned int len = skb->len;
3275 unsigned long flags;
3276 unsigned int nr_frags = 0;
3277 unsigned int mss = 0;
3278 int count = 0;
76c224bc 3279 int tso;
1da177e4
LT		 3280 unsigned int f;
3281 len -= skb->data_len;
3282
65c7973f
JB		 3283 /* This goes back to the question of how to logically map a tx queue
3284 * to a flow. Right now, performance is impacted slightly negatively
3285 * if using multiple tx queues. If the stack breaks away from a
3286 * single qdisc implementation, we can look at this again. */
581d708e 3287 tx_ring = adapter->tx_ring;
24025e4e 3288
581d708e 3289 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 3290 dev_kfree_skb_any(skb);
3291 return NETDEV_TX_OK;
3292 }
3293
032fe6e9
JB		 3294 /* 82571 and newer doesn't need the workaround that limited descriptor
3295 * length to 4kB */
3296 if (adapter->hw.mac_type >= e1000_82571)
3297 max_per_txd = 8192;
3298
7967168c 3299 mss = skb_shinfo(skb)->gso_size;
76c224bc 3300 /* The controller does a simple calculation to
1da177e4
LT		 3301 * make sure there is enough room in the FIFO before
3302 * initiating the DMA for each buffer. The calc is:
3303 * 4 = ceil(buffer len/mss). To make sure we don't
3304 * overrun the FIFO, adjust the max buffer len if mss
3305 * drops. */
96838a40 3306 if (mss) {
9a3056da 3307 uint8_t hdr_len;
1da177e4
LT		 3308 max_per_txd = min(mss << 2, max_per_txd);
3309 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 3310
90fb5135
AK		 3311 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
3312 * points to just header, pull a few bytes of payload from
3313 * frags into skb->data */
9a3056da 3314 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
9f687888
JK		 3315 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
3316 switch (adapter->hw.mac_type) {
3317 unsigned int pull_size;
683a2aa3
HX		 3318 case e1000_82544:
3319 /* Make sure we have room to chop off 4 bytes,
3320 * and that the end alignment will work out to
3321 * this hardware's requirements
3322 * NOTE: this is a TSO only workaround
3323 * if end byte alignment not correct move us
3324 * into the next dword */
3325 if ((unsigned long)(skb->tail - 1) & 4)
3326 break;
3327 /* fall through */
9f687888
JK		 3328 case e1000_82571:
3329 case e1000_82572:
3330 case e1000_82573:
cd94dd0b 3331 case e1000_ich8lan:
9f687888
JK		 3332 pull_size = min((unsigned int)4, skb->data_len);
3333 if (!__pskb_pull_tail(skb, pull_size)) {
a5eafce2 3334 DPRINTK(DRV, ERR,
9f687888
JK		 3335 "__pskb_pull_tail failed.\n");
3336 dev_kfree_skb_any(skb);
749dfc70 3337 return NETDEV_TX_OK;
9f687888
JK		 3338 }
3339 len = skb->len - skb->data_len;
3340 break;
3341 default:
3342 /* do nothing */
3343 break;
d74bbd3b 3344 }
9a3056da 3345 }
1da177e4
LT		 3346 }
3347
9a3056da 3348 /* reserve a descriptor for the offload context */
84fa7933 3349 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
1da177e4 3350 count++;
2648345f 3351 count++;
fd803241 3352
fd803241 3353 /* Controller Erratum workaround */
89114afd 3354 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
fd803241 3355 count++;
fd803241 3356
1da177e4
LT		 3357 count += TXD_USE_COUNT(len, max_txd_pwr);
3358
96838a40 3359 if (adapter->pcix_82544)
1da177e4
LT		 3360 count++;
3361
96838a40 3362 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 3363 * in PCI-X mode, so add one more descriptor to the count
3364 */
96838a40 3365 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3366 (len > 2015)))
3367 count++;
3368
1da177e4 3369 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 3370 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 3371 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
3372 max_txd_pwr);
96838a40 3373 if (adapter->pcix_82544)
1da177e4
LT		 3374 count += nr_frags;
3375
0f15a8fa
JK		 3376
3377 if (adapter->hw.tx_pkt_filtering &&
3378 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 3379 e1000_transfer_dhcp_info(adapter, skb);
3380
581d708e
MC		 3381 local_irq_save(flags);
3382 if (!spin_trylock(&tx_ring->tx_lock)) {
3383 /* Collision - tell upper layer to requeue */
3384 local_irq_restore(flags);
3385 return NETDEV_TX_LOCKED;
3386 }
1da177e4
LT		 3387
3388 /* need: count + 2 desc gap to keep tail from touching
3389 * head, otherwise try next time */
65c7973f 3390 if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2))) {
581d708e 3391 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3392 return NETDEV_TX_BUSY;
3393 }
3394
96838a40
JB		 3395 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
3396 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4 3397 netif_stop_queue(netdev);
1314bbf3 3398 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
581d708e 3399 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3400 return NETDEV_TX_BUSY;
3401 }
3402 }
3403
96838a40 3404 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 3405 tx_flags |= E1000_TX_FLAGS_VLAN;
3406 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
3407 }
3408
581d708e 3409 first = tx_ring->next_to_use;
96838a40 3410
581d708e 3411 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 3412 if (tso < 0) {
3413 dev_kfree_skb_any(skb);
581d708e 3414 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3415 return NETDEV_TX_OK;
3416 }
3417
fd803241
JK		 3418 if (likely(tso)) {
3419 tx_ring->last_tx_tso = 1;
1da177e4 3420 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 3421 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 3422 tx_flags |= E1000_TX_FLAGS_CSUM;
3423
2d7edb92 3424 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 3425 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 3426 * no longer assume, we must. */
60828236 3427 if (likely(skb->protocol == htons(ETH_P_IP)))
2d7edb92
MC		 3428 tx_flags |= E1000_TX_FLAGS_IPV4;
3429
581d708e
MC		 3430 e1000_tx_queue(adapter, tx_ring, tx_flags,
3431 e1000_tx_map(adapter, tx_ring, skb, first,
3432 max_per_txd, nr_frags, mss));
1da177e4
LT		 3433
3434 netdev->trans_start = jiffies;
3435
3436 /* Make sure there is space in the ring for the next send. */
65c7973f 3437 e1000_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 2);
1da177e4 3438
581d708e 3439 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3440 return NETDEV_TX_OK;
3441}
3442
3443/**
3444 * e1000_tx_timeout - Respond to a Tx Hang
3445 * @netdev: network interface device structure
3446 **/
3447
3448static void
3449e1000_tx_timeout(struct net_device *netdev)
3450{
60490fe0 3451 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3452
3453 /* Do the reset outside of interrupt context */
87041639
JK		 3454 adapter->tx_timeout_count++;
3455 schedule_work(&adapter->reset_task);
1da177e4
LT		 3456}
3457
3458static void
65f27f38 3459e1000_reset_task(struct work_struct *work)
1da177e4 3460{
65f27f38
DH		 3461 struct e1000_adapter *adapter =
3462 container_of(work, struct e1000_adapter, reset_task);
1da177e4 3463
2db10a08 3464 e1000_reinit_locked(adapter);
1da177e4
LT		 3465}
3466
3467/**
3468 * e1000_get_stats - Get System Network Statistics
3469 * @netdev: network interface device structure
3470 *
3471 * Returns the address of the device statistics structure.
3472 * The statistics are actually updated from the timer callback.
3473 **/
3474
3475static struct net_device_stats *
3476e1000_get_stats(struct net_device *netdev)
3477{
60490fe0 3478 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3479
6b7660cd 3480 /* only return the current stats */
1da177e4
LT		 3481 return &adapter->net_stats;
3482}
3483
3484/**
3485 * e1000_change_mtu - Change the Maximum Transfer Unit
3486 * @netdev: network interface device structure
3487 * @new_mtu: new value for maximum frame size
3488 *
3489 * Returns 0 on success, negative on failure
3490 **/
3491
3492static int
3493e1000_change_mtu(struct net_device *netdev, int new_mtu)
3494{
60490fe0 3495 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3496 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 3497 uint16_t eeprom_data = 0;
1da177e4 3498
96838a40
JB		 3499 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3500 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3501 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3502 return -EINVAL;
2d7edb92 3503 }
1da177e4 3504
997f5cbd
JK		 3505 /* Adapter-specific max frame size limits. */
3506 switch (adapter->hw.mac_type) {
9e2feace 3507 case e1000_undefined ... e1000_82542_rev2_1:
cd94dd0b 3508 case e1000_ich8lan:
997f5cbd
JK		 3509 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3510 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3511 return -EINVAL;
2d7edb92 3512 }
997f5cbd 3513 break;
85b22eb6 3514 case e1000_82573:
249d71d6
BA		 3515 /* Jumbo Frames not supported if:
3516 * - this is not an 82573L device
3517 * - ASPM is enabled in any way (0x1A bits 3:2) */
85b22eb6
JK		 3518 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
3519 &eeprom_data);
249d71d6
BA		 3520 if ((adapter->hw.device_id != E1000_DEV_ID_82573L) ||
3521 (eeprom_data & EEPROM_WORD1A_ASPM_MASK)) {
85b22eb6
JK		 3522 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3523 DPRINTK(PROBE, ERR,
3524 "Jumbo Frames not supported.\n");
3525 return -EINVAL;
3526 }
3527 break;
3528 }
249d71d6
BA		 3529 /* ERT will be enabled later to enable wire speed receives */
3530
85b22eb6 3531 /* fall through to get support */
997f5cbd
JK		 3532 case e1000_82571:
3533 case e1000_82572:
87041639 3534 case e1000_80003es2lan:
997f5cbd
JK		 3535#define MAX_STD_JUMBO_FRAME_SIZE 9234
3536 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3537 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3538 return -EINVAL;
3539 }
3540 break;
3541 default:
3542 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3543 break;
1da177e4
LT		 3544 }
3545
87f5032e 3546 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
9e2feace
AK		 3547 * means we reserve 2 more, this pushes us to allocate from the next
3548 * larger slab size
3549 * i.e. RXBUFFER_2048 --> size-4096 slab */
3550
3551 if (max_frame <= E1000_RXBUFFER_256)
3552 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3553 else if (max_frame <= E1000_RXBUFFER_512)
3554 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3555 else if (max_frame <= E1000_RXBUFFER_1024)
3556 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3557 else if (max_frame <= E1000_RXBUFFER_2048)
3558 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3559 else if (max_frame <= E1000_RXBUFFER_4096)
3560 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3561 else if (max_frame <= E1000_RXBUFFER_8192)
3562 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3563 else if (max_frame <= E1000_RXBUFFER_16384)
3564 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3565
3566 /* adjust allocation if LPE protects us, and we aren't using SBP */
9e2feace
AK		 3567 if (!adapter->hw.tbi_compatibility_on &&
3568 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3569 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3570 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3571
2d7edb92 3572 netdev->mtu = new_mtu;
83cd8279 3573 adapter->hw.max_frame_size = max_frame;
2d7edb92 3574
2db10a08
AK		 3575 if (netif_running(netdev))
3576 e1000_reinit_locked(adapter);
1da177e4 3577
1da177e4
LT		 3578 return 0;
3579}
3580
3581/**
3582 * e1000_update_stats - Update the board statistics counters
3583 * @adapter: board private structure
3584 **/
3585
3586void
3587e1000_update_stats(struct e1000_adapter *adapter)
3588{
3589 struct e1000_hw *hw = &adapter->hw;
282f33c9 3590 struct pci_dev *pdev = adapter->pdev;
1da177e4
LT		 3591 unsigned long flags;
3592 uint16_t phy_tmp;
3593
3594#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3595
282f33c9
LV		 3596 /*
3597 * Prevent stats update while adapter is being reset, or if the pci
3598 * connection is down.
3599 */
9026729b 3600 if (adapter->link_speed == 0)
282f33c9 3601 return;
81b1955e 3602 if (pci_channel_offline(pdev))
9026729b
AK		 3603 return;
3604
1da177e4
LT		 3605 spin_lock_irqsave(&adapter->stats_lock, flags);
3606
3607 /* these counters are modified from e1000_adjust_tbi_stats,
3608 * called from the interrupt context, so they must only
3609 * be written while holding adapter->stats_lock
3610 */
3611
3612 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3613 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3614 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3615 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3616 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3617 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3618 adapter->stats.roc += E1000_READ_REG(hw, ROC);
cd94dd0b
AK		 3619
3620 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3621 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3622 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3623 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3624 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3625 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3626 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
cd94dd0b 3627 }
1da177e4
LT		 3628
3629 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3630 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3631 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3632 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3633 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3634 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3635 adapter->stats.dc += E1000_READ_REG(hw, DC);
3636 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3637 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3638 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3639 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3640 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3641 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3642 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3643 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3644 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3645 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3646 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3647 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3648 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3649 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3650 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3651 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3652 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3653 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3654 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
cd94dd0b
AK		 3655
3656 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3657 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3658 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3659 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3660 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3661 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3662 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 3663 }
3664
1da177e4
LT		 3665 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3666 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3667
3668 /* used for adaptive IFS */
3669
3670 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3671 adapter->stats.tpt += hw->tx_packet_delta;
3672 hw->collision_delta = E1000_READ_REG(hw, COLC);
3673 adapter->stats.colc += hw->collision_delta;
3674
96838a40 3675 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3676 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3677 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3678 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3679 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3680 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3681 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3682 }
96838a40 3683 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3684 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3685 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 3686
3687 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3688 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3689 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3690 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3691 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3692 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3693 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3694 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
cd94dd0b 3695 }
2d7edb92 3696 }
1da177e4
LT		 3697
3698 /* Fill out the OS statistics structure */
1da177e4
LT		 3699 adapter->net_stats.rx_packets = adapter->stats.gprc;
3700 adapter->net_stats.tx_packets = adapter->stats.gptc;
3701 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3702 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3703 adapter->net_stats.multicast = adapter->stats.mprc;
3704 adapter->net_stats.collisions = adapter->stats.colc;
3705
3706 /* Rx Errors */
3707
87041639
JK		 3708 /* RLEC on some newer hardware can be incorrect so build
3709 * our own version based on RUC and ROC */
1da177e4
LT		 3710 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3711 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3712 adapter->stats.ruc + adapter->stats.roc +
3713 adapter->stats.cexterr;
49559854
MW		 3714 adapter->stats.rlerrc = adapter->stats.ruc + adapter->stats.roc;
3715 adapter->net_stats.rx_length_errors = adapter->stats.rlerrc;
1da177e4
LT		 3716 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3717 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3718 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3719
3720 /* Tx Errors */
49559854
MW		 3721 adapter->stats.txerrc = adapter->stats.ecol + adapter->stats.latecol;
3722 adapter->net_stats.tx_errors = adapter->stats.txerrc;
1da177e4
LT		 3723 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3724 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3725 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
167fb284
JG		 3726 if (adapter->hw.bad_tx_carr_stats_fd &&
3727 adapter->link_duplex == FULL_DUPLEX) {
3728 adapter->net_stats.tx_carrier_errors = 0;
3729 adapter->stats.tncrs = 0;
3730 }
1da177e4
LT		 3731
3732 /* Tx Dropped needs to be maintained elsewhere */
3733
3734 /* Phy Stats */
96838a40
JB		 3735 if (hw->media_type == e1000_media_type_copper) {
3736 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3737 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3738 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3739 adapter->phy_stats.idle_errors += phy_tmp;
3740 }
3741
96838a40 3742 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3743 (hw->phy_type == e1000_phy_m88) &&
3744 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3745 adapter->phy_stats.receive_errors += phy_tmp;
3746 }
3747
15e376b4
JG		 3748 /* Management Stats */
3749 if (adapter->hw.has_smbus) {
3750 adapter->stats.mgptc += E1000_READ_REG(hw, MGTPTC);
3751 adapter->stats.mgprc += E1000_READ_REG(hw, MGTPRC);
3752 adapter->stats.mgpdc += E1000_READ_REG(hw, MGTPDC);
3753 }
3754
1da177e4
LT		 3755 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3756}
9ac98284
JB		 3757#ifdef CONFIG_PCI_MSI
3758
3759/**
3760 * e1000_intr_msi - Interrupt Handler
3761 * @irq: interrupt number
3762 * @data: pointer to a network interface device structure
3763 **/
3764
b5fc8f0c
JB		 3765static irqreturn_t
3766e1000_intr_msi(int irq, void *data)
9ac98284
JB		 3767{
3768 struct net_device *netdev = data;
3769 struct e1000_adapter *adapter = netdev_priv(netdev);
3770 struct e1000_hw *hw = &adapter->hw;
3771#ifndef CONFIG_E1000_NAPI
3772 int i;
3773#endif
b5fc8f0c 3774 uint32_t icr = E1000_READ_REG(hw, ICR);
9ac98284 3775
9ac98284 3776#ifdef CONFIG_E1000_NAPI
b5fc8f0c
JB		 3777 /* read ICR disables interrupts using IAM, so keep up with our
3778 * enable/disable accounting */
3779 atomic_inc(&adapter->irq_sem);
9ac98284 3780#endif
b5fc8f0c
JB		 3781 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3782 hw->get_link_status = 1;
3783 /* 80003ES2LAN workaround-- For packet buffer work-around on
3784 * link down event; disable receives here in the ISR and reset
3785 * adapter in watchdog */
3786 if (netif_carrier_ok(netdev) &&
3787 (adapter->hw.mac_type == e1000_80003es2lan)) {
3788 /* disable receives */
3789 uint32_t rctl = E1000_READ_REG(hw, RCTL);
3790 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
9ac98284 3791 }
b5fc8f0c
JB		 3792 /* guard against interrupt when we're going down */
3793 if (!test_bit(__E1000_DOWN, &adapter->flags))
3794 mod_timer(&adapter->watchdog_timer, jiffies + 1);
9ac98284
JB		 3795 }
3796
3797#ifdef CONFIG_E1000_NAPI
835bb129
JB		 3798 if (likely(netif_rx_schedule_prep(netdev))) {
3799 adapter->total_tx_bytes = 0;
3800 adapter->total_tx_packets = 0;
3801 adapter->total_rx_bytes = 0;
3802 adapter->total_rx_packets = 0;
9ac98284 3803 __netif_rx_schedule(netdev);
835bb129 3804 } else
9ac98284
JB		 3805 e1000_irq_enable(adapter);
3806#else
835bb129
JB		 3807 adapter->total_tx_bytes = 0;
3808 adapter->total_rx_bytes = 0;
3809 adapter->total_tx_packets = 0;
3810 adapter->total_rx_packets = 0;
3811
9ac98284
JB		 3812 for (i = 0; i < E1000_MAX_INTR; i++)
3813 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
46fcc86d 3814 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
9ac98284 3815 break;
835bb129
JB		 3816
3817 if (likely(adapter->itr_setting & 3))
3818 e1000_set_itr(adapter);
9ac98284
JB		 3819#endif
3820
3821 return IRQ_HANDLED;
3822}
3823#endif
1da177e4
LT		 3824
3825/**
3826 * e1000_intr - Interrupt Handler
3827 * @irq: interrupt number
3828 * @data: pointer to a network interface device structure
1da177e4
LT		 3829 **/
3830
3831static irqreturn_t
7d12e780 3832e1000_intr(int irq, void *data)
1da177e4
LT		 3833{
3834 struct net_device *netdev = data;
60490fe0 3835 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3836 struct e1000_hw *hw = &adapter->hw;
87041639 3837 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3838#ifndef CONFIG_E1000_NAPI
581d708e 3839 int i;
835bb129
JB		 3840#endif
3841 if (unlikely(!icr))
3842 return IRQ_NONE; /* Not our interrupt */
3843
3844#ifdef CONFIG_E1000_NAPI
3845 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3846 * not set, then the adapter didn't send an interrupt */
3847 if (unlikely(hw->mac_type >= e1000_82571 &&
3848 !(icr & E1000_ICR_INT_ASSERTED)))
3849 return IRQ_NONE;
3850
1e613fd9
JK		 3851 /* Interrupt Auto-Mask...upon reading ICR,
3852 * interrupts are masked. No need for the
3853 * IMC write, but it does mean we should
3854 * account for it ASAP. */
3855 if (likely(hw->mac_type >= e1000_82571))
3856 atomic_inc(&adapter->irq_sem);
be2b28ed 3857#endif
1da177e4 3858
96838a40 3859 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3860 hw->get_link_status = 1;
87041639
JK		 3861 /* 80003ES2LAN workaround--
3862 * For packet buffer work-around on link down event;
3863 * disable receives here in the ISR and
3864 * reset adapter in watchdog
3865 */
3866 if (netif_carrier_ok(netdev) &&
3867 (adapter->hw.mac_type == e1000_80003es2lan)) {
3868 /* disable receives */
3869 rctl = E1000_READ_REG(hw, RCTL);
3870 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3871 }
1314bbf3
AK		 3872 /* guard against interrupt when we're going down */
3873 if (!test_bit(__E1000_DOWN, &adapter->flags))
3874 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1da177e4
LT		 3875 }
3876
3877#ifdef CONFIG_E1000_NAPI
1e613fd9 3878 if (unlikely(hw->mac_type < e1000_82571)) {
835bb129 3879 /* disable interrupts, without the synchronize_irq bit */
1e613fd9
JK		 3880 atomic_inc(&adapter->irq_sem);
3881 E1000_WRITE_REG(hw, IMC, ~0);
3882 E1000_WRITE_FLUSH(hw);
3883 }
835bb129
JB		 3884 if (likely(netif_rx_schedule_prep(netdev))) {
3885 adapter->total_tx_bytes = 0;
3886 adapter->total_tx_packets = 0;
3887 adapter->total_rx_bytes = 0;
3888 adapter->total_rx_packets = 0;
d3d9e484 3889 __netif_rx_schedule(netdev);
835bb129 3890 } else
90fb5135
AK		 3891 /* this really should not happen! if it does it is basically a
3892 * bug, but not a hard error, so enable ints and continue */
581d708e 3893 e1000_irq_enable(adapter);
c1605eb3 3894#else
1da177e4 3895 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3896 * Due to Hub Link bus being occupied, an interrupt
3897 * de-assertion message is not able to be sent.
3898 * When an interrupt assertion message is generated later,
3899 * two messages are re-ordered and sent out.
3900 * That causes APIC to think 82547 is in de-assertion
3901 * state, while 82547 is in assertion state, resulting
3902 * in dead lock. Writing IMC forces 82547 into
3903 * de-assertion state.
3904 */
3905 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3906 atomic_inc(&adapter->irq_sem);
2648345f 3907 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3908 }
3909
835bb129
JB		 3910 adapter->total_tx_bytes = 0;
3911 adapter->total_rx_bytes = 0;
3912 adapter->total_tx_packets = 0;
3913 adapter->total_rx_packets = 0;
3914
96838a40
JB		 3915 for (i = 0; i < E1000_MAX_INTR; i++)
3916 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
46fcc86d 3917 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3918 break;
3919
835bb129
JB		 3920 if (likely(adapter->itr_setting & 3))
3921 e1000_set_itr(adapter);
3922
96838a40 3923 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3924 e1000_irq_enable(adapter);
581d708e 3925
c1605eb3 3926#endif
1da177e4
LT		 3927 return IRQ_HANDLED;
3928}
3929
3930#ifdef CONFIG_E1000_NAPI
3931/**
3932 * e1000_clean - NAPI Rx polling callback
3933 * @adapter: board private structure
3934 **/
3935
3936static int
581d708e 3937e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3938{
581d708e
MC		 3939 struct e1000_adapter *adapter;
3940 int work_to_do = min(*budget, poll_dev->quota);
d3d9e484 3941 int tx_cleaned = 0, work_done = 0;
581d708e
MC		 3942
3943 /* Must NOT use netdev_priv macro here. */
3944 adapter = poll_dev->priv;
3945
3946 /* Keep link state information with original netdev */
d3d9e484 3947 if (!netif_carrier_ok(poll_dev))
581d708e 3948 goto quit_polling;
2648345f 3949
d3d9e484
AK		 3950 /* e1000_clean is called per-cpu. This lock protects
3951 * tx_ring[0] from being cleaned by multiple cpus
3952 * simultaneously. A failure obtaining the lock means
3953 * tx_ring[0] is currently being cleaned anyway. */
3954 if (spin_trylock(&adapter->tx_queue_lock)) {
3955 tx_cleaned = e1000_clean_tx_irq(adapter,
3956 &adapter->tx_ring[0]);
3957 spin_unlock(&adapter->tx_queue_lock);
581d708e
MC		 3958 }
3959
d3d9e484 3960 adapter->clean_rx(adapter, &adapter->rx_ring[0],
581d708e 3961 &work_done, work_to_do);
1da177e4
LT		 3962
3963 *budget -= work_done;
581d708e 3964 poll_dev->quota -= work_done;
96838a40 3965
2b02893e 3966 /* If no Tx and not enough Rx work done, exit the polling mode */
46fcc86d 3967 if ((!tx_cleaned && (work_done == 0)) ||
d3d9e484 3968 !netif_running(poll_dev)) {
581d708e 3969quit_polling:
835bb129
JB		 3970 if (likely(adapter->itr_setting & 3))
3971 e1000_set_itr(adapter);
581d708e 3972 netif_rx_complete(poll_dev);
1da177e4
LT		 3973 e1000_irq_enable(adapter);
3974 return 0;
3975 }
3976
3977 return 1;
3978}
3979
3980#endif
3981/**
3982 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3983 * @adapter: board private structure
3984 **/
3985
3986static boolean_t
581d708e
MC		 3987e1000_clean_tx_irq(struct e1000_adapter *adapter,
3988 struct e1000_tx_ring *tx_ring)
1da177e4 3989{
1da177e4
LT		 3990 struct net_device *netdev = adapter->netdev;
3991 struct e1000_tx_desc *tx_desc, *eop_desc;
3992 struct e1000_buffer *buffer_info;
3993 unsigned int i, eop;
2a1af5d7
JK		 3994#ifdef CONFIG_E1000_NAPI
3995 unsigned int count = 0;
3996#endif
46fcc86d 3997 boolean_t cleaned = FALSE;
835bb129 3998 unsigned int total_tx_bytes=0, total_tx_packets=0;
1da177e4
LT		 3999
4000 i = tx_ring->next_to_clean;
4001 eop = tx_ring->buffer_info[i].next_to_watch;
4002 eop_desc = E1000_TX_DESC(*tx_ring, eop);
4003
581d708e 4004 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 4005 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 4006 tx_desc = E1000_TX_DESC(*tx_ring, i);
4007 buffer_info = &tx_ring->buffer_info[i];
4008 cleaned = (i == eop);
4009
835bb129 4010 if (cleaned) {
2b65326e 4011 struct sk_buff *skb = buffer_info->skb;
7753b171
JB		 4012 unsigned int segs, bytecount;
4013 segs = skb_shinfo(skb)->gso_segs ?: 1;
4014 /* multiply data chunks by size of headers */
4015 bytecount = ((segs - 1) * skb_headlen(skb)) +
4016 skb->len;
2b65326e 4017 total_tx_packets += segs;
7753b171 4018 total_tx_bytes += bytecount;
835bb129 4019 }
fd803241 4020 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
a9ebadd6 4021 tx_desc->upper.data = 0;
1da177e4 4022
96838a40 4023 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 4024 }
581d708e 4025
1da177e4
LT		 4026 eop = tx_ring->buffer_info[i].next_to_watch;
4027 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 4028#ifdef CONFIG_E1000_NAPI
4029#define E1000_TX_WEIGHT 64
4030 /* weight of a sort for tx, to avoid endless transmit cleanup */
46fcc86d 4031 if (count++ == E1000_TX_WEIGHT) break;
2a1af5d7 4032#endif
1da177e4
LT		 4033 }
4034
4035 tx_ring->next_to_clean = i;
4036
77b2aad5 4037#define TX_WAKE_THRESHOLD 32
65c7973f
JB		 4038 if (unlikely(cleaned && netif_carrier_ok(netdev) &&
4039 E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
4040 /* Make sure that anybody stopping the queue after this
4041 * sees the new next_to_clean.
4042 */
4043 smp_mb();
fcfb1224 4044 if (netif_queue_stopped(netdev)) {
77b2aad5 4045 netif_wake_queue(netdev);
fcfb1224
JB		 4046 ++adapter->restart_queue;
4047 }
77b2aad5 4048 }
2648345f 4049
581d708e 4050 if (adapter->detect_tx_hung) {
2648345f 4051 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 4052 * check with the clearing of time_stamp and movement of i */
4053 adapter->detect_tx_hung = FALSE;
392137fa
JK		 4054 if (tx_ring->buffer_info[eop].dma &&
4055 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 4056 (adapter->tx_timeout_factor * HZ))
70b8f1e1 4057 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 4058 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 4059
4060 /* detected Tx unit hang */
c6963ef5 4061 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 4062 " Tx Queue <%lu>\n"
70b8f1e1
MC		 4063 " TDH <%x>\n"
4064 " TDT <%x>\n"
4065 " next_to_use <%x>\n"
4066 " next_to_clean <%x>\n"
4067 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 4068 " time_stamp <%lx>\n"
4069 " next_to_watch <%x>\n"
4070 " jiffies <%lx>\n"
4071 " next_to_watch.status <%x>\n",
7bfa4816
JK		 4072 (unsigned long)((tx_ring - adapter->tx_ring) /
4073 sizeof(struct e1000_tx_ring)),
581d708e
MC		 4074 readl(adapter->hw.hw_addr + tx_ring->tdh),
4075 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 4076 tx_ring->next_to_use,
392137fa
JK		 4077 tx_ring->next_to_clean,
4078 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 4079 eop,
4080 jiffies,
4081 eop_desc->upper.fields.status);
1da177e4 4082 netif_stop_queue(netdev);
70b8f1e1 4083 }
1da177e4 4084 }
835bb129
JB		 4085 adapter->total_tx_bytes += total_tx_bytes;
4086 adapter->total_tx_packets += total_tx_packets;
1da177e4
LT		 4087 return cleaned;
4088}
4089
4090/**
4091 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 4092 * @adapter: board private structure
4093 * @status_err: receive descriptor status and error fields
4094 * @csum: receive descriptor csum field
4095 * @sk_buff: socket buffer with received data
1da177e4
LT		 4096 **/
4097
e619d523 4098static void
1da177e4 4099e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 4100 uint32_t status_err, uint32_t csum,
4101 struct sk_buff *skb)
1da177e4 4102{
2d7edb92
MC		 4103 uint16_t status = (uint16_t)status_err;
4104 uint8_t errors = (uint8_t)(status_err >> 24);
4105 skb->ip_summed = CHECKSUM_NONE;
4106
1da177e4 4107 /* 82543 or newer only */
96838a40 4108 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 4109 /* Ignore Checksum bit is set */
96838a40 4110 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 4111 /* TCP/UDP checksum error bit is set */
96838a40 4112 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 4113 /* let the stack verify checksum errors */
1da177e4 4114 adapter->hw_csum_err++;
2d7edb92
MC		 4115 return;
4116 }
4117 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 4118 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
4119 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 4120 return;
1da177e4 4121 } else {
96838a40 4122 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 4123 return;
4124 }
4125 /* It must be a TCP or UDP packet with a valid checksum */
4126 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 4127 /* TCP checksum is good */
4128 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 4129 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
4130 /* IP fragment with UDP payload */
4131 /* Hardware complements the payload checksum, so we undo it
4132 * and then put the value in host order for further stack use.
4133 */
4134 csum = ntohl(csum ^ 0xFFFF);
4135 skb->csum = csum;
84fa7933 4136 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 4137 }
2d7edb92 4138 adapter->hw_csum_good++;
1da177e4
LT		 4139}
4140
4141/**
2d7edb92 4142 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 4143 * @adapter: board private structure
4144 **/
4145
4146static boolean_t
4147#ifdef CONFIG_E1000_NAPI
581d708e
MC		 4148e1000_clean_rx_irq(struct e1000_adapter *adapter,
4149 struct e1000_rx_ring *rx_ring,
4150 int *work_done, int work_to_do)
1da177e4 4151#else
581d708e
MC		 4152e1000_clean_rx_irq(struct e1000_adapter *adapter,
4153 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 4154#endif
4155{
1da177e4
LT		 4156 struct net_device *netdev = adapter->netdev;
4157 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 4158 struct e1000_rx_desc *rx_desc, *next_rxd;
4159 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 4160 unsigned long flags;
4161 uint32_t length;
4162 uint8_t last_byte;
4163 unsigned int i;
72d64a43 4164 int cleaned_count = 0;
a1415ee6 4165 boolean_t cleaned = FALSE;
835bb129 4166 unsigned int total_rx_bytes=0, total_rx_packets=0;
1da177e4
LT		 4167
4168 i = rx_ring->next_to_clean;
4169 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 4170 buffer_info = &rx_ring->buffer_info[i];
1da177e4 4171
b92ff8ee 4172 while (rx_desc->status & E1000_RXD_STAT_DD) {
24f476ee 4173 struct sk_buff *skb;
a292ca6e 4174 u8 status;
90fb5135 4175
1da177e4 4176#ifdef CONFIG_E1000_NAPI
96838a40 4177 if (*work_done >= work_to_do)
1da177e4
LT		 4178 break;
4179 (*work_done)++;
4180#endif
a292ca6e 4181 status = rx_desc->status;
b92ff8ee 4182 skb = buffer_info->skb;
86c3d59f
JB		 4183 buffer_info->skb = NULL;
4184
30320be8
JK		 4185 prefetch(skb->data - NET_IP_ALIGN);
4186
86c3d59f
JB		 4187 if (++i == rx_ring->count) i = 0;
4188 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 4189 prefetch(next_rxd);
4190
86c3d59f 4191 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 4192
72d64a43
JK		 4193 cleaned = TRUE;
4194 cleaned_count++;
a292ca6e
JK		 4195 pci_unmap_single(pdev,
4196 buffer_info->dma,
4197 buffer_info->length,
1da177e4
LT		 4198 PCI_DMA_FROMDEVICE);
4199
1da177e4
LT		 4200 length = le16_to_cpu(rx_desc->length);
4201
a1415ee6
JK		 4202 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
4203 /* All receives must fit into a single buffer */
4204 E1000_DBG("%s: Receive packet consumed multiple"
4205 " buffers\n", netdev->name);
864c4e45 4206 /* recycle */
8fc897b0 4207 buffer_info->skb = skb;
1da177e4
LT		 4208 goto next_desc;
4209 }
4210
96838a40 4211 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 4212 last_byte = *(skb->data + length - 1);
b92ff8ee 4213 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 4214 rx_desc->errors, length, last_byte)) {
4215 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 4216 e1000_tbi_adjust_stats(&adapter->hw,
4217 &adapter->stats,
1da177e4
LT		 4218 length, skb->data);
4219 spin_unlock_irqrestore(&adapter->stats_lock,
4220 flags);
4221 length--;
4222 } else {
9e2feace
AK		 4223 /* recycle */
4224 buffer_info->skb = skb;
1da177e4
LT		 4225 goto next_desc;
4226 }
1cb5821f 4227 }
1da177e4 4228
d2a1e213
JB		 4229 /* adjust length to remove Ethernet CRC, this must be
4230 * done after the TBI_ACCEPT workaround above */
4231 length -= 4;
4232
835bb129
JB		 4233 /* probably a little skewed due to removing CRC */
4234 total_rx_bytes += length;
4235 total_rx_packets++;
4236
a292ca6e
JK		 4237 /* code added for copybreak, this should improve
4238 * performance for small packets with large amounts
4239 * of reassembly being done in the stack */
1f753861 4240 if (length < copybreak) {
a292ca6e 4241 struct sk_buff *new_skb =
87f5032e 4242 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
a292ca6e
JK		 4243 if (new_skb) {
4244 skb_reserve(new_skb, NET_IP_ALIGN);
a292ca6e
JK		 4245 memcpy(new_skb->data - NET_IP_ALIGN,
4246 skb->data - NET_IP_ALIGN,
4247 length + NET_IP_ALIGN);
4248 /* save the skb in buffer_info as good */
4249 buffer_info->skb = skb;
4250 skb = new_skb;
a292ca6e 4251 }
996695de
AK		 4252 /* else just continue with the old one */
4253 }
a292ca6e 4254 /* end copybreak code */
996695de 4255 skb_put(skb, length);
1da177e4
LT		 4256
4257 /* Receive Checksum Offload */
a292ca6e
JK		 4258 e1000_rx_checksum(adapter,
4259 (uint32_t)(status) |
2d7edb92 4260 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 4261 le16_to_cpu(rx_desc->csum), skb);
96838a40 4262
1da177e4
LT		 4263 skb->protocol = eth_type_trans(skb, netdev);
4264#ifdef CONFIG_E1000_NAPI
96838a40 4265 if (unlikely(adapter->vlgrp &&
a292ca6e 4266 (status & E1000_RXD_STAT_VP))) {
1da177e4 4267 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 4268 le16_to_cpu(rx_desc->special) &
4269 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 4270 } else {
4271 netif_receive_skb(skb);
4272 }
4273#else /* CONFIG_E1000_NAPI */
96838a40 4274 if (unlikely(adapter->vlgrp &&
b92ff8ee 4275 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 4276 vlan_hwaccel_rx(skb, adapter->vlgrp,
4277 le16_to_cpu(rx_desc->special) &
4278 E1000_RXD_SPC_VLAN_MASK);
4279 } else {
4280 netif_rx(skb);
4281 }
4282#endif /* CONFIG_E1000_NAPI */
4283 netdev->last_rx = jiffies;
4284
4285next_desc:
4286 rx_desc->status = 0;
1da177e4 4287
72d64a43
JK		 4288 /* return some buffers to hardware, one at a time is too slow */
4289 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4290 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4291 cleaned_count = 0;
4292 }
4293
30320be8 4294 /* use prefetched values */
86c3d59f
JB		 4295 rx_desc = next_rxd;
4296 buffer_info = next_buffer;
1da177e4 4297 }
1da177e4 4298 rx_ring->next_to_clean = i;
72d64a43
JK		 4299
4300 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4301 if (cleaned_count)
4302 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92 4303
835bb129
JB		 4304 adapter->total_rx_packets += total_rx_packets;
4305 adapter->total_rx_bytes += total_rx_bytes;
2d7edb92
MC		 4306 return cleaned;
4307}
4308
4309/**
4310 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
4311 * @adapter: board private structure
4312 **/
4313
4314static boolean_t
4315#ifdef CONFIG_E1000_NAPI
581d708e
MC		 4316e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4317 struct e1000_rx_ring *rx_ring,
4318 int *work_done, int work_to_do)
2d7edb92 4319#else
581d708e
MC		 4320e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4321 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 4322#endif
4323{
86c3d59f 4324 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 4325 struct net_device *netdev = adapter->netdev;
4326 struct pci_dev *pdev = adapter->pdev;
86c3d59f 4327 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 4328 struct e1000_ps_page *ps_page;
4329 struct e1000_ps_page_dma *ps_page_dma;
24f476ee 4330 struct sk_buff *skb;
2d7edb92
MC		 4331 unsigned int i, j;
4332 uint32_t length, staterr;
72d64a43 4333 int cleaned_count = 0;
2d7edb92 4334 boolean_t cleaned = FALSE;
835bb129 4335 unsigned int total_rx_bytes=0, total_rx_packets=0;
2d7edb92
MC		 4336
4337 i = rx_ring->next_to_clean;
4338 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 4339 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 4340 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 4341
96838a40 4342 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 4343 ps_page = &rx_ring->ps_page[i];
4344 ps_page_dma = &rx_ring->ps_page_dma[i];
4345#ifdef CONFIG_E1000_NAPI
96838a40 4346 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 4347 break;
4348 (*work_done)++;
4349#endif
86c3d59f
JB		 4350 skb = buffer_info->skb;
4351
30320be8
JK		 4352 /* in the packet split case this is header only */
4353 prefetch(skb->data - NET_IP_ALIGN);
4354
86c3d59f
JB		 4355 if (++i == rx_ring->count) i = 0;
4356 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 4357 prefetch(next_rxd);
4358
86c3d59f 4359 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 4360
2d7edb92 4361 cleaned = TRUE;
72d64a43 4362 cleaned_count++;
2d7edb92
MC		 4363 pci_unmap_single(pdev, buffer_info->dma,
4364 buffer_info->length,
4365 PCI_DMA_FROMDEVICE);
4366
96838a40 4367 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 4368 E1000_DBG("%s: Packet Split buffers didn't pick up"
4369 " the full packet\n", netdev->name);
4370 dev_kfree_skb_irq(skb);
4371 goto next_desc;
4372 }
1da177e4 4373
96838a40 4374 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 4375 dev_kfree_skb_irq(skb);
4376 goto next_desc;
4377 }
4378
4379 length = le16_to_cpu(rx_desc->wb.middle.length0);
4380
96838a40 4381 if (unlikely(!length)) {
2d7edb92
MC		 4382 E1000_DBG("%s: Last part of the packet spanning"
4383 " multiple descriptors\n", netdev->name);
4384 dev_kfree_skb_irq(skb);
4385 goto next_desc;
4386 }
4387
4388 /* Good Receive */
4389 skb_put(skb, length);
4390
dc7c6add
JK		 4391 {
4392 /* this looks ugly, but it seems compiler issues make it
4393 more efficient than reusing j */
4394 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
4395
4396 /* page alloc/put takes too long and effects small packet
4397 * throughput, so unsplit small packets and save the alloc/put*/
1f753861 4398 if (l1 && (l1 <= copybreak) && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add 4399 u8 *vaddr;
76c224bc 4400 /* there is no documentation about how to call
dc7c6add
JK		 4401 * kmap_atomic, so we can't hold the mapping
4402 * very long */
4403 pci_dma_sync_single_for_cpu(pdev,
4404 ps_page_dma->ps_page_dma[0],
4405 PAGE_SIZE,
4406 PCI_DMA_FROMDEVICE);
4407 vaddr = kmap_atomic(ps_page->ps_page[0],
4408 KM_SKB_DATA_SOFTIRQ);
4409 memcpy(skb->tail, vaddr, l1);
4410 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
4411 pci_dma_sync_single_for_device(pdev,
4412 ps_page_dma->ps_page_dma[0],
4413 PAGE_SIZE, PCI_DMA_FROMDEVICE);
f235a2ab
AK		 4414 /* remove the CRC */
4415 l1 -= 4;
dc7c6add 4416 skb_put(skb, l1);
dc7c6add
JK		 4417 goto copydone;
4418 } /* if */
4419 }
90fb5135 4420
96838a40 4421 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 4422 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 4423 break;
2d7edb92
MC		 4424 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
4425 PAGE_SIZE, PCI_DMA_FROMDEVICE);
4426 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 4427 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
4428 length);
2d7edb92 4429 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 4430 skb->len += length;
4431 skb->data_len += length;
5d51b80f 4432 skb->truesize += length;
2d7edb92
MC		 4433 }
4434
f235a2ab
AK		 4435 /* strip the ethernet crc, problem is we're using pages now so
4436 * this whole operation can get a little cpu intensive */
4437 pskb_trim(skb, skb->len - 4);
4438
dc7c6add 4439copydone:
835bb129
JB		 4440 total_rx_bytes += skb->len;
4441 total_rx_packets++;
4442
2d7edb92 4443 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 4444 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 4445 skb->protocol = eth_type_trans(skb, netdev);
4446
96838a40 4447 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 4448 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 4449 adapter->rx_hdr_split++;
2d7edb92 4450#ifdef CONFIG_E1000_NAPI
96838a40 4451 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4452 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 4453 le16_to_cpu(rx_desc->wb.middle.vlan) &
4454 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 4455 } else {
4456 netif_receive_skb(skb);
4457 }
4458#else /* CONFIG_E1000_NAPI */
96838a40 4459 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4460 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 4461 le16_to_cpu(rx_desc->wb.middle.vlan) &
4462 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 4463 } else {
4464 netif_rx(skb);
4465 }
4466#endif /* CONFIG_E1000_NAPI */
4467 netdev->last_rx = jiffies;
4468
4469next_desc:
c3d7a3a4 4470 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 4471 buffer_info->skb = NULL;
2d7edb92 4472
72d64a43
JK		 4473 /* return some buffers to hardware, one at a time is too slow */
4474 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4475 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4476 cleaned_count = 0;
4477 }
4478
30320be8 4479 /* use prefetched values */
86c3d59f
JB		 4480 rx_desc = next_rxd;
4481 buffer_info = next_buffer;
4482
683a38f3 4483 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 4484 }
4485 rx_ring->next_to_clean = i;
72d64a43
JK		 4486
4487 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4488 if (cleaned_count)
4489 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4 4490
835bb129
JB		 4491 adapter->total_rx_packets += total_rx_packets;
4492 adapter->total_rx_bytes += total_rx_bytes;
1da177e4
LT		 4493 return cleaned;
4494}
4495
4496/**
2d7edb92 4497 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 4498 * @adapter: address of board private structure
4499 **/
4500
4501static void
581d708e 4502e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 4503 struct e1000_rx_ring *rx_ring,
a292ca6e 4504 int cleaned_count)
1da177e4 4505{
1da177e4
LT		 4506 struct net_device *netdev = adapter->netdev;
4507 struct pci_dev *pdev = adapter->pdev;
4508 struct e1000_rx_desc *rx_desc;
4509 struct e1000_buffer *buffer_info;
4510 struct sk_buff *skb;
2648345f
MC		 4511 unsigned int i;
4512 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 4513
4514 i = rx_ring->next_to_use;
4515 buffer_info = &rx_ring->buffer_info[i];
4516
a292ca6e 4517 while (cleaned_count--) {
ca6f7224
CH		 4518 skb = buffer_info->skb;
4519 if (skb) {
a292ca6e
JK		 4520 skb_trim(skb, 0);
4521 goto map_skb;
4522 }
4523
ca6f7224 4524 skb = netdev_alloc_skb(netdev, bufsz);
96838a40 4525 if (unlikely(!skb)) {
1da177e4 4526 /* Better luck next round */
72d64a43 4527 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 4528 break;
4529 }
4530
2648345f 4531 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 4532 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4533 struct sk_buff *oldskb = skb;
2648345f
MC		 4534 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
4535 "at %p\n", bufsz, skb->data);
4536 /* Try again, without freeing the previous */
87f5032e 4537 skb = netdev_alloc_skb(netdev, bufsz);
2648345f 4538 /* Failed allocation, critical failure */
1da177e4
LT		 4539 if (!skb) {
4540 dev_kfree_skb(oldskb);
4541 break;
4542 }
2648345f 4543
1da177e4
LT		 4544 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4545 /* give up */
4546 dev_kfree_skb(skb);
4547 dev_kfree_skb(oldskb);
4548 break; /* while !buffer_info->skb */
1da177e4 4549 }
ca6f7224
CH		 4550
4551 /* Use new allocation */
4552 dev_kfree_skb(oldskb);
1da177e4 4553 }
1da177e4
LT		 4554 /* Make buffer alignment 2 beyond a 16 byte boundary
4555 * this will result in a 16 byte aligned IP header after
4556 * the 14 byte MAC header is removed
4557 */
4558 skb_reserve(skb, NET_IP_ALIGN);
4559
1da177e4
LT		 4560 buffer_info->skb = skb;
4561 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 4562map_skb:
1da177e4
LT		 4563 buffer_info->dma = pci_map_single(pdev,
4564 skb->data,
4565 adapter->rx_buffer_len,
4566 PCI_DMA_FROMDEVICE);
4567
2648345f
MC		 4568 /* Fix for errata 23, can't cross 64kB boundary */
4569 if (!e1000_check_64k_bound(adapter,
4570 (void *)(unsigned long)buffer_info->dma,
4571 adapter->rx_buffer_len)) {
4572 DPRINTK(RX_ERR, ERR,
4573 "dma align check failed: %u bytes at %p\n",
4574 adapter->rx_buffer_len,
4575 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 4576 dev_kfree_skb(skb);
4577 buffer_info->skb = NULL;
4578
2648345f 4579 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 4580 adapter->rx_buffer_len,
4581 PCI_DMA_FROMDEVICE);
4582
4583 break; /* while !buffer_info->skb */
4584 }
1da177e4
LT		 4585 rx_desc = E1000_RX_DESC(*rx_ring, i);
4586 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4587
96838a40
JB		 4588 if (unlikely(++i == rx_ring->count))
4589 i = 0;
1da177e4
LT		 4590 buffer_info = &rx_ring->buffer_info[i];
4591 }
4592
b92ff8ee
JB		 4593 if (likely(rx_ring->next_to_use != i)) {
4594 rx_ring->next_to_use = i;
4595 if (unlikely(i-- == 0))
4596 i = (rx_ring->count - 1);
4597
4598 /* Force memory writes to complete before letting h/w
4599 * know there are new descriptors to fetch. (Only
4600 * applicable for weak-ordered memory model archs,
4601 * such as IA-64). */
4602 wmb();
4603 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4604 }
1da177e4
LT		 4605}
4606
2d7edb92
MC		 4607/**
4608 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
4609 * @adapter: address of board private structure
4610 **/
4611
4612static void
581d708e 4613e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 4614 struct e1000_rx_ring *rx_ring,
4615 int cleaned_count)
2d7edb92 4616{
2d7edb92
MC		 4617 struct net_device *netdev = adapter->netdev;
4618 struct pci_dev *pdev = adapter->pdev;
4619 union e1000_rx_desc_packet_split *rx_desc;
4620 struct e1000_buffer *buffer_info;
4621 struct e1000_ps_page *ps_page;
4622 struct e1000_ps_page_dma *ps_page_dma;
4623 struct sk_buff *skb;
4624 unsigned int i, j;
4625
4626 i = rx_ring->next_to_use;
4627 buffer_info = &rx_ring->buffer_info[i];
4628 ps_page = &rx_ring->ps_page[i];
4629 ps_page_dma = &rx_ring->ps_page_dma[i];
4630
72d64a43 4631 while (cleaned_count--) {
2d7edb92
MC		 4632 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4633
96838a40 4634 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4635 if (j < adapter->rx_ps_pages) {
4636 if (likely(!ps_page->ps_page[j])) {
4637 ps_page->ps_page[j] =
4638 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4639 if (unlikely(!ps_page->ps_page[j])) {
4640 adapter->alloc_rx_buff_failed++;
e4c811c9 4641 goto no_buffers;
b92ff8ee 4642 }
e4c811c9
MC		 4643 ps_page_dma->ps_page_dma[j] =
4644 pci_map_page(pdev,
4645 ps_page->ps_page[j],
4646 0, PAGE_SIZE,
4647 PCI_DMA_FROMDEVICE);
4648 }
4649 /* Refresh the desc even if buffer_addrs didn't
96838a40 4650 * change because each write-back erases
e4c811c9
MC		 4651 * this info.
4652 */
4653 rx_desc->read.buffer_addr[j+1] =
4654 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4655 } else
4656 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4657 }
4658
87f5032e 4659 skb = netdev_alloc_skb(netdev,
90fb5135 4660 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
2d7edb92 4661
b92ff8ee
JB		 4662 if (unlikely(!skb)) {
4663 adapter->alloc_rx_buff_failed++;
2d7edb92 4664 break;
b92ff8ee 4665 }
2d7edb92
MC		 4666
4667 /* Make buffer alignment 2 beyond a 16 byte boundary
4668 * this will result in a 16 byte aligned IP header after
4669 * the 14 byte MAC header is removed
4670 */
4671 skb_reserve(skb, NET_IP_ALIGN);
4672
2d7edb92
MC		 4673 buffer_info->skb = skb;
4674 buffer_info->length = adapter->rx_ps_bsize0;
4675 buffer_info->dma = pci_map_single(pdev, skb->data,
4676 adapter->rx_ps_bsize0,
4677 PCI_DMA_FROMDEVICE);
4678
4679 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4680
96838a40 4681 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4682 buffer_info = &rx_ring->buffer_info[i];
4683 ps_page = &rx_ring->ps_page[i];
4684 ps_page_dma = &rx_ring->ps_page_dma[i];
4685 }
4686
4687no_buffers:
b92ff8ee
JB		 4688 if (likely(rx_ring->next_to_use != i)) {
4689 rx_ring->next_to_use = i;
4690 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4691
4692 /* Force memory writes to complete before letting h/w
4693 * know there are new descriptors to fetch. (Only
4694 * applicable for weak-ordered memory model archs,
4695 * such as IA-64). */
4696 wmb();
4697 /* Hardware increments by 16 bytes, but packet split
4698 * descriptors are 32 bytes...so we increment tail
4699 * twice as much.
4700 */
4701 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4702 }
2d7edb92
MC		 4703}
4704
1da177e4
LT		 4705/**
4706 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4707 * @adapter:
4708 **/
4709
4710static void
4711e1000_smartspeed(struct e1000_adapter *adapter)
4712{
4713 uint16_t phy_status;
4714 uint16_t phy_ctrl;
4715
96838a40 4716 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4717 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4718 return;
4719
96838a40 4720 if (adapter->smartspeed == 0) {
1da177e4
LT		 4721 /* If Master/Slave config fault is asserted twice,
4722 * we assume back-to-back */
4723 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4724 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4725 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4726 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4727 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4728 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4729 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4730 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4731 phy_ctrl);
4732 adapter->smartspeed++;
96838a40 4733 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4734 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4735 &phy_ctrl)) {
4736 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4737 MII_CR_RESTART_AUTO_NEG);
4738 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4739 phy_ctrl);
4740 }
4741 }
4742 return;
96838a40 4743 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4744 /* If still no link, perhaps using 2/3 pair cable */
4745 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4746 phy_ctrl |= CR_1000T_MS_ENABLE;
4747 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4748 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4749 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4750 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4751 MII_CR_RESTART_AUTO_NEG);
4752 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4753 }
4754 }
4755 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4756 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4757 adapter->smartspeed = 0;
4758}
4759
4760/**
4761 * e1000_ioctl -
4762 * @netdev:
4763 * @ifreq:
4764 * @cmd:
4765 **/
4766
4767static int
4768e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4769{
4770 switch (cmd) {
4771 case SIOCGMIIPHY:
4772 case SIOCGMIIREG:
4773 case SIOCSMIIREG:
4774 return e1000_mii_ioctl(netdev, ifr, cmd);
4775 default:
4776 return -EOPNOTSUPP;
4777 }
4778}
4779
4780/**
4781 * e1000_mii_ioctl -
4782 * @netdev:
4783 * @ifreq:
4784 * @cmd:
4785 **/
4786
4787static int
4788e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4789{
60490fe0 4790 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4791 struct mii_ioctl_data *data = if_mii(ifr);
4792 int retval;
4793 uint16_t mii_reg;
4794 uint16_t spddplx;
97876fc6 4795 unsigned long flags;
1da177e4 4796
96838a40 4797 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4798 return -EOPNOTSUPP;
4799
4800 switch (cmd) {
4801 case SIOCGMIIPHY:
4802 data->phy_id = adapter->hw.phy_addr;
4803 break;
4804 case SIOCGMIIREG:
96838a40 4805 if (!capable(CAP_NET_ADMIN))
1da177e4 4806 return -EPERM;
97876fc6 4807 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4808 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4809 &data->val_out)) {
4810 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4811 return -EIO;
97876fc6
MC		 4812 }
4813 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4814 break;
4815 case SIOCSMIIREG:
96838a40 4816 if (!capable(CAP_NET_ADMIN))
1da177e4 4817 return -EPERM;
96838a40 4818 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4819 return -EFAULT;
4820 mii_reg = data->val_in;
97876fc6 4821 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4822 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4823 mii_reg)) {
4824 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4825 return -EIO;
97876fc6 4826 }
dc86d32a 4827 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4828 switch (data->reg_num) {
4829 case PHY_CTRL:
96838a40 4830 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4831 break;
96838a40 4832 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4833 adapter->hw.autoneg = 1;
4834 adapter->hw.autoneg_advertised = 0x2F;
4835 } else {
4836 if (mii_reg & 0x40)
4837 spddplx = SPEED_1000;
4838 else if (mii_reg & 0x2000)
4839 spddplx = SPEED_100;
4840 else
4841 spddplx = SPEED_10;
4842 spddplx += (mii_reg & 0x100)
cb764326
JK		 4843 ? DUPLEX_FULL :
4844 DUPLEX_HALF;
1da177e4
LT		 4845 retval = e1000_set_spd_dplx(adapter,
4846 spddplx);
96838a40 4847 if (retval) {
97876fc6 4848 spin_unlock_irqrestore(
96838a40 4849 &adapter->stats_lock,
97876fc6 4850 flags);
1da177e4 4851 return retval;
97876fc6 4852 }
1da177e4 4853 }
2db10a08
AK		 4854 if (netif_running(adapter->netdev))
4855 e1000_reinit_locked(adapter);
4856 else
1da177e4
LT		 4857 e1000_reset(adapter);
4858 break;
4859 case M88E1000_PHY_SPEC_CTRL:
4860 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4861 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4862 spin_unlock_irqrestore(
4863 &adapter->stats_lock, flags);
1da177e4 4864 return -EIO;
97876fc6 4865 }
1da177e4
LT		 4866 break;
4867 }
4868 } else {
4869 switch (data->reg_num) {
4870 case PHY_CTRL:
96838a40 4871 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4872 break;
2db10a08
AK		 4873 if (netif_running(adapter->netdev))
4874 e1000_reinit_locked(adapter);
4875 else
1da177e4
LT		 4876 e1000_reset(adapter);
4877 break;
4878 }
4879 }
97876fc6 4880 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4881 break;
4882 default:
4883 return -EOPNOTSUPP;
4884 }
4885 return E1000_SUCCESS;
4886}
4887
4888void
4889e1000_pci_set_mwi(struct e1000_hw *hw)
4890{
4891 struct e1000_adapter *adapter = hw->back;
2648345f 4892 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4893
96838a40 4894 if (ret_val)
2648345f 4895 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4896}
4897
4898void
4899e1000_pci_clear_mwi(struct e1000_hw *hw)
4900{
4901 struct e1000_adapter *adapter = hw->back;
4902
4903 pci_clear_mwi(adapter->pdev);
4904}
4905
4906void
4907e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4908{
4909 struct e1000_adapter *adapter = hw->back;
4910
4911 pci_read_config_word(adapter->pdev, reg, value);
4912}
4913
4914void
4915e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4916{
4917 struct e1000_adapter *adapter = hw->back;
4918
4919 pci_write_config_word(adapter->pdev, reg, *value);
4920}
4921
caeccb68
JK		 4922int32_t
4923e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4924{
4925 struct e1000_adapter *adapter = hw->back;
4926 uint16_t cap_offset;
4927
4928 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
4929 if (!cap_offset)
4930 return -E1000_ERR_CONFIG;
4931
4932 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
4933
4934 return E1000_SUCCESS;
4935}
4936
1da177e4
LT		 4937void
4938e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4939{
4940 outl(value, port);
4941}
4942
4943static void
4944e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4945{
60490fe0 4946 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4947 uint32_t ctrl, rctl;
4948
4949 e1000_irq_disable(adapter);
4950 adapter->vlgrp = grp;
4951
96838a40 4952 if (grp) {
1da177e4
LT		 4953 /* enable VLAN tag insert/strip */
4954 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4955 ctrl |= E1000_CTRL_VME;
4956 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4957
cd94dd0b 4958 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4959 /* enable VLAN receive filtering */
4960 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4961 rctl |= E1000_RCTL_VFE;
4962 rctl &= ~E1000_RCTL_CFIEN;
4963 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4964 e1000_update_mng_vlan(adapter);
cd94dd0b 4965 }
1da177e4
LT		 4966 } else {
4967 /* disable VLAN tag insert/strip */
4968 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4969 ctrl &= ~E1000_CTRL_VME;
4970 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4971
cd94dd0b 4972 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4973 /* disable VLAN filtering */
4974 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4975 rctl &= ~E1000_RCTL_VFE;
4976 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4977 if (adapter->mng_vlan_id !=
4978 (uint16_t)E1000_MNG_VLAN_NONE) {
4979 e1000_vlan_rx_kill_vid(netdev,
4980 adapter->mng_vlan_id);
4981 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4982 }
cd94dd0b 4983 }
1da177e4
LT		 4984 }
4985
4986 e1000_irq_enable(adapter);
4987}
4988
4989static void
4990e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4991{
60490fe0 4992 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4993 uint32_t vfta, index;
96838a40
JB		 4994
4995 if ((adapter->hw.mng_cookie.status &
4996 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4997 (vid == adapter->mng_vlan_id))
2d7edb92 4998 return;
1da177e4
LT		 4999 /* add VID to filter table */
5000 index = (vid >> 5) & 0x7F;
5001 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
5002 vfta |= (1 << (vid & 0x1F));
5003 e1000_write_vfta(&adapter->hw, index, vfta);
5004}
5005
5006static void
5007e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
5008{
60490fe0 5009 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 5010 uint32_t vfta, index;
5011
5012 e1000_irq_disable(adapter);
5c15bdec 5013 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1da177e4
LT		 5014 e1000_irq_enable(adapter);
5015
96838a40
JB		 5016 if ((adapter->hw.mng_cookie.status &
5017 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 5018 (vid == adapter->mng_vlan_id)) {
5019 /* release control to f/w */
5020 e1000_release_hw_control(adapter);
2d7edb92 5021 return;
ff147013
JK		 5022 }
5023
1da177e4
LT		 5024 /* remove VID from filter table */
5025 index = (vid >> 5) & 0x7F;
5026 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
5027 vfta &= ~(1 << (vid & 0x1F));
5028 e1000_write_vfta(&adapter->hw, index, vfta);
5029}
5030
5031static void
5032e1000_restore_vlan(struct e1000_adapter *adapter)
5033{
5034 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5035
96838a40 5036 if (adapter->vlgrp) {
1da177e4 5037 uint16_t vid;
96838a40 5038 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5c15bdec 5039 if (!vlan_group_get_device(adapter->vlgrp, vid))
1da177e4
LT		 5040 continue;
5041 e1000_vlan_rx_add_vid(adapter->netdev, vid);
5042 }
5043 }
5044}
5045
5046int
5047e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
5048{
5049 adapter->hw.autoneg = 0;
5050
6921368f 5051 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 5052 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 5053 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5054 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
5055 return -EINVAL;
5056 }
5057
96838a40 5058 switch (spddplx) {
1da177e4
LT		 5059 case SPEED_10 + DUPLEX_HALF:
5060 adapter->hw.forced_speed_duplex = e1000_10_half;
5061 break;
5062 case SPEED_10 + DUPLEX_FULL:
5063 adapter->hw.forced_speed_duplex = e1000_10_full;
5064 break;
5065 case SPEED_100 + DUPLEX_HALF:
5066 adapter->hw.forced_speed_duplex = e1000_100_half;
5067 break;
5068 case SPEED_100 + DUPLEX_FULL:
5069 adapter->hw.forced_speed_duplex = e1000_100_full;
5070 break;
5071 case SPEED_1000 + DUPLEX_FULL:
5072 adapter->hw.autoneg = 1;
5073 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
5074 break;
5075 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5076 default:
2648345f 5077 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 5078 return -EINVAL;
5079 }
5080 return 0;
5081}
5082
1da177e4 5083static int
829ca9a3 5084e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 5085{
5086 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 5087 struct e1000_adapter *adapter = netdev_priv(netdev);
0fccd0e9 5088 uint32_t ctrl, ctrl_ext, rctl, status;
1da177e4 5089 uint32_t wufc = adapter->wol;
6fdfef16 5090#ifdef CONFIG_PM
240b1710 5091 int retval = 0;
6fdfef16 5092#endif
1da177e4
LT		 5093
5094 netif_device_detach(netdev);
5095
2db10a08
AK		 5096 if (netif_running(netdev)) {
5097 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 5098 e1000_down(adapter);
2db10a08 5099 }
1da177e4 5100
2f82665f 5101#ifdef CONFIG_PM
1d33e9c6 5102 retval = pci_save_state(pdev);
2f82665f
JB		 5103 if (retval)
5104 return retval;
5105#endif
5106
1da177e4 5107 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 5108 if (status & E1000_STATUS_LU)
1da177e4
LT		 5109 wufc &= ~E1000_WUFC_LNKC;
5110
96838a40 5111 if (wufc) {
1da177e4
LT		 5112 e1000_setup_rctl(adapter);
5113 e1000_set_multi(netdev);
5114
5115 /* turn on all-multi mode if wake on multicast is enabled */
120cd576 5116 if (wufc & E1000_WUFC_MC) {
1da177e4
LT		 5117 rctl = E1000_READ_REG(&adapter->hw, RCTL);
5118 rctl |= E1000_RCTL_MPE;
5119 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
5120 }
5121
96838a40 5122 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 5123 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
5124 /* advertise wake from D3Cold */
5125 #define E1000_CTRL_ADVD3WUC 0x00100000
5126 /* phy power management enable */
5127 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5128 ctrl |= E1000_CTRL_ADVD3WUC |
5129 E1000_CTRL_EN_PHY_PWR_MGMT;
5130 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
5131 }
5132
96838a40 5133 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 5134 adapter->hw.media_type == e1000_media_type_internal_serdes) {
5135 /* keep the laser running in D3 */
5136 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
5137 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
5138 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
5139 }
5140
2d7edb92
MC		 5141 /* Allow time for pending master requests to run */
5142 e1000_disable_pciex_master(&adapter->hw);
5143
1da177e4
LT		 5144 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
5145 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 5146 pci_enable_wake(pdev, PCI_D3hot, 1);
5147 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 5148 } else {
5149 E1000_WRITE_REG(&adapter->hw, WUC, 0);
5150 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 5151 pci_enable_wake(pdev, PCI_D3hot, 0);
5152 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 5153 }
5154
0fccd0e9
JG		 5155 e1000_release_manageability(adapter);
5156
5157 /* make sure adapter isn't asleep if manageability is enabled */
5158 if (adapter->en_mng_pt) {
5159 pci_enable_wake(pdev, PCI_D3hot, 1);
5160 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 5161 }
5162
cd94dd0b
AK		 5163 if (adapter->hw.phy_type == e1000_phy_igp_3)
5164 e1000_phy_powerdown_workaround(&adapter->hw);
5165
edd106fc
AK		 5166 if (netif_running(netdev))
5167 e1000_free_irq(adapter);
5168
b55ccb35
JK		 5169 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5170 * would have already happened in close and is redundant. */
5171 e1000_release_hw_control(adapter);
2d7edb92 5172
1da177e4 5173 pci_disable_device(pdev);
240b1710 5174
d0e027db 5175 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 5176
5177 return 0;
5178}
5179
2f82665f 5180#ifdef CONFIG_PM
1da177e4
LT		 5181static int
5182e1000_resume(struct pci_dev *pdev)
5183{
5184 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 5185 struct e1000_adapter *adapter = netdev_priv(netdev);
0fccd0e9 5186 uint32_t err;
1da177e4 5187
d0e027db 5188 pci_set_power_state(pdev, PCI_D0);
1d33e9c6 5189 pci_restore_state(pdev);
3d1dd8cb
AK		 5190 if ((err = pci_enable_device(pdev))) {
5191 printk(KERN_ERR "e1000: Cannot enable PCI device from suspend\n");
5192 return err;
5193 }
a4cb847d 5194 pci_set_master(pdev);
1da177e4 5195
d0e027db
AK		 5196 pci_enable_wake(pdev, PCI_D3hot, 0);
5197 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4 5198
edd106fc
AK		 5199 if (netif_running(netdev) && (err = e1000_request_irq(adapter)))
5200 return err;
5201
5202 e1000_power_up_phy(adapter);
1da177e4
LT		 5203 e1000_reset(adapter);
5204 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
5205
0fccd0e9
JG		 5206 e1000_init_manageability(adapter);
5207
96838a40 5208 if (netif_running(netdev))
1da177e4
LT		 5209 e1000_up(adapter);
5210
5211 netif_device_attach(netdev);
5212
b55ccb35
JK		 5213 /* If the controller is 82573 and f/w is AMT, do not set
5214 * DRV_LOAD until the interface is up. For all other cases,
5215 * let the f/w know that the h/w is now under the control
5216 * of the driver. */
5217 if (adapter->hw.mac_type != e1000_82573 ||
5218 !e1000_check_mng_mode(&adapter->hw))
5219 e1000_get_hw_control(adapter);
2d7edb92 5220
1da177e4
LT		 5221 return 0;
5222}
5223#endif
c653e635
AK		 5224
5225static void e1000_shutdown(struct pci_dev *pdev)
5226{
5227 e1000_suspend(pdev, PMSG_SUSPEND);
5228}
5229
1da177e4
LT		 5230#ifdef CONFIG_NET_POLL_CONTROLLER
5231/*
5232 * Polling 'interrupt' - used by things like netconsole to send skbs
5233 * without having to re-enable interrupts. It's not called while
5234 * the interrupt routine is executing.
5235 */
5236static void
2648345f 5237e1000_netpoll(struct net_device *netdev)
1da177e4 5238{
60490fe0 5239 struct e1000_adapter *adapter = netdev_priv(netdev);
d3d9e484 5240
1da177e4 5241 disable_irq(adapter->pdev->irq);
7d12e780 5242 e1000_intr(adapter->pdev->irq, netdev);
c4cfe567 5243 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 5244#ifndef CONFIG_E1000_NAPI
5245 adapter->clean_rx(adapter, adapter->rx_ring);
5246#endif
1da177e4
LT		 5247 enable_irq(adapter->pdev->irq);
5248}
5249#endif
5250
9026729b
AK		 5251/**
5252 * e1000_io_error_detected - called when PCI error is detected
5253 * @pdev: Pointer to PCI device
5254 * @state: The current pci conneection state
5255 *
5256 * This function is called after a PCI bus error affecting
5257 * this device has been detected.
5258 */
5259static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5260{
5261 struct net_device *netdev = pci_get_drvdata(pdev);
5262 struct e1000_adapter *adapter = netdev->priv;
5263
5264 netif_device_detach(netdev);
5265
5266 if (netif_running(netdev))
5267 e1000_down(adapter);
72e8d6bb 5268 pci_disable_device(pdev);
9026729b
AK		 5269
5270 /* Request a slot slot reset. */
5271 return PCI_ERS_RESULT_NEED_RESET;
5272}
5273
5274/**
5275 * e1000_io_slot_reset - called after the pci bus has been reset.
5276 * @pdev: Pointer to PCI device
5277 *
5278 * Restart the card from scratch, as if from a cold-boot. Implementation
5279 * resembles the first-half of the e1000_resume routine.
5280 */
5281static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5282{
5283 struct net_device *netdev = pci_get_drvdata(pdev);
5284 struct e1000_adapter *adapter = netdev->priv;
5285
5286 if (pci_enable_device(pdev)) {
5287 printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n");
5288 return PCI_ERS_RESULT_DISCONNECT;
5289 }
5290 pci_set_master(pdev);
5291
dbf38c94
LV		 5292 pci_enable_wake(pdev, PCI_D3hot, 0);
5293 pci_enable_wake(pdev, PCI_D3cold, 0);
9026729b 5294
9026729b
AK		 5295 e1000_reset(adapter);
5296 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
5297
5298 return PCI_ERS_RESULT_RECOVERED;
5299}
5300
5301/**
5302 * e1000_io_resume - called when traffic can start flowing again.
5303 * @pdev: Pointer to PCI device
5304 *
5305 * This callback is called when the error recovery driver tells us that
5306 * its OK to resume normal operation. Implementation resembles the
5307 * second-half of the e1000_resume routine.
5308 */
5309static void e1000_io_resume(struct pci_dev *pdev)
5310{
5311 struct net_device *netdev = pci_get_drvdata(pdev);
5312 struct e1000_adapter *adapter = netdev->priv;
0fccd0e9
JG		 5313
5314 e1000_init_manageability(adapter);
9026729b
AK		 5315
5316 if (netif_running(netdev)) {
5317 if (e1000_up(adapter)) {
5318 printk("e1000: can't bring device back up after reset\n");
5319 return;
5320 }
5321 }
5322
5323 netif_device_attach(netdev);
5324
0fccd0e9
JG		 5325 /* If the controller is 82573 and f/w is AMT, do not set
5326 * DRV_LOAD until the interface is up. For all other cases,
5327 * let the f/w know that the h/w is now under the control
5328 * of the driver. */
5329 if (adapter->hw.mac_type != e1000_82573 ||
5330 !e1000_check_mng_mode(&adapter->hw))
5331 e1000_get_hw_control(adapter);
9026729b 5332
9026729b
AK		 5333}
5334
1da177e4 5335/* e1000_main.c */
Linux 6.x block layer and io_uring tree(s)