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e1000: M88 PHY workaround
[linux-2.6-block.git] / drivers / net / e1000 / e1000_hw.h
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
3d41e30a 4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
3d41e30a 25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27
28*******************************************************************************/
29
30/* e1000_hw.h
31 * Structures, enums, and macros for the MAC
32 */
33
34#ifndef _E1000_HW_H_
35#define _E1000_HW_H_
36
37#include "e1000_osdep.h"
38
39
40/* Forward declarations of structures used by the shared code */
41struct e1000_hw;
42struct e1000_hw_stats;
43
44/* Enumerated types specific to the e1000 hardware */
45/* Media Access Controlers */
46typedef enum {
47 e1000_undefined = 0,
48 e1000_82542_rev2_0,
49 e1000_82542_rev2_1,
50 e1000_82543,
51 e1000_82544,
52 e1000_82540,
53 e1000_82545,
54 e1000_82545_rev_3,
55 e1000_82546,
56 e1000_82546_rev_3,
57 e1000_82541,
58 e1000_82541_rev_2,
59 e1000_82547,
60 e1000_82547_rev_2,
868d5309
MC		 61 e1000_82571,
62 e1000_82572,
2d7edb92 63 e1000_82573,
6418ecc6 64 e1000_80003es2lan,
1da177e4
LT		 65 e1000_num_macs
66} e1000_mac_type;
67
68typedef enum {
69 e1000_eeprom_uninitialized = 0,
70 e1000_eeprom_spi,
71 e1000_eeprom_microwire,
2d7edb92 72 e1000_eeprom_flash,
3893d547 73 e1000_eeprom_none, /* No NVM support */
1da177e4
LT		 74 e1000_num_eeprom_types
75} e1000_eeprom_type;
76
77/* Media Types */
78typedef enum {
79 e1000_media_type_copper = 0,
80 e1000_media_type_fiber = 1,
81 e1000_media_type_internal_serdes = 2,
82 e1000_num_media_types
83} e1000_media_type;
84
85typedef enum {
86 e1000_10_half = 0,
87 e1000_10_full = 1,
88 e1000_100_half = 2,
89 e1000_100_full = 3
90} e1000_speed_duplex_type;
91
92/* Flow Control Settings */
93typedef enum {
94 e1000_fc_none = 0,
95 e1000_fc_rx_pause = 1,
96 e1000_fc_tx_pause = 2,
97 e1000_fc_full = 3,
98 e1000_fc_default = 0xFF
99} e1000_fc_type;
100
101/* PCI bus types */
102typedef enum {
103 e1000_bus_type_unknown = 0,
104 e1000_bus_type_pci,
105 e1000_bus_type_pcix,
2d7edb92 106 e1000_bus_type_pci_express,
1da177e4
LT		 107 e1000_bus_type_reserved
108} e1000_bus_type;
109
110/* PCI bus speeds */
111typedef enum {
112 e1000_bus_speed_unknown = 0,
113 e1000_bus_speed_33,
114 e1000_bus_speed_66,
115 e1000_bus_speed_100,
116 e1000_bus_speed_120,
117 e1000_bus_speed_133,
2d7edb92 118 e1000_bus_speed_2500,
1da177e4
LT		 119 e1000_bus_speed_reserved
120} e1000_bus_speed;
121
122/* PCI bus widths */
123typedef enum {
124 e1000_bus_width_unknown = 0,
125 e1000_bus_width_32,
126 e1000_bus_width_64,
2d7edb92 127 e1000_bus_width_pciex_1,
fd803241 128 e1000_bus_width_pciex_2,
2d7edb92 129 e1000_bus_width_pciex_4,
1da177e4
LT		 130 e1000_bus_width_reserved
131} e1000_bus_width;
132
133/* PHY status info structure and supporting enums */
134typedef enum {
135 e1000_cable_length_50 = 0,
136 e1000_cable_length_50_80,
137 e1000_cable_length_80_110,
138 e1000_cable_length_110_140,
139 e1000_cable_length_140,
140 e1000_cable_length_undefined = 0xFF
141} e1000_cable_length;
142
6418ecc6
JK		 143typedef enum {
144 e1000_gg_cable_length_60 = 0,
145 e1000_gg_cable_length_60_115 = 1,
146 e1000_gg_cable_length_115_150 = 2,
147 e1000_gg_cable_length_150 = 4
148} e1000_gg_cable_length;
149
1da177e4
LT		 150typedef enum {
151 e1000_igp_cable_length_10 = 10,
152 e1000_igp_cable_length_20 = 20,
153 e1000_igp_cable_length_30 = 30,
154 e1000_igp_cable_length_40 = 40,
155 e1000_igp_cable_length_50 = 50,
156 e1000_igp_cable_length_60 = 60,
157 e1000_igp_cable_length_70 = 70,
158 e1000_igp_cable_length_80 = 80,
159 e1000_igp_cable_length_90 = 90,
160 e1000_igp_cable_length_100 = 100,
161 e1000_igp_cable_length_110 = 110,
fd803241 162 e1000_igp_cable_length_115 = 115,
1da177e4
LT		 163 e1000_igp_cable_length_120 = 120,
164 e1000_igp_cable_length_130 = 130,
165 e1000_igp_cable_length_140 = 140,
166 e1000_igp_cable_length_150 = 150,
167 e1000_igp_cable_length_160 = 160,
168 e1000_igp_cable_length_170 = 170,
169 e1000_igp_cable_length_180 = 180
170} e1000_igp_cable_length;
171
172typedef enum {
173 e1000_10bt_ext_dist_enable_normal = 0,
174 e1000_10bt_ext_dist_enable_lower,
175 e1000_10bt_ext_dist_enable_undefined = 0xFF
176} e1000_10bt_ext_dist_enable;
177
178typedef enum {
179 e1000_rev_polarity_normal = 0,
180 e1000_rev_polarity_reversed,
181 e1000_rev_polarity_undefined = 0xFF
182} e1000_rev_polarity;
183
184typedef enum {
185 e1000_downshift_normal = 0,
186 e1000_downshift_activated,
187 e1000_downshift_undefined = 0xFF
188} e1000_downshift;
189
190typedef enum {
191 e1000_smart_speed_default = 0,
192 e1000_smart_speed_on,
193 e1000_smart_speed_off
194} e1000_smart_speed;
195
196typedef enum {
197 e1000_polarity_reversal_enabled = 0,
198 e1000_polarity_reversal_disabled,
199 e1000_polarity_reversal_undefined = 0xFF
200} e1000_polarity_reversal;
201
202typedef enum {
203 e1000_auto_x_mode_manual_mdi = 0,
204 e1000_auto_x_mode_manual_mdix,
205 e1000_auto_x_mode_auto1,
206 e1000_auto_x_mode_auto2,
207 e1000_auto_x_mode_undefined = 0xFF
208} e1000_auto_x_mode;
209
210typedef enum {
211 e1000_1000t_rx_status_not_ok = 0,
212 e1000_1000t_rx_status_ok,
213 e1000_1000t_rx_status_undefined = 0xFF
214} e1000_1000t_rx_status;
215
216typedef enum {
217 e1000_phy_m88 = 0,
218 e1000_phy_igp,
2d7edb92 219 e1000_phy_igp_2,
6418ecc6 220 e1000_phy_gg82563,
1da177e4
LT		 221 e1000_phy_undefined = 0xFF
222} e1000_phy_type;
223
224typedef enum {
225 e1000_ms_hw_default = 0,
226 e1000_ms_force_master,
227 e1000_ms_force_slave,
228 e1000_ms_auto
229} e1000_ms_type;
230
231typedef enum {
232 e1000_ffe_config_enabled = 0,
233 e1000_ffe_config_active,
234 e1000_ffe_config_blocked
235} e1000_ffe_config;
236
237typedef enum {
238 e1000_dsp_config_disabled = 0,
239 e1000_dsp_config_enabled,
240 e1000_dsp_config_activated,
241 e1000_dsp_config_undefined = 0xFF
242} e1000_dsp_config;
243
244struct e1000_phy_info {
245 e1000_cable_length cable_length;
246 e1000_10bt_ext_dist_enable extended_10bt_distance;
247 e1000_rev_polarity cable_polarity;
248 e1000_downshift downshift;
249 e1000_polarity_reversal polarity_correction;
250 e1000_auto_x_mode mdix_mode;
251 e1000_1000t_rx_status local_rx;
252 e1000_1000t_rx_status remote_rx;
253};
254
255struct e1000_phy_stats {
256 uint32_t idle_errors;
257 uint32_t receive_errors;
258};
259
260struct e1000_eeprom_info {
261 e1000_eeprom_type type;
262 uint16_t word_size;
263 uint16_t opcode_bits;
264 uint16_t address_bits;
265 uint16_t delay_usec;
266 uint16_t page_size;
2d7edb92
MC		 267 boolean_t use_eerd;
268 boolean_t use_eewr;
1da177e4
LT		 269};
270
2d7edb92
MC		 271/* Flex ASF Information */
272#define E1000_HOST_IF_MAX_SIZE 2048
273
274typedef enum {
275 e1000_byte_align = 0,
276 e1000_word_align = 1,
277 e1000_dword_align = 2
278} e1000_align_type;
279
1da177e4
LT		 280
281
282/* Error Codes */
283#define E1000_SUCCESS 0
284#define E1000_ERR_EEPROM 1
285#define E1000_ERR_PHY 2
286#define E1000_ERR_CONFIG 3
287#define E1000_ERR_PARAM 4
288#define E1000_ERR_MAC_TYPE 5
289#define E1000_ERR_PHY_TYPE 6
2d7edb92
MC		 290#define E1000_ERR_RESET 9
291#define E1000_ERR_MASTER_REQUESTS_PENDING 10
292#define E1000_ERR_HOST_INTERFACE_COMMAND 11
293#define E1000_BLK_PHY_RESET 12
6418ecc6 294#define E1000_ERR_SWFW_SYNC 13
1da177e4
LT		 295
296/* Function prototypes */
297/* Initialization */
298int32_t e1000_reset_hw(struct e1000_hw *hw);
299int32_t e1000_init_hw(struct e1000_hw *hw);
300int32_t e1000_set_mac_type(struct e1000_hw *hw);
301void e1000_set_media_type(struct e1000_hw *hw);
302
303/* Link Configuration */
304int32_t e1000_setup_link(struct e1000_hw *hw);
305int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
306void e1000_config_collision_dist(struct e1000_hw *hw);
1da177e4
LT		 307int32_t e1000_check_for_link(struct e1000_hw *hw);
308int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
1da177e4
LT		 309int32_t e1000_force_mac_fc(struct e1000_hw *hw);
310
311/* PHY */
312int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
313int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
2d7edb92 314int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
1da177e4 315int32_t e1000_phy_reset(struct e1000_hw *hw);
1da177e4 316int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
1da177e4 317int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
6418ecc6
JK		 318int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
319int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
1da177e4
LT		 320
321/* EEPROM Functions */
2d7edb92 322int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
2d7edb92
MC		 323
324/* MNG HOST IF functions */
325uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
326
327#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
328#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
329
330#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
331#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
332#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
333#define E1000_MNG_IAMT_MODE 0x3
334#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
335
336#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
337#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
338#define E1000_VFTA_ENTRY_SHIFT 0x5
339#define E1000_VFTA_ENTRY_MASK 0x7F
340#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
341
342struct e1000_host_mng_command_header {
343 uint8_t command_id;
344 uint8_t checksum;
345 uint16_t reserved1;
346 uint16_t reserved2;
347 uint16_t command_length;
348};
349
350struct e1000_host_mng_command_info {
351 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
352 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
353};
354#ifdef __BIG_ENDIAN
355struct e1000_host_mng_dhcp_cookie{
356 uint32_t signature;
357 uint16_t vlan_id;
358 uint8_t reserved0;
359 uint8_t status;
360 uint32_t reserved1;
361 uint8_t checksum;
362 uint8_t reserved3;
363 uint16_t reserved2;
364};
365#else
366struct e1000_host_mng_dhcp_cookie{
367 uint32_t signature;
368 uint8_t status;
369 uint8_t reserved0;
370 uint16_t vlan_id;
371 uint32_t reserved1;
372 uint16_t reserved2;
373 uint8_t reserved3;
374 uint8_t checksum;
375};
376#endif
377
76c224bc 378int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
2d7edb92
MC		 379 uint16_t length);
380boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
381boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
2d7edb92 382
1da177e4
LT		 383int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
384int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
385int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
386int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
387int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
388int32_t e1000_read_mac_addr(struct e1000_hw * hw);
2d7edb92
MC		 389int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
390void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
1da177e4
LT		 391
392/* Filters (multicast, vlan, receive) */
6150f038 393void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
1da177e4
LT		 394uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
395void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
396void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
397void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
1da177e4
LT		 398
399/* LED functions */
400int32_t e1000_setup_led(struct e1000_hw *hw);
401int32_t e1000_cleanup_led(struct e1000_hw *hw);
402int32_t e1000_led_on(struct e1000_hw *hw);
403int32_t e1000_led_off(struct e1000_hw *hw);
f1b3a853 404int32_t e1000_blink_led_start(struct e1000_hw *hw);
1da177e4
LT		 405
406/* Adaptive IFS Functions */
407
408/* Everything else */
1da177e4
LT		 409void e1000_reset_adaptive(struct e1000_hw *hw);
410void e1000_update_adaptive(struct e1000_hw *hw);
411void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
412void e1000_get_bus_info(struct e1000_hw *hw);
413void e1000_pci_set_mwi(struct e1000_hw *hw);
414void e1000_pci_clear_mwi(struct e1000_hw *hw);
415void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
416void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
417/* Port I/O is only supported on 82544 and newer */
418uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
6150f038 419uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
1da177e4 420void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
6150f038 421void e1000_enable_pciex_master(struct e1000_hw *hw);
2d7edb92 422int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
2d7edb92
MC		 423int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
424void e1000_release_software_semaphore(struct e1000_hw *hw);
425int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
1da177e4
LT		 426
427/* PCI Device IDs */
428#define E1000_DEV_ID_82542 0x1000
429#define E1000_DEV_ID_82543GC_FIBER 0x1001
430#define E1000_DEV_ID_82543GC_COPPER 0x1004
431#define E1000_DEV_ID_82544EI_COPPER 0x1008
432#define E1000_DEV_ID_82544EI_FIBER 0x1009
433#define E1000_DEV_ID_82544GC_COPPER 0x100C
434#define E1000_DEV_ID_82544GC_LOM 0x100D
435#define E1000_DEV_ID_82540EM 0x100E
436#define E1000_DEV_ID_82540EM_LOM 0x1015
437#define E1000_DEV_ID_82540EP_LOM 0x1016
438#define E1000_DEV_ID_82540EP 0x1017
439#define E1000_DEV_ID_82540EP_LP 0x101E
440#define E1000_DEV_ID_82545EM_COPPER 0x100F
441#define E1000_DEV_ID_82545EM_FIBER 0x1011
442#define E1000_DEV_ID_82545GM_COPPER 0x1026
443#define E1000_DEV_ID_82545GM_FIBER 0x1027
444#define E1000_DEV_ID_82545GM_SERDES 0x1028
445#define E1000_DEV_ID_82546EB_COPPER 0x1010
446#define E1000_DEV_ID_82546EB_FIBER 0x1012
447#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
448#define E1000_DEV_ID_82541EI 0x1013
449#define E1000_DEV_ID_82541EI_MOBILE 0x1018
450#define E1000_DEV_ID_82541ER 0x1078
451#define E1000_DEV_ID_82547GI 0x1075
452#define E1000_DEV_ID_82541GI 0x1076
453#define E1000_DEV_ID_82541GI_MOBILE 0x1077
454#define E1000_DEV_ID_82541GI_LF 0x107C
455#define E1000_DEV_ID_82546GB_COPPER 0x1079
456#define E1000_DEV_ID_82546GB_FIBER 0x107A
457#define E1000_DEV_ID_82546GB_SERDES 0x107B
458#define E1000_DEV_ID_82546GB_PCIE 0x108A
b7ee49db 459#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
1da177e4 460#define E1000_DEV_ID_82547EI 0x1019
868d5309
MC		 461#define E1000_DEV_ID_82571EB_COPPER 0x105E
462#define E1000_DEV_ID_82571EB_FIBER 0x105F
463#define E1000_DEV_ID_82571EB_SERDES 0x1060
464#define E1000_DEV_ID_82572EI_COPPER 0x107D
465#define E1000_DEV_ID_82572EI_FIBER 0x107E
466#define E1000_DEV_ID_82572EI_SERDES 0x107F
2d7edb92
MC		 467#define E1000_DEV_ID_82573E 0x108B
468#define E1000_DEV_ID_82573E_IAMT 0x108C
868d5309 469#define E1000_DEV_ID_82573L 0x109A
b7ee49db 470#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
6418ecc6
JK		 471#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
472#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
2d7edb92 473
1da177e4
LT		 474
475#define NODE_ADDRESS_SIZE 6
476#define ETH_LENGTH_OF_ADDRESS 6
477
478/* MAC decode size is 128K - This is the size of BAR0 */
479#define MAC_DECODE_SIZE (128 * 1024)
480
481#define E1000_82542_2_0_REV_ID 2
482#define E1000_82542_2_1_REV_ID 3
483#define E1000_REVISION_0 0
484#define E1000_REVISION_1 1
485#define E1000_REVISION_2 2
2d7edb92 486#define E1000_REVISION_3 3
1da177e4
LT		 487
488#define SPEED_10 10
489#define SPEED_100 100
490#define SPEED_1000 1000
491#define HALF_DUPLEX 1
492#define FULL_DUPLEX 2
493
494/* The sizes (in bytes) of a ethernet packet */
495#define ENET_HEADER_SIZE 14
496#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
497#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
498#define ETHERNET_FCS_SIZE 4
499#define MAXIMUM_ETHERNET_PACKET_SIZE \
500 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
501#define MINIMUM_ETHERNET_PACKET_SIZE \
502 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
503#define CRC_LENGTH ETHERNET_FCS_SIZE
504#define MAX_JUMBO_FRAME_SIZE 0x3F00
505
506
507/* 802.1q VLAN Packet Sizes */
508#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
509
510/* Ethertype field values */
511#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
512#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
513#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
514
515/* Packet Header defines */
516#define IP_PROTOCOL_TCP 6
517#define IP_PROTOCOL_UDP 0x11
518
519/* This defines the bits that are set in the Interrupt Mask
520 * Set/Read Register. Each bit is documented below:
521 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
522 * o RXSEQ = Receive Sequence Error
523 */
524#define POLL_IMS_ENABLE_MASK ( \
525 E1000_IMS_RXDMT0 | \
526 E1000_IMS_RXSEQ)
527
528/* This defines the bits that are set in the Interrupt Mask
529 * Set/Read Register. Each bit is documented below:
530 * o RXT0 = Receiver Timer Interrupt (ring 0)
531 * o TXDW = Transmit Descriptor Written Back
532 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
533 * o RXSEQ = Receive Sequence Error
534 * o LSC = Link Status Change
535 */
536#define IMS_ENABLE_MASK ( \
537 E1000_IMS_RXT0 | \
538 E1000_IMS_TXDW | \
539 E1000_IMS_RXDMT0 | \
540 E1000_IMS_RXSEQ | \
541 E1000_IMS_LSC)
542
2d7edb92 543
1da177e4
LT		 544/* Number of high/low register pairs in the RAR. The RAR (Receive Address
545 * Registers) holds the directed and multicast addresses that we monitor. We
546 * reserve one of these spots for our directed address, allowing us room for
547 * E1000_RAR_ENTRIES - 1 multicast addresses.
548 */
549#define E1000_RAR_ENTRIES 15
550
551#define MIN_NUMBER_OF_DESCRIPTORS 8
552#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
553
554/* Receive Descriptor */
555struct e1000_rx_desc {
556 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
557 uint16_t length; /* Length of data DMAed into data buffer */
558 uint16_t csum; /* Packet checksum */
559 uint8_t status; /* Descriptor status */
560 uint8_t errors; /* Descriptor Errors */
561 uint16_t special;
562};
563
2d7edb92
MC		 564/* Receive Descriptor - Extended */
565union e1000_rx_desc_extended {
566 struct {
567 uint64_t buffer_addr;
568 uint64_t reserved;
569 } read;
570 struct {
571 struct {
572 uint32_t mrq; /* Multiple Rx Queues */
573 union {
574 uint32_t rss; /* RSS Hash */
575 struct {
576 uint16_t ip_id; /* IP id */
577 uint16_t csum; /* Packet Checksum */
578 } csum_ip;
579 } hi_dword;
580 } lower;
581 struct {
582 uint32_t status_error; /* ext status/error */
583 uint16_t length;
584 uint16_t vlan; /* VLAN tag */
585 } upper;
586 } wb; /* writeback */
587};
588
589#define MAX_PS_BUFFERS 4
590/* Receive Descriptor - Packet Split */
591union e1000_rx_desc_packet_split {
592 struct {
593 /* one buffer for protocol header(s), three data buffers */
594 uint64_t buffer_addr[MAX_PS_BUFFERS];
595 } read;
596 struct {
597 struct {
598 uint32_t mrq; /* Multiple Rx Queues */
599 union {
600 uint32_t rss; /* RSS Hash */
601 struct {
602 uint16_t ip_id; /* IP id */
603 uint16_t csum; /* Packet Checksum */
604 } csum_ip;
605 } hi_dword;
606 } lower;
607 struct {
608 uint32_t status_error; /* ext status/error */
609 uint16_t length0; /* length of buffer 0 */
610 uint16_t vlan; /* VLAN tag */
611 } middle;
612 struct {
613 uint16_t header_status;
614 uint16_t length[3]; /* length of buffers 1-3 */
615 } upper;
616 uint64_t reserved;
617 } wb; /* writeback */
618};
619
1da177e4
LT		 620/* Receive Decriptor bit definitions */
621#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
622#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
623#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
624#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
2d7edb92 625#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
1da177e4
LT		 626#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
627#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
628#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
2d7edb92
MC		 629#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
630#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
631#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
1da177e4
LT		 632#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
633#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
634#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
635#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
636#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
637#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
638#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
639#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
640#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
2d7edb92 641#define E1000_RXD_SPC_PRI_SHIFT 13
1da177e4 642#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
2d7edb92
MC		 643#define E1000_RXD_SPC_CFI_SHIFT 12
644
645#define E1000_RXDEXT_STATERR_CE 0x01000000
646#define E1000_RXDEXT_STATERR_SE 0x02000000
647#define E1000_RXDEXT_STATERR_SEQ 0x04000000
648#define E1000_RXDEXT_STATERR_CXE 0x10000000
649#define E1000_RXDEXT_STATERR_TCPE 0x20000000
650#define E1000_RXDEXT_STATERR_IPE 0x40000000
651#define E1000_RXDEXT_STATERR_RXE 0x80000000
652
653#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
654#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1da177e4
LT		 655
656/* mask to determine if packets should be dropped due to frame errors */
657#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
658 E1000_RXD_ERR_CE | \
659 E1000_RXD_ERR_SE | \
660 E1000_RXD_ERR_SEQ | \
661 E1000_RXD_ERR_CXE | \
662 E1000_RXD_ERR_RXE)
663
2d7edb92
MC		 664
665/* Same mask, but for extended and packet split descriptors */
666#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
667 E1000_RXDEXT_STATERR_CE | \
668 E1000_RXDEXT_STATERR_SE | \
669 E1000_RXDEXT_STATERR_SEQ | \
670 E1000_RXDEXT_STATERR_CXE | \
671 E1000_RXDEXT_STATERR_RXE)
672
1da177e4
LT		 673/* Transmit Descriptor */
674struct e1000_tx_desc {
675 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
676 union {
677 uint32_t data;
678 struct {
679 uint16_t length; /* Data buffer length */
680 uint8_t cso; /* Checksum offset */
681 uint8_t cmd; /* Descriptor control */
682 } flags;
683 } lower;
684 union {
685 uint32_t data;
686 struct {
687 uint8_t status; /* Descriptor status */
688 uint8_t css; /* Checksum start */
689 uint16_t special;
690 } fields;
691 } upper;
692};
693
694/* Transmit Descriptor bit definitions */
695#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
696#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
697#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
698#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
699#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
700#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
701#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
702#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
703#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
704#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
705#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
706#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
707#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
708#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
709#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
710#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
711#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
712#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
713#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
714#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
715
716/* Offload Context Descriptor */
717struct e1000_context_desc {
718 union {
719 uint32_t ip_config;
720 struct {
721 uint8_t ipcss; /* IP checksum start */
722 uint8_t ipcso; /* IP checksum offset */
723 uint16_t ipcse; /* IP checksum end */
724 } ip_fields;
725 } lower_setup;
726 union {
727 uint32_t tcp_config;
728 struct {
729 uint8_t tucss; /* TCP checksum start */
730 uint8_t tucso; /* TCP checksum offset */
731 uint16_t tucse; /* TCP checksum end */
732 } tcp_fields;
733 } upper_setup;
734 uint32_t cmd_and_length; /* */
735 union {
736 uint32_t data;
737 struct {
738 uint8_t status; /* Descriptor status */
739 uint8_t hdr_len; /* Header length */
740 uint16_t mss; /* Maximum segment size */
741 } fields;
742 } tcp_seg_setup;
743};
744
745/* Offload data descriptor */
746struct e1000_data_desc {
747 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
748 union {
749 uint32_t data;
750 struct {
751 uint16_t length; /* Data buffer length */
752 uint8_t typ_len_ext; /* */
753 uint8_t cmd; /* */
754 } flags;
755 } lower;
756 union {
757 uint32_t data;
758 struct {
759 uint8_t status; /* Descriptor status */
760 uint8_t popts; /* Packet Options */
761 uint16_t special; /* */
762 } fields;
763 } upper;
764};
765
766/* Filters */
767#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
768#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
769#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
770
771
772/* Receive Address Register */
773struct e1000_rar {
774 volatile uint32_t low; /* receive address low */
775 volatile uint32_t high; /* receive address high */
776};
777
778/* Number of entries in the Multicast Table Array (MTA). */
779#define E1000_NUM_MTA_REGISTERS 128
780
781/* IPv4 Address Table Entry */
782struct e1000_ipv4_at_entry {
783 volatile uint32_t ipv4_addr; /* IP Address (RW) */
784 volatile uint32_t reserved;
785};
786
787/* Four wakeup IP addresses are supported */
788#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
789#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
790#define E1000_IP6AT_SIZE 1
791
792/* IPv6 Address Table Entry */
793struct e1000_ipv6_at_entry {
794 volatile uint8_t ipv6_addr[16];
795};
796
797/* Flexible Filter Length Table Entry */
798struct e1000_fflt_entry {
799 volatile uint32_t length; /* Flexible Filter Length (RW) */
800 volatile uint32_t reserved;
801};
802
803/* Flexible Filter Mask Table Entry */
804struct e1000_ffmt_entry {
805 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
806 volatile uint32_t reserved;
807};
808
809/* Flexible Filter Value Table Entry */
810struct e1000_ffvt_entry {
811 volatile uint32_t value; /* Flexible Filter Value (RW) */
812 volatile uint32_t reserved;
813};
814
815/* Four Flexible Filters are supported */
816#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
817
818/* Each Flexible Filter is at most 128 (0x80) bytes in length */
819#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
820
821#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
822#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
823#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
824
868d5309
MC		 825#define E1000_DISABLE_SERDES_LOOPBACK 0x0400
826
1da177e4
LT		 827/* Register Set. (82543, 82544)
828 *
829 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
830 * These registers are physically located on the NIC, but are mapped into the
831 * host memory address space.
832 *
833 * RW - register is both readable and writable
834 * RO - register is read only
835 * WO - register is write only
836 * R/clr - register is read only and is cleared when read
837 * A - register array
838 */
839#define E1000_CTRL 0x00000 /* Device Control - RW */
840#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
841#define E1000_STATUS 0x00008 /* Device Status - RO */
842#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
843#define E1000_EERD 0x00014 /* EEPROM Read - RW */
844#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
845#define E1000_FLA 0x0001C /* Flash Access - RW */
846#define E1000_MDIC 0x00020 /* MDI Control - RW */
868d5309 847#define E1000_SCTL 0x00024 /* SerDes Control - RW */
1da177e4
LT		 848#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
849#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
850#define E1000_FCT 0x00030 /* Flow Control Type - RW */
851#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
852#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
853#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
854#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
855#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
856#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
2d7edb92 857#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
1da177e4 858#define E1000_RCTL 0x00100 /* RX Control - RW */
868d5309
MC		 859#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
860#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
861#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
862#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
863#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
864#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
1da177e4
LT		 865#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
866#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
867#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
868#define E1000_TCTL 0x00400 /* TX Control - RW */
6418ecc6 869#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
1da177e4
LT		 870#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
871#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
872#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
873#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
2d7edb92
MC		 874#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
875#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
1da177e4 876#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
2d7edb92
MC		 877#define E1000_PBS 0x01008 /* Packet Buffer Size */
878#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
879#define E1000_FLASH_UPDATES 1000
880#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
881#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
882#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
883#define E1000_FLSWCTL 0x01030 /* FLASH control register */
884#define E1000_FLSWDATA 0x01034 /* FLASH data register */
885#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
886#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
887#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
1da177e4
LT		 888#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
889#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
2d7edb92 890#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
1da177e4
LT		 891#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
892#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
893#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
894#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
895#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
896#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
868d5309
MC		 897#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
898#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
899#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
900#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
901#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
902#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
1da177e4
LT		 903#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
904#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
905#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
2d7edb92 906#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
1da177e4
LT		 907#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
908#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
909#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
910#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
911#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
912#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
913#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
914#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
915#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
916#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
917#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
918#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
919#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
920#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
921#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
96838a40
JB		 922#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
923#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
924#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
925#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
926#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
927#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
928#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
929#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
1da177e4
LT		 930#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
931#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
932#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
933#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
934#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
935#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
936#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
937#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
938#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
939#define E1000_COLC 0x04028 /* Collision Count - R/clr */
940#define E1000_DC 0x04030 /* Defer Count - R/clr */
941#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
942#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
943#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
944#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
945#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
946#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
947#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
948#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
949#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
950#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
951#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
952#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
953#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
954#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
955#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
956#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
957#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
958#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
959#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
960#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
961#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
962#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
963#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
964#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
965#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
966#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
967#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
968#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
969#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
970#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
971#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
972#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
973#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
974#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
975#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
976#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
977#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
978#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
979#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
980#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
981#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
982#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
983#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
984#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
985#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
986#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
987#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
868d5309
MC		 988#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
989#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
990#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
991#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
992#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
993#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
994#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
995#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
996#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
1da177e4 997#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
2d7edb92 998#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
1da177e4
LT		 999#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
1000#define E1000_RA 0x05400 /* Receive Address - RW Array */
1001#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
1002#define E1000_WUC 0x05800 /* Wakeup Control - RW */
1003#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
1004#define E1000_WUS 0x05810 /* Wakeup Status - RO */
1005#define E1000_MANC 0x05820 /* Management Control - RW */
1006#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
1007#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
1008#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
1009#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
1010#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
1011#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
1012#define E1000_HOST_IF 0x08800 /* Host Interface */
1013#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
1014#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1015
6418ecc6
JK		 1016#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
1017#define E1000_MDPHYA 0x0003C /* PHY address - RW */
1018#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */
1019#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
1020
2d7edb92
MC		 1021#define E1000_GCR 0x05B00 /* PCI-Ex Control */
1022#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1023#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1024#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1025#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1026#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1027#define E1000_SWSM 0x05B50 /* SW Semaphore */
1028#define E1000_FWSM 0x05B54 /* FW Semaphore */
1029#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1030#define E1000_HICR 0x08F00 /* Host Inteface Control */
868d5309
MC		 1031
1032/* RSS registers */
1033#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1034#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1035#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1036#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1037#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1038#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1da177e4
LT		 1039/* Register Set (82542)
1040 *
1041 * Some of the 82542 registers are located at different offsets than they are
1042 * in more current versions of the 8254x. Despite the difference in location,
1043 * the registers function in the same manner.
1044 */
1045#define E1000_82542_CTRL E1000_CTRL
1046#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1047#define E1000_82542_STATUS E1000_STATUS
1048#define E1000_82542_EECD E1000_EECD
1049#define E1000_82542_EERD E1000_EERD
1050#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1051#define E1000_82542_FLA E1000_FLA
1052#define E1000_82542_MDIC E1000_MDIC
868d5309 1053#define E1000_82542_SCTL E1000_SCTL
1da177e4
LT		 1054#define E1000_82542_FCAL E1000_FCAL
1055#define E1000_82542_FCAH E1000_FCAH
1056#define E1000_82542_FCT E1000_FCT
1057#define E1000_82542_VET E1000_VET
1058#define E1000_82542_RA 0x00040
1059#define E1000_82542_ICR E1000_ICR
1060#define E1000_82542_ITR E1000_ITR
1061#define E1000_82542_ICS E1000_ICS
1062#define E1000_82542_IMS E1000_IMS
1063#define E1000_82542_IMC E1000_IMC
1064#define E1000_82542_RCTL E1000_RCTL
1065#define E1000_82542_RDTR 0x00108
1066#define E1000_82542_RDBAL 0x00110
1067#define E1000_82542_RDBAH 0x00114
1068#define E1000_82542_RDLEN 0x00118
1069#define E1000_82542_RDH 0x00120
1070#define E1000_82542_RDT 0x00128
868d5309
MC		 1071#define E1000_82542_RDTR0 E1000_82542_RDTR
1072#define E1000_82542_RDBAL0 E1000_82542_RDBAL
1073#define E1000_82542_RDBAH0 E1000_82542_RDBAH
1074#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1075#define E1000_82542_RDH0 E1000_82542_RDH
1076#define E1000_82542_RDT0 E1000_82542_RDT
1077#define E1000_82542_RDTR1 0x00130
1078#define E1000_82542_RDBAL1 0x00138
1079#define E1000_82542_RDBAH1 0x0013C
1080#define E1000_82542_RDLEN1 0x00140
1081#define E1000_82542_RDH1 0x00148
1082#define E1000_82542_RDT1 0x00150
1da177e4
LT		 1083#define E1000_82542_FCRTH 0x00160
1084#define E1000_82542_FCRTL 0x00168
1085#define E1000_82542_FCTTV E1000_FCTTV
1086#define E1000_82542_TXCW E1000_TXCW
1087#define E1000_82542_RXCW E1000_RXCW
1088#define E1000_82542_MTA 0x00200
1089#define E1000_82542_TCTL E1000_TCTL
6418ecc6 1090#define E1000_82542_TCTL_EXT E1000_TCTL_EXT
1da177e4
LT		 1091#define E1000_82542_TIPG E1000_TIPG
1092#define E1000_82542_TDBAL 0x00420
1093#define E1000_82542_TDBAH 0x00424
1094#define E1000_82542_TDLEN 0x00428
1095#define E1000_82542_TDH 0x00430
1096#define E1000_82542_TDT 0x00438
1097#define E1000_82542_TIDV 0x00440
1098#define E1000_82542_TBT E1000_TBT
1099#define E1000_82542_AIT E1000_AIT
1100#define E1000_82542_VFTA 0x00600
1101#define E1000_82542_LEDCTL E1000_LEDCTL
1102#define E1000_82542_PBA E1000_PBA
2d7edb92
MC		 1103#define E1000_82542_PBS E1000_PBS
1104#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1105#define E1000_82542_EEARBC E1000_EEARBC
1106#define E1000_82542_FLASHT E1000_FLASHT
1107#define E1000_82542_EEWR E1000_EEWR
1108#define E1000_82542_FLSWCTL E1000_FLSWCTL
1109#define E1000_82542_FLSWDATA E1000_FLSWDATA
1110#define E1000_82542_FLSWCNT E1000_FLSWCNT
1111#define E1000_82542_FLOP E1000_FLOP
1112#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1113#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1114#define E1000_82542_ERT E1000_ERT
1da177e4
LT		 1115#define E1000_82542_RXDCTL E1000_RXDCTL
1116#define E1000_82542_RADV E1000_RADV
1117#define E1000_82542_RSRPD E1000_RSRPD
1118#define E1000_82542_TXDMAC E1000_TXDMAC
1119#define E1000_82542_TDFHS E1000_TDFHS
1120#define E1000_82542_TDFTS E1000_TDFTS
1121#define E1000_82542_TDFPC E1000_TDFPC
1122#define E1000_82542_TXDCTL E1000_TXDCTL
1123#define E1000_82542_TADV E1000_TADV
1124#define E1000_82542_TSPMT E1000_TSPMT
1125#define E1000_82542_CRCERRS E1000_CRCERRS
1126#define E1000_82542_ALGNERRC E1000_ALGNERRC
1127#define E1000_82542_SYMERRS E1000_SYMERRS
1128#define E1000_82542_RXERRC E1000_RXERRC
1129#define E1000_82542_MPC E1000_MPC
1130#define E1000_82542_SCC E1000_SCC
1131#define E1000_82542_ECOL E1000_ECOL
1132#define E1000_82542_MCC E1000_MCC
1133#define E1000_82542_LATECOL E1000_LATECOL
1134#define E1000_82542_COLC E1000_COLC
1135#define E1000_82542_DC E1000_DC
1136#define E1000_82542_TNCRS E1000_TNCRS
1137#define E1000_82542_SEC E1000_SEC
1138#define E1000_82542_CEXTERR E1000_CEXTERR
1139#define E1000_82542_RLEC E1000_RLEC
1140#define E1000_82542_XONRXC E1000_XONRXC
1141#define E1000_82542_XONTXC E1000_XONTXC
1142#define E1000_82542_XOFFRXC E1000_XOFFRXC
1143#define E1000_82542_XOFFTXC E1000_XOFFTXC
1144#define E1000_82542_FCRUC E1000_FCRUC
1145#define E1000_82542_PRC64 E1000_PRC64
1146#define E1000_82542_PRC127 E1000_PRC127
1147#define E1000_82542_PRC255 E1000_PRC255
1148#define E1000_82542_PRC511 E1000_PRC511
1149#define E1000_82542_PRC1023 E1000_PRC1023
1150#define E1000_82542_PRC1522 E1000_PRC1522
1151#define E1000_82542_GPRC E1000_GPRC
1152#define E1000_82542_BPRC E1000_BPRC
1153#define E1000_82542_MPRC E1000_MPRC
1154#define E1000_82542_GPTC E1000_GPTC
1155#define E1000_82542_GORCL E1000_GORCL
1156#define E1000_82542_GORCH E1000_GORCH
1157#define E1000_82542_GOTCL E1000_GOTCL
1158#define E1000_82542_GOTCH E1000_GOTCH
1159#define E1000_82542_RNBC E1000_RNBC
1160#define E1000_82542_RUC E1000_RUC
1161#define E1000_82542_RFC E1000_RFC
1162#define E1000_82542_ROC E1000_ROC
1163#define E1000_82542_RJC E1000_RJC
1164#define E1000_82542_MGTPRC E1000_MGTPRC
1165#define E1000_82542_MGTPDC E1000_MGTPDC
1166#define E1000_82542_MGTPTC E1000_MGTPTC
1167#define E1000_82542_TORL E1000_TORL
1168#define E1000_82542_TORH E1000_TORH
1169#define E1000_82542_TOTL E1000_TOTL
1170#define E1000_82542_TOTH E1000_TOTH
1171#define E1000_82542_TPR E1000_TPR
1172#define E1000_82542_TPT E1000_TPT
1173#define E1000_82542_PTC64 E1000_PTC64
1174#define E1000_82542_PTC127 E1000_PTC127
1175#define E1000_82542_PTC255 E1000_PTC255
1176#define E1000_82542_PTC511 E1000_PTC511
1177#define E1000_82542_PTC1023 E1000_PTC1023
1178#define E1000_82542_PTC1522 E1000_PTC1522
1179#define E1000_82542_MPTC E1000_MPTC
1180#define E1000_82542_BPTC E1000_BPTC
1181#define E1000_82542_TSCTC E1000_TSCTC
1182#define E1000_82542_TSCTFC E1000_TSCTFC
1183#define E1000_82542_RXCSUM E1000_RXCSUM
1184#define E1000_82542_WUC E1000_WUC
1185#define E1000_82542_WUFC E1000_WUFC
1186#define E1000_82542_WUS E1000_WUS
1187#define E1000_82542_MANC E1000_MANC
1188#define E1000_82542_IPAV E1000_IPAV
1189#define E1000_82542_IP4AT E1000_IP4AT
1190#define E1000_82542_IP6AT E1000_IP6AT
1191#define E1000_82542_WUPL E1000_WUPL
1192#define E1000_82542_WUPM E1000_WUPM
1193#define E1000_82542_FFLT E1000_FFLT
1194#define E1000_82542_TDFH 0x08010
1195#define E1000_82542_TDFT 0x08018
1196#define E1000_82542_FFMT E1000_FFMT
1197#define E1000_82542_FFVT E1000_FFVT
1198#define E1000_82542_HOST_IF E1000_HOST_IF
2d7edb92
MC		 1199#define E1000_82542_IAM E1000_IAM
1200#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1201#define E1000_82542_PSRCTL E1000_PSRCTL
1202#define E1000_82542_RAID E1000_RAID
1203#define E1000_82542_TARC0 E1000_TARC0
1204#define E1000_82542_TDBAL1 E1000_TDBAL1
1205#define E1000_82542_TDBAH1 E1000_TDBAH1
1206#define E1000_82542_TDLEN1 E1000_TDLEN1
1207#define E1000_82542_TDH1 E1000_TDH1
1208#define E1000_82542_TDT1 E1000_TDT1
1209#define E1000_82542_TXDCTL1 E1000_TXDCTL1
1210#define E1000_82542_TARC1 E1000_TARC1
1211#define E1000_82542_RFCTL E1000_RFCTL
1212#define E1000_82542_GCR E1000_GCR
1213#define E1000_82542_GSCL_1 E1000_GSCL_1
1214#define E1000_82542_GSCL_2 E1000_GSCL_2
1215#define E1000_82542_GSCL_3 E1000_GSCL_3
1216#define E1000_82542_GSCL_4 E1000_GSCL_4
1217#define E1000_82542_FACTPS E1000_FACTPS
1218#define E1000_82542_SWSM E1000_SWSM
1219#define E1000_82542_FWSM E1000_FWSM
1220#define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1221#define E1000_82542_IAC E1000_IAC
1222#define E1000_82542_ICRXPTC E1000_ICRXPTC
1223#define E1000_82542_ICRXATC E1000_ICRXATC
1224#define E1000_82542_ICTXPTC E1000_ICTXPTC
1225#define E1000_82542_ICTXATC E1000_ICTXATC
1226#define E1000_82542_ICTXQEC E1000_ICTXQEC
1227#define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1228#define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1229#define E1000_82542_ICRXOC E1000_ICRXOC
1230#define E1000_82542_HICR E1000_HICR
1da177e4 1231
868d5309
MC		 1232#define E1000_82542_CPUVEC E1000_CPUVEC
1233#define E1000_82542_MRQC E1000_MRQC
1234#define E1000_82542_RETA E1000_RETA
1235#define E1000_82542_RSSRK E1000_RSSRK
1236#define E1000_82542_RSSIM E1000_RSSIM
1237#define E1000_82542_RSSIR E1000_RSSIR
6418ecc6
JK		 1238#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
1239#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
868d5309 1240
1da177e4
LT		 1241/* Statistics counters collected by the MAC */
1242struct e1000_hw_stats {
1243 uint64_t crcerrs;
1244 uint64_t algnerrc;
1245 uint64_t symerrs;
1246 uint64_t rxerrc;
1247 uint64_t mpc;
1248 uint64_t scc;
1249 uint64_t ecol;
1250 uint64_t mcc;
1251 uint64_t latecol;
1252 uint64_t colc;
1253 uint64_t dc;
1254 uint64_t tncrs;
1255 uint64_t sec;
1256 uint64_t cexterr;
1257 uint64_t rlec;
1258 uint64_t xonrxc;
1259 uint64_t xontxc;
1260 uint64_t xoffrxc;
1261 uint64_t xofftxc;
1262 uint64_t fcruc;
1263 uint64_t prc64;
1264 uint64_t prc127;
1265 uint64_t prc255;
1266 uint64_t prc511;
1267 uint64_t prc1023;
1268 uint64_t prc1522;
1269 uint64_t gprc;
1270 uint64_t bprc;
1271 uint64_t mprc;
1272 uint64_t gptc;
1273 uint64_t gorcl;
1274 uint64_t gorch;
1275 uint64_t gotcl;
1276 uint64_t gotch;
1277 uint64_t rnbc;
1278 uint64_t ruc;
1279 uint64_t rfc;
1280 uint64_t roc;
1281 uint64_t rjc;
1282 uint64_t mgprc;
1283 uint64_t mgpdc;
1284 uint64_t mgptc;
1285 uint64_t torl;
1286 uint64_t torh;
1287 uint64_t totl;
1288 uint64_t toth;
1289 uint64_t tpr;
1290 uint64_t tpt;
1291 uint64_t ptc64;
1292 uint64_t ptc127;
1293 uint64_t ptc255;
1294 uint64_t ptc511;
1295 uint64_t ptc1023;
1296 uint64_t ptc1522;
1297 uint64_t mptc;
1298 uint64_t bptc;
1299 uint64_t tsctc;
1300 uint64_t tsctfc;
2d7edb92
MC		 1301 uint64_t iac;
1302 uint64_t icrxptc;
1303 uint64_t icrxatc;
1304 uint64_t ictxptc;
1305 uint64_t ictxatc;
1306 uint64_t ictxqec;
1307 uint64_t ictxqmtc;
1308 uint64_t icrxdmtc;
1309 uint64_t icrxoc;
1da177e4
LT		 1310};
1311
1312/* Structure containing variables used by the shared code (e1000_hw.c) */
1313struct e1000_hw {
1bea9add 1314 uint8_t __iomem *hw_addr;
2d7edb92 1315 uint8_t *flash_address;
1da177e4
LT		 1316 e1000_mac_type mac_type;
1317 e1000_phy_type phy_type;
1318 uint32_t phy_init_script;
1319 e1000_media_type media_type;
1320 void *back;
1321 e1000_fc_type fc;
1322 e1000_bus_speed bus_speed;
1323 e1000_bus_width bus_width;
1324 e1000_bus_type bus_type;
1325 struct e1000_eeprom_info eeprom;
1326 e1000_ms_type master_slave;
1327 e1000_ms_type original_master_slave;
1328 e1000_ffe_config ffe_config_state;
1329 uint32_t asf_firmware_present;
2d7edb92 1330 uint32_t eeprom_semaphore_present;
6418ecc6 1331 uint32_t swfw_sync_present;
1da177e4
LT		 1332 unsigned long io_base;
1333 uint32_t phy_id;
1334 uint32_t phy_revision;
1335 uint32_t phy_addr;
1336 uint32_t original_fc;
1337 uint32_t txcw;
1338 uint32_t autoneg_failed;
1339 uint32_t max_frame_size;
1340 uint32_t min_frame_size;
1341 uint32_t mc_filter_type;
1342 uint32_t num_mc_addrs;
1343 uint32_t collision_delta;
1344 uint32_t tx_packet_delta;
1345 uint32_t ledctl_default;
1346 uint32_t ledctl_mode1;
1347 uint32_t ledctl_mode2;
2d7edb92
MC		 1348 boolean_t tx_pkt_filtering;
1349 struct e1000_host_mng_dhcp_cookie mng_cookie;
1da177e4
LT		 1350 uint16_t phy_spd_default;
1351 uint16_t autoneg_advertised;
1352 uint16_t pci_cmd_word;
1353 uint16_t fc_high_water;
1354 uint16_t fc_low_water;
1355 uint16_t fc_pause_time;
1356 uint16_t current_ifs_val;
1357 uint16_t ifs_min_val;
1358 uint16_t ifs_max_val;
1359 uint16_t ifs_step_size;
1360 uint16_t ifs_ratio;
1361 uint16_t device_id;
1362 uint16_t vendor_id;
1363 uint16_t subsystem_id;
1364 uint16_t subsystem_vendor_id;
1365 uint8_t revision_id;
1366 uint8_t autoneg;
1367 uint8_t mdix;
1368 uint8_t forced_speed_duplex;
1369 uint8_t wait_autoneg_complete;
1370 uint8_t dma_fairness;
1371 uint8_t mac_addr[NODE_ADDRESS_SIZE];
1372 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
1373 boolean_t disable_polarity_correction;
1374 boolean_t speed_downgraded;
1375 e1000_smart_speed smart_speed;
1376 e1000_dsp_config dsp_config_state;
1377 boolean_t get_link_status;
1378 boolean_t serdes_link_down;
1379 boolean_t tbi_compatibility_en;
1380 boolean_t tbi_compatibility_on;
868d5309 1381 boolean_t laa_is_present;
1da177e4
LT		 1382 boolean_t phy_reset_disable;
1383 boolean_t fc_send_xon;
1384 boolean_t fc_strict_ieee;
1385 boolean_t report_tx_early;
1386 boolean_t adaptive_ifs;
1387 boolean_t ifs_params_forced;
1388 boolean_t in_ifs_mode;
2d7edb92 1389 boolean_t mng_reg_access_disabled;
8df06e50 1390 boolean_t leave_av_bit_off;
1da177e4
LT		 1391};
1392
1393
1394#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1395#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
2d7edb92
MC		 1396#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1397#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1398#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1399#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1400#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1401#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1da177e4
LT		 1402/* Register Bit Masks */
1403/* Device Control */
1404#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1405#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1406#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
2d7edb92 1407#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1da177e4
LT		 1408#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1409#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1410#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1411#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1412#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1413#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1414#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1415#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1416#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1417#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1418#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1419#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1420#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
868d5309 1421#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
2d7edb92 1422#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
6418ecc6
JK		 1423#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
1424#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
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LT		 1425#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1426#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1427#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1428#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1429#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1430#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1431#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1432#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1433#define E1000_CTRL_RST 0x04000000 /* Global reset */
1434#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1435#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1436#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1437#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1438#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1439
1440/* Device Status */
1441#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1442#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1443#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
2d7edb92 1444#define E1000_STATUS_FUNC_SHIFT 2
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LT		 1445#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1446#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1447#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1448#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1449#define E1000_STATUS_SPEED_MASK 0x000000C0
1450#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1451#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1452#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1453#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
2d7edb92
MC		 1454#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1455#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
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LT		 1456#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1457#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1458#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1459#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1460#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
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JK		 1461#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
1462#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
1463#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
1464#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
1465#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
1466#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
1467#define E1000_STATUS_FUSE_8 0x04000000
1468#define E1000_STATUS_FUSE_9 0x08000000
1469#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
1470#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
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LT		 1471
1472/* Constants used to intrepret the masked PCI-X bus speed. */
1473#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1474#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1475#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1476
1477/* EEPROM/Flash Control */
1478#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1479#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1480#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1481#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1482#define E1000_EECD_FWE_MASK 0x00000030
1483#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1484#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1485#define E1000_EECD_FWE_SHIFT 4
1486#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1487#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1488#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1489#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1490#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1491 * (0-small, 1-large) */
1492#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1493#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1494#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1495#endif
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MC		 1496#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1497#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1498#define E1000_EECD_SIZE_EX_SHIFT 11
1499#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1500#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1501#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1502#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1503#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1504#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1505#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
fd803241 1506#define E1000_EECD_SECVAL_SHIFT 22
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MC		 1507#define E1000_STM_OPCODE 0xDB00
1508#define E1000_HICR_FW_RESET 0xC0
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LT		 1509
1510/* EEPROM Read */
1511#define E1000_EERD_START 0x00000001 /* Start Read */
1512#define E1000_EERD_DONE 0x00000010 /* Read Done */
1513#define E1000_EERD_ADDR_SHIFT 8
1514#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1515#define E1000_EERD_DATA_SHIFT 16
1516#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1517
1518/* SPI EEPROM Status Register */
1519#define EEPROM_STATUS_RDY_SPI 0x01
1520#define EEPROM_STATUS_WEN_SPI 0x02
1521#define EEPROM_STATUS_BP0_SPI 0x04
1522#define EEPROM_STATUS_BP1_SPI 0x08
1523#define EEPROM_STATUS_WPEN_SPI 0x80
1524
1525/* Extended Device Control */
1526#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1527#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1528#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1529#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1530#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1531#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1532#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1533#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1534#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1535#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1536#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1537#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1538#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1539#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1540#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1541#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1542#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1543#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
f56799ea 1544#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
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LT		 1545#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1546#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1547#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
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JK		 1548#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
1549#define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000
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LT		 1550#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1551#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1552#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1553#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1554#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
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MC		 1555#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
1556#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
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MC		 1557#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1558#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
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JK		 1559#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
1560#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
1561#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
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LT		 1562
1563/* MDI Control */
1564#define E1000_MDIC_DATA_MASK 0x0000FFFF
1565#define E1000_MDIC_REG_MASK 0x001F0000
1566#define E1000_MDIC_REG_SHIFT 16
1567#define E1000_MDIC_PHY_MASK 0x03E00000
1568#define E1000_MDIC_PHY_SHIFT 21
1569#define E1000_MDIC_OP_WRITE 0x04000000
1570#define E1000_MDIC_OP_READ 0x08000000
1571#define E1000_MDIC_READY 0x10000000
1572#define E1000_MDIC_INT_EN 0x20000000
1573#define E1000_MDIC_ERROR 0x40000000
1574
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JK		 1575#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
1576#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
1577#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
1578#define E1000_KUMCTRLSTA_REN 0x00200000
1579
1580#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
1581#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
1582#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
1583#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
1584#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
1585#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
1586#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
1587#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
1588#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
1589
1590/* FIFO Control */
1591#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
1592#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1593
1594/* In-Band Control */
1595#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1596
1597/* Half-Duplex Control */
1598#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1599#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1600
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LT		 1601/* LED Control */
1602#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1603#define E1000_LEDCTL_LED0_MODE_SHIFT 0
2d7edb92 1604#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
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LT		 1605#define E1000_LEDCTL_LED0_IVRT 0x00000040
1606#define E1000_LEDCTL_LED0_BLINK 0x00000080
1607#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1608#define E1000_LEDCTL_LED1_MODE_SHIFT 8
2d7edb92 1609#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
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LT		 1610#define E1000_LEDCTL_LED1_IVRT 0x00004000
1611#define E1000_LEDCTL_LED1_BLINK 0x00008000
1612#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1613#define E1000_LEDCTL_LED2_MODE_SHIFT 16
2d7edb92 1614#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
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LT		 1615#define E1000_LEDCTL_LED2_IVRT 0x00400000
1616#define E1000_LEDCTL_LED2_BLINK 0x00800000
1617#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1618#define E1000_LEDCTL_LED3_MODE_SHIFT 24
868d5309 1619#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
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LT		 1620#define E1000_LEDCTL_LED3_IVRT 0x40000000
1621#define E1000_LEDCTL_LED3_BLINK 0x80000000
1622
1623#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1624#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1625#define E1000_LEDCTL_MODE_LINK_UP 0x2
1626#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1627#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1628#define E1000_LEDCTL_MODE_LINK_10 0x5
1629#define E1000_LEDCTL_MODE_LINK_100 0x6
1630#define E1000_LEDCTL_MODE_LINK_1000 0x7
1631#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1632#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1633#define E1000_LEDCTL_MODE_COLLISION 0xA
1634#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1635#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1636#define E1000_LEDCTL_MODE_PAUSED 0xD
1637#define E1000_LEDCTL_MODE_LED_ON 0xE
1638#define E1000_LEDCTL_MODE_LED_OFF 0xF
1639
1640/* Receive Address */
1641#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1642
1643/* Interrupt Cause Read */
1644#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1645#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1646#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1647#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1648#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1649#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1650#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1651#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1652#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1653#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1654#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1655#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1656#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1657#define E1000_ICR_TXD_LOW 0x00008000
1658#define E1000_ICR_SRPD 0x00010000
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MC		 1659#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1660#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1661#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1662#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
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JK		 1663#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1664#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
1665#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
1666#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
1667#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1668#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1669#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
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LT		 1670
1671/* Interrupt Cause Set */
1672#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1673#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1674#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1675#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1676#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1677#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1678#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1679#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1680#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1681#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1682#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1683#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1684#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1685#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1686#define E1000_ICS_SRPD E1000_ICR_SRPD
2d7edb92
MC		 1687#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1688#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1689#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
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JK		 1690#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1691#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1692#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1693#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1694#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1695#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
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LT		 1696
1697/* Interrupt Mask Set */
1698#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1699#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1700#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1701#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1702#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1703#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1704#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1705#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1706#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1707#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1708#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1709#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1710#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1711#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1712#define E1000_IMS_SRPD E1000_ICR_SRPD
2d7edb92
MC		 1713#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1714#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1715#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
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JK		 1716#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1717#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1718#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1719#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1720#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1721#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1da177e4
LT		 1722
1723/* Interrupt Mask Clear */
1724#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1725#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1726#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1727#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1728#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1729#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1730#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1731#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1732#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1733#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1734#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1735#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1736#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1737#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1738#define E1000_IMC_SRPD E1000_ICR_SRPD
2d7edb92
MC		 1739#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1740#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1741#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
6418ecc6
JK		 1742#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1743#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1744#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1745#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1746#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1747#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1da177e4
LT		 1748
1749/* Receive Control */
1750#define E1000_RCTL_RST 0x00000001 /* Software reset */
1751#define E1000_RCTL_EN 0x00000002 /* enable */
1752#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1753#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1754#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1755#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1756#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1757#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1758#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1759#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
2d7edb92
MC		 1760#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1761#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1da177e4
LT		 1762#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1763#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1764#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1765#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1766#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1767#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1768#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1769#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1770#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1771#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1772/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1773#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1774#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1775#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1776#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1777/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1778#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1779#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1780#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1781#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1782#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1783#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1784#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1785#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1786#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1787#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
2d7edb92
MC		 1788#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1789#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1790
1791/* Use byte values for the following shift parameters
1792 * Usage:
1793 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1794 * E1000_PSRCTL_BSIZE0_MASK) |
1795 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1796 * E1000_PSRCTL_BSIZE1_MASK) |
1797 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1798 * E1000_PSRCTL_BSIZE2_MASK) |
1799 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1800 * E1000_PSRCTL_BSIZE3_MASK))
1801 * where value0 = [128..16256], default=256
1802 * value1 = [1024..64512], default=4096
1803 * value2 = [0..64512], default=4096
1804 * value3 = [0..64512], default=0
1805 */
76c224bc 1806
2d7edb92
MC		 1807#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1808#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1809#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1810#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1811
1812#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1813#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1814#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1815#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1da177e4 1816
6418ecc6
JK		 1817/* SW_W_SYNC definitions */
1818#define E1000_SWFW_EEP_SM 0x0001
1819#define E1000_SWFW_PHY0_SM 0x0002
1820#define E1000_SWFW_PHY1_SM 0x0004
1821#define E1000_SWFW_MAC_CSR_SM 0x0008
1822
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LT		 1823/* Receive Descriptor */
1824#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1825#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1826#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1827#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1828#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1829
1830/* Flow Control */
1831#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1832#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1833#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1834#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1835
2d7edb92
MC		 1836/* Header split receive */
1837#define E1000_RFCTL_ISCSI_DIS 0x00000001
1838#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1839#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1840#define E1000_RFCTL_NFSW_DIS 0x00000040
1841#define E1000_RFCTL_NFSR_DIS 0x00000080
1842#define E1000_RFCTL_NFS_VER_MASK 0x00000300
1843#define E1000_RFCTL_NFS_VER_SHIFT 8
1844#define E1000_RFCTL_IPV6_DIS 0x00000400
1845#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1846#define E1000_RFCTL_ACK_DIS 0x00001000
1847#define E1000_RFCTL_ACKD_DIS 0x00002000
1848#define E1000_RFCTL_IPFRSP_DIS 0x00004000
1849#define E1000_RFCTL_EXTEN 0x00008000
1850#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1851#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1852
1da177e4
LT		 1853/* Receive Descriptor Control */
1854#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1855#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1856#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1857#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1858
1859/* Transmit Descriptor Control */
1860#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1861#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1862#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1863#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1864#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1865#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
2d7edb92
MC		 1866#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1867 still to be processed. */
1da177e4
LT		 1868/* Transmit Configuration Word */
1869#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1870#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1871#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1872#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1873#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1874#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1875#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1876#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1877#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1878#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1879
1880/* Receive Configuration Word */
1881#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1882#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1883#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1884#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1885#define E1000_RXCW_C 0x20000000 /* Receive config */
1886#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1887#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1888
1889/* Transmit Control */
1890#define E1000_TCTL_RST 0x00000001 /* software reset */
1891#define E1000_TCTL_EN 0x00000002 /* enable tx */
1892#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1893#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1894#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1895#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1896#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1897#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1898#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1899#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
2d7edb92 1900#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
6418ecc6
JK		 1901/* Extended Transmit Control */
1902#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
1903#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
1904
1905#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
1da177e4
LT		 1906
1907/* Receive Checksum Control */
1908#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1909#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1910#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1911#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
2d7edb92
MC		 1912#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1913#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1914
868d5309
MC		 1915/* Multiple Receive Queue Control */
1916#define E1000_MRQC_ENABLE_MASK 0x00000003
1917#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
1918#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
1919#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
1920#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1921#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
1922#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000
1923#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1924#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
1da177e4
LT		 1925
1926/* Definitions for power management and wakeup registers */
1927/* Wake Up Control */
1928#define E1000_WUC_APME 0x00000001 /* APM Enable */
1929#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1930#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1931#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1932#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1933
1934/* Wake Up Filter Control */
1935#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1936#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1937#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1938#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1939#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1940#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1941#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1942#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
2d7edb92 1943#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1da177e4
LT		 1944#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1945#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1946#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1947#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1948#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1949#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1950#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1951
1952/* Wake Up Status */
1953#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1954#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1955#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1956#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1957#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1958#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1959#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1960#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1961#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1962#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1963#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1964#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1965#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1966
1967/* Management Control */
1968#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1969#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1970#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1971#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1972#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1973#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1974#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1975#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1976#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1977#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1978 * Filtering */
2d7edb92 1979#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
1da177e4
LT		 1980#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1981#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1982#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
85b22eb6 1983#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
2d7edb92 1984#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
1da177e4
LT		 1985#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
1986 * filtering */
1987#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
1988 * memory */
2d7edb92
MC		 1989#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
1990 * filtering */
1991#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
1992#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
1da177e4
LT		 1993#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1994#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1995#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1996#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
1997#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
1998#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
1999
2000#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
2001#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
2002
2d7edb92
MC		 2003/* SW Semaphore Register */
2004#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2005#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2006#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2007#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2008
2009/* FW Semaphore Register */
2010#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2011#define E1000_FWSM_MODE_SHIFT 1
2012#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2013
2014/* FFLT Debug Register */
2015#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2016
2017typedef enum {
2018 e1000_mng_mode_none = 0,
2019 e1000_mng_mode_asf,
2020 e1000_mng_mode_pt,
2021 e1000_mng_mode_ipmi,
2022 e1000_mng_mode_host_interface_only
2023} e1000_mng_mode;
2024
2025/* Host Inteface Control Register */
2026#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2027#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
2028 * to put command in RAM */
2029#define E1000_HICR_SV 0x00000004 /* Status Validity */
2030#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
2031
2032/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2033#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
2034#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
2035#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
2036#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2037
2038struct e1000_host_command_header {
2039 uint8_t command_id;
2040 uint8_t command_length;
2041 uint8_t command_options; /* I/F bits for command, status for return */
2042 uint8_t checksum;
2043};
2044struct e1000_host_command_info {
2045 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2046 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2047};
2048
2049/* Host SMB register #0 */
2050#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
2051#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
2052#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
2053#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
2054
2055/* Host SMB register #1 */
2056#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
2057#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
2058#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
2059#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2060
2061/* FW Status Register */
2062#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
2063
1da177e4
LT		 2064/* Wake Up Packet Length */
2065#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
2066
2067#define E1000_MDALIGN 4096
2068
b7ee49db
JK		 2069/* PCI-Ex registers */
2070
2071/* PCI-Ex Control Register */
0f15a8fa
JK		 2072#define E1000_GCR_RXD_NO_SNOOP 0x00000001
2073#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
2074#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
2075#define E1000_GCR_TXD_NO_SNOOP 0x00000008
2076#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
2077#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
2078
2079#define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
2080 E1000_GCR_RXDSCW_NO_SNOOP | \
2081 E1000_GCR_RXDSCR_NO_SNOOP | \
2082 E1000_GCR_TXD_NO_SNOOP | \
2083 E1000_GCR_TXDSCW_NO_SNOOP | \
2084 E1000_GCR_TXDSCR_NO_SNOOP)
b7ee49db 2085
868d5309 2086#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2d7edb92
MC		 2087/* Function Active and Power State to MNG */
2088#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
2089#define E1000_FACTPS_LAN0_VALID 0x00000004
2090#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
2091#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
2092#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
2093#define E1000_FACTPS_LAN1_VALID 0x00000100
2094#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
2095#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
2096#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
2097#define E1000_FACTPS_IDE_ENABLE 0x00004000
2098#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
2099#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
2100#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
2101#define E1000_FACTPS_SP_ENABLE 0x00100000
2102#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
2103#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
2104#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
2105#define E1000_FACTPS_IPMI_ENABLE 0x04000000
2106#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
2107#define E1000_FACTPS_MNGCG 0x20000000
2108#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
2109#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
2110
1da177e4
LT		 2111/* EEPROM Commands - Microwire */
2112#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2113#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2114#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2115#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2116#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
2117
2118/* EEPROM Commands - SPI */
2119#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2d7edb92
MC		 2120#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2121#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2122#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2123#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2124#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2125#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2126#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2127#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2128#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2129#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1da177e4
LT		 2130
2131/* EEPROM Size definitions */
2d7edb92
MC		 2132#define EEPROM_WORD_SIZE_SHIFT 6
2133#define EEPROM_SIZE_SHIFT 10
1da177e4
LT		 2134#define EEPROM_SIZE_MASK 0x1C00
2135
2136/* EEPROM Word Offsets */
2137#define EEPROM_COMPAT 0x0003
2138#define EEPROM_ID_LED_SETTINGS 0x0004
868d5309 2139#define EEPROM_VERSION 0x0005
1da177e4
LT		 2140#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2141#define EEPROM_PHY_CLASS_WORD 0x0007
2142#define EEPROM_INIT_CONTROL1_REG 0x000A
2143#define EEPROM_INIT_CONTROL2_REG 0x000F
2144#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
85b22eb6 2145#define EEPROM_INIT_3GIO_3 0x001A
1da177e4
LT		 2146#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2147#define EEPROM_CFG 0x0012
2148#define EEPROM_FLASH_VERSION 0x0032
2149#define EEPROM_CHECKSUM_REG 0x003F
2150
868d5309 2151#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
6418ecc6 2152#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
868d5309 2153
1da177e4
LT		 2154/* Word definitions for ID LED Settings */
2155#define ID_LED_RESERVED_0000 0x0000
2156#define ID_LED_RESERVED_FFFF 0xFFFF
2157#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2158 (ID_LED_OFF1_OFF2 << 8) | \
2159 (ID_LED_DEF1_DEF2 << 4) | \
2160 (ID_LED_DEF1_DEF2))
2161#define ID_LED_DEF1_DEF2 0x1
2162#define ID_LED_DEF1_ON2 0x2
2163#define ID_LED_DEF1_OFF2 0x3
2164#define ID_LED_ON1_DEF2 0x4
2165#define ID_LED_ON1_ON2 0x5
2166#define ID_LED_ON1_OFF2 0x6
2167#define ID_LED_OFF1_DEF2 0x7
2168#define ID_LED_OFF1_ON2 0x8
2169#define ID_LED_OFF1_OFF2 0x9
2170
2171#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2172#define IGP_ACTIVITY_LED_ENABLE 0x0300
2173#define IGP_LED3_MODE 0x07000000
2174
2175
2176/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2177#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2178
2179/* Mask bit for PHY class in Word 7 of the EEPROM */
2180#define EEPROM_PHY_CLASS_A 0x8000
2181
2182/* Mask bits for fields in Word 0x0a of the EEPROM */
2183#define EEPROM_WORD0A_ILOS 0x0010
2184#define EEPROM_WORD0A_SWDPIO 0x01E0
2185#define EEPROM_WORD0A_LRST 0x0200
2186#define EEPROM_WORD0A_FD 0x0400
2187#define EEPROM_WORD0A_66MHZ 0x0800
2188
2189/* Mask bits for fields in Word 0x0f of the EEPROM */
2190#define EEPROM_WORD0F_PAUSE_MASK 0x3000
2191#define EEPROM_WORD0F_PAUSE 0x1000
2192#define EEPROM_WORD0F_ASM_DIR 0x2000
2193#define EEPROM_WORD0F_ANE 0x0800
2194#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2195
85b22eb6
JK		 2196/* Mask bits for fields in Word 0x1a of the EEPROM */
2197#define EEPROM_WORD1A_ASPM_MASK 0x000C
2198
1da177e4
LT		 2199/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2200#define EEPROM_SUM 0xBABA
2201
2202/* EEPROM Map defines (WORD OFFSETS)*/
2203#define EEPROM_NODE_ADDRESS_BYTE_0 0
2204#define EEPROM_PBA_BYTE_1 8
2205
2206#define EEPROM_RESERVED_WORD 0xFFFF
2207
2208/* EEPROM Map Sizes (Byte Counts) */
2209#define PBA_SIZE 4
2210
2211/* Collision related configuration parameters */
2212#define E1000_COLLISION_THRESHOLD 15
2213#define E1000_CT_SHIFT 4
0fadb059
JK		 2214/* Collision distance is a 0-based value that applies to
2215 * half-duplex-capable hardware only. */
2216#define E1000_COLLISION_DISTANCE 63
2217#define E1000_COLLISION_DISTANCE_82542 64
1da177e4
LT		 2218#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2219#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2220#define E1000_COLD_SHIFT 12
2221
2222/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2223#define REQ_TX_DESCRIPTOR_MULTIPLE 8
2224#define REQ_RX_DESCRIPTOR_MULTIPLE 8
2225
2226/* Default values for the transmit IPG register */
2227#define DEFAULT_82542_TIPG_IPGT 10
2228#define DEFAULT_82543_TIPG_IPGT_FIBER 9
2229#define DEFAULT_82543_TIPG_IPGT_COPPER 8
2230
2231#define E1000_TIPG_IPGT_MASK 0x000003FF
2232#define E1000_TIPG_IPGR1_MASK 0x000FFC00
2233#define E1000_TIPG_IPGR2_MASK 0x3FF00000
2234
2235#define DEFAULT_82542_TIPG_IPGR1 2
2236#define DEFAULT_82543_TIPG_IPGR1 8
2237#define E1000_TIPG_IPGR1_SHIFT 10
2238
2239#define DEFAULT_82542_TIPG_IPGR2 10
2240#define DEFAULT_82543_TIPG_IPGR2 6
6418ecc6 2241#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
1da177e4
LT		 2242#define E1000_TIPG_IPGR2_SHIFT 20
2243
6418ecc6
JK		 2244#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
2245#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
1da177e4
LT		 2246#define E1000_TXDMAC_DPP 0x00000001
2247
2248/* Adaptive IFS defines */
2249#define TX_THRESHOLD_START 8
2250#define TX_THRESHOLD_INCREMENT 10
2251#define TX_THRESHOLD_DECREMENT 1
2252#define TX_THRESHOLD_STOP 190
2253#define TX_THRESHOLD_DISABLE 0
2254#define TX_THRESHOLD_TIMER_MS 10000
2255#define MIN_NUM_XMITS 1000
2256#define IFS_MAX 80
2257#define IFS_STEP 10
2258#define IFS_MIN 40
2259#define IFS_RATIO 4
2260
2d7edb92
MC		 2261/* Extended Configuration Control and Size */
2262#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2263#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2264#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2265#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2266#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2267#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2268#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2269#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000
2270
2271#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2272#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2273#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2274
1da177e4 2275/* PBA constants */
2d7edb92 2276#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
1da177e4
LT		 2277#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2278#define E1000_PBA_22K 0x0016
2279#define E1000_PBA_24K 0x0018
2280#define E1000_PBA_30K 0x001E
868d5309
MC		 2281#define E1000_PBA_32K 0x0020
2282#define E1000_PBA_38K 0x0026
1da177e4
LT		 2283#define E1000_PBA_40K 0x0028
2284#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2285
2286/* Flow Control Constants */
2287#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2288#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2289#define FLOW_CONTROL_TYPE 0x8808
2290
2291/* The historical defaults for the flow control values are given below. */
2292#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2293#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2294#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2295
2296/* PCIX Config space */
2297#define PCIX_COMMAND_REGISTER 0xE6
2298#define PCIX_STATUS_REGISTER_LO 0xE8
2299#define PCIX_STATUS_REGISTER_HI 0xEA
2300
2301#define PCIX_COMMAND_MMRBC_MASK 0x000C
2302#define PCIX_COMMAND_MMRBC_SHIFT 0x2
2303#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2304#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2305#define PCIX_STATUS_HI_MMRBC_4K 0x3
2306#define PCIX_STATUS_HI_MMRBC_2K 0x2
2307
2308
2309/* Number of bits required to shift right the "pause" bits from the
2310 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2311 */
2312#define PAUSE_SHIFT 5
2313
2314/* Number of bits required to shift left the "SWDPIO" bits from the
2315 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2316 */
2317#define SWDPIO_SHIFT 17
2318
2319/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2320 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2321 */
2322#define SWDPIO__EXT_SHIFT 4
2323
2324/* Number of bits required to shift left the "ILOS" bit from the EEPROM
2325 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2326 */
2327#define ILOS_SHIFT 3
2328
2329
2330#define RECEIVE_BUFFER_ALIGN_SIZE (256)
2331
2332/* Number of milliseconds we wait for auto-negotiation to complete */
2333#define LINK_UP_TIMEOUT 500
2334
2d7edb92
MC		 2335/* Number of 100 microseconds we wait for PCI Express master disable */
2336#define MASTER_DISABLE_TIMEOUT 800
2337/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2338#define AUTO_READ_DONE_TIMEOUT 10
2339/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2340#define PHY_CFG_TIMEOUT 40
2341
1da177e4
LT		 2342#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2343
2344/* The carrier extension symbol, as received by the NIC. */
2345#define CARRIER_EXTENSION 0x0F
2346
2347/* TBI_ACCEPT macro definition:
2348 *
2349 * This macro requires:
2350 * adapter = a pointer to struct e1000_hw
2351 * status = the 8 bit status field of the RX descriptor with EOP set
2352 * error = the 8 bit error field of the RX descriptor with EOP set
2353 * length = the sum of all the length fields of the RX descriptors that
2354 * make up the current frame
2355 * last_byte = the last byte of the frame DMAed by the hardware
2356 * max_frame_length = the maximum frame length we want to accept.
2357 * min_frame_length = the minimum frame length we want to accept.
2358 *
2359 * This macro is a conditional that should be used in the interrupt
2360 * handler's Rx processing routine when RxErrors have been detected.
2361 *
2362 * Typical use:
2363 * ...
2364 * if (TBI_ACCEPT) {
2365 * accept_frame = TRUE;
2366 * e1000_tbi_adjust_stats(adapter, MacAddress);
2367 * frame_length--;
2368 * } else {
2369 * accept_frame = FALSE;
2370 * }
2371 * ...
2372 */
2373
2374#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2375 ((adapter)->tbi_compatibility_on && \
2376 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2377 ((last_byte) == CARRIER_EXTENSION) && \
2378 (((status) & E1000_RXD_STAT_VP) ? \
2379 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2380 ((length) <= ((adapter)->max_frame_size + 1))) : \
2381 (((length) > (adapter)->min_frame_size) && \
2382 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2383
2384
2385/* Structures, enums, and macros for the PHY */
2386
2387/* Bit definitions for the Management Data IO (MDIO) and Management Data
2388 * Clock (MDC) pins in the Device Control Register.
2389 */
2390#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2391#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2392#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2393#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2394#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2395#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2396#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2397#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2398
2399/* PHY 1000 MII Register/Bit Definitions */
2400/* PHY Registers defined by IEEE */
2401#define PHY_CTRL 0x00 /* Control Register */
2402#define PHY_STATUS 0x01 /* Status Regiser */
2403#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2404#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2405#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2406#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2407#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2408#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2409#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2410#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2411#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2412#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2413
2414#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2415#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2416
2417/* M88E1000 Specific Registers */
2418#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2419#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2420#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2421#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2422#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2423#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2424
2425#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2426#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2427#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2428#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2429#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2430
2431#define IGP01E1000_IEEE_REGS_PAGE 0x0000
2432#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2433#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2434
2435/* IGP01E1000 Specific Registers */
2436#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2437#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2438#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2439#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2440#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2441#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2d7edb92 2442#define IGP02E1000_PHY_POWER_MGMT 0x19
1da177e4
LT		 2443#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2444
2445/* IGP01E1000 AGC Registers - stores the cable length values*/
2446#define IGP01E1000_PHY_AGC_A 0x1172
2447#define IGP01E1000_PHY_AGC_B 0x1272
2448#define IGP01E1000_PHY_AGC_C 0x1472
2449#define IGP01E1000_PHY_AGC_D 0x1872
2450
2d7edb92
MC		 2451/* IGP02E1000 AGC Registers for cable length values */
2452#define IGP02E1000_PHY_AGC_A 0x11B1
2453#define IGP02E1000_PHY_AGC_B 0x12B1
2454#define IGP02E1000_PHY_AGC_C 0x14B1
2455#define IGP02E1000_PHY_AGC_D 0x18B1
2456
1da177e4
LT		 2457/* IGP01E1000 DSP Reset Register */
2458#define IGP01E1000_PHY_DSP_RESET 0x1F33
2459#define IGP01E1000_PHY_DSP_SET 0x1F71
2460#define IGP01E1000_PHY_DSP_FFE 0x1F35
2461
2462#define IGP01E1000_PHY_CHANNEL_NUM 4
2d7edb92
MC		 2463#define IGP02E1000_PHY_CHANNEL_NUM 4
2464
1da177e4
LT		 2465#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2466#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2467#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2468#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2469
2470#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2471#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2472
2473#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2474#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2475#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2476#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2477
2478#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2479/* IGP01E1000 PCS Initialization register - stores the polarity status when
2480 * speed = 1000 Mbps. */
2481#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2482#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2483
2484#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2485
6418ecc6
JK		 2486/* Bits...
2487 * 15-5: page
2488 * 4-0: register offset
2489 */
2490#define GG82563_PAGE_SHIFT 5
2491#define GG82563_REG(page, reg) \
2492 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2493#define GG82563_MIN_ALT_REG 30
2494
2495/* GG82563 Specific Registers */
2496#define GG82563_PHY_SPEC_CTRL \
2497 GG82563_REG(0, 16) /* PHY Specific Control */
2498#define GG82563_PHY_SPEC_STATUS \
2499 GG82563_REG(0, 17) /* PHY Specific Status */
2500#define GG82563_PHY_INT_ENABLE \
2501 GG82563_REG(0, 18) /* Interrupt Enable */
2502#define GG82563_PHY_SPEC_STATUS_2 \
2503 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2504#define GG82563_PHY_RX_ERR_CNTR \
2505 GG82563_REG(0, 21) /* Receive Error Counter */
2506#define GG82563_PHY_PAGE_SELECT \
2507 GG82563_REG(0, 22) /* Page Select */
2508#define GG82563_PHY_SPEC_CTRL_2 \
2509 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2510#define GG82563_PHY_PAGE_SELECT_ALT \
2511 GG82563_REG(0, 29) /* Alternate Page Select */
2512#define GG82563_PHY_TEST_CLK_CTRL \
2513 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2514
2515#define GG82563_PHY_MAC_SPEC_CTRL \
2516 GG82563_REG(2, 21) /* MAC Specific Control Register */
2517#define GG82563_PHY_MAC_SPEC_CTRL_2 \
2518 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2519
2520#define GG82563_PHY_DSP_DISTANCE \
2521 GG82563_REG(5, 26) /* DSP Distance */
2522
2523/* Page 193 - Port Control Registers */
2524#define GG82563_PHY_KMRN_MODE_CTRL \
2525 GG82563_REG(193, 16) /* Kumeran Mode Control */
2526#define GG82563_PHY_PORT_RESET \
2527 GG82563_REG(193, 17) /* Port Reset */
2528#define GG82563_PHY_REVISION_ID \
2529 GG82563_REG(193, 18) /* Revision ID */
2530#define GG82563_PHY_DEVICE_ID \
2531 GG82563_REG(193, 19) /* Device ID */
2532#define GG82563_PHY_PWR_MGMT_CTRL \
2533 GG82563_REG(193, 20) /* Power Management Control */
2534#define GG82563_PHY_RATE_ADAPT_CTRL \
2535 GG82563_REG(193, 25) /* Rate Adaptation Control */
2536
2537/* Page 194 - KMRN Registers */
2538#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
2539 GG82563_REG(194, 16) /* FIFO's Control/Status */
2540#define GG82563_PHY_KMRN_CTRL \
2541 GG82563_REG(194, 17) /* Control */
2542#define GG82563_PHY_INBAND_CTRL \
2543 GG82563_REG(194, 18) /* Inband Control */
2544#define GG82563_PHY_KMRN_DIAGNOSTIC \
2545 GG82563_REG(194, 19) /* Diagnostic */
2546#define GG82563_PHY_ACK_TIMEOUTS \
2547 GG82563_REG(194, 20) /* Acknowledge Timeouts */
2548#define GG82563_PHY_ADV_ABILITY \
2549 GG82563_REG(194, 21) /* Advertised Ability */
2550#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
2551 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2552#define GG82563_PHY_ADV_NEXT_PAGE \
2553 GG82563_REG(194, 24) /* Advertised Next Page */
2554#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
2555 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2556#define GG82563_PHY_KMRN_MISC \
2557 GG82563_REG(194, 26) /* Misc. */
1da177e4
LT		 2558
2559/* PHY Control Register */
2560#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2561#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2562#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2563#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2564#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2565#define MII_CR_POWER_DOWN 0x0800 /* Power down */
2566#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2567#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2568#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2569#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2570
2571/* PHY Status Register */
2572#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2573#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2574#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2575#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2576#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2577#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2578#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2579#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2580#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2581#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2582#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2583#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2584#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2585#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2586#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2587
2588/* Autoneg Advertisement Register */
2589#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2590#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2591#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2592#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2593#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2594#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2595#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2596#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2597#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2598#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2599
2600/* Link Partner Ability Register (Base Page) */
2601#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2602#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2603#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2604#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2605#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2606#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2607#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2608#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2609#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2610#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2611#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2612
2613/* Autoneg Expansion Register */
2614#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2615#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2616#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2617#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2618#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2619
2620/* Next Page TX Register */
2621#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2622#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2623 * of different NP
2624 */
2625#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2626 * 0 = cannot comply with msg
2627 */
2628#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2629#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2630 * 0 = sending last NP
2631 */
2632
2633/* Link Partner Next Page Register */
2634#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2635#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2636 * of different NP
2637 */
2638#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2639 * 0 = cannot comply with msg
2640 */
2641#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2642#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2643#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2644 * 0 = sending last NP
2645 */
2646
2647/* 1000BASE-T Control Register */
2648#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2649#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2650#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2651#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2652 /* 0=DTE device */
2653#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2654 /* 0=Configure PHY as Slave */
2655#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2656 /* 0=Automatic Master/Slave config */
2657#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2658#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2659#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2660#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2661#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2662
2663/* 1000BASE-T Status Register */
2664#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2665#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2666#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2667#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2668#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2669#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2670#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2671#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2672#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2673#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2674#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2675#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2676#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2677
2678/* Extended Status Register */
2679#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2680#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2681#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2682#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2683
2684#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2685#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2686
2687#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2688 /* (0=enable, 1=disable) */
2689
2690/* M88E1000 PHY Specific Control Register */
2691#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2692#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2693#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2694#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2695 * 0=CLK125 toggling
2696 */
2697#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2698 /* Manual MDI configuration */
2699#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2700#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2701 * 100BASE-TX/10BASE-T:
2702 * MDI Mode
2703 */
2704#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2705 * all speeds.
2706 */
2707#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2708 /* 1=Enable Extended 10BASE-T distance
2709 * (Lower 10BASE-T RX Threshold)
2710 * 0=Normal 10BASE-T RX Threshold */
2711#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2712 /* 1=5-Bit interface in 100BASE-TX
2713 * 0=MII interface in 100BASE-TX */
2714#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2715#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2716#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2717
2718#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2719#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2720#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2721
2722/* M88E1000 PHY Specific Status Register */
2723#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2724#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2725#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2726#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2727#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2728 * 3=110-140M;4=>140M */
2729#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2730#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2731#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2732#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2733#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2734#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2735#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2736#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2737
2738#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2739#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2740#define M88E1000_PSSR_MDIX_SHIFT 6
2741#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2742
2743/* M88E1000 Extended PHY Specific Control Register */
2744#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2745#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2746 * Will assert lost lock and bring
2747 * link down if idle not seen
2748 * within 1ms in 1000BASE-T
2749 */
2750/* Number of times we will attempt to autonegotiate before downshifting if we
2751 * are the master */
2752#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2753#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2754#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2755#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2756#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2757/* Number of times we will attempt to autonegotiate before downshifting if we
2758 * are the slave */
2759#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2760#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2761#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2762#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2763#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2764#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2765#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2766#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2767
ee04022a
AK		 2768/* M88EC018 Rev 2 specific DownShift settings */
2769#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2770#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2771#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2772#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2773#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2774#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2775#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2776#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2777#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2778
1da177e4
LT		 2779/* IGP01E1000 Specific Port Config Register - R/W */
2780#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2781#define IGP01E1000_PSCFR_PRE_EN 0x0020
2782#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2783#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2784#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2785#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2786
2787/* IGP01E1000 Specific Port Status Register - R/O */
2788#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2789#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2790#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2791#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2792#define IGP01E1000_PSSR_LINK_UP 0x0400
2793#define IGP01E1000_PSSR_MDIX 0x0800
2794#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2795#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2796#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2797#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2798#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2799#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2800
2801/* IGP01E1000 Specific Port Control Register - R/W */
2802#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2803#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2804#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2805#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2806#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2807#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2808
2809/* IGP01E1000 Specific Port Link Health Register */
2810#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2811#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2812#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2813#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2814#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2815#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2816#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2817#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2818#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2819#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2820#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2821#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2822#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2823#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2824
2825/* IGP01E1000 Channel Quality Register */
2826#define IGP01E1000_MSE_CHANNEL_D 0x000F
2827#define IGP01E1000_MSE_CHANNEL_C 0x00F0
2828#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2829#define IGP01E1000_MSE_CHANNEL_A 0xF000
2830
2d7edb92
MC		 2831#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2832#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2833#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2834
1da177e4
LT		 2835/* IGP01E1000 DSP reset macros */
2836#define DSP_RESET_ENABLE 0x0
2837#define DSP_RESET_DISABLE 0x2
2838#define E1000_MAX_DSP_RESETS 10
2839
2d7edb92 2840/* IGP01E1000 & IGP02E1000 AGC Registers */
1da177e4
LT		 2841
2842#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2d7edb92
MC		 2843#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2844
2845/* IGP02E1000 AGC Register Length 9-bit mask */
2846#define IGP02E1000_AGC_LENGTH_MASK 0x7F
1da177e4
LT		 2847
2848/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2849#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
868d5309 2850#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
1da177e4 2851
2d7edb92 2852/* The precision error of the cable length is +/- 10 meters */
1da177e4 2853#define IGP01E1000_AGC_RANGE 10
868d5309 2854#define IGP02E1000_AGC_RANGE 15
1da177e4
LT		 2855
2856/* IGP01E1000 PCS Initialization register */
2857/* bits 3:6 in the PCS registers stores the channels polarity */
2858#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2859
2860/* IGP01E1000 GMII FIFO Register */
2861#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2862 * on Link-Up */
2863#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2864
2865/* IGP01E1000 Analog Register */
2866#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2867#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2868#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2869#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2870
2871#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2872#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2873#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2874#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2875#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2876
2877#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2878#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2879#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2880#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2881
6418ecc6
JK		 2882/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
2883#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
2884#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */
2885#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
2886#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */
2887#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
2888#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */
2889#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */
2890#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */
2891#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */
2892#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
2893#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
2894#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */
2895#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
2896#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
2897#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
2898#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
2899#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
2900
2901/* PHY Specific Status Register (Page 0, Register 17) */
2902#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
2903#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
2904#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
2905#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
2906#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
2907#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
2908#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
2909#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
2910#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
2911#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
2912#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
2913#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
2914#define GG82563_PSSR_SPEED_MASK 0xC000
2915#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
2916#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
2917#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
2918
2919/* PHY Specific Status Register 2 (Page 0, Register 19) */
2920#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
2921#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
2922#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
2923#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
2924#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
2925#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
2926#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
2927#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
2928#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
2929#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
2930#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
2931#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
2932#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
2933
2934/* PHY Specific Control Register 2 (Page 0, Register 26) */
2935#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */
2936#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
2937#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */
2938#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */
2939#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */
2940#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */
2941#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */
2942#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
2943#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
2944#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
2945
2946/* MAC Specific Control Register (Page 2, Register 21) */
2947/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
2948#define GG82563_MSCR_TX_CLK_MASK 0x0007
2949#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
2950#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
2951#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
2952#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
2953
2954#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
2955
2956/* DSP Distance Register (Page 5, Register 26) */
2957#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
2958 1 = 50-80M;
2959 2 = 80-110M;
2960 3 = 110-140M;
2961 4 = >140M */
2962
2963/* Kumeran Mode Control Register (Page 193, Register 16) */
2964#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
2965#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
2966#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
2967#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
2968#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */
2969#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
2970
2971/* Power Management Control Register (Page 193, Register 20) */
2972#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */
2973#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
2974#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
2975#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */
2976#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */
2977#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */
2978#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */
2979#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
2980#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
2981#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
2982#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
2983#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
2984#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
2985
2986/* In-Band Control Register (Page 194, Register 18) */
2987#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
2988
1da177e4
LT		 2989
2990/* Bit definitions for valid PHY IDs. */
2991/* I = Integrated
2992 * E = External
2993 */
2994#define M88E1000_E_PHY_ID 0x01410C50
2995#define M88E1000_I_PHY_ID 0x01410C30
2996#define M88E1011_I_PHY_ID 0x01410C20
2997#define IGP01E1000_I_PHY_ID 0x02A80380
2998#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2999#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
3000#define M88E1011_I_REV_4 0x04
2d7edb92
MC		 3001#define M88E1111_I_PHY_ID 0x01410CC0
3002#define L1LXT971A_PHY_ID 0x001378E0
6418ecc6 3003#define GG82563_E_PHY_ID 0x01410CA0
1da177e4
LT		 3004
3005/* Miscellaneous PHY bit definitions. */
3006#define PHY_PREAMBLE 0xFFFFFFFF
3007#define PHY_SOF 0x01
3008#define PHY_OP_READ 0x02
3009#define PHY_OP_WRITE 0x01
3010#define PHY_TURNAROUND 0x02
3011#define PHY_PREAMBLE_SIZE 32
3012#define MII_CR_SPEED_1000 0x0040
3013#define MII_CR_SPEED_100 0x2000
3014#define MII_CR_SPEED_10 0x0000
3015#define E1000_PHY_ADDRESS 0x01
3016#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
3017#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
3018#define PHY_REVISION_MASK 0xFFFFFFF0
3019#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
3020#define REG4_SPEED_MASK 0x01E0
3021#define REG9_SPEED_MASK 0x0300
3022#define ADVERTISE_10_HALF 0x0001
3023#define ADVERTISE_10_FULL 0x0002
3024#define ADVERTISE_100_HALF 0x0004
3025#define ADVERTISE_100_FULL 0x0008
3026#define ADVERTISE_1000_HALF 0x0010
3027#define ADVERTISE_1000_FULL 0x0020
3028#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
3029#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
3030#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
3031
3032#endif /* _E1000_HW_H_ */
Linux 6.x block layer and io_uring tree(s)