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Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6
[linux-2.6-block.git] / drivers / net / e1000 / e1000_hw.h
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.h
30 * Structures, enums, and macros for the MAC
31 */
32
33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36#include "e1000_osdep.h"
37
38
39/* Forward declarations of structures used by the shared code */
40struct e1000_hw;
41struct e1000_hw_stats;
42
43/* Enumerated types specific to the e1000 hardware */
44/* Media Access Controlers */
45typedef enum {
46 e1000_undefined = 0,
47 e1000_82542_rev2_0,
48 e1000_82542_rev2_1,
49 e1000_82543,
50 e1000_82544,
51 e1000_82540,
52 e1000_82545,
53 e1000_82545_rev_3,
54 e1000_82546,
55 e1000_82546_rev_3,
56 e1000_82541,
57 e1000_82541_rev_2,
58 e1000_82547,
59 e1000_82547_rev_2,
868d5309
MC		 60 e1000_82571,
61 e1000_82572,
2d7edb92 62 e1000_82573,
6418ecc6 63 e1000_80003es2lan,
d37ea5d5 64 e1000_ich8lan,
1da177e4
LT		 65 e1000_num_macs
66} e1000_mac_type;
67
68typedef enum {
69 e1000_eeprom_uninitialized = 0,
70 e1000_eeprom_spi,
71 e1000_eeprom_microwire,
2d7edb92 72 e1000_eeprom_flash,
d37ea5d5 73 e1000_eeprom_ich8,
3893d547 74 e1000_eeprom_none, /* No NVM support */
1da177e4
LT		 75 e1000_num_eeprom_types
76} e1000_eeprom_type;
77
78/* Media Types */
79typedef enum {
80 e1000_media_type_copper = 0,
81 e1000_media_type_fiber = 1,
82 e1000_media_type_internal_serdes = 2,
83 e1000_num_media_types
84} e1000_media_type;
85
86typedef enum {
87 e1000_10_half = 0,
88 e1000_10_full = 1,
89 e1000_100_half = 2,
90 e1000_100_full = 3
91} e1000_speed_duplex_type;
92
93/* Flow Control Settings */
94typedef enum {
11241b10
JK		 95 E1000_FC_NONE = 0,
96 E1000_FC_RX_PAUSE = 1,
97 E1000_FC_TX_PAUSE = 2,
98 E1000_FC_FULL = 3,
99 E1000_FC_DEFAULT = 0xFF
1da177e4
LT		 100} e1000_fc_type;
101
d37ea5d5
AK		 102struct e1000_shadow_ram {
103 uint16_t eeprom_word;
104 boolean_t modified;
105};
106
1da177e4
LT		 107/* PCI bus types */
108typedef enum {
109 e1000_bus_type_unknown = 0,
110 e1000_bus_type_pci,
111 e1000_bus_type_pcix,
2d7edb92 112 e1000_bus_type_pci_express,
1da177e4
LT		 113 e1000_bus_type_reserved
114} e1000_bus_type;
115
116/* PCI bus speeds */
117typedef enum {
118 e1000_bus_speed_unknown = 0,
119 e1000_bus_speed_33,
120 e1000_bus_speed_66,
121 e1000_bus_speed_100,
122 e1000_bus_speed_120,
123 e1000_bus_speed_133,
2d7edb92 124 e1000_bus_speed_2500,
1da177e4
LT		 125 e1000_bus_speed_reserved
126} e1000_bus_speed;
127
128/* PCI bus widths */
129typedef enum {
130 e1000_bus_width_unknown = 0,
131 e1000_bus_width_32,
132 e1000_bus_width_64,
2d7edb92 133 e1000_bus_width_pciex_1,
fd803241 134 e1000_bus_width_pciex_2,
2d7edb92 135 e1000_bus_width_pciex_4,
1da177e4
LT		 136 e1000_bus_width_reserved
137} e1000_bus_width;
138
139/* PHY status info structure and supporting enums */
140typedef enum {
141 e1000_cable_length_50 = 0,
142 e1000_cable_length_50_80,
143 e1000_cable_length_80_110,
144 e1000_cable_length_110_140,
145 e1000_cable_length_140,
146 e1000_cable_length_undefined = 0xFF
147} e1000_cable_length;
148
6418ecc6
JK		 149typedef enum {
150 e1000_gg_cable_length_60 = 0,
151 e1000_gg_cable_length_60_115 = 1,
152 e1000_gg_cable_length_115_150 = 2,
153 e1000_gg_cable_length_150 = 4
154} e1000_gg_cable_length;
155
1da177e4
LT		 156typedef enum {
157 e1000_igp_cable_length_10 = 10,
158 e1000_igp_cable_length_20 = 20,
159 e1000_igp_cable_length_30 = 30,
160 e1000_igp_cable_length_40 = 40,
161 e1000_igp_cable_length_50 = 50,
162 e1000_igp_cable_length_60 = 60,
163 e1000_igp_cable_length_70 = 70,
164 e1000_igp_cable_length_80 = 80,
165 e1000_igp_cable_length_90 = 90,
166 e1000_igp_cable_length_100 = 100,
167 e1000_igp_cable_length_110 = 110,
fd803241 168 e1000_igp_cable_length_115 = 115,
1da177e4
LT		 169 e1000_igp_cable_length_120 = 120,
170 e1000_igp_cable_length_130 = 130,
171 e1000_igp_cable_length_140 = 140,
172 e1000_igp_cable_length_150 = 150,
173 e1000_igp_cable_length_160 = 160,
174 e1000_igp_cable_length_170 = 170,
175 e1000_igp_cable_length_180 = 180
176} e1000_igp_cable_length;
177
178typedef enum {
179 e1000_10bt_ext_dist_enable_normal = 0,
180 e1000_10bt_ext_dist_enable_lower,
181 e1000_10bt_ext_dist_enable_undefined = 0xFF
182} e1000_10bt_ext_dist_enable;
183
184typedef enum {
185 e1000_rev_polarity_normal = 0,
186 e1000_rev_polarity_reversed,
187 e1000_rev_polarity_undefined = 0xFF
188} e1000_rev_polarity;
189
190typedef enum {
191 e1000_downshift_normal = 0,
192 e1000_downshift_activated,
193 e1000_downshift_undefined = 0xFF
194} e1000_downshift;
195
196typedef enum {
197 e1000_smart_speed_default = 0,
198 e1000_smart_speed_on,
199 e1000_smart_speed_off
200} e1000_smart_speed;
201
202typedef enum {
203 e1000_polarity_reversal_enabled = 0,
204 e1000_polarity_reversal_disabled,
205 e1000_polarity_reversal_undefined = 0xFF
206} e1000_polarity_reversal;
207
208typedef enum {
209 e1000_auto_x_mode_manual_mdi = 0,
210 e1000_auto_x_mode_manual_mdix,
211 e1000_auto_x_mode_auto1,
212 e1000_auto_x_mode_auto2,
213 e1000_auto_x_mode_undefined = 0xFF
214} e1000_auto_x_mode;
215
216typedef enum {
217 e1000_1000t_rx_status_not_ok = 0,
218 e1000_1000t_rx_status_ok,
219 e1000_1000t_rx_status_undefined = 0xFF
220} e1000_1000t_rx_status;
221
222typedef enum {
223 e1000_phy_m88 = 0,
224 e1000_phy_igp,
2d7edb92 225 e1000_phy_igp_2,
6418ecc6 226 e1000_phy_gg82563,
d37ea5d5
AK		 227 e1000_phy_igp_3,
228 e1000_phy_ife,
1da177e4
LT		 229 e1000_phy_undefined = 0xFF
230} e1000_phy_type;
231
232typedef enum {
233 e1000_ms_hw_default = 0,
234 e1000_ms_force_master,
235 e1000_ms_force_slave,
236 e1000_ms_auto
237} e1000_ms_type;
238
239typedef enum {
240 e1000_ffe_config_enabled = 0,
241 e1000_ffe_config_active,
242 e1000_ffe_config_blocked
243} e1000_ffe_config;
244
245typedef enum {
246 e1000_dsp_config_disabled = 0,
247 e1000_dsp_config_enabled,
248 e1000_dsp_config_activated,
249 e1000_dsp_config_undefined = 0xFF
250} e1000_dsp_config;
251
252struct e1000_phy_info {
253 e1000_cable_length cable_length;
254 e1000_10bt_ext_dist_enable extended_10bt_distance;
255 e1000_rev_polarity cable_polarity;
256 e1000_downshift downshift;
257 e1000_polarity_reversal polarity_correction;
258 e1000_auto_x_mode mdix_mode;
259 e1000_1000t_rx_status local_rx;
260 e1000_1000t_rx_status remote_rx;
261};
262
263struct e1000_phy_stats {
264 uint32_t idle_errors;
265 uint32_t receive_errors;
266};
267
268struct e1000_eeprom_info {
269 e1000_eeprom_type type;
270 uint16_t word_size;
271 uint16_t opcode_bits;
272 uint16_t address_bits;
273 uint16_t delay_usec;
274 uint16_t page_size;
2d7edb92
MC		 275 boolean_t use_eerd;
276 boolean_t use_eewr;
1da177e4
LT		 277};
278
2d7edb92
MC		 279/* Flex ASF Information */
280#define E1000_HOST_IF_MAX_SIZE 2048
281
282typedef enum {
283 e1000_byte_align = 0,
284 e1000_word_align = 1,
285 e1000_dword_align = 2
286} e1000_align_type;
287
1da177e4
LT		 288
289
290/* Error Codes */
291#define E1000_SUCCESS 0
292#define E1000_ERR_EEPROM 1
293#define E1000_ERR_PHY 2
294#define E1000_ERR_CONFIG 3
295#define E1000_ERR_PARAM 4
296#define E1000_ERR_MAC_TYPE 5
297#define E1000_ERR_PHY_TYPE 6
2d7edb92
MC		 298#define E1000_ERR_RESET 9
299#define E1000_ERR_MASTER_REQUESTS_PENDING 10
300#define E1000_ERR_HOST_INTERFACE_COMMAND 11
301#define E1000_BLK_PHY_RESET 12
6418ecc6 302#define E1000_ERR_SWFW_SYNC 13
1da177e4 303
2a88c173
JK		 304#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
305 (((_value) & 0xff00) >> 8))
306
1da177e4
LT		 307/* Function prototypes */
308/* Initialization */
309int32_t e1000_reset_hw(struct e1000_hw *hw);
310int32_t e1000_init_hw(struct e1000_hw *hw);
311int32_t e1000_set_mac_type(struct e1000_hw *hw);
312void e1000_set_media_type(struct e1000_hw *hw);
313
314/* Link Configuration */
315int32_t e1000_setup_link(struct e1000_hw *hw);
316int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
317void e1000_config_collision_dist(struct e1000_hw *hw);
1da177e4 318int32_t e1000_check_for_link(struct e1000_hw *hw);
35574764 319int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
1da177e4
LT		 320int32_t e1000_force_mac_fc(struct e1000_hw *hw);
321
322/* PHY */
323int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
324int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
2d7edb92 325int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
1da177e4 326int32_t e1000_phy_reset(struct e1000_hw *hw);
1da177e4 327int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
1da177e4 328int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
35574764 329void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
1da177e4
LT		 330
331/* EEPROM Functions */
2d7edb92 332int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
2d7edb92
MC		 333
334/* MNG HOST IF functions */
335uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
336
337#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
338#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
339
340#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
8fc897b0
AK		 341#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
342#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
343#define E1000_MNG_IAMT_MODE 0x3
d37ea5d5 344#define E1000_MNG_ICH_IAMT_MODE 0x2
2d7edb92
MC		 345#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
346
347#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
348#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
349#define E1000_VFTA_ENTRY_SHIFT 0x5
350#define E1000_VFTA_ENTRY_MASK 0x7F
351#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
352
353struct e1000_host_mng_command_header {
354 uint8_t command_id;
355 uint8_t checksum;
356 uint16_t reserved1;
357 uint16_t reserved2;
358 uint16_t command_length;
359};
360
361struct e1000_host_mng_command_info {
362 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
363 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
364};
365#ifdef __BIG_ENDIAN
366struct e1000_host_mng_dhcp_cookie{
367 uint32_t signature;
368 uint16_t vlan_id;
369 uint8_t reserved0;
370 uint8_t status;
371 uint32_t reserved1;
372 uint8_t checksum;
373 uint8_t reserved3;
374 uint16_t reserved2;
375};
376#else
377struct e1000_host_mng_dhcp_cookie{
378 uint32_t signature;
379 uint8_t status;
380 uint8_t reserved0;
381 uint16_t vlan_id;
382 uint32_t reserved1;
383 uint16_t reserved2;
384 uint8_t reserved3;
385 uint8_t checksum;
386};
387#endif
388
76c224bc 389int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
8fc897b0 390 uint16_t length);
2d7edb92
MC		 391boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
392boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
2d7edb92 393
1da177e4
LT		 394int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
395int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
396int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
397int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
1da177e4
LT		 398int32_t e1000_read_mac_addr(struct e1000_hw * hw);
399
400/* Filters (multicast, vlan, receive) */
1da177e4
LT		 401uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
402void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
403void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
404void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
1da177e4
LT		 405
406/* LED functions */
407int32_t e1000_setup_led(struct e1000_hw *hw);
408int32_t e1000_cleanup_led(struct e1000_hw *hw);
409int32_t e1000_led_on(struct e1000_hw *hw);
410int32_t e1000_led_off(struct e1000_hw *hw);
f1b3a853 411int32_t e1000_blink_led_start(struct e1000_hw *hw);
1da177e4
LT		 412
413/* Adaptive IFS Functions */
414
415/* Everything else */
1da177e4
LT		 416void e1000_reset_adaptive(struct e1000_hw *hw);
417void e1000_update_adaptive(struct e1000_hw *hw);
418void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
419void e1000_get_bus_info(struct e1000_hw *hw);
420void e1000_pci_set_mwi(struct e1000_hw *hw);
421void e1000_pci_clear_mwi(struct e1000_hw *hw);
422void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
423void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
caeccb68 424int32_t e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value);
1da177e4 425/* Port I/O is only supported on 82544 and newer */
1da177e4 426void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
2d7edb92 427int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
2d7edb92 428int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
d37ea5d5
AK		 429
430
431#define E1000_READ_REG_IO(a, reg) \
432 e1000_read_reg_io((a), E1000_##reg)
433#define E1000_WRITE_REG_IO(a, reg, val) \
434 e1000_write_reg_io((a), E1000_##reg, val)
1da177e4
LT		 435
436/* PCI Device IDs */
437#define E1000_DEV_ID_82542 0x1000
438#define E1000_DEV_ID_82543GC_FIBER 0x1001
439#define E1000_DEV_ID_82543GC_COPPER 0x1004
440#define E1000_DEV_ID_82544EI_COPPER 0x1008
441#define E1000_DEV_ID_82544EI_FIBER 0x1009
442#define E1000_DEV_ID_82544GC_COPPER 0x100C
443#define E1000_DEV_ID_82544GC_LOM 0x100D
444#define E1000_DEV_ID_82540EM 0x100E
445#define E1000_DEV_ID_82540EM_LOM 0x1015
446#define E1000_DEV_ID_82540EP_LOM 0x1016
447#define E1000_DEV_ID_82540EP 0x1017
448#define E1000_DEV_ID_82540EP_LP 0x101E
449#define E1000_DEV_ID_82545EM_COPPER 0x100F
450#define E1000_DEV_ID_82545EM_FIBER 0x1011
451#define E1000_DEV_ID_82545GM_COPPER 0x1026
452#define E1000_DEV_ID_82545GM_FIBER 0x1027
453#define E1000_DEV_ID_82545GM_SERDES 0x1028
454#define E1000_DEV_ID_82546EB_COPPER 0x1010
455#define E1000_DEV_ID_82546EB_FIBER 0x1012
456#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
457#define E1000_DEV_ID_82541EI 0x1013
458#define E1000_DEV_ID_82541EI_MOBILE 0x1018
d37ea5d5 459#define E1000_DEV_ID_82541ER_LOM 0x1014
1da177e4
LT		 460#define E1000_DEV_ID_82541ER 0x1078
461#define E1000_DEV_ID_82547GI 0x1075
462#define E1000_DEV_ID_82541GI 0x1076
463#define E1000_DEV_ID_82541GI_MOBILE 0x1077
464#define E1000_DEV_ID_82541GI_LF 0x107C
465#define E1000_DEV_ID_82546GB_COPPER 0x1079
466#define E1000_DEV_ID_82546GB_FIBER 0x107A
467#define E1000_DEV_ID_82546GB_SERDES 0x107B
468#define E1000_DEV_ID_82546GB_PCIE 0x108A
b7ee49db 469#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
1da177e4 470#define E1000_DEV_ID_82547EI 0x1019
d37ea5d5 471#define E1000_DEV_ID_82547EI_MOBILE 0x101A
868d5309
MC		 472#define E1000_DEV_ID_82571EB_COPPER 0x105E
473#define E1000_DEV_ID_82571EB_FIBER 0x105F
474#define E1000_DEV_ID_82571EB_SERDES 0x1060
5881cde8 475#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
868d5309
MC		 476#define E1000_DEV_ID_82572EI_COPPER 0x107D
477#define E1000_DEV_ID_82572EI_FIBER 0x107E
478#define E1000_DEV_ID_82572EI_SERDES 0x107F
d37ea5d5 479#define E1000_DEV_ID_82572EI 0x10B9
2d7edb92
MC		 480#define E1000_DEV_ID_82573E 0x108B
481#define E1000_DEV_ID_82573E_IAMT 0x108C
868d5309 482#define E1000_DEV_ID_82573L 0x109A
b7ee49db 483#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
6418ecc6
JK		 484#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
485#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
d37ea5d5
AK		 486#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
487#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
488
489#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
490#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
491#define E1000_DEV_ID_ICH8_IGP_C 0x104B
492#define E1000_DEV_ID_ICH8_IFE 0x104C
493#define E1000_DEV_ID_ICH8_IGP_M 0x104D
2d7edb92 494
1da177e4
LT		 495
496#define NODE_ADDRESS_SIZE 6
497#define ETH_LENGTH_OF_ADDRESS 6
498
499/* MAC decode size is 128K - This is the size of BAR0 */
500#define MAC_DECODE_SIZE (128 * 1024)
501
502#define E1000_82542_2_0_REV_ID 2
503#define E1000_82542_2_1_REV_ID 3
504#define E1000_REVISION_0 0
505#define E1000_REVISION_1 1
506#define E1000_REVISION_2 2
2d7edb92 507#define E1000_REVISION_3 3
1da177e4
LT		 508
509#define SPEED_10 10
510#define SPEED_100 100
511#define SPEED_1000 1000
512#define HALF_DUPLEX 1
513#define FULL_DUPLEX 2
514
515/* The sizes (in bytes) of a ethernet packet */
516#define ENET_HEADER_SIZE 14
517#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
518#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
519#define ETHERNET_FCS_SIZE 4
520#define MAXIMUM_ETHERNET_PACKET_SIZE \
521 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
522#define MINIMUM_ETHERNET_PACKET_SIZE \
523 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
524#define CRC_LENGTH ETHERNET_FCS_SIZE
525#define MAX_JUMBO_FRAME_SIZE 0x3F00
526
527
528/* 802.1q VLAN Packet Sizes */
8fc897b0 529#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
1da177e4
LT		 530
531/* Ethertype field values */
532#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
533#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
534#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
535
536/* Packet Header defines */
537#define IP_PROTOCOL_TCP 6
538#define IP_PROTOCOL_UDP 0x11
539
540/* This defines the bits that are set in the Interrupt Mask
541 * Set/Read Register. Each bit is documented below:
542 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
543 * o RXSEQ = Receive Sequence Error
544 */
545#define POLL_IMS_ENABLE_MASK ( \
546 E1000_IMS_RXDMT0 | \
547 E1000_IMS_RXSEQ)
548
549/* This defines the bits that are set in the Interrupt Mask
550 * Set/Read Register. Each bit is documented below:
551 * o RXT0 = Receiver Timer Interrupt (ring 0)
552 * o TXDW = Transmit Descriptor Written Back
553 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
554 * o RXSEQ = Receive Sequence Error
555 * o LSC = Link Status Change
556 */
557#define IMS_ENABLE_MASK ( \
558 E1000_IMS_RXT0 | \
559 E1000_IMS_TXDW | \
560 E1000_IMS_RXDMT0 | \
561 E1000_IMS_RXSEQ | \
562 E1000_IMS_LSC)
563
d37ea5d5
AK		 564/* Additional interrupts need to be handled for e1000_ich8lan:
565 DSW = The FW changed the status of the DISSW bit in FWSM
566 PHYINT = The LAN connected device generates an interrupt
567 EPRST = Manageability reset event */
568#define IMS_ICH8LAN_ENABLE_MASK (\
569 E1000_IMS_DSW | \
570 E1000_IMS_PHYINT | \
571 E1000_IMS_EPRST)
2d7edb92 572
1da177e4
LT		 573/* Number of high/low register pairs in the RAR. The RAR (Receive Address
574 * Registers) holds the directed and multicast addresses that we monitor. We
575 * reserve one of these spots for our directed address, allowing us room for
576 * E1000_RAR_ENTRIES - 1 multicast addresses.
577 */
578#define E1000_RAR_ENTRIES 15
4f5f2317 579#define E1000_RAR_ENTRIES_ICH8LAN 6
1da177e4 580
4f5f2317
JK		 581#define MIN_NUMBER_OF_DESCRIPTORS 8
582#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
1da177e4
LT		 583
584/* Receive Descriptor */
585struct e1000_rx_desc {
586 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
587 uint16_t length; /* Length of data DMAed into data buffer */
588 uint16_t csum; /* Packet checksum */
589 uint8_t status; /* Descriptor status */
590 uint8_t errors; /* Descriptor Errors */
591 uint16_t special;
592};
593
2d7edb92
MC		 594/* Receive Descriptor - Extended */
595union e1000_rx_desc_extended {
596 struct {
597 uint64_t buffer_addr;
598 uint64_t reserved;
599 } read;
600 struct {
601 struct {
602 uint32_t mrq; /* Multiple Rx Queues */
603 union {
604 uint32_t rss; /* RSS Hash */
605 struct {
606 uint16_t ip_id; /* IP id */
607 uint16_t csum; /* Packet Checksum */
608 } csum_ip;
609 } hi_dword;
610 } lower;
611 struct {
612 uint32_t status_error; /* ext status/error */
613 uint16_t length;
614 uint16_t vlan; /* VLAN tag */
615 } upper;
616 } wb; /* writeback */
617};
618
619#define MAX_PS_BUFFERS 4
620/* Receive Descriptor - Packet Split */
621union e1000_rx_desc_packet_split {
622 struct {
623 /* one buffer for protocol header(s), three data buffers */
624 uint64_t buffer_addr[MAX_PS_BUFFERS];
625 } read;
626 struct {
627 struct {
628 uint32_t mrq; /* Multiple Rx Queues */
629 union {
630 uint32_t rss; /* RSS Hash */
631 struct {
632 uint16_t ip_id; /* IP id */
633 uint16_t csum; /* Packet Checksum */
634 } csum_ip;
635 } hi_dword;
636 } lower;
637 struct {
638 uint32_t status_error; /* ext status/error */
639 uint16_t length0; /* length of buffer 0 */
640 uint16_t vlan; /* VLAN tag */
641 } middle;
642 struct {
643 uint16_t header_status;
644 uint16_t length[3]; /* length of buffers 1-3 */
645 } upper;
646 uint64_t reserved;
647 } wb; /* writeback */
648};
649
1da177e4
LT		 650/* Receive Decriptor bit definitions */
651#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
652#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
653#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
654#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
2d7edb92 655#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
1da177e4
LT		 656#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
657#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
658#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
2d7edb92
MC		 659#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
660#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
661#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
1da177e4
LT		 662#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
663#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
664#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
665#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
666#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
667#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
668#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
669#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
670#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
2d7edb92 671#define E1000_RXD_SPC_PRI_SHIFT 13
1da177e4 672#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
2d7edb92
MC		 673#define E1000_RXD_SPC_CFI_SHIFT 12
674
675#define E1000_RXDEXT_STATERR_CE 0x01000000
676#define E1000_RXDEXT_STATERR_SE 0x02000000
677#define E1000_RXDEXT_STATERR_SEQ 0x04000000
678#define E1000_RXDEXT_STATERR_CXE 0x10000000
679#define E1000_RXDEXT_STATERR_TCPE 0x20000000
680#define E1000_RXDEXT_STATERR_IPE 0x40000000
681#define E1000_RXDEXT_STATERR_RXE 0x80000000
682
683#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
684#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1da177e4
LT		 685
686/* mask to determine if packets should be dropped due to frame errors */
687#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
688 E1000_RXD_ERR_CE | \
689 E1000_RXD_ERR_SE | \
690 E1000_RXD_ERR_SEQ | \
691 E1000_RXD_ERR_CXE | \
692 E1000_RXD_ERR_RXE)
693
2d7edb92
MC		 694
695/* Same mask, but for extended and packet split descriptors */
696#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
697 E1000_RXDEXT_STATERR_CE | \
698 E1000_RXDEXT_STATERR_SE | \
699 E1000_RXDEXT_STATERR_SEQ | \
700 E1000_RXDEXT_STATERR_CXE | \
701 E1000_RXDEXT_STATERR_RXE)
702
8fc897b0 703
1da177e4
LT		 704/* Transmit Descriptor */
705struct e1000_tx_desc {
706 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
707 union {
708 uint32_t data;
709 struct {
710 uint16_t length; /* Data buffer length */
711 uint8_t cso; /* Checksum offset */
712 uint8_t cmd; /* Descriptor control */
713 } flags;
714 } lower;
715 union {
716 uint32_t data;
717 struct {
718 uint8_t status; /* Descriptor status */
719 uint8_t css; /* Checksum start */
720 uint16_t special;
721 } fields;
722 } upper;
723};
724
725/* Transmit Descriptor bit definitions */
726#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
727#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
728#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
729#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
730#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
731#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
732#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
733#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
734#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
735#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
736#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
737#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
738#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
739#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
740#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
741#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
742#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
743#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
744#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
745#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
746
747/* Offload Context Descriptor */
748struct e1000_context_desc {
749 union {
750 uint32_t ip_config;
751 struct {
752 uint8_t ipcss; /* IP checksum start */
753 uint8_t ipcso; /* IP checksum offset */
754 uint16_t ipcse; /* IP checksum end */
755 } ip_fields;
756 } lower_setup;
757 union {
758 uint32_t tcp_config;
759 struct {
760 uint8_t tucss; /* TCP checksum start */
761 uint8_t tucso; /* TCP checksum offset */
762 uint16_t tucse; /* TCP checksum end */
763 } tcp_fields;
764 } upper_setup;
765 uint32_t cmd_and_length; /* */
766 union {
767 uint32_t data;
768 struct {
769 uint8_t status; /* Descriptor status */
770 uint8_t hdr_len; /* Header length */
771 uint16_t mss; /* Maximum segment size */
772 } fields;
773 } tcp_seg_setup;
774};
775
776/* Offload data descriptor */
777struct e1000_data_desc {
778 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
779 union {
780 uint32_t data;
781 struct {
782 uint16_t length; /* Data buffer length */
783 uint8_t typ_len_ext; /* */
784 uint8_t cmd; /* */
785 } flags;
786 } lower;
787 union {
788 uint32_t data;
789 struct {
790 uint8_t status; /* Descriptor status */
791 uint8_t popts; /* Packet Options */
792 uint16_t special; /* */
793 } fields;
794 } upper;
795};
796
797/* Filters */
798#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
799#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
800#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
801
d37ea5d5
AK		 802#define E1000_NUM_UNICAST_ICH8LAN 7
803#define E1000_MC_TBL_SIZE_ICH8LAN 32
804
1da177e4
LT		 805
806/* Receive Address Register */
807struct e1000_rar {
808 volatile uint32_t low; /* receive address low */
809 volatile uint32_t high; /* receive address high */
810};
811
812/* Number of entries in the Multicast Table Array (MTA). */
813#define E1000_NUM_MTA_REGISTERS 128
d37ea5d5 814#define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
1da177e4
LT		 815
816/* IPv4 Address Table Entry */
817struct e1000_ipv4_at_entry {
818 volatile uint32_t ipv4_addr; /* IP Address (RW) */
819 volatile uint32_t reserved;
820};
821
822/* Four wakeup IP addresses are supported */
823#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
824#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
d37ea5d5 825#define E1000_IP4AT_SIZE_ICH8LAN 3
1da177e4
LT		 826#define E1000_IP6AT_SIZE 1
827
828/* IPv6 Address Table Entry */
829struct e1000_ipv6_at_entry {
830 volatile uint8_t ipv6_addr[16];
831};
832
833/* Flexible Filter Length Table Entry */
834struct e1000_fflt_entry {
835 volatile uint32_t length; /* Flexible Filter Length (RW) */
836 volatile uint32_t reserved;
837};
838
839/* Flexible Filter Mask Table Entry */
840struct e1000_ffmt_entry {
841 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
842 volatile uint32_t reserved;
843};
844
845/* Flexible Filter Value Table Entry */
846struct e1000_ffvt_entry {
847 volatile uint32_t value; /* Flexible Filter Value (RW) */
848 volatile uint32_t reserved;
849};
850
851/* Four Flexible Filters are supported */
852#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
853
854/* Each Flexible Filter is at most 128 (0x80) bytes in length */
855#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
856
857#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
858#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
859#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
860
868d5309
MC		 861#define E1000_DISABLE_SERDES_LOOPBACK 0x0400
862
1da177e4
LT		 863/* Register Set. (82543, 82544)
864 *
865 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
866 * These registers are physically located on the NIC, but are mapped into the
867 * host memory address space.
868 *
869 * RW - register is both readable and writable
870 * RO - register is read only
871 * WO - register is write only
872 * R/clr - register is read only and is cleared when read
873 * A - register array
874 */
875#define E1000_CTRL 0x00000 /* Device Control - RW */
876#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
877#define E1000_STATUS 0x00008 /* Device Status - RO */
878#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
879#define E1000_EERD 0x00014 /* EEPROM Read - RW */
880#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
881#define E1000_FLA 0x0001C /* Flash Access - RW */
882#define E1000_MDIC 0x00020 /* MDI Control - RW */
868d5309 883#define E1000_SCTL 0x00024 /* SerDes Control - RW */
d37ea5d5 884#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
1da177e4
LT		 885#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
886#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
887#define E1000_FCT 0x00030 /* Flow Control Type - RW */
888#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
889#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
890#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
891#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
892#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
893#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
2d7edb92 894#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
1da177e4 895#define E1000_RCTL 0x00100 /* RX Control - RW */
868d5309
MC		 896#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
897#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
898#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
899#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
900#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
901#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
1da177e4
LT		 902#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
903#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
904#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
905#define E1000_TCTL 0x00400 /* TX Control - RW */
6418ecc6 906#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
1da177e4
LT		 907#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
908#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
909#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
910#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
2d7edb92
MC		 911#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
912#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
d37ea5d5
AK		 913#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
914#define FEXTNVM_SW_CONFIG 0x0001
1da177e4 915#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
2d7edb92
MC		 916#define E1000_PBS 0x01008 /* Packet Buffer Size */
917#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
918#define E1000_FLASH_UPDATES 1000
919#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
920#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
921#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
922#define E1000_FLSWCTL 0x01030 /* FLASH control register */
923#define E1000_FLSWDATA 0x01034 /* FLASH data register */
924#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
925#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
926#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
1da177e4
LT		 927#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
928#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
2d7edb92 929#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
1da177e4
LT		 930#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
931#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
932#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
933#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
934#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
935#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
868d5309
MC		 936#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
937#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
938#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
939#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
940#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
941#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
d37ea5d5
AK		 942#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
943#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
1da177e4
LT		 944#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
945#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
2d7edb92 946#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
1da177e4 947#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
d37ea5d5 948#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
1da177e4
LT		 949#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
950#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
951#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
952#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
953#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
954#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
955#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
956#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
957#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
958#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
959#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
960#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
961#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
962#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
96838a40
JB		 963#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
964#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
965#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
966#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
967#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
968#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
969#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
970#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
1da177e4
LT		 971#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
972#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
973#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
974#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
975#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
976#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
977#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
978#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
979#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
980#define E1000_COLC 0x04028 /* Collision Count - R/clr */
981#define E1000_DC 0x04030 /* Defer Count - R/clr */
982#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
983#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
984#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
985#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
986#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
987#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
988#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
989#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
990#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
991#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
992#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
993#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
994#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
995#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
996#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
997#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
998#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
999#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
1000#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
1001#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
1002#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
1003#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
1004#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
1005#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
1006#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
1007#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
1008#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
1009#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
1010#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
1011#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
1012#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
1013#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
1014#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
1015#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
1016#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
1017#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
1018#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
1019#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
1020#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
1021#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
1022#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
1023#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
1024#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
1025#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
1026#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
1027#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
1028#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
868d5309
MC		 1029#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
1030#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
1031#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
1032#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
1033#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
1034#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
1035#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
1036#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
1037#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
1da177e4 1038#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
2d7edb92 1039#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
1da177e4
LT		 1040#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
1041#define E1000_RA 0x05400 /* Receive Address - RW Array */
1042#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
1043#define E1000_WUC 0x05800 /* Wakeup Control - RW */
1044#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
1045#define E1000_WUS 0x05810 /* Wakeup Status - RO */
1046#define E1000_MANC 0x05820 /* Management Control - RW */
1047#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
1048#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
1049#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
1050#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
1051#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
1052#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
1053#define E1000_HOST_IF 0x08800 /* Host Interface */
1054#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
1055#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1056
6418ecc6
JK		 1057#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
1058#define E1000_MDPHYA 0x0003C /* PHY address - RW */
1059#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */
1060#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
1061
2d7edb92
MC		 1062#define E1000_GCR 0x05B00 /* PCI-Ex Control */
1063#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1064#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1065#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1066#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1067#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1068#define E1000_SWSM 0x05B50 /* SW Semaphore */
1069#define E1000_FWSM 0x05B54 /* FW Semaphore */
1070#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1071#define E1000_HICR 0x08F00 /* Host Inteface Control */
868d5309
MC		 1072
1073/* RSS registers */
1074#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1075#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1076#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1077#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1078#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1079#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1da177e4
LT		 1080/* Register Set (82542)
1081 *
1082 * Some of the 82542 registers are located at different offsets than they are
1083 * in more current versions of the 8254x. Despite the difference in location,
1084 * the registers function in the same manner.
1085 */
1086#define E1000_82542_CTRL E1000_CTRL
1087#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1088#define E1000_82542_STATUS E1000_STATUS
1089#define E1000_82542_EECD E1000_EECD
1090#define E1000_82542_EERD E1000_EERD
1091#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1092#define E1000_82542_FLA E1000_FLA
1093#define E1000_82542_MDIC E1000_MDIC
868d5309 1094#define E1000_82542_SCTL E1000_SCTL
d37ea5d5 1095#define E1000_82542_FEXTNVM E1000_FEXTNVM
1da177e4
LT		 1096#define E1000_82542_FCAL E1000_FCAL
1097#define E1000_82542_FCAH E1000_FCAH
1098#define E1000_82542_FCT E1000_FCT
1099#define E1000_82542_VET E1000_VET
1100#define E1000_82542_RA 0x00040
1101#define E1000_82542_ICR E1000_ICR
1102#define E1000_82542_ITR E1000_ITR
1103#define E1000_82542_ICS E1000_ICS
1104#define E1000_82542_IMS E1000_IMS
1105#define E1000_82542_IMC E1000_IMC
1106#define E1000_82542_RCTL E1000_RCTL
1107#define E1000_82542_RDTR 0x00108
1108#define E1000_82542_RDBAL 0x00110
1109#define E1000_82542_RDBAH 0x00114
1110#define E1000_82542_RDLEN 0x00118
1111#define E1000_82542_RDH 0x00120
1112#define E1000_82542_RDT 0x00128
868d5309
MC		 1113#define E1000_82542_RDTR0 E1000_82542_RDTR
1114#define E1000_82542_RDBAL0 E1000_82542_RDBAL
1115#define E1000_82542_RDBAH0 E1000_82542_RDBAH
1116#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1117#define E1000_82542_RDH0 E1000_82542_RDH
1118#define E1000_82542_RDT0 E1000_82542_RDT
d37ea5d5
AK		 1119#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1120 * RX Control - RW */
1121#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1122#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1123#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1124#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1125#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1126#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1127#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1128#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1129#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1130#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1131#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
868d5309
MC		 1132#define E1000_82542_RDTR1 0x00130
1133#define E1000_82542_RDBAL1 0x00138
1134#define E1000_82542_RDBAH1 0x0013C
1135#define E1000_82542_RDLEN1 0x00140
1136#define E1000_82542_RDH1 0x00148
1137#define E1000_82542_RDT1 0x00150
1da177e4
LT		 1138#define E1000_82542_FCRTH 0x00160
1139#define E1000_82542_FCRTL 0x00168
1140#define E1000_82542_FCTTV E1000_FCTTV
1141#define E1000_82542_TXCW E1000_TXCW
1142#define E1000_82542_RXCW E1000_RXCW
1143#define E1000_82542_MTA 0x00200
1144#define E1000_82542_TCTL E1000_TCTL
6418ecc6 1145#define E1000_82542_TCTL_EXT E1000_TCTL_EXT
1da177e4
LT		 1146#define E1000_82542_TIPG E1000_TIPG
1147#define E1000_82542_TDBAL 0x00420
1148#define E1000_82542_TDBAH 0x00424
1149#define E1000_82542_TDLEN 0x00428
1150#define E1000_82542_TDH 0x00430
1151#define E1000_82542_TDT 0x00438
1152#define E1000_82542_TIDV 0x00440
1153#define E1000_82542_TBT E1000_TBT
1154#define E1000_82542_AIT E1000_AIT
1155#define E1000_82542_VFTA 0x00600
1156#define E1000_82542_LEDCTL E1000_LEDCTL
1157#define E1000_82542_PBA E1000_PBA
2d7edb92
MC		 1158#define E1000_82542_PBS E1000_PBS
1159#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1160#define E1000_82542_EEARBC E1000_EEARBC
1161#define E1000_82542_FLASHT E1000_FLASHT
1162#define E1000_82542_EEWR E1000_EEWR
1163#define E1000_82542_FLSWCTL E1000_FLSWCTL
1164#define E1000_82542_FLSWDATA E1000_FLSWDATA
1165#define E1000_82542_FLSWCNT E1000_FLSWCNT
1166#define E1000_82542_FLOP E1000_FLOP
1167#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1168#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
d37ea5d5 1169#define E1000_82542_PHY_CTRL E1000_PHY_CTRL
2d7edb92 1170#define E1000_82542_ERT E1000_ERT
1da177e4 1171#define E1000_82542_RXDCTL E1000_RXDCTL
d37ea5d5 1172#define E1000_82542_RXDCTL1 E1000_RXDCTL1
1da177e4
LT		 1173#define E1000_82542_RADV E1000_RADV
1174#define E1000_82542_RSRPD E1000_RSRPD
1175#define E1000_82542_TXDMAC E1000_TXDMAC
d37ea5d5 1176#define E1000_82542_KABGTXD E1000_KABGTXD
1da177e4
LT		 1177#define E1000_82542_TDFHS E1000_TDFHS
1178#define E1000_82542_TDFTS E1000_TDFTS
1179#define E1000_82542_TDFPC E1000_TDFPC
1180#define E1000_82542_TXDCTL E1000_TXDCTL
1181#define E1000_82542_TADV E1000_TADV
1182#define E1000_82542_TSPMT E1000_TSPMT
1183#define E1000_82542_CRCERRS E1000_CRCERRS
1184#define E1000_82542_ALGNERRC E1000_ALGNERRC
1185#define E1000_82542_SYMERRS E1000_SYMERRS
1186#define E1000_82542_RXERRC E1000_RXERRC
1187#define E1000_82542_MPC E1000_MPC
1188#define E1000_82542_SCC E1000_SCC
1189#define E1000_82542_ECOL E1000_ECOL
1190#define E1000_82542_MCC E1000_MCC
1191#define E1000_82542_LATECOL E1000_LATECOL
1192#define E1000_82542_COLC E1000_COLC
1193#define E1000_82542_DC E1000_DC
1194#define E1000_82542_TNCRS E1000_TNCRS
1195#define E1000_82542_SEC E1000_SEC
1196#define E1000_82542_CEXTERR E1000_CEXTERR
1197#define E1000_82542_RLEC E1000_RLEC
1198#define E1000_82542_XONRXC E1000_XONRXC
1199#define E1000_82542_XONTXC E1000_XONTXC
1200#define E1000_82542_XOFFRXC E1000_XOFFRXC
1201#define E1000_82542_XOFFTXC E1000_XOFFTXC
1202#define E1000_82542_FCRUC E1000_FCRUC
1203#define E1000_82542_PRC64 E1000_PRC64
1204#define E1000_82542_PRC127 E1000_PRC127
1205#define E1000_82542_PRC255 E1000_PRC255
1206#define E1000_82542_PRC511 E1000_PRC511
1207#define E1000_82542_PRC1023 E1000_PRC1023
1208#define E1000_82542_PRC1522 E1000_PRC1522
1209#define E1000_82542_GPRC E1000_GPRC
1210#define E1000_82542_BPRC E1000_BPRC
1211#define E1000_82542_MPRC E1000_MPRC
1212#define E1000_82542_GPTC E1000_GPTC
1213#define E1000_82542_GORCL E1000_GORCL
1214#define E1000_82542_GORCH E1000_GORCH
1215#define E1000_82542_GOTCL E1000_GOTCL
1216#define E1000_82542_GOTCH E1000_GOTCH
1217#define E1000_82542_RNBC E1000_RNBC
1218#define E1000_82542_RUC E1000_RUC
1219#define E1000_82542_RFC E1000_RFC
1220#define E1000_82542_ROC E1000_ROC
1221#define E1000_82542_RJC E1000_RJC
1222#define E1000_82542_MGTPRC E1000_MGTPRC
1223#define E1000_82542_MGTPDC E1000_MGTPDC
1224#define E1000_82542_MGTPTC E1000_MGTPTC
1225#define E1000_82542_TORL E1000_TORL
1226#define E1000_82542_TORH E1000_TORH
1227#define E1000_82542_TOTL E1000_TOTL
1228#define E1000_82542_TOTH E1000_TOTH
1229#define E1000_82542_TPR E1000_TPR
1230#define E1000_82542_TPT E1000_TPT
1231#define E1000_82542_PTC64 E1000_PTC64
1232#define E1000_82542_PTC127 E1000_PTC127
1233#define E1000_82542_PTC255 E1000_PTC255
1234#define E1000_82542_PTC511 E1000_PTC511
1235#define E1000_82542_PTC1023 E1000_PTC1023
1236#define E1000_82542_PTC1522 E1000_PTC1522
1237#define E1000_82542_MPTC E1000_MPTC
1238#define E1000_82542_BPTC E1000_BPTC
1239#define E1000_82542_TSCTC E1000_TSCTC
1240#define E1000_82542_TSCTFC E1000_TSCTFC
1241#define E1000_82542_RXCSUM E1000_RXCSUM
1242#define E1000_82542_WUC E1000_WUC
1243#define E1000_82542_WUFC E1000_WUFC
1244#define E1000_82542_WUS E1000_WUS
1245#define E1000_82542_MANC E1000_MANC
1246#define E1000_82542_IPAV E1000_IPAV
1247#define E1000_82542_IP4AT E1000_IP4AT
1248#define E1000_82542_IP6AT E1000_IP6AT
1249#define E1000_82542_WUPL E1000_WUPL
1250#define E1000_82542_WUPM E1000_WUPM
1251#define E1000_82542_FFLT E1000_FFLT
1252#define E1000_82542_TDFH 0x08010
1253#define E1000_82542_TDFT 0x08018
1254#define E1000_82542_FFMT E1000_FFMT
1255#define E1000_82542_FFVT E1000_FFVT
1256#define E1000_82542_HOST_IF E1000_HOST_IF
2d7edb92
MC		 1257#define E1000_82542_IAM E1000_IAM
1258#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1259#define E1000_82542_PSRCTL E1000_PSRCTL
1260#define E1000_82542_RAID E1000_RAID
1261#define E1000_82542_TARC0 E1000_TARC0
1262#define E1000_82542_TDBAL1 E1000_TDBAL1
1263#define E1000_82542_TDBAH1 E1000_TDBAH1
1264#define E1000_82542_TDLEN1 E1000_TDLEN1
1265#define E1000_82542_TDH1 E1000_TDH1
1266#define E1000_82542_TDT1 E1000_TDT1
1267#define E1000_82542_TXDCTL1 E1000_TXDCTL1
1268#define E1000_82542_TARC1 E1000_TARC1
1269#define E1000_82542_RFCTL E1000_RFCTL
1270#define E1000_82542_GCR E1000_GCR
1271#define E1000_82542_GSCL_1 E1000_GSCL_1
1272#define E1000_82542_GSCL_2 E1000_GSCL_2
1273#define E1000_82542_GSCL_3 E1000_GSCL_3
1274#define E1000_82542_GSCL_4 E1000_GSCL_4
1275#define E1000_82542_FACTPS E1000_FACTPS
1276#define E1000_82542_SWSM E1000_SWSM
1277#define E1000_82542_FWSM E1000_FWSM
1278#define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1279#define E1000_82542_IAC E1000_IAC
1280#define E1000_82542_ICRXPTC E1000_ICRXPTC
1281#define E1000_82542_ICRXATC E1000_ICRXATC
1282#define E1000_82542_ICTXPTC E1000_ICTXPTC
1283#define E1000_82542_ICTXATC E1000_ICTXATC
1284#define E1000_82542_ICTXQEC E1000_ICTXQEC
1285#define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1286#define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1287#define E1000_82542_ICRXOC E1000_ICRXOC
1288#define E1000_82542_HICR E1000_HICR
1da177e4 1289
868d5309
MC		 1290#define E1000_82542_CPUVEC E1000_CPUVEC
1291#define E1000_82542_MRQC E1000_MRQC
1292#define E1000_82542_RETA E1000_RETA
1293#define E1000_82542_RSSRK E1000_RSSRK
1294#define E1000_82542_RSSIM E1000_RSSIM
1295#define E1000_82542_RSSIR E1000_RSSIR
6418ecc6
JK		 1296#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
1297#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
868d5309 1298
1da177e4
LT		 1299/* Statistics counters collected by the MAC */
1300struct e1000_hw_stats {
1301 uint64_t crcerrs;
1302 uint64_t algnerrc;
1303 uint64_t symerrs;
1304 uint64_t rxerrc;
49559854 1305 uint64_t txerrc;
1da177e4
LT		 1306 uint64_t mpc;
1307 uint64_t scc;
1308 uint64_t ecol;
1309 uint64_t mcc;
1310 uint64_t latecol;
1311 uint64_t colc;
1312 uint64_t dc;
1313 uint64_t tncrs;
1314 uint64_t sec;
1315 uint64_t cexterr;
1316 uint64_t rlec;
1317 uint64_t xonrxc;
1318 uint64_t xontxc;
1319 uint64_t xoffrxc;
1320 uint64_t xofftxc;
1321 uint64_t fcruc;
1322 uint64_t prc64;
1323 uint64_t prc127;
1324 uint64_t prc255;
1325 uint64_t prc511;
1326 uint64_t prc1023;
1327 uint64_t prc1522;
1328 uint64_t gprc;
1329 uint64_t bprc;
1330 uint64_t mprc;
1331 uint64_t gptc;
1332 uint64_t gorcl;
1333 uint64_t gorch;
1334 uint64_t gotcl;
1335 uint64_t gotch;
1336 uint64_t rnbc;
1337 uint64_t ruc;
1da177e4 1338 uint64_t roc;
49559854
MW		 1339 uint64_t rlerrc;
1340 uint64_t rfc;
1da177e4
LT		 1341 uint64_t rjc;
1342 uint64_t mgprc;
1343 uint64_t mgpdc;
1344 uint64_t mgptc;
1345 uint64_t torl;
1346 uint64_t torh;
1347 uint64_t totl;
1348 uint64_t toth;
1349 uint64_t tpr;
1350 uint64_t tpt;
1351 uint64_t ptc64;
1352 uint64_t ptc127;
1353 uint64_t ptc255;
1354 uint64_t ptc511;
1355 uint64_t ptc1023;
1356 uint64_t ptc1522;
1357 uint64_t mptc;
1358 uint64_t bptc;
1359 uint64_t tsctc;
1360 uint64_t tsctfc;
2d7edb92
MC		 1361 uint64_t iac;
1362 uint64_t icrxptc;
1363 uint64_t icrxatc;
1364 uint64_t ictxptc;
1365 uint64_t ictxatc;
1366 uint64_t ictxqec;
1367 uint64_t ictxqmtc;
1368 uint64_t icrxdmtc;
1369 uint64_t icrxoc;
1da177e4
LT		 1370};
1371
1372/* Structure containing variables used by the shared code (e1000_hw.c) */
1373struct e1000_hw {
0c5649af
AV		 1374 uint8_t __iomem *hw_addr;
1375 uint8_t __iomem *flash_address;
1da177e4
LT		 1376 e1000_mac_type mac_type;
1377 e1000_phy_type phy_type;
1378 uint32_t phy_init_script;
1379 e1000_media_type media_type;
1380 void *back;
d37ea5d5
AK		 1381 struct e1000_shadow_ram *eeprom_shadow_ram;
1382 uint32_t flash_bank_size;
1383 uint32_t flash_base_addr;
1da177e4
LT		 1384 e1000_fc_type fc;
1385 e1000_bus_speed bus_speed;
1386 e1000_bus_width bus_width;
1387 e1000_bus_type bus_type;
1388 struct e1000_eeprom_info eeprom;
1389 e1000_ms_type master_slave;
1390 e1000_ms_type original_master_slave;
1391 e1000_ffe_config ffe_config_state;
1392 uint32_t asf_firmware_present;
2d7edb92 1393 uint32_t eeprom_semaphore_present;
6418ecc6 1394 uint32_t swfw_sync_present;
d37ea5d5 1395 uint32_t swfwhw_semaphore_present;
1da177e4
LT		 1396 unsigned long io_base;
1397 uint32_t phy_id;
1398 uint32_t phy_revision;
1399 uint32_t phy_addr;
1400 uint32_t original_fc;
1401 uint32_t txcw;
1402 uint32_t autoneg_failed;
1403 uint32_t max_frame_size;
1404 uint32_t min_frame_size;
1405 uint32_t mc_filter_type;
1406 uint32_t num_mc_addrs;
1407 uint32_t collision_delta;
1408 uint32_t tx_packet_delta;
1409 uint32_t ledctl_default;
1410 uint32_t ledctl_mode1;
1411 uint32_t ledctl_mode2;
2d7edb92
MC		 1412 boolean_t tx_pkt_filtering;
1413 struct e1000_host_mng_dhcp_cookie mng_cookie;
1da177e4
LT		 1414 uint16_t phy_spd_default;
1415 uint16_t autoneg_advertised;
1416 uint16_t pci_cmd_word;
1417 uint16_t fc_high_water;
1418 uint16_t fc_low_water;
1419 uint16_t fc_pause_time;
1420 uint16_t current_ifs_val;
1421 uint16_t ifs_min_val;
1422 uint16_t ifs_max_val;
1423 uint16_t ifs_step_size;
1424 uint16_t ifs_ratio;
1425 uint16_t device_id;
1426 uint16_t vendor_id;
1427 uint16_t subsystem_id;
1428 uint16_t subsystem_vendor_id;
1429 uint8_t revision_id;
1430 uint8_t autoneg;
1431 uint8_t mdix;
1432 uint8_t forced_speed_duplex;
1433 uint8_t wait_autoneg_complete;
1434 uint8_t dma_fairness;
1435 uint8_t mac_addr[NODE_ADDRESS_SIZE];
1436 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
1437 boolean_t disable_polarity_correction;
1438 boolean_t speed_downgraded;
1439 e1000_smart_speed smart_speed;
1440 e1000_dsp_config dsp_config_state;
1441 boolean_t get_link_status;
1442 boolean_t serdes_link_down;
1443 boolean_t tbi_compatibility_en;
1444 boolean_t tbi_compatibility_on;
868d5309 1445 boolean_t laa_is_present;
1da177e4 1446 boolean_t phy_reset_disable;
09ae3e88 1447 boolean_t initialize_hw_bits_disable;
1da177e4
LT		 1448 boolean_t fc_send_xon;
1449 boolean_t fc_strict_ieee;
1450 boolean_t report_tx_early;
1451 boolean_t adaptive_ifs;
1452 boolean_t ifs_params_forced;
1453 boolean_t in_ifs_mode;
2d7edb92 1454 boolean_t mng_reg_access_disabled;
8df06e50 1455 boolean_t leave_av_bit_off;
d37ea5d5 1456 boolean_t kmrn_lock_loss_workaround_disabled;
1da177e4
LT		 1457};
1458
1459
1460#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1461#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
2d7edb92
MC		 1462#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1463#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1464#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1465#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1466#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1467#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1da177e4
LT		 1468/* Register Bit Masks */
1469/* Device Control */
1470#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1471#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1472#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
2d7edb92 1473#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1da177e4
LT		 1474#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1475#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1476#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1477#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1478#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1479#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1480#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1481#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1482#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1483#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1484#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1485#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1486#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
868d5309 1487#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
2d7edb92 1488#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
6418ecc6
JK		 1489#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
1490#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
1da177e4
LT		 1491#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1492#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1493#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1494#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1495#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1496#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1497#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1498#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1499#define E1000_CTRL_RST 0x04000000 /* Global reset */
1500#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1501#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1502#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1503#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1504#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
d37ea5d5 1505#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1da177e4
LT		 1506
1507/* Device Status */
1508#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1509#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1510#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
2d7edb92 1511#define E1000_STATUS_FUNC_SHIFT 2
1da177e4
LT		 1512#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1513#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1514#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1515#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1516#define E1000_STATUS_SPEED_MASK 0x000000C0
1517#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1518#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1519#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
d37ea5d5
AK		 1520#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1521 by EEPROM/Flash */
1da177e4 1522#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
2d7edb92
MC		 1523#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1524#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1da177e4
LT		 1525#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1526#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1527#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1528#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1529#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
6418ecc6
JK		 1530#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
1531#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
1532#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
1533#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
1534#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
1535#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
1536#define E1000_STATUS_FUSE_8 0x04000000
1537#define E1000_STATUS_FUSE_9 0x08000000
1538#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
1539#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
1da177e4
LT		 1540
1541/* Constants used to intrepret the masked PCI-X bus speed. */
1542#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1543#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1544#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1545
1546/* EEPROM/Flash Control */
1547#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1548#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1549#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1550#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1551#define E1000_EECD_FWE_MASK 0x00000030
1552#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1553#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1554#define E1000_EECD_FWE_SHIFT 4
1555#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1556#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1557#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1558#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1559#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1560 * (0-small, 1-large) */
1561#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1562#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1563#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1564#endif
2d7edb92
MC		 1565#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1566#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1567#define E1000_EECD_SIZE_EX_SHIFT 11
1568#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1569#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1570#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1571#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1572#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1573#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1574#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
fd803241 1575#define E1000_EECD_SECVAL_SHIFT 22
2d7edb92
MC		 1576#define E1000_STM_OPCODE 0xDB00
1577#define E1000_HICR_FW_RESET 0xC0
1da177e4 1578
d37ea5d5
AK		 1579#define E1000_SHADOW_RAM_WORDS 2048
1580#define E1000_ICH8_NVM_SIG_WORD 0x13
1581#define E1000_ICH8_NVM_SIG_MASK 0xC0
1582
1da177e4
LT		 1583/* EEPROM Read */
1584#define E1000_EERD_START 0x00000001 /* Start Read */
1585#define E1000_EERD_DONE 0x00000010 /* Read Done */
1586#define E1000_EERD_ADDR_SHIFT 8
1587#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1588#define E1000_EERD_DATA_SHIFT 16
1589#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1590
1591/* SPI EEPROM Status Register */
1592#define EEPROM_STATUS_RDY_SPI 0x01
1593#define EEPROM_STATUS_WEN_SPI 0x02
1594#define EEPROM_STATUS_BP0_SPI 0x04
1595#define EEPROM_STATUS_BP1_SPI 0x08
1596#define EEPROM_STATUS_WPEN_SPI 0x80
1597
1598/* Extended Device Control */
1599#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1600#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1601#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1602#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1603#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1604#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1605#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1606#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1607#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1608#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1609#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1610#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1611#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1612#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1613#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1614#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1615#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1616#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
f56799ea 1617#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1da177e4
LT		 1618#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1619#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1620#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
35574764 1621#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
6418ecc6 1622#define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000
35574764 1623#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
1da177e4
LT		 1624#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1625#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1626#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1627#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1628#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
35574764
NN		 1629#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1630#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1631#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
6418ecc6
JK		 1632#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
1633#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
1634#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
1da177e4
LT		 1635
1636/* MDI Control */
1637#define E1000_MDIC_DATA_MASK 0x0000FFFF
1638#define E1000_MDIC_REG_MASK 0x001F0000
1639#define E1000_MDIC_REG_SHIFT 16
1640#define E1000_MDIC_PHY_MASK 0x03E00000
1641#define E1000_MDIC_PHY_SHIFT 21
1642#define E1000_MDIC_OP_WRITE 0x04000000
1643#define E1000_MDIC_OP_READ 0x08000000
1644#define E1000_MDIC_READY 0x10000000
1645#define E1000_MDIC_INT_EN 0x20000000
1646#define E1000_MDIC_ERROR 0x40000000
1647
6418ecc6
JK		 1648#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
1649#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
1650#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
1651#define E1000_KUMCTRLSTA_REN 0x00200000
1652
1653#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
1654#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
1655#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
1656#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
1657#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
1658#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
1659#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
1660#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
1661#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
1662
1663/* FIFO Control */
1664#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
1665#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1666
1667/* In-Band Control */
d37ea5d5 1668#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
6418ecc6
JK		 1669#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1670
1671/* Half-Duplex Control */
1672#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1673#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1674
d37ea5d5
AK		 1675#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
1676
1677#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
1678#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
1679
1680#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
1681#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
1682#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
1683
1684#define E1000_KABGTXD_BGSQLBIAS 0x00050000
1685
1686#define E1000_PHY_CTRL_SPD_EN 0x00000001
1687#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1688#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1689#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1690#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1691#define E1000_PHY_CTRL_B2B_EN 0x00000080
1692
1da177e4
LT		 1693/* LED Control */
1694#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1695#define E1000_LEDCTL_LED0_MODE_SHIFT 0
2d7edb92 1696#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1da177e4
LT		 1697#define E1000_LEDCTL_LED0_IVRT 0x00000040
1698#define E1000_LEDCTL_LED0_BLINK 0x00000080
1699#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1700#define E1000_LEDCTL_LED1_MODE_SHIFT 8
2d7edb92 1701#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1da177e4
LT		 1702#define E1000_LEDCTL_LED1_IVRT 0x00004000
1703#define E1000_LEDCTL_LED1_BLINK 0x00008000
1704#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1705#define E1000_LEDCTL_LED2_MODE_SHIFT 16
2d7edb92 1706#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1da177e4
LT		 1707#define E1000_LEDCTL_LED2_IVRT 0x00400000
1708#define E1000_LEDCTL_LED2_BLINK 0x00800000
1709#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1710#define E1000_LEDCTL_LED3_MODE_SHIFT 24
868d5309 1711#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
1da177e4
LT		 1712#define E1000_LEDCTL_LED3_IVRT 0x40000000
1713#define E1000_LEDCTL_LED3_BLINK 0x80000000
1714
1715#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1716#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1717#define E1000_LEDCTL_MODE_LINK_UP 0x2
1718#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1719#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1720#define E1000_LEDCTL_MODE_LINK_10 0x5
1721#define E1000_LEDCTL_MODE_LINK_100 0x6
1722#define E1000_LEDCTL_MODE_LINK_1000 0x7
1723#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1724#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1725#define E1000_LEDCTL_MODE_COLLISION 0xA
1726#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1727#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1728#define E1000_LEDCTL_MODE_PAUSED 0xD
1729#define E1000_LEDCTL_MODE_LED_ON 0xE
1730#define E1000_LEDCTL_MODE_LED_OFF 0xF
1731
1732/* Receive Address */
1733#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1734
1735/* Interrupt Cause Read */
1736#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1737#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1738#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1739#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1740#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1741#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1742#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1743#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1744#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1745#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1746#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1747#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1748#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1749#define E1000_ICR_TXD_LOW 0x00008000
1750#define E1000_ICR_SRPD 0x00010000
2d7edb92
MC		 1751#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1752#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1753#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1754#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
6418ecc6
JK		 1755#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1756#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
1757#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
1758#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
1759#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1760#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1761#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
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AK		 1762#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1763#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1764#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
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LT		 1765
1766/* Interrupt Cause Set */
1767#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1768#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1769#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1770#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1771#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1772#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1773#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1774#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1775#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1776#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1777#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1778#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1779#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1780#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1781#define E1000_ICS_SRPD E1000_ICR_SRPD
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MC		 1782#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1783#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1784#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
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JK		 1785#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1786#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1787#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1788#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1789#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1790#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
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AK		 1791#define E1000_ICS_DSW E1000_ICR_DSW
1792#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1793#define E1000_ICS_EPRST E1000_ICR_EPRST
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LT		 1794
1795/* Interrupt Mask Set */
1796#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1797#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1798#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1799#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1800#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1801#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1802#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1803#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1804#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1805#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1806#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1807#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1808#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1809#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1810#define E1000_IMS_SRPD E1000_ICR_SRPD
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MC		 1811#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1812#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1813#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
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JK		 1814#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1815#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1816#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1817#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1818#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1819#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
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AK		 1820#define E1000_IMS_DSW E1000_ICR_DSW
1821#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1822#define E1000_IMS_EPRST E1000_ICR_EPRST
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LT		 1823
1824/* Interrupt Mask Clear */
1825#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1826#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1827#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1828#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1829#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1830#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1831#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1832#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1833#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1834#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1835#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1836#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1837#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1838#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1839#define E1000_IMC_SRPD E1000_ICR_SRPD
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MC		 1840#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1841#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1842#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
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JK		 1843#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1844#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1845#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1846#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1847#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1848#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
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AK		 1849#define E1000_IMC_DSW E1000_ICR_DSW
1850#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1851#define E1000_IMC_EPRST E1000_ICR_EPRST
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LT		 1852
1853/* Receive Control */
1854#define E1000_RCTL_RST 0x00000001 /* Software reset */
1855#define E1000_RCTL_EN 0x00000002 /* enable */
1856#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1857#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1858#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1859#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1860#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1861#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1862#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1863#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
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MC		 1864#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1865#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
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LT		 1866#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1867#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1868#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1869#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1870#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1871#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1872#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1873#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1874#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1875#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1876/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1877#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1878#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1879#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1880#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1881/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1882#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1883#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1884#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1885#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1886#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1887#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1888#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1889#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1890#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1891#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
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MC		 1892#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1893#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1894
1895/* Use byte values for the following shift parameters
1896 * Usage:
1897 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1898 * E1000_PSRCTL_BSIZE0_MASK) |
1899 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1900 * E1000_PSRCTL_BSIZE1_MASK) |
1901 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1902 * E1000_PSRCTL_BSIZE2_MASK) |
1903 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1904 * E1000_PSRCTL_BSIZE3_MASK))
1905 * where value0 = [128..16256], default=256
1906 * value1 = [1024..64512], default=4096
1907 * value2 = [0..64512], default=4096
1908 * value3 = [0..64512], default=0
1909 */
76c224bc 1910
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MC		 1911#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1912#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1913#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1914#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1915
1916#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1917#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1918#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1919#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1da177e4 1920
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JK		 1921/* SW_W_SYNC definitions */
1922#define E1000_SWFW_EEP_SM 0x0001
1923#define E1000_SWFW_PHY0_SM 0x0002
1924#define E1000_SWFW_PHY1_SM 0x0004
1925#define E1000_SWFW_MAC_CSR_SM 0x0008
1926
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LT		 1927/* Receive Descriptor */
1928#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1929#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1930#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1931#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1932#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1933
1934/* Flow Control */
1935#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1936#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1937#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1938#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1939
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MC		 1940/* Header split receive */
1941#define E1000_RFCTL_ISCSI_DIS 0x00000001
1942#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1943#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1944#define E1000_RFCTL_NFSW_DIS 0x00000040
1945#define E1000_RFCTL_NFSR_DIS 0x00000080
1946#define E1000_RFCTL_NFS_VER_MASK 0x00000300
1947#define E1000_RFCTL_NFS_VER_SHIFT 8
1948#define E1000_RFCTL_IPV6_DIS 0x00000400
1949#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1950#define E1000_RFCTL_ACK_DIS 0x00001000
1951#define E1000_RFCTL_ACKD_DIS 0x00002000
1952#define E1000_RFCTL_IPFRSP_DIS 0x00004000
1953#define E1000_RFCTL_EXTEN 0x00008000
1954#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1955#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1956
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LT		 1957/* Receive Descriptor Control */
1958#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1959#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1960#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1961#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1962
1963/* Transmit Descriptor Control */
1964#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1965#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1966#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1967#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1968#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1969#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
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MC		 1970#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1971 still to be processed. */
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LT		 1972/* Transmit Configuration Word */
1973#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1974#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1975#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1976#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1977#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1978#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1979#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1980#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1981#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1982#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1983
1984/* Receive Configuration Word */
1985#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1986#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1987#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1988#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1989#define E1000_RXCW_C 0x20000000 /* Receive config */
1990#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1991#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1992
1993/* Transmit Control */
1994#define E1000_TCTL_RST 0x00000001 /* software reset */
1995#define E1000_TCTL_EN 0x00000002 /* enable tx */
1996#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1997#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1998#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1999#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
2000#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
2001#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
2002#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
2003#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
2d7edb92 2004#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
6418ecc6
JK		 2005/* Extended Transmit Control */
2006#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
2007#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
2008
2009#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
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LT		 2010
2011/* Receive Checksum Control */
2012#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
2013#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
2014#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
2015#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
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MC		 2016#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
2017#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
2018
868d5309
MC		 2019/* Multiple Receive Queue Control */
2020#define E1000_MRQC_ENABLE_MASK 0x00000003
2021#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
2022#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
2023#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
2024#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2025#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
d37ea5d5 2026#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
868d5309
MC		 2027#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2028#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
d37ea5d5 2029#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1da177e4
LT		 2030
2031/* Definitions for power management and wakeup registers */
2032/* Wake Up Control */
2033#define E1000_WUC_APME 0x00000001 /* APM Enable */
2034#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
2035#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
2036#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
2037#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
2038
2039/* Wake Up Filter Control */
2040#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
2041#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
2042#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
2043#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
2044#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
2045#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
2046#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
2047#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
2d7edb92 2048#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1da177e4
LT		 2049#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
2050#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
2051#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
2052#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
2053#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
2054#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
2055#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2056
2057/* Wake Up Status */
2058#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
2059#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
2060#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
2061#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
2062#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
2063#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
2064#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
2065#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
2066#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
2067#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
2068#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
2069#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
2070#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2071
2072/* Management Control */
2073#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
2074#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
2075#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
2076#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
2077#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
2078#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
2079#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
2080#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
2081#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
2082#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
2083 * Filtering */
2d7edb92 2084#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
1da177e4
LT		 2085#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
2086#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
2087#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
85b22eb6 2088#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
2d7edb92 2089#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
1da177e4
LT		 2090#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
2091 * filtering */
2092#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
2093 * memory */
2d7edb92
MC		 2094#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2095 * filtering */
2096#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
8fc897b0 2097#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
1da177e4
LT		 2098#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2099#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2100#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
2101#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
2102#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
2103#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
2104
2105#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
2106#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
2107
2d7edb92
MC		 2108/* SW Semaphore Register */
2109#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2110#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2111#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2112#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2113
2114/* FW Semaphore Register */
2115#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2116#define E1000_FWSM_MODE_SHIFT 1
2117#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2118
d37ea5d5
AK		 2119#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2120#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2121#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2122#define E1000_FWSM_SKUEL_SHIFT 29
2123#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2124#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2125#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2126#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2127
2d7edb92
MC		 2128/* FFLT Debug Register */
2129#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2130
2131typedef enum {
2132 e1000_mng_mode_none = 0,
2133 e1000_mng_mode_asf,
2134 e1000_mng_mode_pt,
2135 e1000_mng_mode_ipmi,
2136 e1000_mng_mode_host_interface_only
2137} e1000_mng_mode;
2138
2139/* Host Inteface Control Register */
2140#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2141#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
2142 * to put command in RAM */
2143#define E1000_HICR_SV 0x00000004 /* Status Validity */
2144#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
2145
2146/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2147#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
2148#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
2149#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
2150#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2151
2152struct e1000_host_command_header {
2153 uint8_t command_id;
2154 uint8_t command_length;
2155 uint8_t command_options; /* I/F bits for command, status for return */
2156 uint8_t checksum;
2157};
2158struct e1000_host_command_info {
2159 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2160 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2161};
2162
2163/* Host SMB register #0 */
2164#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
2165#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
2166#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
2167#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
2168
2169/* Host SMB register #1 */
2170#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
2171#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
2172#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
2173#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2174
2175/* FW Status Register */
2176#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
2177
1da177e4
LT		 2178/* Wake Up Packet Length */
2179#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
2180
2181#define E1000_MDALIGN 4096
2182
8fc897b0 2183/* PCI-Ex registers*/
b7ee49db
JK		 2184
2185/* PCI-Ex Control Register */
0f15a8fa
JK		 2186#define E1000_GCR_RXD_NO_SNOOP 0x00000001
2187#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
2188#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
2189#define E1000_GCR_TXD_NO_SNOOP 0x00000008
2190#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
2191#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
2192
2193#define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
2194 E1000_GCR_RXDSCW_NO_SNOOP | \
2195 E1000_GCR_RXDSCR_NO_SNOOP | \
2196 E1000_GCR_TXD_NO_SNOOP | \
2197 E1000_GCR_TXDSCW_NO_SNOOP | \
2198 E1000_GCR_TXDSCR_NO_SNOOP)
b7ee49db 2199
d37ea5d5
AK		 2200#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2201
868d5309 2202#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2d7edb92
MC		 2203/* Function Active and Power State to MNG */
2204#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
2205#define E1000_FACTPS_LAN0_VALID 0x00000004
2206#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
2207#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
2208#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
2209#define E1000_FACTPS_LAN1_VALID 0x00000100
2210#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
2211#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
2212#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
2213#define E1000_FACTPS_IDE_ENABLE 0x00004000
2214#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
2215#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
2216#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
2217#define E1000_FACTPS_SP_ENABLE 0x00100000
2218#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
2219#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
2220#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
2221#define E1000_FACTPS_IPMI_ENABLE 0x04000000
2222#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
2223#define E1000_FACTPS_MNGCG 0x20000000
2224#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
2225#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
2226
caeccb68
JK		 2227/* PCI-Ex Config Space */
2228#define PCI_EX_LINK_STATUS 0x12
2229#define PCI_EX_LINK_WIDTH_MASK 0x3F0
2230#define PCI_EX_LINK_WIDTH_SHIFT 4
2231
1da177e4
LT		 2232/* EEPROM Commands - Microwire */
2233#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2234#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2235#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2236#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2237#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
2238
2239/* EEPROM Commands - SPI */
8fc897b0 2240#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2d7edb92
MC		 2241#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2242#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2243#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2244#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2245#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2246#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2247#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2248#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2249#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2250#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1da177e4
LT		 2251
2252/* EEPROM Size definitions */
2d7edb92
MC		 2253#define EEPROM_WORD_SIZE_SHIFT 6
2254#define EEPROM_SIZE_SHIFT 10
1da177e4
LT		 2255#define EEPROM_SIZE_MASK 0x1C00
2256
2257/* EEPROM Word Offsets */
2258#define EEPROM_COMPAT 0x0003
2259#define EEPROM_ID_LED_SETTINGS 0x0004
868d5309 2260#define EEPROM_VERSION 0x0005
1da177e4
LT		 2261#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2262#define EEPROM_PHY_CLASS_WORD 0x0007
2263#define EEPROM_INIT_CONTROL1_REG 0x000A
2264#define EEPROM_INIT_CONTROL2_REG 0x000F
d37ea5d5 2265#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
1da177e4 2266#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
85b22eb6 2267#define EEPROM_INIT_3GIO_3 0x001A
d37ea5d5 2268#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
1da177e4
LT		 2269#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2270#define EEPROM_CFG 0x0012
2271#define EEPROM_FLASH_VERSION 0x0032
2272#define EEPROM_CHECKSUM_REG 0x003F
2273
868d5309 2274#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
6418ecc6 2275#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
868d5309 2276
1da177e4
LT		 2277/* Word definitions for ID LED Settings */
2278#define ID_LED_RESERVED_0000 0x0000
2279#define ID_LED_RESERVED_FFFF 0xFFFF
d37ea5d5
AK		 2280#define ID_LED_RESERVED_82573 0xF746
2281#define ID_LED_DEFAULT_82573 0x1811
1da177e4
LT		 2282#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2283 (ID_LED_OFF1_OFF2 << 8) | \
2284 (ID_LED_DEF1_DEF2 << 4) | \
2285 (ID_LED_DEF1_DEF2))
d37ea5d5
AK		 2286#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
2287 (ID_LED_DEF1_OFF2 << 8) | \
2288 (ID_LED_DEF1_ON2 << 4) | \
2289 (ID_LED_DEF1_DEF2))
1da177e4
LT		 2290#define ID_LED_DEF1_DEF2 0x1
2291#define ID_LED_DEF1_ON2 0x2
2292#define ID_LED_DEF1_OFF2 0x3
2293#define ID_LED_ON1_DEF2 0x4
2294#define ID_LED_ON1_ON2 0x5
2295#define ID_LED_ON1_OFF2 0x6
2296#define ID_LED_OFF1_DEF2 0x7
2297#define ID_LED_OFF1_ON2 0x8
2298#define ID_LED_OFF1_OFF2 0x9
2299
2300#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2301#define IGP_ACTIVITY_LED_ENABLE 0x0300
2302#define IGP_LED3_MODE 0x07000000
2303
2304
2305/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2306#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2307
2308/* Mask bit for PHY class in Word 7 of the EEPROM */
2309#define EEPROM_PHY_CLASS_A 0x8000
2310
2311/* Mask bits for fields in Word 0x0a of the EEPROM */
2312#define EEPROM_WORD0A_ILOS 0x0010
2313#define EEPROM_WORD0A_SWDPIO 0x01E0
2314#define EEPROM_WORD0A_LRST 0x0200
2315#define EEPROM_WORD0A_FD 0x0400
2316#define EEPROM_WORD0A_66MHZ 0x0800
2317
2318/* Mask bits for fields in Word 0x0f of the EEPROM */
2319#define EEPROM_WORD0F_PAUSE_MASK 0x3000
2320#define EEPROM_WORD0F_PAUSE 0x1000
2321#define EEPROM_WORD0F_ASM_DIR 0x2000
2322#define EEPROM_WORD0F_ANE 0x0800
2323#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
d37ea5d5
AK		 2324#define EEPROM_WORD0F_LPLU 0x0001
2325
2326/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
2327#define EEPROM_WORD1020_GIGA_DISABLE 0x0010
2328#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
1da177e4 2329
85b22eb6
JK		 2330/* Mask bits for fields in Word 0x1a of the EEPROM */
2331#define EEPROM_WORD1A_ASPM_MASK 0x000C
2332
1da177e4
LT		 2333/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2334#define EEPROM_SUM 0xBABA
2335
2336/* EEPROM Map defines (WORD OFFSETS)*/
2337#define EEPROM_NODE_ADDRESS_BYTE_0 0
2338#define EEPROM_PBA_BYTE_1 8
2339
2340#define EEPROM_RESERVED_WORD 0xFFFF
2341
2342/* EEPROM Map Sizes (Byte Counts) */
2343#define PBA_SIZE 4
2344
2345/* Collision related configuration parameters */
2346#define E1000_COLLISION_THRESHOLD 15
2347#define E1000_CT_SHIFT 4
0fadb059
JK		 2348/* Collision distance is a 0-based value that applies to
2349 * half-duplex-capable hardware only. */
2350#define E1000_COLLISION_DISTANCE 63
2351#define E1000_COLLISION_DISTANCE_82542 64
1da177e4
LT		 2352#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2353#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2354#define E1000_COLD_SHIFT 12
2355
2356/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2357#define REQ_TX_DESCRIPTOR_MULTIPLE 8
2358#define REQ_RX_DESCRIPTOR_MULTIPLE 8
2359
2360/* Default values for the transmit IPG register */
2361#define DEFAULT_82542_TIPG_IPGT 10
2362#define DEFAULT_82543_TIPG_IPGT_FIBER 9
2363#define DEFAULT_82543_TIPG_IPGT_COPPER 8
2364
2365#define E1000_TIPG_IPGT_MASK 0x000003FF
2366#define E1000_TIPG_IPGR1_MASK 0x000FFC00
2367#define E1000_TIPG_IPGR2_MASK 0x3FF00000
2368
2369#define DEFAULT_82542_TIPG_IPGR1 2
2370#define DEFAULT_82543_TIPG_IPGR1 8
2371#define E1000_TIPG_IPGR1_SHIFT 10
2372
2373#define DEFAULT_82542_TIPG_IPGR2 10
2374#define DEFAULT_82543_TIPG_IPGR2 6
6418ecc6 2375#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
1da177e4
LT		 2376#define E1000_TIPG_IPGR2_SHIFT 20
2377
6418ecc6
JK		 2378#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
2379#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
1da177e4
LT		 2380#define E1000_TXDMAC_DPP 0x00000001
2381
2382/* Adaptive IFS defines */
2383#define TX_THRESHOLD_START 8
2384#define TX_THRESHOLD_INCREMENT 10
2385#define TX_THRESHOLD_DECREMENT 1
2386#define TX_THRESHOLD_STOP 190
2387#define TX_THRESHOLD_DISABLE 0
2388#define TX_THRESHOLD_TIMER_MS 10000
2389#define MIN_NUM_XMITS 1000
2390#define IFS_MAX 80
2391#define IFS_STEP 10
2392#define IFS_MIN 40
2393#define IFS_RATIO 4
2394
2d7edb92
MC		 2395/* Extended Configuration Control and Size */
2396#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2397#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2398#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2399#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2400#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2401#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2402#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
d37ea5d5 2403#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
2d7edb92
MC		 2404
2405#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2406#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2407#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
d37ea5d5
AK		 2408#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
2409#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2d7edb92 2410
1da177e4 2411/* PBA constants */
d37ea5d5 2412#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2d7edb92 2413#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
1da177e4
LT		 2414#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2415#define E1000_PBA_22K 0x0016
2416#define E1000_PBA_24K 0x0018
2417#define E1000_PBA_30K 0x001E
868d5309 2418#define E1000_PBA_32K 0x0020
d37ea5d5 2419#define E1000_PBA_34K 0x0022
868d5309 2420#define E1000_PBA_38K 0x0026
1da177e4
LT		 2421#define E1000_PBA_40K 0x0028
2422#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2423
d37ea5d5
AK		 2424#define E1000_PBS_16K E1000_PBA_16K
2425
1da177e4
LT		 2426/* Flow Control Constants */
2427#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2428#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2429#define FLOW_CONTROL_TYPE 0x8808
2430
2431/* The historical defaults for the flow control values are given below. */
2432#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2433#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2434#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2435
2436/* PCIX Config space */
2437#define PCIX_COMMAND_REGISTER 0xE6
2438#define PCIX_STATUS_REGISTER_LO 0xE8
2439#define PCIX_STATUS_REGISTER_HI 0xEA
2440
2441#define PCIX_COMMAND_MMRBC_MASK 0x000C
2442#define PCIX_COMMAND_MMRBC_SHIFT 0x2
2443#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2444#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2445#define PCIX_STATUS_HI_MMRBC_4K 0x3
2446#define PCIX_STATUS_HI_MMRBC_2K 0x2
2447
2448
2449/* Number of bits required to shift right the "pause" bits from the
2450 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2451 */
2452#define PAUSE_SHIFT 5
2453
2454/* Number of bits required to shift left the "SWDPIO" bits from the
2455 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2456 */
2457#define SWDPIO_SHIFT 17
2458
2459/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2460 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2461 */
2462#define SWDPIO__EXT_SHIFT 4
2463
2464/* Number of bits required to shift left the "ILOS" bit from the EEPROM
2465 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2466 */
2467#define ILOS_SHIFT 3
2468
2469
2470#define RECEIVE_BUFFER_ALIGN_SIZE (256)
2471
2472/* Number of milliseconds we wait for auto-negotiation to complete */
2473#define LINK_UP_TIMEOUT 500
2474
2d7edb92
MC		 2475/* Number of 100 microseconds we wait for PCI Express master disable */
2476#define MASTER_DISABLE_TIMEOUT 800
2477/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2478#define AUTO_READ_DONE_TIMEOUT 10
2479/* Number of milliseconds we wait for PHY configuration done after MAC reset */
d37ea5d5 2480#define PHY_CFG_TIMEOUT 100
2d7edb92 2481
1da177e4
LT		 2482#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2483
2484/* The carrier extension symbol, as received by the NIC. */
2485#define CARRIER_EXTENSION 0x0F
2486
2487/* TBI_ACCEPT macro definition:
2488 *
2489 * This macro requires:
2490 * adapter = a pointer to struct e1000_hw
2491 * status = the 8 bit status field of the RX descriptor with EOP set
2492 * error = the 8 bit error field of the RX descriptor with EOP set
2493 * length = the sum of all the length fields of the RX descriptors that
2494 * make up the current frame
2495 * last_byte = the last byte of the frame DMAed by the hardware
2496 * max_frame_length = the maximum frame length we want to accept.
2497 * min_frame_length = the minimum frame length we want to accept.
2498 *
2499 * This macro is a conditional that should be used in the interrupt
2500 * handler's Rx processing routine when RxErrors have been detected.
2501 *
2502 * Typical use:
2503 * ...
2504 * if (TBI_ACCEPT) {
2505 * accept_frame = TRUE;
2506 * e1000_tbi_adjust_stats(adapter, MacAddress);
2507 * frame_length--;
2508 * } else {
2509 * accept_frame = FALSE;
2510 * }
2511 * ...
2512 */
2513
2514#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2515 ((adapter)->tbi_compatibility_on && \
2516 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2517 ((last_byte) == CARRIER_EXTENSION) && \
2518 (((status) & E1000_RXD_STAT_VP) ? \
2519 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2520 ((length) <= ((adapter)->max_frame_size + 1))) : \
2521 (((length) > (adapter)->min_frame_size) && \
2522 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2523
2524
2525/* Structures, enums, and macros for the PHY */
2526
2527/* Bit definitions for the Management Data IO (MDIO) and Management Data
2528 * Clock (MDC) pins in the Device Control Register.
2529 */
2530#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2531#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2532#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2533#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2534#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2535#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2536#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2537#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2538
2539/* PHY 1000 MII Register/Bit Definitions */
2540/* PHY Registers defined by IEEE */
2541#define PHY_CTRL 0x00 /* Control Register */
2542#define PHY_STATUS 0x01 /* Status Regiser */
2543#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2544#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2545#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2546#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2547#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2548#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2549#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2550#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2551#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2552#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2553
2554#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2555#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2556
2557/* M88E1000 Specific Registers */
2558#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2559#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2560#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2561#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2562#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2563#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2564
2565#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2566#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2567#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2568#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2569#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2570
2571#define IGP01E1000_IEEE_REGS_PAGE 0x0000
2572#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2573#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2574
2575/* IGP01E1000 Specific Registers */
2576#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2577#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2578#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2579#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2580#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2581#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2d7edb92 2582#define IGP02E1000_PHY_POWER_MGMT 0x19
1da177e4
LT		 2583#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2584
2585/* IGP01E1000 AGC Registers - stores the cable length values*/
2586#define IGP01E1000_PHY_AGC_A 0x1172
2587#define IGP01E1000_PHY_AGC_B 0x1272
2588#define IGP01E1000_PHY_AGC_C 0x1472
2589#define IGP01E1000_PHY_AGC_D 0x1872
2590
2d7edb92
MC		 2591/* IGP02E1000 AGC Registers for cable length values */
2592#define IGP02E1000_PHY_AGC_A 0x11B1
2593#define IGP02E1000_PHY_AGC_B 0x12B1
2594#define IGP02E1000_PHY_AGC_C 0x14B1
2595#define IGP02E1000_PHY_AGC_D 0x18B1
2596
1da177e4
LT		 2597/* IGP01E1000 DSP Reset Register */
2598#define IGP01E1000_PHY_DSP_RESET 0x1F33
2599#define IGP01E1000_PHY_DSP_SET 0x1F71
2600#define IGP01E1000_PHY_DSP_FFE 0x1F35
2601
2602#define IGP01E1000_PHY_CHANNEL_NUM 4
2d7edb92
MC		 2603#define IGP02E1000_PHY_CHANNEL_NUM 4
2604
1da177e4
LT		 2605#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2606#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2607#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2608#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2609
2610#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2611#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2612
2613#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2614#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2615#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2616#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2617
2618#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2619/* IGP01E1000 PCS Initialization register - stores the polarity status when
2620 * speed = 1000 Mbps. */
2621#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2622#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2623
2624#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2625
6418ecc6
JK		 2626/* Bits...
2627 * 15-5: page
2628 * 4-0: register offset
2629 */
2630#define GG82563_PAGE_SHIFT 5
2631#define GG82563_REG(page, reg) \
2632 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2633#define GG82563_MIN_ALT_REG 30
2634
2635/* GG82563 Specific Registers */
2636#define GG82563_PHY_SPEC_CTRL \
2637 GG82563_REG(0, 16) /* PHY Specific Control */
2638#define GG82563_PHY_SPEC_STATUS \
2639 GG82563_REG(0, 17) /* PHY Specific Status */
2640#define GG82563_PHY_INT_ENABLE \
2641 GG82563_REG(0, 18) /* Interrupt Enable */
2642#define GG82563_PHY_SPEC_STATUS_2 \
2643 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2644#define GG82563_PHY_RX_ERR_CNTR \
2645 GG82563_REG(0, 21) /* Receive Error Counter */
2646#define GG82563_PHY_PAGE_SELECT \
2647 GG82563_REG(0, 22) /* Page Select */
2648#define GG82563_PHY_SPEC_CTRL_2 \
2649 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2650#define GG82563_PHY_PAGE_SELECT_ALT \
2651 GG82563_REG(0, 29) /* Alternate Page Select */
2652#define GG82563_PHY_TEST_CLK_CTRL \
2653 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2654
2655#define GG82563_PHY_MAC_SPEC_CTRL \
2656 GG82563_REG(2, 21) /* MAC Specific Control Register */
2657#define GG82563_PHY_MAC_SPEC_CTRL_2 \
2658 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2659
2660#define GG82563_PHY_DSP_DISTANCE \
2661 GG82563_REG(5, 26) /* DSP Distance */
2662
2663/* Page 193 - Port Control Registers */
2664#define GG82563_PHY_KMRN_MODE_CTRL \
2665 GG82563_REG(193, 16) /* Kumeran Mode Control */
2666#define GG82563_PHY_PORT_RESET \
2667 GG82563_REG(193, 17) /* Port Reset */
2668#define GG82563_PHY_REVISION_ID \
2669 GG82563_REG(193, 18) /* Revision ID */
2670#define GG82563_PHY_DEVICE_ID \
2671 GG82563_REG(193, 19) /* Device ID */
2672#define GG82563_PHY_PWR_MGMT_CTRL \
2673 GG82563_REG(193, 20) /* Power Management Control */
2674#define GG82563_PHY_RATE_ADAPT_CTRL \
2675 GG82563_REG(193, 25) /* Rate Adaptation Control */
2676
2677/* Page 194 - KMRN Registers */
2678#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
2679 GG82563_REG(194, 16) /* FIFO's Control/Status */
2680#define GG82563_PHY_KMRN_CTRL \
2681 GG82563_REG(194, 17) /* Control */
2682#define GG82563_PHY_INBAND_CTRL \
2683 GG82563_REG(194, 18) /* Inband Control */
2684#define GG82563_PHY_KMRN_DIAGNOSTIC \
2685 GG82563_REG(194, 19) /* Diagnostic */
2686#define GG82563_PHY_ACK_TIMEOUTS \
2687 GG82563_REG(194, 20) /* Acknowledge Timeouts */
2688#define GG82563_PHY_ADV_ABILITY \
2689 GG82563_REG(194, 21) /* Advertised Ability */
2690#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
2691 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2692#define GG82563_PHY_ADV_NEXT_PAGE \
2693 GG82563_REG(194, 24) /* Advertised Next Page */
2694#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
2695 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2696#define GG82563_PHY_KMRN_MISC \
2697 GG82563_REG(194, 26) /* Misc. */
1da177e4
LT		 2698
2699/* PHY Control Register */
2700#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2701#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2702#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2703#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2704#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2705#define MII_CR_POWER_DOWN 0x0800 /* Power down */
2706#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2707#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2708#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2709#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2710
2711/* PHY Status Register */
2712#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2713#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2714#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2715#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2716#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2717#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2718#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2719#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2720#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2721#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2722#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2723#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2724#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2725#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2726#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2727
2728/* Autoneg Advertisement Register */
2729#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2730#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2731#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2732#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2733#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2734#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2735#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2736#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2737#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2738#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2739
2740/* Link Partner Ability Register (Base Page) */
2741#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2742#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2743#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2744#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2745#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2746#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2747#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2748#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2749#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2750#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2751#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2752
2753/* Autoneg Expansion Register */
2754#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2755#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2756#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2757#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2758#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2759
2760/* Next Page TX Register */
2761#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2762#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2763 * of different NP
2764 */
2765#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2766 * 0 = cannot comply with msg
2767 */
2768#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2769#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2770 * 0 = sending last NP
2771 */
2772
2773/* Link Partner Next Page Register */
2774#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2775#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2776 * of different NP
2777 */
2778#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2779 * 0 = cannot comply with msg
2780 */
2781#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2782#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2783#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2784 * 0 = sending last NP
2785 */
2786
2787/* 1000BASE-T Control Register */
2788#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2789#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2790#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2791#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2792 /* 0=DTE device */
2793#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2794 /* 0=Configure PHY as Slave */
2795#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2796 /* 0=Automatic Master/Slave config */
2797#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2798#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2799#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2800#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2801#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2802
2803/* 1000BASE-T Status Register */
2804#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2805#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2806#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2807#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2808#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2809#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2810#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2811#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2812#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2813#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2814#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2815#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2816#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2817
2818/* Extended Status Register */
2819#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2820#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2821#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2822#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2823
2824#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2825#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2826
2827#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2828 /* (0=enable, 1=disable) */
2829
2830/* M88E1000 PHY Specific Control Register */
2831#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2832#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2833#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2834#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2835 * 0=CLK125 toggling
2836 */
2837#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2838 /* Manual MDI configuration */
2839#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2840#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2841 * 100BASE-TX/10BASE-T:
2842 * MDI Mode
2843 */
2844#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2845 * all speeds.
2846 */
2847#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2848 /* 1=Enable Extended 10BASE-T distance
2849 * (Lower 10BASE-T RX Threshold)
2850 * 0=Normal 10BASE-T RX Threshold */
2851#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2852 /* 1=5-Bit interface in 100BASE-TX
2853 * 0=MII interface in 100BASE-TX */
2854#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2855#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2856#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2857
2858#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2859#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2860#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2861
2862/* M88E1000 PHY Specific Status Register */
2863#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2864#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2865#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2866#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2867#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2868 * 3=110-140M;4=>140M */
2869#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2870#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2871#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2872#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2873#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2874#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2875#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2876#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2877
2878#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2879#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2880#define M88E1000_PSSR_MDIX_SHIFT 6
2881#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2882
2883/* M88E1000 Extended PHY Specific Control Register */
2884#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2885#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2886 * Will assert lost lock and bring
2887 * link down if idle not seen
2888 * within 1ms in 1000BASE-T
2889 */
2890/* Number of times we will attempt to autonegotiate before downshifting if we
2891 * are the master */
2892#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2893#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2894#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2895#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2896#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2897/* Number of times we will attempt to autonegotiate before downshifting if we
2898 * are the slave */
2899#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2900#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2901#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2902#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2903#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2904#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2905#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2906#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2907
ee04022a
AK		 2908/* M88EC018 Rev 2 specific DownShift settings */
2909#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2910#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2911#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2912#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2913#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2914#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2915#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2916#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2917#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2918
1da177e4
LT		 2919/* IGP01E1000 Specific Port Config Register - R/W */
2920#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2921#define IGP01E1000_PSCFR_PRE_EN 0x0020
2922#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2923#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2924#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2925#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2926
2927/* IGP01E1000 Specific Port Status Register - R/O */
2928#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2929#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2930#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2931#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2932#define IGP01E1000_PSSR_LINK_UP 0x0400
2933#define IGP01E1000_PSSR_MDIX 0x0800
2934#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2935#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2936#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2937#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2938#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2939#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2940
2941/* IGP01E1000 Specific Port Control Register - R/W */
2942#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2943#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2944#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2945#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2946#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2947#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2948
2949/* IGP01E1000 Specific Port Link Health Register */
2950#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2951#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2952#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2953#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2954#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2955#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2956#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2957#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2958#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2959#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2960#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2961#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2962#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2963#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2964
2965/* IGP01E1000 Channel Quality Register */
2966#define IGP01E1000_MSE_CHANNEL_D 0x000F
2967#define IGP01E1000_MSE_CHANNEL_C 0x00F0
2968#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2969#define IGP01E1000_MSE_CHANNEL_A 0xF000
2970
2d7edb92
MC		 2971#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2972#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2973#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2974
1da177e4
LT		 2975/* IGP01E1000 DSP reset macros */
2976#define DSP_RESET_ENABLE 0x0
2977#define DSP_RESET_DISABLE 0x2
2978#define E1000_MAX_DSP_RESETS 10
2979
2d7edb92 2980/* IGP01E1000 & IGP02E1000 AGC Registers */
1da177e4
LT		 2981
2982#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2d7edb92
MC		 2983#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2984
2985/* IGP02E1000 AGC Register Length 9-bit mask */
2986#define IGP02E1000_AGC_LENGTH_MASK 0x7F
1da177e4
LT		 2987
2988/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2989#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
868d5309 2990#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
1da177e4 2991
2d7edb92 2992/* The precision error of the cable length is +/- 10 meters */
1da177e4 2993#define IGP01E1000_AGC_RANGE 10
868d5309 2994#define IGP02E1000_AGC_RANGE 15
1da177e4
LT		 2995
2996/* IGP01E1000 PCS Initialization register */
2997/* bits 3:6 in the PCS registers stores the channels polarity */
2998#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2999
3000/* IGP01E1000 GMII FIFO Register */
3001#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
3002 * on Link-Up */
3003#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
3004
3005/* IGP01E1000 Analog Register */
3006#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
3007#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
3008#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
3009#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
3010
3011#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
3012#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
3013#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
3014#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
3015#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
3016
3017#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
3018#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
3019#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
3020#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
3021
6418ecc6
JK		 3022/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
3023#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
3024#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */
3025#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
3026#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */
3027#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
3028#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */
3029#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */
3030#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */
3031#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */
3032#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
3033#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
3034#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */
3035#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
3036#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
3037#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
3038#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
3039#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
3040
3041/* PHY Specific Status Register (Page 0, Register 17) */
3042#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
3043#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
3044#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
3045#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
3046#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
3047#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
3048#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
3049#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
3050#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
3051#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
3052#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
3053#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
3054#define GG82563_PSSR_SPEED_MASK 0xC000
3055#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
3056#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
3057#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
3058
3059/* PHY Specific Status Register 2 (Page 0, Register 19) */
3060#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
3061#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
3062#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
3063#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
3064#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
3065#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
3066#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
3067#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
3068#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
3069#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
3070#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
3071#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
3072#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
3073
3074/* PHY Specific Control Register 2 (Page 0, Register 26) */
3075#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */
3076#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
3077#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */
3078#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */
3079#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */
3080#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */
3081#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */
3082#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
3083#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
3084#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
3085
3086/* MAC Specific Control Register (Page 2, Register 21) */
3087/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
3088#define GG82563_MSCR_TX_CLK_MASK 0x0007
3089#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
3090#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
3091#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
3092#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
3093
3094#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
3095
3096/* DSP Distance Register (Page 5, Register 26) */
3097#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
8fc897b0
AK		 3098 1 = 50-80M;
3099 2 = 80-110M;
3100 3 = 110-140M;
3101 4 = >140M */
6418ecc6
JK		 3102
3103/* Kumeran Mode Control Register (Page 193, Register 16) */
3104#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
3105#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
3106#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
3107#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
3108#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */
3109#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
3110
3111/* Power Management Control Register (Page 193, Register 20) */
3112#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */
3113#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
3114#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
3115#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */
3116#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */
3117#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */
3118#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */
3119#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
3120#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
3121#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
3122#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
3123#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
3124#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
3125
3126/* In-Band Control Register (Page 194, Register 18) */
3127#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
3128
1da177e4
LT		 3129
3130/* Bit definitions for valid PHY IDs. */
3131/* I = Integrated
3132 * E = External
3133 */
2a88c173 3134#define M88_VENDOR 0x0141
1da177e4
LT		 3135#define M88E1000_E_PHY_ID 0x01410C50
3136#define M88E1000_I_PHY_ID 0x01410C30
3137#define M88E1011_I_PHY_ID 0x01410C20
3138#define IGP01E1000_I_PHY_ID 0x02A80380
3139#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
3140#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
3141#define M88E1011_I_REV_4 0x04
2d7edb92
MC		 3142#define M88E1111_I_PHY_ID 0x01410CC0
3143#define L1LXT971A_PHY_ID 0x001378E0
6418ecc6 3144#define GG82563_E_PHY_ID 0x01410CA0
1da177e4 3145
d37ea5d5
AK		 3146
3147/* Bits...
3148 * 15-5: page
3149 * 4-0: register offset
3150 */
3151#define PHY_PAGE_SHIFT 5
3152#define PHY_REG(page, reg) \
3153 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
3154
3155#define IGP3_PHY_PORT_CTRL \
3156 PHY_REG(769, 17) /* Port General Configuration */
3157#define IGP3_PHY_RATE_ADAPT_CTRL \
3158 PHY_REG(769, 25) /* Rate Adapter Control Register */
3159
3160#define IGP3_KMRN_FIFO_CTRL_STATS \
3161 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
3162#define IGP3_KMRN_POWER_MNG_CTRL \
3163 PHY_REG(770, 17) /* KMRN Power Management Control Register */
3164#define IGP3_KMRN_INBAND_CTRL \
3165 PHY_REG(770, 18) /* KMRN Inband Control Register */
3166#define IGP3_KMRN_DIAG \
3167 PHY_REG(770, 19) /* KMRN Diagnostic register */
3168#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
3169#define IGP3_KMRN_ACK_TIMEOUT \
3170 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
3171
3172#define IGP3_VR_CTRL \
3173 PHY_REG(776, 18) /* Voltage regulator control register */
3174#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
3175
3176#define IGP3_CAPABILITY \
3177 PHY_REG(776, 19) /* IGP3 Capability Register */
3178
3179/* Capabilities for SKU Control */
3180#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
3181#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
3182#define IGP3_CAP_ASF 0x0004 /* Support ASF */
3183#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
3184#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
3185#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
3186#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
3187#define IGP3_CAP_RSS 0x0080 /* Support RSS */
3188#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
3189#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
3190
3191#define IGP3_PPC_JORDAN_EN 0x0001
3192#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
3193
3194#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
3195#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
3196#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
3197#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
3198
3199#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
3200#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
3201
3202#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
3203#define IGP3_KMRN_EC_DIS_INBAND 0x0080
3204
3205#define IGP03E1000_E_PHY_ID 0x02A80390
3206#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
3207#define IFE_PLUS_E_PHY_ID 0x02A80320
3208#define IFE_C_E_PHY_ID 0x02A80310
3209
3210#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
3211#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
3212#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
3213#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */
3214#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
3215#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
3216#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
3217#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
3218#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
3219#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
3220#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
3221#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
3222#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
3223
3224#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */
3225#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
3226#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
3227#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
3228#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
3229#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
3230#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
3231#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
3232
3233#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */
3234#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
3235#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
3236#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
3237#define IFE_PSC_FORCE_POLARITY_SHIFT 5
3238#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
3239
3240#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
3241#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
3242#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
3243#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorthm is completed */
3244#define IFE_PMC_MDIX_MODE_SHIFT 6
3245#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
3246
3247#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
3248#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
3249#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
3250#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
3251#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
3252#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
3253#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
3254#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
3255#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
3256#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3257#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3258
2a88c173
JK		 3259#define ICH8_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
3260#define ICH8_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
3261#define ICH8_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
d37ea5d5
AK		 3262#define ICH8_FLASH_SEG_SIZE_256 256
3263#define ICH8_FLASH_SEG_SIZE_4K 4096
2a88c173 3264#define ICH9_FLASH_SEG_SIZE_8K 8192
d37ea5d5
AK		 3265#define ICH8_FLASH_SEG_SIZE_64K 65536
3266
3267#define ICH8_CYCLE_READ 0x0
3268#define ICH8_CYCLE_RESERVED 0x1
3269#define ICH8_CYCLE_WRITE 0x2
3270#define ICH8_CYCLE_ERASE 0x3
3271
3272#define ICH8_FLASH_GFPREG 0x0000
3273#define ICH8_FLASH_HSFSTS 0x0004
3274#define ICH8_FLASH_HSFCTL 0x0006
3275#define ICH8_FLASH_FADDR 0x0008
3276#define ICH8_FLASH_FDATA0 0x0010
3277#define ICH8_FLASH_FRACC 0x0050
3278#define ICH8_FLASH_FREG0 0x0054
3279#define ICH8_FLASH_FREG1 0x0058
3280#define ICH8_FLASH_FREG2 0x005C
3281#define ICH8_FLASH_FREG3 0x0060
3282#define ICH8_FLASH_FPR0 0x0074
3283#define ICH8_FLASH_FPR1 0x0078
3284#define ICH8_FLASH_SSFSTS 0x0090
3285#define ICH8_FLASH_SSFCTL 0x0092
3286#define ICH8_FLASH_PREOP 0x0094
3287#define ICH8_FLASH_OPTYPE 0x0096
3288#define ICH8_FLASH_OPMENU 0x0098
3289
3290#define ICH8_FLASH_REG_MAPSIZE 0x00A0
3291#define ICH8_FLASH_SECTOR_SIZE 4096
3292#define ICH8_GFPREG_BASE_MASK 0x1FFF
3293#define ICH8_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3294
3295/* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
3296/* Offset 04h HSFSTS */
3297union ich8_hws_flash_status {
3298 struct ich8_hsfsts {
3299#ifdef E1000_BIG_ENDIAN
3300 uint16_t reserved2 :6;
3301 uint16_t fldesvalid :1;
3302 uint16_t flockdn :1;
3303 uint16_t flcdone :1;
3304 uint16_t flcerr :1;
3305 uint16_t dael :1;
3306 uint16_t berasesz :2;
3307 uint16_t flcinprog :1;
3308 uint16_t reserved1 :2;
3309#else
3310 uint16_t flcdone :1; /* bit 0 Flash Cycle Done */
3311 uint16_t flcerr :1; /* bit 1 Flash Cycle Error */
3312 uint16_t dael :1; /* bit 2 Direct Access error Log */
3313 uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */
3314 uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */
3315 uint16_t reserved1 :2; /* bit 13:6 Reserved */
3316 uint16_t reserved2 :6; /* bit 13:6 Reserved */
3317 uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */
3318 uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */
3319#endif
3320 } hsf_status;
3321 uint16_t regval;
3322};
3323
3324/* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
3325/* Offset 06h FLCTL */
3326union ich8_hws_flash_ctrl {
3327 struct ich8_hsflctl {
3328#ifdef E1000_BIG_ENDIAN
3329 uint16_t fldbcount :2;
3330 uint16_t flockdn :6;
3331 uint16_t flcgo :1;
3332 uint16_t flcycle :2;
3333 uint16_t reserved :5;
3334#else
3335 uint16_t flcgo :1; /* 0 Flash Cycle Go */
3336 uint16_t flcycle :2; /* 2:1 Flash Cycle */
3337 uint16_t reserved :5; /* 7:3 Reserved */
3338 uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */
3339 uint16_t flockdn :6; /* 15:10 Reserved */
3340#endif
3341 } hsf_ctrl;
3342 uint16_t regval;
3343};
3344
3345/* ICH8 Flash Region Access Permissions */
3346union ich8_hws_flash_regacc {
3347 struct ich8_flracc {
3348#ifdef E1000_BIG_ENDIAN
3349 uint32_t gmwag :8;
3350 uint32_t gmrag :8;
3351 uint32_t grwa :8;
3352 uint32_t grra :8;
3353#else
3354 uint32_t grra :8; /* 0:7 GbE region Read Access */
3355 uint32_t grwa :8; /* 8:15 GbE region Write Access */
3356 uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */
3357 uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */
3358#endif
3359 } hsf_flregacc;
3360 uint16_t regval;
3361};
3362
1da177e4
LT		 3363/* Miscellaneous PHY bit definitions. */
3364#define PHY_PREAMBLE 0xFFFFFFFF
3365#define PHY_SOF 0x01
3366#define PHY_OP_READ 0x02
3367#define PHY_OP_WRITE 0x01
3368#define PHY_TURNAROUND 0x02
3369#define PHY_PREAMBLE_SIZE 32
3370#define MII_CR_SPEED_1000 0x0040
3371#define MII_CR_SPEED_100 0x2000
3372#define MII_CR_SPEED_10 0x0000
3373#define E1000_PHY_ADDRESS 0x01
3374#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
3375#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
3376#define PHY_REVISION_MASK 0xFFFFFFF0
3377#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
3378#define REG4_SPEED_MASK 0x01E0
3379#define REG9_SPEED_MASK 0x0300
3380#define ADVERTISE_10_HALF 0x0001
3381#define ADVERTISE_10_FULL 0x0002
3382#define ADVERTISE_100_HALF 0x0004
3383#define ADVERTISE_100_FULL 0x0008
3384#define ADVERTISE_1000_HALF 0x0010
3385#define ADVERTISE_1000_FULL 0x0020
3386#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
3387#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
3388#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
3389
3390#endif /* _E1000_HW_H_ */
Linux 6.x block layer and io_uring tree(s)