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e1000: FIX: Don't limit descriptor size to 4kb for PCI-E adapters
[linux-2.6-block.git] / drivers / net / e1000 / e1000_hw.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
8fc897b0 33
1da177e4
LT		 34#include "e1000_hw.h"
35
35574764
NN		 36static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
37static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
38static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
39static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
40static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
41static void e1000_release_software_semaphore(struct e1000_hw *hw);
42
43static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
44static int32_t e1000_check_downshift(struct e1000_hw *hw);
45static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
46static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47static void e1000_clear_vfta(struct e1000_hw *hw);
48static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
49static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
50static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
51static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
52static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
53static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
54static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
55static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
56static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
57static int32_t e1000_get_software_flag(struct e1000_hw *hw);
58static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
59static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
60static int32_t e1000_id_led_init(struct e1000_hw *hw);
61static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
62static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
63static void e1000_init_rx_addrs(struct e1000_hw *hw);
09ae3e88 64static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
35574764
NN		 65static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
66static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
67static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
68static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
69static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
70static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
71static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
72static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
74static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
75static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
76static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
77static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
78static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
79static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
80static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
81static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
82static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
83static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
84static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
86static void e1000_release_software_flag(struct e1000_hw *hw);
87static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
88static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
89static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
90static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
91static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
92static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
1da177e4
LT		 93static int32_t e1000_set_phy_type(struct e1000_hw *hw);
94static void e1000_phy_init_script(struct e1000_hw *hw);
95static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
96static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
97static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
98static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
99static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
100static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
101static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
102static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
103 uint16_t count);
104static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
105static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
106static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
107 uint16_t words, uint16_t *data);
108static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
109 uint16_t offset, uint16_t words,
110 uint16_t *data);
111static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
112static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
113static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
114static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
115 uint16_t count);
116static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
117 uint16_t phy_data);
118static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
119 uint16_t *phy_data);
120static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
121static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
122static void e1000_release_eeprom(struct e1000_hw *hw);
123static void e1000_standby_eeprom(struct e1000_hw *hw);
1da177e4
LT		 124static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
125static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
126static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
2d7edb92
MC		 127static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
128static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
cd94dd0b
AK		 129static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
130 uint16_t duplex);
6418ecc6 131static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
1da177e4
LT		 132
133/* IGP cable length table */
134static const
135uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
136 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
137 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
138 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
139 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
140 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
141 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
142 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
143 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
144
2d7edb92
MC		 145static const
146uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
868d5309
MC		 147 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
148 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
149 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
150 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
151 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
152 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
153 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
154 104, 109, 114, 118, 121, 124};
2d7edb92 155
1da177e4
LT		 156/******************************************************************************
157 * Set the phy type member in the hw struct.
158 *
159 * hw - Struct containing variables accessed by shared code
160 *****************************************************************************/
35574764 161static int32_t
1da177e4
LT		 162e1000_set_phy_type(struct e1000_hw *hw)
163{
164 DEBUGFUNC("e1000_set_phy_type");
165
8fc897b0 166 if (hw->mac_type == e1000_undefined)
2d7edb92
MC		 167 return -E1000_ERR_PHY_TYPE;
168
8fc897b0 169 switch (hw->phy_id) {
1da177e4
LT		 170 case M88E1000_E_PHY_ID:
171 case M88E1000_I_PHY_ID:
172 case M88E1011_I_PHY_ID:
2d7edb92 173 case M88E1111_I_PHY_ID:
1da177e4
LT		 174 hw->phy_type = e1000_phy_m88;
175 break;
176 case IGP01E1000_I_PHY_ID:
8fc897b0
AK		 177 if (hw->mac_type == e1000_82541 ||
178 hw->mac_type == e1000_82541_rev_2 ||
179 hw->mac_type == e1000_82547 ||
180 hw->mac_type == e1000_82547_rev_2) {
1da177e4
LT		 181 hw->phy_type = e1000_phy_igp;
182 break;
183 }
cd94dd0b
AK		 184 case IGP03E1000_E_PHY_ID:
185 hw->phy_type = e1000_phy_igp_3;
186 break;
187 case IFE_E_PHY_ID:
188 case IFE_PLUS_E_PHY_ID:
189 case IFE_C_E_PHY_ID:
190 hw->phy_type = e1000_phy_ife;
191 break;
6418ecc6
JK		 192 case GG82563_E_PHY_ID:
193 if (hw->mac_type == e1000_80003es2lan) {
194 hw->phy_type = e1000_phy_gg82563;
195 break;
196 }
1da177e4
LT		 197 /* Fall Through */
198 default:
199 /* Should never have loaded on this device */
200 hw->phy_type = e1000_phy_undefined;
201 return -E1000_ERR_PHY_TYPE;
202 }
203
204 return E1000_SUCCESS;
205}
206
207/******************************************************************************
208 * IGP phy init script - initializes the GbE PHY
209 *
210 * hw - Struct containing variables accessed by shared code
211 *****************************************************************************/
212static void
213e1000_phy_init_script(struct e1000_hw *hw)
214{
215 uint32_t ret_val;
216 uint16_t phy_saved_data;
217
218 DEBUGFUNC("e1000_phy_init_script");
219
8fc897b0 220 if (hw->phy_init_script) {
f8ec4733 221 msleep(20);
1da177e4
LT		 222
223 /* Save off the current value of register 0x2F5B to be restored at
224 * the end of this routine. */
225 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
226
227 /* Disabled the PHY transmitter */
228 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
229
f8ec4733 230 msleep(20);
1da177e4
LT		 231
232 e1000_write_phy_reg(hw,0x0000,0x0140);
233
f8ec4733 234 msleep(5);
1da177e4 235
8fc897b0 236 switch (hw->mac_type) {
1da177e4
LT		 237 case e1000_82541:
238 case e1000_82547:
239 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
240
241 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
242
243 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
244
245 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
246
247 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
248
249 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
250
251 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
252
253 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
254
255 e1000_write_phy_reg(hw, 0x2010, 0x0008);
256 break;
257
258 case e1000_82541_rev_2:
259 case e1000_82547_rev_2:
260 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
261 break;
262 default:
263 break;
264 }
265
266 e1000_write_phy_reg(hw, 0x0000, 0x3300);
267
f8ec4733 268 msleep(20);
1da177e4
LT		 269
270 /* Now enable the transmitter */
271 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
272
8fc897b0 273 if (hw->mac_type == e1000_82547) {
1da177e4
LT		 274 uint16_t fused, fine, coarse;
275
276 /* Move to analog registers page */
277 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
278
8fc897b0 279 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1da177e4
LT		 280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
281
282 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
283 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
284
8fc897b0 285 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1da177e4
LT		 286 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
287 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
8fc897b0 288 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1da177e4
LT		 289 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
290
291 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
292 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
293 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
294
295 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
296 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
297 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
298 }
299 }
300 }
301}
302
303/******************************************************************************
304 * Set the mac type member in the hw struct.
305 *
306 * hw - Struct containing variables accessed by shared code
307 *****************************************************************************/
308int32_t
309e1000_set_mac_type(struct e1000_hw *hw)
310{
311 DEBUGFUNC("e1000_set_mac_type");
312
313 switch (hw->device_id) {
314 case E1000_DEV_ID_82542:
315 switch (hw->revision_id) {
316 case E1000_82542_2_0_REV_ID:
317 hw->mac_type = e1000_82542_rev2_0;
318 break;
319 case E1000_82542_2_1_REV_ID:
320 hw->mac_type = e1000_82542_rev2_1;
321 break;
322 default:
323 /* Invalid 82542 revision ID */
324 return -E1000_ERR_MAC_TYPE;
325 }
326 break;
327 case E1000_DEV_ID_82543GC_FIBER:
328 case E1000_DEV_ID_82543GC_COPPER:
329 hw->mac_type = e1000_82543;
330 break;
331 case E1000_DEV_ID_82544EI_COPPER:
332 case E1000_DEV_ID_82544EI_FIBER:
333 case E1000_DEV_ID_82544GC_COPPER:
334 case E1000_DEV_ID_82544GC_LOM:
335 hw->mac_type = e1000_82544;
336 break;
337 case E1000_DEV_ID_82540EM:
338 case E1000_DEV_ID_82540EM_LOM:
339 case E1000_DEV_ID_82540EP:
340 case E1000_DEV_ID_82540EP_LOM:
341 case E1000_DEV_ID_82540EP_LP:
342 hw->mac_type = e1000_82540;
343 break;
344 case E1000_DEV_ID_82545EM_COPPER:
345 case E1000_DEV_ID_82545EM_FIBER:
346 hw->mac_type = e1000_82545;
347 break;
348 case E1000_DEV_ID_82545GM_COPPER:
349 case E1000_DEV_ID_82545GM_FIBER:
350 case E1000_DEV_ID_82545GM_SERDES:
351 hw->mac_type = e1000_82545_rev_3;
352 break;
353 case E1000_DEV_ID_82546EB_COPPER:
354 case E1000_DEV_ID_82546EB_FIBER:
355 case E1000_DEV_ID_82546EB_QUAD_COPPER:
356 hw->mac_type = e1000_82546;
357 break;
358 case E1000_DEV_ID_82546GB_COPPER:
359 case E1000_DEV_ID_82546GB_FIBER:
360 case E1000_DEV_ID_82546GB_SERDES:
361 case E1000_DEV_ID_82546GB_PCIE:
b7ee49db
JK		 362 case E1000_DEV_ID_82546GB_QUAD_COPPER:
363 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1da177e4
LT		 364 hw->mac_type = e1000_82546_rev_3;
365 break;
366 case E1000_DEV_ID_82541EI:
367 case E1000_DEV_ID_82541EI_MOBILE:
cd94dd0b 368 case E1000_DEV_ID_82541ER_LOM:
1da177e4
LT		 369 hw->mac_type = e1000_82541;
370 break;
371 case E1000_DEV_ID_82541ER:
372 case E1000_DEV_ID_82541GI:
373 case E1000_DEV_ID_82541GI_LF:
374 case E1000_DEV_ID_82541GI_MOBILE:
375 hw->mac_type = e1000_82541_rev_2;
376 break;
377 case E1000_DEV_ID_82547EI:
cd94dd0b 378 case E1000_DEV_ID_82547EI_MOBILE:
1da177e4
LT		 379 hw->mac_type = e1000_82547;
380 break;
381 case E1000_DEV_ID_82547GI:
382 hw->mac_type = e1000_82547_rev_2;
383 break;
868d5309
MC		 384 case E1000_DEV_ID_82571EB_COPPER:
385 case E1000_DEV_ID_82571EB_FIBER:
386 case E1000_DEV_ID_82571EB_SERDES:
5881cde8 387 case E1000_DEV_ID_82571EB_QUAD_COPPER:
868d5309
MC		 388 hw->mac_type = e1000_82571;
389 break;
390 case E1000_DEV_ID_82572EI_COPPER:
391 case E1000_DEV_ID_82572EI_FIBER:
392 case E1000_DEV_ID_82572EI_SERDES:
cd94dd0b 393 case E1000_DEV_ID_82572EI:
868d5309
MC		 394 hw->mac_type = e1000_82572;
395 break;
2d7edb92
MC		 396 case E1000_DEV_ID_82573E:
397 case E1000_DEV_ID_82573E_IAMT:
868d5309 398 case E1000_DEV_ID_82573L:
2d7edb92
MC		 399 hw->mac_type = e1000_82573;
400 break;
cd94dd0b
AK		 401 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
402 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
6418ecc6
JK		 403 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
404 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
405 hw->mac_type = e1000_80003es2lan;
406 break;
cd94dd0b
AK		 407 case E1000_DEV_ID_ICH8_IGP_M_AMT:
408 case E1000_DEV_ID_ICH8_IGP_AMT:
409 case E1000_DEV_ID_ICH8_IGP_C:
410 case E1000_DEV_ID_ICH8_IFE:
411 case E1000_DEV_ID_ICH8_IGP_M:
412 hw->mac_type = e1000_ich8lan;
413 break;
1da177e4
LT		 414 default:
415 /* Should never have loaded on this device */
416 return -E1000_ERR_MAC_TYPE;
417 }
418
8fc897b0 419 switch (hw->mac_type) {
cd94dd0b
AK		 420 case e1000_ich8lan:
421 hw->swfwhw_semaphore_present = TRUE;
422 hw->asf_firmware_present = TRUE;
423 break;
6418ecc6
JK		 424 case e1000_80003es2lan:
425 hw->swfw_sync_present = TRUE;
426 /* fall through */
868d5309
MC		 427 case e1000_82571:
428 case e1000_82572:
2d7edb92
MC		 429 case e1000_82573:
430 hw->eeprom_semaphore_present = TRUE;
431 /* fall through */
1da177e4
LT		 432 case e1000_82541:
433 case e1000_82547:
434 case e1000_82541_rev_2:
435 case e1000_82547_rev_2:
436 hw->asf_firmware_present = TRUE;
437 break;
438 default:
439 break;
440 }
441
442 return E1000_SUCCESS;
443}
444
445/*****************************************************************************
446 * Set media type and TBI compatibility.
447 *
448 * hw - Struct containing variables accessed by shared code
449 * **************************************************************************/
450void
451e1000_set_media_type(struct e1000_hw *hw)
452{
453 uint32_t status;
454
455 DEBUGFUNC("e1000_set_media_type");
456
8fc897b0 457 if (hw->mac_type != e1000_82543) {
1da177e4
LT		 458 /* tbi_compatibility is only valid on 82543 */
459 hw->tbi_compatibility_en = FALSE;
460 }
461
462 switch (hw->device_id) {
463 case E1000_DEV_ID_82545GM_SERDES:
464 case E1000_DEV_ID_82546GB_SERDES:
868d5309
MC		 465 case E1000_DEV_ID_82571EB_SERDES:
466 case E1000_DEV_ID_82572EI_SERDES:
6418ecc6 467 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1da177e4
LT		 468 hw->media_type = e1000_media_type_internal_serdes;
469 break;
470 default:
3893d547
MC		 471 switch (hw->mac_type) {
472 case e1000_82542_rev2_0:
473 case e1000_82542_rev2_1:
474 hw->media_type = e1000_media_type_fiber;
475 break;
cd94dd0b 476 case e1000_ich8lan:
3893d547
MC		 477 case e1000_82573:
478 /* The STATUS_TBIMODE bit is reserved or reused for the this
479 * device.
480 */
481 hw->media_type = e1000_media_type_copper;
482 break;
483 default:
1da177e4 484 status = E1000_READ_REG(hw, STATUS);
3893d547 485 if (status & E1000_STATUS_TBIMODE) {
1da177e4
LT		 486 hw->media_type = e1000_media_type_fiber;
487 /* tbi_compatibility not valid on fiber */
488 hw->tbi_compatibility_en = FALSE;
489 } else {
490 hw->media_type = e1000_media_type_copper;
491 }
3893d547 492 break;
1da177e4
LT		 493 }
494 }
495}
496
497/******************************************************************************
498 * Reset the transmit and receive units; mask and clear all interrupts.
499 *
500 * hw - Struct containing variables accessed by shared code
501 *****************************************************************************/
502int32_t
503e1000_reset_hw(struct e1000_hw *hw)
504{
505 uint32_t ctrl;
506 uint32_t ctrl_ext;
507 uint32_t icr;
508 uint32_t manc;
509 uint32_t led_ctrl;
2d7edb92
MC		 510 uint32_t timeout;
511 uint32_t extcnf_ctrl;
512 int32_t ret_val;
1da177e4
LT		 513
514 DEBUGFUNC("e1000_reset_hw");
515
516 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
8fc897b0 517 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 518 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
519 e1000_pci_clear_mwi(hw);
520 }
521
8fc897b0 522 if (hw->bus_type == e1000_bus_type_pci_express) {
2d7edb92
MC		 523 /* Prevent the PCI-E bus from sticking if there is no TLP connection
524 * on the last TLP read/write transaction when MAC is reset.
525 */
8fc897b0 526 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
2d7edb92
MC		 527 DEBUGOUT("PCI-E Master disable polling has failed.\n");
528 }
529 }
530
1da177e4
LT		 531 /* Clear interrupt mask to stop board from generating interrupts */
532 DEBUGOUT("Masking off all interrupts\n");
533 E1000_WRITE_REG(hw, IMC, 0xffffffff);
534
535 /* Disable the Transmit and Receive units. Then delay to allow
536 * any pending transactions to complete before we hit the MAC with
537 * the global reset.
538 */
539 E1000_WRITE_REG(hw, RCTL, 0);
540 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
541 E1000_WRITE_FLUSH(hw);
542
543 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
544 hw->tbi_compatibility_on = FALSE;
545
546 /* Delay to allow any outstanding PCI transactions to complete before
547 * resetting the device
548 */
f8ec4733 549 msleep(10);
1da177e4
LT		 550
551 ctrl = E1000_READ_REG(hw, CTRL);
552
553 /* Must reset the PHY before resetting the MAC */
8fc897b0 554 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2d7edb92 555 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
f8ec4733 556 msleep(5);
1da177e4
LT		 557 }
558
2d7edb92
MC		 559 /* Must acquire the MDIO ownership before MAC reset.
560 * Ownership defaults to firmware after a reset. */
8fc897b0 561 if (hw->mac_type == e1000_82573) {
2d7edb92
MC		 562 timeout = 10;
563
564 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
565 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
566
567 do {
568 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
569 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
570
8fc897b0 571 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
2d7edb92
MC		 572 break;
573 else
574 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
575
f8ec4733 576 msleep(2);
2d7edb92 577 timeout--;
8fc897b0 578 } while (timeout);
2d7edb92
MC		 579 }
580
cd94dd0b
AK		 581 /* Workaround for ICH8 bit corruption issue in FIFO memory */
582 if (hw->mac_type == e1000_ich8lan) {
583 /* Set Tx and Rx buffer allocation to 8k apiece. */
584 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
585 /* Set Packet Buffer Size to 16k. */
586 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
587 }
588
1da177e4
LT		 589 /* Issue a global reset to the MAC. This will reset the chip's
590 * transmit, receive, DMA, and link units. It will not effect
591 * the current PCI configuration. The global reset bit is self-
592 * clearing, and should clear within a microsecond.
593 */
594 DEBUGOUT("Issuing a global reset to MAC\n");
595
8fc897b0 596 switch (hw->mac_type) {
1da177e4
LT		 597 case e1000_82544:
598 case e1000_82540:
599 case e1000_82545:
600 case e1000_82546:
601 case e1000_82541:
602 case e1000_82541_rev_2:
603 /* These controllers can't ack the 64-bit write when issuing the
604 * reset, so use IO-mapping as a workaround to issue the reset */
605 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
606 break;
607 case e1000_82545_rev_3:
608 case e1000_82546_rev_3:
609 /* Reset is performed on a shadow of the control register */
610 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
611 break;
cd94dd0b
AK		 612 case e1000_ich8lan:
613 if (!hw->phy_reset_disable &&
614 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
615 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
616 * at the same time to make sure the interface between
617 * MAC and the external PHY is reset.
618 */
619 ctrl |= E1000_CTRL_PHY_RST;
620 }
621
622 e1000_get_software_flag(hw);
623 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
f8ec4733 624 msleep(5);
cd94dd0b 625 break;
1da177e4
LT		 626 default:
627 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
628 break;
629 }
630
631 /* After MAC reset, force reload of EEPROM to restore power-on settings to
632 * device. Later controllers reload the EEPROM automatically, so just wait
633 * for reload to complete.
634 */
8fc897b0 635 switch (hw->mac_type) {
1da177e4
LT		 636 case e1000_82542_rev2_0:
637 case e1000_82542_rev2_1:
638 case e1000_82543:
639 case e1000_82544:
640 /* Wait for reset to complete */
641 udelay(10);
642 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
643 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
644 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
645 E1000_WRITE_FLUSH(hw);
646 /* Wait for EEPROM reload */
f8ec4733 647 msleep(2);
1da177e4
LT		 648 break;
649 case e1000_82541:
650 case e1000_82541_rev_2:
651 case e1000_82547:
652 case e1000_82547_rev_2:
653 /* Wait for EEPROM reload */
f8ec4733 654 msleep(20);
1da177e4 655 break;
2d7edb92 656 case e1000_82573:
fd803241
JK		 657 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
658 udelay(10);
659 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
660 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
661 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
662 E1000_WRITE_FLUSH(hw);
663 }
2d7edb92 664 /* fall through */
2a88c173
JK		 665 default:
666 /* Auto read done will delay 5ms or poll based on mac type */
2d7edb92 667 ret_val = e1000_get_auto_rd_done(hw);
8fc897b0 668 if (ret_val)
2d7edb92
MC		 669 return ret_val;
670 break;
1da177e4
LT		 671 }
672
673 /* Disable HW ARPs on ASF enabled adapters */
8fc897b0 674 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
1da177e4
LT		 675 manc = E1000_READ_REG(hw, MANC);
676 manc &= ~(E1000_MANC_ARP_EN);
677 E1000_WRITE_REG(hw, MANC, manc);
678 }
679
8fc897b0 680 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1da177e4
LT		 681 e1000_phy_init_script(hw);
682
683 /* Configure activity LED after PHY reset */
684 led_ctrl = E1000_READ_REG(hw, LEDCTL);
685 led_ctrl &= IGP_ACTIVITY_LED_MASK;
686 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
687 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
688 }
689
690 /* Clear interrupt mask to stop board from generating interrupts */
691 DEBUGOUT("Masking off all interrupts\n");
692 E1000_WRITE_REG(hw, IMC, 0xffffffff);
693
694 /* Clear any pending interrupt events. */
695 icr = E1000_READ_REG(hw, ICR);
696
697 /* If MWI was previously enabled, reenable it. */
8fc897b0 698 if (hw->mac_type == e1000_82542_rev2_0) {
f8ec4733 699 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 700 e1000_pci_set_mwi(hw);
701 }
702
cd94dd0b
AK		 703 if (hw->mac_type == e1000_ich8lan) {
704 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
705 kab |= E1000_KABGTXD_BGSQLBIAS;
706 E1000_WRITE_REG(hw, KABGTXD, kab);
707 }
708
1da177e4
LT		 709 return E1000_SUCCESS;
710}
711
09ae3e88
JK		 712/******************************************************************************
713 *
714 * Initialize a number of hardware-dependent bits
715 *
716 * hw: Struct containing variables accessed by shared code
717 *
718 * This function contains hardware limitation workarounds for PCI-E adapters
719 *
720 *****************************************************************************/
721static void
722e1000_initialize_hardware_bits(struct e1000_hw *hw)
723{
724 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
725 /* Settings common to all PCI-express silicon */
726 uint32_t reg_ctrl, reg_ctrl_ext;
727 uint32_t reg_tarc0, reg_tarc1;
728 uint32_t reg_tctl;
729 uint32_t reg_txdctl, reg_txdctl1;
730
731 /* link autonegotiation/sync workarounds */
732 reg_tarc0 = E1000_READ_REG(hw, TARC0);
733 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
734
735 /* Enable not-done TX descriptor counting */
736 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
737 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
738 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
739 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
740 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
741 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
742
743 switch (hw->mac_type) {
744 case e1000_82571:
745 case e1000_82572:
746 /* Clear PHY TX compatible mode bits */
747 reg_tarc1 = E1000_READ_REG(hw, TARC1);
748 reg_tarc1 &= ~((1 << 30)|(1 << 29));
749
750 /* link autonegotiation/sync workarounds */
751 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
752
753 /* TX ring control fixes */
754 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
755
756 /* Multiple read bit is reversed polarity */
757 reg_tctl = E1000_READ_REG(hw, TCTL);
758 if (reg_tctl & E1000_TCTL_MULR)
759 reg_tarc1 &= ~(1 << 28);
760 else
761 reg_tarc1 |= (1 << 28);
762
763 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
764 break;
765 case e1000_82573:
766 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
767 reg_ctrl_ext &= ~(1 << 23);
768 reg_ctrl_ext |= (1 << 22);
769
770 /* TX byte count fix */
771 reg_ctrl = E1000_READ_REG(hw, CTRL);
772 reg_ctrl &= ~(1 << 29);
773
774 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
775 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
776 break;
777 case e1000_80003es2lan:
778 /* improve small packet performace for fiber/serdes */
779 if ((hw->media_type == e1000_media_type_fiber) ||
780 (hw->media_type == e1000_media_type_internal_serdes)) {
781 reg_tarc0 &= ~(1 << 20);
782 }
783
784 /* Multiple read bit is reversed polarity */
785 reg_tctl = E1000_READ_REG(hw, TCTL);
786 reg_tarc1 = E1000_READ_REG(hw, TARC1);
787 if (reg_tctl & E1000_TCTL_MULR)
788 reg_tarc1 &= ~(1 << 28);
789 else
790 reg_tarc1 |= (1 << 28);
791
792 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
793 break;
794 case e1000_ich8lan:
795 /* Reduce concurrent DMA requests to 3 from 4 */
796 if ((hw->revision_id < 3) ||
797 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
798 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
799 reg_tarc0 |= ((1 << 29)|(1 << 28));
800
801 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
802 reg_ctrl_ext |= (1 << 22);
803 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
804
805 /* workaround TX hang with TSO=on */
806 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
807
808 /* Multiple read bit is reversed polarity */
809 reg_tctl = E1000_READ_REG(hw, TCTL);
810 reg_tarc1 = E1000_READ_REG(hw, TARC1);
811 if (reg_tctl & E1000_TCTL_MULR)
812 reg_tarc1 &= ~(1 << 28);
813 else
814 reg_tarc1 |= (1 << 28);
815
816 /* workaround TX hang with TSO=on */
817 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
818
819 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
820 break;
821 default:
822 break;
823 }
824
825 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
826 }
827}
828
1da177e4
LT		 829/******************************************************************************
830 * Performs basic configuration of the adapter.
831 *
832 * hw - Struct containing variables accessed by shared code
833 *
834 * Assumes that the controller has previously been reset and is in a
835 * post-reset uninitialized state. Initializes the receive address registers,
836 * multicast table, and VLAN filter table. Calls routines to setup link
837 * configuration and flow control settings. Clears all on-chip counters. Leaves
838 * the transmit and receive units disabled and uninitialized.
839 *****************************************************************************/
840int32_t
841e1000_init_hw(struct e1000_hw *hw)
842{
843 uint32_t ctrl;
844 uint32_t i;
845 int32_t ret_val;
846 uint16_t pcix_cmd_word;
847 uint16_t pcix_stat_hi_word;
848 uint16_t cmd_mmrbc;
849 uint16_t stat_mmrbc;
2d7edb92 850 uint32_t mta_size;
6418ecc6 851 uint32_t reg_data;
b7ee49db 852 uint32_t ctrl_ext;
2d7edb92 853
1da177e4
LT		 854 DEBUGFUNC("e1000_init_hw");
855
7820d428 856 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
09ae3e88
JK		 857 if ((hw->mac_type == e1000_ich8lan) &&
858 ((hw->revision_id < 3) ||
859 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
860 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
861 reg_data = E1000_READ_REG(hw, STATUS);
862 reg_data &= ~0x80000000;
863 E1000_WRITE_REG(hw, STATUS, reg_data);
7820d428
JK		 864 }
865
1da177e4
LT		 866 /* Initialize Identification LED */
867 ret_val = e1000_id_led_init(hw);
8fc897b0 868 if (ret_val) {
1da177e4
LT		 869 DEBUGOUT("Error Initializing Identification LED\n");
870 return ret_val;
871 }
872
873 /* Set the media type and TBI compatibility */
874 e1000_set_media_type(hw);
875
09ae3e88
JK		 876 /* Must be called after e1000_set_media_type because media_type is used */
877 e1000_initialize_hardware_bits(hw);
878
1da177e4
LT		 879 /* Disabling VLAN filtering. */
880 DEBUGOUT("Initializing the IEEE VLAN\n");
cd94dd0b
AK		 881 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
882 if (hw->mac_type != e1000_ich8lan) {
883 if (hw->mac_type < e1000_82545_rev_3)
884 E1000_WRITE_REG(hw, VET, 0);
885 e1000_clear_vfta(hw);
886 }
1da177e4
LT		 887
888 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
8fc897b0 889 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 890 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
891 e1000_pci_clear_mwi(hw);
892 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
893 E1000_WRITE_FLUSH(hw);
f8ec4733 894 msleep(5);
1da177e4
LT		 895 }
896
897 /* Setup the receive address. This involves initializing all of the Receive
898 * Address Registers (RARs 0 - 15).
899 */
900 e1000_init_rx_addrs(hw);
901
902 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
8fc897b0 903 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 904 E1000_WRITE_REG(hw, RCTL, 0);
905 E1000_WRITE_FLUSH(hw);
f8ec4733
JG		 906 msleep(1);
907 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 908 e1000_pci_set_mwi(hw);
909 }
910
911 /* Zero out the Multicast HASH table */
912 DEBUGOUT("Zeroing the MTA\n");
2d7edb92 913 mta_size = E1000_MC_TBL_SIZE;
cd94dd0b
AK		 914 if (hw->mac_type == e1000_ich8lan)
915 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
8fc897b0 916 for (i = 0; i < mta_size; i++) {
1da177e4 917 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 918 /* use write flush to prevent Memory Write Block (MWB) from
919 * occuring when accessing our register space */
920 E1000_WRITE_FLUSH(hw);
921 }
1da177e4
LT		 922
923 /* Set the PCI priority bit correctly in the CTRL register. This
924 * determines if the adapter gives priority to receives, or if it
2d7edb92
MC		 925 * gives equal priority to transmits and receives. Valid only on
926 * 82542 and 82543 silicon.
1da177e4 927 */
8fc897b0 928 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1da177e4
LT		 929 ctrl = E1000_READ_REG(hw, CTRL);
930 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
931 }
932
8fc897b0 933 switch (hw->mac_type) {
1da177e4
LT		 934 case e1000_82545_rev_3:
935 case e1000_82546_rev_3:
936 break;
937 default:
938 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
8fc897b0 939 if (hw->bus_type == e1000_bus_type_pcix) {
1da177e4
LT		 940 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
941 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
942 &pcix_stat_hi_word);
943 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
944 PCIX_COMMAND_MMRBC_SHIFT;
945 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
946 PCIX_STATUS_HI_MMRBC_SHIFT;
8fc897b0 947 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1da177e4 948 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
8fc897b0 949 if (cmd_mmrbc > stat_mmrbc) {
1da177e4
LT		 950 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
951 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
952 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
953 &pcix_cmd_word);
954 }
955 }
956 break;
957 }
958
cd94dd0b
AK		 959 /* More time needed for PHY to initialize */
960 if (hw->mac_type == e1000_ich8lan)
f8ec4733 961 msleep(15);
cd94dd0b 962
1da177e4
LT		 963 /* Call a subroutine to configure the link and setup flow control. */
964 ret_val = e1000_setup_link(hw);
965
966 /* Set the transmit descriptor write-back policy */
8fc897b0 967 if (hw->mac_type > e1000_82544) {
1da177e4
LT		 968 ctrl = E1000_READ_REG(hw, TXDCTL);
969 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
970 E1000_WRITE_REG(hw, TXDCTL, ctrl);
971 }
972
2d7edb92 973 if (hw->mac_type == e1000_82573) {
76c224bc 974 e1000_enable_tx_pkt_filtering(hw);
2d7edb92
MC		 975 }
976
868d5309
MC		 977 switch (hw->mac_type) {
978 default:
979 break;
6418ecc6
JK		 980 case e1000_80003es2lan:
981 /* Enable retransmit on late collisions */
982 reg_data = E1000_READ_REG(hw, TCTL);
983 reg_data |= E1000_TCTL_RTLC;
984 E1000_WRITE_REG(hw, TCTL, reg_data);
985
986 /* Configure Gigabit Carry Extend Padding */
987 reg_data = E1000_READ_REG(hw, TCTL_EXT);
988 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
989 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
990 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
991
992 /* Configure Transmit Inter-Packet Gap */
993 reg_data = E1000_READ_REG(hw, TIPG);
994 reg_data &= ~E1000_TIPG_IPGT_MASK;
995 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
996 E1000_WRITE_REG(hw, TIPG, reg_data);
997
998 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
999 reg_data &= ~0x00100000;
1000 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1001 /* Fall through */
868d5309 1002 case e1000_82571:
a7990ba6 1003 case e1000_82572:
cd94dd0b 1004 case e1000_ich8lan:
868d5309 1005 ctrl = E1000_READ_REG(hw, TXDCTL1);
6418ecc6 1006 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
868d5309
MC		 1007 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1008 break;
1009 }
1010
1011
868d5309
MC		 1012 if (hw->mac_type == e1000_82573) {
1013 uint32_t gcr = E1000_READ_REG(hw, GCR);
1014 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1015 E1000_WRITE_REG(hw, GCR, gcr);
1016 }
2d7edb92 1017
1da177e4
LT		 1018 /* Clear all of the statistics registers (clear on read). It is
1019 * important that we do this after we have tried to establish link
1020 * because the symbol error count will increment wildly if there
1021 * is no link.
1022 */
1023 e1000_clear_hw_cntrs(hw);
1024
cd94dd0b
AK		 1025 /* ICH8 No-snoop bits are opposite polarity.
1026 * Set to snoop by default after reset. */
1027 if (hw->mac_type == e1000_ich8lan)
1028 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1029
b7ee49db
JK		 1030 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1031 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1032 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1033 /* Relaxed ordering must be disabled to avoid a parity
1034 * error crash in a PCI slot. */
1035 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1036 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1037 }
1038
1da177e4
LT		 1039 return ret_val;
1040}
1041
1042/******************************************************************************
1043 * Adjust SERDES output amplitude based on EEPROM setting.
1044 *
1045 * hw - Struct containing variables accessed by shared code.
1046 *****************************************************************************/
1047static int32_t
1048e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1049{
1050 uint16_t eeprom_data;
1051 int32_t ret_val;
1052
1053 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1054
8fc897b0 1055 if (hw->media_type != e1000_media_type_internal_serdes)
1da177e4
LT		 1056 return E1000_SUCCESS;
1057
8fc897b0 1058 switch (hw->mac_type) {
1da177e4
LT		 1059 case e1000_82545_rev_3:
1060 case e1000_82546_rev_3:
1061 break;
1062 default:
1063 return E1000_SUCCESS;
1064 }
1065
1066 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1067 if (ret_val) {
1068 return ret_val;
1069 }
1070
8fc897b0 1071 if (eeprom_data != EEPROM_RESERVED_WORD) {
1da177e4 1072 /* Adjust SERDES output amplitude only. */
76c224bc 1073 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1da177e4 1074 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
8fc897b0 1075 if (ret_val)
1da177e4
LT		 1076 return ret_val;
1077 }
1078
1079 return E1000_SUCCESS;
1080}
1081
1082/******************************************************************************
1083 * Configures flow control and link settings.
1084 *
1085 * hw - Struct containing variables accessed by shared code
1086 *
1087 * Determines which flow control settings to use. Calls the apropriate media-
1088 * specific link configuration function. Configures the flow control settings.
1089 * Assuming the adapter has a valid link partner, a valid link should be
1090 * established. Assumes the hardware has previously been reset and the
1091 * transmitter and receiver are not enabled.
1092 *****************************************************************************/
1093int32_t
1094e1000_setup_link(struct e1000_hw *hw)
1095{
1096 uint32_t ctrl_ext;
1097 int32_t ret_val;
1098 uint16_t eeprom_data;
1099
1100 DEBUGFUNC("e1000_setup_link");
1101
526f9957
JK		 1102 /* In the case of the phy reset being blocked, we already have a link.
1103 * We do not have to set it up again. */
1104 if (e1000_check_phy_reset_block(hw))
1105 return E1000_SUCCESS;
1106
1da177e4
LT		 1107 /* Read and store word 0x0F of the EEPROM. This word contains bits
1108 * that determine the hardware's default PAUSE (flow control) mode,
1109 * a bit that determines whether the HW defaults to enabling or
1110 * disabling auto-negotiation, and the direction of the
1111 * SW defined pins. If there is no SW over-ride of the flow
1112 * control setting, then the variable hw->fc will
1113 * be initialized based on a value in the EEPROM.
1114 */
11241b10 1115 if (hw->fc == E1000_FC_DEFAULT) {
fd803241 1116 switch (hw->mac_type) {
cd94dd0b 1117 case e1000_ich8lan:
fd803241 1118 case e1000_82573:
11241b10 1119 hw->fc = E1000_FC_FULL;
fd803241
JK		 1120 break;
1121 default:
1122 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1123 1, &eeprom_data);
1124 if (ret_val) {
1125 DEBUGOUT("EEPROM Read Error\n");
1126 return -E1000_ERR_EEPROM;
1127 }
1128 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
11241b10 1129 hw->fc = E1000_FC_NONE;
fd803241
JK		 1130 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1131 EEPROM_WORD0F_ASM_DIR)
11241b10 1132 hw->fc = E1000_FC_TX_PAUSE;
fd803241 1133 else
11241b10 1134 hw->fc = E1000_FC_FULL;
fd803241
JK		 1135 break;
1136 }
1da177e4
LT		 1137 }
1138
1139 /* We want to save off the original Flow Control configuration just
1140 * in case we get disconnected and then reconnected into a different
1141 * hub or switch with different Flow Control capabilities.
1142 */
8fc897b0 1143 if (hw->mac_type == e1000_82542_rev2_0)
11241b10 1144 hw->fc &= (~E1000_FC_TX_PAUSE);
1da177e4 1145
8fc897b0 1146 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
11241b10 1147 hw->fc &= (~E1000_FC_RX_PAUSE);
1da177e4
LT		 1148
1149 hw->original_fc = hw->fc;
1150
1151 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1152
1153 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1154 * polarity value for the SW controlled pins, and setup the
1155 * Extended Device Control reg with that info.
1156 * This is needed because one of the SW controlled pins is used for
1157 * signal detection. So this should be done before e1000_setup_pcs_link()
1158 * or e1000_phy_setup() is called.
1159 */
497fce5e 1160 if (hw->mac_type == e1000_82543) {
8fc897b0
AK		 1161 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1162 1, &eeprom_data);
1163 if (ret_val) {
1164 DEBUGOUT("EEPROM Read Error\n");
1165 return -E1000_ERR_EEPROM;
1166 }
1da177e4
LT		 1167 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1168 SWDPIO__EXT_SHIFT);
1169 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1170 }
1171
1172 /* Call the necessary subroutine to configure the link. */
1173 ret_val = (hw->media_type == e1000_media_type_copper) ?
1174 e1000_setup_copper_link(hw) :
1175 e1000_setup_fiber_serdes_link(hw);
1176
1177 /* Initialize the flow control address, type, and PAUSE timer
1178 * registers to their default values. This is done even if flow
1179 * control is disabled, because it does not hurt anything to
1180 * initialize these registers.
1181 */
1182 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1183
cd94dd0b
AK		 1184 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1185 if (hw->mac_type != e1000_ich8lan) {
1186 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1187 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1188 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1189 }
2d7edb92 1190
1da177e4
LT		 1191 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1192
1193 /* Set the flow control receive threshold registers. Normally,
1194 * these registers will be set to a default threshold that may be
1195 * adjusted later by the driver's runtime code. However, if the
1196 * ability to transmit pause frames in not enabled, then these
1197 * registers will be set to 0.
1198 */
11241b10 1199 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1da177e4
LT		 1200 E1000_WRITE_REG(hw, FCRTL, 0);
1201 E1000_WRITE_REG(hw, FCRTH, 0);
1202 } else {
1203 /* We need to set up the Receive Threshold high and low water marks
1204 * as well as (optionally) enabling the transmission of XON frames.
1205 */
8fc897b0 1206 if (hw->fc_send_xon) {
1da177e4
LT		 1207 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1208 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1209 } else {
1210 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1211 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1212 }
1213 }
1214 return ret_val;
1215}
1216
1217/******************************************************************************
1218 * Sets up link for a fiber based or serdes based adapter
1219 *
1220 * hw - Struct containing variables accessed by shared code
1221 *
1222 * Manipulates Physical Coding Sublayer functions in order to configure
1223 * link. Assumes the hardware has been previously reset and the transmitter
1224 * and receiver are not enabled.
1225 *****************************************************************************/
1226static int32_t
1227e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1228{
1229 uint32_t ctrl;
1230 uint32_t status;
1231 uint32_t txcw = 0;
1232 uint32_t i;
1233 uint32_t signal = 0;
1234 int32_t ret_val;
1235
1236 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1237
868d5309
MC		 1238 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1239 * until explicitly turned off or a power cycle is performed. A read to
1240 * the register does not indicate its status. Therefore, we ensure
1241 * loopback mode is disabled during initialization.
1242 */
1243 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1244 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1245
09ae3e88 1246 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1da177e4
LT		 1247 * set when the optics detect a signal. On older adapters, it will be
1248 * cleared when there is a signal. This applies to fiber media only.
09ae3e88
JK		 1249 * If we're on serdes media, adjust the output amplitude to value
1250 * set in the EEPROM.
1da177e4
LT		 1251 */
1252 ctrl = E1000_READ_REG(hw, CTRL);
8fc897b0 1253 if (hw->media_type == e1000_media_type_fiber)
1da177e4
LT		 1254 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1255
1256 ret_val = e1000_adjust_serdes_amplitude(hw);
8fc897b0 1257 if (ret_val)
1da177e4
LT		 1258 return ret_val;
1259
1260 /* Take the link out of reset */
1261 ctrl &= ~(E1000_CTRL_LRST);
1262
1263 /* Adjust VCO speed to improve BER performance */
1264 ret_val = e1000_set_vco_speed(hw);
8fc897b0 1265 if (ret_val)
1da177e4
LT		 1266 return ret_val;
1267
1268 e1000_config_collision_dist(hw);
1269
1270 /* Check for a software override of the flow control settings, and setup
1271 * the device accordingly. If auto-negotiation is enabled, then software
1272 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1273 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1274 * auto-negotiation is disabled, then software will have to manually
1275 * configure the two flow control enable bits in the CTRL register.
1276 *
1277 * The possible values of the "fc" parameter are:
1278 * 0: Flow control is completely disabled
1279 * 1: Rx flow control is enabled (we can receive pause frames, but
1280 * not send pause frames).
1281 * 2: Tx flow control is enabled (we can send pause frames but we do
1282 * not support receiving pause frames).
1283 * 3: Both Rx and TX flow control (symmetric) are enabled.
1284 */
1285 switch (hw->fc) {
11241b10 1286 case E1000_FC_NONE:
1da177e4
LT		 1287 /* Flow control is completely disabled by a software over-ride. */
1288 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1289 break;
11241b10 1290 case E1000_FC_RX_PAUSE:
1da177e4
LT		 1291 /* RX Flow control is enabled and TX Flow control is disabled by a
1292 * software over-ride. Since there really isn't a way to advertise
1293 * that we are capable of RX Pause ONLY, we will advertise that we
1294 * support both symmetric and asymmetric RX PAUSE. Later, we will
1295 * disable the adapter's ability to send PAUSE frames.
1296 */
1297 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1298 break;
11241b10 1299 case E1000_FC_TX_PAUSE:
1da177e4
LT		 1300 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1301 * software over-ride.
1302 */
1303 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1304 break;
11241b10 1305 case E1000_FC_FULL:
1da177e4
LT		 1306 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1307 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1308 break;
1309 default:
1310 DEBUGOUT("Flow control param set incorrectly\n");
1311 return -E1000_ERR_CONFIG;
1312 break;
1313 }
1314
1315 /* Since auto-negotiation is enabled, take the link out of reset (the link
1316 * will be in reset, because we previously reset the chip). This will
1317 * restart auto-negotiation. If auto-neogtiation is successful then the
1318 * link-up status bit will be set and the flow control enable bits (RFCE
1319 * and TFCE) will be set according to their negotiated value.
1320 */
1321 DEBUGOUT("Auto-negotiation enabled\n");
1322
1323 E1000_WRITE_REG(hw, TXCW, txcw);
1324 E1000_WRITE_REG(hw, CTRL, ctrl);
1325 E1000_WRITE_FLUSH(hw);
1326
1327 hw->txcw = txcw;
f8ec4733 1328 msleep(1);
1da177e4
LT		 1329
1330 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1331 * indication in the Device Status Register. Time-out if a link isn't
1332 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1333 * less than 500 milliseconds even if the other end is doing it in SW).
1334 * For internal serdes, we just assume a signal is present, then poll.
1335 */
8fc897b0 1336 if (hw->media_type == e1000_media_type_internal_serdes ||
1da177e4
LT		 1337 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1338 DEBUGOUT("Looking for Link\n");
8fc897b0 1339 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
f8ec4733 1340 msleep(10);
1da177e4 1341 status = E1000_READ_REG(hw, STATUS);
8fc897b0 1342 if (status & E1000_STATUS_LU) break;
1da177e4 1343 }
8fc897b0 1344 if (i == (LINK_UP_TIMEOUT / 10)) {
1da177e4
LT		 1345 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1346 hw->autoneg_failed = 1;
1347 /* AutoNeg failed to achieve a link, so we'll call
1348 * e1000_check_for_link. This routine will force the link up if
1349 * we detect a signal. This will allow us to communicate with
1350 * non-autonegotiating link partners.
1351 */
1352 ret_val = e1000_check_for_link(hw);
8fc897b0 1353 if (ret_val) {
1da177e4
LT		 1354 DEBUGOUT("Error while checking for link\n");
1355 return ret_val;
1356 }
1357 hw->autoneg_failed = 0;
1358 } else {
1359 hw->autoneg_failed = 0;
1360 DEBUGOUT("Valid Link Found\n");
1361 }
1362 } else {
1363 DEBUGOUT("No Signal Detected\n");
1364 }
1365 return E1000_SUCCESS;
1366}
1367
1368/******************************************************************************
2d7edb92 1369* Make sure we have a valid PHY and change PHY mode before link setup.
1da177e4
LT		 1370*
1371* hw - Struct containing variables accessed by shared code
1372******************************************************************************/
1373static int32_t
2d7edb92 1374e1000_copper_link_preconfig(struct e1000_hw *hw)
1da177e4
LT		 1375{
1376 uint32_t ctrl;
1da177e4 1377 int32_t ret_val;
1da177e4
LT		 1378 uint16_t phy_data;
1379
2d7edb92 1380 DEBUGFUNC("e1000_copper_link_preconfig");
1da177e4
LT		 1381
1382 ctrl = E1000_READ_REG(hw, CTRL);
1383 /* With 82543, we need to force speed and duplex on the MAC equal to what
1384 * the PHY speed and duplex configuration is. In addition, we need to
1385 * perform a hardware reset on the PHY to take it out of reset.
1386 */
8fc897b0 1387 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 1388 ctrl |= E1000_CTRL_SLU;
1389 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1390 E1000_WRITE_REG(hw, CTRL, ctrl);
1391 } else {
1392 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1393 E1000_WRITE_REG(hw, CTRL, ctrl);
2d7edb92 1394 ret_val = e1000_phy_hw_reset(hw);
8fc897b0 1395 if (ret_val)
2d7edb92 1396 return ret_val;
1da177e4
LT		 1397 }
1398
1399 /* Make sure we have a valid PHY */
1400 ret_val = e1000_detect_gig_phy(hw);
8fc897b0 1401 if (ret_val) {
1da177e4
LT		 1402 DEBUGOUT("Error, did not detect valid phy.\n");
1403 return ret_val;
1404 }
1405 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1406
1407 /* Set PHY to class A mode (if necessary) */
1408 ret_val = e1000_set_phy_mode(hw);
8fc897b0 1409 if (ret_val)
1da177e4
LT		 1410 return ret_val;
1411
8fc897b0 1412 if ((hw->mac_type == e1000_82545_rev_3) ||
1da177e4
LT		 1413 (hw->mac_type == e1000_82546_rev_3)) {
1414 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1415 phy_data |= 0x00000008;
1416 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1417 }
1418
8fc897b0
AK		 1419 if (hw->mac_type <= e1000_82543 ||
1420 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1421 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1da177e4
LT		 1422 hw->phy_reset_disable = FALSE;
1423
2d7edb92
MC		 1424 return E1000_SUCCESS;
1425}
1da177e4 1426
1da177e4 1427
2d7edb92
MC		 1428/********************************************************************
1429* Copper link setup for e1000_phy_igp series.
1430*
1431* hw - Struct containing variables accessed by shared code
1432*********************************************************************/
1433static int32_t
1434e1000_copper_link_igp_setup(struct e1000_hw *hw)
1435{
1436 uint32_t led_ctrl;
1437 int32_t ret_val;
1438 uint16_t phy_data;
1da177e4 1439
2d7edb92 1440 DEBUGFUNC("e1000_copper_link_igp_setup");
1da177e4 1441
2d7edb92
MC		 1442 if (hw->phy_reset_disable)
1443 return E1000_SUCCESS;
76c224bc 1444
2d7edb92
MC		 1445 ret_val = e1000_phy_reset(hw);
1446 if (ret_val) {
1447 DEBUGOUT("Error Resetting the PHY\n");
1448 return ret_val;
1449 }
1da177e4 1450
8fc897b0 1451 /* Wait 15ms for MAC to configure PHY from eeprom settings */
f8ec4733 1452 msleep(15);
cd94dd0b 1453 if (hw->mac_type != e1000_ich8lan) {
2d7edb92
MC		 1454 /* Configure activity LED after PHY reset */
1455 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1456 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1457 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1458 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
cd94dd0b 1459 }
1da177e4 1460
c9c1b834
JK		 1461 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1462 if (hw->phy_type == e1000_phy_igp) {
1463 /* disable lplu d3 during driver init */
1464 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1465 if (ret_val) {
1466 DEBUGOUT("Error Disabling LPLU D3\n");
1467 return ret_val;
1468 }
2d7edb92 1469 }
1da177e4 1470
2d7edb92
MC		 1471 /* disable lplu d0 during driver init */
1472 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1473 if (ret_val) {
1474 DEBUGOUT("Error Disabling LPLU D0\n");
1475 return ret_val;
1476 }
1477 /* Configure mdi-mdix settings */
1478 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1479 if (ret_val)
1480 return ret_val;
1da177e4 1481
2d7edb92
MC		 1482 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1483 hw->dsp_config_state = e1000_dsp_config_disabled;
1484 /* Force MDI for earlier revs of the IGP PHY */
1485 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1486 hw->mdix = 1;
1da177e4 1487
2d7edb92
MC		 1488 } else {
1489 hw->dsp_config_state = e1000_dsp_config_enabled;
1490 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1da177e4 1491
2d7edb92
MC		 1492 switch (hw->mdix) {
1493 case 1:
1494 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1495 break;
1496 case 2:
1497 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1498 break;
1499 case 0:
1500 default:
1501 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1502 break;
1503 }
1504 }
1505 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
8fc897b0 1506 if (ret_val)
2d7edb92 1507 return ret_val;
1da177e4 1508
2d7edb92 1509 /* set auto-master slave resolution settings */
8fc897b0 1510 if (hw->autoneg) {
2d7edb92 1511 e1000_ms_type phy_ms_setting = hw->master_slave;
1da177e4 1512
8fc897b0 1513 if (hw->ffe_config_state == e1000_ffe_config_active)
2d7edb92 1514 hw->ffe_config_state = e1000_ffe_config_enabled;
1da177e4 1515
8fc897b0 1516 if (hw->dsp_config_state == e1000_dsp_config_activated)
2d7edb92 1517 hw->dsp_config_state = e1000_dsp_config_enabled;
1da177e4 1518
2d7edb92
MC		 1519 /* when autonegotiation advertisment is only 1000Mbps then we
1520 * should disable SmartSpeed and enable Auto MasterSlave
1521 * resolution as hardware default. */
8fc897b0 1522 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2d7edb92 1523 /* Disable SmartSpeed */
8fc897b0
AK		 1524 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1525 &phy_data);
1526 if (ret_val)
1da177e4 1527 return ret_val;
2d7edb92 1528 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
8fc897b0
AK		 1529 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1530 phy_data);
1531 if (ret_val)
1da177e4 1532 return ret_val;
2d7edb92
MC		 1533 /* Set auto Master/Slave resolution process */
1534 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
8fc897b0 1535 if (ret_val)
2d7edb92
MC		 1536 return ret_val;
1537 phy_data &= ~CR_1000T_MS_ENABLE;
1538 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
8fc897b0 1539 if (ret_val)
2d7edb92
MC		 1540 return ret_val;
1541 }
1da177e4 1542
2d7edb92 1543 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
8fc897b0 1544 if (ret_val)
2d7edb92 1545 return ret_val;
1da177e4 1546
2d7edb92
MC		 1547 /* load defaults for future use */
1548 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1549 ((phy_data & CR_1000T_MS_VALUE) ?
1550 e1000_ms_force_master :
1551 e1000_ms_force_slave) :
1552 e1000_ms_auto;
1da177e4 1553
2d7edb92
MC		 1554 switch (phy_ms_setting) {
1555 case e1000_ms_force_master:
1556 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1557 break;
1558 case e1000_ms_force_slave:
1559 phy_data |= CR_1000T_MS_ENABLE;
1560 phy_data &= ~(CR_1000T_MS_VALUE);
1561 break;
1562 case e1000_ms_auto:
1563 phy_data &= ~CR_1000T_MS_ENABLE;
1564 default:
1565 break;
1566 }
1567 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
8fc897b0 1568 if (ret_val)
2d7edb92 1569 return ret_val;
2b02893e 1570 }
1da177e4 1571
2b02893e 1572 return E1000_SUCCESS;
2d7edb92 1573}
1da177e4 1574
6418ecc6
JK		 1575/********************************************************************
1576* Copper link setup for e1000_phy_gg82563 series.
1577*
1578* hw - Struct containing variables accessed by shared code
1579*********************************************************************/
1580static int32_t
1581e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1582{
1583 int32_t ret_val;
1584 uint16_t phy_data;
1585 uint32_t reg_data;
1586
1587 DEBUGFUNC("e1000_copper_link_ggp_setup");
1588
8fc897b0 1589 if (!hw->phy_reset_disable) {
76c224bc 1590
6418ecc6
JK		 1591 /* Enable CRS on TX for half-duplex operation. */
1592 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1593 &phy_data);
8fc897b0 1594 if (ret_val)
6418ecc6
JK		 1595 return ret_val;
1596
1597 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1598 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1599 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1600
1601 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1602 phy_data);
8fc897b0 1603 if (ret_val)
6418ecc6
JK		 1604 return ret_val;
1605
1606 /* Options:
1607 * MDI/MDI-X = 0 (default)
1608 * 0 - Auto for all speeds
1609 * 1 - MDI mode
1610 * 2 - MDI-X mode
1611 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1612 */
1613 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
8fc897b0 1614 if (ret_val)
6418ecc6
JK		 1615 return ret_val;
1616
1617 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1618
1619 switch (hw->mdix) {
1620 case 1:
1621 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1622 break;
1623 case 2:
1624 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1625 break;
1626 case 0:
1627 default:
1628 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1629 break;
1630 }
1631
1632 /* Options:
1633 * disable_polarity_correction = 0 (default)
1634 * Automatic Correction for Reversed Cable Polarity
1635 * 0 - Disabled
1636 * 1 - Enabled
1637 */
1638 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
8fc897b0 1639 if (hw->disable_polarity_correction == 1)
6418ecc6
JK		 1640 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1641 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1642
8fc897b0 1643 if (ret_val)
6418ecc6
JK		 1644 return ret_val;
1645
1646 /* SW Reset the PHY so all changes take effect */
1647 ret_val = e1000_phy_reset(hw);
1648 if (ret_val) {
1649 DEBUGOUT("Error Resetting the PHY\n");
1650 return ret_val;
1651 }
1652 } /* phy_reset_disable */
1653
1654 if (hw->mac_type == e1000_80003es2lan) {
1655 /* Bypass RX and TX FIFO's */
1656 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1657 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1658 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1659 if (ret_val)
1660 return ret_val;
1661
1662 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1663 if (ret_val)
1664 return ret_val;
1665
1666 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1667 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1668
1669 if (ret_val)
1670 return ret_val;
1671
1672 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1673 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1674 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1675
1676 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1677 &phy_data);
1678 if (ret_val)
1679 return ret_val;
1680
1681 /* Do not init these registers when the HW is in IAMT mode, since the
1682 * firmware will have already initialized them. We only initialize
1683 * them if the HW is not in IAMT mode.
1684 */
1685 if (e1000_check_mng_mode(hw) == FALSE) {
1686 /* Enable Electrical Idle on the PHY */
1687 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1688 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1689 phy_data);
1690 if (ret_val)
1691 return ret_val;
1692
1693 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1694 &phy_data);
1695 if (ret_val)
1696 return ret_val;
1697
cd94dd0b 1698 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
6418ecc6
JK		 1699 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1700 phy_data);
8fc897b0 1701
6418ecc6
JK		 1702 if (ret_val)
1703 return ret_val;
1704 }
1705
1706 /* Workaround: Disable padding in Kumeran interface in the MAC
1707 * and in the PHY to avoid CRC errors.
1708 */
1709 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1710 &phy_data);
1711 if (ret_val)
1712 return ret_val;
1713 phy_data |= GG82563_ICR_DIS_PADDING;
1714 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1715 phy_data);
1716 if (ret_val)
1717 return ret_val;
1718 }
1719
1720 return E1000_SUCCESS;
1721}
1da177e4 1722
2d7edb92
MC		 1723/********************************************************************
1724* Copper link setup for e1000_phy_m88 series.
1725*
1726* hw - Struct containing variables accessed by shared code
1727*********************************************************************/
1728static int32_t
1729e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1730{
1731 int32_t ret_val;
1732 uint16_t phy_data;
1da177e4 1733
2d7edb92 1734 DEBUGFUNC("e1000_copper_link_mgp_setup");
1da177e4 1735
8fc897b0 1736 if (hw->phy_reset_disable)
2d7edb92 1737 return E1000_SUCCESS;
76c224bc 1738
2d7edb92
MC		 1739 /* Enable CRS on TX. This must be set for half-duplex operation. */
1740 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 1741 if (ret_val)
2d7edb92 1742 return ret_val;
1da177e4 1743
2d7edb92 1744 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1da177e4 1745
2d7edb92
MC		 1746 /* Options:
1747 * MDI/MDI-X = 0 (default)
1748 * 0 - Auto for all speeds
1749 * 1 - MDI mode
1750 * 2 - MDI-X mode
1751 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1752 */
1753 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1da177e4 1754
2d7edb92
MC		 1755 switch (hw->mdix) {
1756 case 1:
1757 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1758 break;
1759 case 2:
1760 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1761 break;
1762 case 3:
1763 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1764 break;
1765 case 0:
1766 default:
1767 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1768 break;
1769 }
1770
1771 /* Options:
1772 * disable_polarity_correction = 0 (default)
1773 * Automatic Correction for Reversed Cable Polarity
1774 * 0 - Disabled
1775 * 1 - Enabled
1da177e4 1776 */
2d7edb92 1777 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
8fc897b0 1778 if (hw->disable_polarity_correction == 1)
2d7edb92 1779 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
ee04022a
AK		 1780 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1781 if (ret_val)
2d7edb92
MC		 1782 return ret_val;
1783
2d7edb92 1784 if (hw->phy_revision < M88E1011_I_REV_4) {
ee04022a
AK		 1785 /* Force TX_CLK in the Extended PHY Specific Control Register
1786 * to 25MHz clock.
1787 */
1788 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1789 if (ret_val)
1790 return ret_val;
1791
1792 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1793
1794 if ((hw->phy_revision == E1000_REVISION_2) &&
1795 (hw->phy_id == M88E1111_I_PHY_ID)) {
1796 /* Vidalia Phy, set the downshift counter to 5x */
1797 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1798 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1799 ret_val = e1000_write_phy_reg(hw,
1800 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1801 if (ret_val)
1802 return ret_val;
1803 } else {
1804 /* Configure Master and Slave downshift values */
1805 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
2d7edb92 1806 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
ee04022a 1807 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
2d7edb92 1808 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
ee04022a
AK		 1809 ret_val = e1000_write_phy_reg(hw,
1810 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1811 if (ret_val)
1812 return ret_val;
1813 }
2d7edb92 1814 }
1da177e4 1815
2d7edb92
MC		 1816 /* SW Reset the PHY so all changes take effect */
1817 ret_val = e1000_phy_reset(hw);
8fc897b0 1818 if (ret_val) {
2d7edb92
MC		 1819 DEBUGOUT("Error Resetting the PHY\n");
1820 return ret_val;
1da177e4
LT		 1821 }
1822
2d7edb92 1823 return E1000_SUCCESS;
1da177e4
LT		 1824}
1825
2d7edb92
MC		 1826/********************************************************************
1827* Setup auto-negotiation and flow control advertisements,
1828* and then perform auto-negotiation.
1da177e4
LT		 1829*
1830* hw - Struct containing variables accessed by shared code
2d7edb92
MC		 1831*********************************************************************/
1832static int32_t
1833e1000_copper_link_autoneg(struct e1000_hw *hw)
1da177e4
LT		 1834{
1835 int32_t ret_val;
2d7edb92 1836 uint16_t phy_data;
1da177e4 1837
2d7edb92 1838 DEBUGFUNC("e1000_copper_link_autoneg");
1da177e4 1839
2d7edb92
MC		 1840 /* Perform some bounds checking on the hw->autoneg_advertised
1841 * parameter. If this variable is zero, then set it to the default.
1842 */
1843 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1844
1845 /* If autoneg_advertised is zero, we assume it was not defaulted
1846 * by the calling code so we set to advertise full capability.
1847 */
8fc897b0 1848 if (hw->autoneg_advertised == 0)
2d7edb92
MC		 1849 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1850
cd94dd0b
AK		 1851 /* IFE phy only supports 10/100 */
1852 if (hw->phy_type == e1000_phy_ife)
1853 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1854
2d7edb92
MC		 1855 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1856 ret_val = e1000_phy_setup_autoneg(hw);
8fc897b0 1857 if (ret_val) {
2d7edb92
MC		 1858 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1859 return ret_val;
1860 }
1861 DEBUGOUT("Restarting Auto-Neg\n");
1862
1863 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1864 * the Auto Neg Restart bit in the PHY control register.
1865 */
1866 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8fc897b0 1867 if (ret_val)
1da177e4
LT		 1868 return ret_val;
1869
2d7edb92
MC		 1870 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1871 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8fc897b0 1872 if (ret_val)
1da177e4
LT		 1873 return ret_val;
1874
2d7edb92
MC		 1875 /* Does the user want to wait for Auto-Neg to complete here, or
1876 * check at a later time (for example, callback routine).
1877 */
8fc897b0 1878 if (hw->wait_autoneg_complete) {
2d7edb92 1879 ret_val = e1000_wait_autoneg(hw);
8fc897b0 1880 if (ret_val) {
2d7edb92
MC		 1881 DEBUGOUT("Error while waiting for autoneg to complete\n");
1882 return ret_val;
1883 }
1884 }
1885
1886 hw->get_link_status = TRUE;
1887
1888 return E1000_SUCCESS;
1889}
1890
2d7edb92
MC		 1891/******************************************************************************
1892* Config the MAC and the PHY after link is up.
1893* 1) Set up the MAC to the current PHY speed/duplex
1894* if we are on 82543. If we
1895* are on newer silicon, we only need to configure
1896* collision distance in the Transmit Control Register.
1897* 2) Set up flow control on the MAC to that established with
1898* the link partner.
76c224bc 1899* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2d7edb92
MC		 1900*
1901* hw - Struct containing variables accessed by shared code
1902******************************************************************************/
1903static int32_t
1904e1000_copper_link_postconfig(struct e1000_hw *hw)
1905{
1906 int32_t ret_val;
1907 DEBUGFUNC("e1000_copper_link_postconfig");
76c224bc 1908
8fc897b0 1909 if (hw->mac_type >= e1000_82544) {
2d7edb92
MC		 1910 e1000_config_collision_dist(hw);
1911 } else {
1912 ret_val = e1000_config_mac_to_phy(hw);
8fc897b0 1913 if (ret_val) {
2d7edb92
MC		 1914 DEBUGOUT("Error configuring MAC to PHY settings\n");
1915 return ret_val;
1916 }
1917 }
1918 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 1919 if (ret_val) {
2d7edb92
MC		 1920 DEBUGOUT("Error Configuring Flow Control\n");
1921 return ret_val;
1922 }
1923
1924 /* Config DSP to improve Giga link quality */
8fc897b0 1925 if (hw->phy_type == e1000_phy_igp) {
2d7edb92 1926 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
8fc897b0 1927 if (ret_val) {
2d7edb92
MC		 1928 DEBUGOUT("Error Configuring DSP after link up\n");
1929 return ret_val;
1930 }
1931 }
76c224bc 1932
2d7edb92
MC		 1933 return E1000_SUCCESS;
1934}
1935
1936/******************************************************************************
1937* Detects which PHY is present and setup the speed and duplex
1938*
1939* hw - Struct containing variables accessed by shared code
1940******************************************************************************/
1941static int32_t
1942e1000_setup_copper_link(struct e1000_hw *hw)
1943{
1944 int32_t ret_val;
1945 uint16_t i;
1946 uint16_t phy_data;
6418ecc6 1947 uint16_t reg_data;
2d7edb92
MC		 1948
1949 DEBUGFUNC("e1000_setup_copper_link");
1950
cd94dd0b
AK		 1951 switch (hw->mac_type) {
1952 case e1000_80003es2lan:
1953 case e1000_ich8lan:
1954 /* Set the mac to wait the maximum time between each
1955 * iteration and increase the max iterations when
1956 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1957 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1958 if (ret_val)
1959 return ret_val;
1960 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1961 if (ret_val)
1962 return ret_val;
1963 reg_data |= 0x3F;
1964 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1965 if (ret_val)
1966 return ret_val;
1967 default:
1968 break;
1969 }
1970
2d7edb92
MC		 1971 /* Check if it is a valid PHY and set PHY mode if necessary. */
1972 ret_val = e1000_copper_link_preconfig(hw);
8fc897b0 1973 if (ret_val)
2d7edb92
MC		 1974 return ret_val;
1975
6418ecc6
JK		 1976 switch (hw->mac_type) {
1977 case e1000_80003es2lan:
cd94dd0b
AK		 1978 /* Kumeran registers are written-only */
1979 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
6418ecc6
JK		 1980 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1981 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1982 reg_data);
1983 if (ret_val)
1984 return ret_val;
1985 break;
1986 default:
1987 break;
1988 }
1989
2d7edb92 1990 if (hw->phy_type == e1000_phy_igp ||
cd94dd0b 1991 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92
MC		 1992 hw->phy_type == e1000_phy_igp_2) {
1993 ret_val = e1000_copper_link_igp_setup(hw);
8fc897b0 1994 if (ret_val)
2d7edb92
MC		 1995 return ret_val;
1996 } else if (hw->phy_type == e1000_phy_m88) {
1997 ret_val = e1000_copper_link_mgp_setup(hw);
8fc897b0 1998 if (ret_val)
2d7edb92 1999 return ret_val;
6418ecc6
JK		 2000 } else if (hw->phy_type == e1000_phy_gg82563) {
2001 ret_val = e1000_copper_link_ggp_setup(hw);
8fc897b0 2002 if (ret_val)
6418ecc6 2003 return ret_val;
2d7edb92
MC		 2004 }
2005
8fc897b0 2006 if (hw->autoneg) {
76c224bc
AK		 2007 /* Setup autoneg and flow control advertisement
2008 * and perform autonegotiation */
2d7edb92 2009 ret_val = e1000_copper_link_autoneg(hw);
8fc897b0 2010 if (ret_val)
76c224bc 2011 return ret_val;
2d7edb92
MC		 2012 } else {
2013 /* PHY will be set to 10H, 10F, 100H,or 100F
2014 * depending on value from forced_speed_duplex. */
2015 DEBUGOUT("Forcing speed and duplex\n");
2016 ret_val = e1000_phy_force_speed_duplex(hw);
8fc897b0 2017 if (ret_val) {
2d7edb92
MC		 2018 DEBUGOUT("Error Forcing Speed and Duplex\n");
2019 return ret_val;
2020 }
2021 }
2022
2023 /* Check link status. Wait up to 100 microseconds for link to become
2024 * valid.
2025 */
8fc897b0 2026 for (i = 0; i < 10; i++) {
2d7edb92 2027 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2028 if (ret_val)
2d7edb92
MC		 2029 return ret_val;
2030 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2031 if (ret_val)
2d7edb92
MC		 2032 return ret_val;
2033
8fc897b0 2034 if (phy_data & MII_SR_LINK_STATUS) {
2d7edb92
MC		 2035 /* Config the MAC and PHY after link is up */
2036 ret_val = e1000_copper_link_postconfig(hw);
8fc897b0 2037 if (ret_val)
2d7edb92 2038 return ret_val;
76c224bc 2039
2d7edb92
MC		 2040 DEBUGOUT("Valid link established!!!\n");
2041 return E1000_SUCCESS;
2042 }
2043 udelay(10);
2044 }
2045
2046 DEBUGOUT("Unable to establish link!!!\n");
2047 return E1000_SUCCESS;
2048}
2049
6418ecc6
JK		 2050/******************************************************************************
2051* Configure the MAC-to-PHY interface for 10/100Mbps
2052*
2053* hw - Struct containing variables accessed by shared code
2054******************************************************************************/
2055static int32_t
cd94dd0b 2056e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
6418ecc6
JK		 2057{
2058 int32_t ret_val = E1000_SUCCESS;
2059 uint32_t tipg;
2060 uint16_t reg_data;
2061
2062 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2063
2064 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2065 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2066 reg_data);
2067 if (ret_val)
2068 return ret_val;
2069
2070 /* Configure Transmit Inter-Packet Gap */
2071 tipg = E1000_READ_REG(hw, TIPG);
2072 tipg &= ~E1000_TIPG_IPGT_MASK;
2073 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2074 E1000_WRITE_REG(hw, TIPG, tipg);
2075
cd94dd0b
AK		 2076 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2077
2078 if (ret_val)
2079 return ret_val;
2080
2081 if (duplex == HALF_DUPLEX)
2082 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2083 else
2084 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2085
2086 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2087
6418ecc6
JK		 2088 return ret_val;
2089}
2090
2091static int32_t
2092e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2093{
2094 int32_t ret_val = E1000_SUCCESS;
2095 uint16_t reg_data;
2096 uint32_t tipg;
2097
2098 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2099
2100 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2101 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2102 reg_data);
2103 if (ret_val)
2104 return ret_val;
2105
2106 /* Configure Transmit Inter-Packet Gap */
2107 tipg = E1000_READ_REG(hw, TIPG);
2108 tipg &= ~E1000_TIPG_IPGT_MASK;
2109 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2110 E1000_WRITE_REG(hw, TIPG, tipg);
2111
cd94dd0b
AK		 2112 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2113
2114 if (ret_val)
2115 return ret_val;
2116
2117 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2118 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2119
6418ecc6
JK		 2120 return ret_val;
2121}
2122
2d7edb92
MC		 2123/******************************************************************************
2124* Configures PHY autoneg and flow control advertisement settings
2125*
2126* hw - Struct containing variables accessed by shared code
2127******************************************************************************/
2128int32_t
2129e1000_phy_setup_autoneg(struct e1000_hw *hw)
2130{
2131 int32_t ret_val;
2132 uint16_t mii_autoneg_adv_reg;
2133 uint16_t mii_1000t_ctrl_reg;
2134
2135 DEBUGFUNC("e1000_phy_setup_autoneg");
2136
2137 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2138 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
8fc897b0 2139 if (ret_val)
2d7edb92
MC		 2140 return ret_val;
2141
cd94dd0b
AK		 2142 if (hw->phy_type != e1000_phy_ife) {
2143 /* Read the MII 1000Base-T Control Register (Address 9). */
2144 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2145 if (ret_val)
2146 return ret_val;
2147 } else
2148 mii_1000t_ctrl_reg=0;
2d7edb92
MC		 2149
2150 /* Need to parse both autoneg_advertised and fc and set up
2151 * the appropriate PHY registers. First we will parse for
1da177e4
LT		 2152 * autoneg_advertised software override. Since we can advertise
2153 * a plethora of combinations, we need to check each bit
2154 * individually.
2155 */
2156
2157 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2158 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2159 * the 1000Base-T Control Register (Address 9).
2160 */
2161 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2162 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2163
2164 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2165
2166 /* Do we want to advertise 10 Mb Half Duplex? */
8fc897b0 2167 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1da177e4
LT		 2168 DEBUGOUT("Advertise 10mb Half duplex\n");
2169 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2170 }
2171
2172 /* Do we want to advertise 10 Mb Full Duplex? */
8fc897b0 2173 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1da177e4
LT		 2174 DEBUGOUT("Advertise 10mb Full duplex\n");
2175 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2176 }
2177
2178 /* Do we want to advertise 100 Mb Half Duplex? */
8fc897b0 2179 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1da177e4
LT		 2180 DEBUGOUT("Advertise 100mb Half duplex\n");
2181 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2182 }
2183
2184 /* Do we want to advertise 100 Mb Full Duplex? */
8fc897b0 2185 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1da177e4
LT		 2186 DEBUGOUT("Advertise 100mb Full duplex\n");
2187 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2188 }
2189
2190 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
8fc897b0 2191 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1da177e4
LT		 2192 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2193 }
2194
2195 /* Do we want to advertise 1000 Mb Full Duplex? */
8fc897b0 2196 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1da177e4
LT		 2197 DEBUGOUT("Advertise 1000mb Full duplex\n");
2198 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
cd94dd0b
AK		 2199 if (hw->phy_type == e1000_phy_ife) {
2200 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2201 }
1da177e4
LT		 2202 }
2203
2204 /* Check for a software override of the flow control settings, and
2205 * setup the PHY advertisement registers accordingly. If
2206 * auto-negotiation is enabled, then software will have to set the
2207 * "PAUSE" bits to the correct value in the Auto-Negotiation
2208 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2209 *
2210 * The possible values of the "fc" parameter are:
2211 * 0: Flow control is completely disabled
2212 * 1: Rx flow control is enabled (we can receive pause frames
2213 * but not send pause frames).
2214 * 2: Tx flow control is enabled (we can send pause frames
2215 * but we do not support receiving pause frames).
2216 * 3: Both Rx and TX flow control (symmetric) are enabled.
2217 * other: No software override. The flow control configuration
2218 * in the EEPROM is used.
2219 */
2220 switch (hw->fc) {
11241b10 2221 case E1000_FC_NONE: /* 0 */
1da177e4
LT		 2222 /* Flow control (RX & TX) is completely disabled by a
2223 * software over-ride.
2224 */
2225 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2226 break;
11241b10 2227 case E1000_FC_RX_PAUSE: /* 1 */
1da177e4
LT		 2228 /* RX Flow control is enabled, and TX Flow control is
2229 * disabled, by a software over-ride.
2230 */
2231 /* Since there really isn't a way to advertise that we are
2232 * capable of RX Pause ONLY, we will advertise that we
2233 * support both symmetric and asymmetric RX PAUSE. Later
2234 * (in e1000_config_fc_after_link_up) we will disable the
2235 *hw's ability to send PAUSE frames.
2236 */
2237 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2238 break;
11241b10 2239 case E1000_FC_TX_PAUSE: /* 2 */
1da177e4
LT		 2240 /* TX Flow control is enabled, and RX Flow control is
2241 * disabled, by a software over-ride.
2242 */
2243 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2244 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2245 break;
11241b10 2246 case E1000_FC_FULL: /* 3 */
1da177e4
LT		 2247 /* Flow control (both RX and TX) is enabled by a software
2248 * over-ride.
2249 */
2250 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2251 break;
2252 default:
2253 DEBUGOUT("Flow control param set incorrectly\n");
2254 return -E1000_ERR_CONFIG;
2255 }
2256
2257 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
8fc897b0 2258 if (ret_val)
1da177e4
LT		 2259 return ret_val;
2260
2261 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2262
cd94dd0b
AK		 2263 if (hw->phy_type != e1000_phy_ife) {
2264 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2265 if (ret_val)
2266 return ret_val;
2267 }
1da177e4
LT		 2268
2269 return E1000_SUCCESS;
2270}
2271
2272/******************************************************************************
2273* Force PHY speed and duplex settings to hw->forced_speed_duplex
2274*
2275* hw - Struct containing variables accessed by shared code
2276******************************************************************************/
2277static int32_t
2278e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2279{
2280 uint32_t ctrl;
2281 int32_t ret_val;
2282 uint16_t mii_ctrl_reg;
2283 uint16_t mii_status_reg;
2284 uint16_t phy_data;
2285 uint16_t i;
2286
2287 DEBUGFUNC("e1000_phy_force_speed_duplex");
2288
2289 /* Turn off Flow control if we are forcing speed and duplex. */
11241b10 2290 hw->fc = E1000_FC_NONE;
1da177e4
LT		 2291
2292 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2293
2294 /* Read the Device Control Register. */
2295 ctrl = E1000_READ_REG(hw, CTRL);
2296
2297 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2298 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2299 ctrl &= ~(DEVICE_SPEED_MASK);
2300
2301 /* Clear the Auto Speed Detect Enable bit. */
2302 ctrl &= ~E1000_CTRL_ASDE;
2303
2304 /* Read the MII Control Register. */
2305 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
8fc897b0 2306 if (ret_val)
1da177e4
LT		 2307 return ret_val;
2308
2309 /* We need to disable autoneg in order to force link and duplex. */
2310
2311 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2312
2313 /* Are we forcing Full or Half Duplex? */
8fc897b0
AK		 2314 if (hw->forced_speed_duplex == e1000_100_full ||
2315 hw->forced_speed_duplex == e1000_10_full) {
1da177e4
LT		 2316 /* We want to force full duplex so we SET the full duplex bits in the
2317 * Device and MII Control Registers.
2318 */
2319 ctrl |= E1000_CTRL_FD;
2320 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2321 DEBUGOUT("Full Duplex\n");
2322 } else {
2323 /* We want to force half duplex so we CLEAR the full duplex bits in
2324 * the Device and MII Control Registers.
2325 */
2326 ctrl &= ~E1000_CTRL_FD;
2327 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2328 DEBUGOUT("Half Duplex\n");
2329 }
2330
2331 /* Are we forcing 100Mbps??? */
8fc897b0 2332 if (hw->forced_speed_duplex == e1000_100_full ||
1da177e4
LT		 2333 hw->forced_speed_duplex == e1000_100_half) {
2334 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2335 ctrl |= E1000_CTRL_SPD_100;
2336 mii_ctrl_reg |= MII_CR_SPEED_100;
2337 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2338 DEBUGOUT("Forcing 100mb ");
2339 } else {
2340 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2341 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2342 mii_ctrl_reg |= MII_CR_SPEED_10;
2343 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2344 DEBUGOUT("Forcing 10mb ");
2345 }
2346
2347 e1000_config_collision_dist(hw);
2348
2349 /* Write the configured values back to the Device Control Reg. */
2350 E1000_WRITE_REG(hw, CTRL, ctrl);
2351
6418ecc6
JK		 2352 if ((hw->phy_type == e1000_phy_m88) ||
2353 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4 2354 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2355 if (ret_val)
1da177e4
LT		 2356 return ret_val;
2357
2358 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2359 * forced whenever speed are duplex are forced.
2360 */
2361 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2362 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
8fc897b0 2363 if (ret_val)
1da177e4
LT		 2364 return ret_val;
2365
2366 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2367
2368 /* Need to reset the PHY or these changes will be ignored */
2369 mii_ctrl_reg |= MII_CR_RESET;
cd94dd0b
AK		 2370 /* Disable MDI-X support for 10/100 */
2371 } else if (hw->phy_type == e1000_phy_ife) {
2372 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2373 if (ret_val)
2374 return ret_val;
2375
2376 phy_data &= ~IFE_PMC_AUTO_MDIX;
2377 phy_data &= ~IFE_PMC_FORCE_MDIX;
2378
2379 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2380 if (ret_val)
2381 return ret_val;
1da177e4
LT		 2382 } else {
2383 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2384 * forced whenever speed or duplex are forced.
2385 */
2386 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
8fc897b0 2387 if (ret_val)
1da177e4
LT		 2388 return ret_val;
2389
2390 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2391 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2392
2393 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
8fc897b0 2394 if (ret_val)
1da177e4
LT		 2395 return ret_val;
2396 }
2397
2398 /* Write back the modified PHY MII control register. */
2399 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
8fc897b0 2400 if (ret_val)
1da177e4
LT		 2401 return ret_val;
2402
2403 udelay(1);
2404
2405 /* The wait_autoneg_complete flag may be a little misleading here.
2406 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2407 * But we do want to delay for a period while forcing only so we
2408 * don't generate false No Link messages. So we will wait here
2409 * only if the user has set wait_autoneg_complete to 1, which is
2410 * the default.
2411 */
8fc897b0 2412 if (hw->wait_autoneg_complete) {
1da177e4
LT		 2413 /* We will wait for autoneg to complete. */
2414 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2415 mii_status_reg = 0;
2416
2417 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
8fc897b0 2418 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 2419 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2420 * to be set.
2421 */
2422 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2423 if (ret_val)
1da177e4
LT		 2424 return ret_val;
2425
2426 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2427 if (ret_val)
1da177e4
LT		 2428 return ret_val;
2429
8fc897b0 2430 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 2431 msleep(100);
1da177e4 2432 }
8fc897b0 2433 if ((i == 0) &&
6418ecc6
JK		 2434 ((hw->phy_type == e1000_phy_m88) ||
2435 (hw->phy_type == e1000_phy_gg82563))) {
1da177e4
LT		 2436 /* We didn't get link. Reset the DSP and wait again for link. */
2437 ret_val = e1000_phy_reset_dsp(hw);
8fc897b0 2438 if (ret_val) {
1da177e4
LT		 2439 DEBUGOUT("Error Resetting PHY DSP\n");
2440 return ret_val;
2441 }
2442 }
2443 /* This loop will early-out if the link condition has been met. */
8fc897b0
AK		 2444 for (i = PHY_FORCE_TIME; i > 0; i--) {
2445 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 2446 msleep(100);
1da177e4
LT		 2447 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2448 * to be set.
2449 */
2450 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2451 if (ret_val)
1da177e4
LT		 2452 return ret_val;
2453
2454 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2455 if (ret_val)
1da177e4
LT		 2456 return ret_val;
2457 }
2458 }
2459
2460 if (hw->phy_type == e1000_phy_m88) {
2461 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2462 * Extended PHY Specific Control Register to 25MHz clock. This value
2463 * defaults back to a 2.5MHz clock when the PHY is reset.
2464 */
2465 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2466 if (ret_val)
1da177e4
LT		 2467 return ret_val;
2468
2469 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2470 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
8fc897b0 2471 if (ret_val)
1da177e4
LT		 2472 return ret_val;
2473
2474 /* In addition, because of the s/w reset above, we need to enable CRS on
2475 * TX. This must be set for both full and half duplex operation.
2476 */
2477 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2478 if (ret_val)
1da177e4
LT		 2479 return ret_val;
2480
2481 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2482 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
8fc897b0 2483 if (ret_val)
1da177e4
LT		 2484 return ret_val;
2485
8fc897b0
AK		 2486 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2487 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2488 hw->forced_speed_duplex == e1000_10_half)) {
1da177e4 2489 ret_val = e1000_polarity_reversal_workaround(hw);
8fc897b0 2490 if (ret_val)
1da177e4
LT		 2491 return ret_val;
2492 }
6418ecc6
JK		 2493 } else if (hw->phy_type == e1000_phy_gg82563) {
2494 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2495 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2496 * we're not in a forced 10/duplex configuration. */
2497 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2498 if (ret_val)
2499 return ret_val;
2500
2501 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2502 if ((hw->forced_speed_duplex == e1000_10_full) ||
2503 (hw->forced_speed_duplex == e1000_10_half))
2504 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2505 else
2506 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2507
2508 /* Also due to the reset, we need to enable CRS on Tx. */
2509 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2510
2511 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2512 if (ret_val)
2513 return ret_val;
1da177e4
LT		 2514 }
2515 return E1000_SUCCESS;
2516}
2517
2518/******************************************************************************
2519* Sets the collision distance in the Transmit Control register
2520*
2521* hw - Struct containing variables accessed by shared code
2522*
2523* Link should have been established previously. Reads the speed and duplex
2524* information from the Device Status register.
2525******************************************************************************/
2526void
2527e1000_config_collision_dist(struct e1000_hw *hw)
2528{
0fadb059 2529 uint32_t tctl, coll_dist;
1da177e4
LT		 2530
2531 DEBUGFUNC("e1000_config_collision_dist");
2532
0fadb059
JK		 2533 if (hw->mac_type < e1000_82543)
2534 coll_dist = E1000_COLLISION_DISTANCE_82542;
2535 else
2536 coll_dist = E1000_COLLISION_DISTANCE;
2537
1da177e4
LT		 2538 tctl = E1000_READ_REG(hw, TCTL);
2539
2540 tctl &= ~E1000_TCTL_COLD;
0fadb059 2541 tctl |= coll_dist << E1000_COLD_SHIFT;
1da177e4
LT		 2542
2543 E1000_WRITE_REG(hw, TCTL, tctl);
2544 E1000_WRITE_FLUSH(hw);
2545}
2546
2547/******************************************************************************
2548* Sets MAC speed and duplex settings to reflect the those in the PHY
2549*
2550* hw - Struct containing variables accessed by shared code
2551* mii_reg - data to write to the MII control register
2552*
2553* The contents of the PHY register containing the needed information need to
2554* be passed in.
2555******************************************************************************/
2556static int32_t
2557e1000_config_mac_to_phy(struct e1000_hw *hw)
2558{
2559 uint32_t ctrl;
2560 int32_t ret_val;
2561 uint16_t phy_data;
2562
2563 DEBUGFUNC("e1000_config_mac_to_phy");
2564
76c224bc 2565 /* 82544 or newer MAC, Auto Speed Detection takes care of
2d7edb92
MC		 2566 * MAC speed/duplex configuration.*/
2567 if (hw->mac_type >= e1000_82544)
2568 return E1000_SUCCESS;
2569
1da177e4
LT		 2570 /* Read the Device Control Register and set the bits to Force Speed
2571 * and Duplex.
2572 */
2573 ctrl = E1000_READ_REG(hw, CTRL);
2574 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2575 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2576
2577 /* Set up duplex in the Device Control and Transmit Control
2578 * registers depending on negotiated values.
2579 */
2d7edb92 2580 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
8fc897b0 2581 if (ret_val)
2d7edb92 2582 return ret_val;
1da177e4 2583
8fc897b0 2584 if (phy_data & M88E1000_PSSR_DPLX)
2d7edb92 2585 ctrl |= E1000_CTRL_FD;
76c224bc 2586 else
2d7edb92 2587 ctrl &= ~E1000_CTRL_FD;
1da177e4 2588
2d7edb92 2589 e1000_config_collision_dist(hw);
1da177e4 2590
2d7edb92
MC		 2591 /* Set up speed in the Device Control register depending on
2592 * negotiated values.
2593 */
8fc897b0 2594 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2d7edb92 2595 ctrl |= E1000_CTRL_SPD_1000;
8fc897b0 2596 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2d7edb92 2597 ctrl |= E1000_CTRL_SPD_100;
1da177e4 2598
1da177e4
LT		 2599 /* Write the configured values back to the Device Control Reg. */
2600 E1000_WRITE_REG(hw, CTRL, ctrl);
2601 return E1000_SUCCESS;
2602}
2603
2604/******************************************************************************
2605 * Forces the MAC's flow control settings.
2606 *
2607 * hw - Struct containing variables accessed by shared code
2608 *
2609 * Sets the TFCE and RFCE bits in the device control register to reflect
2610 * the adapter settings. TFCE and RFCE need to be explicitly set by
2611 * software when a Copper PHY is used because autonegotiation is managed
2612 * by the PHY rather than the MAC. Software must also configure these
2613 * bits when link is forced on a fiber connection.
2614 *****************************************************************************/
2615int32_t
2616e1000_force_mac_fc(struct e1000_hw *hw)
2617{
2618 uint32_t ctrl;
2619
2620 DEBUGFUNC("e1000_force_mac_fc");
2621
2622 /* Get the current configuration of the Device Control Register */
2623 ctrl = E1000_READ_REG(hw, CTRL);
2624
2625 /* Because we didn't get link via the internal auto-negotiation
2626 * mechanism (we either forced link or we got link via PHY
2627 * auto-neg), we have to manually enable/disable transmit an
2628 * receive flow control.
2629 *
2630 * The "Case" statement below enables/disable flow control
2631 * according to the "hw->fc" parameter.
2632 *
2633 * The possible values of the "fc" parameter are:
2634 * 0: Flow control is completely disabled
2635 * 1: Rx flow control is enabled (we can receive pause
2636 * frames but not send pause frames).
2637 * 2: Tx flow control is enabled (we can send pause frames
2638 * frames but we do not receive pause frames).
2639 * 3: Both Rx and TX flow control (symmetric) is enabled.
2640 * other: No other values should be possible at this point.
2641 */
2642
2643 switch (hw->fc) {
11241b10 2644 case E1000_FC_NONE:
1da177e4
LT		 2645 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2646 break;
11241b10 2647 case E1000_FC_RX_PAUSE:
1da177e4
LT		 2648 ctrl &= (~E1000_CTRL_TFCE);
2649 ctrl |= E1000_CTRL_RFCE;
2650 break;
11241b10 2651 case E1000_FC_TX_PAUSE:
1da177e4
LT		 2652 ctrl &= (~E1000_CTRL_RFCE);
2653 ctrl |= E1000_CTRL_TFCE;
2654 break;
11241b10 2655 case E1000_FC_FULL:
1da177e4
LT		 2656 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2657 break;
2658 default:
2659 DEBUGOUT("Flow control param set incorrectly\n");
2660 return -E1000_ERR_CONFIG;
2661 }
2662
2663 /* Disable TX Flow Control for 82542 (rev 2.0) */
8fc897b0 2664 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2665 ctrl &= (~E1000_CTRL_TFCE);
2666
2667 E1000_WRITE_REG(hw, CTRL, ctrl);
2668 return E1000_SUCCESS;
2669}
2670
2671/******************************************************************************
2672 * Configures flow control settings after link is established
2673 *
2674 * hw - Struct containing variables accessed by shared code
2675 *
2676 * Should be called immediately after a valid link has been established.
2677 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2678 * and autonegotiation is enabled, the MAC flow control settings will be set
2679 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2680 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2681 *****************************************************************************/
3ad2cc67 2682static int32_t
1da177e4
LT		 2683e1000_config_fc_after_link_up(struct e1000_hw *hw)
2684{
2685 int32_t ret_val;
2686 uint16_t mii_status_reg;
2687 uint16_t mii_nway_adv_reg;
2688 uint16_t mii_nway_lp_ability_reg;
2689 uint16_t speed;
2690 uint16_t duplex;
2691
2692 DEBUGFUNC("e1000_config_fc_after_link_up");
2693
2694 /* Check for the case where we have fiber media and auto-neg failed
2695 * so we had to force link. In this case, we need to force the
2696 * configuration of the MAC to match the "fc" parameter.
2697 */
8fc897b0
AK		 2698 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2699 ((hw->media_type == e1000_media_type_internal_serdes) &&
2700 (hw->autoneg_failed)) ||
2701 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1da177e4 2702 ret_val = e1000_force_mac_fc(hw);
8fc897b0 2703 if (ret_val) {
1da177e4
LT		 2704 DEBUGOUT("Error forcing flow control settings\n");
2705 return ret_val;
2706 }
2707 }
2708
2709 /* Check for the case where we have copper media and auto-neg is
2710 * enabled. In this case, we need to check and see if Auto-Neg
2711 * has completed, and if so, how the PHY and link partner has
2712 * flow control configured.
2713 */
8fc897b0 2714 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1da177e4
LT		 2715 /* Read the MII Status Register and check to see if AutoNeg
2716 * has completed. We read this twice because this reg has
2717 * some "sticky" (latched) bits.
2718 */
2719 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2720 if (ret_val)
1da177e4
LT		 2721 return ret_val;
2722 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2723 if (ret_val)
1da177e4
LT		 2724 return ret_val;
2725
8fc897b0 2726 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1da177e4
LT		 2727 /* The AutoNeg process has completed, so we now need to
2728 * read both the Auto Negotiation Advertisement Register
2729 * (Address 4) and the Auto_Negotiation Base Page Ability
2730 * Register (Address 5) to determine how flow control was
2731 * negotiated.
2732 */
2733 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2734 &mii_nway_adv_reg);
8fc897b0 2735 if (ret_val)
1da177e4
LT		 2736 return ret_val;
2737 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2738 &mii_nway_lp_ability_reg);
8fc897b0 2739 if (ret_val)
1da177e4
LT		 2740 return ret_val;
2741
2742 /* Two bits in the Auto Negotiation Advertisement Register
2743 * (Address 4) and two bits in the Auto Negotiation Base
2744 * Page Ability Register (Address 5) determine flow control
2745 * for both the PHY and the link partner. The following
2746 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2747 * 1999, describes these PAUSE resolution bits and how flow
2748 * control is determined based upon these settings.
2749 * NOTE: DC = Don't Care
2750 *
2751 * LOCAL DEVICE | LINK PARTNER
2752 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2753 *-------|---------|-------|---------|--------------------
11241b10
JK		 2754 * 0 | 0 | DC | DC | E1000_FC_NONE
2755 * 0 | 1 | 0 | DC | E1000_FC_NONE
2756 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2757 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2758 * 1 | 0 | 0 | DC | E1000_FC_NONE
2759 * 1 | DC | 1 | DC | E1000_FC_FULL
2760 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2761 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
1da177e4
LT		 2762 *
2763 */
2764 /* Are both PAUSE bits set to 1? If so, this implies
2765 * Symmetric Flow Control is enabled at both ends. The
2766 * ASM_DIR bits are irrelevant per the spec.
2767 *
2768 * For Symmetric Flow Control:
2769 *
2770 * LOCAL DEVICE | LINK PARTNER
2771 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2772 *-------|---------|-------|---------|--------------------
11241b10 2773 * 1 | DC | 1 | DC | E1000_FC_FULL
1da177e4
LT		 2774 *
2775 */
8fc897b0
AK		 2776 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2777 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1da177e4
LT		 2778 /* Now we need to check if the user selected RX ONLY
2779 * of pause frames. In this case, we had to advertise
2780 * FULL flow control because we could not advertise RX
2781 * ONLY. Hence, we must now check to see if we need to
2782 * turn OFF the TRANSMISSION of PAUSE frames.
2783 */
11241b10
JK		 2784 if (hw->original_fc == E1000_FC_FULL) {
2785 hw->fc = E1000_FC_FULL;
a42a507c 2786 DEBUGOUT("Flow Control = FULL.\n");
1da177e4 2787 } else {
11241b10 2788 hw->fc = E1000_FC_RX_PAUSE;
a42a507c 2789 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2790 }
2791 }
2792 /* For receiving PAUSE frames ONLY.
2793 *
2794 * LOCAL DEVICE | LINK PARTNER
2795 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2796 *-------|---------|-------|---------|--------------------
11241b10 2797 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
1da177e4
LT		 2798 *
2799 */
8fc897b0
AK		 2800 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2801 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2802 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2803 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
11241b10 2804 hw->fc = E1000_FC_TX_PAUSE;
a42a507c 2805 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1da177e4
LT		 2806 }
2807 /* For transmitting PAUSE frames ONLY.
2808 *
2809 * LOCAL DEVICE | LINK PARTNER
2810 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2811 *-------|---------|-------|---------|--------------------
11241b10 2812 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
1da177e4
LT		 2813 *
2814 */
8fc897b0
AK		 2815 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2816 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2817 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2818 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
11241b10 2819 hw->fc = E1000_FC_RX_PAUSE;
a42a507c 2820 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2821 }
2822 /* Per the IEEE spec, at this point flow control should be
2823 * disabled. However, we want to consider that we could
2824 * be connected to a legacy switch that doesn't advertise
2825 * desired flow control, but can be forced on the link
2826 * partner. So if we advertised no flow control, that is
2827 * what we will resolve to. If we advertised some kind of
2828 * receive capability (Rx Pause Only or Full Flow Control)
2829 * and the link partner advertised none, we will configure
2830 * ourselves to enable Rx Flow Control only. We can do
2831 * this safely for two reasons: If the link partner really
2832 * didn't want flow control enabled, and we enable Rx, no
2833 * harm done since we won't be receiving any PAUSE frames
2834 * anyway. If the intent on the link partner was to have
2835 * flow control enabled, then by us enabling RX only, we
2836 * can at least receive pause frames and process them.
2837 * This is a good idea because in most cases, since we are
2838 * predominantly a server NIC, more times than not we will
2839 * be asked to delay transmission of packets than asking
2840 * our link partner to pause transmission of frames.
2841 */
11241b10
JK		 2842 else if ((hw->original_fc == E1000_FC_NONE ||
2843 hw->original_fc == E1000_FC_TX_PAUSE) ||
8fc897b0 2844 hw->fc_strict_ieee) {
11241b10 2845 hw->fc = E1000_FC_NONE;
a42a507c 2846 DEBUGOUT("Flow Control = NONE.\n");
1da177e4 2847 } else {
11241b10 2848 hw->fc = E1000_FC_RX_PAUSE;
a42a507c 2849 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2850 }
2851
2852 /* Now we need to do one last check... If we auto-
2853 * negotiated to HALF DUPLEX, flow control should not be
2854 * enabled per IEEE 802.3 spec.
2855 */
2856 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
8fc897b0 2857 if (ret_val) {
1da177e4
LT		 2858 DEBUGOUT("Error getting link speed and duplex\n");
2859 return ret_val;
2860 }
2861
8fc897b0 2862 if (duplex == HALF_DUPLEX)
11241b10 2863 hw->fc = E1000_FC_NONE;
1da177e4
LT		 2864
2865 /* Now we call a subroutine to actually force the MAC
2866 * controller to use the correct flow control settings.
2867 */
2868 ret_val = e1000_force_mac_fc(hw);
8fc897b0 2869 if (ret_val) {
1da177e4
LT		 2870 DEBUGOUT("Error forcing flow control settings\n");
2871 return ret_val;
2872 }
2873 } else {
a42a507c 2874 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1da177e4
LT		 2875 }
2876 }
2877 return E1000_SUCCESS;
2878}
2879
2880/******************************************************************************
2881 * Checks to see if the link status of the hardware has changed.
2882 *
2883 * hw - Struct containing variables accessed by shared code
2884 *
2885 * Called by any function that needs to check the link status of the adapter.
2886 *****************************************************************************/
2887int32_t
2888e1000_check_for_link(struct e1000_hw *hw)
2889{
2890 uint32_t rxcw = 0;
2891 uint32_t ctrl;
2892 uint32_t status;
2893 uint32_t rctl;
2894 uint32_t icr;
2895 uint32_t signal = 0;
2896 int32_t ret_val;
2897 uint16_t phy_data;
2898
2899 DEBUGFUNC("e1000_check_for_link");
2900
2901 ctrl = E1000_READ_REG(hw, CTRL);
2902 status = E1000_READ_REG(hw, STATUS);
2903
2904 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2905 * set when the optics detect a signal. On older adapters, it will be
2906 * cleared when there is a signal. This applies to fiber media only.
2907 */
8fc897b0
AK		 2908 if ((hw->media_type == e1000_media_type_fiber) ||
2909 (hw->media_type == e1000_media_type_internal_serdes)) {
1da177e4
LT		 2910 rxcw = E1000_READ_REG(hw, RXCW);
2911
8fc897b0 2912 if (hw->media_type == e1000_media_type_fiber) {
1da177e4 2913 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
8fc897b0 2914 if (status & E1000_STATUS_LU)
1da177e4
LT		 2915 hw->get_link_status = FALSE;
2916 }
2917 }
2918
2919 /* If we have a copper PHY then we only want to go out to the PHY
2920 * registers to see if Auto-Neg has completed and/or if our link
2921 * status has changed. The get_link_status flag will be set if we
2922 * receive a Link Status Change interrupt or we have Rx Sequence
2923 * Errors.
2924 */
8fc897b0 2925 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1da177e4
LT		 2926 /* First we want to see if the MII Status Register reports
2927 * link. If so, then we want to get the current speed/duplex
2928 * of the PHY.
2929 * Read the register twice since the link bit is sticky.
2930 */
2931 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2932 if (ret_val)
1da177e4
LT		 2933 return ret_val;
2934 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2935 if (ret_val)
1da177e4
LT		 2936 return ret_val;
2937
8fc897b0 2938 if (phy_data & MII_SR_LINK_STATUS) {
1da177e4
LT		 2939 hw->get_link_status = FALSE;
2940 /* Check if there was DownShift, must be checked immediately after
2941 * link-up */
2942 e1000_check_downshift(hw);
2943
2944 /* If we are on 82544 or 82543 silicon and speed/duplex
2945 * are forced to 10H or 10F, then we will implement the polarity
2946 * reversal workaround. We disable interrupts first, and upon
2947 * returning, place the devices interrupt state to its previous
2948 * value except for the link status change interrupt which will
2949 * happen due to the execution of this workaround.
2950 */
2951
8fc897b0
AK		 2952 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2953 (!hw->autoneg) &&
2954 (hw->forced_speed_duplex == e1000_10_full ||
2955 hw->forced_speed_duplex == e1000_10_half)) {
1da177e4
LT		 2956 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2957 ret_val = e1000_polarity_reversal_workaround(hw);
2958 icr = E1000_READ_REG(hw, ICR);
2959 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2960 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2961 }
2962
2963 } else {
2964 /* No link detected */
2965 e1000_config_dsp_after_link_change(hw, FALSE);
2966 return 0;
2967 }
2968
2969 /* If we are forcing speed/duplex, then we simply return since
2970 * we have already determined whether we have link or not.
2971 */
8fc897b0 2972 if (!hw->autoneg) return -E1000_ERR_CONFIG;
1da177e4
LT		 2973
2974 /* optimize the dsp settings for the igp phy */
2975 e1000_config_dsp_after_link_change(hw, TRUE);
2976
2977 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2978 * have Si on board that is 82544 or newer, Auto
2979 * Speed Detection takes care of MAC speed/duplex
2980 * configuration. So we only need to configure Collision
2981 * Distance in the MAC. Otherwise, we need to force
2982 * speed/duplex on the MAC to the current PHY speed/duplex
2983 * settings.
2984 */
8fc897b0 2985 if (hw->mac_type >= e1000_82544)
1da177e4
LT		 2986 e1000_config_collision_dist(hw);
2987 else {
2988 ret_val = e1000_config_mac_to_phy(hw);
8fc897b0 2989 if (ret_val) {
1da177e4
LT		 2990 DEBUGOUT("Error configuring MAC to PHY settings\n");
2991 return ret_val;
2992 }
2993 }
2994
2995 /* Configure Flow Control now that Auto-Neg has completed. First, we
2996 * need to restore the desired flow control settings because we may
2997 * have had to re-autoneg with a different link partner.
2998 */
2999 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 3000 if (ret_val) {
1da177e4
LT		 3001 DEBUGOUT("Error configuring flow control\n");
3002 return ret_val;
3003 }
3004
3005 /* At this point we know that we are on copper and we have
3006 * auto-negotiated link. These are conditions for checking the link
3007 * partner capability register. We use the link speed to determine if
3008 * TBI compatibility needs to be turned on or off. If the link is not
3009 * at gigabit speed, then TBI compatibility is not needed. If we are
3010 * at gigabit speed, we turn on TBI compatibility.
3011 */
8fc897b0 3012 if (hw->tbi_compatibility_en) {
1da177e4 3013 uint16_t speed, duplex;
592600a0
AK		 3014 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3015 if (ret_val) {
3016 DEBUGOUT("Error getting link speed and duplex\n");
3017 return ret_val;
3018 }
3019 if (speed != SPEED_1000) {
1da177e4
LT		 3020 /* If link speed is not set to gigabit speed, we do not need
3021 * to enable TBI compatibility.
3022 */
8fc897b0 3023 if (hw->tbi_compatibility_on) {
1da177e4
LT		 3024 /* If we previously were in the mode, turn it off. */
3025 rctl = E1000_READ_REG(hw, RCTL);
3026 rctl &= ~E1000_RCTL_SBP;
3027 E1000_WRITE_REG(hw, RCTL, rctl);
3028 hw->tbi_compatibility_on = FALSE;
3029 }
3030 } else {
3031 /* If TBI compatibility is was previously off, turn it on. For
3032 * compatibility with a TBI link partner, we will store bad
3033 * packets. Some frames have an additional byte on the end and
3034 * will look like CRC errors to to the hardware.
3035 */
8fc897b0 3036 if (!hw->tbi_compatibility_on) {
1da177e4
LT		 3037 hw->tbi_compatibility_on = TRUE;
3038 rctl = E1000_READ_REG(hw, RCTL);
3039 rctl |= E1000_RCTL_SBP;
3040 E1000_WRITE_REG(hw, RCTL, rctl);
3041 }
3042 }
3043 }
3044 }
3045 /* If we don't have link (auto-negotiation failed or link partner cannot
3046 * auto-negotiate), the cable is plugged in (we have signal), and our
3047 * link partner is not trying to auto-negotiate with us (we are receiving
3048 * idles or data), we need to force link up. We also need to give
3049 * auto-negotiation time to complete, in case the cable was just plugged
3050 * in. The autoneg_failed flag does this.
3051 */
8fc897b0 3052 else if ((((hw->media_type == e1000_media_type_fiber) &&
1da177e4 3053 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
8fc897b0
AK		 3054 (hw->media_type == e1000_media_type_internal_serdes)) &&
3055 (!(status & E1000_STATUS_LU)) &&
3056 (!(rxcw & E1000_RXCW_C))) {
3057 if (hw->autoneg_failed == 0) {
1da177e4
LT		 3058 hw->autoneg_failed = 1;
3059 return 0;
3060 }
a42a507c 3061 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1da177e4
LT		 3062
3063 /* Disable auto-negotiation in the TXCW register */
3064 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3065
3066 /* Force link-up and also force full-duplex. */
3067 ctrl = E1000_READ_REG(hw, CTRL);
3068 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3069 E1000_WRITE_REG(hw, CTRL, ctrl);
3070
3071 /* Configure Flow Control after forcing link up. */
3072 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 3073 if (ret_val) {
1da177e4
LT		 3074 DEBUGOUT("Error configuring flow control\n");
3075 return ret_val;
3076 }
3077 }
3078 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3079 * auto-negotiation in the TXCW register and disable forced link in the
3080 * Device Control register in an attempt to auto-negotiate with our link
3081 * partner.
3082 */
8fc897b0
AK		 3083 else if (((hw->media_type == e1000_media_type_fiber) ||
3084 (hw->media_type == e1000_media_type_internal_serdes)) &&
3085 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
a42a507c 3086 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1da177e4
LT		 3087 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3088 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3089
3090 hw->serdes_link_down = FALSE;
3091 }
3092 /* If we force link for non-auto-negotiation switch, check link status
3093 * based on MAC synchronization for internal serdes media type.
3094 */
8fc897b0
AK		 3095 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3096 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
1da177e4
LT		 3097 /* SYNCH bit and IV bit are sticky. */
3098 udelay(10);
8fc897b0
AK		 3099 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3100 if (!(rxcw & E1000_RXCW_IV)) {
1da177e4
LT		 3101 hw->serdes_link_down = FALSE;
3102 DEBUGOUT("SERDES: Link is up.\n");
3103 }
3104 } else {
3105 hw->serdes_link_down = TRUE;
3106 DEBUGOUT("SERDES: Link is down.\n");
3107 }
3108 }
8fc897b0
AK		 3109 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3110 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
1da177e4
LT		 3111 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3112 }
3113 return E1000_SUCCESS;
3114}
3115
3116/******************************************************************************
3117 * Detects the current speed and duplex settings of the hardware.
3118 *
3119 * hw - Struct containing variables accessed by shared code
3120 * speed - Speed of the connection
3121 * duplex - Duplex setting of the connection
3122 *****************************************************************************/
3123int32_t
3124e1000_get_speed_and_duplex(struct e1000_hw *hw,
3125 uint16_t *speed,
3126 uint16_t *duplex)
3127{
3128 uint32_t status;
3129 int32_t ret_val;
3130 uint16_t phy_data;
3131
3132 DEBUGFUNC("e1000_get_speed_and_duplex");
3133
8fc897b0 3134 if (hw->mac_type >= e1000_82543) {
1da177e4 3135 status = E1000_READ_REG(hw, STATUS);
8fc897b0 3136 if (status & E1000_STATUS_SPEED_1000) {
1da177e4
LT		 3137 *speed = SPEED_1000;
3138 DEBUGOUT("1000 Mbs, ");
8fc897b0 3139 } else if (status & E1000_STATUS_SPEED_100) {
1da177e4
LT		 3140 *speed = SPEED_100;
3141 DEBUGOUT("100 Mbs, ");
3142 } else {
3143 *speed = SPEED_10;
3144 DEBUGOUT("10 Mbs, ");
3145 }
3146
8fc897b0 3147 if (status & E1000_STATUS_FD) {
1da177e4 3148 *duplex = FULL_DUPLEX;
a42a507c 3149 DEBUGOUT("Full Duplex\n");
1da177e4
LT		 3150 } else {
3151 *duplex = HALF_DUPLEX;
a42a507c 3152 DEBUGOUT(" Half Duplex\n");
1da177e4
LT		 3153 }
3154 } else {
a42a507c 3155 DEBUGOUT("1000 Mbs, Full Duplex\n");
1da177e4
LT		 3156 *speed = SPEED_1000;
3157 *duplex = FULL_DUPLEX;
3158 }
3159
3160 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3161 * if it is operating at half duplex. Here we set the duplex settings to
3162 * match the duplex in the link partner's capabilities.
3163 */
8fc897b0 3164 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
1da177e4 3165 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
8fc897b0 3166 if (ret_val)
1da177e4
LT		 3167 return ret_val;
3168
8fc897b0 3169 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
1da177e4
LT		 3170 *duplex = HALF_DUPLEX;
3171 else {
3172 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
8fc897b0 3173 if (ret_val)
1da177e4 3174 return ret_val;
8fc897b0 3175 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
1da177e4
LT		 3176 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3177 *duplex = HALF_DUPLEX;
3178 }
3179 }
3180
76c224bc 3181 if ((hw->mac_type == e1000_80003es2lan) &&
6418ecc6
JK		 3182 (hw->media_type == e1000_media_type_copper)) {
3183 if (*speed == SPEED_1000)
3184 ret_val = e1000_configure_kmrn_for_1000(hw);
3185 else
cd94dd0b
AK		 3186 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3187 if (ret_val)
3188 return ret_val;
3189 }
3190
3191 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3192 ret_val = e1000_kumeran_lock_loss_workaround(hw);
6418ecc6
JK		 3193 if (ret_val)
3194 return ret_val;
3195 }
3196
1da177e4
LT		 3197 return E1000_SUCCESS;
3198}
3199
3200/******************************************************************************
3201* Blocks until autoneg completes or times out (~4.5 seconds)
3202*
3203* hw - Struct containing variables accessed by shared code
3204******************************************************************************/
3ad2cc67 3205static int32_t
1da177e4
LT		 3206e1000_wait_autoneg(struct e1000_hw *hw)
3207{
3208 int32_t ret_val;
3209 uint16_t i;
3210 uint16_t phy_data;
3211
3212 DEBUGFUNC("e1000_wait_autoneg");
3213 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3214
3215 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
8fc897b0 3216 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
1da177e4
LT		 3217 /* Read the MII Status Register and wait for Auto-Neg
3218 * Complete bit to be set.
3219 */
3220 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 3221 if (ret_val)
1da177e4
LT		 3222 return ret_val;
3223 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 3224 if (ret_val)
1da177e4 3225 return ret_val;
8fc897b0 3226 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
1da177e4
LT		 3227 return E1000_SUCCESS;
3228 }
f8ec4733 3229 msleep(100);
1da177e4
LT		 3230 }
3231 return E1000_SUCCESS;
3232}
3233
3234/******************************************************************************
3235* Raises the Management Data Clock
3236*
3237* hw - Struct containing variables accessed by shared code
3238* ctrl - Device control register's current value
3239******************************************************************************/
3240static void
3241e1000_raise_mdi_clk(struct e1000_hw *hw,
3242 uint32_t *ctrl)
3243{
3244 /* Raise the clock input to the Management Data Clock (by setting the MDC
3245 * bit), and then delay 10 microseconds.
3246 */
3247 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3248 E1000_WRITE_FLUSH(hw);
3249 udelay(10);
3250}
3251
3252/******************************************************************************
3253* Lowers the Management Data Clock
3254*
3255* hw - Struct containing variables accessed by shared code
3256* ctrl - Device control register's current value
3257******************************************************************************/
3258static void
3259e1000_lower_mdi_clk(struct e1000_hw *hw,
3260 uint32_t *ctrl)
3261{
3262 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3263 * bit), and then delay 10 microseconds.
3264 */
3265 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3266 E1000_WRITE_FLUSH(hw);
3267 udelay(10);
3268}
3269
3270/******************************************************************************
3271* Shifts data bits out to the PHY
3272*
3273* hw - Struct containing variables accessed by shared code
3274* data - Data to send out to the PHY
3275* count - Number of bits to shift out
3276*
3277* Bits are shifted out in MSB to LSB order.
3278******************************************************************************/
3279static void
3280e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3281 uint32_t data,
3282 uint16_t count)
3283{
3284 uint32_t ctrl;
3285 uint32_t mask;
3286
3287 /* We need to shift "count" number of bits out to the PHY. So, the value
3288 * in the "data" parameter will be shifted out to the PHY one bit at a
3289 * time. In order to do this, "data" must be broken down into bits.
3290 */
3291 mask = 0x01;
3292 mask <<= (count - 1);
3293
3294 ctrl = E1000_READ_REG(hw, CTRL);
3295
3296 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3297 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3298
8fc897b0 3299 while (mask) {
1da177e4
LT		 3300 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3301 * then raising and lowering the Management Data Clock. A "0" is
3302 * shifted out to the PHY by setting the MDIO bit to "0" and then
3303 * raising and lowering the clock.
3304 */
8fc897b0
AK		 3305 if (data & mask)
3306 ctrl |= E1000_CTRL_MDIO;
3307 else
3308 ctrl &= ~E1000_CTRL_MDIO;
1da177e4
LT		 3309
3310 E1000_WRITE_REG(hw, CTRL, ctrl);
3311 E1000_WRITE_FLUSH(hw);
3312
3313 udelay(10);
3314
3315 e1000_raise_mdi_clk(hw, &ctrl);
3316 e1000_lower_mdi_clk(hw, &ctrl);
3317
3318 mask = mask >> 1;
3319 }
3320}
3321
3322/******************************************************************************
3323* Shifts data bits in from the PHY
3324*
3325* hw - Struct containing variables accessed by shared code
3326*
3327* Bits are shifted in in MSB to LSB order.
3328******************************************************************************/
3329static uint16_t
3330e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3331{
3332 uint32_t ctrl;
3333 uint16_t data = 0;
3334 uint8_t i;
3335
3336 /* In order to read a register from the PHY, we need to shift in a total
3337 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3338 * to avoid contention on the MDIO pin when a read operation is performed.
3339 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3340 * by raising the input to the Management Data Clock (setting the MDC bit),
3341 * and then reading the value of the MDIO bit.
3342 */
3343 ctrl = E1000_READ_REG(hw, CTRL);
3344
3345 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3346 ctrl &= ~E1000_CTRL_MDIO_DIR;
3347 ctrl &= ~E1000_CTRL_MDIO;
3348
3349 E1000_WRITE_REG(hw, CTRL, ctrl);
3350 E1000_WRITE_FLUSH(hw);
3351
3352 /* Raise and Lower the clock before reading in the data. This accounts for
3353 * the turnaround bits. The first clock occurred when we clocked out the
3354 * last bit of the Register Address.
3355 */
3356 e1000_raise_mdi_clk(hw, &ctrl);
3357 e1000_lower_mdi_clk(hw, &ctrl);
3358
8fc897b0 3359 for (data = 0, i = 0; i < 16; i++) {
1da177e4
LT		 3360 data = data << 1;
3361 e1000_raise_mdi_clk(hw, &ctrl);
3362 ctrl = E1000_READ_REG(hw, CTRL);
3363 /* Check to see if we shifted in a "1". */
8fc897b0
AK		 3364 if (ctrl & E1000_CTRL_MDIO)
3365 data |= 1;
1da177e4
LT		 3366 e1000_lower_mdi_clk(hw, &ctrl);
3367 }
3368
3369 e1000_raise_mdi_clk(hw, &ctrl);
3370 e1000_lower_mdi_clk(hw, &ctrl);
3371
3372 return data;
3373}
3374
e4c780b1 3375static int32_t
6418ecc6
JK		 3376e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3377{
3378 uint32_t swfw_sync = 0;
3379 uint32_t swmask = mask;
3380 uint32_t fwmask = mask << 16;
3381 int32_t timeout = 200;
3382
3383 DEBUGFUNC("e1000_swfw_sync_acquire");
3384
cd94dd0b
AK		 3385 if (hw->swfwhw_semaphore_present)
3386 return e1000_get_software_flag(hw);
3387
6418ecc6
JK		 3388 if (!hw->swfw_sync_present)
3389 return e1000_get_hw_eeprom_semaphore(hw);
3390
8fc897b0 3391 while (timeout) {
6418ecc6
JK		 3392 if (e1000_get_hw_eeprom_semaphore(hw))
3393 return -E1000_ERR_SWFW_SYNC;
3394
3395 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3396 if (!(swfw_sync & (fwmask | swmask))) {
3397 break;
3398 }
3399
3400 /* firmware currently using resource (fwmask) */
3401 /* or other software thread currently using resource (swmask) */
3402 e1000_put_hw_eeprom_semaphore(hw);
f8ec4733 3403 mdelay(5);
6418ecc6
JK		 3404 timeout--;
3405 }
3406
3407 if (!timeout) {
3408 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3409 return -E1000_ERR_SWFW_SYNC;
3410 }
3411
3412 swfw_sync |= swmask;
3413 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3414
3415 e1000_put_hw_eeprom_semaphore(hw);
3416 return E1000_SUCCESS;
3417}
3418
e4c780b1 3419static void
6418ecc6
JK		 3420e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3421{
3422 uint32_t swfw_sync;
3423 uint32_t swmask = mask;
3424
3425 DEBUGFUNC("e1000_swfw_sync_release");
3426
cd94dd0b
AK		 3427 if (hw->swfwhw_semaphore_present) {
3428 e1000_release_software_flag(hw);
3429 return;
3430 }
3431
6418ecc6
JK		 3432 if (!hw->swfw_sync_present) {
3433 e1000_put_hw_eeprom_semaphore(hw);
3434 return;
3435 }
3436
3437 /* if (e1000_get_hw_eeprom_semaphore(hw))
3438 * return -E1000_ERR_SWFW_SYNC; */
3439 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3440 /* empty */
3441
3442 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3443 swfw_sync &= ~swmask;
3444 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3445
3446 e1000_put_hw_eeprom_semaphore(hw);
3447}
3448
1da177e4
LT		 3449/*****************************************************************************
3450* Reads the value from a PHY register, if the value is on a specific non zero
3451* page, sets the page first.
3452* hw - Struct containing variables accessed by shared code
3453* reg_addr - address of the PHY register to read
3454******************************************************************************/
3455int32_t
3456e1000_read_phy_reg(struct e1000_hw *hw,
3457 uint32_t reg_addr,
3458 uint16_t *phy_data)
3459{
3460 uint32_t ret_val;
6418ecc6 3461 uint16_t swfw;
1da177e4
LT		 3462
3463 DEBUGFUNC("e1000_read_phy_reg");
3464
6418ecc6
JK		 3465 if ((hw->mac_type == e1000_80003es2lan) &&
3466 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3467 swfw = E1000_SWFW_PHY1_SM;
3468 } else {
3469 swfw = E1000_SWFW_PHY0_SM;
3470 }
3471 if (e1000_swfw_sync_acquire(hw, swfw))
3472 return -E1000_ERR_SWFW_SYNC;
3473
cd94dd0b
AK		 3474 if ((hw->phy_type == e1000_phy_igp ||
3475 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 3476 hw->phy_type == e1000_phy_igp_2) &&
1da177e4
LT		 3477 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3478 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3479 (uint16_t)reg_addr);
8fc897b0 3480 if (ret_val) {
6418ecc6 3481 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3482 return ret_val;
3483 }
6418ecc6
JK		 3484 } else if (hw->phy_type == e1000_phy_gg82563) {
3485 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3486 (hw->mac_type == e1000_80003es2lan)) {
3487 /* Select Configuration Page */
3488 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3489 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3490 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3491 } else {
3492 /* Use Alternative Page Select register to access
3493 * registers 30 and 31
3494 */
3495 ret_val = e1000_write_phy_reg_ex(hw,
3496 GG82563_PHY_PAGE_SELECT_ALT,
3497 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3498 }
3499
3500 if (ret_val) {
3501 e1000_swfw_sync_release(hw, swfw);
3502 return ret_val;
3503 }
3504 }
1da177e4
LT		 3505 }
3506
3507 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3508 phy_data);
3509
6418ecc6 3510 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3511 return ret_val;
3512}
3513
35574764
NN		 3514static int32_t
3515e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
1da177e4
LT		 3516 uint16_t *phy_data)
3517{
3518 uint32_t i;
3519 uint32_t mdic = 0;
3520 const uint32_t phy_addr = 1;
3521
3522 DEBUGFUNC("e1000_read_phy_reg_ex");
3523
8fc897b0 3524 if (reg_addr > MAX_PHY_REG_ADDRESS) {
1da177e4
LT		 3525 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3526 return -E1000_ERR_PARAM;
3527 }
3528
8fc897b0 3529 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 3530 /* Set up Op-code, Phy Address, and register address in the MDI
3531 * Control register. The MAC will take care of interfacing with the
3532 * PHY to retrieve the desired data.
3533 */
3534 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3535 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3536 (E1000_MDIC_OP_READ));
3537
3538 E1000_WRITE_REG(hw, MDIC, mdic);
3539
3540 /* Poll the ready bit to see if the MDI read completed */
8fc897b0 3541 for (i = 0; i < 64; i++) {
1da177e4
LT		 3542 udelay(50);
3543 mdic = E1000_READ_REG(hw, MDIC);
8fc897b0 3544 if (mdic & E1000_MDIC_READY) break;
1da177e4 3545 }
8fc897b0 3546 if (!(mdic & E1000_MDIC_READY)) {
1da177e4
LT		 3547 DEBUGOUT("MDI Read did not complete\n");
3548 return -E1000_ERR_PHY;
3549 }
8fc897b0 3550 if (mdic & E1000_MDIC_ERROR) {
1da177e4
LT		 3551 DEBUGOUT("MDI Error\n");
3552 return -E1000_ERR_PHY;
3553 }
3554 *phy_data = (uint16_t) mdic;
3555 } else {
3556 /* We must first send a preamble through the MDIO pin to signal the
3557 * beginning of an MII instruction. This is done by sending 32
3558 * consecutive "1" bits.
3559 */
3560 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3561
3562 /* Now combine the next few fields that are required for a read
3563 * operation. We use this method instead of calling the
3564 * e1000_shift_out_mdi_bits routine five different times. The format of
3565 * a MII read instruction consists of a shift out of 14 bits and is
3566 * defined as follows:
3567 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3568 * followed by a shift in of 18 bits. This first two bits shifted in
3569 * are TurnAround bits used to avoid contention on the MDIO pin when a
3570 * READ operation is performed. These two bits are thrown away
3571 * followed by a shift in of 16 bits which contains the desired data.
3572 */
3573 mdic = ((reg_addr) | (phy_addr << 5) |
3574 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3575
3576 e1000_shift_out_mdi_bits(hw, mdic, 14);
3577
3578 /* Now that we've shifted out the read command to the MII, we need to
3579 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3580 * register address.
3581 */
3582 *phy_data = e1000_shift_in_mdi_bits(hw);
3583 }
3584 return E1000_SUCCESS;
3585}
3586
3587/******************************************************************************
3588* Writes a value to a PHY register
3589*
3590* hw - Struct containing variables accessed by shared code
3591* reg_addr - address of the PHY register to write
3592* data - data to write to the PHY
3593******************************************************************************/
3594int32_t
35574764 3595e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
1da177e4
LT		 3596 uint16_t phy_data)
3597{
3598 uint32_t ret_val;
6418ecc6 3599 uint16_t swfw;
1da177e4
LT		 3600
3601 DEBUGFUNC("e1000_write_phy_reg");
3602
6418ecc6
JK		 3603 if ((hw->mac_type == e1000_80003es2lan) &&
3604 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3605 swfw = E1000_SWFW_PHY1_SM;
3606 } else {
3607 swfw = E1000_SWFW_PHY0_SM;
3608 }
3609 if (e1000_swfw_sync_acquire(hw, swfw))
3610 return -E1000_ERR_SWFW_SYNC;
3611
cd94dd0b
AK		 3612 if ((hw->phy_type == e1000_phy_igp ||
3613 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 3614 hw->phy_type == e1000_phy_igp_2) &&
1da177e4
LT		 3615 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3616 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3617 (uint16_t)reg_addr);
8fc897b0 3618 if (ret_val) {
6418ecc6 3619 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3620 return ret_val;
3621 }
6418ecc6
JK		 3622 } else if (hw->phy_type == e1000_phy_gg82563) {
3623 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3624 (hw->mac_type == e1000_80003es2lan)) {
3625 /* Select Configuration Page */
3626 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3627 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3628 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3629 } else {
3630 /* Use Alternative Page Select register to access
3631 * registers 30 and 31
3632 */
3633 ret_val = e1000_write_phy_reg_ex(hw,
3634 GG82563_PHY_PAGE_SELECT_ALT,
3635 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3636 }
3637
3638 if (ret_val) {
3639 e1000_swfw_sync_release(hw, swfw);
3640 return ret_val;
3641 }
3642 }
1da177e4
LT		 3643 }
3644
3645 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3646 phy_data);
3647
6418ecc6 3648 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3649 return ret_val;
3650}
3651
35574764
NN		 3652static int32_t
3653e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3654 uint16_t phy_data)
1da177e4
LT		 3655{
3656 uint32_t i;
3657 uint32_t mdic = 0;
3658 const uint32_t phy_addr = 1;
3659
3660 DEBUGFUNC("e1000_write_phy_reg_ex");
3661
8fc897b0 3662 if (reg_addr > MAX_PHY_REG_ADDRESS) {
1da177e4
LT		 3663 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3664 return -E1000_ERR_PARAM;
3665 }
3666
8fc897b0 3667 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 3668 /* Set up Op-code, Phy Address, register address, and data intended
3669 * for the PHY register in the MDI Control register. The MAC will take
3670 * care of interfacing with the PHY to send the desired data.
3671 */
3672 mdic = (((uint32_t) phy_data) |
3673 (reg_addr << E1000_MDIC_REG_SHIFT) |
3674 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3675 (E1000_MDIC_OP_WRITE));
3676
3677 E1000_WRITE_REG(hw, MDIC, mdic);
3678
3679 /* Poll the ready bit to see if the MDI read completed */
8fc897b0 3680 for (i = 0; i < 641; i++) {
1da177e4
LT		 3681 udelay(5);
3682 mdic = E1000_READ_REG(hw, MDIC);
8fc897b0 3683 if (mdic & E1000_MDIC_READY) break;
1da177e4 3684 }
8fc897b0 3685 if (!(mdic & E1000_MDIC_READY)) {
1da177e4
LT		 3686 DEBUGOUT("MDI Write did not complete\n");
3687 return -E1000_ERR_PHY;
3688 }
3689 } else {
3690 /* We'll need to use the SW defined pins to shift the write command
3691 * out to the PHY. We first send a preamble to the PHY to signal the
3692 * beginning of the MII instruction. This is done by sending 32
3693 * consecutive "1" bits.
3694 */
3695 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3696
3697 /* Now combine the remaining required fields that will indicate a
3698 * write operation. We use this method instead of calling the
3699 * e1000_shift_out_mdi_bits routine for each field in the command. The
3700 * format of a MII write instruction is as follows:
3701 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3702 */
3703 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3704 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3705 mdic <<= 16;
3706 mdic |= (uint32_t) phy_data;
3707
3708 e1000_shift_out_mdi_bits(hw, mdic, 32);
3709 }
3710
3711 return E1000_SUCCESS;
3712}
3713
e4c780b1 3714static int32_t
6418ecc6
JK		 3715e1000_read_kmrn_reg(struct e1000_hw *hw,
3716 uint32_t reg_addr,
3717 uint16_t *data)
3718{
3719 uint32_t reg_val;
3720 uint16_t swfw;
3721 DEBUGFUNC("e1000_read_kmrn_reg");
3722
3723 if ((hw->mac_type == e1000_80003es2lan) &&
3724 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3725 swfw = E1000_SWFW_PHY1_SM;
3726 } else {
3727 swfw = E1000_SWFW_PHY0_SM;
3728 }
3729 if (e1000_swfw_sync_acquire(hw, swfw))
3730 return -E1000_ERR_SWFW_SYNC;
3731
3732 /* Write register address */
3733 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3734 E1000_KUMCTRLSTA_OFFSET) |
3735 E1000_KUMCTRLSTA_REN;
3736 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3737 udelay(2);
3738
3739 /* Read the data returned */
3740 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3741 *data = (uint16_t)reg_val;
3742
3743 e1000_swfw_sync_release(hw, swfw);
3744 return E1000_SUCCESS;
3745}
3746
e4c780b1 3747static int32_t
6418ecc6
JK		 3748e1000_write_kmrn_reg(struct e1000_hw *hw,
3749 uint32_t reg_addr,
3750 uint16_t data)
3751{
3752 uint32_t reg_val;
3753 uint16_t swfw;
3754 DEBUGFUNC("e1000_write_kmrn_reg");
3755
3756 if ((hw->mac_type == e1000_80003es2lan) &&
3757 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3758 swfw = E1000_SWFW_PHY1_SM;
3759 } else {
3760 swfw = E1000_SWFW_PHY0_SM;
3761 }
3762 if (e1000_swfw_sync_acquire(hw, swfw))
3763 return -E1000_ERR_SWFW_SYNC;
3764
3765 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3766 E1000_KUMCTRLSTA_OFFSET) | data;
3767 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3768 udelay(2);
3769
3770 e1000_swfw_sync_release(hw, swfw);
3771 return E1000_SUCCESS;
3772}
2d7edb92 3773
1da177e4
LT		 3774/******************************************************************************
3775* Returns the PHY to the power-on reset state
3776*
3777* hw - Struct containing variables accessed by shared code
3778******************************************************************************/
2d7edb92 3779int32_t
1da177e4
LT		 3780e1000_phy_hw_reset(struct e1000_hw *hw)
3781{
3782 uint32_t ctrl, ctrl_ext;
3783 uint32_t led_ctrl;
2d7edb92 3784 int32_t ret_val;
6418ecc6 3785 uint16_t swfw;
1da177e4
LT		 3786
3787 DEBUGFUNC("e1000_phy_hw_reset");
3788
2d7edb92
MC		 3789 /* In the case of the phy reset being blocked, it's not an error, we
3790 * simply return success without performing the reset. */
3791 ret_val = e1000_check_phy_reset_block(hw);
3792 if (ret_val)
3793 return E1000_SUCCESS;
3794
1da177e4
LT		 3795 DEBUGOUT("Resetting Phy...\n");
3796
8fc897b0 3797 if (hw->mac_type > e1000_82543) {
6418ecc6
JK		 3798 if ((hw->mac_type == e1000_80003es2lan) &&
3799 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3800 swfw = E1000_SWFW_PHY1_SM;
3801 } else {
3802 swfw = E1000_SWFW_PHY0_SM;
3803 }
3804 if (e1000_swfw_sync_acquire(hw, swfw)) {
2a88c173 3805 DEBUGOUT("Unable to acquire swfw sync\n");
6418ecc6
JK		 3806 return -E1000_ERR_SWFW_SYNC;
3807 }
1da177e4
LT		 3808 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3809 * bit. Then, take it out of reset.
76c224bc 3810 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
fd803241 3811 * and deassert. For e1000_82571 hardware and later, we instead delay
0f15a8fa 3812 * for 50us between and 10ms after the deassertion.
1da177e4
LT		 3813 */
3814 ctrl = E1000_READ_REG(hw, CTRL);
3815 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3816 E1000_WRITE_FLUSH(hw);
76c224bc
AK		 3817
3818 if (hw->mac_type < e1000_82571)
f8ec4733 3819 msleep(10);
b55ccb35
JK		 3820 else
3821 udelay(100);
76c224bc 3822
1da177e4
LT		 3823 E1000_WRITE_REG(hw, CTRL, ctrl);
3824 E1000_WRITE_FLUSH(hw);
76c224bc 3825
fd803241 3826 if (hw->mac_type >= e1000_82571)
f8ec4733 3827 mdelay(10);
35574764 3828
6418ecc6 3829 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3830 } else {
3831 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3832 * bit to put the PHY into reset. Then, take it out of reset.
3833 */
3834 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3835 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3836 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3837 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3838 E1000_WRITE_FLUSH(hw);
f8ec4733 3839 msleep(10);
1da177e4
LT		 3840 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3841 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3842 E1000_WRITE_FLUSH(hw);
3843 }
3844 udelay(150);
3845
8fc897b0 3846 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1da177e4
LT		 3847 /* Configure activity LED after PHY reset */
3848 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3849 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3850 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3851 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3852 }
2d7edb92
MC		 3853
3854 /* Wait for FW to finish PHY configuration. */
3855 ret_val = e1000_get_phy_cfg_done(hw);
8fc897b0
AK		 3856 if (ret_val != E1000_SUCCESS)
3857 return ret_val;
6418ecc6 3858 e1000_release_software_semaphore(hw);
2d7edb92 3859
8fc897b0
AK		 3860 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3861 ret_val = e1000_init_lcd_from_nvm(hw);
3862
2d7edb92 3863 return ret_val;
1da177e4
LT		 3864}
3865
3866/******************************************************************************
3867* Resets the PHY
3868*
3869* hw - Struct containing variables accessed by shared code
3870*
3871* Sets bit 15 of the MII Control regiser
3872******************************************************************************/
3873int32_t
3874e1000_phy_reset(struct e1000_hw *hw)
3875{
3876 int32_t ret_val;
3877 uint16_t phy_data;
3878
3879 DEBUGFUNC("e1000_phy_reset");
3880
2d7edb92
MC		 3881 /* In the case of the phy reset being blocked, it's not an error, we
3882 * simply return success without performing the reset. */
3883 ret_val = e1000_check_phy_reset_block(hw);
3884 if (ret_val)
3885 return E1000_SUCCESS;
3886
2a88c173
JK		 3887 switch (hw->phy_type) {
3888 case e1000_phy_igp:
3889 case e1000_phy_igp_2:
3890 case e1000_phy_igp_3:
3891 case e1000_phy_ife:
2d7edb92 3892 ret_val = e1000_phy_hw_reset(hw);
8fc897b0 3893 if (ret_val)
2d7edb92
MC		 3894 return ret_val;
3895 break;
3896 default:
1da177e4 3897 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8fc897b0 3898 if (ret_val)
1da177e4
LT		 3899 return ret_val;
3900
3901 phy_data |= MII_CR_RESET;
3902 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8fc897b0 3903 if (ret_val)
1da177e4
LT		 3904 return ret_val;
3905
3906 udelay(1);
2d7edb92
MC		 3907 break;
3908 }
1da177e4 3909
8fc897b0 3910 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
1da177e4
LT		 3911 e1000_phy_init_script(hw);
3912
3913 return E1000_SUCCESS;
3914}
3915
d37ea5d5
AK		 3916/******************************************************************************
3917* Work-around for 82566 power-down: on D3 entry-
3918* 1) disable gigabit link
3919* 2) write VR power-down enable
3920* 3) read it back
3921* if successful continue, else issue LCD reset and repeat
3922*
3923* hw - struct containing variables accessed by shared code
3924******************************************************************************/
3925void
3926e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3927{
3928 int32_t reg;
3929 uint16_t phy_data;
3930 int32_t retry = 0;
3931
3932 DEBUGFUNC("e1000_phy_powerdown_workaround");
3933
3934 if (hw->phy_type != e1000_phy_igp_3)
3935 return;
3936
3937 do {
3938 /* Disable link */
3939 reg = E1000_READ_REG(hw, PHY_CTRL);
3940 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3941 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3942
3943 /* Write VR power-down enable */
3944 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3945 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3946 IGP3_VR_CTRL_MODE_SHUT);
3947
3948 /* Read it back and test */
3949 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3950 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3951 break;
3952
3953 /* Issue PHY reset and repeat at most one more time */
3954 reg = E1000_READ_REG(hw, CTRL);
3955 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3956 retry++;
3957 } while (retry);
3958
3959 return;
3960
3961}
3962
3963/******************************************************************************
3964* Work-around for 82566 Kumeran PCS lock loss:
3965* On link status change (i.e. PCI reset, speed change) and link is up and
3966* speed is gigabit-
3967* 0) if workaround is optionally disabled do nothing
3968* 1) wait 1ms for Kumeran link to come up
3969* 2) check Kumeran Diagnostic register PCS lock loss bit
3970* 3) if not set the link is locked (all is good), otherwise...
3971* 4) reset the PHY
3972* 5) repeat up to 10 times
3973* Note: this is only called for IGP3 copper when speed is 1gb.
3974*
3975* hw - struct containing variables accessed by shared code
3976******************************************************************************/
e4c780b1 3977static int32_t
d37ea5d5
AK		 3978e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3979{
3980 int32_t ret_val;
3981 int32_t reg;
3982 int32_t cnt;
3983 uint16_t phy_data;
3984
3985 if (hw->kmrn_lock_loss_workaround_disabled)
3986 return E1000_SUCCESS;
3987
8fc897b0
AK		 3988 /* Make sure link is up before proceeding. If not just return.
3989 * Attempting this while link is negotiating fouled up link
d37ea5d5
AK		 3990 * stability */
3991 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3992 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3993
3994 if (phy_data & MII_SR_LINK_STATUS) {
3995 for (cnt = 0; cnt < 10; cnt++) {
3996 /* read once to clear */
3997 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3998 if (ret_val)
3999 return ret_val;
4000 /* and again to get new status */
4001 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4002 if (ret_val)
4003 return ret_val;
4004
4005 /* check for PCS lock */
4006 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4007 return E1000_SUCCESS;
4008
4009 /* Issue PHY reset */
4010 e1000_phy_hw_reset(hw);
f8ec4733 4011 mdelay(5);
d37ea5d5
AK		 4012 }
4013 /* Disable GigE link negotiation */
4014 reg = E1000_READ_REG(hw, PHY_CTRL);
4015 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4016 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4017
4018 /* unable to acquire PCS lock */
4019 return E1000_ERR_PHY;
4020 }
4021
4022 return E1000_SUCCESS;
4023}
4024
1da177e4
LT		 4025/******************************************************************************
4026* Probes the expected PHY address for known PHY IDs
4027*
4028* hw - Struct containing variables accessed by shared code
4029******************************************************************************/
35574764 4030static int32_t
1da177e4
LT		 4031e1000_detect_gig_phy(struct e1000_hw *hw)
4032{
4033 int32_t phy_init_status, ret_val;
4034 uint16_t phy_id_high, phy_id_low;
4035 boolean_t match = FALSE;
4036
4037 DEBUGFUNC("e1000_detect_gig_phy");
4038
2a88c173
JK		 4039 if (hw->phy_id != 0)
4040 return E1000_SUCCESS;
4041
868d5309
MC		 4042 /* The 82571 firmware may still be configuring the PHY. In this
4043 * case, we cannot access the PHY until the configuration is done. So
4044 * we explicitly set the PHY values. */
cd94dd0b
AK		 4045 if (hw->mac_type == e1000_82571 ||
4046 hw->mac_type == e1000_82572) {
868d5309
MC		 4047 hw->phy_id = IGP01E1000_I_PHY_ID;
4048 hw->phy_type = e1000_phy_igp_2;
4049 return E1000_SUCCESS;
4050 }
4051
6418ecc6
JK		 4052 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4053 * around that forces PHY page 0 to be set or the reads fail. The rest of
4054 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4055 * So for ESB-2 we need to have this set so our reads won't fail. If the
4056 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4057 * this out as well. */
4058 if (hw->mac_type == e1000_80003es2lan)
4059 hw->phy_type = e1000_phy_gg82563;
4060
1da177e4
LT		 4061 /* Read the PHY ID Registers to identify which PHY is onboard. */
4062 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
cd94dd0b 4063 if (ret_val)
1da177e4
LT		 4064 return ret_val;
4065
4066 hw->phy_id = (uint32_t) (phy_id_high << 16);
4067 udelay(20);
4068 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
8fc897b0 4069 if (ret_val)
1da177e4
LT		 4070 return ret_val;
4071
4072 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4073 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4074
8fc897b0 4075 switch (hw->mac_type) {
1da177e4 4076 case e1000_82543:
8fc897b0 4077 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
1da177e4
LT		 4078 break;
4079 case e1000_82544:
8fc897b0 4080 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
1da177e4
LT		 4081 break;
4082 case e1000_82540:
4083 case e1000_82545:
4084 case e1000_82545_rev_3:
4085 case e1000_82546:
4086 case e1000_82546_rev_3:
8fc897b0 4087 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
1da177e4
LT		 4088 break;
4089 case e1000_82541:
4090 case e1000_82541_rev_2:
4091 case e1000_82547:
4092 case e1000_82547_rev_2:
8fc897b0 4093 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
1da177e4 4094 break;
2d7edb92 4095 case e1000_82573:
8fc897b0 4096 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
2d7edb92 4097 break;
6418ecc6
JK		 4098 case e1000_80003es2lan:
4099 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4100 break;
cd94dd0b
AK		 4101 case e1000_ich8lan:
4102 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4103 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4104 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4105 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4106 break;
1da177e4
LT		 4107 default:
4108 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4109 return -E1000_ERR_CONFIG;
4110 }
4111 phy_init_status = e1000_set_phy_type(hw);
4112
4113 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4114 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4115 return E1000_SUCCESS;
4116 }
4117 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4118 return -E1000_ERR_PHY;
4119}
4120
4121/******************************************************************************
4122* Resets the PHY's DSP
4123*
4124* hw - Struct containing variables accessed by shared code
4125******************************************************************************/
4126static int32_t
4127e1000_phy_reset_dsp(struct e1000_hw *hw)
4128{
4129 int32_t ret_val;
4130 DEBUGFUNC("e1000_phy_reset_dsp");
4131
4132 do {
6418ecc6
JK		 4133 if (hw->phy_type != e1000_phy_gg82563) {
4134 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
8fc897b0 4135 if (ret_val) break;
6418ecc6 4136 }
1da177e4 4137 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
8fc897b0 4138 if (ret_val) break;
1da177e4 4139 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
8fc897b0 4140 if (ret_val) break;
1da177e4 4141 ret_val = E1000_SUCCESS;
8fc897b0 4142 } while (0);
1da177e4
LT		 4143
4144 return ret_val;
4145}
4146
4147/******************************************************************************
4148* Get PHY information from various PHY registers for igp PHY only.
4149*
4150* hw - Struct containing variables accessed by shared code
4151* phy_info - PHY information structure
4152******************************************************************************/
cff93eb3 4153static int32_t
1da177e4
LT		 4154e1000_phy_igp_get_info(struct e1000_hw *hw,
4155 struct e1000_phy_info *phy_info)
4156{
4157 int32_t ret_val;
70c6f30a
JK		 4158 uint16_t phy_data, min_length, max_length, average;
4159 e1000_rev_polarity polarity;
1da177e4
LT		 4160
4161 DEBUGFUNC("e1000_phy_igp_get_info");
4162
4163 /* The downshift status is checked only once, after link is established,
4164 * and it stored in the hw->speed_downgraded parameter. */
2d7edb92 4165 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
1da177e4
LT		 4166
4167 /* IGP01E1000 does not need to support it. */
4168 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4169
4170 /* IGP01E1000 always correct polarity reversal */
4171 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4172
4173 /* Check polarity status */
4174 ret_val = e1000_check_polarity(hw, &polarity);
8fc897b0 4175 if (ret_val)
1da177e4
LT		 4176 return ret_val;
4177
4178 phy_info->cable_polarity = polarity;
4179
4180 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
8fc897b0 4181 if (ret_val)
1da177e4
LT		 4182 return ret_val;
4183
70c6f30a
JK		 4184 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4185 IGP01E1000_PSSR_MDIX_SHIFT);
1da177e4 4186
8fc897b0 4187 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1da177e4
LT		 4188 IGP01E1000_PSSR_SPEED_1000MBPS) {
4189 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4190 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
8fc897b0 4191 if (ret_val)
1da177e4
LT		 4192 return ret_val;
4193
70c6f30a
JK		 4194 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4195 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4196 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4197 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4198 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4199 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1da177e4
LT		 4200
4201 /* Get cable length */
4202 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
8fc897b0 4203 if (ret_val)
1da177e4
LT		 4204 return ret_val;
4205
2d7edb92 4206 /* Translate to old method */
1da177e4
LT		 4207 average = (max_length + min_length) / 2;
4208
8fc897b0 4209 if (average <= e1000_igp_cable_length_50)
1da177e4 4210 phy_info->cable_length = e1000_cable_length_50;
8fc897b0 4211 else if (average <= e1000_igp_cable_length_80)
1da177e4 4212 phy_info->cable_length = e1000_cable_length_50_80;
8fc897b0 4213 else if (average <= e1000_igp_cable_length_110)
1da177e4 4214 phy_info->cable_length = e1000_cable_length_80_110;
8fc897b0 4215 else if (average <= e1000_igp_cable_length_140)
1da177e4
LT		 4216 phy_info->cable_length = e1000_cable_length_110_140;
4217 else
4218 phy_info->cable_length = e1000_cable_length_140;
4219 }
4220
4221 return E1000_SUCCESS;
4222}
4223
d37ea5d5
AK		 4224/******************************************************************************
4225* Get PHY information from various PHY registers for ife PHY only.
4226*
4227* hw - Struct containing variables accessed by shared code
4228* phy_info - PHY information structure
4229******************************************************************************/
e4c780b1 4230static int32_t
d37ea5d5
AK		 4231e1000_phy_ife_get_info(struct e1000_hw *hw,
4232 struct e1000_phy_info *phy_info)
4233{
4234 int32_t ret_val;
70c6f30a
JK		 4235 uint16_t phy_data;
4236 e1000_rev_polarity polarity;
d37ea5d5
AK		 4237
4238 DEBUGFUNC("e1000_phy_ife_get_info");
4239
4240 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4241 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4242
4243 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4244 if (ret_val)
4245 return ret_val;
4246 phy_info->polarity_correction =
70c6f30a
JK		 4247 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4248 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4249 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
d37ea5d5
AK		 4250
4251 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4252 ret_val = e1000_check_polarity(hw, &polarity);
4253 if (ret_val)
4254 return ret_val;
4255 } else {
4256 /* Polarity is forced. */
70c6f30a
JK		 4257 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4258 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4259 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
d37ea5d5
AK		 4260 }
4261 phy_info->cable_polarity = polarity;
4262
4263 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4264 if (ret_val)
4265 return ret_val;
4266
70c6f30a
JK		 4267 phy_info->mdix_mode = (e1000_auto_x_mode)
4268 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4269 IFE_PMC_MDIX_MODE_SHIFT);
d37ea5d5
AK		 4270
4271 return E1000_SUCCESS;
4272}
4273
1da177e4
LT		 4274/******************************************************************************
4275* Get PHY information from various PHY registers fot m88 PHY only.
4276*
4277* hw - Struct containing variables accessed by shared code
4278* phy_info - PHY information structure
4279******************************************************************************/
3ad2cc67 4280static int32_t
1da177e4
LT		 4281e1000_phy_m88_get_info(struct e1000_hw *hw,
4282 struct e1000_phy_info *phy_info)
4283{
4284 int32_t ret_val;
70c6f30a
JK		 4285 uint16_t phy_data;
4286 e1000_rev_polarity polarity;
1da177e4
LT		 4287
4288 DEBUGFUNC("e1000_phy_m88_get_info");
4289
4290 /* The downshift status is checked only once, after link is established,
4291 * and it stored in the hw->speed_downgraded parameter. */
2d7edb92 4292 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
1da177e4
LT		 4293
4294 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 4295 if (ret_val)
1da177e4
LT		 4296 return ret_val;
4297
4298 phy_info->extended_10bt_distance =
70c6f30a
JK		 4299 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4300 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4301 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4302
1da177e4 4303 phy_info->polarity_correction =
70c6f30a
JK		 4304 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4305 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4306 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
1da177e4
LT		 4307
4308 /* Check polarity status */
4309 ret_val = e1000_check_polarity(hw, &polarity);
8fc897b0 4310 if (ret_val)
76c224bc 4311 return ret_val;
1da177e4
LT		 4312 phy_info->cable_polarity = polarity;
4313
4314 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
8fc897b0 4315 if (ret_val)
1da177e4
LT		 4316 return ret_val;
4317
70c6f30a
JK		 4318 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4319 M88E1000_PSSR_MDIX_SHIFT);
1da177e4
LT		 4320
4321 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4322 /* Cable Length Estimation and Local/Remote Receiver Information
4323 * are only valid at 1000 Mbps.
4324 */
6418ecc6 4325 if (hw->phy_type != e1000_phy_gg82563) {
70c6f30a 4326 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6418ecc6
JK		 4327 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4328 } else {
4329 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4330 &phy_data);
4331 if (ret_val)
4332 return ret_val;
4333
70c6f30a 4334 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
6418ecc6 4335 }
1da177e4
LT		 4336
4337 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
8fc897b0 4338 if (ret_val)
1da177e4
LT		 4339 return ret_val;
4340
70c6f30a
JK		 4341 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4342 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4343 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4344 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4345 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4346 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1da177e4 4347
1da177e4
LT		 4348 }
4349
4350 return E1000_SUCCESS;
4351}
4352
4353/******************************************************************************
4354* Get PHY information from various PHY registers
4355*
4356* hw - Struct containing variables accessed by shared code
4357* phy_info - PHY information structure
4358******************************************************************************/
4359int32_t
4360e1000_phy_get_info(struct e1000_hw *hw,
4361 struct e1000_phy_info *phy_info)
4362{
4363 int32_t ret_val;
4364 uint16_t phy_data;
4365
4366 DEBUGFUNC("e1000_phy_get_info");
4367
4368 phy_info->cable_length = e1000_cable_length_undefined;
4369 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4370 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4371 phy_info->downshift = e1000_downshift_undefined;
4372 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4373 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4374 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4375 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4376
8fc897b0 4377 if (hw->media_type != e1000_media_type_copper) {
1da177e4
LT		 4378 DEBUGOUT("PHY info is only valid for copper media\n");
4379 return -E1000_ERR_CONFIG;
4380 }
4381
4382 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 4383 if (ret_val)
1da177e4
LT		 4384 return ret_val;
4385
4386 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 4387 if (ret_val)
1da177e4
LT		 4388 return ret_val;
4389
8fc897b0 4390 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
1da177e4
LT		 4391 DEBUGOUT("PHY info is only valid if link is up\n");
4392 return -E1000_ERR_CONFIG;
4393 }
4394
cd94dd0b
AK		 4395 if (hw->phy_type == e1000_phy_igp ||
4396 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 4397 hw->phy_type == e1000_phy_igp_2)
1da177e4 4398 return e1000_phy_igp_get_info(hw, phy_info);
cd94dd0b
AK		 4399 else if (hw->phy_type == e1000_phy_ife)
4400 return e1000_phy_ife_get_info(hw, phy_info);
1da177e4
LT		 4401 else
4402 return e1000_phy_m88_get_info(hw, phy_info);
4403}
4404
4405int32_t
4406e1000_validate_mdi_setting(struct e1000_hw *hw)
4407{
4408 DEBUGFUNC("e1000_validate_mdi_settings");
4409
8fc897b0 4410 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
1da177e4
LT		 4411 DEBUGOUT("Invalid MDI setting detected\n");
4412 hw->mdix = 1;
4413 return -E1000_ERR_CONFIG;
4414 }
4415 return E1000_SUCCESS;
4416}
4417
4418
4419/******************************************************************************
4420 * Sets up eeprom variables in the hw struct. Must be called after mac_type
0f15a8fa
JK		 4421 * is configured. Additionally, if this is ICH8, the flash controller GbE
4422 * registers must be mapped, or this will crash.
1da177e4
LT		 4423 *
4424 * hw - Struct containing variables accessed by shared code
4425 *****************************************************************************/
2d7edb92 4426int32_t
1da177e4
LT		 4427e1000_init_eeprom_params(struct e1000_hw *hw)
4428{
4429 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4430 uint32_t eecd = E1000_READ_REG(hw, EECD);
2d7edb92 4431 int32_t ret_val = E1000_SUCCESS;
1da177e4
LT		 4432 uint16_t eeprom_size;
4433
4434 DEBUGFUNC("e1000_init_eeprom_params");
4435
4436 switch (hw->mac_type) {
4437 case e1000_82542_rev2_0:
4438 case e1000_82542_rev2_1:
4439 case e1000_82543:
4440 case e1000_82544:
4441 eeprom->type = e1000_eeprom_microwire;
4442 eeprom->word_size = 64;
4443 eeprom->opcode_bits = 3;
4444 eeprom->address_bits = 6;
4445 eeprom->delay_usec = 50;
2d7edb92
MC		 4446 eeprom->use_eerd = FALSE;
4447 eeprom->use_eewr = FALSE;
1da177e4
LT		 4448 break;
4449 case e1000_82540:
4450 case e1000_82545:
4451 case e1000_82545_rev_3:
4452 case e1000_82546:
4453 case e1000_82546_rev_3:
4454 eeprom->type = e1000_eeprom_microwire;
4455 eeprom->opcode_bits = 3;
4456 eeprom->delay_usec = 50;
8fc897b0 4457 if (eecd & E1000_EECD_SIZE) {
1da177e4
LT		 4458 eeprom->word_size = 256;
4459 eeprom->address_bits = 8;
4460 } else {
4461 eeprom->word_size = 64;
4462 eeprom->address_bits = 6;
4463 }
2d7edb92
MC		 4464 eeprom->use_eerd = FALSE;
4465 eeprom->use_eewr = FALSE;
1da177e4
LT		 4466 break;
4467 case e1000_82541:
4468 case e1000_82541_rev_2:
4469 case e1000_82547:
4470 case e1000_82547_rev_2:
4471 if (eecd & E1000_EECD_TYPE) {
4472 eeprom->type = e1000_eeprom_spi;
4473 eeprom->opcode_bits = 8;
4474 eeprom->delay_usec = 1;
4475 if (eecd & E1000_EECD_ADDR_BITS) {
4476 eeprom->page_size = 32;
4477 eeprom->address_bits = 16;
4478 } else {
4479 eeprom->page_size = 8;
4480 eeprom->address_bits = 8;
4481 }
4482 } else {
4483 eeprom->type = e1000_eeprom_microwire;
4484 eeprom->opcode_bits = 3;
4485 eeprom->delay_usec = 50;
4486 if (eecd & E1000_EECD_ADDR_BITS) {
4487 eeprom->word_size = 256;
4488 eeprom->address_bits = 8;
4489 } else {
4490 eeprom->word_size = 64;
4491 eeprom->address_bits = 6;
4492 }
4493 }
2d7edb92
MC		 4494 eeprom->use_eerd = FALSE;
4495 eeprom->use_eewr = FALSE;
4496 break;
868d5309
MC		 4497 case e1000_82571:
4498 case e1000_82572:
4499 eeprom->type = e1000_eeprom_spi;
4500 eeprom->opcode_bits = 8;
4501 eeprom->delay_usec = 1;
4502 if (eecd & E1000_EECD_ADDR_BITS) {
4503 eeprom->page_size = 32;
4504 eeprom->address_bits = 16;
4505 } else {
4506 eeprom->page_size = 8;
4507 eeprom->address_bits = 8;
4508 }
4509 eeprom->use_eerd = FALSE;
4510 eeprom->use_eewr = FALSE;
4511 break;
2d7edb92
MC		 4512 case e1000_82573:
4513 eeprom->type = e1000_eeprom_spi;
4514 eeprom->opcode_bits = 8;
4515 eeprom->delay_usec = 1;
4516 if (eecd & E1000_EECD_ADDR_BITS) {
4517 eeprom->page_size = 32;
4518 eeprom->address_bits = 16;
4519 } else {
4520 eeprom->page_size = 8;
4521 eeprom->address_bits = 8;
4522 }
4523 eeprom->use_eerd = TRUE;
4524 eeprom->use_eewr = TRUE;
8fc897b0 4525 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
2d7edb92
MC		 4526 eeprom->type = e1000_eeprom_flash;
4527 eeprom->word_size = 2048;
4528
4529 /* Ensure that the Autonomous FLASH update bit is cleared due to
4530 * Flash update issue on parts which use a FLASH for NVM. */
4531 eecd &= ~E1000_EECD_AUPDEN;
4532 E1000_WRITE_REG(hw, EECD, eecd);
4533 }
1da177e4 4534 break;
6418ecc6
JK		 4535 case e1000_80003es2lan:
4536 eeprom->type = e1000_eeprom_spi;
4537 eeprom->opcode_bits = 8;
4538 eeprom->delay_usec = 1;
4539 if (eecd & E1000_EECD_ADDR_BITS) {
4540 eeprom->page_size = 32;
4541 eeprom->address_bits = 16;
4542 } else {
4543 eeprom->page_size = 8;
4544 eeprom->address_bits = 8;
4545 }
4546 eeprom->use_eerd = TRUE;
4547 eeprom->use_eewr = FALSE;
4548 break;
cd94dd0b 4549 case e1000_ich8lan:
35574764 4550 {
cd94dd0b
AK		 4551 int32_t i = 0;
4552 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4553
4554 eeprom->type = e1000_eeprom_ich8;
4555 eeprom->use_eerd = FALSE;
4556 eeprom->use_eewr = FALSE;
4557 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4558
4559 /* Zero the shadow RAM structure. But don't load it from NVM
4560 * so as to save time for driver init */
4561 if (hw->eeprom_shadow_ram != NULL) {
4562 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4563 hw->eeprom_shadow_ram[i].modified = FALSE;
4564 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4565 }
4566 }
4567
4568 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4569 ICH8_FLASH_SECTOR_SIZE;
4570
4571 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4572 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4573 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4574 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4575
4576 break;
35574764 4577 }
1da177e4
LT		 4578 default:
4579 break;
4580 }
4581
4582 if (eeprom->type == e1000_eeprom_spi) {
2d7edb92
MC		 4583 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4584 * 32KB (incremented by powers of 2).
4585 */
8fc897b0 4586 if (hw->mac_type <= e1000_82547_rev_2) {
2d7edb92
MC		 4587 /* Set to default value for initial eeprom read. */
4588 eeprom->word_size = 64;
4589 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
8fc897b0 4590 if (ret_val)
2d7edb92
MC		 4591 return ret_val;
4592 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4593 /* 256B eeprom size was not supported in earlier hardware, so we
4594 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4595 * is never the result used in the shifting logic below. */
8fc897b0 4596 if (eeprom_size)
2d7edb92
MC		 4597 eeprom_size++;
4598 } else {
4599 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4600 E1000_EECD_SIZE_EX_SHIFT);
1da177e4 4601 }
2d7edb92
MC		 4602
4603 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
1da177e4 4604 }
2d7edb92 4605 return ret_val;
1da177e4
LT		 4606}
4607
4608/******************************************************************************
4609 * Raises the EEPROM's clock input.
4610 *
4611 * hw - Struct containing variables accessed by shared code
4612 * eecd - EECD's current value
4613 *****************************************************************************/
4614static void
4615e1000_raise_ee_clk(struct e1000_hw *hw,
4616 uint32_t *eecd)
4617{
4618 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4619 * wait <delay> microseconds.
4620 */
4621 *eecd = *eecd | E1000_EECD_SK;
4622 E1000_WRITE_REG(hw, EECD, *eecd);
4623 E1000_WRITE_FLUSH(hw);
4624 udelay(hw->eeprom.delay_usec);
4625}
4626
4627/******************************************************************************
4628 * Lowers the EEPROM's clock input.
4629 *
4630 * hw - Struct containing variables accessed by shared code
4631 * eecd - EECD's current value
4632 *****************************************************************************/
4633static void
4634e1000_lower_ee_clk(struct e1000_hw *hw,
4635 uint32_t *eecd)
4636{
4637 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4638 * wait 50 microseconds.
4639 */
4640 *eecd = *eecd & ~E1000_EECD_SK;
4641 E1000_WRITE_REG(hw, EECD, *eecd);
4642 E1000_WRITE_FLUSH(hw);
4643 udelay(hw->eeprom.delay_usec);
4644}
4645
4646/******************************************************************************
4647 * Shift data bits out to the EEPROM.
4648 *
4649 * hw - Struct containing variables accessed by shared code
4650 * data - data to send to the EEPROM
4651 * count - number of bits to shift out
4652 *****************************************************************************/
4653static void
4654e1000_shift_out_ee_bits(struct e1000_hw *hw,
4655 uint16_t data,
4656 uint16_t count)
4657{
4658 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4659 uint32_t eecd;
4660 uint32_t mask;
4661
4662 /* We need to shift "count" bits out to the EEPROM. So, value in the
4663 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4664 * In order to do this, "data" must be broken down into bits.
4665 */
4666 mask = 0x01 << (count - 1);
4667 eecd = E1000_READ_REG(hw, EECD);
4668 if (eeprom->type == e1000_eeprom_microwire) {
4669 eecd &= ~E1000_EECD_DO;
4670 } else if (eeprom->type == e1000_eeprom_spi) {
4671 eecd |= E1000_EECD_DO;
4672 }
4673 do {
4674 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4675 * and then raising and then lowering the clock (the SK bit controls
4676 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4677 * by setting "DI" to "0" and then raising and then lowering the clock.
4678 */
4679 eecd &= ~E1000_EECD_DI;
4680
8fc897b0 4681 if (data & mask)
1da177e4
LT		 4682 eecd |= E1000_EECD_DI;
4683
4684 E1000_WRITE_REG(hw, EECD, eecd);
4685 E1000_WRITE_FLUSH(hw);
4686
4687 udelay(eeprom->delay_usec);
4688
4689 e1000_raise_ee_clk(hw, &eecd);
4690 e1000_lower_ee_clk(hw, &eecd);
4691
4692 mask = mask >> 1;
4693
8fc897b0 4694 } while (mask);
1da177e4
LT		 4695
4696 /* We leave the "DI" bit set to "0" when we leave this routine. */
4697 eecd &= ~E1000_EECD_DI;
4698 E1000_WRITE_REG(hw, EECD, eecd);
4699}
4700
4701/******************************************************************************
4702 * Shift data bits in from the EEPROM
4703 *
4704 * hw - Struct containing variables accessed by shared code
4705 *****************************************************************************/
4706static uint16_t
4707e1000_shift_in_ee_bits(struct e1000_hw *hw,
4708 uint16_t count)
4709{
4710 uint32_t eecd;
4711 uint32_t i;
4712 uint16_t data;
4713
4714 /* In order to read a register from the EEPROM, we need to shift 'count'
4715 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4716 * input to the EEPROM (setting the SK bit), and then reading the value of
4717 * the "DO" bit. During this "shifting in" process the "DI" bit should
4718 * always be clear.
4719 */
4720
4721 eecd = E1000_READ_REG(hw, EECD);
4722
4723 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4724 data = 0;
4725
8fc897b0 4726 for (i = 0; i < count; i++) {
1da177e4
LT		 4727 data = data << 1;
4728 e1000_raise_ee_clk(hw, &eecd);
4729
4730 eecd = E1000_READ_REG(hw, EECD);
4731
4732 eecd &= ~(E1000_EECD_DI);
8fc897b0 4733 if (eecd & E1000_EECD_DO)
1da177e4
LT		 4734 data |= 1;
4735
4736 e1000_lower_ee_clk(hw, &eecd);
4737 }
4738
4739 return data;
4740}
4741
4742/******************************************************************************
4743 * Prepares EEPROM for access
4744 *
4745 * hw - Struct containing variables accessed by shared code
4746 *
4747 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4748 * function should be called before issuing a command to the EEPROM.
4749 *****************************************************************************/
4750static int32_t
4751e1000_acquire_eeprom(struct e1000_hw *hw)
4752{
4753 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4754 uint32_t eecd, i=0;
4755
4756 DEBUGFUNC("e1000_acquire_eeprom");
4757
6418ecc6
JK		 4758 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4759 return -E1000_ERR_SWFW_SYNC;
1da177e4
LT		 4760 eecd = E1000_READ_REG(hw, EECD);
4761
2d7edb92 4762 if (hw->mac_type != e1000_82573) {
868d5309 4763 /* Request EEPROM Access */
8fc897b0 4764 if (hw->mac_type > e1000_82544) {
868d5309 4765 eecd |= E1000_EECD_REQ;
1da177e4 4766 E1000_WRITE_REG(hw, EECD, eecd);
868d5309 4767 eecd = E1000_READ_REG(hw, EECD);
8fc897b0 4768 while ((!(eecd & E1000_EECD_GNT)) &&
868d5309
MC		 4769 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4770 i++;
4771 udelay(5);
4772 eecd = E1000_READ_REG(hw, EECD);
4773 }
8fc897b0 4774 if (!(eecd & E1000_EECD_GNT)) {
868d5309
MC		 4775 eecd &= ~E1000_EECD_REQ;
4776 E1000_WRITE_REG(hw, EECD, eecd);
4777 DEBUGOUT("Could not acquire EEPROM grant\n");
6418ecc6 4778 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
868d5309
MC		 4779 return -E1000_ERR_EEPROM;
4780 }
1da177e4
LT		 4781 }
4782 }
4783
4784 /* Setup EEPROM for Read/Write */
4785
4786 if (eeprom->type == e1000_eeprom_microwire) {
4787 /* Clear SK and DI */
4788 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4789 E1000_WRITE_REG(hw, EECD, eecd);
4790
4791 /* Set CS */
4792 eecd |= E1000_EECD_CS;
4793 E1000_WRITE_REG(hw, EECD, eecd);
4794 } else if (eeprom->type == e1000_eeprom_spi) {
4795 /* Clear SK and CS */
4796 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4797 E1000_WRITE_REG(hw, EECD, eecd);
4798 udelay(1);
4799 }
4800
4801 return E1000_SUCCESS;
4802}
4803
4804/******************************************************************************
4805 * Returns EEPROM to a "standby" state
4806 *
4807 * hw - Struct containing variables accessed by shared code
4808 *****************************************************************************/
4809static void
4810e1000_standby_eeprom(struct e1000_hw *hw)
4811{
4812 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4813 uint32_t eecd;
4814
4815 eecd = E1000_READ_REG(hw, EECD);
4816
8fc897b0 4817 if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 4818 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4819 E1000_WRITE_REG(hw, EECD, eecd);
4820 E1000_WRITE_FLUSH(hw);
4821 udelay(eeprom->delay_usec);
4822
4823 /* Clock high */
4824 eecd |= E1000_EECD_SK;
4825 E1000_WRITE_REG(hw, EECD, eecd);
4826 E1000_WRITE_FLUSH(hw);
4827 udelay(eeprom->delay_usec);
4828
4829 /* Select EEPROM */
4830 eecd |= E1000_EECD_CS;
4831 E1000_WRITE_REG(hw, EECD, eecd);
4832 E1000_WRITE_FLUSH(hw);
4833 udelay(eeprom->delay_usec);
4834
4835 /* Clock low */
4836 eecd &= ~E1000_EECD_SK;
4837 E1000_WRITE_REG(hw, EECD, eecd);
4838 E1000_WRITE_FLUSH(hw);
4839 udelay(eeprom->delay_usec);
8fc897b0 4840 } else if (eeprom->type == e1000_eeprom_spi) {
1da177e4
LT		 4841 /* Toggle CS to flush commands */
4842 eecd |= E1000_EECD_CS;
4843 E1000_WRITE_REG(hw, EECD, eecd);
4844 E1000_WRITE_FLUSH(hw);
4845 udelay(eeprom->delay_usec);
4846 eecd &= ~E1000_EECD_CS;
4847 E1000_WRITE_REG(hw, EECD, eecd);
4848 E1000_WRITE_FLUSH(hw);
4849 udelay(eeprom->delay_usec);
4850 }
4851}
4852
4853/******************************************************************************
4854 * Terminates a command by inverting the EEPROM's chip select pin
4855 *
4856 * hw - Struct containing variables accessed by shared code
4857 *****************************************************************************/
4858static void
4859e1000_release_eeprom(struct e1000_hw *hw)
4860{
4861 uint32_t eecd;
4862
4863 DEBUGFUNC("e1000_release_eeprom");
4864
4865 eecd = E1000_READ_REG(hw, EECD);
4866
4867 if (hw->eeprom.type == e1000_eeprom_spi) {
4868 eecd |= E1000_EECD_CS; /* Pull CS high */
4869 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4870
4871 E1000_WRITE_REG(hw, EECD, eecd);
4872
4873 udelay(hw->eeprom.delay_usec);
8fc897b0 4874 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
1da177e4
LT		 4875 /* cleanup eeprom */
4876
4877 /* CS on Microwire is active-high */
4878 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4879
4880 E1000_WRITE_REG(hw, EECD, eecd);
4881
4882 /* Rising edge of clock */
4883 eecd |= E1000_EECD_SK;
4884 E1000_WRITE_REG(hw, EECD, eecd);
4885 E1000_WRITE_FLUSH(hw);
4886 udelay(hw->eeprom.delay_usec);
4887
4888 /* Falling edge of clock */
4889 eecd &= ~E1000_EECD_SK;
4890 E1000_WRITE_REG(hw, EECD, eecd);
4891 E1000_WRITE_FLUSH(hw);
4892 udelay(hw->eeprom.delay_usec);
4893 }
4894
4895 /* Stop requesting EEPROM access */
8fc897b0 4896 if (hw->mac_type > e1000_82544) {
1da177e4
LT		 4897 eecd &= ~E1000_EECD_REQ;
4898 E1000_WRITE_REG(hw, EECD, eecd);
4899 }
2d7edb92 4900
6418ecc6 4901 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
1da177e4
LT		 4902}
4903
4904/******************************************************************************
4905 * Reads a 16 bit word from the EEPROM.
4906 *
4907 * hw - Struct containing variables accessed by shared code
4908 *****************************************************************************/
35574764 4909static int32_t
1da177e4
LT		 4910e1000_spi_eeprom_ready(struct e1000_hw *hw)
4911{
4912 uint16_t retry_count = 0;
4913 uint8_t spi_stat_reg;
4914
4915 DEBUGFUNC("e1000_spi_eeprom_ready");
4916
4917 /* Read "Status Register" repeatedly until the LSB is cleared. The
4918 * EEPROM will signal that the command has been completed by clearing
4919 * bit 0 of the internal status register. If it's not cleared within
4920 * 5 milliseconds, then error out.
4921 */
4922 retry_count = 0;
4923 do {
4924 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4925 hw->eeprom.opcode_bits);
4926 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4927 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4928 break;
4929
4930 udelay(5);
4931 retry_count += 5;
4932
4933 e1000_standby_eeprom(hw);
8fc897b0 4934 } while (retry_count < EEPROM_MAX_RETRY_SPI);
1da177e4
LT		 4935
4936 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4937 * only 0-5mSec on 5V devices)
4938 */
8fc897b0 4939 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
1da177e4
LT		 4940 DEBUGOUT("SPI EEPROM Status error\n");
4941 return -E1000_ERR_EEPROM;
4942 }
4943
4944 return E1000_SUCCESS;
4945}
4946
4947/******************************************************************************
4948 * Reads a 16 bit word from the EEPROM.
4949 *
4950 * hw - Struct containing variables accessed by shared code
4951 * offset - offset of word in the EEPROM to read
4952 * data - word read from the EEPROM
4953 * words - number of words to read
4954 *****************************************************************************/
4955int32_t
4956e1000_read_eeprom(struct e1000_hw *hw,
4957 uint16_t offset,
4958 uint16_t words,
4959 uint16_t *data)
4960{
4961 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4962 uint32_t i = 0;
4963
4964 DEBUGFUNC("e1000_read_eeprom");
2d7edb92 4965
2a88c173
JK		 4966 /* If eeprom is not yet detected, do so now */
4967 if (eeprom->word_size == 0)
4968 e1000_init_eeprom_params(hw);
4969
1da177e4
LT		 4970 /* A check for invalid values: offset too large, too many words, and not
4971 * enough words.
4972 */
8fc897b0 4973 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
1da177e4 4974 (words == 0)) {
2a88c173 4975 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
1da177e4
LT		 4976 return -E1000_ERR_EEPROM;
4977 }
4978
2a88c173
JK		 4979 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4980 * directly. In this case, we need to acquire the EEPROM so that
4981 * FW or other port software does not interrupt.
4982 */
4d351858 4983 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
8fc897b0 4984 hw->eeprom.use_eerd == FALSE) {
2a88c173
JK		 4985 /* Prepare the EEPROM for bit-bang reading */
4986 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4987 return -E1000_ERR_EEPROM;
2d7edb92
MC		 4988 }
4989
2a88c173
JK		 4990 /* Eerd register EEPROM access requires no eeprom aquire/release */
4991 if (eeprom->use_eerd == TRUE)
4992 return e1000_read_eeprom_eerd(hw, offset, words, data);
1da177e4 4993
2a88c173 4994 /* ICH EEPROM access is done via the ICH flash controller */
cd94dd0b
AK		 4995 if (eeprom->type == e1000_eeprom_ich8)
4996 return e1000_read_eeprom_ich8(hw, offset, words, data);
4997
2a88c173
JK		 4998 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
4999 * acquired the EEPROM at this point, so any returns should relase it */
cd94dd0b 5000 if (eeprom->type == e1000_eeprom_spi) {
1da177e4
LT		 5001 uint16_t word_in;
5002 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5003
8fc897b0 5004 if (e1000_spi_eeprom_ready(hw)) {
1da177e4
LT		 5005 e1000_release_eeprom(hw);
5006 return -E1000_ERR_EEPROM;
5007 }
5008
5009 e1000_standby_eeprom(hw);
5010
5011 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
8fc897b0 5012 if ((eeprom->address_bits == 8) && (offset >= 128))
1da177e4
LT		 5013 read_opcode |= EEPROM_A8_OPCODE_SPI;
5014
5015 /* Send the READ command (opcode + addr) */
5016 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5017 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5018
5019 /* Read the data. The address of the eeprom internally increments with
5020 * each byte (spi) being read, saving on the overhead of eeprom setup
5021 * and tear-down. The address counter will roll over if reading beyond
5022 * the size of the eeprom, thus allowing the entire memory to be read
5023 * starting from any offset. */
5024 for (i = 0; i < words; i++) {
5025 word_in = e1000_shift_in_ee_bits(hw, 16);
5026 data[i] = (word_in >> 8) | (word_in << 8);
5027 }
8fc897b0 5028 } else if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 5029 for (i = 0; i < words; i++) {
5030 /* Send the READ command (opcode + addr) */
5031 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5032 eeprom->opcode_bits);
5033 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5034 eeprom->address_bits);
5035
5036 /* Read the data. For microwire, each word requires the overhead
5037 * of eeprom setup and tear-down. */
5038 data[i] = e1000_shift_in_ee_bits(hw, 16);
5039 e1000_standby_eeprom(hw);
5040 }
5041 }
5042
5043 /* End this read operation */
5044 e1000_release_eeprom(hw);
5045
5046 return E1000_SUCCESS;
5047}
5048
5049/******************************************************************************
2d7edb92 5050 * Reads a 16 bit word from the EEPROM using the EERD register.
1da177e4
LT		 5051 *
5052 * hw - Struct containing variables accessed by shared code
2d7edb92
MC		 5053 * offset - offset of word in the EEPROM to read
5054 * data - word read from the EEPROM
5055 * words - number of words to read
1da177e4 5056 *****************************************************************************/
3ad2cc67 5057static int32_t
2d7edb92
MC		 5058e1000_read_eeprom_eerd(struct e1000_hw *hw,
5059 uint16_t offset,
5060 uint16_t words,
5061 uint16_t *data)
1da177e4 5062{
2d7edb92
MC		 5063 uint32_t i, eerd = 0;
5064 int32_t error = 0;
1da177e4 5065
2d7edb92
MC		 5066 for (i = 0; i < words; i++) {
5067 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5068 E1000_EEPROM_RW_REG_START;
1da177e4 5069
2d7edb92
MC		 5070 E1000_WRITE_REG(hw, EERD, eerd);
5071 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
76c224bc 5072
8fc897b0 5073 if (error) {
2d7edb92 5074 break;
1da177e4 5075 }
2d7edb92 5076 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
76c224bc 5077
1da177e4 5078 }
76c224bc 5079
2d7edb92 5080 return error;
1da177e4
LT		 5081}
5082
5083/******************************************************************************
2d7edb92 5084 * Writes a 16 bit word from the EEPROM using the EEWR register.
1da177e4
LT		 5085 *
5086 * hw - Struct containing variables accessed by shared code
2d7edb92
MC		 5087 * offset - offset of word in the EEPROM to read
5088 * data - word read from the EEPROM
5089 * words - number of words to read
1da177e4 5090 *****************************************************************************/
3ad2cc67 5091static int32_t
2d7edb92
MC		 5092e1000_write_eeprom_eewr(struct e1000_hw *hw,
5093 uint16_t offset,
5094 uint16_t words,
5095 uint16_t *data)
1da177e4 5096{
2d7edb92
MC		 5097 uint32_t register_value = 0;
5098 uint32_t i = 0;
5099 int32_t error = 0;
1da177e4 5100
6418ecc6
JK		 5101 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5102 return -E1000_ERR_SWFW_SYNC;
5103
2d7edb92 5104 for (i = 0; i < words; i++) {
76c224bc
AK		 5105 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5106 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
2d7edb92 5107 E1000_EEPROM_RW_REG_START;
1da177e4 5108
2d7edb92 5109 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
8fc897b0 5110 if (error) {
2d7edb92 5111 break;
76c224bc 5112 }
2d7edb92
MC		 5113
5114 E1000_WRITE_REG(hw, EEWR, register_value);
76c224bc 5115
2d7edb92 5116 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
76c224bc 5117
8fc897b0 5118 if (error) {
2d7edb92 5119 break;
76c224bc 5120 }
2d7edb92 5121 }
76c224bc 5122
6418ecc6 5123 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
2d7edb92
MC		 5124 return error;
5125}
5126
5127/******************************************************************************
5128 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5129 *
5130 * hw - Struct containing variables accessed by shared code
5131 *****************************************************************************/
3ad2cc67 5132static int32_t
2d7edb92
MC		 5133e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5134{
5135 uint32_t attempts = 100000;
5136 uint32_t i, reg = 0;
5137 int32_t done = E1000_ERR_EEPROM;
5138
8fc897b0
AK		 5139 for (i = 0; i < attempts; i++) {
5140 if (eerd == E1000_EEPROM_POLL_READ)
2d7edb92 5141 reg = E1000_READ_REG(hw, EERD);
76c224bc 5142 else
2d7edb92
MC		 5143 reg = E1000_READ_REG(hw, EEWR);
5144
8fc897b0 5145 if (reg & E1000_EEPROM_RW_REG_DONE) {
2d7edb92
MC		 5146 done = E1000_SUCCESS;
5147 break;
5148 }
5149 udelay(5);
5150 }
5151
5152 return done;
5153}
5154
5155/***************************************************************************
5156* Description: Determines if the onboard NVM is FLASH or EEPROM.
5157*
5158* hw - Struct containing variables accessed by shared code
5159****************************************************************************/
3ad2cc67 5160static boolean_t
2d7edb92
MC		 5161e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5162{
5163 uint32_t eecd = 0;
5164
6418ecc6
JK		 5165 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5166
cd94dd0b
AK		 5167 if (hw->mac_type == e1000_ich8lan)
5168 return FALSE;
5169
5170 if (hw->mac_type == e1000_82573) {
2d7edb92
MC		 5171 eecd = E1000_READ_REG(hw, EECD);
5172
5173 /* Isolate bits 15 & 16 */
5174 eecd = ((eecd >> 15) & 0x03);
5175
5176 /* If both bits are set, device is Flash type */
8fc897b0 5177 if (eecd == 0x03) {
2d7edb92
MC		 5178 return FALSE;
5179 }
5180 }
5181 return TRUE;
5182}
5183
5184/******************************************************************************
5185 * Verifies that the EEPROM has a valid checksum
5186 *
5187 * hw - Struct containing variables accessed by shared code
5188 *
5189 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5190 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5191 * valid.
5192 *****************************************************************************/
5193int32_t
5194e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5195{
5196 uint16_t checksum = 0;
5197 uint16_t i, eeprom_data;
5198
5199 DEBUGFUNC("e1000_validate_eeprom_checksum");
5200
5201 if ((hw->mac_type == e1000_82573) &&
5202 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5203 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5204 * 10h-12h. Checksum may need to be fixed. */
5205 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5206 if ((eeprom_data & 0x10) == 0) {
5207 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5208 * has already been fixed. If the checksum is still wrong and this
5209 * bit is a 1, we need to return bad checksum. Otherwise, we need
5210 * to set this bit to a 1 and update the checksum. */
5211 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5212 if ((eeprom_data & 0x8000) == 0) {
5213 eeprom_data |= 0x8000;
5214 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5215 e1000_update_eeprom_checksum(hw);
5216 }
5217 }
5218 }
5219
cd94dd0b
AK		 5220 if (hw->mac_type == e1000_ich8lan) {
5221 /* Drivers must allocate the shadow ram structure for the
5222 * EEPROM checksum to be updated. Otherwise, this bit as well
5223 * as the checksum must both be set correctly for this
5224 * validation to pass.
5225 */
5226 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5227 if ((eeprom_data & 0x40) == 0) {
5228 eeprom_data |= 0x40;
5229 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5230 e1000_update_eeprom_checksum(hw);
5231 }
5232 }
5233
5234 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5235 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
2d7edb92
MC		 5236 DEBUGOUT("EEPROM Read Error\n");
5237 return -E1000_ERR_EEPROM;
5238 }
5239 checksum += eeprom_data;
5240 }
5241
8fc897b0 5242 if (checksum == (uint16_t) EEPROM_SUM)
2d7edb92
MC		 5243 return E1000_SUCCESS;
5244 else {
5245 DEBUGOUT("EEPROM Checksum Invalid\n");
5246 return -E1000_ERR_EEPROM;
5247 }
5248}
5249
5250/******************************************************************************
5251 * Calculates the EEPROM checksum and writes it to the EEPROM
5252 *
5253 * hw - Struct containing variables accessed by shared code
5254 *
5255 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5256 * Writes the difference to word offset 63 of the EEPROM.
5257 *****************************************************************************/
5258int32_t
5259e1000_update_eeprom_checksum(struct e1000_hw *hw)
5260{
cd94dd0b 5261 uint32_t ctrl_ext;
2d7edb92
MC		 5262 uint16_t checksum = 0;
5263 uint16_t i, eeprom_data;
5264
5265 DEBUGFUNC("e1000_update_eeprom_checksum");
5266
8fc897b0
AK		 5267 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5268 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
2d7edb92
MC		 5269 DEBUGOUT("EEPROM Read Error\n");
5270 return -E1000_ERR_EEPROM;
5271 }
5272 checksum += eeprom_data;
5273 }
5274 checksum = (uint16_t) EEPROM_SUM - checksum;
8fc897b0 5275 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
1da177e4
LT		 5276 DEBUGOUT("EEPROM Write Error\n");
5277 return -E1000_ERR_EEPROM;
2d7edb92
MC		 5278 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5279 e1000_commit_shadow_ram(hw);
cd94dd0b
AK		 5280 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5281 e1000_commit_shadow_ram(hw);
5282 /* Reload the EEPROM, or else modifications will not appear
5283 * until after next adapter reset. */
5284 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5285 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5286 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
f8ec4733 5287 msleep(10);
1da177e4
LT		 5288 }
5289 return E1000_SUCCESS;
5290}
5291
5292/******************************************************************************
5293 * Parent function for writing words to the different EEPROM types.
5294 *
5295 * hw - Struct containing variables accessed by shared code
5296 * offset - offset within the EEPROM to be written to
5297 * words - number of words to write
5298 * data - 16 bit word to be written to the EEPROM
5299 *
5300 * If e1000_update_eeprom_checksum is not called after this function, the
5301 * EEPROM will most likely contain an invalid checksum.
5302 *****************************************************************************/
5303int32_t
5304e1000_write_eeprom(struct e1000_hw *hw,
5305 uint16_t offset,
5306 uint16_t words,
5307 uint16_t *data)
5308{
5309 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5310 int32_t status = 0;
5311
5312 DEBUGFUNC("e1000_write_eeprom");
5313
2a88c173
JK		 5314 /* If eeprom is not yet detected, do so now */
5315 if (eeprom->word_size == 0)
5316 e1000_init_eeprom_params(hw);
5317
1da177e4
LT		 5318 /* A check for invalid values: offset too large, too many words, and not
5319 * enough words.
5320 */
8fc897b0 5321 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
1da177e4
LT		 5322 (words == 0)) {
5323 DEBUGOUT("\"words\" parameter out of bounds\n");
5324 return -E1000_ERR_EEPROM;
5325 }
5326
868d5309 5327 /* 82573 writes only through eewr */
8fc897b0 5328 if (eeprom->use_eewr == TRUE)
2d7edb92
MC		 5329 return e1000_write_eeprom_eewr(hw, offset, words, data);
5330
cd94dd0b
AK		 5331 if (eeprom->type == e1000_eeprom_ich8)
5332 return e1000_write_eeprom_ich8(hw, offset, words, data);
5333
1da177e4
LT		 5334 /* Prepare the EEPROM for writing */
5335 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5336 return -E1000_ERR_EEPROM;
5337
8fc897b0 5338 if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 5339 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5340 } else {
5341 status = e1000_write_eeprom_spi(hw, offset, words, data);
f8ec4733 5342 msleep(10);
1da177e4
LT		 5343 }
5344
5345 /* Done with writing */
5346 e1000_release_eeprom(hw);
5347
5348 return status;
5349}
5350
5351/******************************************************************************
5352 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5353 *
5354 * hw - Struct containing variables accessed by shared code
5355 * offset - offset within the EEPROM to be written to
5356 * words - number of words to write
5357 * data - pointer to array of 8 bit words to be written to the EEPROM
5358 *
5359 *****************************************************************************/
35574764 5360static int32_t
1da177e4
LT		 5361e1000_write_eeprom_spi(struct e1000_hw *hw,
5362 uint16_t offset,
5363 uint16_t words,
5364 uint16_t *data)
5365{
5366 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5367 uint16_t widx = 0;
5368
5369 DEBUGFUNC("e1000_write_eeprom_spi");
5370
5371 while (widx < words) {
5372 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5373
8fc897b0 5374 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
1da177e4
LT		 5375
5376 e1000_standby_eeprom(hw);
5377
5378 /* Send the WRITE ENABLE command (8 bit opcode ) */
5379 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5380 eeprom->opcode_bits);
5381
5382 e1000_standby_eeprom(hw);
5383
5384 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
8fc897b0 5385 if ((eeprom->address_bits == 8) && (offset >= 128))
1da177e4
LT		 5386 write_opcode |= EEPROM_A8_OPCODE_SPI;
5387
5388 /* Send the Write command (8-bit opcode + addr) */
5389 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5390
5391 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5392 eeprom->address_bits);
5393
5394 /* Send the data */
5395
5396 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5397 while (widx < words) {
5398 uint16_t word_out = data[widx];
5399 word_out = (word_out >> 8) | (word_out << 8);
5400 e1000_shift_out_ee_bits(hw, word_out, 16);
5401 widx++;
5402
5403 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5404 * operation, while the smaller eeproms are capable of an 8-byte
5405 * PAGE WRITE operation. Break the inner loop to pass new address
5406 */
8fc897b0 5407 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
1da177e4
LT		 5408 e1000_standby_eeprom(hw);
5409 break;
5410 }
5411 }
5412 }
5413
5414 return E1000_SUCCESS;
5415}
5416
5417/******************************************************************************
5418 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5419 *
5420 * hw - Struct containing variables accessed by shared code
5421 * offset - offset within the EEPROM to be written to
5422 * words - number of words to write
5423 * data - pointer to array of 16 bit words to be written to the EEPROM
5424 *
5425 *****************************************************************************/
35574764 5426static int32_t
1da177e4
LT		 5427e1000_write_eeprom_microwire(struct e1000_hw *hw,
5428 uint16_t offset,
5429 uint16_t words,
5430 uint16_t *data)
5431{
5432 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5433 uint32_t eecd;
5434 uint16_t words_written = 0;
5435 uint16_t i = 0;
5436
5437 DEBUGFUNC("e1000_write_eeprom_microwire");
5438
5439 /* Send the write enable command to the EEPROM (3-bit opcode plus
5440 * 6/8-bit dummy address beginning with 11). It's less work to include
5441 * the 11 of the dummy address as part of the opcode than it is to shift
5442 * it over the correct number of bits for the address. This puts the
5443 * EEPROM into write/erase mode.
5444 */
5445 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5446 (uint16_t)(eeprom->opcode_bits + 2));
5447
5448 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5449
5450 /* Prepare the EEPROM */
5451 e1000_standby_eeprom(hw);
5452
5453 while (words_written < words) {
5454 /* Send the Write command (3-bit opcode + addr) */
5455 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5456 eeprom->opcode_bits);
5457
5458 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5459 eeprom->address_bits);
5460
5461 /* Send the data */
5462 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5463
5464 /* Toggle the CS line. This in effect tells the EEPROM to execute
5465 * the previous command.
5466 */
5467 e1000_standby_eeprom(hw);
5468
5469 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5470 * signal that the command has been completed by raising the DO signal.
5471 * If DO does not go high in 10 milliseconds, then error out.
5472 */
8fc897b0 5473 for (i = 0; i < 200; i++) {
1da177e4 5474 eecd = E1000_READ_REG(hw, EECD);
8fc897b0 5475 if (eecd & E1000_EECD_DO) break;
1da177e4
LT		 5476 udelay(50);
5477 }
8fc897b0 5478 if (i == 200) {
1da177e4
LT		 5479 DEBUGOUT("EEPROM Write did not complete\n");
5480 return -E1000_ERR_EEPROM;
5481 }
5482
5483 /* Recover from write */
5484 e1000_standby_eeprom(hw);
5485
5486 words_written++;
5487 }
5488
5489 /* Send the write disable command to the EEPROM (3-bit opcode plus
5490 * 6/8-bit dummy address beginning with 10). It's less work to include
5491 * the 10 of the dummy address as part of the opcode than it is to shift
5492 * it over the correct number of bits for the address. This takes the
5493 * EEPROM out of write/erase mode.
5494 */
5495 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5496 (uint16_t)(eeprom->opcode_bits + 2));
5497
5498 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5499
5500 return E1000_SUCCESS;
5501}
5502
2d7edb92
MC		 5503/******************************************************************************
5504 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5505 * in the eeprom cache and the non modified values in the currently active bank
5506 * to the new bank.
5507 *
5508 * hw - Struct containing variables accessed by shared code
5509 * offset - offset of word in the EEPROM to read
5510 * data - word read from the EEPROM
5511 * words - number of words to read
5512 *****************************************************************************/
3ad2cc67 5513static int32_t
2d7edb92
MC		 5514e1000_commit_shadow_ram(struct e1000_hw *hw)
5515{
5516 uint32_t attempts = 100000;
5517 uint32_t eecd = 0;
5518 uint32_t flop = 0;
5519 uint32_t i = 0;
5520 int32_t error = E1000_SUCCESS;
cd94dd0b
AK		 5521 uint32_t old_bank_offset = 0;
5522 uint32_t new_bank_offset = 0;
cd94dd0b
AK		 5523 uint8_t low_byte = 0;
5524 uint8_t high_byte = 0;
cd94dd0b 5525 boolean_t sector_write_failed = FALSE;
2d7edb92
MC		 5526
5527 if (hw->mac_type == e1000_82573) {
cd94dd0b
AK		 5528 /* The flop register will be used to determine if flash type is STM */
5529 flop = E1000_READ_REG(hw, FLOP);
2d7edb92
MC		 5530 for (i=0; i < attempts; i++) {
5531 eecd = E1000_READ_REG(hw, EECD);
5532 if ((eecd & E1000_EECD_FLUPD) == 0) {
5533 break;
5534 }
5535 udelay(5);
5536 }
5537
5538 if (i == attempts) {
5539 return -E1000_ERR_EEPROM;
5540 }
5541
96838a40 5542 /* If STM opcode located in bits 15:8 of flop, reset firmware */
2d7edb92
MC		 5543 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5544 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5545 }
5546
5547 /* Perform the flash update */
5548 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5549
96838a40 5550 for (i=0; i < attempts; i++) {
2d7edb92
MC		 5551 eecd = E1000_READ_REG(hw, EECD);
5552 if ((eecd & E1000_EECD_FLUPD) == 0) {
5553 break;
5554 }
5555 udelay(5);
5556 }
5557
5558 if (i == attempts) {
5559 return -E1000_ERR_EEPROM;
5560 }
5561 }
5562
cd94dd0b
AK		 5563 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5564 /* We're writing to the opposite bank so if we're on bank 1,
5565 * write to bank 0 etc. We also need to erase the segment that
5566 * is going to be written */
5567 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5568 new_bank_offset = hw->flash_bank_size * 2;
5569 old_bank_offset = 0;
5570 e1000_erase_ich8_4k_segment(hw, 1);
5571 } else {
5572 old_bank_offset = hw->flash_bank_size * 2;
5573 new_bank_offset = 0;
5574 e1000_erase_ich8_4k_segment(hw, 0);
5575 }
5576
2a88c173
JK		 5577 sector_write_failed = FALSE;
5578 /* Loop for every byte in the shadow RAM,
5579 * which is in units of words. */
5580 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5581 /* Determine whether to write the value stored
5582 * in the other NVM bank or a modified value stored
5583 * in the shadow RAM */
5584 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5585 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5586 udelay(100);
5587 error = e1000_verify_write_ich8_byte(hw,
5588 (i << 1) + new_bank_offset, low_byte);
5589
5590 if (error != E1000_SUCCESS)
5591 sector_write_failed = TRUE;
5592 else {
cd94dd0b
AK		 5593 high_byte =
5594 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
cd94dd0b 5595 udelay(100);
2a88c173
JK		 5596 }
5597 } else {
5598 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5599 &low_byte);
5600 udelay(100);
5601 error = e1000_verify_write_ich8_byte(hw,
5602 (i << 1) + new_bank_offset, low_byte);
5603
5604 if (error != E1000_SUCCESS)
5605 sector_write_failed = TRUE;
5606 else {
cd94dd0b
AK		 5607 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5608 &high_byte);
2a88c173 5609 udelay(100);
cd94dd0b 5610 }
2a88c173 5611 }
cd94dd0b 5612
2a88c173
JK		 5613 /* If the write of the low byte was successful, go ahread and
5614 * write the high byte while checking to make sure that if it
5615 * is the signature byte, then it is handled properly */
5616 if (sector_write_failed == FALSE) {
cd94dd0b
AK		 5617 /* If the word is 0x13, then make sure the signature bits
5618 * (15:14) are 11b until the commit has completed.
5619 * This will allow us to write 10b which indicates the
5620 * signature is valid. We want to do this after the write
5621 * has completed so that we don't mark the segment valid
5622 * while the write is still in progress */
5623 if (i == E1000_ICH8_NVM_SIG_WORD)
5624 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5625
5626 error = e1000_verify_write_ich8_byte(hw,
2a88c173 5627 (i << 1) + new_bank_offset + 1, high_byte);
cd94dd0b
AK		 5628 if (error != E1000_SUCCESS)
5629 sector_write_failed = TRUE;
5630
2a88c173
JK		 5631 } else {
5632 /* If the write failed then break from the loop and
5633 * return an error */
5634 break;
cd94dd0b 5635 }
2a88c173 5636 }
cd94dd0b 5637
2a88c173
JK		 5638 /* Don't bother writing the segment valid bits if sector
5639 * programming failed. */
5640 if (sector_write_failed == FALSE) {
5641 /* Finally validate the new segment by setting bit 15:14
5642 * to 10b in word 0x13 , this can be done without an
5643 * erase as well since these bits are 11 to start with
5644 * and we need to change bit 14 to 0b */
5645 e1000_read_ich8_byte(hw,
5646 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5647 &high_byte);
5648 high_byte &= 0xBF;
5649 error = e1000_verify_write_ich8_byte(hw,
5650 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5651 /* And invalidate the previously valid segment by setting
5652 * its signature word (0x13) high_byte to 0b. This can be
5653 * done without an erase because flash erase sets all bits
5654 * to 1's. We can write 1's to 0's without an erase */
5655 if (error == E1000_SUCCESS) {
cd94dd0b 5656 error = e1000_verify_write_ich8_byte(hw,
2a88c173
JK		 5657 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5658 }
cd94dd0b 5659
2a88c173
JK		 5660 /* Clear the now not used entry in the cache */
5661 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5662 hw->eeprom_shadow_ram[i].modified = FALSE;
5663 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
cd94dd0b 5664 }
2a88c173 5665 }
cd94dd0b
AK		 5666 }
5667
2d7edb92
MC		 5668 return error;
5669}
5670
1da177e4
LT		 5671/******************************************************************************
5672 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5673 * second function of dual function devices
5674 *
5675 * hw - Struct containing variables accessed by shared code
5676 *****************************************************************************/
5677int32_t
5678e1000_read_mac_addr(struct e1000_hw * hw)
5679{
5680 uint16_t offset;
5681 uint16_t eeprom_data, i;
5682
5683 DEBUGFUNC("e1000_read_mac_addr");
5684
8fc897b0 5685 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1da177e4 5686 offset = i >> 1;
8fc897b0 5687 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1da177e4
LT		 5688 DEBUGOUT("EEPROM Read Error\n");
5689 return -E1000_ERR_EEPROM;
5690 }
5691 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5692 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5693 }
96838a40 5694
868d5309
MC		 5695 switch (hw->mac_type) {
5696 default:
5697 break;
5698 case e1000_82546:
5699 case e1000_82546_rev_3:
5700 case e1000_82571:
6418ecc6 5701 case e1000_80003es2lan:
8fc897b0 5702 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1da177e4 5703 hw->perm_mac_addr[5] ^= 0x01;
868d5309
MC		 5704 break;
5705 }
1da177e4 5706
8fc897b0 5707 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
1da177e4
LT		 5708 hw->mac_addr[i] = hw->perm_mac_addr[i];
5709 return E1000_SUCCESS;
5710}
5711
5712/******************************************************************************
5713 * Initializes receive address filters.
5714 *
5715 * hw - Struct containing variables accessed by shared code
5716 *
5717 * Places the MAC address in receive address register 0 and clears the rest
5718 * of the receive addresss registers. Clears the multicast table. Assumes
5719 * the receiver is in reset when the routine is called.
5720 *****************************************************************************/
3ad2cc67 5721static void
1da177e4
LT		 5722e1000_init_rx_addrs(struct e1000_hw *hw)
5723{
5724 uint32_t i;
2d7edb92 5725 uint32_t rar_num;
1da177e4
LT		 5726
5727 DEBUGFUNC("e1000_init_rx_addrs");
5728
5729 /* Setup the receive address. */
5730 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5731
5732 e1000_rar_set(hw, hw->mac_addr, 0);
5733
2d7edb92 5734 rar_num = E1000_RAR_ENTRIES;
868d5309
MC		 5735
5736 /* Reserve a spot for the Locally Administered Address to work around
5737 * an 82571 issue in which a reset on one port will reload the MAC on
5738 * the other port. */
5739 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5740 rar_num -= 1;
cd94dd0b
AK		 5741 if (hw->mac_type == e1000_ich8lan)
5742 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5743
1da177e4
LT		 5744 /* Zero out the other 15 receive addresses. */
5745 DEBUGOUT("Clearing RAR[1-15]\n");
8fc897b0 5746 for (i = 1; i < rar_num; i++) {
1da177e4 5747 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4ca213a6 5748 E1000_WRITE_FLUSH(hw);
1da177e4 5749 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4ca213a6 5750 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5751 }
5752}
5753
1da177e4
LT		 5754/******************************************************************************
5755 * Hashes an address to determine its location in the multicast table
5756 *
5757 * hw - Struct containing variables accessed by shared code
5758 * mc_addr - the multicast address to hash
5759 *****************************************************************************/
5760uint32_t
5761e1000_hash_mc_addr(struct e1000_hw *hw,
5762 uint8_t *mc_addr)
5763{
5764 uint32_t hash_value = 0;
5765
5766 /* The portion of the address that is used for the hash table is
5767 * determined by the mc_filter_type setting.
5768 */
5769 switch (hw->mc_filter_type) {
5770 /* [0] [1] [2] [3] [4] [5]
5771 * 01 AA 00 12 34 56
5772 * LSB MSB
5773 */
5774 case 0:
cd94dd0b
AK		 5775 if (hw->mac_type == e1000_ich8lan) {
5776 /* [47:38] i.e. 0x158 for above example address */
5777 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5778 } else {
5779 /* [47:36] i.e. 0x563 for above example address */
5780 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5781 }
1da177e4
LT		 5782 break;
5783 case 1:
cd94dd0b
AK		 5784 if (hw->mac_type == e1000_ich8lan) {
5785 /* [46:37] i.e. 0x2B1 for above example address */
5786 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5787 } else {
5788 /* [46:35] i.e. 0xAC6 for above example address */
5789 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5790 }
1da177e4
LT		 5791 break;
5792 case 2:
cd94dd0b
AK		 5793 if (hw->mac_type == e1000_ich8lan) {
5794 /*[45:36] i.e. 0x163 for above example address */
5795 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5796 } else {
5797 /* [45:34] i.e. 0x5D8 for above example address */
5798 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5799 }
1da177e4
LT		 5800 break;
5801 case 3:
cd94dd0b
AK		 5802 if (hw->mac_type == e1000_ich8lan) {
5803 /* [43:34] i.e. 0x18D for above example address */
5804 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5805 } else {
5806 /* [43:32] i.e. 0x634 for above example address */
5807 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5808 }
1da177e4
LT		 5809 break;
5810 }
5811
5812 hash_value &= 0xFFF;
cd94dd0b
AK		 5813 if (hw->mac_type == e1000_ich8lan)
5814 hash_value &= 0x3FF;
2d7edb92 5815
1da177e4
LT		 5816 return hash_value;
5817}
5818
5819/******************************************************************************
5820 * Sets the bit in the multicast table corresponding to the hash value.
5821 *
5822 * hw - Struct containing variables accessed by shared code
5823 * hash_value - Multicast address hash value
5824 *****************************************************************************/
5825void
5826e1000_mta_set(struct e1000_hw *hw,
5827 uint32_t hash_value)
5828{
5829 uint32_t hash_bit, hash_reg;
5830 uint32_t mta;
5831 uint32_t temp;
5832
5833 /* The MTA is a register array of 128 32-bit registers.
5834 * It is treated like an array of 4096 bits. We want to set
5835 * bit BitArray[hash_value]. So we figure out what register
5836 * the bit is in, read it, OR in the new bit, then write
5837 * back the new value. The register is determined by the
5838 * upper 7 bits of the hash value and the bit within that
5839 * register are determined by the lower 5 bits of the value.
5840 */
5841 hash_reg = (hash_value >> 5) & 0x7F;
cd94dd0b
AK		 5842 if (hw->mac_type == e1000_ich8lan)
5843 hash_reg &= 0x1F;
1da177e4
LT		 5844 hash_bit = hash_value & 0x1F;
5845
5846 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5847
5848 mta |= (1 << hash_bit);
5849
5850 /* If we are on an 82544 and we are trying to write an odd offset
5851 * in the MTA, save off the previous entry before writing and
5852 * restore the old value after writing.
5853 */
8fc897b0 5854 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
1da177e4
LT		 5855 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5856 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4ca213a6 5857 E1000_WRITE_FLUSH(hw);
1da177e4 5858 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4ca213a6 5859 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5860 } else {
5861 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4ca213a6 5862 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5863 }
5864}
5865
5866/******************************************************************************
5867 * Puts an ethernet address into a receive address register.
5868 *
5869 * hw - Struct containing variables accessed by shared code
5870 * addr - Address to put into receive address register
5871 * index - Receive address register to write
5872 *****************************************************************************/
5873void
5874e1000_rar_set(struct e1000_hw *hw,
5875 uint8_t *addr,
5876 uint32_t index)
5877{
5878 uint32_t rar_low, rar_high;
5879
5880 /* HW expects these in little endian so we reverse the byte order
5881 * from network order (big endian) to little endian
5882 */
5883 rar_low = ((uint32_t) addr[0] |
5884 ((uint32_t) addr[1] << 8) |
5885 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
8df06e50 5886 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
1da177e4 5887
8df06e50
JK		 5888 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5889 * unit hang.
5890 *
5891 * Description:
5892 * If there are any Rx frames queued up or otherwise present in the HW
5893 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5894 * hang. To work around this issue, we have to disable receives and
5895 * flush out all Rx frames before we enable RSS. To do so, we modify we
5896 * redirect all Rx traffic to manageability and then reset the HW.
5897 * This flushes away Rx frames, and (since the redirections to
5898 * manageability persists across resets) keeps new ones from coming in
5899 * while we work. Then, we clear the Address Valid AV bit for all MAC
5900 * addresses and undo the re-direction to manageability.
5901 * Now, frames are coming in again, but the MAC won't accept them, so
5902 * far so good. We now proceed to initialize RSS (if necessary) and
5903 * configure the Rx unit. Last, we re-enable the AV bits and continue
5904 * on our merry way.
5905 */
5906 switch (hw->mac_type) {
5907 case e1000_82571:
5908 case e1000_82572:
6418ecc6 5909 case e1000_80003es2lan:
8df06e50
JK		 5910 if (hw->leave_av_bit_off == TRUE)
5911 break;
5912 default:
5913 /* Indicate to hardware the Address is Valid. */
5914 rar_high |= E1000_RAH_AV;
5915 break;
5916 }
1da177e4
LT		 5917
5918 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4ca213a6 5919 E1000_WRITE_FLUSH(hw);
1da177e4 5920 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4ca213a6 5921 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5922}
5923
5924/******************************************************************************
5925 * Writes a value to the specified offset in the VLAN filter table.
5926 *
5927 * hw - Struct containing variables accessed by shared code
5928 * offset - Offset in VLAN filer table to write
5929 * value - Value to write into VLAN filter table
5930 *****************************************************************************/
5931void
5932e1000_write_vfta(struct e1000_hw *hw,
5933 uint32_t offset,
5934 uint32_t value)
5935{
5936 uint32_t temp;
5937
cd94dd0b
AK		 5938 if (hw->mac_type == e1000_ich8lan)
5939 return;
5940
5941 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
1da177e4
LT		 5942 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5943 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4ca213a6 5944 E1000_WRITE_FLUSH(hw);
1da177e4 5945 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4ca213a6 5946 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5947 } else {
5948 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4ca213a6 5949 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5950 }
5951}
5952
5953/******************************************************************************
5954 * Clears the VLAN filer table
5955 *
5956 * hw - Struct containing variables accessed by shared code
5957 *****************************************************************************/
3ad2cc67 5958static void
1da177e4
LT		 5959e1000_clear_vfta(struct e1000_hw *hw)
5960{
5961 uint32_t offset;
2d7edb92
MC		 5962 uint32_t vfta_value = 0;
5963 uint32_t vfta_offset = 0;
5964 uint32_t vfta_bit_in_reg = 0;
5965
cd94dd0b
AK		 5966 if (hw->mac_type == e1000_ich8lan)
5967 return;
5968
2d7edb92
MC		 5969 if (hw->mac_type == e1000_82573) {
5970 if (hw->mng_cookie.vlan_id != 0) {
5971 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5972 * ID. The following operations determine which 32b entry
5973 * (i.e. offset) into the array we want to set the VLAN ID
5974 * (i.e. bit) of the manageability unit. */
5975 vfta_offset = (hw->mng_cookie.vlan_id >>
5976 E1000_VFTA_ENTRY_SHIFT) &
5977 E1000_VFTA_ENTRY_MASK;
5978 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5979 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5980 }
5981 }
5982 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5983 /* If the offset we want to clear is the same offset of the
5984 * manageability VLAN ID, then clear all bits except that of the
5985 * manageability unit */
5986 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5987 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4ca213a6 5988 E1000_WRITE_FLUSH(hw);
2d7edb92 5989 }
1da177e4
LT		 5990}
5991
3ad2cc67 5992static int32_t
1da177e4
LT		 5993e1000_id_led_init(struct e1000_hw * hw)
5994{
5995 uint32_t ledctl;
5996 const uint32_t ledctl_mask = 0x000000FF;
5997 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5998 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5999 uint16_t eeprom_data, i, temp;
6000 const uint16_t led_mask = 0x0F;
6001
6002 DEBUGFUNC("e1000_id_led_init");
6003
8fc897b0 6004 if (hw->mac_type < e1000_82540) {
1da177e4
LT		 6005 /* Nothing to do */
6006 return E1000_SUCCESS;
6007 }
6008
6009 ledctl = E1000_READ_REG(hw, LEDCTL);
6010 hw->ledctl_default = ledctl;
6011 hw->ledctl_mode1 = hw->ledctl_default;
6012 hw->ledctl_mode2 = hw->ledctl_default;
6013
8fc897b0 6014 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
1da177e4
LT		 6015 DEBUGOUT("EEPROM Read Error\n");
6016 return -E1000_ERR_EEPROM;
6017 }
cd94dd0b
AK		 6018
6019 if ((hw->mac_type == e1000_82573) &&
6020 (eeprom_data == ID_LED_RESERVED_82573))
6021 eeprom_data = ID_LED_DEFAULT_82573;
6022 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6023 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6024 if (hw->mac_type == e1000_ich8lan)
6025 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6026 else
6027 eeprom_data = ID_LED_DEFAULT;
6028 }
6029 for (i = 0; i < 4; i++) {
1da177e4 6030 temp = (eeprom_data >> (i << 2)) & led_mask;
8fc897b0 6031 switch (temp) {
1da177e4
LT		 6032 case ID_LED_ON1_DEF2:
6033 case ID_LED_ON1_ON2:
6034 case ID_LED_ON1_OFF2:
6035 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6036 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6037 break;
6038 case ID_LED_OFF1_DEF2:
6039 case ID_LED_OFF1_ON2:
6040 case ID_LED_OFF1_OFF2:
6041 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6042 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6043 break;
6044 default:
6045 /* Do nothing */
6046 break;
6047 }
8fc897b0 6048 switch (temp) {
1da177e4
LT		 6049 case ID_LED_DEF1_ON2:
6050 case ID_LED_ON1_ON2:
6051 case ID_LED_OFF1_ON2:
6052 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6053 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6054 break;
6055 case ID_LED_DEF1_OFF2:
6056 case ID_LED_ON1_OFF2:
6057 case ID_LED_OFF1_OFF2:
6058 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6059 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6060 break;
6061 default:
6062 /* Do nothing */
6063 break;
6064 }
6065 }
6066 return E1000_SUCCESS;
6067}
6068
6069/******************************************************************************
6070 * Prepares SW controlable LED for use and saves the current state of the LED.
6071 *
6072 * hw - Struct containing variables accessed by shared code
6073 *****************************************************************************/
6074int32_t
6075e1000_setup_led(struct e1000_hw *hw)
6076{
6077 uint32_t ledctl;
6078 int32_t ret_val = E1000_SUCCESS;
6079
6080 DEBUGFUNC("e1000_setup_led");
6081
8fc897b0 6082 switch (hw->mac_type) {
1da177e4
LT		 6083 case e1000_82542_rev2_0:
6084 case e1000_82542_rev2_1:
6085 case e1000_82543:
6086 case e1000_82544:
6087 /* No setup necessary */
6088 break;
6089 case e1000_82541:
6090 case e1000_82547:
6091 case e1000_82541_rev_2:
6092 case e1000_82547_rev_2:
6093 /* Turn off PHY Smart Power Down (if enabled) */
6094 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6095 &hw->phy_spd_default);
8fc897b0 6096 if (ret_val)
1da177e4
LT		 6097 return ret_val;
6098 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6099 (uint16_t)(hw->phy_spd_default &
6100 ~IGP01E1000_GMII_SPD));
8fc897b0 6101 if (ret_val)
1da177e4
LT		 6102 return ret_val;
6103 /* Fall Through */
6104 default:
8fc897b0 6105 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6106 ledctl = E1000_READ_REG(hw, LEDCTL);
6107 /* Save current LEDCTL settings */
6108 hw->ledctl_default = ledctl;
6109 /* Turn off LED0 */
6110 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6111 E1000_LEDCTL_LED0_BLINK |
6112 E1000_LEDCTL_LED0_MODE_MASK);
6113 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6114 E1000_LEDCTL_LED0_MODE_SHIFT);
6115 E1000_WRITE_REG(hw, LEDCTL, ledctl);
8fc897b0 6116 } else if (hw->media_type == e1000_media_type_copper)
1da177e4
LT		 6117 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6118 break;
6119 }
6120
6121 return E1000_SUCCESS;
6122}
6123
8fc897b0 6124
f1b3a853
AK		 6125/******************************************************************************
6126 * Used on 82571 and later Si that has LED blink bits.
6127 * Callers must use their own timer and should have already called
6128 * e1000_id_led_init()
6129 * Call e1000_cleanup led() to stop blinking
6130 *
6131 * hw - Struct containing variables accessed by shared code
6132 *****************************************************************************/
6133int32_t
6134e1000_blink_led_start(struct e1000_hw *hw)
6135{
6136 int16_t i;
6137 uint32_t ledctl_blink = 0;
6138
6139 DEBUGFUNC("e1000_id_led_blink_on");
6140
6141 if (hw->mac_type < e1000_82571) {
6142 /* Nothing to do */
6143 return E1000_SUCCESS;
6144 }
6145 if (hw->media_type == e1000_media_type_fiber) {
6146 /* always blink LED0 for PCI-E fiber */
6147 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6148 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6149 } else {
6150 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6151 ledctl_blink = hw->ledctl_mode2;
6152 for (i=0; i < 4; i++)
6153 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6154 E1000_LEDCTL_MODE_LED_ON)
6155 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6156 }
6157
6158 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6159
6160 return E1000_SUCCESS;
6161}
6162
1da177e4
LT		 6163/******************************************************************************
6164 * Restores the saved state of the SW controlable LED.
6165 *
6166 * hw - Struct containing variables accessed by shared code
6167 *****************************************************************************/
6168int32_t
6169e1000_cleanup_led(struct e1000_hw *hw)
6170{
6171 int32_t ret_val = E1000_SUCCESS;
6172
6173 DEBUGFUNC("e1000_cleanup_led");
6174
8fc897b0 6175 switch (hw->mac_type) {
1da177e4
LT		 6176 case e1000_82542_rev2_0:
6177 case e1000_82542_rev2_1:
6178 case e1000_82543:
6179 case e1000_82544:
6180 /* No cleanup necessary */
6181 break;
6182 case e1000_82541:
6183 case e1000_82547:
6184 case e1000_82541_rev_2:
6185 case e1000_82547_rev_2:
6186 /* Turn on PHY Smart Power Down (if previously enabled) */
6187 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6188 hw->phy_spd_default);
8fc897b0 6189 if (ret_val)
1da177e4
LT		 6190 return ret_val;
6191 /* Fall Through */
6192 default:
cd94dd0b
AK		 6193 if (hw->phy_type == e1000_phy_ife) {
6194 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6195 break;
6196 }
1da177e4
LT		 6197 /* Restore LEDCTL settings */
6198 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6199 break;
6200 }
6201
6202 return E1000_SUCCESS;
6203}
6204
6205/******************************************************************************
6206 * Turns on the software controllable LED
6207 *
6208 * hw - Struct containing variables accessed by shared code
6209 *****************************************************************************/
6210int32_t
6211e1000_led_on(struct e1000_hw *hw)
6212{
6213 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6214
6215 DEBUGFUNC("e1000_led_on");
6216
8fc897b0 6217 switch (hw->mac_type) {
1da177e4
LT		 6218 case e1000_82542_rev2_0:
6219 case e1000_82542_rev2_1:
6220 case e1000_82543:
6221 /* Set SW Defineable Pin 0 to turn on the LED */
6222 ctrl |= E1000_CTRL_SWDPIN0;
6223 ctrl |= E1000_CTRL_SWDPIO0;
6224 break;
6225 case e1000_82544:
8fc897b0 6226 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6227 /* Set SW Defineable Pin 0 to turn on the LED */
6228 ctrl |= E1000_CTRL_SWDPIN0;
6229 ctrl |= E1000_CTRL_SWDPIO0;
6230 } else {
6231 /* Clear SW Defineable Pin 0 to turn on the LED */
6232 ctrl &= ~E1000_CTRL_SWDPIN0;
6233 ctrl |= E1000_CTRL_SWDPIO0;
6234 }
6235 break;
6236 default:
8fc897b0 6237 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6238 /* Clear SW Defineable Pin 0 to turn on the LED */
6239 ctrl &= ~E1000_CTRL_SWDPIN0;
6240 ctrl |= E1000_CTRL_SWDPIO0;
cd94dd0b
AK		 6241 } else if (hw->phy_type == e1000_phy_ife) {
6242 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6243 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6244 } else if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 6245 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6246 return E1000_SUCCESS;
6247 }
6248 break;
6249 }
6250
6251 E1000_WRITE_REG(hw, CTRL, ctrl);
6252
6253 return E1000_SUCCESS;
6254}
6255
6256/******************************************************************************
6257 * Turns off the software controllable LED
6258 *
6259 * hw - Struct containing variables accessed by shared code
6260 *****************************************************************************/
6261int32_t
6262e1000_led_off(struct e1000_hw *hw)
6263{
6264 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6265
6266 DEBUGFUNC("e1000_led_off");
6267
8fc897b0 6268 switch (hw->mac_type) {
1da177e4
LT		 6269 case e1000_82542_rev2_0:
6270 case e1000_82542_rev2_1:
6271 case e1000_82543:
6272 /* Clear SW Defineable Pin 0 to turn off the LED */
6273 ctrl &= ~E1000_CTRL_SWDPIN0;
6274 ctrl |= E1000_CTRL_SWDPIO0;
6275 break;
6276 case e1000_82544:
8fc897b0 6277 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6278 /* Clear SW Defineable Pin 0 to turn off the LED */
6279 ctrl &= ~E1000_CTRL_SWDPIN0;
6280 ctrl |= E1000_CTRL_SWDPIO0;
6281 } else {
6282 /* Set SW Defineable Pin 0 to turn off the LED */
6283 ctrl |= E1000_CTRL_SWDPIN0;
6284 ctrl |= E1000_CTRL_SWDPIO0;
6285 }
6286 break;
6287 default:
8fc897b0 6288 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6289 /* Set SW Defineable Pin 0 to turn off the LED */
6290 ctrl |= E1000_CTRL_SWDPIN0;
6291 ctrl |= E1000_CTRL_SWDPIO0;
cd94dd0b
AK		 6292 } else if (hw->phy_type == e1000_phy_ife) {
6293 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6294 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6295 } else if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 6296 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6297 return E1000_SUCCESS;
6298 }
6299 break;
6300 }
6301
6302 E1000_WRITE_REG(hw, CTRL, ctrl);
6303
6304 return E1000_SUCCESS;
6305}
6306
6307/******************************************************************************
6308 * Clears all hardware statistics counters.
6309 *
6310 * hw - Struct containing variables accessed by shared code
6311 *****************************************************************************/
35574764 6312static void
1da177e4
LT		 6313e1000_clear_hw_cntrs(struct e1000_hw *hw)
6314{
6315 volatile uint32_t temp;
6316
6317 temp = E1000_READ_REG(hw, CRCERRS);
6318 temp = E1000_READ_REG(hw, SYMERRS);
6319 temp = E1000_READ_REG(hw, MPC);
6320 temp = E1000_READ_REG(hw, SCC);
6321 temp = E1000_READ_REG(hw, ECOL);
6322 temp = E1000_READ_REG(hw, MCC);
6323 temp = E1000_READ_REG(hw, LATECOL);
6324 temp = E1000_READ_REG(hw, COLC);
6325 temp = E1000_READ_REG(hw, DC);
6326 temp = E1000_READ_REG(hw, SEC);
6327 temp = E1000_READ_REG(hw, RLEC);
6328 temp = E1000_READ_REG(hw, XONRXC);
6329 temp = E1000_READ_REG(hw, XONTXC);
6330 temp = E1000_READ_REG(hw, XOFFRXC);
6331 temp = E1000_READ_REG(hw, XOFFTXC);
6332 temp = E1000_READ_REG(hw, FCRUC);
cd94dd0b
AK		 6333
6334 if (hw->mac_type != e1000_ich8lan) {
1da177e4
LT		 6335 temp = E1000_READ_REG(hw, PRC64);
6336 temp = E1000_READ_REG(hw, PRC127);
6337 temp = E1000_READ_REG(hw, PRC255);
6338 temp = E1000_READ_REG(hw, PRC511);
6339 temp = E1000_READ_REG(hw, PRC1023);
6340 temp = E1000_READ_REG(hw, PRC1522);
cd94dd0b
AK		 6341 }
6342
1da177e4
LT		 6343 temp = E1000_READ_REG(hw, GPRC);
6344 temp = E1000_READ_REG(hw, BPRC);
6345 temp = E1000_READ_REG(hw, MPRC);
6346 temp = E1000_READ_REG(hw, GPTC);
6347 temp = E1000_READ_REG(hw, GORCL);
6348 temp = E1000_READ_REG(hw, GORCH);
6349 temp = E1000_READ_REG(hw, GOTCL);
6350 temp = E1000_READ_REG(hw, GOTCH);
6351 temp = E1000_READ_REG(hw, RNBC);
6352 temp = E1000_READ_REG(hw, RUC);
6353 temp = E1000_READ_REG(hw, RFC);
6354 temp = E1000_READ_REG(hw, ROC);
6355 temp = E1000_READ_REG(hw, RJC);
6356 temp = E1000_READ_REG(hw, TORL);
6357 temp = E1000_READ_REG(hw, TORH);
6358 temp = E1000_READ_REG(hw, TOTL);
6359 temp = E1000_READ_REG(hw, TOTH);
6360 temp = E1000_READ_REG(hw, TPR);
6361 temp = E1000_READ_REG(hw, TPT);
cd94dd0b
AK		 6362
6363 if (hw->mac_type != e1000_ich8lan) {
1da177e4
LT		 6364 temp = E1000_READ_REG(hw, PTC64);
6365 temp = E1000_READ_REG(hw, PTC127);
6366 temp = E1000_READ_REG(hw, PTC255);
6367 temp = E1000_READ_REG(hw, PTC511);
6368 temp = E1000_READ_REG(hw, PTC1023);
6369 temp = E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 6370 }
6371
1da177e4
LT		 6372 temp = E1000_READ_REG(hw, MPTC);
6373 temp = E1000_READ_REG(hw, BPTC);
6374
8fc897b0 6375 if (hw->mac_type < e1000_82543) return;
1da177e4
LT		 6376
6377 temp = E1000_READ_REG(hw, ALGNERRC);
6378 temp = E1000_READ_REG(hw, RXERRC);
6379 temp = E1000_READ_REG(hw, TNCRS);
6380 temp = E1000_READ_REG(hw, CEXTERR);
6381 temp = E1000_READ_REG(hw, TSCTC);
6382 temp = E1000_READ_REG(hw, TSCTFC);
6383
8fc897b0 6384 if (hw->mac_type <= e1000_82544) return;
1da177e4
LT		 6385
6386 temp = E1000_READ_REG(hw, MGTPRC);
6387 temp = E1000_READ_REG(hw, MGTPDC);
6388 temp = E1000_READ_REG(hw, MGTPTC);
2d7edb92 6389
8fc897b0 6390 if (hw->mac_type <= e1000_82547_rev_2) return;
2d7edb92
MC		 6391
6392 temp = E1000_READ_REG(hw, IAC);
6393 temp = E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 6394
6395 if (hw->mac_type == e1000_ich8lan) return;
6396
2d7edb92
MC		 6397 temp = E1000_READ_REG(hw, ICRXPTC);
6398 temp = E1000_READ_REG(hw, ICRXATC);
6399 temp = E1000_READ_REG(hw, ICTXPTC);
6400 temp = E1000_READ_REG(hw, ICTXATC);
6401 temp = E1000_READ_REG(hw, ICTXQEC);
6402 temp = E1000_READ_REG(hw, ICTXQMTC);
6403 temp = E1000_READ_REG(hw, ICRXDMTC);
1da177e4
LT		 6404}
6405
6406/******************************************************************************
6407 * Resets Adaptive IFS to its default state.
6408 *
6409 * hw - Struct containing variables accessed by shared code
6410 *
6411 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6412 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6413 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6414 * before calling this function.
6415 *****************************************************************************/
6416void
6417e1000_reset_adaptive(struct e1000_hw *hw)
6418{
6419 DEBUGFUNC("e1000_reset_adaptive");
6420
8fc897b0
AK		 6421 if (hw->adaptive_ifs) {
6422 if (!hw->ifs_params_forced) {
1da177e4
LT		 6423 hw->current_ifs_val = 0;
6424 hw->ifs_min_val = IFS_MIN;
6425 hw->ifs_max_val = IFS_MAX;
6426 hw->ifs_step_size = IFS_STEP;
6427 hw->ifs_ratio = IFS_RATIO;
6428 }
6429 hw->in_ifs_mode = FALSE;
6430 E1000_WRITE_REG(hw, AIT, 0);
6431 } else {
6432 DEBUGOUT("Not in Adaptive IFS mode!\n");
6433 }
6434}
6435
6436/******************************************************************************
6437 * Called during the callback/watchdog routine to update IFS value based on
6438 * the ratio of transmits to collisions.
6439 *
6440 * hw - Struct containing variables accessed by shared code
6441 * tx_packets - Number of transmits since last callback
6442 * total_collisions - Number of collisions since last callback
6443 *****************************************************************************/
6444void
6445e1000_update_adaptive(struct e1000_hw *hw)
6446{
6447 DEBUGFUNC("e1000_update_adaptive");
6448
8fc897b0
AK		 6449 if (hw->adaptive_ifs) {
6450 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6451 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
1da177e4 6452 hw->in_ifs_mode = TRUE;
8fc897b0
AK		 6453 if (hw->current_ifs_val < hw->ifs_max_val) {
6454 if (hw->current_ifs_val == 0)
1da177e4
LT		 6455 hw->current_ifs_val = hw->ifs_min_val;
6456 else
6457 hw->current_ifs_val += hw->ifs_step_size;
6458 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6459 }
6460 }
6461 } else {
8fc897b0 6462 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
1da177e4
LT		 6463 hw->current_ifs_val = 0;
6464 hw->in_ifs_mode = FALSE;
6465 E1000_WRITE_REG(hw, AIT, 0);
6466 }
6467 }
6468 } else {
6469 DEBUGOUT("Not in Adaptive IFS mode!\n");
6470 }
6471}
6472
6473/******************************************************************************
6474 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6475 *
6476 * hw - Struct containing variables accessed by shared code
6477 * frame_len - The length of the frame in question
6478 * mac_addr - The Ethernet destination address of the frame in question
6479 *****************************************************************************/
6480void
6481e1000_tbi_adjust_stats(struct e1000_hw *hw,
6482 struct e1000_hw_stats *stats,
6483 uint32_t frame_len,
6484 uint8_t *mac_addr)
6485{
6486 uint64_t carry_bit;
6487
6488 /* First adjust the frame length. */
6489 frame_len--;
6490 /* We need to adjust the statistics counters, since the hardware
6491 * counters overcount this packet as a CRC error and undercount
6492 * the packet as a good packet
6493 */
6494 /* This packet should not be counted as a CRC error. */
6495 stats->crcerrs--;
6496 /* This packet does count as a Good Packet Received. */
6497 stats->gprc++;
6498
6499 /* Adjust the Good Octets received counters */
6500 carry_bit = 0x80000000 & stats->gorcl;
6501 stats->gorcl += frame_len;
6502 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6503 * Received Count) was one before the addition,
6504 * AND it is zero after, then we lost the carry out,
6505 * need to add one to Gorch (Good Octets Received Count High).
6506 * This could be simplified if all environments supported
6507 * 64-bit integers.
6508 */
8fc897b0 6509 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
1da177e4
LT		 6510 stats->gorch++;
6511 /* Is this a broadcast or multicast? Check broadcast first,
6512 * since the test for a multicast frame will test positive on
6513 * a broadcast frame.
6514 */
8fc897b0 6515 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
1da177e4
LT		 6516 /* Broadcast packet */
6517 stats->bprc++;
8fc897b0 6518 else if (*mac_addr & 0x01)
1da177e4
LT		 6519 /* Multicast packet */
6520 stats->mprc++;
6521
8fc897b0 6522 if (frame_len == hw->max_frame_size) {
1da177e4
LT		 6523 /* In this case, the hardware has overcounted the number of
6524 * oversize frames.
6525 */
8fc897b0 6526 if (stats->roc > 0)
1da177e4
LT		 6527 stats->roc--;
6528 }
6529
6530 /* Adjust the bin counters when the extra byte put the frame in the
6531 * wrong bin. Remember that the frame_len was adjusted above.
6532 */
8fc897b0 6533 if (frame_len == 64) {
1da177e4
LT		 6534 stats->prc64++;
6535 stats->prc127--;
8fc897b0 6536 } else if (frame_len == 127) {
1da177e4
LT		 6537 stats->prc127++;
6538 stats->prc255--;
8fc897b0 6539 } else if (frame_len == 255) {
1da177e4
LT		 6540 stats->prc255++;
6541 stats->prc511--;
8fc897b0 6542 } else if (frame_len == 511) {
1da177e4
LT		 6543 stats->prc511++;
6544 stats->prc1023--;
8fc897b0 6545 } else if (frame_len == 1023) {
1da177e4
LT		 6546 stats->prc1023++;
6547 stats->prc1522--;
8fc897b0 6548 } else if (frame_len == 1522) {
1da177e4
LT		 6549 stats->prc1522++;
6550 }
6551}
6552
6553/******************************************************************************
6554 * Gets the current PCI bus type, speed, and width of the hardware
6555 *
6556 * hw - Struct containing variables accessed by shared code
6557 *****************************************************************************/
6558void
6559e1000_get_bus_info(struct e1000_hw *hw)
6560{
caeccb68
JK		 6561 int32_t ret_val;
6562 uint16_t pci_ex_link_status;
1da177e4
LT		 6563 uint32_t status;
6564
6565 switch (hw->mac_type) {
6566 case e1000_82542_rev2_0:
6567 case e1000_82542_rev2_1:
6568 hw->bus_type = e1000_bus_type_unknown;
6569 hw->bus_speed = e1000_bus_speed_unknown;
6570 hw->bus_width = e1000_bus_width_unknown;
6571 break;
caeccb68 6572 case e1000_82571:
868d5309 6573 case e1000_82572:
2d7edb92 6574 case e1000_82573:
caeccb68 6575 case e1000_80003es2lan:
fd803241
JK		 6576 hw->bus_type = e1000_bus_type_pci_express;
6577 hw->bus_speed = e1000_bus_speed_2500;
caeccb68
JK		 6578 ret_val = e1000_read_pcie_cap_reg(hw,
6579 PCI_EX_LINK_STATUS,
6580 &pci_ex_link_status);
6581 if (ret_val)
6582 hw->bus_width = e1000_bus_width_unknown;
6583 else
6584 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6585 PCI_EX_LINK_WIDTH_SHIFT;
fd803241 6586 break;
cd94dd0b 6587 case e1000_ich8lan:
2d7edb92
MC		 6588 hw->bus_type = e1000_bus_type_pci_express;
6589 hw->bus_speed = e1000_bus_speed_2500;
caeccb68 6590 hw->bus_width = e1000_bus_width_pciex_1;
2d7edb92 6591 break;
1da177e4
LT		 6592 default:
6593 status = E1000_READ_REG(hw, STATUS);
6594 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6595 e1000_bus_type_pcix : e1000_bus_type_pci;
6596
8fc897b0 6597 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
1da177e4
LT		 6598 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6599 e1000_bus_speed_66 : e1000_bus_speed_120;
8fc897b0 6600 } else if (hw->bus_type == e1000_bus_type_pci) {
1da177e4
LT		 6601 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6602 e1000_bus_speed_66 : e1000_bus_speed_33;
6603 } else {
6604 switch (status & E1000_STATUS_PCIX_SPEED) {
6605 case E1000_STATUS_PCIX_SPEED_66:
6606 hw->bus_speed = e1000_bus_speed_66;
6607 break;
6608 case E1000_STATUS_PCIX_SPEED_100:
6609 hw->bus_speed = e1000_bus_speed_100;
6610 break;
6611 case E1000_STATUS_PCIX_SPEED_133:
6612 hw->bus_speed = e1000_bus_speed_133;
6613 break;
6614 default:
6615 hw->bus_speed = e1000_bus_speed_reserved;
6616 break;
6617 }
6618 }
6619 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6620 e1000_bus_width_64 : e1000_bus_width_32;
6621 break;
6622 }
6623}
1da177e4
LT		 6624
6625/******************************************************************************
6626 * Writes a value to one of the devices registers using port I/O (as opposed to
6627 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6628 *
6629 * hw - Struct containing variables accessed by shared code
6630 * offset - offset to write to
6631 * value - value to write
6632 *****************************************************************************/
3ad2cc67 6633static void
1da177e4
LT		 6634e1000_write_reg_io(struct e1000_hw *hw,
6635 uint32_t offset,
6636 uint32_t value)
6637{
6638 unsigned long io_addr = hw->io_base;
6639 unsigned long io_data = hw->io_base + 4;
6640
6641 e1000_io_write(hw, io_addr, offset);
6642 e1000_io_write(hw, io_data, value);
6643}
6644
1da177e4
LT		 6645/******************************************************************************
6646 * Estimates the cable length.
6647 *
6648 * hw - Struct containing variables accessed by shared code
6649 * min_length - The estimated minimum length
6650 * max_length - The estimated maximum length
6651 *
6652 * returns: - E1000_ERR_XXX
6653 * E1000_SUCCESS
6654 *
6655 * This function always returns a ranged length (minimum & maximum).
6656 * So for M88 phy's, this function interprets the one value returned from the
6657 * register to the minimum and maximum range.
6658 * For IGP phy's, the function calculates the range by the AGC registers.
6659 *****************************************************************************/
3ad2cc67 6660static int32_t
1da177e4
LT		 6661e1000_get_cable_length(struct e1000_hw *hw,
6662 uint16_t *min_length,
6663 uint16_t *max_length)
6664{
6665 int32_t ret_val;
6666 uint16_t agc_value = 0;
1da177e4
LT		 6667 uint16_t i, phy_data;
6668 uint16_t cable_length;
6669
6670 DEBUGFUNC("e1000_get_cable_length");
6671
6672 *min_length = *max_length = 0;
6673
6674 /* Use old method for Phy older than IGP */
8fc897b0 6675 if (hw->phy_type == e1000_phy_m88) {
2d7edb92 6676
1da177e4
LT		 6677 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6678 &phy_data);
8fc897b0 6679 if (ret_val)
1da177e4
LT		 6680 return ret_val;
6681 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6682 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6683
6684 /* Convert the enum value to ranged values */
6685 switch (cable_length) {
6686 case e1000_cable_length_50:
6687 *min_length = 0;
6688 *max_length = e1000_igp_cable_length_50;
6689 break;
6690 case e1000_cable_length_50_80:
6691 *min_length = e1000_igp_cable_length_50;
6692 *max_length = e1000_igp_cable_length_80;
6693 break;
6694 case e1000_cable_length_80_110:
6695 *min_length = e1000_igp_cable_length_80;
6696 *max_length = e1000_igp_cable_length_110;
6697 break;
6698 case e1000_cable_length_110_140:
6699 *min_length = e1000_igp_cable_length_110;
6700 *max_length = e1000_igp_cable_length_140;
6701 break;
6702 case e1000_cable_length_140:
6703 *min_length = e1000_igp_cable_length_140;
6704 *max_length = e1000_igp_cable_length_170;
6705 break;
6706 default:
6707 return -E1000_ERR_PHY;
6708 break;
6709 }
6418ecc6
JK		 6710 } else if (hw->phy_type == e1000_phy_gg82563) {
6711 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6712 &phy_data);
6713 if (ret_val)
6714 return ret_val;
6715 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6716
6717 switch (cable_length) {
6718 case e1000_gg_cable_length_60:
6719 *min_length = 0;
6720 *max_length = e1000_igp_cable_length_60;
6721 break;
6722 case e1000_gg_cable_length_60_115:
6723 *min_length = e1000_igp_cable_length_60;
6724 *max_length = e1000_igp_cable_length_115;
6725 break;
6726 case e1000_gg_cable_length_115_150:
6727 *min_length = e1000_igp_cable_length_115;
6728 *max_length = e1000_igp_cable_length_150;
6729 break;
6730 case e1000_gg_cable_length_150:
6731 *min_length = e1000_igp_cable_length_150;
6732 *max_length = e1000_igp_cable_length_180;
6733 break;
6734 default:
6735 return -E1000_ERR_PHY;
6736 break;
6737 }
8fc897b0 6738 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
cd94dd0b
AK		 6739 uint16_t cur_agc_value;
6740 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
1da177e4
LT		 6741 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6742 {IGP01E1000_PHY_AGC_A,
6743 IGP01E1000_PHY_AGC_B,
6744 IGP01E1000_PHY_AGC_C,
6745 IGP01E1000_PHY_AGC_D};
6746 /* Read the AGC registers for all channels */
8fc897b0 6747 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4
LT		 6748
6749 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
8fc897b0 6750 if (ret_val)
1da177e4
LT		 6751 return ret_val;
6752
cd94dd0b 6753 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
1da177e4 6754
cd94dd0b
AK		 6755 /* Value bound check. */
6756 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6757 (cur_agc_value == 0))
1da177e4
LT		 6758 return -E1000_ERR_PHY;
6759
cd94dd0b 6760 agc_value += cur_agc_value;
1da177e4
LT		 6761
6762 /* Update minimal AGC value. */
cd94dd0b
AK		 6763 if (min_agc_value > cur_agc_value)
6764 min_agc_value = cur_agc_value;
1da177e4
LT		 6765 }
6766
6767 /* Remove the minimal AGC result for length < 50m */
cd94dd0b
AK		 6768 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6769 agc_value -= min_agc_value;
1da177e4
LT		 6770
6771 /* Get the average length of the remaining 3 channels */
6772 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6773 } else {
6774 /* Get the average length of all the 4 channels. */
6775 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6776 }
6777
6778 /* Set the range of the calculated length. */
6779 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6780 IGP01E1000_AGC_RANGE) > 0) ?
6781 (e1000_igp_cable_length_table[agc_value] -
6782 IGP01E1000_AGC_RANGE) : 0;
6783 *max_length = e1000_igp_cable_length_table[agc_value] +
6784 IGP01E1000_AGC_RANGE;
cd94dd0b
AK		 6785 } else if (hw->phy_type == e1000_phy_igp_2 ||
6786 hw->phy_type == e1000_phy_igp_3) {
6787 uint16_t cur_agc_index, max_agc_index = 0;
6788 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
868d5309
MC		 6789 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6790 {IGP02E1000_PHY_AGC_A,
6791 IGP02E1000_PHY_AGC_B,
6792 IGP02E1000_PHY_AGC_C,
6793 IGP02E1000_PHY_AGC_D};
6794 /* Read the AGC registers for all channels */
6795 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6796 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6797 if (ret_val)
6798 return ret_val;
6799
8fc897b0 6800 /* Getting bits 15:9, which represent the combination of course and
868d5309
MC		 6801 * fine gain values. The result is a number that can be put into
6802 * the lookup table to obtain the approximate cable length. */
cd94dd0b
AK		 6803 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6804 IGP02E1000_AGC_LENGTH_MASK;
868d5309 6805
cd94dd0b
AK		 6806 /* Array index bound check. */
6807 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6808 (cur_agc_index == 0))
6809 return -E1000_ERR_PHY;
868d5309 6810
cd94dd0b
AK		 6811 /* Remove min & max AGC values from calculation. */
6812 if (e1000_igp_2_cable_length_table[min_agc_index] >
6813 e1000_igp_2_cable_length_table[cur_agc_index])
6814 min_agc_index = cur_agc_index;
6815 if (e1000_igp_2_cable_length_table[max_agc_index] <
6816 e1000_igp_2_cable_length_table[cur_agc_index])
6817 max_agc_index = cur_agc_index;
6818
6819 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
868d5309
MC		 6820 }
6821
cd94dd0b
AK		 6822 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6823 e1000_igp_2_cable_length_table[max_agc_index]);
868d5309
MC		 6824 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6825
6826 /* Calculate cable length with the error range of +/- 10 meters. */
6827 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6828 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6829 *max_length = agc_value + IGP02E1000_AGC_RANGE;
1da177e4
LT		 6830 }
6831
6832 return E1000_SUCCESS;
6833}
6834
6835/******************************************************************************
6836 * Check the cable polarity
6837 *
6838 * hw - Struct containing variables accessed by shared code
6839 * polarity - output parameter : 0 - Polarity is not reversed
6840 * 1 - Polarity is reversed.
6841 *
6842 * returns: - E1000_ERR_XXX
6843 * E1000_SUCCESS
6844 *
6845 * For phy's older then IGP, this function simply reads the polarity bit in the
6846 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6847 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6848 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6849 * IGP01E1000_PHY_PCS_INIT_REG.
6850 *****************************************************************************/
3ad2cc67 6851static int32_t
1da177e4 6852e1000_check_polarity(struct e1000_hw *hw,
70c6f30a 6853 e1000_rev_polarity *polarity)
1da177e4
LT		 6854{
6855 int32_t ret_val;
6856 uint16_t phy_data;
6857
6858 DEBUGFUNC("e1000_check_polarity");
6859
6418ecc6
JK		 6860 if ((hw->phy_type == e1000_phy_m88) ||
6861 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4
LT		 6862 /* return the Polarity bit in the Status register. */
6863 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6864 &phy_data);
8fc897b0 6865 if (ret_val)
1da177e4 6866 return ret_val;
70c6f30a
JK		 6867 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6868 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6869 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6870
cd94dd0b
AK		 6871 } else if (hw->phy_type == e1000_phy_igp ||
6872 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 6873 hw->phy_type == e1000_phy_igp_2) {
1da177e4
LT		 6874 /* Read the Status register to check the speed */
6875 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6876 &phy_data);
8fc897b0 6877 if (ret_val)
1da177e4
LT		 6878 return ret_val;
6879
6880 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6881 * find the polarity status */
8fc897b0 6882 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1da177e4
LT		 6883 IGP01E1000_PSSR_SPEED_1000MBPS) {
6884
6885 /* Read the GIG initialization PCS register (0x00B4) */
6886 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6887 &phy_data);
8fc897b0 6888 if (ret_val)
1da177e4
LT		 6889 return ret_val;
6890
6891 /* Check the polarity bits */
70c6f30a
JK		 6892 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6893 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
1da177e4
LT		 6894 } else {
6895 /* For 10 Mbps, read the polarity bit in the status register. (for
6896 * 100 Mbps this bit is always 0) */
70c6f30a
JK		 6897 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6898 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
1da177e4 6899 }
cd94dd0b
AK		 6900 } else if (hw->phy_type == e1000_phy_ife) {
6901 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6902 &phy_data);
6903 if (ret_val)
6904 return ret_val;
70c6f30a
JK		 6905 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6906 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6907 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
1da177e4
LT		 6908 }
6909 return E1000_SUCCESS;
6910}
6911
6912/******************************************************************************
6913 * Check if Downshift occured
6914 *
6915 * hw - Struct containing variables accessed by shared code
6916 * downshift - output parameter : 0 - No Downshift ocured.
6917 * 1 - Downshift ocured.
6918 *
6919 * returns: - E1000_ERR_XXX
76c224bc 6920 * E1000_SUCCESS
1da177e4
LT		 6921 *
6922 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6923 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6924 * Link Health register. In IGP this bit is latched high, so the driver must
6925 * read it immediately after link is established.
6926 *****************************************************************************/
3ad2cc67 6927static int32_t
1da177e4
LT		 6928e1000_check_downshift(struct e1000_hw *hw)
6929{
6930 int32_t ret_val;
6931 uint16_t phy_data;
6932
6933 DEBUGFUNC("e1000_check_downshift");
6934
cd94dd0b
AK		 6935 if (hw->phy_type == e1000_phy_igp ||
6936 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 6937 hw->phy_type == e1000_phy_igp_2) {
1da177e4
LT		 6938 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6939 &phy_data);
8fc897b0 6940 if (ret_val)
1da177e4
LT		 6941 return ret_val;
6942
6943 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6418ecc6
JK		 6944 } else if ((hw->phy_type == e1000_phy_m88) ||
6945 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4
LT		 6946 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6947 &phy_data);
8fc897b0 6948 if (ret_val)
1da177e4
LT		 6949 return ret_val;
6950
6951 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6952 M88E1000_PSSR_DOWNSHIFT_SHIFT;
cd94dd0b
AK		 6953 } else if (hw->phy_type == e1000_phy_ife) {
6954 /* e1000_phy_ife supports 10/100 speed only */
6955 hw->speed_downgraded = FALSE;
1da177e4 6956 }
2d7edb92 6957
1da177e4
LT		 6958 return E1000_SUCCESS;
6959}
6960
6961/*****************************************************************************
6962 *
6963 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6964 * gigabit link is achieved to improve link quality.
6965 *
6966 * hw: Struct containing variables accessed by shared code
6967 *
6968 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6969 * E1000_SUCCESS at any other case.
6970 *
6971 ****************************************************************************/
6972
3ad2cc67 6973static int32_t
1da177e4
LT		 6974e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6975 boolean_t link_up)
6976{
6977 int32_t ret_val;
6978 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6979 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6980 {IGP01E1000_PHY_AGC_PARAM_A,
6981 IGP01E1000_PHY_AGC_PARAM_B,
6982 IGP01E1000_PHY_AGC_PARAM_C,
6983 IGP01E1000_PHY_AGC_PARAM_D};
6984 uint16_t min_length, max_length;
6985
6986 DEBUGFUNC("e1000_config_dsp_after_link_change");
6987
8fc897b0 6988 if (hw->phy_type != e1000_phy_igp)
1da177e4
LT		 6989 return E1000_SUCCESS;
6990
8fc897b0 6991 if (link_up) {
1da177e4 6992 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
8fc897b0 6993 if (ret_val) {
1da177e4
LT		 6994 DEBUGOUT("Error getting link speed and duplex\n");
6995 return ret_val;
6996 }
6997
8fc897b0 6998 if (speed == SPEED_1000) {
1da177e4 6999
cd94dd0b
AK		 7000 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7001 if (ret_val)
7002 return ret_val;
1da177e4 7003
8fc897b0 7004 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
1da177e4
LT		 7005 min_length >= e1000_igp_cable_length_50) {
7006
8fc897b0 7007 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4
LT		 7008 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7009 &phy_data);
8fc897b0 7010 if (ret_val)
1da177e4
LT		 7011 return ret_val;
7012
7013 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7014
7015 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7016 phy_data);
8fc897b0 7017 if (ret_val)
1da177e4
LT		 7018 return ret_val;
7019 }
7020 hw->dsp_config_state = e1000_dsp_config_activated;
7021 }
7022
8fc897b0 7023 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
1da177e4
LT		 7024 (min_length < e1000_igp_cable_length_50)) {
7025
7026 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7027 uint32_t idle_errs = 0;
7028
7029 /* clear previous idle error counts */
7030 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7031 &phy_data);
8fc897b0 7032 if (ret_val)
1da177e4
LT		 7033 return ret_val;
7034
8fc897b0 7035 for (i = 0; i < ffe_idle_err_timeout; i++) {
1da177e4
LT		 7036 udelay(1000);
7037 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7038 &phy_data);
8fc897b0 7039 if (ret_val)
1da177e4
LT		 7040 return ret_val;
7041
7042 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
8fc897b0 7043 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
1da177e4
LT		 7044 hw->ffe_config_state = e1000_ffe_config_active;
7045
7046 ret_val = e1000_write_phy_reg(hw,
7047 IGP01E1000_PHY_DSP_FFE,
7048 IGP01E1000_PHY_DSP_FFE_CM_CP);
8fc897b0 7049 if (ret_val)
1da177e4
LT		 7050 return ret_val;
7051 break;
7052 }
7053
8fc897b0 7054 if (idle_errs)
1da177e4
LT		 7055 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7056 }
7057 }
7058 }
7059 } else {
8fc897b0 7060 if (hw->dsp_config_state == e1000_dsp_config_activated) {
1da177e4
LT		 7061 /* Save off the current value of register 0x2F5B to be restored at
7062 * the end of the routines. */
7063 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7064
8fc897b0 7065 if (ret_val)
1da177e4
LT		 7066 return ret_val;
7067
7068 /* Disable the PHY transmitter */
7069 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7070
8fc897b0 7071 if (ret_val)
1da177e4
LT		 7072 return ret_val;
7073
f8ec4733 7074 mdelay(20);
1da177e4
LT		 7075
7076 ret_val = e1000_write_phy_reg(hw, 0x0000,
7077 IGP01E1000_IEEE_FORCE_GIGA);
8fc897b0 7078 if (ret_val)
1da177e4 7079 return ret_val;
8fc897b0 7080 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4 7081 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
8fc897b0 7082 if (ret_val)
1da177e4
LT		 7083 return ret_val;
7084
7085 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7086 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7087
7088 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
8fc897b0 7089 if (ret_val)
1da177e4
LT		 7090 return ret_val;
7091 }
7092
7093 ret_val = e1000_write_phy_reg(hw, 0x0000,
7094 IGP01E1000_IEEE_RESTART_AUTONEG);
8fc897b0 7095 if (ret_val)
1da177e4
LT		 7096 return ret_val;
7097
f8ec4733 7098 mdelay(20);
1da177e4
LT		 7099
7100 /* Now enable the transmitter */
7101 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7102
8fc897b0 7103 if (ret_val)
1da177e4
LT		 7104 return ret_val;
7105
7106 hw->dsp_config_state = e1000_dsp_config_enabled;
7107 }
7108
8fc897b0 7109 if (hw->ffe_config_state == e1000_ffe_config_active) {
1da177e4
LT		 7110 /* Save off the current value of register 0x2F5B to be restored at
7111 * the end of the routines. */
7112 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7113
8fc897b0 7114 if (ret_val)
1da177e4
LT		 7115 return ret_val;
7116
7117 /* Disable the PHY transmitter */
7118 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7119
8fc897b0 7120 if (ret_val)
1da177e4
LT		 7121 return ret_val;
7122
f8ec4733 7123 mdelay(20);
1da177e4
LT		 7124
7125 ret_val = e1000_write_phy_reg(hw, 0x0000,
7126 IGP01E1000_IEEE_FORCE_GIGA);
8fc897b0 7127 if (ret_val)
1da177e4
LT		 7128 return ret_val;
7129 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7130 IGP01E1000_PHY_DSP_FFE_DEFAULT);
8fc897b0 7131 if (ret_val)
1da177e4
LT		 7132 return ret_val;
7133
7134 ret_val = e1000_write_phy_reg(hw, 0x0000,
7135 IGP01E1000_IEEE_RESTART_AUTONEG);
8fc897b0 7136 if (ret_val)
1da177e4
LT		 7137 return ret_val;
7138
f8ec4733 7139 mdelay(20);
1da177e4
LT		 7140
7141 /* Now enable the transmitter */
7142 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7143
8fc897b0 7144 if (ret_val)
1da177e4
LT		 7145 return ret_val;
7146
7147 hw->ffe_config_state = e1000_ffe_config_enabled;
7148 }
7149 }
7150 return E1000_SUCCESS;
7151}
7152
7153/*****************************************************************************
7154 * Set PHY to class A mode
7155 * Assumes the following operations will follow to enable the new class mode.
7156 * 1. Do a PHY soft reset
7157 * 2. Restart auto-negotiation or force link.
7158 *
7159 * hw - Struct containing variables accessed by shared code
7160 ****************************************************************************/
7161static int32_t
7162e1000_set_phy_mode(struct e1000_hw *hw)
7163{
7164 int32_t ret_val;
7165 uint16_t eeprom_data;
7166
7167 DEBUGFUNC("e1000_set_phy_mode");
7168
8fc897b0
AK		 7169 if ((hw->mac_type == e1000_82545_rev_3) &&
7170 (hw->media_type == e1000_media_type_copper)) {
1da177e4 7171 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
8fc897b0 7172 if (ret_val) {
1da177e4
LT		 7173 return ret_val;
7174 }
7175
8fc897b0
AK		 7176 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7177 (eeprom_data & EEPROM_PHY_CLASS_A)) {
1da177e4 7178 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
8fc897b0 7179 if (ret_val)
1da177e4
LT		 7180 return ret_val;
7181 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
8fc897b0 7182 if (ret_val)
1da177e4
LT		 7183 return ret_val;
7184
7185 hw->phy_reset_disable = FALSE;
7186 }
7187 }
7188
7189 return E1000_SUCCESS;
7190}
7191
7192/*****************************************************************************
7193 *
7194 * This function sets the lplu state according to the active flag. When
7195 * activating lplu this function also disables smart speed and vise versa.
7196 * lplu will not be activated unless the device autonegotiation advertisment
7197 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7198 * hw: Struct containing variables accessed by shared code
7199 * active - true to enable lplu false to disable lplu.
7200 *
7201 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7202 * E1000_SUCCESS at any other case.
7203 *
7204 ****************************************************************************/
7205
3ad2cc67 7206static int32_t
1da177e4
LT		 7207e1000_set_d3_lplu_state(struct e1000_hw *hw,
7208 boolean_t active)
7209{
cd94dd0b 7210 uint32_t phy_ctrl = 0;
1da177e4
LT		 7211 int32_t ret_val;
7212 uint16_t phy_data;
7213 DEBUGFUNC("e1000_set_d3_lplu_state");
7214
cd94dd0b
AK		 7215 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7216 && hw->phy_type != e1000_phy_igp_3)
1da177e4
LT		 7217 return E1000_SUCCESS;
7218
7219 /* During driver activity LPLU should not be used or it will attain link
7220 * from the lowest speeds starting from 10Mbps. The capability is used for
7221 * Dx transitions and states */
cd94dd0b 7222 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
2d7edb92 7223 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
cd94dd0b 7224 if (ret_val)
2d7edb92 7225 return ret_val;
cd94dd0b
AK		 7226 } else if (hw->mac_type == e1000_ich8lan) {
7227 /* MAC writes into PHY register based on the state transition
7228 * and start auto-negotiation. SW driver can overwrite the settings
7229 * in CSR PHY power control E1000_PHY_CTRL register. */
7230 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2d7edb92
MC		 7231 } else {
7232 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
8fc897b0 7233 if (ret_val)
1da177e4 7234 return ret_val;
2d7edb92
MC		 7235 }
7236
8fc897b0
AK		 7237 if (!active) {
7238 if (hw->mac_type == e1000_82541_rev_2 ||
7239 hw->mac_type == e1000_82547_rev_2) {
2d7edb92
MC		 7240 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7241 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
8fc897b0 7242 if (ret_val)
2d7edb92
MC		 7243 return ret_val;
7244 } else {
cd94dd0b
AK		 7245 if (hw->mac_type == e1000_ich8lan) {
7246 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7247 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7248 } else {
2d7edb92
MC		 7249 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7250 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7251 phy_data);
7252 if (ret_val)
7253 return ret_val;
cd94dd0b 7254 }
2d7edb92 7255 }
1da177e4
LT		 7256
7257 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7258 * Dx states where the power conservation is most important. During
7259 * driver activity we should enable SmartSpeed, so performance is
7260 * maintained. */
7261 if (hw->smart_speed == e1000_smart_speed_on) {
7262 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7263 &phy_data);
8fc897b0 7264 if (ret_val)
1da177e4
LT		 7265 return ret_val;
7266
7267 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7268 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7269 phy_data);
8fc897b0 7270 if (ret_val)
1da177e4
LT		 7271 return ret_val;
7272 } else if (hw->smart_speed == e1000_smart_speed_off) {
7273 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7274 &phy_data);
35574764 7275 if (ret_val)
1da177e4
LT		 7276 return ret_val;
7277
7278 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7279 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7280 phy_data);
8fc897b0 7281 if (ret_val)
1da177e4
LT		 7282 return ret_val;
7283 }
7284
8fc897b0
AK		 7285 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7286 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7287 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
1da177e4 7288
8fc897b0 7289 if (hw->mac_type == e1000_82541_rev_2 ||
cd94dd0b 7290 hw->mac_type == e1000_82547_rev_2) {
2d7edb92
MC		 7291 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7292 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
8fc897b0 7293 if (ret_val)
2d7edb92
MC		 7294 return ret_val;
7295 } else {
cd94dd0b
AK		 7296 if (hw->mac_type == e1000_ich8lan) {
7297 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7298 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7299 } else {
2d7edb92
MC		 7300 phy_data |= IGP02E1000_PM_D3_LPLU;
7301 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7302 phy_data);
7303 if (ret_val)
7304 return ret_val;
cd94dd0b 7305 }
2d7edb92
MC		 7306 }
7307
7308 /* When LPLU is enabled we should disable SmartSpeed */
7309 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8fc897b0 7310 if (ret_val)
2d7edb92
MC		 7311 return ret_val;
7312
7313 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7314 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
8fc897b0 7315 if (ret_val)
2d7edb92
MC		 7316 return ret_val;
7317
7318 }
7319 return E1000_SUCCESS;
7320}
7321
7322/*****************************************************************************
7323 *
7324 * This function sets the lplu d0 state according to the active flag. When
7325 * activating lplu this function also disables smart speed and vise versa.
7326 * lplu will not be activated unless the device autonegotiation advertisment
7327 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7328 * hw: Struct containing variables accessed by shared code
7329 * active - true to enable lplu false to disable lplu.
7330 *
7331 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7332 * E1000_SUCCESS at any other case.
7333 *
7334 ****************************************************************************/
7335
3ad2cc67 7336static int32_t
2d7edb92
MC		 7337e1000_set_d0_lplu_state(struct e1000_hw *hw,
7338 boolean_t active)
7339{
cd94dd0b 7340 uint32_t phy_ctrl = 0;
2d7edb92
MC		 7341 int32_t ret_val;
7342 uint16_t phy_data;
7343 DEBUGFUNC("e1000_set_d0_lplu_state");
7344
8fc897b0 7345 if (hw->mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 7346 return E1000_SUCCESS;
7347
cd94dd0b
AK		 7348 if (hw->mac_type == e1000_ich8lan) {
7349 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7350 } else {
2d7edb92 7351 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
8fc897b0 7352 if (ret_val)
1da177e4 7353 return ret_val;
cd94dd0b 7354 }
1da177e4 7355
2d7edb92 7356 if (!active) {
cd94dd0b
AK		 7357 if (hw->mac_type == e1000_ich8lan) {
7358 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7359 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7360 } else {
2d7edb92
MC		 7361 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7362 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7363 if (ret_val)
7364 return ret_val;
cd94dd0b 7365 }
2d7edb92
MC		 7366
7367 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7368 * Dx states where the power conservation is most important. During
7369 * driver activity we should enable SmartSpeed, so performance is
7370 * maintained. */
7371 if (hw->smart_speed == e1000_smart_speed_on) {
7372 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7373 &phy_data);
8fc897b0 7374 if (ret_val)
2d7edb92
MC		 7375 return ret_val;
7376
7377 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7378 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7379 phy_data);
8fc897b0 7380 if (ret_val)
2d7edb92
MC		 7381 return ret_val;
7382 } else if (hw->smart_speed == e1000_smart_speed_off) {
7383 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7384 &phy_data);
35574764 7385 if (ret_val)
2d7edb92
MC		 7386 return ret_val;
7387
7388 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7389 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7390 phy_data);
8fc897b0 7391 if (ret_val)
2d7edb92
MC		 7392 return ret_val;
7393 }
7394
7395
7396 } else {
76c224bc 7397
cd94dd0b
AK		 7398 if (hw->mac_type == e1000_ich8lan) {
7399 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7400 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7401 } else {
76c224bc 7402 phy_data |= IGP02E1000_PM_D0_LPLU;
2d7edb92
MC		 7403 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7404 if (ret_val)
7405 return ret_val;
cd94dd0b 7406 }
2d7edb92 7407
1da177e4
LT		 7408 /* When LPLU is enabled we should disable SmartSpeed */
7409 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8fc897b0 7410 if (ret_val)
1da177e4
LT		 7411 return ret_val;
7412
7413 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7414 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
8fc897b0 7415 if (ret_val)
1da177e4
LT		 7416 return ret_val;
7417
7418 }
7419 return E1000_SUCCESS;
7420}
7421
7422/******************************************************************************
7423 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7424 *
7425 * hw - Struct containing variables accessed by shared code
7426 *****************************************************************************/
7427static int32_t
7428e1000_set_vco_speed(struct e1000_hw *hw)
7429{
7430 int32_t ret_val;
7431 uint16_t default_page = 0;
7432 uint16_t phy_data;
7433
7434 DEBUGFUNC("e1000_set_vco_speed");
7435
8fc897b0 7436 switch (hw->mac_type) {
1da177e4
LT		 7437 case e1000_82545_rev_3:
7438 case e1000_82546_rev_3:
7439 break;
7440 default:
7441 return E1000_SUCCESS;
7442 }
7443
7444 /* Set PHY register 30, page 5, bit 8 to 0 */
7445
7446 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
8fc897b0 7447 if (ret_val)
1da177e4
LT		 7448 return ret_val;
7449
7450 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
8fc897b0 7451 if (ret_val)
1da177e4
LT		 7452 return ret_val;
7453
7454 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8fc897b0 7455 if (ret_val)
1da177e4
LT		 7456 return ret_val;
7457
7458 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7459 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8fc897b0 7460 if (ret_val)
1da177e4
LT		 7461 return ret_val;
7462
7463 /* Set PHY register 30, page 4, bit 11 to 1 */
7464
7465 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
8fc897b0 7466 if (ret_val)
1da177e4
LT		 7467 return ret_val;
7468
7469 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8fc897b0 7470 if (ret_val)
1da177e4
LT		 7471 return ret_val;
7472
7473 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7474 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8fc897b0 7475 if (ret_val)
1da177e4
LT		 7476 return ret_val;
7477
7478 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
8fc897b0 7479 if (ret_val)
1da177e4
LT		 7480 return ret_val;
7481
7482 return E1000_SUCCESS;
7483}
7484
1da177e4 7485
2d7edb92
MC		 7486/*****************************************************************************
7487 * This function reads the cookie from ARC ram.
7488 *
7489 * returns: - E1000_SUCCESS .
7490 ****************************************************************************/
35574764 7491static int32_t
2d7edb92
MC		 7492e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7493{
7494 uint8_t i;
76c224bc 7495 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
2d7edb92 7496 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
1da177e4 7497
2d7edb92
MC		 7498 length = (length >> 2);
7499 offset = (offset >> 2);
1da177e4 7500
2d7edb92
MC		 7501 for (i = 0; i < length; i++) {
7502 *((uint32_t *) buffer + i) =
7503 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7504 }
7505 return E1000_SUCCESS;
7506}
7507
7508
7509/*****************************************************************************
7510 * This function checks whether the HOST IF is enabled for command operaton
7511 * and also checks whether the previous command is completed.
7512 * It busy waits in case of previous command is not completed.
7513 *
76c224bc 7514 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
2d7edb92
MC		 7515 * timeout
7516 * - E1000_SUCCESS for success.
7517 ****************************************************************************/
3ad2cc67 7518static int32_t
2d7edb92
MC		 7519e1000_mng_enable_host_if(struct e1000_hw * hw)
7520{
7521 uint32_t hicr;
7522 uint8_t i;
7523
7524 /* Check that the host interface is enabled. */
7525 hicr = E1000_READ_REG(hw, HICR);
7526 if ((hicr & E1000_HICR_EN) == 0) {
7527 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7528 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7529 }
7530 /* check the previous command is completed */
7531 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7532 hicr = E1000_READ_REG(hw, HICR);
7533 if (!(hicr & E1000_HICR_C))
7534 break;
f8ec4733 7535 mdelay(1);
2d7edb92
MC		 7536 }
7537
76c224bc 7538 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2d7edb92
MC		 7539 DEBUGOUT("Previous command timeout failed .\n");
7540 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7541 }
7542 return E1000_SUCCESS;
7543}
7544
7545/*****************************************************************************
7546 * This function writes the buffer content at the offset given on the host if.
7547 * It also does alignment considerations to do the writes in most efficient way.
7548 * Also fills up the sum of the buffer in *buffer parameter.
7549 *
7550 * returns - E1000_SUCCESS for success.
7551 ****************************************************************************/
3ad2cc67 7552static int32_t
2d7edb92
MC		 7553e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7554 uint16_t length, uint16_t offset, uint8_t *sum)
7555{
7556 uint8_t *tmp;
7557 uint8_t *bufptr = buffer;
8fc897b0 7558 uint32_t data = 0;
2d7edb92
MC		 7559 uint16_t remaining, i, j, prev_bytes;
7560
7561 /* sum = only sum of the data and it is not checksum */
7562
7563 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7564 return -E1000_ERR_PARAM;
7565 }
7566
7567 tmp = (uint8_t *)&data;
7568 prev_bytes = offset & 0x3;
7569 offset &= 0xFFFC;
7570 offset >>= 2;
7571
7572 if (prev_bytes) {
7573 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7574 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7575 *(tmp + j) = *bufptr++;
7576 *sum += *(tmp + j);
7577 }
7578 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7579 length -= j - prev_bytes;
7580 offset++;
7581 }
7582
7583 remaining = length & 0x3;
7584 length -= remaining;
7585
7586 /* Calculate length in DWORDs */
7587 length >>= 2;
7588
7589 /* The device driver writes the relevant command block into the
7590 * ram area. */
7591 for (i = 0; i < length; i++) {
7592 for (j = 0; j < sizeof(uint32_t); j++) {
7593 *(tmp + j) = *bufptr++;
7594 *sum += *(tmp + j);
7595 }
7596
7597 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7598 }
7599 if (remaining) {
7600 for (j = 0; j < sizeof(uint32_t); j++) {
7601 if (j < remaining)
7602 *(tmp + j) = *bufptr++;
7603 else
7604 *(tmp + j) = 0;
7605
7606 *sum += *(tmp + j);
7607 }
7608 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7609 }
7610
7611 return E1000_SUCCESS;
7612}
7613
7614
7615/*****************************************************************************
7616 * This function writes the command header after does the checksum calculation.
7617 *
7618 * returns - E1000_SUCCESS for success.
7619 ****************************************************************************/
3ad2cc67 7620static int32_t
2d7edb92
MC		 7621e1000_mng_write_cmd_header(struct e1000_hw * hw,
7622 struct e1000_host_mng_command_header * hdr)
7623{
7624 uint16_t i;
7625 uint8_t sum;
7626 uint8_t *buffer;
7627
7628 /* Write the whole command header structure which includes sum of
7629 * the buffer */
7630
7631 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7632
7633 sum = hdr->checksum;
7634 hdr->checksum = 0;
7635
7636 buffer = (uint8_t *) hdr;
7637 i = length;
8fc897b0 7638 while (i--)
2d7edb92
MC		 7639 sum += buffer[i];
7640
7641 hdr->checksum = 0 - sum;
7642
7643 length >>= 2;
7644 /* The device driver writes the relevant command block into the ram area. */
4ca213a6 7645 for (i = 0; i < length; i++) {
2d7edb92 7646 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
4ca213a6
AK		 7647 E1000_WRITE_FLUSH(hw);
7648 }
2d7edb92
MC		 7649
7650 return E1000_SUCCESS;
7651}
7652
7653
7654/*****************************************************************************
7655 * This function indicates to ARC that a new command is pending which completes
7656 * one write operation by the driver.
7657 *
7658 * returns - E1000_SUCCESS for success.
7659 ****************************************************************************/
3ad2cc67 7660static int32_t
8fc897b0 7661e1000_mng_write_commit(struct e1000_hw * hw)
2d7edb92
MC		 7662{
7663 uint32_t hicr;
7664
7665 hicr = E1000_READ_REG(hw, HICR);
7666 /* Setting this bit tells the ARC that a new command is pending. */
7667 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7668
7669 return E1000_SUCCESS;
7670}
7671
7672
7673/*****************************************************************************
7674 * This function checks the mode of the firmware.
7675 *
7676 * returns - TRUE when the mode is IAMT or FALSE.
7677 ****************************************************************************/
7678boolean_t
cd94dd0b 7679e1000_check_mng_mode(struct e1000_hw *hw)
2d7edb92
MC		 7680{
7681 uint32_t fwsm;
7682
7683 fwsm = E1000_READ_REG(hw, FWSM);
7684
cd94dd0b
AK		 7685 if (hw->mac_type == e1000_ich8lan) {
7686 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7687 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7688 return TRUE;
7689 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7690 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2d7edb92
MC		 7691 return TRUE;
7692
7693 return FALSE;
7694}
7695
7696
7697/*****************************************************************************
7698 * This function writes the dhcp info .
7699 ****************************************************************************/
7700int32_t
7701e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
35574764 7702 uint16_t length)
2d7edb92
MC		 7703{
7704 int32_t ret_val;
7705 struct e1000_host_mng_command_header hdr;
7706
7707 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7708 hdr.command_length = length;
7709 hdr.reserved1 = 0;
7710 hdr.reserved2 = 0;
7711 hdr.checksum = 0;
7712
7713 ret_val = e1000_mng_enable_host_if(hw);
7714 if (ret_val == E1000_SUCCESS) {
7715 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7716 &(hdr.checksum));
7717 if (ret_val == E1000_SUCCESS) {
7718 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7719 if (ret_val == E1000_SUCCESS)
7720 ret_val = e1000_mng_write_commit(hw);
7721 }
7722 }
7723 return ret_val;
7724}
7725
7726
7727/*****************************************************************************
7728 * This function calculates the checksum.
7729 *
7730 * returns - checksum of buffer contents.
7731 ****************************************************************************/
35574764 7732static uint8_t
2d7edb92
MC		 7733e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7734{
7735 uint8_t sum = 0;
7736 uint32_t i;
7737
7738 if (!buffer)
7739 return 0;
7740
7741 for (i=0; i < length; i++)
7742 sum += buffer[i];
7743
7744 return (uint8_t) (0 - sum);
7745}
7746
7747/*****************************************************************************
7748 * This function checks whether tx pkt filtering needs to be enabled or not.
7749 *
7750 * returns - TRUE for packet filtering or FALSE.
7751 ****************************************************************************/
7752boolean_t
7753e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7754{
7755 /* called in init as well as watchdog timer functions */
7756
7757 int32_t ret_val, checksum;
7758 boolean_t tx_filter = FALSE;
7759 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7760 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7761
7762 if (e1000_check_mng_mode(hw)) {
7763 ret_val = e1000_mng_enable_host_if(hw);
7764 if (ret_val == E1000_SUCCESS) {
7765 ret_val = e1000_host_if_read_cookie(hw, buffer);
7766 if (ret_val == E1000_SUCCESS) {
7767 checksum = hdr->checksum;
7768 hdr->checksum = 0;
7769 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7770 checksum == e1000_calculate_mng_checksum((char *)buffer,
7771 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7772 if (hdr->status &
7773 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7774 tx_filter = TRUE;
7775 } else
7776 tx_filter = TRUE;
7777 } else
7778 tx_filter = TRUE;
7779 }
7780 }
7781
7782 hw->tx_pkt_filtering = tx_filter;
7783 return tx_filter;
7784}
7785
7786/******************************************************************************
7787 * Verifies the hardware needs to allow ARPs to be processed by the host
7788 *
7789 * hw - Struct containing variables accessed by shared code
7790 *
7791 * returns: - TRUE/FALSE
7792 *
7793 *****************************************************************************/
7794uint32_t
7795e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7796{
7797 uint32_t manc;
7798 uint32_t fwsm, factps;
7799
7800 if (hw->asf_firmware_present) {
7801 manc = E1000_READ_REG(hw, MANC);
7802
7803 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7804 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7805 return FALSE;
7806 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7807 fwsm = E1000_READ_REG(hw, FWSM);
7808 factps = E1000_READ_REG(hw, FACTPS);
7809
7810 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7811 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7812 (factps & E1000_FACTPS_MNGCG))
7813 return TRUE;
7814 } else
7815 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7816 return TRUE;
7817 }
7818 return FALSE;
7819}
7820
7821static int32_t
7822e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7823{
7824 int32_t ret_val;
7825 uint16_t mii_status_reg;
7826 uint16_t i;
7827
7828 /* Polarity reversal workaround for forced 10F/10H links. */
7829
7830 /* Disable the transmitter on the PHY */
7831
7832 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8fc897b0 7833 if (ret_val)
1da177e4
LT		 7834 return ret_val;
7835 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
8fc897b0 7836 if (ret_val)
1da177e4
LT		 7837 return ret_val;
7838
7839 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8fc897b0 7840 if (ret_val)
1da177e4
LT		 7841 return ret_val;
7842
7843 /* This loop will early-out if the NO link condition has been met. */
8fc897b0 7844 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 7845 /* Read the MII Status Register and wait for Link Status bit
7846 * to be clear.
7847 */
7848
7849 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7850 if (ret_val)
1da177e4
LT		 7851 return ret_val;
7852
7853 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7854 if (ret_val)
1da177e4
LT		 7855 return ret_val;
7856
8fc897b0 7857 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
f8ec4733 7858 mdelay(100);
1da177e4
LT		 7859 }
7860
7861 /* Recommended delay time after link has been lost */
f8ec4733 7862 mdelay(1000);
1da177e4
LT		 7863
7864 /* Now we will re-enable th transmitter on the PHY */
7865
7866 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8fc897b0 7867 if (ret_val)
1da177e4 7868 return ret_val;
f8ec4733 7869 mdelay(50);
1da177e4 7870 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
8fc897b0 7871 if (ret_val)
1da177e4 7872 return ret_val;
f8ec4733 7873 mdelay(50);
1da177e4 7874 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
8fc897b0 7875 if (ret_val)
1da177e4 7876 return ret_val;
f8ec4733 7877 mdelay(50);
1da177e4 7878 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
8fc897b0 7879 if (ret_val)
1da177e4
LT		 7880 return ret_val;
7881
7882 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8fc897b0 7883 if (ret_val)
1da177e4
LT		 7884 return ret_val;
7885
7886 /* This loop will early-out if the link condition has been met. */
8fc897b0 7887 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 7888 /* Read the MII Status Register and wait for Link Status bit
7889 * to be set.
7890 */
7891
7892 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7893 if (ret_val)
1da177e4
LT		 7894 return ret_val;
7895
7896 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7897 if (ret_val)
1da177e4
LT		 7898 return ret_val;
7899
8fc897b0 7900 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 7901 mdelay(100);
1da177e4
LT		 7902 }
7903 return E1000_SUCCESS;
7904}
7905
2d7edb92
MC		 7906/***************************************************************************
7907 *
7908 * Disables PCI-Express master access.
7909 *
7910 * hw: Struct containing variables accessed by shared code
7911 *
7912 * returns: - none.
7913 *
7914 ***************************************************************************/
3ad2cc67 7915static void
2d7edb92
MC		 7916e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7917{
7918 uint32_t ctrl;
7919
7920 DEBUGFUNC("e1000_set_pci_express_master_disable");
7921
7922 if (hw->bus_type != e1000_bus_type_pci_express)
7923 return;
7924
7925 ctrl = E1000_READ_REG(hw, CTRL);
7926 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7927 E1000_WRITE_REG(hw, CTRL, ctrl);
7928}
7929
2d7edb92
MC		 7930/*******************************************************************************
7931 *
7932 * Disables PCI-Express master access and verifies there are no pending requests
7933 *
7934 * hw: Struct containing variables accessed by shared code
7935 *
7936 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7937 * caused the master requests to be disabled.
7938 * E1000_SUCCESS master requests disabled.
7939 *
7940 ******************************************************************************/
7941int32_t
7942e1000_disable_pciex_master(struct e1000_hw *hw)
7943{
7944 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7945
7946 DEBUGFUNC("e1000_disable_pciex_master");
7947
7948 if (hw->bus_type != e1000_bus_type_pci_express)
7949 return E1000_SUCCESS;
7950
7951 e1000_set_pci_express_master_disable(hw);
7952
8fc897b0
AK		 7953 while (timeout) {
7954 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
2d7edb92
MC		 7955 break;
7956 else
7957 udelay(100);
7958 timeout--;
7959 }
7960
8fc897b0 7961 if (!timeout) {
2d7edb92
MC		 7962 DEBUGOUT("Master requests are pending.\n");
7963 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7964 }
7965
7966 return E1000_SUCCESS;
7967}
7968
7969/*******************************************************************************
7970 *
7971 * Check for EEPROM Auto Read bit done.
7972 *
7973 * hw: Struct containing variables accessed by shared code
7974 *
7975 * returns: - E1000_ERR_RESET if fail to reset MAC
7976 * E1000_SUCCESS at any other case.
7977 *
7978 ******************************************************************************/
3ad2cc67 7979static int32_t
2d7edb92
MC		 7980e1000_get_auto_rd_done(struct e1000_hw *hw)
7981{
7982 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7983
7984 DEBUGFUNC("e1000_get_auto_rd_done");
7985
7986 switch (hw->mac_type) {
7987 default:
f8ec4733 7988 msleep(5);
2d7edb92 7989 break;
868d5309
MC		 7990 case e1000_82571:
7991 case e1000_82572:
2d7edb92 7992 case e1000_82573:
6418ecc6 7993 case e1000_80003es2lan:
cd94dd0b
AK		 7994 case e1000_ich8lan:
7995 while (timeout) {
7996 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
7997 break;
f8ec4733 7998 else msleep(1);
2d7edb92
MC		 7999 timeout--;
8000 }
8001
8fc897b0 8002 if (!timeout) {
2d7edb92
MC		 8003 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8004 return -E1000_ERR_RESET;
8005 }
8006 break;
8007 }
8008
fd803241
JK		 8009 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8010 * Need to wait for PHY configuration completion before accessing NVM
8011 * and PHY. */
8012 if (hw->mac_type == e1000_82573)
f8ec4733 8013 msleep(25);
fd803241 8014
2d7edb92
MC		 8015 return E1000_SUCCESS;
8016}
8017
8018/***************************************************************************
8019 * Checks if the PHY configuration is done
8020 *
8021 * hw: Struct containing variables accessed by shared code
8022 *
8023 * returns: - E1000_ERR_RESET if fail to reset MAC
8024 * E1000_SUCCESS at any other case.
8025 *
8026 ***************************************************************************/
3ad2cc67 8027static int32_t
2d7edb92
MC		 8028e1000_get_phy_cfg_done(struct e1000_hw *hw)
8029{
868d5309
MC		 8030 int32_t timeout = PHY_CFG_TIMEOUT;
8031 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8032
2d7edb92
MC		 8033 DEBUGFUNC("e1000_get_phy_cfg_done");
8034
868d5309
MC		 8035 switch (hw->mac_type) {
8036 default:
f8ec4733 8037 mdelay(10);
868d5309 8038 break;
6418ecc6
JK		 8039 case e1000_80003es2lan:
8040 /* Separate *_CFG_DONE_* bit for each port */
8041 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8042 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8043 /* Fall Through */
868d5309
MC		 8044 case e1000_82571:
8045 case e1000_82572:
8046 while (timeout) {
8047 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8048 break;
8049 else
f8ec4733 8050 msleep(1);
868d5309
MC		 8051 timeout--;
8052 }
868d5309
MC		 8053 if (!timeout) {
8054 DEBUGOUT("MNG configuration cycle has not completed.\n");
8055 return -E1000_ERR_RESET;
8056 }
8057 break;
8058 }
2d7edb92
MC		 8059
8060 return E1000_SUCCESS;
8061}
8062
8063/***************************************************************************
8064 *
8065 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8066 * adapter or Eeprom access.
8067 *
8068 * hw: Struct containing variables accessed by shared code
8069 *
8070 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8071 * E1000_SUCCESS at any other case.
8072 *
8073 ***************************************************************************/
3ad2cc67 8074static int32_t
2d7edb92
MC		 8075e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8076{
8077 int32_t timeout;
8078 uint32_t swsm;
8079
8080 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8081
8fc897b0 8082 if (!hw->eeprom_semaphore_present)
2d7edb92
MC		 8083 return E1000_SUCCESS;
8084
6418ecc6
JK		 8085 if (hw->mac_type == e1000_80003es2lan) {
8086 /* Get the SW semaphore. */
8087 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8088 return -E1000_ERR_EEPROM;
8089 }
2d7edb92
MC		 8090
8091 /* Get the FW semaphore. */
8092 timeout = hw->eeprom.word_size + 1;
8fc897b0 8093 while (timeout) {
2d7edb92
MC		 8094 swsm = E1000_READ_REG(hw, SWSM);
8095 swsm |= E1000_SWSM_SWESMBI;
8096 E1000_WRITE_REG(hw, SWSM, swsm);
8097 /* if we managed to set the bit we got the semaphore. */
8098 swsm = E1000_READ_REG(hw, SWSM);
8fc897b0 8099 if (swsm & E1000_SWSM_SWESMBI)
2d7edb92
MC		 8100 break;
8101
8102 udelay(50);
8103 timeout--;
8104 }
8105
8fc897b0 8106 if (!timeout) {
2d7edb92
MC		 8107 /* Release semaphores */
8108 e1000_put_hw_eeprom_semaphore(hw);
8109 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8110 return -E1000_ERR_EEPROM;
8111 }
8112
8113 return E1000_SUCCESS;
8114}
8115
8116/***************************************************************************
8117 * This function clears HW semaphore bits.
8118 *
8119 * hw: Struct containing variables accessed by shared code
8120 *
8121 * returns: - None.
8122 *
8123 ***************************************************************************/
3ad2cc67 8124static void
2d7edb92
MC		 8125e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8126{
8127 uint32_t swsm;
8128
8129 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8130
8fc897b0 8131 if (!hw->eeprom_semaphore_present)
2d7edb92
MC		 8132 return;
8133
8134 swsm = E1000_READ_REG(hw, SWSM);
6418ecc6
JK		 8135 if (hw->mac_type == e1000_80003es2lan) {
8136 /* Release both semaphores. */
8137 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8138 } else
868d5309 8139 swsm &= ~(E1000_SWSM_SWESMBI);
2d7edb92
MC		 8140 E1000_WRITE_REG(hw, SWSM, swsm);
8141}
8142
6418ecc6
JK		 8143/***************************************************************************
8144 *
8145 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8146 *
8147 * hw: Struct containing variables accessed by shared code
8148 *
8149 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8150 * E1000_SUCCESS at any other case.
8151 *
8152 ***************************************************************************/
e4c780b1 8153static int32_t
6418ecc6
JK		 8154e1000_get_software_semaphore(struct e1000_hw *hw)
8155{
8156 int32_t timeout = hw->eeprom.word_size + 1;
8157 uint32_t swsm;
8158
8159 DEBUGFUNC("e1000_get_software_semaphore");
8160
35574764 8161 if (hw->mac_type != e1000_80003es2lan) {
6418ecc6 8162 return E1000_SUCCESS;
35574764 8163 }
6418ecc6 8164
8fc897b0 8165 while (timeout) {
6418ecc6
JK		 8166 swsm = E1000_READ_REG(hw, SWSM);
8167 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8fc897b0 8168 if (!(swsm & E1000_SWSM_SMBI))
6418ecc6 8169 break;
f8ec4733 8170 mdelay(1);
6418ecc6
JK		 8171 timeout--;
8172 }
8173
8fc897b0 8174 if (!timeout) {
6418ecc6
JK		 8175 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8176 return -E1000_ERR_RESET;
8177 }
8178
8179 return E1000_SUCCESS;
8180}
8181
8182/***************************************************************************
8183 *
8184 * Release semaphore bit (SMBI).
8185 *
8186 * hw: Struct containing variables accessed by shared code
8187 *
8188 ***************************************************************************/
e4c780b1 8189static void
6418ecc6
JK		 8190e1000_release_software_semaphore(struct e1000_hw *hw)
8191{
8192 uint32_t swsm;
8193
8194 DEBUGFUNC("e1000_release_software_semaphore");
8195
35574764 8196 if (hw->mac_type != e1000_80003es2lan) {
6418ecc6 8197 return;
35574764 8198 }
6418ecc6
JK		 8199
8200 swsm = E1000_READ_REG(hw, SWSM);
8201 /* Release the SW semaphores.*/
8202 swsm &= ~E1000_SWSM_SMBI;
8203 E1000_WRITE_REG(hw, SWSM, swsm);
8204}
8205
2d7edb92
MC		 8206/******************************************************************************
8207 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8208 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8209 * the caller to figure out how to deal with it.
8210 *
8211 * hw - Struct containing variables accessed by shared code
8212 *
8213 * returns: - E1000_BLK_PHY_RESET
8214 * E1000_SUCCESS
8215 *
8216 *****************************************************************************/
8217int32_t
8218e1000_check_phy_reset_block(struct e1000_hw *hw)
8219{
8220 uint32_t manc = 0;
cd94dd0b
AK		 8221 uint32_t fwsm = 0;
8222
8223 if (hw->mac_type == e1000_ich8lan) {
8224 fwsm = E1000_READ_REG(hw, FWSM);
8225 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8226 : E1000_BLK_PHY_RESET;
8227 }
96838a40
JB		 8228
8229 if (hw->mac_type > e1000_82547_rev_2)
2d7edb92
MC		 8230 manc = E1000_READ_REG(hw, MANC);
8231 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
35574764 8232 E1000_BLK_PHY_RESET : E1000_SUCCESS;
2d7edb92
MC		 8233}
8234
3ad2cc67 8235static uint8_t
2d7edb92
MC		 8236e1000_arc_subsystem_valid(struct e1000_hw *hw)
8237{
8238 uint32_t fwsm;
8239
8240 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8241 * may not be provided a DMA clock when no manageability features are
8242 * enabled. We do not want to perform any reads/writes to these registers
8243 * if this is the case. We read FWSM to determine the manageability mode.
8244 */
8245 switch (hw->mac_type) {
868d5309
MC		 8246 case e1000_82571:
8247 case e1000_82572:
2d7edb92 8248 case e1000_82573:
6418ecc6 8249 case e1000_80003es2lan:
2d7edb92 8250 fwsm = E1000_READ_REG(hw, FWSM);
8fc897b0 8251 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
2d7edb92
MC		 8252 return TRUE;
8253 break;
cd94dd0b
AK		 8254 case e1000_ich8lan:
8255 return TRUE;
2d7edb92
MC		 8256 default:
8257 break;
8258 }
8259 return FALSE;
8260}
8261
8262
d37ea5d5
AK		 8263/******************************************************************************
8264 * Configure PCI-Ex no-snoop
8265 *
8266 * hw - Struct containing variables accessed by shared code.
8267 * no_snoop - Bitmap of no-snoop events.
8268 *
8269 * returns: E1000_SUCCESS
8270 *
8271 *****************************************************************************/
e4c780b1 8272static int32_t
d37ea5d5
AK		 8273e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8274{
8275 uint32_t gcr_reg = 0;
8276
8277 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8278
8279 if (hw->bus_type == e1000_bus_type_unknown)
8280 e1000_get_bus_info(hw);
8281
8282 if (hw->bus_type != e1000_bus_type_pci_express)
8283 return E1000_SUCCESS;
8284
8285 if (no_snoop) {
8286 gcr_reg = E1000_READ_REG(hw, GCR);
8287 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8288 gcr_reg |= no_snoop;
8289 E1000_WRITE_REG(hw, GCR, gcr_reg);
8290 }
8291 if (hw->mac_type == e1000_ich8lan) {
8292 uint32_t ctrl_ext;
8293
8294 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8295
8296 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8297 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8298 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8299 }
8300
8301 return E1000_SUCCESS;
8302}
8303
8304/***************************************************************************
8305 *
8306 * Get software semaphore FLAG bit (SWFLAG).
8307 * SWFLAG is used to synchronize the access to all shared resource between
8308 * SW, FW and HW.
8309 *
8310 * hw: Struct containing variables accessed by shared code
8311 *
8312 ***************************************************************************/
e4c780b1 8313static int32_t
d37ea5d5
AK		 8314e1000_get_software_flag(struct e1000_hw *hw)
8315{
8316 int32_t timeout = PHY_CFG_TIMEOUT;
8317 uint32_t extcnf_ctrl;
8318
8319 DEBUGFUNC("e1000_get_software_flag");
8320
8321 if (hw->mac_type == e1000_ich8lan) {
8322 while (timeout) {
8323 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8324 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8325 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8326
8327 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8328 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8329 break;
f8ec4733 8330 mdelay(1);
d37ea5d5
AK		 8331 timeout--;
8332 }
8333
8334 if (!timeout) {
8335 DEBUGOUT("FW or HW locks the resource too long.\n");
8336 return -E1000_ERR_CONFIG;
8337 }
8338 }
8339
8340 return E1000_SUCCESS;
8341}
8342
8343/***************************************************************************
8344 *
8345 * Release software semaphore FLAG bit (SWFLAG).
8346 * SWFLAG is used to synchronize the access to all shared resource between
8347 * SW, FW and HW.
8348 *
8349 * hw: Struct containing variables accessed by shared code
8350 *
8351 ***************************************************************************/
e4c780b1 8352static void
d37ea5d5
AK		 8353e1000_release_software_flag(struct e1000_hw *hw)
8354{
8355 uint32_t extcnf_ctrl;
8356
8357 DEBUGFUNC("e1000_release_software_flag");
8358
8359 if (hw->mac_type == e1000_ich8lan) {
8360 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8361 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8362 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8363 }
8364
8365 return;
8366}
8367
d37ea5d5
AK		 8368/******************************************************************************
8369 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8370 * register.
8371 *
8372 * hw - Struct containing variables accessed by shared code
8373 * offset - offset of word in the EEPROM to read
8374 * data - word read from the EEPROM
8375 * words - number of words to read
8376 *****************************************************************************/
e4c780b1 8377static int32_t
d37ea5d5
AK		 8378e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8379 uint16_t *data)
8380{
8381 int32_t error = E1000_SUCCESS;
8382 uint32_t flash_bank = 0;
8383 uint32_t act_offset = 0;
8384 uint32_t bank_offset = 0;
8385 uint16_t word = 0;
8386 uint16_t i = 0;
8387
8388 /* We need to know which is the valid flash bank. In the event
8389 * that we didn't allocate eeprom_shadow_ram, we may not be
8390 * managing flash_bank. So it cannot be trusted and needs
8391 * to be updated with each read.
8392 */
8393 /* Value of bit 22 corresponds to the flash bank we're on. */
8394 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8395
8396 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8397 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8398
8399 error = e1000_get_software_flag(hw);
8400 if (error != E1000_SUCCESS)
8401 return error;
8402
8403 for (i = 0; i < words; i++) {
8404 if (hw->eeprom_shadow_ram != NULL &&
8405 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8406 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8407 } else {
8408 /* The NVM part needs a byte offset, hence * 2 */
8409 act_offset = bank_offset + ((offset + i) * 2);
8410 error = e1000_read_ich8_word(hw, act_offset, &word);
8411 if (error != E1000_SUCCESS)
8412 break;
8413 data[i] = word;
8414 }
8415 }
8416
8417 e1000_release_software_flag(hw);
8418
8419 return error;
8420}
8421
8422/******************************************************************************
8423 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8424 * register. Actually, writes are written to the shadow ram cache in the hw
8425 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8426 * the NVM, which occurs when the NVM checksum is updated.
8427 *
8428 * hw - Struct containing variables accessed by shared code
8429 * offset - offset of word in the EEPROM to write
8430 * words - number of words to write
8431 * data - words to write to the EEPROM
8432 *****************************************************************************/
e4c780b1 8433static int32_t
d37ea5d5
AK		 8434e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8435 uint16_t *data)
8436{
8437 uint32_t i = 0;
8438 int32_t error = E1000_SUCCESS;
8439
8440 error = e1000_get_software_flag(hw);
8441 if (error != E1000_SUCCESS)
8442 return error;
8443
8444 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8445 * allocated. Subsequent reads to the modified words are read from
8446 * this cached structure as well. Writes will only go into this
8447 * cached structure unless it's followed by a call to
8448 * e1000_update_eeprom_checksum() where it will commit the changes
8449 * and clear the "modified" field.
8450 */
8451 if (hw->eeprom_shadow_ram != NULL) {
8452 for (i = 0; i < words; i++) {
8453 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8454 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8455 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8456 } else {
8457 error = -E1000_ERR_EEPROM;
8458 break;
8459 }
8460 }
8461 } else {
8462 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8463 * as they don't perform any NVM writes. An attempt in doing so
8464 * will result in this error.
8465 */
8466 error = -E1000_ERR_EEPROM;
8467 }
8468
8469 e1000_release_software_flag(hw);
8470
8471 return error;
8472}
8473
8474/******************************************************************************
8475 * This function does initial flash setup so that a new read/write/erase cycle
8476 * can be started.
8477 *
8478 * hw - The pointer to the hw structure
8479 ****************************************************************************/
e4c780b1 8480static int32_t
d37ea5d5
AK		 8481e1000_ich8_cycle_init(struct e1000_hw *hw)
8482{
8483 union ich8_hws_flash_status hsfsts;
8484 int32_t error = E1000_ERR_EEPROM;
8485 int32_t i = 0;
8486
8487 DEBUGFUNC("e1000_ich8_cycle_init");
8488
8489 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8490
8491 /* May be check the Flash Des Valid bit in Hw status */
8492 if (hsfsts.hsf_status.fldesvalid == 0) {
8493 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8494 return error;
8495 }
8496
8497 /* Clear FCERR in Hw status by writing 1 */
8498 /* Clear DAEL in Hw status by writing a 1 */
8499 hsfsts.hsf_status.flcerr = 1;
8500 hsfsts.hsf_status.dael = 1;
8501
8502 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8503
8504 /* Either we should have a hardware SPI cycle in progress bit to check
8505 * against, in order to start a new cycle or FDONE bit should be changed
8506 * in the hardware so that it is 1 after harware reset, which can then be
8507 * used as an indication whether a cycle is in progress or has been
8508 * completed .. we should also have some software semaphore mechanism to
8509 * guard FDONE or the cycle in progress bit so that two threads access to
8510 * those bits can be sequentiallized or a way so that 2 threads dont
8511 * start the cycle at the same time */
8512
8513 if (hsfsts.hsf_status.flcinprog == 0) {
8514 /* There is no cycle running at present, so we can start a cycle */
8515 /* Begin by setting Flash Cycle Done. */
8516 hsfsts.hsf_status.flcdone = 1;
8517 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8518 error = E1000_SUCCESS;
8519 } else {
8520 /* otherwise poll for sometime so the current cycle has a chance
8521 * to end before giving up. */
8522 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8523 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8524 if (hsfsts.hsf_status.flcinprog == 0) {
8525 error = E1000_SUCCESS;
8526 break;
8527 }
8528 udelay(1);
8529 }
8530 if (error == E1000_SUCCESS) {
8531 /* Successful in waiting for previous cycle to timeout,
8532 * now set the Flash Cycle Done. */
8533 hsfsts.hsf_status.flcdone = 1;
8534 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8535 } else {
8536 DEBUGOUT("Flash controller busy, cannot get access");
8537 }
8538 }
8539 return error;
8540}
8541
8542/******************************************************************************
8543 * This function starts a flash cycle and waits for its completion
8544 *
8545 * hw - The pointer to the hw structure
8546 ****************************************************************************/
e4c780b1 8547static int32_t
d37ea5d5
AK		 8548e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8549{
8550 union ich8_hws_flash_ctrl hsflctl;
8551 union ich8_hws_flash_status hsfsts;
8552 int32_t error = E1000_ERR_EEPROM;
8553 uint32_t i = 0;
8554
8555 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8556 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8557 hsflctl.hsf_ctrl.flcgo = 1;
8558 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8559
8560 /* wait till FDONE bit is set to 1 */
8561 do {
8562 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8563 if (hsfsts.hsf_status.flcdone == 1)
8564 break;
8565 udelay(1);
8566 i++;
8567 } while (i < timeout);
8568 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8569 error = E1000_SUCCESS;
8570 }
8571 return error;
8572}
8573
8574/******************************************************************************
8575 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8576 *
8577 * hw - The pointer to the hw structure
8578 * index - The index of the byte or word to read.
8579 * size - Size of data to read, 1=byte 2=word
8580 * data - Pointer to the word to store the value read.
8581 *****************************************************************************/
e4c780b1 8582static int32_t
d37ea5d5
AK		 8583e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8584 uint32_t size, uint16_t* data)
8585{
8586 union ich8_hws_flash_status hsfsts;
8587 union ich8_hws_flash_ctrl hsflctl;
8588 uint32_t flash_linear_address;
8589 uint32_t flash_data = 0;
8590 int32_t error = -E1000_ERR_EEPROM;
8591 int32_t count = 0;
8592
8593 DEBUGFUNC("e1000_read_ich8_data");
8594
8595 if (size < 1 || size > 2 || data == 0x0 ||
8596 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8597 return error;
8598
8599 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8600 hw->flash_base_addr;
8601
8602 do {
8603 udelay(1);
8604 /* Steps */
8605 error = e1000_ich8_cycle_init(hw);
8606 if (error != E1000_SUCCESS)
8607 break;
8608
8609 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8610 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8611 hsflctl.hsf_ctrl.fldbcount = size - 1;
8612 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8613 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8614
8615 /* Write the last 24 bits of index into Flash Linear address field in
8616 * Flash Address */
8617 /* TODO: TBD maybe check the index against the size of flash */
8618
8619 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8620
8621 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8622
8623 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8624 * sequence a few more times, else read in (shift in) the Flash Data0,
8625 * the order is least significant byte first msb to lsb */
8626 if (error == E1000_SUCCESS) {
8627 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8628 if (size == 1) {
8629 *data = (uint8_t)(flash_data & 0x000000FF);
8630 } else if (size == 2) {
8631 *data = (uint16_t)(flash_data & 0x0000FFFF);
8632 }
8633 break;
8634 } else {
8635 /* If we've gotten here, then things are probably completely hosed,
8636 * but if the error condition is detected, it won't hurt to give
8637 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8638 */
8639 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8640 if (hsfsts.hsf_status.flcerr == 1) {
8641 /* Repeat for some time before giving up. */
8642 continue;
8643 } else if (hsfsts.hsf_status.flcdone == 0) {
8644 DEBUGOUT("Timeout error - flash cycle did not complete.");
8645 break;
8646 }
8647 }
8648 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8649
8650 return error;
8651}
8652
8653/******************************************************************************
8654 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8655 *
8656 * hw - The pointer to the hw structure
8657 * index - The index of the byte/word to read.
8658 * size - Size of data to read, 1=byte 2=word
8659 * data - The byte(s) to write to the NVM.
8660 *****************************************************************************/
e4c780b1 8661static int32_t
d37ea5d5
AK		 8662e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8663 uint16_t data)
8664{
8665 union ich8_hws_flash_status hsfsts;
8666 union ich8_hws_flash_ctrl hsflctl;
8667 uint32_t flash_linear_address;
8668 uint32_t flash_data = 0;
8669 int32_t error = -E1000_ERR_EEPROM;
8670 int32_t count = 0;
8671
8672 DEBUGFUNC("e1000_write_ich8_data");
8673
8674 if (size < 1 || size > 2 || data > size * 0xff ||
8675 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8676 return error;
8677
8678 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8679 hw->flash_base_addr;
8680
8681 do {
8682 udelay(1);
8683 /* Steps */
8684 error = e1000_ich8_cycle_init(hw);
8685 if (error != E1000_SUCCESS)
8686 break;
8687
8688 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8689 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8690 hsflctl.hsf_ctrl.fldbcount = size -1;
8691 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8692 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8693
8694 /* Write the last 24 bits of index into Flash Linear address field in
8695 * Flash Address */
8696 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8697
8698 if (size == 1)
8699 flash_data = (uint32_t)data & 0x00FF;
8700 else
8701 flash_data = (uint32_t)data;
8702
8703 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8704
8705 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8706 * sequence a few more times else done */
8707 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8708 if (error == E1000_SUCCESS) {
8709 break;
8710 } else {
8711 /* If we're here, then things are most likely completely hosed,
8712 * but if the error condition is detected, it won't hurt to give
8713 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8714 */
8715 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8716 if (hsfsts.hsf_status.flcerr == 1) {
8717 /* Repeat for some time before giving up. */
8718 continue;
8719 } else if (hsfsts.hsf_status.flcdone == 0) {
8720 DEBUGOUT("Timeout error - flash cycle did not complete.");
8721 break;
8722 }
8723 }
8724 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8725
8726 return error;
8727}
8728
8729/******************************************************************************
8730 * Reads a single byte from the NVM using the ICH8 flash access registers.
8731 *
8732 * hw - pointer to e1000_hw structure
8733 * index - The index of the byte to read.
8734 * data - Pointer to a byte to store the value read.
8735 *****************************************************************************/
e4c780b1 8736static int32_t
d37ea5d5
AK		 8737e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8738{
8739 int32_t status = E1000_SUCCESS;
8740 uint16_t word = 0;
8741
8742 status = e1000_read_ich8_data(hw, index, 1, &word);
8743 if (status == E1000_SUCCESS) {
8744 *data = (uint8_t)word;
8745 }
8746
8747 return status;
8748}
8749
8750/******************************************************************************
8751 * Writes a single byte to the NVM using the ICH8 flash access registers.
8752 * Performs verification by reading back the value and then going through
8753 * a retry algorithm before giving up.
8754 *
8755 * hw - pointer to e1000_hw structure
8756 * index - The index of the byte to write.
8757 * byte - The byte to write to the NVM.
8758 *****************************************************************************/
e4c780b1 8759static int32_t
d37ea5d5
AK		 8760e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8761{
8762 int32_t error = E1000_SUCCESS;
2a88c173 8763 int32_t program_retries = 0;
d37ea5d5 8764
2a88c173 8765 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
d37ea5d5 8766
2a88c173
JK		 8767 error = e1000_write_ich8_byte(hw, index, byte);
8768
8769 if (error != E1000_SUCCESS) {
8770 for (program_retries = 0; program_retries < 100; program_retries++) {
8771 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8772 error = e1000_write_ich8_byte(hw, index, byte);
8773 udelay(100);
8774 if (error == E1000_SUCCESS)
8775 break;
8776 }
d37ea5d5 8777 }
2a88c173 8778
d37ea5d5
AK		 8779 if (program_retries == 100)
8780 error = E1000_ERR_EEPROM;
8781
8782 return error;
8783}
8784
8785/******************************************************************************
8786 * Writes a single byte to the NVM using the ICH8 flash access registers.
8787 *
8788 * hw - pointer to e1000_hw structure
8789 * index - The index of the byte to read.
8790 * data - The byte to write to the NVM.
8791 *****************************************************************************/
e4c780b1 8792static int32_t
d37ea5d5
AK		 8793e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8794{
8795 int32_t status = E1000_SUCCESS;
8796 uint16_t word = (uint16_t)data;
8797
8798 status = e1000_write_ich8_data(hw, index, 1, word);
8799
8800 return status;
8801}
8802
8803/******************************************************************************
8804 * Reads a word from the NVM using the ICH8 flash access registers.
8805 *
8806 * hw - pointer to e1000_hw structure
8807 * index - The starting byte index of the word to read.
8808 * data - Pointer to a word to store the value read.
8809 *****************************************************************************/
e4c780b1 8810static int32_t
d37ea5d5
AK		 8811e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8812{
8813 int32_t status = E1000_SUCCESS;
8814 status = e1000_read_ich8_data(hw, index, 2, data);
8815 return status;
8816}
8817
8818/******************************************************************************
2a88c173
JK		 8819 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8820 * based.
d37ea5d5
AK		 8821 *
8822 * hw - pointer to e1000_hw structure
2a88c173 8823 * bank - 0 for first bank, 1 for second bank
d37ea5d5 8824 *
2a88c173
JK		 8825 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8826 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8827 * bank size may be 4, 8 or 64 KBytes
d37ea5d5 8828 *****************************************************************************/
2a88c173
JK		 8829int32_t
8830e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
d37ea5d5
AK		 8831{
8832 union ich8_hws_flash_status hsfsts;
8833 union ich8_hws_flash_ctrl hsflctl;
8834 uint32_t flash_linear_address;
8835 int32_t count = 0;
8836 int32_t error = E1000_ERR_EEPROM;
2a88c173
JK		 8837 int32_t iteration;
8838 int32_t sub_sector_size = 0;
8839 int32_t bank_size;
d37ea5d5
AK		 8840 int32_t j = 0;
8841 int32_t error_flag = 0;
8842
8843 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8844
8845 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8846 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8847 * consecutive sectors. The start index for the nth Hw sector can be
2a88c173 8848 * calculated as bank * 4096 + n * 256
d37ea5d5
AK		 8849 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8850 * The start index for the nth Hw sector can be calculated
2a88c173
JK		 8851 * as bank * 4096
8852 * 10: The HW sector is 8K bytes
8853 * 11: The Hw sector size is 64K bytes */
d37ea5d5
AK		 8854 if (hsfsts.hsf_status.berasesz == 0x0) {
8855 /* Hw sector size 256 */
2a88c173
JK		 8856 sub_sector_size = ICH8_FLASH_SEG_SIZE_256;
8857 bank_size = ICH8_FLASH_SECTOR_SIZE;
d37ea5d5
AK		 8858 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8859 } else if (hsfsts.hsf_status.berasesz == 0x1) {
2a88c173
JK		 8860 bank_size = ICH8_FLASH_SEG_SIZE_4K;
8861 iteration = 1;
8862 } else if (hw->mac_type != e1000_ich8lan &&
8863 hsfsts.hsf_status.berasesz == 0x2) {
8864 /* 8K erase size invalid for ICH8 - added in for ICH9 */
8865 bank_size = ICH9_FLASH_SEG_SIZE_8K;
d37ea5d5
AK		 8866 iteration = 1;
8867 } else if (hsfsts.hsf_status.berasesz == 0x3) {
2a88c173 8868 bank_size = ICH8_FLASH_SEG_SIZE_64K;
d37ea5d5
AK		 8869 iteration = 1;
8870 } else {
8871 return error;
8872 }
8873
8874 for (j = 0; j < iteration ; j++) {
8875 do {
8876 count++;
8877 /* Steps */
8878 error = e1000_ich8_cycle_init(hw);
8879 if (error != E1000_SUCCESS) {
8880 error_flag = 1;
8881 break;
8882 }
8883
8884 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8885 * Control */
8886 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8887 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8888 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8889
8890 /* Write the last 24 bits of an index within the block into Flash
8891 * Linear address field in Flash Address. This probably needs to
2a88c173
JK		 8892 * be calculated here based off the on-chip erase sector size and
8893 * the software bank size (4, 8 or 64 KBytes) */
8894 flash_linear_address = bank * bank_size + j * sub_sector_size;
d37ea5d5 8895 flash_linear_address += hw->flash_base_addr;
2a88c173 8896 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
d37ea5d5
AK		 8897
8898 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8899
2a88c173 8900 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_ERASE_TIMEOUT);
d37ea5d5
AK		 8901 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8902 * sequence a few more times else Done */
8903 if (error == E1000_SUCCESS) {
8904 break;
8905 } else {
8906 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8907 if (hsfsts.hsf_status.flcerr == 1) {
8908 /* repeat for some time before giving up */
8909 continue;
8910 } else if (hsfsts.hsf_status.flcdone == 0) {
8911 error_flag = 1;
8912 break;
8913 }
8914 }
8915 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8916 if (error_flag == 1)
8917 break;
8918 }
8919 if (error_flag != 1)
8920 error = E1000_SUCCESS;
8921 return error;
8922}
8923
e4c780b1 8924static int32_t
d37ea5d5
AK		 8925e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8926 uint32_t cnf_base_addr, uint32_t cnf_size)
8927{
8928 uint32_t ret_val = E1000_SUCCESS;
8929 uint16_t word_addr, reg_data, reg_addr;
8930 uint16_t i;
8931
8932 /* cnf_base_addr is in DWORD */
8933 word_addr = (uint16_t)(cnf_base_addr << 1);
8934
8935 /* cnf_size is returned in size of dwords */
8936 for (i = 0; i < cnf_size; i++) {
8937 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
8938 if (ret_val)
8939 return ret_val;
8940
8941 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
8942 if (ret_val)
8943 return ret_val;
8944
8945 ret_val = e1000_get_software_flag(hw);
8946 if (ret_val != E1000_SUCCESS)
8947 return ret_val;
8948
8949 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
8950
8951 e1000_release_software_flag(hw);
8952 }
8953
8954 return ret_val;
8955}
8956
8957
2a88c173
JK		 8958/******************************************************************************
8959 * This function initializes the PHY from the NVM on ICH8 platforms. This
8960 * is needed due to an issue where the NVM configuration is not properly
8961 * autoloaded after power transitions. Therefore, after each PHY reset, we
8962 * will load the configuration data out of the NVM manually.
8963 *
8964 * hw: Struct containing variables accessed by shared code
8965 *****************************************************************************/
e4c780b1 8966static int32_t
d37ea5d5
AK		 8967e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8968{
8969 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8970
8971 if (hw->phy_type != e1000_phy_igp_3)
8972 return E1000_SUCCESS;
8973
8974 /* Check if SW needs configure the PHY */
8975 reg_data = E1000_READ_REG(hw, FEXTNVM);
8976 if (!(reg_data & FEXTNVM_SW_CONFIG))
8977 return E1000_SUCCESS;
8978
8979 /* Wait for basic configuration completes before proceeding*/
8980 loop = 0;
8981 do {
8982 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
8983 udelay(100);
8984 loop++;
8985 } while ((!reg_data) && (loop < 50));
8986
8987 /* Clear the Init Done bit for the next init event */
8988 reg_data = E1000_READ_REG(hw, STATUS);
8989 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8990 E1000_WRITE_REG(hw, STATUS, reg_data);
8991
8992 /* Make sure HW does not configure LCD from PHY extended configuration
8993 before SW configuration */
8994 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
8995 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
8996 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
8997 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
8998 cnf_size >>= 16;
8999 if (cnf_size) {
9000 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9001 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9002 /* cnf_base_addr is in DWORD */
9003 cnf_base_addr >>= 16;
9004
9005 /* Configure LCD from extended configuration region. */
9006 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9007 cnf_size);
9008 if (ret_val)
9009 return ret_val;
9010 }
9011 }
9012
9013 return E1000_SUCCESS;
9014}
9015
9016
2d7edb92 9017
Linux 6.x block layer and io_uring tree(s)