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1da177e4 LT |
1 | /******************************************************************************* |
2 | ||
3 | ||
3d41e30a | 4 | Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved. |
1da177e4 LT |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms of the GNU General Public License as published by the Free | |
8 | Software Foundation; either version 2 of the License, or (at your option) | |
9 | any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., 59 | |
18 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in the | |
21 | file called LICENSE. | |
22 | ||
23 | Contact Information: | |
24 | Linux NICS <linux.nics@intel.com> | |
3d41e30a | 25 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
1da177e4 LT |
26 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | ||
28 | *******************************************************************************/ | |
29 | ||
30 | /* e1000_hw.c | |
31 | * Shared functions for accessing and configuring the MAC | |
32 | */ | |
33 | ||
34 | #include "e1000_hw.h" | |
35 | ||
36 | static int32_t e1000_set_phy_type(struct e1000_hw *hw); | |
37 | static void e1000_phy_init_script(struct e1000_hw *hw); | |
38 | static int32_t e1000_setup_copper_link(struct e1000_hw *hw); | |
39 | static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); | |
40 | static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); | |
41 | static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); | |
42 | static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); | |
43 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); | |
44 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); | |
45 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, | |
46 | uint16_t count); | |
47 | static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); | |
48 | static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); | |
49 | static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, | |
50 | uint16_t words, uint16_t *data); | |
51 | static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, | |
52 | uint16_t offset, uint16_t words, | |
53 | uint16_t *data); | |
54 | static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); | |
55 | static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); | |
56 | static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); | |
57 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, | |
58 | uint16_t count); | |
59 | static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, | |
60 | uint16_t phy_data); | |
61 | static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, | |
62 | uint16_t *phy_data); | |
63 | static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); | |
64 | static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); | |
65 | static void e1000_release_eeprom(struct e1000_hw *hw); | |
66 | static void e1000_standby_eeprom(struct e1000_hw *hw); | |
1da177e4 LT |
67 | static int32_t e1000_set_vco_speed(struct e1000_hw *hw); |
68 | static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); | |
69 | static int32_t e1000_set_phy_mode(struct e1000_hw *hw); | |
2d7edb92 MC |
70 | static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); |
71 | static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); | |
3ad2cc67 AB |
72 | static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); |
73 | static int32_t e1000_check_downshift(struct e1000_hw *hw); | |
74 | static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity); | |
75 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw); | |
76 | static void e1000_clear_vfta(struct e1000_hw *hw); | |
77 | static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); | |
78 | static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |
79 | boolean_t link_up); | |
80 | static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); | |
81 | static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); | |
82 | static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); | |
83 | static int32_t e1000_get_cable_length(struct e1000_hw *hw, | |
84 | uint16_t *min_length, | |
85 | uint16_t *max_length); | |
86 | static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); | |
87 | static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); | |
88 | static int32_t e1000_id_led_init(struct e1000_hw * hw); | |
89 | static void e1000_init_rx_addrs(struct e1000_hw *hw); | |
90 | static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); | |
91 | static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); | |
92 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); | |
93 | static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, | |
94 | uint16_t words, uint16_t *data); | |
95 | static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); | |
96 | static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); | |
97 | static int32_t e1000_wait_autoneg(struct e1000_hw *hw); | |
98 | ||
99 | static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, | |
100 | uint32_t value); | |
101 | ||
102 | #define E1000_WRITE_REG_IO(a, reg, val) \ | |
103 | e1000_write_reg_io((a), E1000_##reg, val) | |
6418ecc6 JK |
104 | static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw); |
105 | static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); | |
1da177e4 LT |
106 | |
107 | /* IGP cable length table */ | |
108 | static const | |
109 | uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = | |
110 | { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, | |
111 | 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, | |
112 | 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, | |
113 | 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, | |
114 | 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, | |
115 | 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, | |
116 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, | |
117 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; | |
118 | ||
2d7edb92 MC |
119 | static const |
120 | uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = | |
868d5309 MC |
121 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
122 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, | |
123 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, | |
124 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, | |
125 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, | |
126 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, | |
127 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, | |
128 | 104, 109, 114, 118, 121, 124}; | |
2d7edb92 | 129 | |
1da177e4 LT |
130 | |
131 | /****************************************************************************** | |
132 | * Set the phy type member in the hw struct. | |
133 | * | |
134 | * hw - Struct containing variables accessed by shared code | |
135 | *****************************************************************************/ | |
136 | int32_t | |
137 | e1000_set_phy_type(struct e1000_hw *hw) | |
138 | { | |
139 | DEBUGFUNC("e1000_set_phy_type"); | |
140 | ||
2d7edb92 MC |
141 | if(hw->mac_type == e1000_undefined) |
142 | return -E1000_ERR_PHY_TYPE; | |
143 | ||
1da177e4 LT |
144 | switch(hw->phy_id) { |
145 | case M88E1000_E_PHY_ID: | |
146 | case M88E1000_I_PHY_ID: | |
147 | case M88E1011_I_PHY_ID: | |
2d7edb92 | 148 | case M88E1111_I_PHY_ID: |
1da177e4 LT |
149 | hw->phy_type = e1000_phy_m88; |
150 | break; | |
151 | case IGP01E1000_I_PHY_ID: | |
152 | if(hw->mac_type == e1000_82541 || | |
153 | hw->mac_type == e1000_82541_rev_2 || | |
154 | hw->mac_type == e1000_82547 || | |
155 | hw->mac_type == e1000_82547_rev_2) { | |
156 | hw->phy_type = e1000_phy_igp; | |
157 | break; | |
158 | } | |
6418ecc6 JK |
159 | case GG82563_E_PHY_ID: |
160 | if (hw->mac_type == e1000_80003es2lan) { | |
161 | hw->phy_type = e1000_phy_gg82563; | |
162 | break; | |
163 | } | |
1da177e4 LT |
164 | /* Fall Through */ |
165 | default: | |
166 | /* Should never have loaded on this device */ | |
167 | hw->phy_type = e1000_phy_undefined; | |
168 | return -E1000_ERR_PHY_TYPE; | |
169 | } | |
170 | ||
171 | return E1000_SUCCESS; | |
172 | } | |
173 | ||
174 | /****************************************************************************** | |
175 | * IGP phy init script - initializes the GbE PHY | |
176 | * | |
177 | * hw - Struct containing variables accessed by shared code | |
178 | *****************************************************************************/ | |
179 | static void | |
180 | e1000_phy_init_script(struct e1000_hw *hw) | |
181 | { | |
182 | uint32_t ret_val; | |
183 | uint16_t phy_saved_data; | |
184 | ||
185 | DEBUGFUNC("e1000_phy_init_script"); | |
186 | ||
1da177e4 LT |
187 | if(hw->phy_init_script) { |
188 | msec_delay(20); | |
189 | ||
190 | /* Save off the current value of register 0x2F5B to be restored at | |
191 | * the end of this routine. */ | |
192 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
193 | ||
194 | /* Disabled the PHY transmitter */ | |
195 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
196 | ||
197 | msec_delay(20); | |
198 | ||
199 | e1000_write_phy_reg(hw,0x0000,0x0140); | |
200 | ||
201 | msec_delay(5); | |
202 | ||
203 | switch(hw->mac_type) { | |
204 | case e1000_82541: | |
205 | case e1000_82547: | |
206 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); | |
207 | ||
208 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); | |
209 | ||
210 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); | |
211 | ||
212 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); | |
213 | ||
214 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); | |
215 | ||
216 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); | |
217 | ||
218 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); | |
219 | ||
220 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); | |
221 | ||
222 | e1000_write_phy_reg(hw, 0x2010, 0x0008); | |
223 | break; | |
224 | ||
225 | case e1000_82541_rev_2: | |
226 | case e1000_82547_rev_2: | |
227 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); | |
228 | break; | |
229 | default: | |
230 | break; | |
231 | } | |
232 | ||
233 | e1000_write_phy_reg(hw, 0x0000, 0x3300); | |
234 | ||
235 | msec_delay(20); | |
236 | ||
237 | /* Now enable the transmitter */ | |
238 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
239 | ||
240 | if(hw->mac_type == e1000_82547) { | |
241 | uint16_t fused, fine, coarse; | |
242 | ||
243 | /* Move to analog registers page */ | |
244 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); | |
245 | ||
246 | if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { | |
247 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); | |
248 | ||
249 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; | |
250 | coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; | |
251 | ||
252 | if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { | |
253 | coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; | |
254 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; | |
255 | } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) | |
256 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; | |
257 | ||
258 | fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | | |
259 | (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | | |
260 | (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); | |
261 | ||
262 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); | |
263 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, | |
264 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); | |
265 | } | |
266 | } | |
267 | } | |
268 | } | |
269 | ||
270 | /****************************************************************************** | |
271 | * Set the mac type member in the hw struct. | |
272 | * | |
273 | * hw - Struct containing variables accessed by shared code | |
274 | *****************************************************************************/ | |
275 | int32_t | |
276 | e1000_set_mac_type(struct e1000_hw *hw) | |
277 | { | |
278 | DEBUGFUNC("e1000_set_mac_type"); | |
279 | ||
280 | switch (hw->device_id) { | |
281 | case E1000_DEV_ID_82542: | |
282 | switch (hw->revision_id) { | |
283 | case E1000_82542_2_0_REV_ID: | |
284 | hw->mac_type = e1000_82542_rev2_0; | |
285 | break; | |
286 | case E1000_82542_2_1_REV_ID: | |
287 | hw->mac_type = e1000_82542_rev2_1; | |
288 | break; | |
289 | default: | |
290 | /* Invalid 82542 revision ID */ | |
291 | return -E1000_ERR_MAC_TYPE; | |
292 | } | |
293 | break; | |
294 | case E1000_DEV_ID_82543GC_FIBER: | |
295 | case E1000_DEV_ID_82543GC_COPPER: | |
296 | hw->mac_type = e1000_82543; | |
297 | break; | |
298 | case E1000_DEV_ID_82544EI_COPPER: | |
299 | case E1000_DEV_ID_82544EI_FIBER: | |
300 | case E1000_DEV_ID_82544GC_COPPER: | |
301 | case E1000_DEV_ID_82544GC_LOM: | |
302 | hw->mac_type = e1000_82544; | |
303 | break; | |
304 | case E1000_DEV_ID_82540EM: | |
305 | case E1000_DEV_ID_82540EM_LOM: | |
306 | case E1000_DEV_ID_82540EP: | |
307 | case E1000_DEV_ID_82540EP_LOM: | |
308 | case E1000_DEV_ID_82540EP_LP: | |
309 | hw->mac_type = e1000_82540; | |
310 | break; | |
311 | case E1000_DEV_ID_82545EM_COPPER: | |
312 | case E1000_DEV_ID_82545EM_FIBER: | |
313 | hw->mac_type = e1000_82545; | |
314 | break; | |
315 | case E1000_DEV_ID_82545GM_COPPER: | |
316 | case E1000_DEV_ID_82545GM_FIBER: | |
317 | case E1000_DEV_ID_82545GM_SERDES: | |
318 | hw->mac_type = e1000_82545_rev_3; | |
319 | break; | |
320 | case E1000_DEV_ID_82546EB_COPPER: | |
321 | case E1000_DEV_ID_82546EB_FIBER: | |
322 | case E1000_DEV_ID_82546EB_QUAD_COPPER: | |
323 | hw->mac_type = e1000_82546; | |
324 | break; | |
325 | case E1000_DEV_ID_82546GB_COPPER: | |
326 | case E1000_DEV_ID_82546GB_FIBER: | |
327 | case E1000_DEV_ID_82546GB_SERDES: | |
328 | case E1000_DEV_ID_82546GB_PCIE: | |
b7ee49db JK |
329 | case E1000_DEV_ID_82546GB_QUAD_COPPER: |
330 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: | |
1da177e4 LT |
331 | hw->mac_type = e1000_82546_rev_3; |
332 | break; | |
333 | case E1000_DEV_ID_82541EI: | |
334 | case E1000_DEV_ID_82541EI_MOBILE: | |
335 | hw->mac_type = e1000_82541; | |
336 | break; | |
337 | case E1000_DEV_ID_82541ER: | |
338 | case E1000_DEV_ID_82541GI: | |
339 | case E1000_DEV_ID_82541GI_LF: | |
340 | case E1000_DEV_ID_82541GI_MOBILE: | |
341 | hw->mac_type = e1000_82541_rev_2; | |
342 | break; | |
343 | case E1000_DEV_ID_82547EI: | |
344 | hw->mac_type = e1000_82547; | |
345 | break; | |
346 | case E1000_DEV_ID_82547GI: | |
347 | hw->mac_type = e1000_82547_rev_2; | |
348 | break; | |
868d5309 MC |
349 | case E1000_DEV_ID_82571EB_COPPER: |
350 | case E1000_DEV_ID_82571EB_FIBER: | |
351 | case E1000_DEV_ID_82571EB_SERDES: | |
352 | hw->mac_type = e1000_82571; | |
353 | break; | |
354 | case E1000_DEV_ID_82572EI_COPPER: | |
355 | case E1000_DEV_ID_82572EI_FIBER: | |
356 | case E1000_DEV_ID_82572EI_SERDES: | |
357 | hw->mac_type = e1000_82572; | |
358 | break; | |
2d7edb92 MC |
359 | case E1000_DEV_ID_82573E: |
360 | case E1000_DEV_ID_82573E_IAMT: | |
868d5309 | 361 | case E1000_DEV_ID_82573L: |
2d7edb92 MC |
362 | hw->mac_type = e1000_82573; |
363 | break; | |
6418ecc6 JK |
364 | case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: |
365 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
366 | hw->mac_type = e1000_80003es2lan; | |
367 | break; | |
1da177e4 LT |
368 | default: |
369 | /* Should never have loaded on this device */ | |
370 | return -E1000_ERR_MAC_TYPE; | |
371 | } | |
372 | ||
373 | switch(hw->mac_type) { | |
6418ecc6 JK |
374 | case e1000_80003es2lan: |
375 | hw->swfw_sync_present = TRUE; | |
376 | /* fall through */ | |
868d5309 MC |
377 | case e1000_82571: |
378 | case e1000_82572: | |
2d7edb92 MC |
379 | case e1000_82573: |
380 | hw->eeprom_semaphore_present = TRUE; | |
381 | /* fall through */ | |
1da177e4 LT |
382 | case e1000_82541: |
383 | case e1000_82547: | |
384 | case e1000_82541_rev_2: | |
385 | case e1000_82547_rev_2: | |
386 | hw->asf_firmware_present = TRUE; | |
387 | break; | |
388 | default: | |
389 | break; | |
390 | } | |
391 | ||
392 | return E1000_SUCCESS; | |
393 | } | |
394 | ||
395 | /***************************************************************************** | |
396 | * Set media type and TBI compatibility. | |
397 | * | |
398 | * hw - Struct containing variables accessed by shared code | |
399 | * **************************************************************************/ | |
400 | void | |
401 | e1000_set_media_type(struct e1000_hw *hw) | |
402 | { | |
403 | uint32_t status; | |
404 | ||
405 | DEBUGFUNC("e1000_set_media_type"); | |
406 | ||
407 | if(hw->mac_type != e1000_82543) { | |
408 | /* tbi_compatibility is only valid on 82543 */ | |
409 | hw->tbi_compatibility_en = FALSE; | |
410 | } | |
411 | ||
412 | switch (hw->device_id) { | |
413 | case E1000_DEV_ID_82545GM_SERDES: | |
414 | case E1000_DEV_ID_82546GB_SERDES: | |
868d5309 MC |
415 | case E1000_DEV_ID_82571EB_SERDES: |
416 | case E1000_DEV_ID_82572EI_SERDES: | |
6418ecc6 | 417 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
1da177e4 LT |
418 | hw->media_type = e1000_media_type_internal_serdes; |
419 | break; | |
420 | default: | |
3893d547 MC |
421 | switch (hw->mac_type) { |
422 | case e1000_82542_rev2_0: | |
423 | case e1000_82542_rev2_1: | |
424 | hw->media_type = e1000_media_type_fiber; | |
425 | break; | |
426 | case e1000_82573: | |
427 | /* The STATUS_TBIMODE bit is reserved or reused for the this | |
428 | * device. | |
429 | */ | |
430 | hw->media_type = e1000_media_type_copper; | |
431 | break; | |
432 | default: | |
1da177e4 | 433 | status = E1000_READ_REG(hw, STATUS); |
3893d547 | 434 | if (status & E1000_STATUS_TBIMODE) { |
1da177e4 LT |
435 | hw->media_type = e1000_media_type_fiber; |
436 | /* tbi_compatibility not valid on fiber */ | |
437 | hw->tbi_compatibility_en = FALSE; | |
438 | } else { | |
439 | hw->media_type = e1000_media_type_copper; | |
440 | } | |
3893d547 | 441 | break; |
1da177e4 LT |
442 | } |
443 | } | |
444 | } | |
445 | ||
446 | /****************************************************************************** | |
447 | * Reset the transmit and receive units; mask and clear all interrupts. | |
448 | * | |
449 | * hw - Struct containing variables accessed by shared code | |
450 | *****************************************************************************/ | |
451 | int32_t | |
452 | e1000_reset_hw(struct e1000_hw *hw) | |
453 | { | |
454 | uint32_t ctrl; | |
455 | uint32_t ctrl_ext; | |
456 | uint32_t icr; | |
457 | uint32_t manc; | |
458 | uint32_t led_ctrl; | |
2d7edb92 MC |
459 | uint32_t timeout; |
460 | uint32_t extcnf_ctrl; | |
461 | int32_t ret_val; | |
1da177e4 LT |
462 | |
463 | DEBUGFUNC("e1000_reset_hw"); | |
464 | ||
465 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ | |
466 | if(hw->mac_type == e1000_82542_rev2_0) { | |
467 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); | |
468 | e1000_pci_clear_mwi(hw); | |
469 | } | |
470 | ||
2d7edb92 MC |
471 | if(hw->bus_type == e1000_bus_type_pci_express) { |
472 | /* Prevent the PCI-E bus from sticking if there is no TLP connection | |
473 | * on the last TLP read/write transaction when MAC is reset. | |
474 | */ | |
475 | if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) { | |
476 | DEBUGOUT("PCI-E Master disable polling has failed.\n"); | |
477 | } | |
478 | } | |
479 | ||
1da177e4 LT |
480 | /* Clear interrupt mask to stop board from generating interrupts */ |
481 | DEBUGOUT("Masking off all interrupts\n"); | |
482 | E1000_WRITE_REG(hw, IMC, 0xffffffff); | |
483 | ||
484 | /* Disable the Transmit and Receive units. Then delay to allow | |
485 | * any pending transactions to complete before we hit the MAC with | |
486 | * the global reset. | |
487 | */ | |
488 | E1000_WRITE_REG(hw, RCTL, 0); | |
489 | E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); | |
490 | E1000_WRITE_FLUSH(hw); | |
491 | ||
492 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ | |
493 | hw->tbi_compatibility_on = FALSE; | |
494 | ||
495 | /* Delay to allow any outstanding PCI transactions to complete before | |
496 | * resetting the device | |
497 | */ | |
498 | msec_delay(10); | |
499 | ||
500 | ctrl = E1000_READ_REG(hw, CTRL); | |
501 | ||
502 | /* Must reset the PHY before resetting the MAC */ | |
503 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | |
2d7edb92 | 504 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
1da177e4 LT |
505 | msec_delay(5); |
506 | } | |
507 | ||
2d7edb92 MC |
508 | /* Must acquire the MDIO ownership before MAC reset. |
509 | * Ownership defaults to firmware after a reset. */ | |
510 | if(hw->mac_type == e1000_82573) { | |
511 | timeout = 10; | |
512 | ||
513 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | |
514 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
515 | ||
516 | do { | |
517 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); | |
518 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | |
519 | ||
520 | if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
521 | break; | |
522 | else | |
523 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
524 | ||
525 | msec_delay(2); | |
526 | timeout--; | |
527 | } while(timeout); | |
528 | } | |
529 | ||
1da177e4 LT |
530 | /* Issue a global reset to the MAC. This will reset the chip's |
531 | * transmit, receive, DMA, and link units. It will not effect | |
532 | * the current PCI configuration. The global reset bit is self- | |
533 | * clearing, and should clear within a microsecond. | |
534 | */ | |
535 | DEBUGOUT("Issuing a global reset to MAC\n"); | |
536 | ||
537 | switch(hw->mac_type) { | |
538 | case e1000_82544: | |
539 | case e1000_82540: | |
540 | case e1000_82545: | |
541 | case e1000_82546: | |
542 | case e1000_82541: | |
543 | case e1000_82541_rev_2: | |
544 | /* These controllers can't ack the 64-bit write when issuing the | |
545 | * reset, so use IO-mapping as a workaround to issue the reset */ | |
546 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); | |
547 | break; | |
548 | case e1000_82545_rev_3: | |
549 | case e1000_82546_rev_3: | |
550 | /* Reset is performed on a shadow of the control register */ | |
551 | E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); | |
552 | break; | |
553 | default: | |
554 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); | |
555 | break; | |
556 | } | |
557 | ||
558 | /* After MAC reset, force reload of EEPROM to restore power-on settings to | |
559 | * device. Later controllers reload the EEPROM automatically, so just wait | |
560 | * for reload to complete. | |
561 | */ | |
562 | switch(hw->mac_type) { | |
563 | case e1000_82542_rev2_0: | |
564 | case e1000_82542_rev2_1: | |
565 | case e1000_82543: | |
566 | case e1000_82544: | |
567 | /* Wait for reset to complete */ | |
568 | udelay(10); | |
569 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
570 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
571 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
572 | E1000_WRITE_FLUSH(hw); | |
573 | /* Wait for EEPROM reload */ | |
574 | msec_delay(2); | |
575 | break; | |
576 | case e1000_82541: | |
577 | case e1000_82541_rev_2: | |
578 | case e1000_82547: | |
579 | case e1000_82547_rev_2: | |
580 | /* Wait for EEPROM reload */ | |
581 | msec_delay(20); | |
582 | break; | |
2d7edb92 | 583 | case e1000_82573: |
fd803241 JK |
584 | if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
585 | udelay(10); | |
586 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
587 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
588 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
589 | E1000_WRITE_FLUSH(hw); | |
590 | } | |
2d7edb92 | 591 | /* fall through */ |
868d5309 MC |
592 | case e1000_82571: |
593 | case e1000_82572: | |
6418ecc6 | 594 | case e1000_80003es2lan: |
2d7edb92 MC |
595 | ret_val = e1000_get_auto_rd_done(hw); |
596 | if(ret_val) | |
597 | /* We don't want to continue accessing MAC registers. */ | |
598 | return ret_val; | |
599 | break; | |
1da177e4 LT |
600 | default: |
601 | /* Wait for EEPROM reload (it happens automatically) */ | |
602 | msec_delay(5); | |
603 | break; | |
604 | } | |
605 | ||
606 | /* Disable HW ARPs on ASF enabled adapters */ | |
2d7edb92 | 607 | if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { |
1da177e4 LT |
608 | manc = E1000_READ_REG(hw, MANC); |
609 | manc &= ~(E1000_MANC_ARP_EN); | |
610 | E1000_WRITE_REG(hw, MANC, manc); | |
611 | } | |
612 | ||
613 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | |
614 | e1000_phy_init_script(hw); | |
615 | ||
616 | /* Configure activity LED after PHY reset */ | |
617 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
618 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
619 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
620 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
621 | } | |
622 | ||
623 | /* Clear interrupt mask to stop board from generating interrupts */ | |
624 | DEBUGOUT("Masking off all interrupts\n"); | |
625 | E1000_WRITE_REG(hw, IMC, 0xffffffff); | |
626 | ||
627 | /* Clear any pending interrupt events. */ | |
628 | icr = E1000_READ_REG(hw, ICR); | |
629 | ||
630 | /* If MWI was previously enabled, reenable it. */ | |
631 | if(hw->mac_type == e1000_82542_rev2_0) { | |
632 | if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) | |
633 | e1000_pci_set_mwi(hw); | |
634 | } | |
635 | ||
636 | return E1000_SUCCESS; | |
637 | } | |
638 | ||
639 | /****************************************************************************** | |
640 | * Performs basic configuration of the adapter. | |
641 | * | |
642 | * hw - Struct containing variables accessed by shared code | |
643 | * | |
644 | * Assumes that the controller has previously been reset and is in a | |
645 | * post-reset uninitialized state. Initializes the receive address registers, | |
646 | * multicast table, and VLAN filter table. Calls routines to setup link | |
647 | * configuration and flow control settings. Clears all on-chip counters. Leaves | |
648 | * the transmit and receive units disabled and uninitialized. | |
649 | *****************************************************************************/ | |
650 | int32_t | |
651 | e1000_init_hw(struct e1000_hw *hw) | |
652 | { | |
653 | uint32_t ctrl; | |
654 | uint32_t i; | |
655 | int32_t ret_val; | |
656 | uint16_t pcix_cmd_word; | |
657 | uint16_t pcix_stat_hi_word; | |
658 | uint16_t cmd_mmrbc; | |
659 | uint16_t stat_mmrbc; | |
2d7edb92 | 660 | uint32_t mta_size; |
6418ecc6 | 661 | uint32_t reg_data; |
b7ee49db | 662 | uint32_t ctrl_ext; |
2d7edb92 | 663 | |
1da177e4 LT |
664 | DEBUGFUNC("e1000_init_hw"); |
665 | ||
666 | /* Initialize Identification LED */ | |
667 | ret_val = e1000_id_led_init(hw); | |
668 | if(ret_val) { | |
669 | DEBUGOUT("Error Initializing Identification LED\n"); | |
670 | return ret_val; | |
671 | } | |
672 | ||
673 | /* Set the media type and TBI compatibility */ | |
674 | e1000_set_media_type(hw); | |
675 | ||
676 | /* Disabling VLAN filtering. */ | |
677 | DEBUGOUT("Initializing the IEEE VLAN\n"); | |
2d7edb92 MC |
678 | if (hw->mac_type < e1000_82545_rev_3) |
679 | E1000_WRITE_REG(hw, VET, 0); | |
1da177e4 LT |
680 | e1000_clear_vfta(hw); |
681 | ||
682 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ | |
683 | if(hw->mac_type == e1000_82542_rev2_0) { | |
684 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); | |
685 | e1000_pci_clear_mwi(hw); | |
686 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); | |
687 | E1000_WRITE_FLUSH(hw); | |
688 | msec_delay(5); | |
689 | } | |
690 | ||
691 | /* Setup the receive address. This involves initializing all of the Receive | |
692 | * Address Registers (RARs 0 - 15). | |
693 | */ | |
694 | e1000_init_rx_addrs(hw); | |
695 | ||
696 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ | |
697 | if(hw->mac_type == e1000_82542_rev2_0) { | |
698 | E1000_WRITE_REG(hw, RCTL, 0); | |
699 | E1000_WRITE_FLUSH(hw); | |
700 | msec_delay(1); | |
701 | if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) | |
702 | e1000_pci_set_mwi(hw); | |
703 | } | |
704 | ||
705 | /* Zero out the Multicast HASH table */ | |
706 | DEBUGOUT("Zeroing the MTA\n"); | |
2d7edb92 MC |
707 | mta_size = E1000_MC_TBL_SIZE; |
708 | for(i = 0; i < mta_size; i++) | |
1da177e4 LT |
709 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
710 | ||
711 | /* Set the PCI priority bit correctly in the CTRL register. This | |
712 | * determines if the adapter gives priority to receives, or if it | |
2d7edb92 MC |
713 | * gives equal priority to transmits and receives. Valid only on |
714 | * 82542 and 82543 silicon. | |
1da177e4 | 715 | */ |
2d7edb92 | 716 | if(hw->dma_fairness && hw->mac_type <= e1000_82543) { |
1da177e4 LT |
717 | ctrl = E1000_READ_REG(hw, CTRL); |
718 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); | |
719 | } | |
720 | ||
721 | switch(hw->mac_type) { | |
722 | case e1000_82545_rev_3: | |
723 | case e1000_82546_rev_3: | |
724 | break; | |
725 | default: | |
726 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ | |
727 | if(hw->bus_type == e1000_bus_type_pcix) { | |
728 | e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); | |
729 | e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, | |
730 | &pcix_stat_hi_word); | |
731 | cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> | |
732 | PCIX_COMMAND_MMRBC_SHIFT; | |
733 | stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> | |
734 | PCIX_STATUS_HI_MMRBC_SHIFT; | |
735 | if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) | |
736 | stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; | |
737 | if(cmd_mmrbc > stat_mmrbc) { | |
738 | pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; | |
739 | pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; | |
740 | e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, | |
741 | &pcix_cmd_word); | |
742 | } | |
743 | } | |
744 | break; | |
745 | } | |
746 | ||
747 | /* Call a subroutine to configure the link and setup flow control. */ | |
748 | ret_val = e1000_setup_link(hw); | |
749 | ||
750 | /* Set the transmit descriptor write-back policy */ | |
751 | if(hw->mac_type > e1000_82544) { | |
752 | ctrl = E1000_READ_REG(hw, TXDCTL); | |
753 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; | |
2d7edb92 MC |
754 | switch (hw->mac_type) { |
755 | default: | |
756 | break; | |
868d5309 MC |
757 | case e1000_82571: |
758 | case e1000_82572: | |
2d7edb92 | 759 | case e1000_82573: |
6418ecc6 | 760 | case e1000_80003es2lan: |
2d7edb92 MC |
761 | ctrl |= E1000_TXDCTL_COUNT_DESC; |
762 | break; | |
763 | } | |
1da177e4 LT |
764 | E1000_WRITE_REG(hw, TXDCTL, ctrl); |
765 | } | |
766 | ||
2d7edb92 | 767 | if (hw->mac_type == e1000_82573) { |
76c224bc | 768 | e1000_enable_tx_pkt_filtering(hw); |
2d7edb92 MC |
769 | } |
770 | ||
868d5309 MC |
771 | switch (hw->mac_type) { |
772 | default: | |
773 | break; | |
6418ecc6 JK |
774 | case e1000_80003es2lan: |
775 | /* Enable retransmit on late collisions */ | |
776 | reg_data = E1000_READ_REG(hw, TCTL); | |
777 | reg_data |= E1000_TCTL_RTLC; | |
778 | E1000_WRITE_REG(hw, TCTL, reg_data); | |
779 | ||
780 | /* Configure Gigabit Carry Extend Padding */ | |
781 | reg_data = E1000_READ_REG(hw, TCTL_EXT); | |
782 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | |
783 | reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; | |
784 | E1000_WRITE_REG(hw, TCTL_EXT, reg_data); | |
785 | ||
786 | /* Configure Transmit Inter-Packet Gap */ | |
787 | reg_data = E1000_READ_REG(hw, TIPG); | |
788 | reg_data &= ~E1000_TIPG_IPGT_MASK; | |
789 | reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | |
790 | E1000_WRITE_REG(hw, TIPG, reg_data); | |
791 | ||
792 | reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); | |
793 | reg_data &= ~0x00100000; | |
794 | E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); | |
795 | /* Fall through */ | |
868d5309 | 796 | case e1000_82571: |
a7990ba6 | 797 | case e1000_82572: |
868d5309 | 798 | ctrl = E1000_READ_REG(hw, TXDCTL1); |
6418ecc6 JK |
799 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
800 | if(hw->mac_type >= e1000_82571) | |
801 | ctrl |= E1000_TXDCTL_COUNT_DESC; | |
868d5309 MC |
802 | E1000_WRITE_REG(hw, TXDCTL1, ctrl); |
803 | break; | |
804 | } | |
805 | ||
806 | ||
807 | ||
808 | if (hw->mac_type == e1000_82573) { | |
809 | uint32_t gcr = E1000_READ_REG(hw, GCR); | |
810 | gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
811 | E1000_WRITE_REG(hw, GCR, gcr); | |
812 | } | |
2d7edb92 | 813 | |
1da177e4 LT |
814 | /* Clear all of the statistics registers (clear on read). It is |
815 | * important that we do this after we have tried to establish link | |
816 | * because the symbol error count will increment wildly if there | |
817 | * is no link. | |
818 | */ | |
819 | e1000_clear_hw_cntrs(hw); | |
820 | ||
b7ee49db JK |
821 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
822 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { | |
823 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
824 | /* Relaxed ordering must be disabled to avoid a parity | |
825 | * error crash in a PCI slot. */ | |
826 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
827 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
828 | } | |
829 | ||
1da177e4 LT |
830 | return ret_val; |
831 | } | |
832 | ||
833 | /****************************************************************************** | |
834 | * Adjust SERDES output amplitude based on EEPROM setting. | |
835 | * | |
836 | * hw - Struct containing variables accessed by shared code. | |
837 | *****************************************************************************/ | |
838 | static int32_t | |
839 | e1000_adjust_serdes_amplitude(struct e1000_hw *hw) | |
840 | { | |
841 | uint16_t eeprom_data; | |
842 | int32_t ret_val; | |
843 | ||
844 | DEBUGFUNC("e1000_adjust_serdes_amplitude"); | |
845 | ||
846 | if(hw->media_type != e1000_media_type_internal_serdes) | |
847 | return E1000_SUCCESS; | |
848 | ||
849 | switch(hw->mac_type) { | |
850 | case e1000_82545_rev_3: | |
851 | case e1000_82546_rev_3: | |
852 | break; | |
853 | default: | |
854 | return E1000_SUCCESS; | |
855 | } | |
856 | ||
857 | ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); | |
858 | if (ret_val) { | |
859 | return ret_val; | |
860 | } | |
861 | ||
862 | if(eeprom_data != EEPROM_RESERVED_WORD) { | |
863 | /* Adjust SERDES output amplitude only. */ | |
76c224bc | 864 | eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
1da177e4 LT |
865 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
866 | if(ret_val) | |
867 | return ret_val; | |
868 | } | |
869 | ||
870 | return E1000_SUCCESS; | |
871 | } | |
872 | ||
873 | /****************************************************************************** | |
874 | * Configures flow control and link settings. | |
875 | * | |
876 | * hw - Struct containing variables accessed by shared code | |
877 | * | |
878 | * Determines which flow control settings to use. Calls the apropriate media- | |
879 | * specific link configuration function. Configures the flow control settings. | |
880 | * Assuming the adapter has a valid link partner, a valid link should be | |
881 | * established. Assumes the hardware has previously been reset and the | |
882 | * transmitter and receiver are not enabled. | |
883 | *****************************************************************************/ | |
884 | int32_t | |
885 | e1000_setup_link(struct e1000_hw *hw) | |
886 | { | |
887 | uint32_t ctrl_ext; | |
888 | int32_t ret_val; | |
889 | uint16_t eeprom_data; | |
890 | ||
891 | DEBUGFUNC("e1000_setup_link"); | |
892 | ||
526f9957 JK |
893 | /* In the case of the phy reset being blocked, we already have a link. |
894 | * We do not have to set it up again. */ | |
895 | if (e1000_check_phy_reset_block(hw)) | |
896 | return E1000_SUCCESS; | |
897 | ||
1da177e4 LT |
898 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
899 | * that determine the hardware's default PAUSE (flow control) mode, | |
900 | * a bit that determines whether the HW defaults to enabling or | |
901 | * disabling auto-negotiation, and the direction of the | |
902 | * SW defined pins. If there is no SW over-ride of the flow | |
903 | * control setting, then the variable hw->fc will | |
904 | * be initialized based on a value in the EEPROM. | |
905 | */ | |
fd803241 JK |
906 | if (hw->fc == e1000_fc_default) { |
907 | switch (hw->mac_type) { | |
908 | case e1000_82573: | |
1da177e4 | 909 | hw->fc = e1000_fc_full; |
fd803241 JK |
910 | break; |
911 | default: | |
912 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, | |
913 | 1, &eeprom_data); | |
914 | if (ret_val) { | |
915 | DEBUGOUT("EEPROM Read Error\n"); | |
916 | return -E1000_ERR_EEPROM; | |
917 | } | |
918 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) | |
919 | hw->fc = e1000_fc_none; | |
920 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == | |
921 | EEPROM_WORD0F_ASM_DIR) | |
922 | hw->fc = e1000_fc_tx_pause; | |
923 | else | |
924 | hw->fc = e1000_fc_full; | |
925 | break; | |
926 | } | |
1da177e4 LT |
927 | } |
928 | ||
929 | /* We want to save off the original Flow Control configuration just | |
930 | * in case we get disconnected and then reconnected into a different | |
931 | * hub or switch with different Flow Control capabilities. | |
932 | */ | |
933 | if(hw->mac_type == e1000_82542_rev2_0) | |
934 | hw->fc &= (~e1000_fc_tx_pause); | |
935 | ||
936 | if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) | |
937 | hw->fc &= (~e1000_fc_rx_pause); | |
938 | ||
939 | hw->original_fc = hw->fc; | |
940 | ||
941 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); | |
942 | ||
943 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial | |
944 | * polarity value for the SW controlled pins, and setup the | |
945 | * Extended Device Control reg with that info. | |
946 | * This is needed because one of the SW controlled pins is used for | |
947 | * signal detection. So this should be done before e1000_setup_pcs_link() | |
948 | * or e1000_phy_setup() is called. | |
949 | */ | |
497fce5e JK |
950 | if (hw->mac_type == e1000_82543) { |
951 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, | |
952 | 1, &eeprom_data); | |
953 | if (ret_val) { | |
954 | DEBUGOUT("EEPROM Read Error\n"); | |
955 | return -E1000_ERR_EEPROM; | |
956 | } | |
1da177e4 LT |
957 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
958 | SWDPIO__EXT_SHIFT); | |
959 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
960 | } | |
961 | ||
962 | /* Call the necessary subroutine to configure the link. */ | |
963 | ret_val = (hw->media_type == e1000_media_type_copper) ? | |
964 | e1000_setup_copper_link(hw) : | |
965 | e1000_setup_fiber_serdes_link(hw); | |
966 | ||
967 | /* Initialize the flow control address, type, and PAUSE timer | |
968 | * registers to their default values. This is done even if flow | |
969 | * control is disabled, because it does not hurt anything to | |
970 | * initialize these registers. | |
971 | */ | |
972 | DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); | |
973 | ||
974 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); | |
975 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); | |
976 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); | |
2d7edb92 | 977 | |
1da177e4 LT |
978 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
979 | ||
980 | /* Set the flow control receive threshold registers. Normally, | |
981 | * these registers will be set to a default threshold that may be | |
982 | * adjusted later by the driver's runtime code. However, if the | |
983 | * ability to transmit pause frames in not enabled, then these | |
984 | * registers will be set to 0. | |
985 | */ | |
986 | if(!(hw->fc & e1000_fc_tx_pause)) { | |
987 | E1000_WRITE_REG(hw, FCRTL, 0); | |
988 | E1000_WRITE_REG(hw, FCRTH, 0); | |
989 | } else { | |
990 | /* We need to set up the Receive Threshold high and low water marks | |
991 | * as well as (optionally) enabling the transmission of XON frames. | |
992 | */ | |
993 | if(hw->fc_send_xon) { | |
994 | E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); | |
995 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); | |
996 | } else { | |
997 | E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); | |
998 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); | |
999 | } | |
1000 | } | |
1001 | return ret_val; | |
1002 | } | |
1003 | ||
1004 | /****************************************************************************** | |
1005 | * Sets up link for a fiber based or serdes based adapter | |
1006 | * | |
1007 | * hw - Struct containing variables accessed by shared code | |
1008 | * | |
1009 | * Manipulates Physical Coding Sublayer functions in order to configure | |
1010 | * link. Assumes the hardware has been previously reset and the transmitter | |
1011 | * and receiver are not enabled. | |
1012 | *****************************************************************************/ | |
1013 | static int32_t | |
1014 | e1000_setup_fiber_serdes_link(struct e1000_hw *hw) | |
1015 | { | |
1016 | uint32_t ctrl; | |
1017 | uint32_t status; | |
1018 | uint32_t txcw = 0; | |
1019 | uint32_t i; | |
1020 | uint32_t signal = 0; | |
1021 | int32_t ret_val; | |
1022 | ||
1023 | DEBUGFUNC("e1000_setup_fiber_serdes_link"); | |
1024 | ||
868d5309 MC |
1025 | /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists |
1026 | * until explicitly turned off or a power cycle is performed. A read to | |
1027 | * the register does not indicate its status. Therefore, we ensure | |
1028 | * loopback mode is disabled during initialization. | |
1029 | */ | |
1030 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) | |
1031 | E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); | |
1032 | ||
1da177e4 LT |
1033 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be |
1034 | * set when the optics detect a signal. On older adapters, it will be | |
1035 | * cleared when there is a signal. This applies to fiber media only. | |
1036 | * If we're on serdes media, adjust the output amplitude to value set in | |
1037 | * the EEPROM. | |
1038 | */ | |
1039 | ctrl = E1000_READ_REG(hw, CTRL); | |
1040 | if(hw->media_type == e1000_media_type_fiber) | |
1041 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; | |
1042 | ||
1043 | ret_val = e1000_adjust_serdes_amplitude(hw); | |
1044 | if(ret_val) | |
1045 | return ret_val; | |
1046 | ||
1047 | /* Take the link out of reset */ | |
1048 | ctrl &= ~(E1000_CTRL_LRST); | |
1049 | ||
1050 | /* Adjust VCO speed to improve BER performance */ | |
1051 | ret_val = e1000_set_vco_speed(hw); | |
1052 | if(ret_val) | |
1053 | return ret_val; | |
1054 | ||
1055 | e1000_config_collision_dist(hw); | |
1056 | ||
1057 | /* Check for a software override of the flow control settings, and setup | |
1058 | * the device accordingly. If auto-negotiation is enabled, then software | |
1059 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit | |
1060 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if | |
1061 | * auto-negotiation is disabled, then software will have to manually | |
1062 | * configure the two flow control enable bits in the CTRL register. | |
1063 | * | |
1064 | * The possible values of the "fc" parameter are: | |
1065 | * 0: Flow control is completely disabled | |
1066 | * 1: Rx flow control is enabled (we can receive pause frames, but | |
1067 | * not send pause frames). | |
1068 | * 2: Tx flow control is enabled (we can send pause frames but we do | |
1069 | * not support receiving pause frames). | |
1070 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
1071 | */ | |
1072 | switch (hw->fc) { | |
1073 | case e1000_fc_none: | |
1074 | /* Flow control is completely disabled by a software over-ride. */ | |
1075 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); | |
1076 | break; | |
1077 | case e1000_fc_rx_pause: | |
1078 | /* RX Flow control is enabled and TX Flow control is disabled by a | |
1079 | * software over-ride. Since there really isn't a way to advertise | |
1080 | * that we are capable of RX Pause ONLY, we will advertise that we | |
1081 | * support both symmetric and asymmetric RX PAUSE. Later, we will | |
1082 | * disable the adapter's ability to send PAUSE frames. | |
1083 | */ | |
1084 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
1085 | break; | |
1086 | case e1000_fc_tx_pause: | |
1087 | /* TX Flow control is enabled, and RX Flow control is disabled, by a | |
1088 | * software over-ride. | |
1089 | */ | |
1090 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); | |
1091 | break; | |
1092 | case e1000_fc_full: | |
1093 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ | |
1094 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); | |
1095 | break; | |
1096 | default: | |
1097 | DEBUGOUT("Flow control param set incorrectly\n"); | |
1098 | return -E1000_ERR_CONFIG; | |
1099 | break; | |
1100 | } | |
1101 | ||
1102 | /* Since auto-negotiation is enabled, take the link out of reset (the link | |
1103 | * will be in reset, because we previously reset the chip). This will | |
1104 | * restart auto-negotiation. If auto-neogtiation is successful then the | |
1105 | * link-up status bit will be set and the flow control enable bits (RFCE | |
1106 | * and TFCE) will be set according to their negotiated value. | |
1107 | */ | |
1108 | DEBUGOUT("Auto-negotiation enabled\n"); | |
1109 | ||
1110 | E1000_WRITE_REG(hw, TXCW, txcw); | |
1111 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
1112 | E1000_WRITE_FLUSH(hw); | |
1113 | ||
1114 | hw->txcw = txcw; | |
1115 | msec_delay(1); | |
1116 | ||
1117 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" | |
1118 | * indication in the Device Status Register. Time-out if a link isn't | |
1119 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in | |
1120 | * less than 500 milliseconds even if the other end is doing it in SW). | |
1121 | * For internal serdes, we just assume a signal is present, then poll. | |
1122 | */ | |
1123 | if(hw->media_type == e1000_media_type_internal_serdes || | |
1124 | (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { | |
1125 | DEBUGOUT("Looking for Link\n"); | |
1126 | for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { | |
1127 | msec_delay(10); | |
1128 | status = E1000_READ_REG(hw, STATUS); | |
1129 | if(status & E1000_STATUS_LU) break; | |
1130 | } | |
1131 | if(i == (LINK_UP_TIMEOUT / 10)) { | |
1132 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); | |
1133 | hw->autoneg_failed = 1; | |
1134 | /* AutoNeg failed to achieve a link, so we'll call | |
1135 | * e1000_check_for_link. This routine will force the link up if | |
1136 | * we detect a signal. This will allow us to communicate with | |
1137 | * non-autonegotiating link partners. | |
1138 | */ | |
1139 | ret_val = e1000_check_for_link(hw); | |
1140 | if(ret_val) { | |
1141 | DEBUGOUT("Error while checking for link\n"); | |
1142 | return ret_val; | |
1143 | } | |
1144 | hw->autoneg_failed = 0; | |
1145 | } else { | |
1146 | hw->autoneg_failed = 0; | |
1147 | DEBUGOUT("Valid Link Found\n"); | |
1148 | } | |
1149 | } else { | |
1150 | DEBUGOUT("No Signal Detected\n"); | |
1151 | } | |
1152 | return E1000_SUCCESS; | |
1153 | } | |
1154 | ||
1155 | /****************************************************************************** | |
2d7edb92 | 1156 | * Make sure we have a valid PHY and change PHY mode before link setup. |
1da177e4 LT |
1157 | * |
1158 | * hw - Struct containing variables accessed by shared code | |
1159 | ******************************************************************************/ | |
1160 | static int32_t | |
2d7edb92 | 1161 | e1000_copper_link_preconfig(struct e1000_hw *hw) |
1da177e4 LT |
1162 | { |
1163 | uint32_t ctrl; | |
1da177e4 | 1164 | int32_t ret_val; |
1da177e4 LT |
1165 | uint16_t phy_data; |
1166 | ||
2d7edb92 | 1167 | DEBUGFUNC("e1000_copper_link_preconfig"); |
1da177e4 LT |
1168 | |
1169 | ctrl = E1000_READ_REG(hw, CTRL); | |
1170 | /* With 82543, we need to force speed and duplex on the MAC equal to what | |
1171 | * the PHY speed and duplex configuration is. In addition, we need to | |
1172 | * perform a hardware reset on the PHY to take it out of reset. | |
1173 | */ | |
1174 | if(hw->mac_type > e1000_82543) { | |
1175 | ctrl |= E1000_CTRL_SLU; | |
1176 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1177 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
1178 | } else { | |
1179 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); | |
1180 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2d7edb92 MC |
1181 | ret_val = e1000_phy_hw_reset(hw); |
1182 | if(ret_val) | |
1183 | return ret_val; | |
1da177e4 LT |
1184 | } |
1185 | ||
1186 | /* Make sure we have a valid PHY */ | |
1187 | ret_val = e1000_detect_gig_phy(hw); | |
1188 | if(ret_val) { | |
1189 | DEBUGOUT("Error, did not detect valid phy.\n"); | |
1190 | return ret_val; | |
1191 | } | |
1192 | DEBUGOUT1("Phy ID = %x \n", hw->phy_id); | |
1193 | ||
1194 | /* Set PHY to class A mode (if necessary) */ | |
1195 | ret_val = e1000_set_phy_mode(hw); | |
1196 | if(ret_val) | |
1197 | return ret_val; | |
1198 | ||
1199 | if((hw->mac_type == e1000_82545_rev_3) || | |
1200 | (hw->mac_type == e1000_82546_rev_3)) { | |
1201 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1202 | phy_data |= 0x00000008; | |
1203 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1204 | } | |
1205 | ||
1206 | if(hw->mac_type <= e1000_82543 || | |
1207 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || | |
1208 | hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) | |
1209 | hw->phy_reset_disable = FALSE; | |
1210 | ||
2d7edb92 MC |
1211 | return E1000_SUCCESS; |
1212 | } | |
1da177e4 | 1213 | |
1da177e4 | 1214 | |
2d7edb92 MC |
1215 | /******************************************************************** |
1216 | * Copper link setup for e1000_phy_igp series. | |
1217 | * | |
1218 | * hw - Struct containing variables accessed by shared code | |
1219 | *********************************************************************/ | |
1220 | static int32_t | |
1221 | e1000_copper_link_igp_setup(struct e1000_hw *hw) | |
1222 | { | |
1223 | uint32_t led_ctrl; | |
1224 | int32_t ret_val; | |
1225 | uint16_t phy_data; | |
1da177e4 | 1226 | |
2d7edb92 | 1227 | DEBUGFUNC("e1000_copper_link_igp_setup"); |
1da177e4 | 1228 | |
2d7edb92 MC |
1229 | if (hw->phy_reset_disable) |
1230 | return E1000_SUCCESS; | |
76c224bc | 1231 | |
2d7edb92 MC |
1232 | ret_val = e1000_phy_reset(hw); |
1233 | if (ret_val) { | |
1234 | DEBUGOUT("Error Resetting the PHY\n"); | |
1235 | return ret_val; | |
1236 | } | |
1da177e4 | 1237 | |
2d7edb92 MC |
1238 | /* Wait 10ms for MAC to configure PHY from eeprom settings */ |
1239 | msec_delay(15); | |
1da177e4 | 1240 | |
2d7edb92 MC |
1241 | /* Configure activity LED after PHY reset */ |
1242 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
1243 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
1244 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1245 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
1da177e4 | 1246 | |
2d7edb92 MC |
1247 | /* disable lplu d3 during driver init */ |
1248 | ret_val = e1000_set_d3_lplu_state(hw, FALSE); | |
1249 | if (ret_val) { | |
1250 | DEBUGOUT("Error Disabling LPLU D3\n"); | |
1251 | return ret_val; | |
1252 | } | |
1da177e4 | 1253 | |
2d7edb92 MC |
1254 | /* disable lplu d0 during driver init */ |
1255 | ret_val = e1000_set_d0_lplu_state(hw, FALSE); | |
1256 | if (ret_val) { | |
1257 | DEBUGOUT("Error Disabling LPLU D0\n"); | |
1258 | return ret_val; | |
1259 | } | |
1260 | /* Configure mdi-mdix settings */ | |
1261 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
1262 | if (ret_val) | |
1263 | return ret_val; | |
1da177e4 | 1264 | |
2d7edb92 MC |
1265 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1266 | hw->dsp_config_state = e1000_dsp_config_disabled; | |
1267 | /* Force MDI for earlier revs of the IGP PHY */ | |
1268 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); | |
1269 | hw->mdix = 1; | |
1da177e4 | 1270 | |
2d7edb92 MC |
1271 | } else { |
1272 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
1273 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1da177e4 | 1274 | |
2d7edb92 MC |
1275 | switch (hw->mdix) { |
1276 | case 1: | |
1277 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1278 | break; | |
1279 | case 2: | |
1280 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1281 | break; | |
1282 | case 0: | |
1283 | default: | |
1284 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; | |
1285 | break; | |
1286 | } | |
1287 | } | |
1288 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
1289 | if(ret_val) | |
1290 | return ret_val; | |
1da177e4 | 1291 | |
2d7edb92 MC |
1292 | /* set auto-master slave resolution settings */ |
1293 | if(hw->autoneg) { | |
1294 | e1000_ms_type phy_ms_setting = hw->master_slave; | |
1da177e4 | 1295 | |
2d7edb92 MC |
1296 | if(hw->ffe_config_state == e1000_ffe_config_active) |
1297 | hw->ffe_config_state = e1000_ffe_config_enabled; | |
1da177e4 | 1298 | |
2d7edb92 MC |
1299 | if(hw->dsp_config_state == e1000_dsp_config_activated) |
1300 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
1da177e4 | 1301 | |
2d7edb92 MC |
1302 | /* when autonegotiation advertisment is only 1000Mbps then we |
1303 | * should disable SmartSpeed and enable Auto MasterSlave | |
1304 | * resolution as hardware default. */ | |
1305 | if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { | |
1306 | /* Disable SmartSpeed */ | |
1307 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
1da177e4 LT |
1308 | if(ret_val) |
1309 | return ret_val; | |
2d7edb92 MC |
1310 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
1311 | ret_val = e1000_write_phy_reg(hw, | |
1312 | IGP01E1000_PHY_PORT_CONFIG, | |
1313 | phy_data); | |
1da177e4 LT |
1314 | if(ret_val) |
1315 | return ret_val; | |
2d7edb92 MC |
1316 | /* Set auto Master/Slave resolution process */ |
1317 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); | |
1318 | if(ret_val) | |
1319 | return ret_val; | |
1320 | phy_data &= ~CR_1000T_MS_ENABLE; | |
1321 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | |
1322 | if(ret_val) | |
1323 | return ret_val; | |
1324 | } | |
1da177e4 | 1325 | |
2d7edb92 MC |
1326 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
1327 | if(ret_val) | |
1328 | return ret_val; | |
1da177e4 | 1329 | |
2d7edb92 MC |
1330 | /* load defaults for future use */ |
1331 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? | |
1332 | ((phy_data & CR_1000T_MS_VALUE) ? | |
1333 | e1000_ms_force_master : | |
1334 | e1000_ms_force_slave) : | |
1335 | e1000_ms_auto; | |
1da177e4 | 1336 | |
2d7edb92 MC |
1337 | switch (phy_ms_setting) { |
1338 | case e1000_ms_force_master: | |
1339 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
1340 | break; | |
1341 | case e1000_ms_force_slave: | |
1342 | phy_data |= CR_1000T_MS_ENABLE; | |
1343 | phy_data &= ~(CR_1000T_MS_VALUE); | |
1344 | break; | |
1345 | case e1000_ms_auto: | |
1346 | phy_data &= ~CR_1000T_MS_ENABLE; | |
1347 | default: | |
1348 | break; | |
1349 | } | |
1350 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | |
1351 | if(ret_val) | |
1352 | return ret_val; | |
2b02893e | 1353 | } |
1da177e4 | 1354 | |
2b02893e | 1355 | return E1000_SUCCESS; |
2d7edb92 | 1356 | } |
1da177e4 | 1357 | |
6418ecc6 JK |
1358 | /******************************************************************** |
1359 | * Copper link setup for e1000_phy_gg82563 series. | |
1360 | * | |
1361 | * hw - Struct containing variables accessed by shared code | |
1362 | *********************************************************************/ | |
1363 | static int32_t | |
1364 | e1000_copper_link_ggp_setup(struct e1000_hw *hw) | |
1365 | { | |
1366 | int32_t ret_val; | |
1367 | uint16_t phy_data; | |
1368 | uint32_t reg_data; | |
1369 | ||
1370 | DEBUGFUNC("e1000_copper_link_ggp_setup"); | |
1371 | ||
1372 | if(!hw->phy_reset_disable) { | |
76c224bc | 1373 | |
6418ecc6 JK |
1374 | /* Enable CRS on TX for half-duplex operation. */ |
1375 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, | |
1376 | &phy_data); | |
1377 | if(ret_val) | |
1378 | return ret_val; | |
1379 | ||
1380 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
1381 | /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ | |
1382 | phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; | |
1383 | ||
1384 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, | |
1385 | phy_data); | |
1386 | if(ret_val) | |
1387 | return ret_val; | |
1388 | ||
1389 | /* Options: | |
1390 | * MDI/MDI-X = 0 (default) | |
1391 | * 0 - Auto for all speeds | |
1392 | * 1 - MDI mode | |
1393 | * 2 - MDI-X mode | |
1394 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
1395 | */ | |
1396 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); | |
1397 | if(ret_val) | |
1398 | return ret_val; | |
1399 | ||
1400 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
1401 | ||
1402 | switch (hw->mdix) { | |
1403 | case 1: | |
1404 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
1405 | break; | |
1406 | case 2: | |
1407 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
1408 | break; | |
1409 | case 0: | |
1410 | default: | |
1411 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
1412 | break; | |
1413 | } | |
1414 | ||
1415 | /* Options: | |
1416 | * disable_polarity_correction = 0 (default) | |
1417 | * Automatic Correction for Reversed Cable Polarity | |
1418 | * 0 - Disabled | |
1419 | * 1 - Enabled | |
1420 | */ | |
1421 | phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
1422 | if(hw->disable_polarity_correction == 1) | |
1423 | phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
1424 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); | |
1425 | ||
1426 | if(ret_val) | |
1427 | return ret_val; | |
1428 | ||
1429 | /* SW Reset the PHY so all changes take effect */ | |
1430 | ret_val = e1000_phy_reset(hw); | |
1431 | if (ret_val) { | |
1432 | DEBUGOUT("Error Resetting the PHY\n"); | |
1433 | return ret_val; | |
1434 | } | |
1435 | } /* phy_reset_disable */ | |
1436 | ||
1437 | if (hw->mac_type == e1000_80003es2lan) { | |
1438 | /* Bypass RX and TX FIFO's */ | |
1439 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, | |
1440 | E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | | |
1441 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); | |
1442 | if (ret_val) | |
1443 | return ret_val; | |
1444 | ||
1445 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); | |
1446 | if (ret_val) | |
1447 | return ret_val; | |
1448 | ||
1449 | phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
1450 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); | |
1451 | ||
1452 | if (ret_val) | |
1453 | return ret_val; | |
1454 | ||
1455 | reg_data = E1000_READ_REG(hw, CTRL_EXT); | |
1456 | reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | |
1457 | E1000_WRITE_REG(hw, CTRL_EXT, reg_data); | |
1458 | ||
1459 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, | |
1460 | &phy_data); | |
1461 | if (ret_val) | |
1462 | return ret_val; | |
1463 | ||
1464 | /* Do not init these registers when the HW is in IAMT mode, since the | |
1465 | * firmware will have already initialized them. We only initialize | |
1466 | * them if the HW is not in IAMT mode. | |
1467 | */ | |
1468 | if (e1000_check_mng_mode(hw) == FALSE) { | |
1469 | /* Enable Electrical Idle on the PHY */ | |
1470 | phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
1471 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, | |
1472 | phy_data); | |
1473 | if (ret_val) | |
1474 | return ret_val; | |
1475 | ||
1476 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, | |
1477 | &phy_data); | |
1478 | if (ret_val) | |
1479 | return ret_val; | |
1480 | ||
1481 | /* Enable Pass False Carrier on the PHY */ | |
1482 | phy_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
1483 | ||
1484 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, | |
1485 | phy_data); | |
1486 | if (ret_val) | |
1487 | return ret_val; | |
1488 | } | |
1489 | ||
1490 | /* Workaround: Disable padding in Kumeran interface in the MAC | |
1491 | * and in the PHY to avoid CRC errors. | |
1492 | */ | |
1493 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, | |
1494 | &phy_data); | |
1495 | if (ret_val) | |
1496 | return ret_val; | |
1497 | phy_data |= GG82563_ICR_DIS_PADDING; | |
1498 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, | |
1499 | phy_data); | |
1500 | if (ret_val) | |
1501 | return ret_val; | |
1502 | } | |
1503 | ||
1504 | return E1000_SUCCESS; | |
1505 | } | |
1da177e4 | 1506 | |
2d7edb92 MC |
1507 | /******************************************************************** |
1508 | * Copper link setup for e1000_phy_m88 series. | |
1509 | * | |
1510 | * hw - Struct containing variables accessed by shared code | |
1511 | *********************************************************************/ | |
1512 | static int32_t | |
1513 | e1000_copper_link_mgp_setup(struct e1000_hw *hw) | |
1514 | { | |
1515 | int32_t ret_val; | |
1516 | uint16_t phy_data; | |
1da177e4 | 1517 | |
2d7edb92 | 1518 | DEBUGFUNC("e1000_copper_link_mgp_setup"); |
1da177e4 | 1519 | |
2d7edb92 MC |
1520 | if(hw->phy_reset_disable) |
1521 | return E1000_SUCCESS; | |
76c224bc | 1522 | |
2d7edb92 MC |
1523 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
1524 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1525 | if(ret_val) | |
1526 | return ret_val; | |
1da177e4 | 1527 | |
2d7edb92 | 1528 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
1da177e4 | 1529 | |
2d7edb92 MC |
1530 | /* Options: |
1531 | * MDI/MDI-X = 0 (default) | |
1532 | * 0 - Auto for all speeds | |
1533 | * 1 - MDI mode | |
1534 | * 2 - MDI-X mode | |
1535 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
1536 | */ | |
1537 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
1da177e4 | 1538 | |
2d7edb92 MC |
1539 | switch (hw->mdix) { |
1540 | case 1: | |
1541 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
1542 | break; | |
1543 | case 2: | |
1544 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
1545 | break; | |
1546 | case 3: | |
1547 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
1548 | break; | |
1549 | case 0: | |
1550 | default: | |
1551 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
1552 | break; | |
1553 | } | |
1554 | ||
1555 | /* Options: | |
1556 | * disable_polarity_correction = 0 (default) | |
1557 | * Automatic Correction for Reversed Cable Polarity | |
1558 | * 0 - Disabled | |
1559 | * 1 - Enabled | |
1da177e4 | 1560 | */ |
2d7edb92 MC |
1561 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
1562 | if(hw->disable_polarity_correction == 1) | |
1563 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
1564 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1da177e4 LT |
1565 | if(ret_val) |
1566 | return ret_val; | |
2d7edb92 MC |
1567 | |
1568 | /* Force TX_CLK in the Extended PHY Specific Control Register | |
1569 | * to 25MHz clock. | |
1570 | */ | |
1571 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
1572 | if(ret_val) | |
1573 | return ret_val; | |
1574 | ||
1575 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
1576 | ||
1577 | if (hw->phy_revision < M88E1011_I_REV_4) { | |
1578 | /* Configure Master and Slave downshift values */ | |
1579 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
1580 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
1581 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
1582 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
1583 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1da177e4 LT |
1584 | if(ret_val) |
1585 | return ret_val; | |
2d7edb92 | 1586 | } |
1da177e4 | 1587 | |
2d7edb92 MC |
1588 | /* SW Reset the PHY so all changes take effect */ |
1589 | ret_val = e1000_phy_reset(hw); | |
1590 | if(ret_val) { | |
1591 | DEBUGOUT("Error Resetting the PHY\n"); | |
1592 | return ret_val; | |
1da177e4 LT |
1593 | } |
1594 | ||
2d7edb92 | 1595 | return E1000_SUCCESS; |
1da177e4 LT |
1596 | } |
1597 | ||
2d7edb92 MC |
1598 | /******************************************************************** |
1599 | * Setup auto-negotiation and flow control advertisements, | |
1600 | * and then perform auto-negotiation. | |
1da177e4 LT |
1601 | * |
1602 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
1603 | *********************************************************************/ |
1604 | static int32_t | |
1605 | e1000_copper_link_autoneg(struct e1000_hw *hw) | |
1da177e4 LT |
1606 | { |
1607 | int32_t ret_val; | |
2d7edb92 | 1608 | uint16_t phy_data; |
1da177e4 | 1609 | |
2d7edb92 | 1610 | DEBUGFUNC("e1000_copper_link_autoneg"); |
1da177e4 | 1611 | |
2d7edb92 MC |
1612 | /* Perform some bounds checking on the hw->autoneg_advertised |
1613 | * parameter. If this variable is zero, then set it to the default. | |
1614 | */ | |
1615 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
1616 | ||
1617 | /* If autoneg_advertised is zero, we assume it was not defaulted | |
1618 | * by the calling code so we set to advertise full capability. | |
1619 | */ | |
1620 | if(hw->autoneg_advertised == 0) | |
1621 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
1622 | ||
1623 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); | |
1624 | ret_val = e1000_phy_setup_autoneg(hw); | |
1625 | if(ret_val) { | |
1626 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); | |
1627 | return ret_val; | |
1628 | } | |
1629 | DEBUGOUT("Restarting Auto-Neg\n"); | |
1630 | ||
1631 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and | |
1632 | * the Auto Neg Restart bit in the PHY control register. | |
1633 | */ | |
1634 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | |
1da177e4 LT |
1635 | if(ret_val) |
1636 | return ret_val; | |
1637 | ||
2d7edb92 MC |
1638 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
1639 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | |
1da177e4 LT |
1640 | if(ret_val) |
1641 | return ret_val; | |
1642 | ||
2d7edb92 MC |
1643 | /* Does the user want to wait for Auto-Neg to complete here, or |
1644 | * check at a later time (for example, callback routine). | |
1645 | */ | |
1646 | if(hw->wait_autoneg_complete) { | |
1647 | ret_val = e1000_wait_autoneg(hw); | |
1648 | if(ret_val) { | |
1649 | DEBUGOUT("Error while waiting for autoneg to complete\n"); | |
1650 | return ret_val; | |
1651 | } | |
1652 | } | |
1653 | ||
1654 | hw->get_link_status = TRUE; | |
1655 | ||
1656 | return E1000_SUCCESS; | |
1657 | } | |
1658 | ||
1659 | ||
1660 | /****************************************************************************** | |
1661 | * Config the MAC and the PHY after link is up. | |
1662 | * 1) Set up the MAC to the current PHY speed/duplex | |
1663 | * if we are on 82543. If we | |
1664 | * are on newer silicon, we only need to configure | |
1665 | * collision distance in the Transmit Control Register. | |
1666 | * 2) Set up flow control on the MAC to that established with | |
1667 | * the link partner. | |
76c224bc | 1668 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
2d7edb92 MC |
1669 | * |
1670 | * hw - Struct containing variables accessed by shared code | |
1671 | ******************************************************************************/ | |
1672 | static int32_t | |
1673 | e1000_copper_link_postconfig(struct e1000_hw *hw) | |
1674 | { | |
1675 | int32_t ret_val; | |
1676 | DEBUGFUNC("e1000_copper_link_postconfig"); | |
76c224bc | 1677 | |
2d7edb92 MC |
1678 | if(hw->mac_type >= e1000_82544) { |
1679 | e1000_config_collision_dist(hw); | |
1680 | } else { | |
1681 | ret_val = e1000_config_mac_to_phy(hw); | |
1682 | if(ret_val) { | |
1683 | DEBUGOUT("Error configuring MAC to PHY settings\n"); | |
1684 | return ret_val; | |
1685 | } | |
1686 | } | |
1687 | ret_val = e1000_config_fc_after_link_up(hw); | |
1688 | if(ret_val) { | |
1689 | DEBUGOUT("Error Configuring Flow Control\n"); | |
1690 | return ret_val; | |
1691 | } | |
1692 | ||
1693 | /* Config DSP to improve Giga link quality */ | |
1694 | if(hw->phy_type == e1000_phy_igp) { | |
1695 | ret_val = e1000_config_dsp_after_link_change(hw, TRUE); | |
1696 | if(ret_val) { | |
1697 | DEBUGOUT("Error Configuring DSP after link up\n"); | |
1698 | return ret_val; | |
1699 | } | |
1700 | } | |
76c224bc | 1701 | |
2d7edb92 MC |
1702 | return E1000_SUCCESS; |
1703 | } | |
1704 | ||
1705 | /****************************************************************************** | |
1706 | * Detects which PHY is present and setup the speed and duplex | |
1707 | * | |
1708 | * hw - Struct containing variables accessed by shared code | |
1709 | ******************************************************************************/ | |
1710 | static int32_t | |
1711 | e1000_setup_copper_link(struct e1000_hw *hw) | |
1712 | { | |
1713 | int32_t ret_val; | |
1714 | uint16_t i; | |
1715 | uint16_t phy_data; | |
6418ecc6 | 1716 | uint16_t reg_data; |
2d7edb92 MC |
1717 | |
1718 | DEBUGFUNC("e1000_setup_copper_link"); | |
1719 | ||
1720 | /* Check if it is a valid PHY and set PHY mode if necessary. */ | |
1721 | ret_val = e1000_copper_link_preconfig(hw); | |
1722 | if(ret_val) | |
1723 | return ret_val; | |
1724 | ||
6418ecc6 JK |
1725 | switch (hw->mac_type) { |
1726 | case e1000_80003es2lan: | |
1727 | ret_val = e1000_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, | |
1728 | ®_data); | |
1729 | if (ret_val) | |
1730 | return ret_val; | |
1731 | reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; | |
1732 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, | |
1733 | reg_data); | |
1734 | if (ret_val) | |
1735 | return ret_val; | |
1736 | break; | |
1737 | default: | |
1738 | break; | |
1739 | } | |
1740 | ||
2d7edb92 MC |
1741 | if (hw->phy_type == e1000_phy_igp || |
1742 | hw->phy_type == e1000_phy_igp_2) { | |
1743 | ret_val = e1000_copper_link_igp_setup(hw); | |
1744 | if(ret_val) | |
1745 | return ret_val; | |
1746 | } else if (hw->phy_type == e1000_phy_m88) { | |
1747 | ret_val = e1000_copper_link_mgp_setup(hw); | |
1748 | if(ret_val) | |
1749 | return ret_val; | |
6418ecc6 JK |
1750 | } else if (hw->phy_type == e1000_phy_gg82563) { |
1751 | ret_val = e1000_copper_link_ggp_setup(hw); | |
1752 | if(ret_val) | |
1753 | return ret_val; | |
2d7edb92 MC |
1754 | } |
1755 | ||
1756 | if(hw->autoneg) { | |
76c224bc AK |
1757 | /* Setup autoneg and flow control advertisement |
1758 | * and perform autonegotiation */ | |
2d7edb92 MC |
1759 | ret_val = e1000_copper_link_autoneg(hw); |
1760 | if(ret_val) | |
76c224bc | 1761 | return ret_val; |
2d7edb92 MC |
1762 | } else { |
1763 | /* PHY will be set to 10H, 10F, 100H,or 100F | |
1764 | * depending on value from forced_speed_duplex. */ | |
1765 | DEBUGOUT("Forcing speed and duplex\n"); | |
1766 | ret_val = e1000_phy_force_speed_duplex(hw); | |
1767 | if(ret_val) { | |
1768 | DEBUGOUT("Error Forcing Speed and Duplex\n"); | |
1769 | return ret_val; | |
1770 | } | |
1771 | } | |
1772 | ||
1773 | /* Check link status. Wait up to 100 microseconds for link to become | |
1774 | * valid. | |
1775 | */ | |
1776 | for(i = 0; i < 10; i++) { | |
1777 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
1778 | if(ret_val) | |
1779 | return ret_val; | |
1780 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
1781 | if(ret_val) | |
1782 | return ret_val; | |
1783 | ||
1784 | if(phy_data & MII_SR_LINK_STATUS) { | |
1785 | /* Config the MAC and PHY after link is up */ | |
1786 | ret_val = e1000_copper_link_postconfig(hw); | |
1787 | if(ret_val) | |
1788 | return ret_val; | |
76c224bc | 1789 | |
2d7edb92 MC |
1790 | DEBUGOUT("Valid link established!!!\n"); |
1791 | return E1000_SUCCESS; | |
1792 | } | |
1793 | udelay(10); | |
1794 | } | |
1795 | ||
1796 | DEBUGOUT("Unable to establish link!!!\n"); | |
1797 | return E1000_SUCCESS; | |
1798 | } | |
1799 | ||
6418ecc6 JK |
1800 | /****************************************************************************** |
1801 | * Configure the MAC-to-PHY interface for 10/100Mbps | |
1802 | * | |
1803 | * hw - Struct containing variables accessed by shared code | |
1804 | ******************************************************************************/ | |
1805 | static int32_t | |
1806 | e1000_configure_kmrn_for_10_100(struct e1000_hw *hw) | |
1807 | { | |
1808 | int32_t ret_val = E1000_SUCCESS; | |
1809 | uint32_t tipg; | |
1810 | uint16_t reg_data; | |
1811 | ||
1812 | DEBUGFUNC("e1000_configure_kmrn_for_10_100"); | |
1813 | ||
1814 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
1815 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, | |
1816 | reg_data); | |
1817 | if (ret_val) | |
1818 | return ret_val; | |
1819 | ||
1820 | /* Configure Transmit Inter-Packet Gap */ | |
1821 | tipg = E1000_READ_REG(hw, TIPG); | |
1822 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1823 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; | |
1824 | E1000_WRITE_REG(hw, TIPG, tipg); | |
1825 | ||
1826 | return ret_val; | |
1827 | } | |
1828 | ||
1829 | static int32_t | |
1830 | e1000_configure_kmrn_for_1000(struct e1000_hw *hw) | |
1831 | { | |
1832 | int32_t ret_val = E1000_SUCCESS; | |
1833 | uint16_t reg_data; | |
1834 | uint32_t tipg; | |
1835 | ||
1836 | DEBUGFUNC("e1000_configure_kmrn_for_1000"); | |
1837 | ||
1838 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; | |
1839 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, | |
1840 | reg_data); | |
1841 | if (ret_val) | |
1842 | return ret_val; | |
1843 | ||
1844 | /* Configure Transmit Inter-Packet Gap */ | |
1845 | tipg = E1000_READ_REG(hw, TIPG); | |
1846 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1847 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; | |
1848 | E1000_WRITE_REG(hw, TIPG, tipg); | |
1849 | ||
1850 | return ret_val; | |
1851 | } | |
1852 | ||
2d7edb92 MC |
1853 | /****************************************************************************** |
1854 | * Configures PHY autoneg and flow control advertisement settings | |
1855 | * | |
1856 | * hw - Struct containing variables accessed by shared code | |
1857 | ******************************************************************************/ | |
1858 | int32_t | |
1859 | e1000_phy_setup_autoneg(struct e1000_hw *hw) | |
1860 | { | |
1861 | int32_t ret_val; | |
1862 | uint16_t mii_autoneg_adv_reg; | |
1863 | uint16_t mii_1000t_ctrl_reg; | |
1864 | ||
1865 | DEBUGFUNC("e1000_phy_setup_autoneg"); | |
1866 | ||
1867 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
1868 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); | |
1869 | if(ret_val) | |
1870 | return ret_val; | |
1871 | ||
96838a40 JB |
1872 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
1873 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | |
1874 | if(ret_val) | |
1875 | return ret_val; | |
2d7edb92 MC |
1876 | |
1877 | /* Need to parse both autoneg_advertised and fc and set up | |
1878 | * the appropriate PHY registers. First we will parse for | |
1da177e4 LT |
1879 | * autoneg_advertised software override. Since we can advertise |
1880 | * a plethora of combinations, we need to check each bit | |
1881 | * individually. | |
1882 | */ | |
1883 | ||
1884 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg | |
1885 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
1886 | * the 1000Base-T Control Register (Address 9). | |
1887 | */ | |
1888 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; | |
1889 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; | |
1890 | ||
1891 | DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); | |
1892 | ||
1893 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
1894 | if(hw->autoneg_advertised & ADVERTISE_10_HALF) { | |
1895 | DEBUGOUT("Advertise 10mb Half duplex\n"); | |
1896 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; | |
1897 | } | |
1898 | ||
1899 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
1900 | if(hw->autoneg_advertised & ADVERTISE_10_FULL) { | |
1901 | DEBUGOUT("Advertise 10mb Full duplex\n"); | |
1902 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; | |
1903 | } | |
1904 | ||
1905 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
1906 | if(hw->autoneg_advertised & ADVERTISE_100_HALF) { | |
1907 | DEBUGOUT("Advertise 100mb Half duplex\n"); | |
1908 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; | |
1909 | } | |
1910 | ||
1911 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
1912 | if(hw->autoneg_advertised & ADVERTISE_100_FULL) { | |
1913 | DEBUGOUT("Advertise 100mb Full duplex\n"); | |
1914 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; | |
1915 | } | |
1916 | ||
1917 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
1918 | if(hw->autoneg_advertised & ADVERTISE_1000_HALF) { | |
1919 | DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); | |
1920 | } | |
1921 | ||
1922 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
1923 | if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { | |
1924 | DEBUGOUT("Advertise 1000mb Full duplex\n"); | |
1925 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; | |
1926 | } | |
1927 | ||
1928 | /* Check for a software override of the flow control settings, and | |
1929 | * setup the PHY advertisement registers accordingly. If | |
1930 | * auto-negotiation is enabled, then software will have to set the | |
1931 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
1932 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. | |
1933 | * | |
1934 | * The possible values of the "fc" parameter are: | |
1935 | * 0: Flow control is completely disabled | |
1936 | * 1: Rx flow control is enabled (we can receive pause frames | |
1937 | * but not send pause frames). | |
1938 | * 2: Tx flow control is enabled (we can send pause frames | |
1939 | * but we do not support receiving pause frames). | |
1940 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
1941 | * other: No software override. The flow control configuration | |
1942 | * in the EEPROM is used. | |
1943 | */ | |
1944 | switch (hw->fc) { | |
1945 | case e1000_fc_none: /* 0 */ | |
1946 | /* Flow control (RX & TX) is completely disabled by a | |
1947 | * software over-ride. | |
1948 | */ | |
1949 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1950 | break; | |
1951 | case e1000_fc_rx_pause: /* 1 */ | |
1952 | /* RX Flow control is enabled, and TX Flow control is | |
1953 | * disabled, by a software over-ride. | |
1954 | */ | |
1955 | /* Since there really isn't a way to advertise that we are | |
1956 | * capable of RX Pause ONLY, we will advertise that we | |
1957 | * support both symmetric and asymmetric RX PAUSE. Later | |
1958 | * (in e1000_config_fc_after_link_up) we will disable the | |
1959 | *hw's ability to send PAUSE frames. | |
1960 | */ | |
1961 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1962 | break; | |
1963 | case e1000_fc_tx_pause: /* 2 */ | |
1964 | /* TX Flow control is enabled, and RX Flow control is | |
1965 | * disabled, by a software over-ride. | |
1966 | */ | |
1967 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
1968 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
1969 | break; | |
1970 | case e1000_fc_full: /* 3 */ | |
1971 | /* Flow control (both RX and TX) is enabled by a software | |
1972 | * over-ride. | |
1973 | */ | |
1974 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1975 | break; | |
1976 | default: | |
1977 | DEBUGOUT("Flow control param set incorrectly\n"); | |
1978 | return -E1000_ERR_CONFIG; | |
1979 | } | |
1980 | ||
1981 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); | |
1982 | if(ret_val) | |
1983 | return ret_val; | |
1984 | ||
1985 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); | |
1986 | ||
76c224bc | 1987 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
1da177e4 LT |
1988 | if(ret_val) |
1989 | return ret_val; | |
1990 | ||
1991 | return E1000_SUCCESS; | |
1992 | } | |
1993 | ||
1994 | /****************************************************************************** | |
1995 | * Force PHY speed and duplex settings to hw->forced_speed_duplex | |
1996 | * | |
1997 | * hw - Struct containing variables accessed by shared code | |
1998 | ******************************************************************************/ | |
1999 | static int32_t | |
2000 | e1000_phy_force_speed_duplex(struct e1000_hw *hw) | |
2001 | { | |
2002 | uint32_t ctrl; | |
2003 | int32_t ret_val; | |
2004 | uint16_t mii_ctrl_reg; | |
2005 | uint16_t mii_status_reg; | |
2006 | uint16_t phy_data; | |
2007 | uint16_t i; | |
2008 | ||
2009 | DEBUGFUNC("e1000_phy_force_speed_duplex"); | |
2010 | ||
2011 | /* Turn off Flow control if we are forcing speed and duplex. */ | |
2012 | hw->fc = e1000_fc_none; | |
2013 | ||
2014 | DEBUGOUT1("hw->fc = %d\n", hw->fc); | |
2015 | ||
2016 | /* Read the Device Control Register. */ | |
2017 | ctrl = E1000_READ_REG(hw, CTRL); | |
2018 | ||
2019 | /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ | |
2020 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
2021 | ctrl &= ~(DEVICE_SPEED_MASK); | |
2022 | ||
2023 | /* Clear the Auto Speed Detect Enable bit. */ | |
2024 | ctrl &= ~E1000_CTRL_ASDE; | |
2025 | ||
2026 | /* Read the MII Control Register. */ | |
2027 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); | |
2028 | if(ret_val) | |
2029 | return ret_val; | |
2030 | ||
2031 | /* We need to disable autoneg in order to force link and duplex. */ | |
2032 | ||
2033 | mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; | |
2034 | ||
2035 | /* Are we forcing Full or Half Duplex? */ | |
2036 | if(hw->forced_speed_duplex == e1000_100_full || | |
2037 | hw->forced_speed_duplex == e1000_10_full) { | |
2038 | /* We want to force full duplex so we SET the full duplex bits in the | |
2039 | * Device and MII Control Registers. | |
2040 | */ | |
2041 | ctrl |= E1000_CTRL_FD; | |
2042 | mii_ctrl_reg |= MII_CR_FULL_DUPLEX; | |
2043 | DEBUGOUT("Full Duplex\n"); | |
2044 | } else { | |
2045 | /* We want to force half duplex so we CLEAR the full duplex bits in | |
2046 | * the Device and MII Control Registers. | |
2047 | */ | |
2048 | ctrl &= ~E1000_CTRL_FD; | |
2049 | mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; | |
2050 | DEBUGOUT("Half Duplex\n"); | |
2051 | } | |
2052 | ||
2053 | /* Are we forcing 100Mbps??? */ | |
2054 | if(hw->forced_speed_duplex == e1000_100_full || | |
2055 | hw->forced_speed_duplex == e1000_100_half) { | |
2056 | /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ | |
2057 | ctrl |= E1000_CTRL_SPD_100; | |
2058 | mii_ctrl_reg |= MII_CR_SPEED_100; | |
2059 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
2060 | DEBUGOUT("Forcing 100mb "); | |
2061 | } else { | |
2062 | /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ | |
2063 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
2064 | mii_ctrl_reg |= MII_CR_SPEED_10; | |
2065 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
2066 | DEBUGOUT("Forcing 10mb "); | |
2067 | } | |
2068 | ||
2069 | e1000_config_collision_dist(hw); | |
2070 | ||
2071 | /* Write the configured values back to the Device Control Reg. */ | |
2072 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2073 | ||
6418ecc6 JK |
2074 | if ((hw->phy_type == e1000_phy_m88) || |
2075 | (hw->phy_type == e1000_phy_gg82563)) { | |
1da177e4 LT |
2076 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
2077 | if(ret_val) | |
2078 | return ret_val; | |
2079 | ||
2080 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
2081 | * forced whenever speed are duplex are forced. | |
2082 | */ | |
2083 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
2084 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
2085 | if(ret_val) | |
2086 | return ret_val; | |
2087 | ||
2088 | DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); | |
2089 | ||
2090 | /* Need to reset the PHY or these changes will be ignored */ | |
2091 | mii_ctrl_reg |= MII_CR_RESET; | |
2092 | } else { | |
2093 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
2094 | * forced whenever speed or duplex are forced. | |
2095 | */ | |
2096 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
2097 | if(ret_val) | |
2098 | return ret_val; | |
2099 | ||
2100 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
2101 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
2102 | ||
2103 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
2104 | if(ret_val) | |
2105 | return ret_val; | |
2106 | } | |
2107 | ||
2108 | /* Write back the modified PHY MII control register. */ | |
2109 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); | |
2110 | if(ret_val) | |
2111 | return ret_val; | |
2112 | ||
2113 | udelay(1); | |
2114 | ||
2115 | /* The wait_autoneg_complete flag may be a little misleading here. | |
2116 | * Since we are forcing speed and duplex, Auto-Neg is not enabled. | |
2117 | * But we do want to delay for a period while forcing only so we | |
2118 | * don't generate false No Link messages. So we will wait here | |
2119 | * only if the user has set wait_autoneg_complete to 1, which is | |
2120 | * the default. | |
2121 | */ | |
2122 | if(hw->wait_autoneg_complete) { | |
2123 | /* We will wait for autoneg to complete. */ | |
2124 | DEBUGOUT("Waiting for forced speed/duplex link.\n"); | |
2125 | mii_status_reg = 0; | |
2126 | ||
2127 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ | |
2128 | for(i = PHY_FORCE_TIME; i > 0; i--) { | |
2129 | /* Read the MII Status Register and wait for Auto-Neg Complete bit | |
2130 | * to be set. | |
2131 | */ | |
2132 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
2133 | if(ret_val) | |
2134 | return ret_val; | |
2135 | ||
2136 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
2137 | if(ret_val) | |
2138 | return ret_val; | |
2139 | ||
2140 | if(mii_status_reg & MII_SR_LINK_STATUS) break; | |
2141 | msec_delay(100); | |
2142 | } | |
2143 | if((i == 0) && | |
6418ecc6 JK |
2144 | ((hw->phy_type == e1000_phy_m88) || |
2145 | (hw->phy_type == e1000_phy_gg82563))) { | |
1da177e4 LT |
2146 | /* We didn't get link. Reset the DSP and wait again for link. */ |
2147 | ret_val = e1000_phy_reset_dsp(hw); | |
2148 | if(ret_val) { | |
2149 | DEBUGOUT("Error Resetting PHY DSP\n"); | |
2150 | return ret_val; | |
2151 | } | |
2152 | } | |
2153 | /* This loop will early-out if the link condition has been met. */ | |
2154 | for(i = PHY_FORCE_TIME; i > 0; i--) { | |
2155 | if(mii_status_reg & MII_SR_LINK_STATUS) break; | |
2156 | msec_delay(100); | |
2157 | /* Read the MII Status Register and wait for Auto-Neg Complete bit | |
2158 | * to be set. | |
2159 | */ | |
2160 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
2161 | if(ret_val) | |
2162 | return ret_val; | |
2163 | ||
2164 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
2165 | if(ret_val) | |
2166 | return ret_val; | |
2167 | } | |
2168 | } | |
2169 | ||
2170 | if (hw->phy_type == e1000_phy_m88) { | |
2171 | /* Because we reset the PHY above, we need to re-force TX_CLK in the | |
2172 | * Extended PHY Specific Control Register to 25MHz clock. This value | |
2173 | * defaults back to a 2.5MHz clock when the PHY is reset. | |
2174 | */ | |
2175 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
2176 | if(ret_val) | |
2177 | return ret_val; | |
2178 | ||
2179 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
2180 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
2181 | if(ret_val) | |
2182 | return ret_val; | |
2183 | ||
2184 | /* In addition, because of the s/w reset above, we need to enable CRS on | |
2185 | * TX. This must be set for both full and half duplex operation. | |
2186 | */ | |
2187 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
2188 | if(ret_val) | |
2189 | return ret_val; | |
2190 | ||
2191 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
2192 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
2193 | if(ret_val) | |
2194 | return ret_val; | |
2195 | ||
2196 | if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && | |
2197 | (!hw->autoneg) && | |
2198 | (hw->forced_speed_duplex == e1000_10_full || | |
2199 | hw->forced_speed_duplex == e1000_10_half)) { | |
2200 | ret_val = e1000_polarity_reversal_workaround(hw); | |
2201 | if(ret_val) | |
2202 | return ret_val; | |
2203 | } | |
6418ecc6 JK |
2204 | } else if (hw->phy_type == e1000_phy_gg82563) { |
2205 | /* The TX_CLK of the Extended PHY Specific Control Register defaults | |
2206 | * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if | |
2207 | * we're not in a forced 10/duplex configuration. */ | |
2208 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
2209 | if (ret_val) | |
2210 | return ret_val; | |
2211 | ||
2212 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; | |
2213 | if ((hw->forced_speed_duplex == e1000_10_full) || | |
2214 | (hw->forced_speed_duplex == e1000_10_half)) | |
2215 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; | |
2216 | else | |
2217 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; | |
2218 | ||
2219 | /* Also due to the reset, we need to enable CRS on Tx. */ | |
2220 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
2221 | ||
2222 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
2223 | if (ret_val) | |
2224 | return ret_val; | |
1da177e4 LT |
2225 | } |
2226 | return E1000_SUCCESS; | |
2227 | } | |
2228 | ||
2229 | /****************************************************************************** | |
2230 | * Sets the collision distance in the Transmit Control register | |
2231 | * | |
2232 | * hw - Struct containing variables accessed by shared code | |
2233 | * | |
2234 | * Link should have been established previously. Reads the speed and duplex | |
2235 | * information from the Device Status register. | |
2236 | ******************************************************************************/ | |
2237 | void | |
2238 | e1000_config_collision_dist(struct e1000_hw *hw) | |
2239 | { | |
0fadb059 | 2240 | uint32_t tctl, coll_dist; |
1da177e4 LT |
2241 | |
2242 | DEBUGFUNC("e1000_config_collision_dist"); | |
2243 | ||
0fadb059 JK |
2244 | if (hw->mac_type < e1000_82543) |
2245 | coll_dist = E1000_COLLISION_DISTANCE_82542; | |
2246 | else | |
2247 | coll_dist = E1000_COLLISION_DISTANCE; | |
2248 | ||
1da177e4 LT |
2249 | tctl = E1000_READ_REG(hw, TCTL); |
2250 | ||
2251 | tctl &= ~E1000_TCTL_COLD; | |
0fadb059 | 2252 | tctl |= coll_dist << E1000_COLD_SHIFT; |
1da177e4 LT |
2253 | |
2254 | E1000_WRITE_REG(hw, TCTL, tctl); | |
2255 | E1000_WRITE_FLUSH(hw); | |
2256 | } | |
2257 | ||
2258 | /****************************************************************************** | |
2259 | * Sets MAC speed and duplex settings to reflect the those in the PHY | |
2260 | * | |
2261 | * hw - Struct containing variables accessed by shared code | |
2262 | * mii_reg - data to write to the MII control register | |
2263 | * | |
2264 | * The contents of the PHY register containing the needed information need to | |
2265 | * be passed in. | |
2266 | ******************************************************************************/ | |
2267 | static int32_t | |
2268 | e1000_config_mac_to_phy(struct e1000_hw *hw) | |
2269 | { | |
2270 | uint32_t ctrl; | |
2271 | int32_t ret_val; | |
2272 | uint16_t phy_data; | |
2273 | ||
2274 | DEBUGFUNC("e1000_config_mac_to_phy"); | |
2275 | ||
76c224bc | 2276 | /* 82544 or newer MAC, Auto Speed Detection takes care of |
2d7edb92 MC |
2277 | * MAC speed/duplex configuration.*/ |
2278 | if (hw->mac_type >= e1000_82544) | |
2279 | return E1000_SUCCESS; | |
2280 | ||
1da177e4 LT |
2281 | /* Read the Device Control Register and set the bits to Force Speed |
2282 | * and Duplex. | |
2283 | */ | |
2284 | ctrl = E1000_READ_REG(hw, CTRL); | |
2285 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
2286 | ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); | |
2287 | ||
2288 | /* Set up duplex in the Device Control and Transmit Control | |
2289 | * registers depending on negotiated values. | |
2290 | */ | |
2d7edb92 MC |
2291 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
2292 | if(ret_val) | |
2293 | return ret_val; | |
1da177e4 | 2294 | |
76c224bc | 2295 | if(phy_data & M88E1000_PSSR_DPLX) |
2d7edb92 | 2296 | ctrl |= E1000_CTRL_FD; |
76c224bc | 2297 | else |
2d7edb92 | 2298 | ctrl &= ~E1000_CTRL_FD; |
1da177e4 | 2299 | |
2d7edb92 | 2300 | e1000_config_collision_dist(hw); |
1da177e4 | 2301 | |
2d7edb92 MC |
2302 | /* Set up speed in the Device Control register depending on |
2303 | * negotiated values. | |
2304 | */ | |
2305 | if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) | |
2306 | ctrl |= E1000_CTRL_SPD_1000; | |
2307 | else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) | |
2308 | ctrl |= E1000_CTRL_SPD_100; | |
1da177e4 | 2309 | |
1da177e4 LT |
2310 | /* Write the configured values back to the Device Control Reg. */ |
2311 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2312 | return E1000_SUCCESS; | |
2313 | } | |
2314 | ||
2315 | /****************************************************************************** | |
2316 | * Forces the MAC's flow control settings. | |
2317 | * | |
2318 | * hw - Struct containing variables accessed by shared code | |
2319 | * | |
2320 | * Sets the TFCE and RFCE bits in the device control register to reflect | |
2321 | * the adapter settings. TFCE and RFCE need to be explicitly set by | |
2322 | * software when a Copper PHY is used because autonegotiation is managed | |
2323 | * by the PHY rather than the MAC. Software must also configure these | |
2324 | * bits when link is forced on a fiber connection. | |
2325 | *****************************************************************************/ | |
2326 | int32_t | |
2327 | e1000_force_mac_fc(struct e1000_hw *hw) | |
2328 | { | |
2329 | uint32_t ctrl; | |
2330 | ||
2331 | DEBUGFUNC("e1000_force_mac_fc"); | |
2332 | ||
2333 | /* Get the current configuration of the Device Control Register */ | |
2334 | ctrl = E1000_READ_REG(hw, CTRL); | |
2335 | ||
2336 | /* Because we didn't get link via the internal auto-negotiation | |
2337 | * mechanism (we either forced link or we got link via PHY | |
2338 | * auto-neg), we have to manually enable/disable transmit an | |
2339 | * receive flow control. | |
2340 | * | |
2341 | * The "Case" statement below enables/disable flow control | |
2342 | * according to the "hw->fc" parameter. | |
2343 | * | |
2344 | * The possible values of the "fc" parameter are: | |
2345 | * 0: Flow control is completely disabled | |
2346 | * 1: Rx flow control is enabled (we can receive pause | |
2347 | * frames but not send pause frames). | |
2348 | * 2: Tx flow control is enabled (we can send pause frames | |
2349 | * frames but we do not receive pause frames). | |
2350 | * 3: Both Rx and TX flow control (symmetric) is enabled. | |
2351 | * other: No other values should be possible at this point. | |
2352 | */ | |
2353 | ||
2354 | switch (hw->fc) { | |
2355 | case e1000_fc_none: | |
2356 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); | |
2357 | break; | |
2358 | case e1000_fc_rx_pause: | |
2359 | ctrl &= (~E1000_CTRL_TFCE); | |
2360 | ctrl |= E1000_CTRL_RFCE; | |
2361 | break; | |
2362 | case e1000_fc_tx_pause: | |
2363 | ctrl &= (~E1000_CTRL_RFCE); | |
2364 | ctrl |= E1000_CTRL_TFCE; | |
2365 | break; | |
2366 | case e1000_fc_full: | |
2367 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); | |
2368 | break; | |
2369 | default: | |
2370 | DEBUGOUT("Flow control param set incorrectly\n"); | |
2371 | return -E1000_ERR_CONFIG; | |
2372 | } | |
2373 | ||
2374 | /* Disable TX Flow Control for 82542 (rev 2.0) */ | |
2375 | if(hw->mac_type == e1000_82542_rev2_0) | |
2376 | ctrl &= (~E1000_CTRL_TFCE); | |
2377 | ||
2378 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2379 | return E1000_SUCCESS; | |
2380 | } | |
2381 | ||
2382 | /****************************************************************************** | |
2383 | * Configures flow control settings after link is established | |
2384 | * | |
2385 | * hw - Struct containing variables accessed by shared code | |
2386 | * | |
2387 | * Should be called immediately after a valid link has been established. | |
2388 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode | |
2389 | * and autonegotiation is enabled, the MAC flow control settings will be set | |
2390 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE | |
2391 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. | |
2392 | *****************************************************************************/ | |
3ad2cc67 | 2393 | static int32_t |
1da177e4 LT |
2394 | e1000_config_fc_after_link_up(struct e1000_hw *hw) |
2395 | { | |
2396 | int32_t ret_val; | |
2397 | uint16_t mii_status_reg; | |
2398 | uint16_t mii_nway_adv_reg; | |
2399 | uint16_t mii_nway_lp_ability_reg; | |
2400 | uint16_t speed; | |
2401 | uint16_t duplex; | |
2402 | ||
2403 | DEBUGFUNC("e1000_config_fc_after_link_up"); | |
2404 | ||
2405 | /* Check for the case where we have fiber media and auto-neg failed | |
2406 | * so we had to force link. In this case, we need to force the | |
2407 | * configuration of the MAC to match the "fc" parameter. | |
2408 | */ | |
2409 | if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || | |
2410 | ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) || | |
2411 | ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { | |
2412 | ret_val = e1000_force_mac_fc(hw); | |
2413 | if(ret_val) { | |
2414 | DEBUGOUT("Error forcing flow control settings\n"); | |
2415 | return ret_val; | |
2416 | } | |
2417 | } | |
2418 | ||
2419 | /* Check for the case where we have copper media and auto-neg is | |
2420 | * enabled. In this case, we need to check and see if Auto-Neg | |
2421 | * has completed, and if so, how the PHY and link partner has | |
2422 | * flow control configured. | |
2423 | */ | |
2424 | if((hw->media_type == e1000_media_type_copper) && hw->autoneg) { | |
2425 | /* Read the MII Status Register and check to see if AutoNeg | |
2426 | * has completed. We read this twice because this reg has | |
2427 | * some "sticky" (latched) bits. | |
2428 | */ | |
2429 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
2430 | if(ret_val) | |
2431 | return ret_val; | |
2432 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
2433 | if(ret_val) | |
2434 | return ret_val; | |
2435 | ||
2436 | if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) { | |
2437 | /* The AutoNeg process has completed, so we now need to | |
2438 | * read both the Auto Negotiation Advertisement Register | |
2439 | * (Address 4) and the Auto_Negotiation Base Page Ability | |
2440 | * Register (Address 5) to determine how flow control was | |
2441 | * negotiated. | |
2442 | */ | |
2443 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, | |
2444 | &mii_nway_adv_reg); | |
2445 | if(ret_val) | |
2446 | return ret_val; | |
2447 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, | |
2448 | &mii_nway_lp_ability_reg); | |
2449 | if(ret_val) | |
2450 | return ret_val; | |
2451 | ||
2452 | /* Two bits in the Auto Negotiation Advertisement Register | |
2453 | * (Address 4) and two bits in the Auto Negotiation Base | |
2454 | * Page Ability Register (Address 5) determine flow control | |
2455 | * for both the PHY and the link partner. The following | |
2456 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, | |
2457 | * 1999, describes these PAUSE resolution bits and how flow | |
2458 | * control is determined based upon these settings. | |
2459 | * NOTE: DC = Don't Care | |
2460 | * | |
2461 | * LOCAL DEVICE | LINK PARTNER | |
2462 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution | |
2463 | *-------|---------|-------|---------|-------------------- | |
2464 | * 0 | 0 | DC | DC | e1000_fc_none | |
2465 | * 0 | 1 | 0 | DC | e1000_fc_none | |
2466 | * 0 | 1 | 1 | 0 | e1000_fc_none | |
2467 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
2468 | * 1 | 0 | 0 | DC | e1000_fc_none | |
2469 | * 1 | DC | 1 | DC | e1000_fc_full | |
2470 | * 1 | 1 | 0 | 0 | e1000_fc_none | |
2471 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
2472 | * | |
2473 | */ | |
2474 | /* Are both PAUSE bits set to 1? If so, this implies | |
2475 | * Symmetric Flow Control is enabled at both ends. The | |
2476 | * ASM_DIR bits are irrelevant per the spec. | |
2477 | * | |
2478 | * For Symmetric Flow Control: | |
2479 | * | |
2480 | * LOCAL DEVICE | LINK PARTNER | |
2481 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2482 | *-------|---------|-------|---------|-------------------- | |
2483 | * 1 | DC | 1 | DC | e1000_fc_full | |
2484 | * | |
2485 | */ | |
2486 | if((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
2487 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { | |
2488 | /* Now we need to check if the user selected RX ONLY | |
2489 | * of pause frames. In this case, we had to advertise | |
2490 | * FULL flow control because we could not advertise RX | |
2491 | * ONLY. Hence, we must now check to see if we need to | |
2492 | * turn OFF the TRANSMISSION of PAUSE frames. | |
2493 | */ | |
2494 | if(hw->original_fc == e1000_fc_full) { | |
2495 | hw->fc = e1000_fc_full; | |
a42a507c | 2496 | DEBUGOUT("Flow Control = FULL.\n"); |
1da177e4 LT |
2497 | } else { |
2498 | hw->fc = e1000_fc_rx_pause; | |
a42a507c | 2499 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
1da177e4 LT |
2500 | } |
2501 | } | |
2502 | /* For receiving PAUSE frames ONLY. | |
2503 | * | |
2504 | * LOCAL DEVICE | LINK PARTNER | |
2505 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2506 | *-------|---------|-------|---------|-------------------- | |
2507 | * 0 | 1 | 1 | 1 | e1000_fc_tx_pause | |
2508 | * | |
2509 | */ | |
2510 | else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
2511 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
2512 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
2513 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
2514 | hw->fc = e1000_fc_tx_pause; | |
a42a507c | 2515 | DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); |
1da177e4 LT |
2516 | } |
2517 | /* For transmitting PAUSE frames ONLY. | |
2518 | * | |
2519 | * LOCAL DEVICE | LINK PARTNER | |
2520 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result | |
2521 | *-------|---------|-------|---------|-------------------- | |
2522 | * 1 | 1 | 0 | 1 | e1000_fc_rx_pause | |
2523 | * | |
2524 | */ | |
2525 | else if((mii_nway_adv_reg & NWAY_AR_PAUSE) && | |
2526 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && | |
2527 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && | |
2528 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | |
2529 | hw->fc = e1000_fc_rx_pause; | |
a42a507c | 2530 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
1da177e4 LT |
2531 | } |
2532 | /* Per the IEEE spec, at this point flow control should be | |
2533 | * disabled. However, we want to consider that we could | |
2534 | * be connected to a legacy switch that doesn't advertise | |
2535 | * desired flow control, but can be forced on the link | |
2536 | * partner. So if we advertised no flow control, that is | |
2537 | * what we will resolve to. If we advertised some kind of | |
2538 | * receive capability (Rx Pause Only or Full Flow Control) | |
2539 | * and the link partner advertised none, we will configure | |
2540 | * ourselves to enable Rx Flow Control only. We can do | |
2541 | * this safely for two reasons: If the link partner really | |
2542 | * didn't want flow control enabled, and we enable Rx, no | |
2543 | * harm done since we won't be receiving any PAUSE frames | |
2544 | * anyway. If the intent on the link partner was to have | |
2545 | * flow control enabled, then by us enabling RX only, we | |
2546 | * can at least receive pause frames and process them. | |
2547 | * This is a good idea because in most cases, since we are | |
2548 | * predominantly a server NIC, more times than not we will | |
2549 | * be asked to delay transmission of packets than asking | |
2550 | * our link partner to pause transmission of frames. | |
2551 | */ | |
2552 | else if((hw->original_fc == e1000_fc_none || | |
2553 | hw->original_fc == e1000_fc_tx_pause) || | |
2554 | hw->fc_strict_ieee) { | |
2555 | hw->fc = e1000_fc_none; | |
a42a507c | 2556 | DEBUGOUT("Flow Control = NONE.\n"); |
1da177e4 LT |
2557 | } else { |
2558 | hw->fc = e1000_fc_rx_pause; | |
a42a507c | 2559 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
1da177e4 LT |
2560 | } |
2561 | ||
2562 | /* Now we need to do one last check... If we auto- | |
2563 | * negotiated to HALF DUPLEX, flow control should not be | |
2564 | * enabled per IEEE 802.3 spec. | |
2565 | */ | |
2566 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
2567 | if(ret_val) { | |
2568 | DEBUGOUT("Error getting link speed and duplex\n"); | |
2569 | return ret_val; | |
2570 | } | |
2571 | ||
2572 | if(duplex == HALF_DUPLEX) | |
2573 | hw->fc = e1000_fc_none; | |
2574 | ||
2575 | /* Now we call a subroutine to actually force the MAC | |
2576 | * controller to use the correct flow control settings. | |
2577 | */ | |
2578 | ret_val = e1000_force_mac_fc(hw); | |
2579 | if(ret_val) { | |
2580 | DEBUGOUT("Error forcing flow control settings\n"); | |
2581 | return ret_val; | |
2582 | } | |
2583 | } else { | |
a42a507c | 2584 | DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); |
1da177e4 LT |
2585 | } |
2586 | } | |
2587 | return E1000_SUCCESS; | |
2588 | } | |
2589 | ||
2590 | /****************************************************************************** | |
2591 | * Checks to see if the link status of the hardware has changed. | |
2592 | * | |
2593 | * hw - Struct containing variables accessed by shared code | |
2594 | * | |
2595 | * Called by any function that needs to check the link status of the adapter. | |
2596 | *****************************************************************************/ | |
2597 | int32_t | |
2598 | e1000_check_for_link(struct e1000_hw *hw) | |
2599 | { | |
2600 | uint32_t rxcw = 0; | |
2601 | uint32_t ctrl; | |
2602 | uint32_t status; | |
2603 | uint32_t rctl; | |
2604 | uint32_t icr; | |
2605 | uint32_t signal = 0; | |
2606 | int32_t ret_val; | |
2607 | uint16_t phy_data; | |
2608 | ||
2609 | DEBUGFUNC("e1000_check_for_link"); | |
2610 | ||
2611 | ctrl = E1000_READ_REG(hw, CTRL); | |
2612 | status = E1000_READ_REG(hw, STATUS); | |
2613 | ||
2614 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be | |
2615 | * set when the optics detect a signal. On older adapters, it will be | |
2616 | * cleared when there is a signal. This applies to fiber media only. | |
2617 | */ | |
2618 | if((hw->media_type == e1000_media_type_fiber) || | |
2619 | (hw->media_type == e1000_media_type_internal_serdes)) { | |
2620 | rxcw = E1000_READ_REG(hw, RXCW); | |
2621 | ||
2622 | if(hw->media_type == e1000_media_type_fiber) { | |
2623 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; | |
2624 | if(status & E1000_STATUS_LU) | |
2625 | hw->get_link_status = FALSE; | |
2626 | } | |
2627 | } | |
2628 | ||
2629 | /* If we have a copper PHY then we only want to go out to the PHY | |
2630 | * registers to see if Auto-Neg has completed and/or if our link | |
2631 | * status has changed. The get_link_status flag will be set if we | |
2632 | * receive a Link Status Change interrupt or we have Rx Sequence | |
2633 | * Errors. | |
2634 | */ | |
2635 | if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { | |
2636 | /* First we want to see if the MII Status Register reports | |
2637 | * link. If so, then we want to get the current speed/duplex | |
2638 | * of the PHY. | |
2639 | * Read the register twice since the link bit is sticky. | |
2640 | */ | |
2641 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
2642 | if(ret_val) | |
2643 | return ret_val; | |
2644 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
2645 | if(ret_val) | |
2646 | return ret_val; | |
2647 | ||
2648 | if(phy_data & MII_SR_LINK_STATUS) { | |
2649 | hw->get_link_status = FALSE; | |
2650 | /* Check if there was DownShift, must be checked immediately after | |
2651 | * link-up */ | |
2652 | e1000_check_downshift(hw); | |
2653 | ||
2654 | /* If we are on 82544 or 82543 silicon and speed/duplex | |
2655 | * are forced to 10H or 10F, then we will implement the polarity | |
2656 | * reversal workaround. We disable interrupts first, and upon | |
2657 | * returning, place the devices interrupt state to its previous | |
2658 | * value except for the link status change interrupt which will | |
2659 | * happen due to the execution of this workaround. | |
2660 | */ | |
2661 | ||
2662 | if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && | |
2663 | (!hw->autoneg) && | |
2664 | (hw->forced_speed_duplex == e1000_10_full || | |
2665 | hw->forced_speed_duplex == e1000_10_half)) { | |
2666 | E1000_WRITE_REG(hw, IMC, 0xffffffff); | |
2667 | ret_val = e1000_polarity_reversal_workaround(hw); | |
2668 | icr = E1000_READ_REG(hw, ICR); | |
2669 | E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); | |
2670 | E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); | |
2671 | } | |
2672 | ||
2673 | } else { | |
2674 | /* No link detected */ | |
2675 | e1000_config_dsp_after_link_change(hw, FALSE); | |
2676 | return 0; | |
2677 | } | |
2678 | ||
2679 | /* If we are forcing speed/duplex, then we simply return since | |
2680 | * we have already determined whether we have link or not. | |
2681 | */ | |
2682 | if(!hw->autoneg) return -E1000_ERR_CONFIG; | |
2683 | ||
2684 | /* optimize the dsp settings for the igp phy */ | |
2685 | e1000_config_dsp_after_link_change(hw, TRUE); | |
2686 | ||
2687 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we | |
2688 | * have Si on board that is 82544 or newer, Auto | |
2689 | * Speed Detection takes care of MAC speed/duplex | |
2690 | * configuration. So we only need to configure Collision | |
2691 | * Distance in the MAC. Otherwise, we need to force | |
2692 | * speed/duplex on the MAC to the current PHY speed/duplex | |
2693 | * settings. | |
2694 | */ | |
2695 | if(hw->mac_type >= e1000_82544) | |
2696 | e1000_config_collision_dist(hw); | |
2697 | else { | |
2698 | ret_val = e1000_config_mac_to_phy(hw); | |
2699 | if(ret_val) { | |
2700 | DEBUGOUT("Error configuring MAC to PHY settings\n"); | |
2701 | return ret_val; | |
2702 | } | |
2703 | } | |
2704 | ||
2705 | /* Configure Flow Control now that Auto-Neg has completed. First, we | |
2706 | * need to restore the desired flow control settings because we may | |
2707 | * have had to re-autoneg with a different link partner. | |
2708 | */ | |
2709 | ret_val = e1000_config_fc_after_link_up(hw); | |
2710 | if(ret_val) { | |
2711 | DEBUGOUT("Error configuring flow control\n"); | |
2712 | return ret_val; | |
2713 | } | |
2714 | ||
2715 | /* At this point we know that we are on copper and we have | |
2716 | * auto-negotiated link. These are conditions for checking the link | |
2717 | * partner capability register. We use the link speed to determine if | |
2718 | * TBI compatibility needs to be turned on or off. If the link is not | |
2719 | * at gigabit speed, then TBI compatibility is not needed. If we are | |
2720 | * at gigabit speed, we turn on TBI compatibility. | |
2721 | */ | |
2722 | if(hw->tbi_compatibility_en) { | |
2723 | uint16_t speed, duplex; | |
2724 | e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
2725 | if(speed != SPEED_1000) { | |
2726 | /* If link speed is not set to gigabit speed, we do not need | |
2727 | * to enable TBI compatibility. | |
2728 | */ | |
2729 | if(hw->tbi_compatibility_on) { | |
2730 | /* If we previously were in the mode, turn it off. */ | |
2731 | rctl = E1000_READ_REG(hw, RCTL); | |
2732 | rctl &= ~E1000_RCTL_SBP; | |
2733 | E1000_WRITE_REG(hw, RCTL, rctl); | |
2734 | hw->tbi_compatibility_on = FALSE; | |
2735 | } | |
2736 | } else { | |
2737 | /* If TBI compatibility is was previously off, turn it on. For | |
2738 | * compatibility with a TBI link partner, we will store bad | |
2739 | * packets. Some frames have an additional byte on the end and | |
2740 | * will look like CRC errors to to the hardware. | |
2741 | */ | |
2742 | if(!hw->tbi_compatibility_on) { | |
2743 | hw->tbi_compatibility_on = TRUE; | |
2744 | rctl = E1000_READ_REG(hw, RCTL); | |
2745 | rctl |= E1000_RCTL_SBP; | |
2746 | E1000_WRITE_REG(hw, RCTL, rctl); | |
2747 | } | |
2748 | } | |
2749 | } | |
2750 | } | |
2751 | /* If we don't have link (auto-negotiation failed or link partner cannot | |
2752 | * auto-negotiate), the cable is plugged in (we have signal), and our | |
2753 | * link partner is not trying to auto-negotiate with us (we are receiving | |
2754 | * idles or data), we need to force link up. We also need to give | |
2755 | * auto-negotiation time to complete, in case the cable was just plugged | |
2756 | * in. The autoneg_failed flag does this. | |
2757 | */ | |
2758 | else if((((hw->media_type == e1000_media_type_fiber) && | |
2759 | ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || | |
2760 | (hw->media_type == e1000_media_type_internal_serdes)) && | |
2761 | (!(status & E1000_STATUS_LU)) && | |
2762 | (!(rxcw & E1000_RXCW_C))) { | |
2763 | if(hw->autoneg_failed == 0) { | |
2764 | hw->autoneg_failed = 1; | |
2765 | return 0; | |
2766 | } | |
a42a507c | 2767 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); |
1da177e4 LT |
2768 | |
2769 | /* Disable auto-negotiation in the TXCW register */ | |
2770 | E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); | |
2771 | ||
2772 | /* Force link-up and also force full-duplex. */ | |
2773 | ctrl = E1000_READ_REG(hw, CTRL); | |
2774 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
2775 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
2776 | ||
2777 | /* Configure Flow Control after forcing link up. */ | |
2778 | ret_val = e1000_config_fc_after_link_up(hw); | |
2779 | if(ret_val) { | |
2780 | DEBUGOUT("Error configuring flow control\n"); | |
2781 | return ret_val; | |
2782 | } | |
2783 | } | |
2784 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable | |
2785 | * auto-negotiation in the TXCW register and disable forced link in the | |
2786 | * Device Control register in an attempt to auto-negotiate with our link | |
2787 | * partner. | |
2788 | */ | |
2789 | else if(((hw->media_type == e1000_media_type_fiber) || | |
2790 | (hw->media_type == e1000_media_type_internal_serdes)) && | |
2791 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { | |
a42a507c | 2792 | DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
1da177e4 LT |
2793 | E1000_WRITE_REG(hw, TXCW, hw->txcw); |
2794 | E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); | |
2795 | ||
2796 | hw->serdes_link_down = FALSE; | |
2797 | } | |
2798 | /* If we force link for non-auto-negotiation switch, check link status | |
2799 | * based on MAC synchronization for internal serdes media type. | |
2800 | */ | |
2801 | else if((hw->media_type == e1000_media_type_internal_serdes) && | |
2802 | !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { | |
2803 | /* SYNCH bit and IV bit are sticky. */ | |
2804 | udelay(10); | |
2805 | if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { | |
2806 | if(!(rxcw & E1000_RXCW_IV)) { | |
2807 | hw->serdes_link_down = FALSE; | |
2808 | DEBUGOUT("SERDES: Link is up.\n"); | |
2809 | } | |
2810 | } else { | |
2811 | hw->serdes_link_down = TRUE; | |
2812 | DEBUGOUT("SERDES: Link is down.\n"); | |
2813 | } | |
2814 | } | |
2815 | if((hw->media_type == e1000_media_type_internal_serdes) && | |
2816 | (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { | |
2817 | hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); | |
2818 | } | |
2819 | return E1000_SUCCESS; | |
2820 | } | |
2821 | ||
2822 | /****************************************************************************** | |
2823 | * Detects the current speed and duplex settings of the hardware. | |
2824 | * | |
2825 | * hw - Struct containing variables accessed by shared code | |
2826 | * speed - Speed of the connection | |
2827 | * duplex - Duplex setting of the connection | |
2828 | *****************************************************************************/ | |
2829 | int32_t | |
2830 | e1000_get_speed_and_duplex(struct e1000_hw *hw, | |
2831 | uint16_t *speed, | |
2832 | uint16_t *duplex) | |
2833 | { | |
2834 | uint32_t status; | |
2835 | int32_t ret_val; | |
2836 | uint16_t phy_data; | |
2837 | ||
2838 | DEBUGFUNC("e1000_get_speed_and_duplex"); | |
2839 | ||
2840 | if(hw->mac_type >= e1000_82543) { | |
2841 | status = E1000_READ_REG(hw, STATUS); | |
2842 | if(status & E1000_STATUS_SPEED_1000) { | |
2843 | *speed = SPEED_1000; | |
2844 | DEBUGOUT("1000 Mbs, "); | |
2845 | } else if(status & E1000_STATUS_SPEED_100) { | |
2846 | *speed = SPEED_100; | |
2847 | DEBUGOUT("100 Mbs, "); | |
2848 | } else { | |
2849 | *speed = SPEED_10; | |
2850 | DEBUGOUT("10 Mbs, "); | |
2851 | } | |
2852 | ||
2853 | if(status & E1000_STATUS_FD) { | |
2854 | *duplex = FULL_DUPLEX; | |
a42a507c | 2855 | DEBUGOUT("Full Duplex\n"); |
1da177e4 LT |
2856 | } else { |
2857 | *duplex = HALF_DUPLEX; | |
a42a507c | 2858 | DEBUGOUT(" Half Duplex\n"); |
1da177e4 LT |
2859 | } |
2860 | } else { | |
a42a507c | 2861 | DEBUGOUT("1000 Mbs, Full Duplex\n"); |
1da177e4 LT |
2862 | *speed = SPEED_1000; |
2863 | *duplex = FULL_DUPLEX; | |
2864 | } | |
2865 | ||
2866 | /* IGP01 PHY may advertise full duplex operation after speed downgrade even | |
2867 | * if it is operating at half duplex. Here we set the duplex settings to | |
2868 | * match the duplex in the link partner's capabilities. | |
2869 | */ | |
2870 | if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { | |
2871 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); | |
2872 | if(ret_val) | |
2873 | return ret_val; | |
2874 | ||
2875 | if(!(phy_data & NWAY_ER_LP_NWAY_CAPS)) | |
2876 | *duplex = HALF_DUPLEX; | |
2877 | else { | |
2878 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); | |
2879 | if(ret_val) | |
2880 | return ret_val; | |
2881 | if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || | |
2882 | (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) | |
2883 | *duplex = HALF_DUPLEX; | |
2884 | } | |
2885 | } | |
2886 | ||
76c224bc | 2887 | if ((hw->mac_type == e1000_80003es2lan) && |
6418ecc6 JK |
2888 | (hw->media_type == e1000_media_type_copper)) { |
2889 | if (*speed == SPEED_1000) | |
2890 | ret_val = e1000_configure_kmrn_for_1000(hw); | |
2891 | else | |
2892 | ret_val = e1000_configure_kmrn_for_10_100(hw); | |
2893 | if (ret_val) | |
2894 | return ret_val; | |
2895 | } | |
2896 | ||
1da177e4 LT |
2897 | return E1000_SUCCESS; |
2898 | } | |
2899 | ||
2900 | /****************************************************************************** | |
2901 | * Blocks until autoneg completes or times out (~4.5 seconds) | |
2902 | * | |
2903 | * hw - Struct containing variables accessed by shared code | |
2904 | ******************************************************************************/ | |
3ad2cc67 | 2905 | static int32_t |
1da177e4 LT |
2906 | e1000_wait_autoneg(struct e1000_hw *hw) |
2907 | { | |
2908 | int32_t ret_val; | |
2909 | uint16_t i; | |
2910 | uint16_t phy_data; | |
2911 | ||
2912 | DEBUGFUNC("e1000_wait_autoneg"); | |
2913 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); | |
2914 | ||
2915 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ | |
2916 | for(i = PHY_AUTO_NEG_TIME; i > 0; i--) { | |
2917 | /* Read the MII Status Register and wait for Auto-Neg | |
2918 | * Complete bit to be set. | |
2919 | */ | |
2920 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
2921 | if(ret_val) | |
2922 | return ret_val; | |
2923 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
2924 | if(ret_val) | |
2925 | return ret_val; | |
2926 | if(phy_data & MII_SR_AUTONEG_COMPLETE) { | |
2927 | return E1000_SUCCESS; | |
2928 | } | |
2929 | msec_delay(100); | |
2930 | } | |
2931 | return E1000_SUCCESS; | |
2932 | } | |
2933 | ||
2934 | /****************************************************************************** | |
2935 | * Raises the Management Data Clock | |
2936 | * | |
2937 | * hw - Struct containing variables accessed by shared code | |
2938 | * ctrl - Device control register's current value | |
2939 | ******************************************************************************/ | |
2940 | static void | |
2941 | e1000_raise_mdi_clk(struct e1000_hw *hw, | |
2942 | uint32_t *ctrl) | |
2943 | { | |
2944 | /* Raise the clock input to the Management Data Clock (by setting the MDC | |
2945 | * bit), and then delay 10 microseconds. | |
2946 | */ | |
2947 | E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); | |
2948 | E1000_WRITE_FLUSH(hw); | |
2949 | udelay(10); | |
2950 | } | |
2951 | ||
2952 | /****************************************************************************** | |
2953 | * Lowers the Management Data Clock | |
2954 | * | |
2955 | * hw - Struct containing variables accessed by shared code | |
2956 | * ctrl - Device control register's current value | |
2957 | ******************************************************************************/ | |
2958 | static void | |
2959 | e1000_lower_mdi_clk(struct e1000_hw *hw, | |
2960 | uint32_t *ctrl) | |
2961 | { | |
2962 | /* Lower the clock input to the Management Data Clock (by clearing the MDC | |
2963 | * bit), and then delay 10 microseconds. | |
2964 | */ | |
2965 | E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); | |
2966 | E1000_WRITE_FLUSH(hw); | |
2967 | udelay(10); | |
2968 | } | |
2969 | ||
2970 | /****************************************************************************** | |
2971 | * Shifts data bits out to the PHY | |
2972 | * | |
2973 | * hw - Struct containing variables accessed by shared code | |
2974 | * data - Data to send out to the PHY | |
2975 | * count - Number of bits to shift out | |
2976 | * | |
2977 | * Bits are shifted out in MSB to LSB order. | |
2978 | ******************************************************************************/ | |
2979 | static void | |
2980 | e1000_shift_out_mdi_bits(struct e1000_hw *hw, | |
2981 | uint32_t data, | |
2982 | uint16_t count) | |
2983 | { | |
2984 | uint32_t ctrl; | |
2985 | uint32_t mask; | |
2986 | ||
2987 | /* We need to shift "count" number of bits out to the PHY. So, the value | |
2988 | * in the "data" parameter will be shifted out to the PHY one bit at a | |
2989 | * time. In order to do this, "data" must be broken down into bits. | |
2990 | */ | |
2991 | mask = 0x01; | |
2992 | mask <<= (count - 1); | |
2993 | ||
2994 | ctrl = E1000_READ_REG(hw, CTRL); | |
2995 | ||
2996 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ | |
2997 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); | |
2998 | ||
2999 | while(mask) { | |
3000 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and | |
3001 | * then raising and lowering the Management Data Clock. A "0" is | |
3002 | * shifted out to the PHY by setting the MDIO bit to "0" and then | |
3003 | * raising and lowering the clock. | |
3004 | */ | |
3005 | if(data & mask) ctrl |= E1000_CTRL_MDIO; | |
3006 | else ctrl &= ~E1000_CTRL_MDIO; | |
3007 | ||
3008 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
3009 | E1000_WRITE_FLUSH(hw); | |
3010 | ||
3011 | udelay(10); | |
3012 | ||
3013 | e1000_raise_mdi_clk(hw, &ctrl); | |
3014 | e1000_lower_mdi_clk(hw, &ctrl); | |
3015 | ||
3016 | mask = mask >> 1; | |
3017 | } | |
3018 | } | |
3019 | ||
3020 | /****************************************************************************** | |
3021 | * Shifts data bits in from the PHY | |
3022 | * | |
3023 | * hw - Struct containing variables accessed by shared code | |
3024 | * | |
3025 | * Bits are shifted in in MSB to LSB order. | |
3026 | ******************************************************************************/ | |
3027 | static uint16_t | |
3028 | e1000_shift_in_mdi_bits(struct e1000_hw *hw) | |
3029 | { | |
3030 | uint32_t ctrl; | |
3031 | uint16_t data = 0; | |
3032 | uint8_t i; | |
3033 | ||
3034 | /* In order to read a register from the PHY, we need to shift in a total | |
3035 | * of 18 bits from the PHY. The first two bit (turnaround) times are used | |
3036 | * to avoid contention on the MDIO pin when a read operation is performed. | |
3037 | * These two bits are ignored by us and thrown away. Bits are "shifted in" | |
3038 | * by raising the input to the Management Data Clock (setting the MDC bit), | |
3039 | * and then reading the value of the MDIO bit. | |
3040 | */ | |
3041 | ctrl = E1000_READ_REG(hw, CTRL); | |
3042 | ||
3043 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ | |
3044 | ctrl &= ~E1000_CTRL_MDIO_DIR; | |
3045 | ctrl &= ~E1000_CTRL_MDIO; | |
3046 | ||
3047 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
3048 | E1000_WRITE_FLUSH(hw); | |
3049 | ||
3050 | /* Raise and Lower the clock before reading in the data. This accounts for | |
3051 | * the turnaround bits. The first clock occurred when we clocked out the | |
3052 | * last bit of the Register Address. | |
3053 | */ | |
3054 | e1000_raise_mdi_clk(hw, &ctrl); | |
3055 | e1000_lower_mdi_clk(hw, &ctrl); | |
3056 | ||
3057 | for(data = 0, i = 0; i < 16; i++) { | |
3058 | data = data << 1; | |
3059 | e1000_raise_mdi_clk(hw, &ctrl); | |
3060 | ctrl = E1000_READ_REG(hw, CTRL); | |
3061 | /* Check to see if we shifted in a "1". */ | |
3062 | if(ctrl & E1000_CTRL_MDIO) data |= 1; | |
3063 | e1000_lower_mdi_clk(hw, &ctrl); | |
3064 | } | |
3065 | ||
3066 | e1000_raise_mdi_clk(hw, &ctrl); | |
3067 | e1000_lower_mdi_clk(hw, &ctrl); | |
3068 | ||
3069 | return data; | |
3070 | } | |
3071 | ||
6418ecc6 JK |
3072 | int32_t |
3073 | e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) | |
3074 | { | |
3075 | uint32_t swfw_sync = 0; | |
3076 | uint32_t swmask = mask; | |
3077 | uint32_t fwmask = mask << 16; | |
3078 | int32_t timeout = 200; | |
3079 | ||
3080 | DEBUGFUNC("e1000_swfw_sync_acquire"); | |
3081 | ||
3082 | if (!hw->swfw_sync_present) | |
3083 | return e1000_get_hw_eeprom_semaphore(hw); | |
3084 | ||
3085 | while(timeout) { | |
3086 | if (e1000_get_hw_eeprom_semaphore(hw)) | |
3087 | return -E1000_ERR_SWFW_SYNC; | |
3088 | ||
3089 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); | |
3090 | if (!(swfw_sync & (fwmask | swmask))) { | |
3091 | break; | |
3092 | } | |
3093 | ||
3094 | /* firmware currently using resource (fwmask) */ | |
3095 | /* or other software thread currently using resource (swmask) */ | |
3096 | e1000_put_hw_eeprom_semaphore(hw); | |
3097 | msec_delay_irq(5); | |
3098 | timeout--; | |
3099 | } | |
3100 | ||
3101 | if (!timeout) { | |
3102 | DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); | |
3103 | return -E1000_ERR_SWFW_SYNC; | |
3104 | } | |
3105 | ||
3106 | swfw_sync |= swmask; | |
3107 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); | |
3108 | ||
3109 | e1000_put_hw_eeprom_semaphore(hw); | |
3110 | return E1000_SUCCESS; | |
3111 | } | |
3112 | ||
3113 | void | |
3114 | e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) | |
3115 | { | |
3116 | uint32_t swfw_sync; | |
3117 | uint32_t swmask = mask; | |
3118 | ||
3119 | DEBUGFUNC("e1000_swfw_sync_release"); | |
3120 | ||
3121 | if (!hw->swfw_sync_present) { | |
3122 | e1000_put_hw_eeprom_semaphore(hw); | |
3123 | return; | |
3124 | } | |
3125 | ||
3126 | /* if (e1000_get_hw_eeprom_semaphore(hw)) | |
3127 | * return -E1000_ERR_SWFW_SYNC; */ | |
3128 | while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); | |
3129 | /* empty */ | |
3130 | ||
3131 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); | |
3132 | swfw_sync &= ~swmask; | |
3133 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); | |
3134 | ||
3135 | e1000_put_hw_eeprom_semaphore(hw); | |
3136 | } | |
3137 | ||
1da177e4 LT |
3138 | /***************************************************************************** |
3139 | * Reads the value from a PHY register, if the value is on a specific non zero | |
3140 | * page, sets the page first. | |
3141 | * hw - Struct containing variables accessed by shared code | |
3142 | * reg_addr - address of the PHY register to read | |
3143 | ******************************************************************************/ | |
3144 | int32_t | |
3145 | e1000_read_phy_reg(struct e1000_hw *hw, | |
3146 | uint32_t reg_addr, | |
3147 | uint16_t *phy_data) | |
3148 | { | |
3149 | uint32_t ret_val; | |
6418ecc6 | 3150 | uint16_t swfw; |
1da177e4 LT |
3151 | |
3152 | DEBUGFUNC("e1000_read_phy_reg"); | |
3153 | ||
6418ecc6 JK |
3154 | if ((hw->mac_type == e1000_80003es2lan) && |
3155 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { | |
3156 | swfw = E1000_SWFW_PHY1_SM; | |
3157 | } else { | |
3158 | swfw = E1000_SWFW_PHY0_SM; | |
3159 | } | |
3160 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3161 | return -E1000_ERR_SWFW_SYNC; | |
3162 | ||
76c224bc | 3163 | if((hw->phy_type == e1000_phy_igp || |
2d7edb92 | 3164 | hw->phy_type == e1000_phy_igp_2) && |
1da177e4 LT |
3165 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
3166 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | |
3167 | (uint16_t)reg_addr); | |
3168 | if(ret_val) { | |
6418ecc6 | 3169 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3170 | return ret_val; |
3171 | } | |
6418ecc6 JK |
3172 | } else if (hw->phy_type == e1000_phy_gg82563) { |
3173 | if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || | |
3174 | (hw->mac_type == e1000_80003es2lan)) { | |
3175 | /* Select Configuration Page */ | |
3176 | if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { | |
3177 | ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, | |
3178 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); | |
3179 | } else { | |
3180 | /* Use Alternative Page Select register to access | |
3181 | * registers 30 and 31 | |
3182 | */ | |
3183 | ret_val = e1000_write_phy_reg_ex(hw, | |
3184 | GG82563_PHY_PAGE_SELECT_ALT, | |
3185 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); | |
3186 | } | |
3187 | ||
3188 | if (ret_val) { | |
3189 | e1000_swfw_sync_release(hw, swfw); | |
3190 | return ret_val; | |
3191 | } | |
3192 | } | |
1da177e4 LT |
3193 | } |
3194 | ||
3195 | ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, | |
3196 | phy_data); | |
3197 | ||
6418ecc6 | 3198 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3199 | return ret_val; |
3200 | } | |
3201 | ||
3202 | int32_t | |
3203 | e1000_read_phy_reg_ex(struct e1000_hw *hw, | |
3204 | uint32_t reg_addr, | |
3205 | uint16_t *phy_data) | |
3206 | { | |
3207 | uint32_t i; | |
3208 | uint32_t mdic = 0; | |
3209 | const uint32_t phy_addr = 1; | |
3210 | ||
3211 | DEBUGFUNC("e1000_read_phy_reg_ex"); | |
3212 | ||
3213 | if(reg_addr > MAX_PHY_REG_ADDRESS) { | |
3214 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); | |
3215 | return -E1000_ERR_PARAM; | |
3216 | } | |
3217 | ||
3218 | if(hw->mac_type > e1000_82543) { | |
3219 | /* Set up Op-code, Phy Address, and register address in the MDI | |
3220 | * Control register. The MAC will take care of interfacing with the | |
3221 | * PHY to retrieve the desired data. | |
3222 | */ | |
3223 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | | |
3224 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
3225 | (E1000_MDIC_OP_READ)); | |
3226 | ||
3227 | E1000_WRITE_REG(hw, MDIC, mdic); | |
3228 | ||
3229 | /* Poll the ready bit to see if the MDI read completed */ | |
3230 | for(i = 0; i < 64; i++) { | |
3231 | udelay(50); | |
3232 | mdic = E1000_READ_REG(hw, MDIC); | |
3233 | if(mdic & E1000_MDIC_READY) break; | |
3234 | } | |
3235 | if(!(mdic & E1000_MDIC_READY)) { | |
3236 | DEBUGOUT("MDI Read did not complete\n"); | |
3237 | return -E1000_ERR_PHY; | |
3238 | } | |
3239 | if(mdic & E1000_MDIC_ERROR) { | |
3240 | DEBUGOUT("MDI Error\n"); | |
3241 | return -E1000_ERR_PHY; | |
3242 | } | |
3243 | *phy_data = (uint16_t) mdic; | |
3244 | } else { | |
3245 | /* We must first send a preamble through the MDIO pin to signal the | |
3246 | * beginning of an MII instruction. This is done by sending 32 | |
3247 | * consecutive "1" bits. | |
3248 | */ | |
3249 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
3250 | ||
3251 | /* Now combine the next few fields that are required for a read | |
3252 | * operation. We use this method instead of calling the | |
3253 | * e1000_shift_out_mdi_bits routine five different times. The format of | |
3254 | * a MII read instruction consists of a shift out of 14 bits and is | |
3255 | * defined as follows: | |
3256 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> | |
3257 | * followed by a shift in of 18 bits. This first two bits shifted in | |
3258 | * are TurnAround bits used to avoid contention on the MDIO pin when a | |
3259 | * READ operation is performed. These two bits are thrown away | |
3260 | * followed by a shift in of 16 bits which contains the desired data. | |
3261 | */ | |
3262 | mdic = ((reg_addr) | (phy_addr << 5) | | |
3263 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); | |
3264 | ||
3265 | e1000_shift_out_mdi_bits(hw, mdic, 14); | |
3266 | ||
3267 | /* Now that we've shifted out the read command to the MII, we need to | |
3268 | * "shift in" the 16-bit value (18 total bits) of the requested PHY | |
3269 | * register address. | |
3270 | */ | |
3271 | *phy_data = e1000_shift_in_mdi_bits(hw); | |
3272 | } | |
3273 | return E1000_SUCCESS; | |
3274 | } | |
3275 | ||
3276 | /****************************************************************************** | |
3277 | * Writes a value to a PHY register | |
3278 | * | |
3279 | * hw - Struct containing variables accessed by shared code | |
3280 | * reg_addr - address of the PHY register to write | |
3281 | * data - data to write to the PHY | |
3282 | ******************************************************************************/ | |
3283 | int32_t | |
3284 | e1000_write_phy_reg(struct e1000_hw *hw, | |
3285 | uint32_t reg_addr, | |
3286 | uint16_t phy_data) | |
3287 | { | |
3288 | uint32_t ret_val; | |
6418ecc6 | 3289 | uint16_t swfw; |
1da177e4 LT |
3290 | |
3291 | DEBUGFUNC("e1000_write_phy_reg"); | |
3292 | ||
6418ecc6 JK |
3293 | if ((hw->mac_type == e1000_80003es2lan) && |
3294 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { | |
3295 | swfw = E1000_SWFW_PHY1_SM; | |
3296 | } else { | |
3297 | swfw = E1000_SWFW_PHY0_SM; | |
3298 | } | |
3299 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3300 | return -E1000_ERR_SWFW_SYNC; | |
3301 | ||
76c224bc | 3302 | if((hw->phy_type == e1000_phy_igp || |
2d7edb92 | 3303 | hw->phy_type == e1000_phy_igp_2) && |
1da177e4 LT |
3304 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
3305 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | |
3306 | (uint16_t)reg_addr); | |
3307 | if(ret_val) { | |
6418ecc6 | 3308 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3309 | return ret_val; |
3310 | } | |
6418ecc6 JK |
3311 | } else if (hw->phy_type == e1000_phy_gg82563) { |
3312 | if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || | |
3313 | (hw->mac_type == e1000_80003es2lan)) { | |
3314 | /* Select Configuration Page */ | |
3315 | if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { | |
3316 | ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, | |
3317 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); | |
3318 | } else { | |
3319 | /* Use Alternative Page Select register to access | |
3320 | * registers 30 and 31 | |
3321 | */ | |
3322 | ret_val = e1000_write_phy_reg_ex(hw, | |
3323 | GG82563_PHY_PAGE_SELECT_ALT, | |
3324 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); | |
3325 | } | |
3326 | ||
3327 | if (ret_val) { | |
3328 | e1000_swfw_sync_release(hw, swfw); | |
3329 | return ret_val; | |
3330 | } | |
3331 | } | |
1da177e4 LT |
3332 | } |
3333 | ||
3334 | ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, | |
3335 | phy_data); | |
3336 | ||
6418ecc6 | 3337 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3338 | return ret_val; |
3339 | } | |
3340 | ||
3341 | int32_t | |
3342 | e1000_write_phy_reg_ex(struct e1000_hw *hw, | |
3343 | uint32_t reg_addr, | |
3344 | uint16_t phy_data) | |
3345 | { | |
3346 | uint32_t i; | |
3347 | uint32_t mdic = 0; | |
3348 | const uint32_t phy_addr = 1; | |
3349 | ||
3350 | DEBUGFUNC("e1000_write_phy_reg_ex"); | |
3351 | ||
3352 | if(reg_addr > MAX_PHY_REG_ADDRESS) { | |
3353 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); | |
3354 | return -E1000_ERR_PARAM; | |
3355 | } | |
3356 | ||
3357 | if(hw->mac_type > e1000_82543) { | |
3358 | /* Set up Op-code, Phy Address, register address, and data intended | |
3359 | * for the PHY register in the MDI Control register. The MAC will take | |
3360 | * care of interfacing with the PHY to send the desired data. | |
3361 | */ | |
3362 | mdic = (((uint32_t) phy_data) | | |
3363 | (reg_addr << E1000_MDIC_REG_SHIFT) | | |
3364 | (phy_addr << E1000_MDIC_PHY_SHIFT) | | |
3365 | (E1000_MDIC_OP_WRITE)); | |
3366 | ||
3367 | E1000_WRITE_REG(hw, MDIC, mdic); | |
3368 | ||
3369 | /* Poll the ready bit to see if the MDI read completed */ | |
3370 | for(i = 0; i < 640; i++) { | |
3371 | udelay(5); | |
3372 | mdic = E1000_READ_REG(hw, MDIC); | |
3373 | if(mdic & E1000_MDIC_READY) break; | |
3374 | } | |
3375 | if(!(mdic & E1000_MDIC_READY)) { | |
3376 | DEBUGOUT("MDI Write did not complete\n"); | |
3377 | return -E1000_ERR_PHY; | |
3378 | } | |
3379 | } else { | |
3380 | /* We'll need to use the SW defined pins to shift the write command | |
3381 | * out to the PHY. We first send a preamble to the PHY to signal the | |
3382 | * beginning of the MII instruction. This is done by sending 32 | |
3383 | * consecutive "1" bits. | |
3384 | */ | |
3385 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); | |
3386 | ||
3387 | /* Now combine the remaining required fields that will indicate a | |
3388 | * write operation. We use this method instead of calling the | |
3389 | * e1000_shift_out_mdi_bits routine for each field in the command. The | |
3390 | * format of a MII write instruction is as follows: | |
3391 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. | |
3392 | */ | |
3393 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | | |
3394 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); | |
3395 | mdic <<= 16; | |
3396 | mdic |= (uint32_t) phy_data; | |
3397 | ||
3398 | e1000_shift_out_mdi_bits(hw, mdic, 32); | |
3399 | } | |
3400 | ||
3401 | return E1000_SUCCESS; | |
3402 | } | |
3403 | ||
6418ecc6 JK |
3404 | int32_t |
3405 | e1000_read_kmrn_reg(struct e1000_hw *hw, | |
3406 | uint32_t reg_addr, | |
3407 | uint16_t *data) | |
3408 | { | |
3409 | uint32_t reg_val; | |
3410 | uint16_t swfw; | |
3411 | DEBUGFUNC("e1000_read_kmrn_reg"); | |
3412 | ||
3413 | if ((hw->mac_type == e1000_80003es2lan) && | |
3414 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { | |
3415 | swfw = E1000_SWFW_PHY1_SM; | |
3416 | } else { | |
3417 | swfw = E1000_SWFW_PHY0_SM; | |
3418 | } | |
3419 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3420 | return -E1000_ERR_SWFW_SYNC; | |
3421 | ||
3422 | /* Write register address */ | |
3423 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & | |
3424 | E1000_KUMCTRLSTA_OFFSET) | | |
3425 | E1000_KUMCTRLSTA_REN; | |
3426 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); | |
3427 | udelay(2); | |
3428 | ||
3429 | /* Read the data returned */ | |
3430 | reg_val = E1000_READ_REG(hw, KUMCTRLSTA); | |
3431 | *data = (uint16_t)reg_val; | |
3432 | ||
3433 | e1000_swfw_sync_release(hw, swfw); | |
3434 | return E1000_SUCCESS; | |
3435 | } | |
3436 | ||
3437 | int32_t | |
3438 | e1000_write_kmrn_reg(struct e1000_hw *hw, | |
3439 | uint32_t reg_addr, | |
3440 | uint16_t data) | |
3441 | { | |
3442 | uint32_t reg_val; | |
3443 | uint16_t swfw; | |
3444 | DEBUGFUNC("e1000_write_kmrn_reg"); | |
3445 | ||
3446 | if ((hw->mac_type == e1000_80003es2lan) && | |
3447 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { | |
3448 | swfw = E1000_SWFW_PHY1_SM; | |
3449 | } else { | |
3450 | swfw = E1000_SWFW_PHY0_SM; | |
3451 | } | |
3452 | if (e1000_swfw_sync_acquire(hw, swfw)) | |
3453 | return -E1000_ERR_SWFW_SYNC; | |
3454 | ||
3455 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & | |
3456 | E1000_KUMCTRLSTA_OFFSET) | data; | |
3457 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); | |
3458 | udelay(2); | |
3459 | ||
3460 | e1000_swfw_sync_release(hw, swfw); | |
3461 | return E1000_SUCCESS; | |
3462 | } | |
2d7edb92 | 3463 | |
1da177e4 LT |
3464 | /****************************************************************************** |
3465 | * Returns the PHY to the power-on reset state | |
3466 | * | |
3467 | * hw - Struct containing variables accessed by shared code | |
3468 | ******************************************************************************/ | |
2d7edb92 | 3469 | int32_t |
1da177e4 LT |
3470 | e1000_phy_hw_reset(struct e1000_hw *hw) |
3471 | { | |
3472 | uint32_t ctrl, ctrl_ext; | |
3473 | uint32_t led_ctrl; | |
2d7edb92 | 3474 | int32_t ret_val; |
6418ecc6 | 3475 | uint16_t swfw; |
1da177e4 LT |
3476 | |
3477 | DEBUGFUNC("e1000_phy_hw_reset"); | |
3478 | ||
2d7edb92 MC |
3479 | /* In the case of the phy reset being blocked, it's not an error, we |
3480 | * simply return success without performing the reset. */ | |
3481 | ret_val = e1000_check_phy_reset_block(hw); | |
3482 | if (ret_val) | |
3483 | return E1000_SUCCESS; | |
3484 | ||
1da177e4 LT |
3485 | DEBUGOUT("Resetting Phy...\n"); |
3486 | ||
3487 | if(hw->mac_type > e1000_82543) { | |
6418ecc6 JK |
3488 | if ((hw->mac_type == e1000_80003es2lan) && |
3489 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { | |
3490 | swfw = E1000_SWFW_PHY1_SM; | |
3491 | } else { | |
3492 | swfw = E1000_SWFW_PHY0_SM; | |
3493 | } | |
3494 | if (e1000_swfw_sync_acquire(hw, swfw)) { | |
3495 | e1000_release_software_semaphore(hw); | |
3496 | return -E1000_ERR_SWFW_SYNC; | |
3497 | } | |
1da177e4 LT |
3498 | /* Read the device control register and assert the E1000_CTRL_PHY_RST |
3499 | * bit. Then, take it out of reset. | |
76c224bc | 3500 | * For pre-e1000_82571 hardware, we delay for 10ms between the assert |
fd803241 | 3501 | * and deassert. For e1000_82571 hardware and later, we instead delay |
0f15a8fa | 3502 | * for 50us between and 10ms after the deassertion. |
1da177e4 LT |
3503 | */ |
3504 | ctrl = E1000_READ_REG(hw, CTRL); | |
3505 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); | |
3506 | E1000_WRITE_FLUSH(hw); | |
76c224bc AK |
3507 | |
3508 | if (hw->mac_type < e1000_82571) | |
fd803241 | 3509 | msec_delay(10); |
b55ccb35 JK |
3510 | else |
3511 | udelay(100); | |
76c224bc | 3512 | |
1da177e4 LT |
3513 | E1000_WRITE_REG(hw, CTRL, ctrl); |
3514 | E1000_WRITE_FLUSH(hw); | |
76c224bc | 3515 | |
fd803241 JK |
3516 | if (hw->mac_type >= e1000_82571) |
3517 | msec_delay(10); | |
6418ecc6 | 3518 | e1000_swfw_sync_release(hw, swfw); |
1da177e4 LT |
3519 | } else { |
3520 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR | |
3521 | * bit to put the PHY into reset. Then, take it out of reset. | |
3522 | */ | |
3523 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | |
3524 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; | |
3525 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; | |
3526 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
3527 | E1000_WRITE_FLUSH(hw); | |
3528 | msec_delay(10); | |
3529 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; | |
3530 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | |
3531 | E1000_WRITE_FLUSH(hw); | |
3532 | } | |
3533 | udelay(150); | |
3534 | ||
3535 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | |
3536 | /* Configure activity LED after PHY reset */ | |
3537 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | |
3538 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
3539 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
3540 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | |
3541 | } | |
2d7edb92 MC |
3542 | |
3543 | /* Wait for FW to finish PHY configuration. */ | |
3544 | ret_val = e1000_get_phy_cfg_done(hw); | |
6418ecc6 | 3545 | e1000_release_software_semaphore(hw); |
2d7edb92 MC |
3546 | |
3547 | return ret_val; | |
1da177e4 LT |
3548 | } |
3549 | ||
3550 | /****************************************************************************** | |
3551 | * Resets the PHY | |
3552 | * | |
3553 | * hw - Struct containing variables accessed by shared code | |
3554 | * | |
3555 | * Sets bit 15 of the MII Control regiser | |
3556 | ******************************************************************************/ | |
3557 | int32_t | |
3558 | e1000_phy_reset(struct e1000_hw *hw) | |
3559 | { | |
3560 | int32_t ret_val; | |
3561 | uint16_t phy_data; | |
3562 | ||
3563 | DEBUGFUNC("e1000_phy_reset"); | |
3564 | ||
2d7edb92 MC |
3565 | /* In the case of the phy reset being blocked, it's not an error, we |
3566 | * simply return success without performing the reset. */ | |
3567 | ret_val = e1000_check_phy_reset_block(hw); | |
3568 | if (ret_val) | |
3569 | return E1000_SUCCESS; | |
3570 | ||
3571 | switch (hw->mac_type) { | |
3572 | case e1000_82541_rev_2: | |
868d5309 MC |
3573 | case e1000_82571: |
3574 | case e1000_82572: | |
2d7edb92 MC |
3575 | ret_val = e1000_phy_hw_reset(hw); |
3576 | if(ret_val) | |
3577 | return ret_val; | |
3578 | break; | |
3579 | default: | |
1da177e4 LT |
3580 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
3581 | if(ret_val) | |
3582 | return ret_val; | |
3583 | ||
3584 | phy_data |= MII_CR_RESET; | |
3585 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | |
3586 | if(ret_val) | |
3587 | return ret_val; | |
3588 | ||
3589 | udelay(1); | |
2d7edb92 MC |
3590 | break; |
3591 | } | |
1da177e4 | 3592 | |
2d7edb92 | 3593 | if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) |
1da177e4 LT |
3594 | e1000_phy_init_script(hw); |
3595 | ||
3596 | return E1000_SUCCESS; | |
3597 | } | |
3598 | ||
3599 | /****************************************************************************** | |
3600 | * Probes the expected PHY address for known PHY IDs | |
3601 | * | |
3602 | * hw - Struct containing variables accessed by shared code | |
3603 | ******************************************************************************/ | |
3ad2cc67 | 3604 | static int32_t |
1da177e4 LT |
3605 | e1000_detect_gig_phy(struct e1000_hw *hw) |
3606 | { | |
3607 | int32_t phy_init_status, ret_val; | |
3608 | uint16_t phy_id_high, phy_id_low; | |
3609 | boolean_t match = FALSE; | |
3610 | ||
3611 | DEBUGFUNC("e1000_detect_gig_phy"); | |
3612 | ||
868d5309 MC |
3613 | /* The 82571 firmware may still be configuring the PHY. In this |
3614 | * case, we cannot access the PHY until the configuration is done. So | |
3615 | * we explicitly set the PHY values. */ | |
3616 | if(hw->mac_type == e1000_82571 || | |
3617 | hw->mac_type == e1000_82572) { | |
3618 | hw->phy_id = IGP01E1000_I_PHY_ID; | |
3619 | hw->phy_type = e1000_phy_igp_2; | |
3620 | return E1000_SUCCESS; | |
3621 | } | |
3622 | ||
6418ecc6 JK |
3623 | /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- |
3624 | * around that forces PHY page 0 to be set or the reads fail. The rest of | |
3625 | * the code in this routine uses e1000_read_phy_reg to read the PHY ID. | |
3626 | * So for ESB-2 we need to have this set so our reads won't fail. If the | |
3627 | * attached PHY is not a e1000_phy_gg82563, the routines below will figure | |
3628 | * this out as well. */ | |
3629 | if (hw->mac_type == e1000_80003es2lan) | |
3630 | hw->phy_type = e1000_phy_gg82563; | |
3631 | ||
1da177e4 LT |
3632 | /* Read the PHY ID Registers to identify which PHY is onboard. */ |
3633 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); | |
3634 | if(ret_val) | |
3635 | return ret_val; | |
3636 | ||
3637 | hw->phy_id = (uint32_t) (phy_id_high << 16); | |
3638 | udelay(20); | |
3639 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); | |
3640 | if(ret_val) | |
3641 | return ret_val; | |
3642 | ||
3643 | hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); | |
3644 | hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; | |
3645 | ||
3646 | switch(hw->mac_type) { | |
3647 | case e1000_82543: | |
3648 | if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; | |
3649 | break; | |
3650 | case e1000_82544: | |
3651 | if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; | |
3652 | break; | |
3653 | case e1000_82540: | |
3654 | case e1000_82545: | |
3655 | case e1000_82545_rev_3: | |
3656 | case e1000_82546: | |
3657 | case e1000_82546_rev_3: | |
3658 | if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; | |
3659 | break; | |
3660 | case e1000_82541: | |
3661 | case e1000_82541_rev_2: | |
3662 | case e1000_82547: | |
3663 | case e1000_82547_rev_2: | |
3664 | if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; | |
3665 | break; | |
2d7edb92 MC |
3666 | case e1000_82573: |
3667 | if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; | |
3668 | break; | |
6418ecc6 JK |
3669 | case e1000_80003es2lan: |
3670 | if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; | |
3671 | break; | |
1da177e4 LT |
3672 | default: |
3673 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); | |
3674 | return -E1000_ERR_CONFIG; | |
3675 | } | |
3676 | phy_init_status = e1000_set_phy_type(hw); | |
3677 | ||
3678 | if ((match) && (phy_init_status == E1000_SUCCESS)) { | |
3679 | DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); | |
3680 | return E1000_SUCCESS; | |
3681 | } | |
3682 | DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); | |
3683 | return -E1000_ERR_PHY; | |
3684 | } | |
3685 | ||
3686 | /****************************************************************************** | |
3687 | * Resets the PHY's DSP | |
3688 | * | |
3689 | * hw - Struct containing variables accessed by shared code | |
3690 | ******************************************************************************/ | |
3691 | static int32_t | |
3692 | e1000_phy_reset_dsp(struct e1000_hw *hw) | |
3693 | { | |
3694 | int32_t ret_val; | |
3695 | DEBUGFUNC("e1000_phy_reset_dsp"); | |
3696 | ||
3697 | do { | |
6418ecc6 JK |
3698 | if (hw->phy_type != e1000_phy_gg82563) { |
3699 | ret_val = e1000_write_phy_reg(hw, 29, 0x001d); | |
3700 | if(ret_val) break; | |
3701 | } | |
1da177e4 LT |
3702 | ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); |
3703 | if(ret_val) break; | |
3704 | ret_val = e1000_write_phy_reg(hw, 30, 0x0000); | |
3705 | if(ret_val) break; | |
3706 | ret_val = E1000_SUCCESS; | |
3707 | } while(0); | |
3708 | ||
3709 | return ret_val; | |
3710 | } | |
3711 | ||
3712 | /****************************************************************************** | |
3713 | * Get PHY information from various PHY registers for igp PHY only. | |
3714 | * | |
3715 | * hw - Struct containing variables accessed by shared code | |
3716 | * phy_info - PHY information structure | |
3717 | ******************************************************************************/ | |
3ad2cc67 | 3718 | static int32_t |
1da177e4 LT |
3719 | e1000_phy_igp_get_info(struct e1000_hw *hw, |
3720 | struct e1000_phy_info *phy_info) | |
3721 | { | |
3722 | int32_t ret_val; | |
3723 | uint16_t phy_data, polarity, min_length, max_length, average; | |
3724 | ||
3725 | DEBUGFUNC("e1000_phy_igp_get_info"); | |
3726 | ||
3727 | /* The downshift status is checked only once, after link is established, | |
3728 | * and it stored in the hw->speed_downgraded parameter. */ | |
2d7edb92 | 3729 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
1da177e4 LT |
3730 | |
3731 | /* IGP01E1000 does not need to support it. */ | |
3732 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; | |
3733 | ||
3734 | /* IGP01E1000 always correct polarity reversal */ | |
3735 | phy_info->polarity_correction = e1000_polarity_reversal_enabled; | |
3736 | ||
3737 | /* Check polarity status */ | |
3738 | ret_val = e1000_check_polarity(hw, &polarity); | |
3739 | if(ret_val) | |
3740 | return ret_val; | |
3741 | ||
3742 | phy_info->cable_polarity = polarity; | |
3743 | ||
3744 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); | |
3745 | if(ret_val) | |
3746 | return ret_val; | |
3747 | ||
3748 | phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >> | |
3749 | IGP01E1000_PSSR_MDIX_SHIFT; | |
3750 | ||
3751 | if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == | |
3752 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
3753 | /* Local/Remote Receiver Information are only valid at 1000 Mbps */ | |
3754 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); | |
3755 | if(ret_val) | |
3756 | return ret_val; | |
3757 | ||
3758 | phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> | |
3759 | SR_1000T_LOCAL_RX_STATUS_SHIFT; | |
3760 | phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> | |
3761 | SR_1000T_REMOTE_RX_STATUS_SHIFT; | |
3762 | ||
3763 | /* Get cable length */ | |
3764 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); | |
3765 | if(ret_val) | |
3766 | return ret_val; | |
3767 | ||
2d7edb92 | 3768 | /* Translate to old method */ |
1da177e4 LT |
3769 | average = (max_length + min_length) / 2; |
3770 | ||
3771 | if(average <= e1000_igp_cable_length_50) | |
3772 | phy_info->cable_length = e1000_cable_length_50; | |
3773 | else if(average <= e1000_igp_cable_length_80) | |
3774 | phy_info->cable_length = e1000_cable_length_50_80; | |
3775 | else if(average <= e1000_igp_cable_length_110) | |
3776 | phy_info->cable_length = e1000_cable_length_80_110; | |
3777 | else if(average <= e1000_igp_cable_length_140) | |
3778 | phy_info->cable_length = e1000_cable_length_110_140; | |
3779 | else | |
3780 | phy_info->cable_length = e1000_cable_length_140; | |
3781 | } | |
3782 | ||
3783 | return E1000_SUCCESS; | |
3784 | } | |
3785 | ||
3786 | /****************************************************************************** | |
3787 | * Get PHY information from various PHY registers fot m88 PHY only. | |
3788 | * | |
3789 | * hw - Struct containing variables accessed by shared code | |
3790 | * phy_info - PHY information structure | |
3791 | ******************************************************************************/ | |
3ad2cc67 | 3792 | static int32_t |
1da177e4 LT |
3793 | e1000_phy_m88_get_info(struct e1000_hw *hw, |
3794 | struct e1000_phy_info *phy_info) | |
3795 | { | |
3796 | int32_t ret_val; | |
3797 | uint16_t phy_data, polarity; | |
3798 | ||
3799 | DEBUGFUNC("e1000_phy_m88_get_info"); | |
3800 | ||
3801 | /* The downshift status is checked only once, after link is established, | |
3802 | * and it stored in the hw->speed_downgraded parameter. */ | |
2d7edb92 | 3803 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
1da177e4 LT |
3804 | |
3805 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
3806 | if(ret_val) | |
3807 | return ret_val; | |
3808 | ||
3809 | phy_info->extended_10bt_distance = | |
3810 | (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> | |
3811 | M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT; | |
3812 | phy_info->polarity_correction = | |
3813 | (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> | |
3814 | M88E1000_PSCR_POLARITY_REVERSAL_SHIFT; | |
3815 | ||
3816 | /* Check polarity status */ | |
3817 | ret_val = e1000_check_polarity(hw, &polarity); | |
3818 | if(ret_val) | |
76c224bc | 3819 | return ret_val; |
1da177e4 LT |
3820 | phy_info->cable_polarity = polarity; |
3821 | ||
3822 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
3823 | if(ret_val) | |
3824 | return ret_val; | |
3825 | ||
3826 | phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >> | |
3827 | M88E1000_PSSR_MDIX_SHIFT; | |
3828 | ||
3829 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
3830 | /* Cable Length Estimation and Local/Remote Receiver Information | |
3831 | * are only valid at 1000 Mbps. | |
3832 | */ | |
6418ecc6 JK |
3833 | if (hw->phy_type != e1000_phy_gg82563) { |
3834 | phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
3835 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); | |
3836 | } else { | |
3837 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, | |
3838 | &phy_data); | |
3839 | if (ret_val) | |
3840 | return ret_val; | |
3841 | ||
3842 | phy_info->cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; | |
3843 | } | |
1da177e4 LT |
3844 | |
3845 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); | |
3846 | if(ret_val) | |
3847 | return ret_val; | |
3848 | ||
3849 | phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >> | |
3850 | SR_1000T_LOCAL_RX_STATUS_SHIFT; | |
3851 | ||
3852 | phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >> | |
3853 | SR_1000T_REMOTE_RX_STATUS_SHIFT; | |
3854 | } | |
3855 | ||
3856 | return E1000_SUCCESS; | |
3857 | } | |
3858 | ||
3859 | /****************************************************************************** | |
3860 | * Get PHY information from various PHY registers | |
3861 | * | |
3862 | * hw - Struct containing variables accessed by shared code | |
3863 | * phy_info - PHY information structure | |
3864 | ******************************************************************************/ | |
3865 | int32_t | |
3866 | e1000_phy_get_info(struct e1000_hw *hw, | |
3867 | struct e1000_phy_info *phy_info) | |
3868 | { | |
3869 | int32_t ret_val; | |
3870 | uint16_t phy_data; | |
3871 | ||
3872 | DEBUGFUNC("e1000_phy_get_info"); | |
3873 | ||
3874 | phy_info->cable_length = e1000_cable_length_undefined; | |
3875 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; | |
3876 | phy_info->cable_polarity = e1000_rev_polarity_undefined; | |
3877 | phy_info->downshift = e1000_downshift_undefined; | |
3878 | phy_info->polarity_correction = e1000_polarity_reversal_undefined; | |
3879 | phy_info->mdix_mode = e1000_auto_x_mode_undefined; | |
3880 | phy_info->local_rx = e1000_1000t_rx_status_undefined; | |
3881 | phy_info->remote_rx = e1000_1000t_rx_status_undefined; | |
3882 | ||
3883 | if(hw->media_type != e1000_media_type_copper) { | |
3884 | DEBUGOUT("PHY info is only valid for copper media\n"); | |
3885 | return -E1000_ERR_CONFIG; | |
3886 | } | |
3887 | ||
3888 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
3889 | if(ret_val) | |
3890 | return ret_val; | |
3891 | ||
3892 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); | |
3893 | if(ret_val) | |
3894 | return ret_val; | |
3895 | ||
3896 | if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { | |
3897 | DEBUGOUT("PHY info is only valid if link is up\n"); | |
3898 | return -E1000_ERR_CONFIG; | |
3899 | } | |
3900 | ||
2d7edb92 MC |
3901 | if(hw->phy_type == e1000_phy_igp || |
3902 | hw->phy_type == e1000_phy_igp_2) | |
1da177e4 LT |
3903 | return e1000_phy_igp_get_info(hw, phy_info); |
3904 | else | |
3905 | return e1000_phy_m88_get_info(hw, phy_info); | |
3906 | } | |
3907 | ||
3908 | int32_t | |
3909 | e1000_validate_mdi_setting(struct e1000_hw *hw) | |
3910 | { | |
3911 | DEBUGFUNC("e1000_validate_mdi_settings"); | |
3912 | ||
3913 | if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { | |
3914 | DEBUGOUT("Invalid MDI setting detected\n"); | |
3915 | hw->mdix = 1; | |
3916 | return -E1000_ERR_CONFIG; | |
3917 | } | |
3918 | return E1000_SUCCESS; | |
3919 | } | |
3920 | ||
3921 | ||
3922 | /****************************************************************************** | |
3923 | * Sets up eeprom variables in the hw struct. Must be called after mac_type | |
0f15a8fa JK |
3924 | * is configured. Additionally, if this is ICH8, the flash controller GbE |
3925 | * registers must be mapped, or this will crash. | |
1da177e4 LT |
3926 | * |
3927 | * hw - Struct containing variables accessed by shared code | |
3928 | *****************************************************************************/ | |
2d7edb92 | 3929 | int32_t |
1da177e4 LT |
3930 | e1000_init_eeprom_params(struct e1000_hw *hw) |
3931 | { | |
3932 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
3933 | uint32_t eecd = E1000_READ_REG(hw, EECD); | |
2d7edb92 | 3934 | int32_t ret_val = E1000_SUCCESS; |
1da177e4 LT |
3935 | uint16_t eeprom_size; |
3936 | ||
3937 | DEBUGFUNC("e1000_init_eeprom_params"); | |
3938 | ||
3939 | switch (hw->mac_type) { | |
3940 | case e1000_82542_rev2_0: | |
3941 | case e1000_82542_rev2_1: | |
3942 | case e1000_82543: | |
3943 | case e1000_82544: | |
3944 | eeprom->type = e1000_eeprom_microwire; | |
3945 | eeprom->word_size = 64; | |
3946 | eeprom->opcode_bits = 3; | |
3947 | eeprom->address_bits = 6; | |
3948 | eeprom->delay_usec = 50; | |
2d7edb92 MC |
3949 | eeprom->use_eerd = FALSE; |
3950 | eeprom->use_eewr = FALSE; | |
1da177e4 LT |
3951 | break; |
3952 | case e1000_82540: | |
3953 | case e1000_82545: | |
3954 | case e1000_82545_rev_3: | |
3955 | case e1000_82546: | |
3956 | case e1000_82546_rev_3: | |
3957 | eeprom->type = e1000_eeprom_microwire; | |
3958 | eeprom->opcode_bits = 3; | |
3959 | eeprom->delay_usec = 50; | |
3960 | if(eecd & E1000_EECD_SIZE) { | |
3961 | eeprom->word_size = 256; | |
3962 | eeprom->address_bits = 8; | |
3963 | } else { | |
3964 | eeprom->word_size = 64; | |
3965 | eeprom->address_bits = 6; | |
3966 | } | |
2d7edb92 MC |
3967 | eeprom->use_eerd = FALSE; |
3968 | eeprom->use_eewr = FALSE; | |
1da177e4 LT |
3969 | break; |
3970 | case e1000_82541: | |
3971 | case e1000_82541_rev_2: | |
3972 | case e1000_82547: | |
3973 | case e1000_82547_rev_2: | |
3974 | if (eecd & E1000_EECD_TYPE) { | |
3975 | eeprom->type = e1000_eeprom_spi; | |
3976 | eeprom->opcode_bits = 8; | |
3977 | eeprom->delay_usec = 1; | |
3978 | if (eecd & E1000_EECD_ADDR_BITS) { | |
3979 | eeprom->page_size = 32; | |
3980 | eeprom->address_bits = 16; | |
3981 | } else { | |
3982 | eeprom->page_size = 8; | |
3983 | eeprom->address_bits = 8; | |
3984 | } | |
3985 | } else { | |
3986 | eeprom->type = e1000_eeprom_microwire; | |
3987 | eeprom->opcode_bits = 3; | |
3988 | eeprom->delay_usec = 50; | |
3989 | if (eecd & E1000_EECD_ADDR_BITS) { | |
3990 | eeprom->word_size = 256; | |
3991 | eeprom->address_bits = 8; | |
3992 | } else { | |
3993 | eeprom->word_size = 64; | |
3994 | eeprom->address_bits = 6; | |
3995 | } | |
3996 | } | |
2d7edb92 MC |
3997 | eeprom->use_eerd = FALSE; |
3998 | eeprom->use_eewr = FALSE; | |
3999 | break; | |
868d5309 MC |
4000 | case e1000_82571: |
4001 | case e1000_82572: | |
4002 | eeprom->type = e1000_eeprom_spi; | |
4003 | eeprom->opcode_bits = 8; | |
4004 | eeprom->delay_usec = 1; | |
4005 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4006 | eeprom->page_size = 32; | |
4007 | eeprom->address_bits = 16; | |
4008 | } else { | |
4009 | eeprom->page_size = 8; | |
4010 | eeprom->address_bits = 8; | |
4011 | } | |
4012 | eeprom->use_eerd = FALSE; | |
4013 | eeprom->use_eewr = FALSE; | |
4014 | break; | |
2d7edb92 MC |
4015 | case e1000_82573: |
4016 | eeprom->type = e1000_eeprom_spi; | |
4017 | eeprom->opcode_bits = 8; | |
4018 | eeprom->delay_usec = 1; | |
4019 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4020 | eeprom->page_size = 32; | |
4021 | eeprom->address_bits = 16; | |
4022 | } else { | |
4023 | eeprom->page_size = 8; | |
4024 | eeprom->address_bits = 8; | |
4025 | } | |
4026 | eeprom->use_eerd = TRUE; | |
4027 | eeprom->use_eewr = TRUE; | |
4028 | if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) { | |
4029 | eeprom->type = e1000_eeprom_flash; | |
4030 | eeprom->word_size = 2048; | |
4031 | ||
4032 | /* Ensure that the Autonomous FLASH update bit is cleared due to | |
4033 | * Flash update issue on parts which use a FLASH for NVM. */ | |
4034 | eecd &= ~E1000_EECD_AUPDEN; | |
4035 | E1000_WRITE_REG(hw, EECD, eecd); | |
4036 | } | |
1da177e4 | 4037 | break; |
6418ecc6 JK |
4038 | case e1000_80003es2lan: |
4039 | eeprom->type = e1000_eeprom_spi; | |
4040 | eeprom->opcode_bits = 8; | |
4041 | eeprom->delay_usec = 1; | |
4042 | if (eecd & E1000_EECD_ADDR_BITS) { | |
4043 | eeprom->page_size = 32; | |
4044 | eeprom->address_bits = 16; | |
4045 | } else { | |
4046 | eeprom->page_size = 8; | |
4047 | eeprom->address_bits = 8; | |
4048 | } | |
4049 | eeprom->use_eerd = TRUE; | |
4050 | eeprom->use_eewr = FALSE; | |
4051 | break; | |
1da177e4 LT |
4052 | default: |
4053 | break; | |
4054 | } | |
4055 | ||
4056 | if (eeprom->type == e1000_eeprom_spi) { | |
2d7edb92 MC |
4057 | /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
4058 | * 32KB (incremented by powers of 2). | |
4059 | */ | |
4060 | if(hw->mac_type <= e1000_82547_rev_2) { | |
4061 | /* Set to default value for initial eeprom read. */ | |
4062 | eeprom->word_size = 64; | |
4063 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); | |
4064 | if(ret_val) | |
4065 | return ret_val; | |
4066 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; | |
4067 | /* 256B eeprom size was not supported in earlier hardware, so we | |
4068 | * bump eeprom_size up one to ensure that "1" (which maps to 256B) | |
4069 | * is never the result used in the shifting logic below. */ | |
4070 | if(eeprom_size) | |
4071 | eeprom_size++; | |
4072 | } else { | |
4073 | eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
4074 | E1000_EECD_SIZE_EX_SHIFT); | |
1da177e4 | 4075 | } |
2d7edb92 MC |
4076 | |
4077 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); | |
1da177e4 | 4078 | } |
2d7edb92 | 4079 | return ret_val; |
1da177e4 LT |
4080 | } |
4081 | ||
4082 | /****************************************************************************** | |
4083 | * Raises the EEPROM's clock input. | |
4084 | * | |
4085 | * hw - Struct containing variables accessed by shared code | |
4086 | * eecd - EECD's current value | |
4087 | *****************************************************************************/ | |
4088 | static void | |
4089 | e1000_raise_ee_clk(struct e1000_hw *hw, | |
4090 | uint32_t *eecd) | |
4091 | { | |
4092 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then | |
4093 | * wait <delay> microseconds. | |
4094 | */ | |
4095 | *eecd = *eecd | E1000_EECD_SK; | |
4096 | E1000_WRITE_REG(hw, EECD, *eecd); | |
4097 | E1000_WRITE_FLUSH(hw); | |
4098 | udelay(hw->eeprom.delay_usec); | |
4099 | } | |
4100 | ||
4101 | /****************************************************************************** | |
4102 | * Lowers the EEPROM's clock input. | |
4103 | * | |
4104 | * hw - Struct containing variables accessed by shared code | |
4105 | * eecd - EECD's current value | |
4106 | *****************************************************************************/ | |
4107 | static void | |
4108 | e1000_lower_ee_clk(struct e1000_hw *hw, | |
4109 | uint32_t *eecd) | |
4110 | { | |
4111 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then | |
4112 | * wait 50 microseconds. | |
4113 | */ | |
4114 | *eecd = *eecd & ~E1000_EECD_SK; | |
4115 | E1000_WRITE_REG(hw, EECD, *eecd); | |
4116 | E1000_WRITE_FLUSH(hw); | |
4117 | udelay(hw->eeprom.delay_usec); | |
4118 | } | |
4119 | ||
4120 | /****************************************************************************** | |
4121 | * Shift data bits out to the EEPROM. | |
4122 | * | |
4123 | * hw - Struct containing variables accessed by shared code | |
4124 | * data - data to send to the EEPROM | |
4125 | * count - number of bits to shift out | |
4126 | *****************************************************************************/ | |
4127 | static void | |
4128 | e1000_shift_out_ee_bits(struct e1000_hw *hw, | |
4129 | uint16_t data, | |
4130 | uint16_t count) | |
4131 | { | |
4132 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4133 | uint32_t eecd; | |
4134 | uint32_t mask; | |
4135 | ||
4136 | /* We need to shift "count" bits out to the EEPROM. So, value in the | |
4137 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | |
4138 | * In order to do this, "data" must be broken down into bits. | |
4139 | */ | |
4140 | mask = 0x01 << (count - 1); | |
4141 | eecd = E1000_READ_REG(hw, EECD); | |
4142 | if (eeprom->type == e1000_eeprom_microwire) { | |
4143 | eecd &= ~E1000_EECD_DO; | |
4144 | } else if (eeprom->type == e1000_eeprom_spi) { | |
4145 | eecd |= E1000_EECD_DO; | |
4146 | } | |
4147 | do { | |
4148 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", | |
4149 | * and then raising and then lowering the clock (the SK bit controls | |
4150 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM | |
4151 | * by setting "DI" to "0" and then raising and then lowering the clock. | |
4152 | */ | |
4153 | eecd &= ~E1000_EECD_DI; | |
4154 | ||
4155 | if(data & mask) | |
4156 | eecd |= E1000_EECD_DI; | |
4157 | ||
4158 | E1000_WRITE_REG(hw, EECD, eecd); | |
4159 | E1000_WRITE_FLUSH(hw); | |
4160 | ||
4161 | udelay(eeprom->delay_usec); | |
4162 | ||
4163 | e1000_raise_ee_clk(hw, &eecd); | |
4164 | e1000_lower_ee_clk(hw, &eecd); | |
4165 | ||
4166 | mask = mask >> 1; | |
4167 | ||
4168 | } while(mask); | |
4169 | ||
4170 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | |
4171 | eecd &= ~E1000_EECD_DI; | |
4172 | E1000_WRITE_REG(hw, EECD, eecd); | |
4173 | } | |
4174 | ||
4175 | /****************************************************************************** | |
4176 | * Shift data bits in from the EEPROM | |
4177 | * | |
4178 | * hw - Struct containing variables accessed by shared code | |
4179 | *****************************************************************************/ | |
4180 | static uint16_t | |
4181 | e1000_shift_in_ee_bits(struct e1000_hw *hw, | |
4182 | uint16_t count) | |
4183 | { | |
4184 | uint32_t eecd; | |
4185 | uint32_t i; | |
4186 | uint16_t data; | |
4187 | ||
4188 | /* In order to read a register from the EEPROM, we need to shift 'count' | |
4189 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock | |
4190 | * input to the EEPROM (setting the SK bit), and then reading the value of | |
4191 | * the "DO" bit. During this "shifting in" process the "DI" bit should | |
4192 | * always be clear. | |
4193 | */ | |
4194 | ||
4195 | eecd = E1000_READ_REG(hw, EECD); | |
4196 | ||
4197 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
4198 | data = 0; | |
4199 | ||
4200 | for(i = 0; i < count; i++) { | |
4201 | data = data << 1; | |
4202 | e1000_raise_ee_clk(hw, &eecd); | |
4203 | ||
4204 | eecd = E1000_READ_REG(hw, EECD); | |
4205 | ||
4206 | eecd &= ~(E1000_EECD_DI); | |
4207 | if(eecd & E1000_EECD_DO) | |
4208 | data |= 1; | |
4209 | ||
4210 | e1000_lower_ee_clk(hw, &eecd); | |
4211 | } | |
4212 | ||
4213 | return data; | |
4214 | } | |
4215 | ||
4216 | /****************************************************************************** | |
4217 | * Prepares EEPROM for access | |
4218 | * | |
4219 | * hw - Struct containing variables accessed by shared code | |
4220 | * | |
4221 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This | |
4222 | * function should be called before issuing a command to the EEPROM. | |
4223 | *****************************************************************************/ | |
4224 | static int32_t | |
4225 | e1000_acquire_eeprom(struct e1000_hw *hw) | |
4226 | { | |
4227 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4228 | uint32_t eecd, i=0; | |
4229 | ||
4230 | DEBUGFUNC("e1000_acquire_eeprom"); | |
4231 | ||
6418ecc6 JK |
4232 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
4233 | return -E1000_ERR_SWFW_SYNC; | |
1da177e4 LT |
4234 | eecd = E1000_READ_REG(hw, EECD); |
4235 | ||
2d7edb92 | 4236 | if (hw->mac_type != e1000_82573) { |
868d5309 MC |
4237 | /* Request EEPROM Access */ |
4238 | if(hw->mac_type > e1000_82544) { | |
4239 | eecd |= E1000_EECD_REQ; | |
1da177e4 | 4240 | E1000_WRITE_REG(hw, EECD, eecd); |
868d5309 MC |
4241 | eecd = E1000_READ_REG(hw, EECD); |
4242 | while((!(eecd & E1000_EECD_GNT)) && | |
4243 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { | |
4244 | i++; | |
4245 | udelay(5); | |
4246 | eecd = E1000_READ_REG(hw, EECD); | |
4247 | } | |
4248 | if(!(eecd & E1000_EECD_GNT)) { | |
4249 | eecd &= ~E1000_EECD_REQ; | |
4250 | E1000_WRITE_REG(hw, EECD, eecd); | |
4251 | DEBUGOUT("Could not acquire EEPROM grant\n"); | |
6418ecc6 | 4252 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
868d5309 MC |
4253 | return -E1000_ERR_EEPROM; |
4254 | } | |
1da177e4 LT |
4255 | } |
4256 | } | |
4257 | ||
4258 | /* Setup EEPROM for Read/Write */ | |
4259 | ||
4260 | if (eeprom->type == e1000_eeprom_microwire) { | |
4261 | /* Clear SK and DI */ | |
4262 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); | |
4263 | E1000_WRITE_REG(hw, EECD, eecd); | |
4264 | ||
4265 | /* Set CS */ | |
4266 | eecd |= E1000_EECD_CS; | |
4267 | E1000_WRITE_REG(hw, EECD, eecd); | |
4268 | } else if (eeprom->type == e1000_eeprom_spi) { | |
4269 | /* Clear SK and CS */ | |
4270 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
4271 | E1000_WRITE_REG(hw, EECD, eecd); | |
4272 | udelay(1); | |
4273 | } | |
4274 | ||
4275 | return E1000_SUCCESS; | |
4276 | } | |
4277 | ||
4278 | /****************************************************************************** | |
4279 | * Returns EEPROM to a "standby" state | |
4280 | * | |
4281 | * hw - Struct containing variables accessed by shared code | |
4282 | *****************************************************************************/ | |
4283 | static void | |
4284 | e1000_standby_eeprom(struct e1000_hw *hw) | |
4285 | { | |
4286 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4287 | uint32_t eecd; | |
4288 | ||
4289 | eecd = E1000_READ_REG(hw, EECD); | |
4290 | ||
4291 | if(eeprom->type == e1000_eeprom_microwire) { | |
4292 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
4293 | E1000_WRITE_REG(hw, EECD, eecd); | |
4294 | E1000_WRITE_FLUSH(hw); | |
4295 | udelay(eeprom->delay_usec); | |
4296 | ||
4297 | /* Clock high */ | |
4298 | eecd |= E1000_EECD_SK; | |
4299 | E1000_WRITE_REG(hw, EECD, eecd); | |
4300 | E1000_WRITE_FLUSH(hw); | |
4301 | udelay(eeprom->delay_usec); | |
4302 | ||
4303 | /* Select EEPROM */ | |
4304 | eecd |= E1000_EECD_CS; | |
4305 | E1000_WRITE_REG(hw, EECD, eecd); | |
4306 | E1000_WRITE_FLUSH(hw); | |
4307 | udelay(eeprom->delay_usec); | |
4308 | ||
4309 | /* Clock low */ | |
4310 | eecd &= ~E1000_EECD_SK; | |
4311 | E1000_WRITE_REG(hw, EECD, eecd); | |
4312 | E1000_WRITE_FLUSH(hw); | |
4313 | udelay(eeprom->delay_usec); | |
4314 | } else if(eeprom->type == e1000_eeprom_spi) { | |
4315 | /* Toggle CS to flush commands */ | |
4316 | eecd |= E1000_EECD_CS; | |
4317 | E1000_WRITE_REG(hw, EECD, eecd); | |
4318 | E1000_WRITE_FLUSH(hw); | |
4319 | udelay(eeprom->delay_usec); | |
4320 | eecd &= ~E1000_EECD_CS; | |
4321 | E1000_WRITE_REG(hw, EECD, eecd); | |
4322 | E1000_WRITE_FLUSH(hw); | |
4323 | udelay(eeprom->delay_usec); | |
4324 | } | |
4325 | } | |
4326 | ||
4327 | /****************************************************************************** | |
4328 | * Terminates a command by inverting the EEPROM's chip select pin | |
4329 | * | |
4330 | * hw - Struct containing variables accessed by shared code | |
4331 | *****************************************************************************/ | |
4332 | static void | |
4333 | e1000_release_eeprom(struct e1000_hw *hw) | |
4334 | { | |
4335 | uint32_t eecd; | |
4336 | ||
4337 | DEBUGFUNC("e1000_release_eeprom"); | |
4338 | ||
4339 | eecd = E1000_READ_REG(hw, EECD); | |
4340 | ||
4341 | if (hw->eeprom.type == e1000_eeprom_spi) { | |
4342 | eecd |= E1000_EECD_CS; /* Pull CS high */ | |
4343 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ | |
4344 | ||
4345 | E1000_WRITE_REG(hw, EECD, eecd); | |
4346 | ||
4347 | udelay(hw->eeprom.delay_usec); | |
4348 | } else if(hw->eeprom.type == e1000_eeprom_microwire) { | |
4349 | /* cleanup eeprom */ | |
4350 | ||
4351 | /* CS on Microwire is active-high */ | |
4352 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); | |
4353 | ||
4354 | E1000_WRITE_REG(hw, EECD, eecd); | |
4355 | ||
4356 | /* Rising edge of clock */ | |
4357 | eecd |= E1000_EECD_SK; | |
4358 | E1000_WRITE_REG(hw, EECD, eecd); | |
4359 | E1000_WRITE_FLUSH(hw); | |
4360 | udelay(hw->eeprom.delay_usec); | |
4361 | ||
4362 | /* Falling edge of clock */ | |
4363 | eecd &= ~E1000_EECD_SK; | |
4364 | E1000_WRITE_REG(hw, EECD, eecd); | |
4365 | E1000_WRITE_FLUSH(hw); | |
4366 | udelay(hw->eeprom.delay_usec); | |
4367 | } | |
4368 | ||
4369 | /* Stop requesting EEPROM access */ | |
4370 | if(hw->mac_type > e1000_82544) { | |
4371 | eecd &= ~E1000_EECD_REQ; | |
4372 | E1000_WRITE_REG(hw, EECD, eecd); | |
4373 | } | |
2d7edb92 | 4374 | |
6418ecc6 | 4375 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
1da177e4 LT |
4376 | } |
4377 | ||
4378 | /****************************************************************************** | |
4379 | * Reads a 16 bit word from the EEPROM. | |
4380 | * | |
4381 | * hw - Struct containing variables accessed by shared code | |
4382 | *****************************************************************************/ | |
4383 | int32_t | |
4384 | e1000_spi_eeprom_ready(struct e1000_hw *hw) | |
4385 | { | |
4386 | uint16_t retry_count = 0; | |
4387 | uint8_t spi_stat_reg; | |
4388 | ||
4389 | DEBUGFUNC("e1000_spi_eeprom_ready"); | |
4390 | ||
4391 | /* Read "Status Register" repeatedly until the LSB is cleared. The | |
4392 | * EEPROM will signal that the command has been completed by clearing | |
4393 | * bit 0 of the internal status register. If it's not cleared within | |
4394 | * 5 milliseconds, then error out. | |
4395 | */ | |
4396 | retry_count = 0; | |
4397 | do { | |
4398 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, | |
4399 | hw->eeprom.opcode_bits); | |
4400 | spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); | |
4401 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) | |
4402 | break; | |
4403 | ||
4404 | udelay(5); | |
4405 | retry_count += 5; | |
4406 | ||
4407 | e1000_standby_eeprom(hw); | |
4408 | } while(retry_count < EEPROM_MAX_RETRY_SPI); | |
4409 | ||
4410 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and | |
4411 | * only 0-5mSec on 5V devices) | |
4412 | */ | |
4413 | if(retry_count >= EEPROM_MAX_RETRY_SPI) { | |
4414 | DEBUGOUT("SPI EEPROM Status error\n"); | |
4415 | return -E1000_ERR_EEPROM; | |
4416 | } | |
4417 | ||
4418 | return E1000_SUCCESS; | |
4419 | } | |
4420 | ||
4421 | /****************************************************************************** | |
4422 | * Reads a 16 bit word from the EEPROM. | |
4423 | * | |
4424 | * hw - Struct containing variables accessed by shared code | |
4425 | * offset - offset of word in the EEPROM to read | |
4426 | * data - word read from the EEPROM | |
4427 | * words - number of words to read | |
4428 | *****************************************************************************/ | |
4429 | int32_t | |
4430 | e1000_read_eeprom(struct e1000_hw *hw, | |
4431 | uint16_t offset, | |
4432 | uint16_t words, | |
4433 | uint16_t *data) | |
4434 | { | |
4435 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4436 | uint32_t i = 0; | |
2d7edb92 | 4437 | int32_t ret_val; |
1da177e4 LT |
4438 | |
4439 | DEBUGFUNC("e1000_read_eeprom"); | |
2d7edb92 | 4440 | |
1da177e4 LT |
4441 | /* A check for invalid values: offset too large, too many words, and not |
4442 | * enough words. | |
4443 | */ | |
4444 | if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || | |
4445 | (words == 0)) { | |
4446 | DEBUGOUT("\"words\" parameter out of bounds\n"); | |
4447 | return -E1000_ERR_EEPROM; | |
4448 | } | |
4449 | ||
4d351858 JK |
4450 | /* FLASH reads without acquiring the semaphore are safe */ |
4451 | if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && | |
4452 | hw->eeprom.use_eerd == FALSE) { | |
4453 | switch (hw->mac_type) { | |
6418ecc6 JK |
4454 | case e1000_80003es2lan: |
4455 | break; | |
4d351858 JK |
4456 | default: |
4457 | /* Prepare the EEPROM for reading */ | |
4458 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | |
4459 | return -E1000_ERR_EEPROM; | |
4460 | break; | |
4461 | } | |
2d7edb92 MC |
4462 | } |
4463 | ||
96838a40 | 4464 | if (eeprom->use_eerd == TRUE) { |
2d7edb92 MC |
4465 | ret_val = e1000_read_eeprom_eerd(hw, offset, words, data); |
4466 | if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || | |
4467 | (hw->mac_type != e1000_82573)) | |
4468 | e1000_release_eeprom(hw); | |
4469 | return ret_val; | |
4470 | } | |
1da177e4 LT |
4471 | |
4472 | if(eeprom->type == e1000_eeprom_spi) { | |
4473 | uint16_t word_in; | |
4474 | uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; | |
4475 | ||
4476 | if(e1000_spi_eeprom_ready(hw)) { | |
4477 | e1000_release_eeprom(hw); | |
4478 | return -E1000_ERR_EEPROM; | |
4479 | } | |
4480 | ||
4481 | e1000_standby_eeprom(hw); | |
4482 | ||
4483 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | |
4484 | if((eeprom->address_bits == 8) && (offset >= 128)) | |
4485 | read_opcode |= EEPROM_A8_OPCODE_SPI; | |
4486 | ||
4487 | /* Send the READ command (opcode + addr) */ | |
4488 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); | |
4489 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); | |
4490 | ||
4491 | /* Read the data. The address of the eeprom internally increments with | |
4492 | * each byte (spi) being read, saving on the overhead of eeprom setup | |
4493 | * and tear-down. The address counter will roll over if reading beyond | |
4494 | * the size of the eeprom, thus allowing the entire memory to be read | |
4495 | * starting from any offset. */ | |
4496 | for (i = 0; i < words; i++) { | |
4497 | word_in = e1000_shift_in_ee_bits(hw, 16); | |
4498 | data[i] = (word_in >> 8) | (word_in << 8); | |
4499 | } | |
4500 | } else if(eeprom->type == e1000_eeprom_microwire) { | |
4501 | for (i = 0; i < words; i++) { | |
4502 | /* Send the READ command (opcode + addr) */ | |
4503 | e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, | |
4504 | eeprom->opcode_bits); | |
4505 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), | |
4506 | eeprom->address_bits); | |
4507 | ||
4508 | /* Read the data. For microwire, each word requires the overhead | |
4509 | * of eeprom setup and tear-down. */ | |
4510 | data[i] = e1000_shift_in_ee_bits(hw, 16); | |
4511 | e1000_standby_eeprom(hw); | |
4512 | } | |
4513 | } | |
4514 | ||
4515 | /* End this read operation */ | |
4516 | e1000_release_eeprom(hw); | |
4517 | ||
4518 | return E1000_SUCCESS; | |
4519 | } | |
4520 | ||
4521 | /****************************************************************************** | |
2d7edb92 | 4522 | * Reads a 16 bit word from the EEPROM using the EERD register. |
1da177e4 LT |
4523 | * |
4524 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
4525 | * offset - offset of word in the EEPROM to read |
4526 | * data - word read from the EEPROM | |
4527 | * words - number of words to read | |
1da177e4 | 4528 | *****************************************************************************/ |
3ad2cc67 | 4529 | static int32_t |
2d7edb92 MC |
4530 | e1000_read_eeprom_eerd(struct e1000_hw *hw, |
4531 | uint16_t offset, | |
4532 | uint16_t words, | |
4533 | uint16_t *data) | |
1da177e4 | 4534 | { |
2d7edb92 MC |
4535 | uint32_t i, eerd = 0; |
4536 | int32_t error = 0; | |
1da177e4 | 4537 | |
2d7edb92 MC |
4538 | for (i = 0; i < words; i++) { |
4539 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + | |
4540 | E1000_EEPROM_RW_REG_START; | |
1da177e4 | 4541 | |
2d7edb92 MC |
4542 | E1000_WRITE_REG(hw, EERD, eerd); |
4543 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); | |
76c224bc | 4544 | |
2d7edb92 MC |
4545 | if(error) { |
4546 | break; | |
1da177e4 | 4547 | } |
2d7edb92 | 4548 | data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); |
76c224bc | 4549 | |
1da177e4 | 4550 | } |
76c224bc | 4551 | |
2d7edb92 | 4552 | return error; |
1da177e4 LT |
4553 | } |
4554 | ||
4555 | /****************************************************************************** | |
2d7edb92 | 4556 | * Writes a 16 bit word from the EEPROM using the EEWR register. |
1da177e4 LT |
4557 | * |
4558 | * hw - Struct containing variables accessed by shared code | |
2d7edb92 MC |
4559 | * offset - offset of word in the EEPROM to read |
4560 | * data - word read from the EEPROM | |
4561 | * words - number of words to read | |
1da177e4 | 4562 | *****************************************************************************/ |
3ad2cc67 | 4563 | static int32_t |
2d7edb92 MC |
4564 | e1000_write_eeprom_eewr(struct e1000_hw *hw, |
4565 | uint16_t offset, | |
4566 | uint16_t words, | |
4567 | uint16_t *data) | |
1da177e4 | 4568 | { |
2d7edb92 MC |
4569 | uint32_t register_value = 0; |
4570 | uint32_t i = 0; | |
4571 | int32_t error = 0; | |
1da177e4 | 4572 | |
6418ecc6 JK |
4573 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
4574 | return -E1000_ERR_SWFW_SYNC; | |
4575 | ||
2d7edb92 | 4576 | for (i = 0; i < words; i++) { |
76c224bc AK |
4577 | register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | |
4578 | ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | | |
2d7edb92 | 4579 | E1000_EEPROM_RW_REG_START; |
1da177e4 | 4580 | |
2d7edb92 MC |
4581 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
4582 | if(error) { | |
4583 | break; | |
76c224bc | 4584 | } |
2d7edb92 MC |
4585 | |
4586 | E1000_WRITE_REG(hw, EEWR, register_value); | |
76c224bc | 4587 | |
2d7edb92 | 4588 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
76c224bc | 4589 | |
2d7edb92 MC |
4590 | if(error) { |
4591 | break; | |
76c224bc | 4592 | } |
2d7edb92 | 4593 | } |
76c224bc | 4594 | |
6418ecc6 | 4595 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
2d7edb92 MC |
4596 | return error; |
4597 | } | |
4598 | ||
4599 | /****************************************************************************** | |
4600 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | |
4601 | * | |
4602 | * hw - Struct containing variables accessed by shared code | |
4603 | *****************************************************************************/ | |
3ad2cc67 | 4604 | static int32_t |
2d7edb92 MC |
4605 | e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) |
4606 | { | |
4607 | uint32_t attempts = 100000; | |
4608 | uint32_t i, reg = 0; | |
4609 | int32_t done = E1000_ERR_EEPROM; | |
4610 | ||
4611 | for(i = 0; i < attempts; i++) { | |
4612 | if(eerd == E1000_EEPROM_POLL_READ) | |
4613 | reg = E1000_READ_REG(hw, EERD); | |
76c224bc | 4614 | else |
2d7edb92 MC |
4615 | reg = E1000_READ_REG(hw, EEWR); |
4616 | ||
4617 | if(reg & E1000_EEPROM_RW_REG_DONE) { | |
4618 | done = E1000_SUCCESS; | |
4619 | break; | |
4620 | } | |
4621 | udelay(5); | |
4622 | } | |
4623 | ||
4624 | return done; | |
4625 | } | |
4626 | ||
4627 | /*************************************************************************** | |
4628 | * Description: Determines if the onboard NVM is FLASH or EEPROM. | |
4629 | * | |
4630 | * hw - Struct containing variables accessed by shared code | |
4631 | ****************************************************************************/ | |
3ad2cc67 | 4632 | static boolean_t |
2d7edb92 MC |
4633 | e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) |
4634 | { | |
4635 | uint32_t eecd = 0; | |
4636 | ||
6418ecc6 JK |
4637 | DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); |
4638 | ||
2d7edb92 MC |
4639 | if(hw->mac_type == e1000_82573) { |
4640 | eecd = E1000_READ_REG(hw, EECD); | |
4641 | ||
4642 | /* Isolate bits 15 & 16 */ | |
4643 | eecd = ((eecd >> 15) & 0x03); | |
4644 | ||
4645 | /* If both bits are set, device is Flash type */ | |
4646 | if(eecd == 0x03) { | |
4647 | return FALSE; | |
4648 | } | |
4649 | } | |
4650 | return TRUE; | |
4651 | } | |
4652 | ||
4653 | /****************************************************************************** | |
4654 | * Verifies that the EEPROM has a valid checksum | |
4655 | * | |
4656 | * hw - Struct containing variables accessed by shared code | |
4657 | * | |
4658 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. | |
4659 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is | |
4660 | * valid. | |
4661 | *****************************************************************************/ | |
4662 | int32_t | |
4663 | e1000_validate_eeprom_checksum(struct e1000_hw *hw) | |
4664 | { | |
4665 | uint16_t checksum = 0; | |
4666 | uint16_t i, eeprom_data; | |
4667 | ||
4668 | DEBUGFUNC("e1000_validate_eeprom_checksum"); | |
4669 | ||
4670 | if ((hw->mac_type == e1000_82573) && | |
4671 | (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { | |
4672 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating | |
4673 | * 10h-12h. Checksum may need to be fixed. */ | |
4674 | e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); | |
4675 | if ((eeprom_data & 0x10) == 0) { | |
4676 | /* Read 0x23 and check bit 15. This bit is a 1 when the checksum | |
4677 | * has already been fixed. If the checksum is still wrong and this | |
4678 | * bit is a 1, we need to return bad checksum. Otherwise, we need | |
4679 | * to set this bit to a 1 and update the checksum. */ | |
4680 | e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); | |
4681 | if ((eeprom_data & 0x8000) == 0) { | |
4682 | eeprom_data |= 0x8000; | |
4683 | e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); | |
4684 | e1000_update_eeprom_checksum(hw); | |
4685 | } | |
4686 | } | |
4687 | } | |
4688 | ||
4689 | for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { | |
4690 | if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | |
4691 | DEBUGOUT("EEPROM Read Error\n"); | |
4692 | return -E1000_ERR_EEPROM; | |
4693 | } | |
4694 | checksum += eeprom_data; | |
4695 | } | |
4696 | ||
4697 | if(checksum == (uint16_t) EEPROM_SUM) | |
4698 | return E1000_SUCCESS; | |
4699 | else { | |
4700 | DEBUGOUT("EEPROM Checksum Invalid\n"); | |
4701 | return -E1000_ERR_EEPROM; | |
4702 | } | |
4703 | } | |
4704 | ||
4705 | /****************************************************************************** | |
4706 | * Calculates the EEPROM checksum and writes it to the EEPROM | |
4707 | * | |
4708 | * hw - Struct containing variables accessed by shared code | |
4709 | * | |
4710 | * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. | |
4711 | * Writes the difference to word offset 63 of the EEPROM. | |
4712 | *****************************************************************************/ | |
4713 | int32_t | |
4714 | e1000_update_eeprom_checksum(struct e1000_hw *hw) | |
4715 | { | |
4716 | uint16_t checksum = 0; | |
4717 | uint16_t i, eeprom_data; | |
4718 | ||
4719 | DEBUGFUNC("e1000_update_eeprom_checksum"); | |
4720 | ||
4721 | for(i = 0; i < EEPROM_CHECKSUM_REG; i++) { | |
4722 | if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | |
4723 | DEBUGOUT("EEPROM Read Error\n"); | |
4724 | return -E1000_ERR_EEPROM; | |
4725 | } | |
4726 | checksum += eeprom_data; | |
4727 | } | |
4728 | checksum = (uint16_t) EEPROM_SUM - checksum; | |
1da177e4 LT |
4729 | if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
4730 | DEBUGOUT("EEPROM Write Error\n"); | |
4731 | return -E1000_ERR_EEPROM; | |
2d7edb92 MC |
4732 | } else if (hw->eeprom.type == e1000_eeprom_flash) { |
4733 | e1000_commit_shadow_ram(hw); | |
1da177e4 LT |
4734 | } |
4735 | return E1000_SUCCESS; | |
4736 | } | |
4737 | ||
4738 | /****************************************************************************** | |
4739 | * Parent function for writing words to the different EEPROM types. | |
4740 | * | |
4741 | * hw - Struct containing variables accessed by shared code | |
4742 | * offset - offset within the EEPROM to be written to | |
4743 | * words - number of words to write | |
4744 | * data - 16 bit word to be written to the EEPROM | |
4745 | * | |
4746 | * If e1000_update_eeprom_checksum is not called after this function, the | |
4747 | * EEPROM will most likely contain an invalid checksum. | |
4748 | *****************************************************************************/ | |
4749 | int32_t | |
4750 | e1000_write_eeprom(struct e1000_hw *hw, | |
4751 | uint16_t offset, | |
4752 | uint16_t words, | |
4753 | uint16_t *data) | |
4754 | { | |
4755 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4756 | int32_t status = 0; | |
4757 | ||
4758 | DEBUGFUNC("e1000_write_eeprom"); | |
4759 | ||
4760 | /* A check for invalid values: offset too large, too many words, and not | |
4761 | * enough words. | |
4762 | */ | |
4763 | if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || | |
4764 | (words == 0)) { | |
4765 | DEBUGOUT("\"words\" parameter out of bounds\n"); | |
4766 | return -E1000_ERR_EEPROM; | |
4767 | } | |
4768 | ||
868d5309 | 4769 | /* 82573 writes only through eewr */ |
2d7edb92 MC |
4770 | if(eeprom->use_eewr == TRUE) |
4771 | return e1000_write_eeprom_eewr(hw, offset, words, data); | |
4772 | ||
1da177e4 LT |
4773 | /* Prepare the EEPROM for writing */ |
4774 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | |
4775 | return -E1000_ERR_EEPROM; | |
4776 | ||
4777 | if(eeprom->type == e1000_eeprom_microwire) { | |
4778 | status = e1000_write_eeprom_microwire(hw, offset, words, data); | |
4779 | } else { | |
4780 | status = e1000_write_eeprom_spi(hw, offset, words, data); | |
4781 | msec_delay(10); | |
4782 | } | |
4783 | ||
4784 | /* Done with writing */ | |
4785 | e1000_release_eeprom(hw); | |
4786 | ||
4787 | return status; | |
4788 | } | |
4789 | ||
4790 | /****************************************************************************** | |
4791 | * Writes a 16 bit word to a given offset in an SPI EEPROM. | |
4792 | * | |
4793 | * hw - Struct containing variables accessed by shared code | |
4794 | * offset - offset within the EEPROM to be written to | |
4795 | * words - number of words to write | |
4796 | * data - pointer to array of 8 bit words to be written to the EEPROM | |
4797 | * | |
4798 | *****************************************************************************/ | |
4799 | int32_t | |
4800 | e1000_write_eeprom_spi(struct e1000_hw *hw, | |
4801 | uint16_t offset, | |
4802 | uint16_t words, | |
4803 | uint16_t *data) | |
4804 | { | |
4805 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4806 | uint16_t widx = 0; | |
4807 | ||
4808 | DEBUGFUNC("e1000_write_eeprom_spi"); | |
4809 | ||
4810 | while (widx < words) { | |
4811 | uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; | |
4812 | ||
4813 | if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; | |
4814 | ||
4815 | e1000_standby_eeprom(hw); | |
4816 | ||
4817 | /* Send the WRITE ENABLE command (8 bit opcode ) */ | |
4818 | e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, | |
4819 | eeprom->opcode_bits); | |
4820 | ||
4821 | e1000_standby_eeprom(hw); | |
4822 | ||
4823 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ | |
4824 | if((eeprom->address_bits == 8) && (offset >= 128)) | |
4825 | write_opcode |= EEPROM_A8_OPCODE_SPI; | |
4826 | ||
4827 | /* Send the Write command (8-bit opcode + addr) */ | |
4828 | e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); | |
4829 | ||
4830 | e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), | |
4831 | eeprom->address_bits); | |
4832 | ||
4833 | /* Send the data */ | |
4834 | ||
4835 | /* Loop to allow for up to whole page write (32 bytes) of eeprom */ | |
4836 | while (widx < words) { | |
4837 | uint16_t word_out = data[widx]; | |
4838 | word_out = (word_out >> 8) | (word_out << 8); | |
4839 | e1000_shift_out_ee_bits(hw, word_out, 16); | |
4840 | widx++; | |
4841 | ||
4842 | /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE | |
4843 | * operation, while the smaller eeproms are capable of an 8-byte | |
4844 | * PAGE WRITE operation. Break the inner loop to pass new address | |
4845 | */ | |
4846 | if((((offset + widx)*2) % eeprom->page_size) == 0) { | |
4847 | e1000_standby_eeprom(hw); | |
4848 | break; | |
4849 | } | |
4850 | } | |
4851 | } | |
4852 | ||
4853 | return E1000_SUCCESS; | |
4854 | } | |
4855 | ||
4856 | /****************************************************************************** | |
4857 | * Writes a 16 bit word to a given offset in a Microwire EEPROM. | |
4858 | * | |
4859 | * hw - Struct containing variables accessed by shared code | |
4860 | * offset - offset within the EEPROM to be written to | |
4861 | * words - number of words to write | |
4862 | * data - pointer to array of 16 bit words to be written to the EEPROM | |
4863 | * | |
4864 | *****************************************************************************/ | |
4865 | int32_t | |
4866 | e1000_write_eeprom_microwire(struct e1000_hw *hw, | |
4867 | uint16_t offset, | |
4868 | uint16_t words, | |
4869 | uint16_t *data) | |
4870 | { | |
4871 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | |
4872 | uint32_t eecd; | |
4873 | uint16_t words_written = 0; | |
4874 | uint16_t i = 0; | |
4875 | ||
4876 | DEBUGFUNC("e1000_write_eeprom_microwire"); | |
4877 | ||
4878 | /* Send the write enable command to the EEPROM (3-bit opcode plus | |
4879 | * 6/8-bit dummy address beginning with 11). It's less work to include | |
4880 | * the 11 of the dummy address as part of the opcode than it is to shift | |
4881 | * it over the correct number of bits for the address. This puts the | |
4882 | * EEPROM into write/erase mode. | |
4883 | */ | |
4884 | e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, | |
4885 | (uint16_t)(eeprom->opcode_bits + 2)); | |
4886 | ||
4887 | e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); | |
4888 | ||
4889 | /* Prepare the EEPROM */ | |
4890 | e1000_standby_eeprom(hw); | |
4891 | ||
4892 | while (words_written < words) { | |
4893 | /* Send the Write command (3-bit opcode + addr) */ | |
4894 | e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, | |
4895 | eeprom->opcode_bits); | |
4896 | ||
4897 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), | |
4898 | eeprom->address_bits); | |
4899 | ||
4900 | /* Send the data */ | |
4901 | e1000_shift_out_ee_bits(hw, data[words_written], 16); | |
4902 | ||
4903 | /* Toggle the CS line. This in effect tells the EEPROM to execute | |
4904 | * the previous command. | |
4905 | */ | |
4906 | e1000_standby_eeprom(hw); | |
4907 | ||
4908 | /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will | |
4909 | * signal that the command has been completed by raising the DO signal. | |
4910 | * If DO does not go high in 10 milliseconds, then error out. | |
4911 | */ | |
4912 | for(i = 0; i < 200; i++) { | |
4913 | eecd = E1000_READ_REG(hw, EECD); | |
4914 | if(eecd & E1000_EECD_DO) break; | |
4915 | udelay(50); | |
4916 | } | |
4917 | if(i == 200) { | |
4918 | DEBUGOUT("EEPROM Write did not complete\n"); | |
4919 | return -E1000_ERR_EEPROM; | |
4920 | } | |
4921 | ||
4922 | /* Recover from write */ | |
4923 | e1000_standby_eeprom(hw); | |
4924 | ||
4925 | words_written++; | |
4926 | } | |
4927 | ||
4928 | /* Send the write disable command to the EEPROM (3-bit opcode plus | |
4929 | * 6/8-bit dummy address beginning with 10). It's less work to include | |
4930 | * the 10 of the dummy address as part of the opcode than it is to shift | |
4931 | * it over the correct number of bits for the address. This takes the | |
4932 | * EEPROM out of write/erase mode. | |
4933 | */ | |
4934 | e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, | |
4935 | (uint16_t)(eeprom->opcode_bits + 2)); | |
4936 | ||
4937 | e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); | |
4938 | ||
4939 | return E1000_SUCCESS; | |
4940 | } | |
4941 | ||
2d7edb92 MC |
4942 | /****************************************************************************** |
4943 | * Flushes the cached eeprom to NVM. This is done by saving the modified values | |
4944 | * in the eeprom cache and the non modified values in the currently active bank | |
4945 | * to the new bank. | |
4946 | * | |
4947 | * hw - Struct containing variables accessed by shared code | |
4948 | * offset - offset of word in the EEPROM to read | |
4949 | * data - word read from the EEPROM | |
4950 | * words - number of words to read | |
4951 | *****************************************************************************/ | |
3ad2cc67 | 4952 | static int32_t |
2d7edb92 MC |
4953 | e1000_commit_shadow_ram(struct e1000_hw *hw) |
4954 | { | |
4955 | uint32_t attempts = 100000; | |
4956 | uint32_t eecd = 0; | |
4957 | uint32_t flop = 0; | |
4958 | uint32_t i = 0; | |
4959 | int32_t error = E1000_SUCCESS; | |
4960 | ||
4961 | /* The flop register will be used to determine if flash type is STM */ | |
4962 | flop = E1000_READ_REG(hw, FLOP); | |
4963 | ||
4964 | if (hw->mac_type == e1000_82573) { | |
4965 | for (i=0; i < attempts; i++) { | |
4966 | eecd = E1000_READ_REG(hw, EECD); | |
4967 | if ((eecd & E1000_EECD_FLUPD) == 0) { | |
4968 | break; | |
4969 | } | |
4970 | udelay(5); | |
4971 | } | |
4972 | ||
4973 | if (i == attempts) { | |
4974 | return -E1000_ERR_EEPROM; | |
4975 | } | |
4976 | ||
96838a40 | 4977 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ |
2d7edb92 MC |
4978 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { |
4979 | E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); | |
4980 | } | |
4981 | ||
4982 | /* Perform the flash update */ | |
4983 | E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); | |
4984 | ||
96838a40 | 4985 | for (i=0; i < attempts; i++) { |
2d7edb92 MC |
4986 | eecd = E1000_READ_REG(hw, EECD); |
4987 | if ((eecd & E1000_EECD_FLUPD) == 0) { | |
4988 | break; | |
4989 | } | |
4990 | udelay(5); | |
4991 | } | |
4992 | ||
4993 | if (i == attempts) { | |
4994 | return -E1000_ERR_EEPROM; | |
4995 | } | |
4996 | } | |
4997 | ||
4998 | return error; | |
4999 | } | |
5000 | ||
1da177e4 LT |
5001 | /****************************************************************************** |
5002 | * Reads the adapter's part number from the EEPROM | |
5003 | * | |
5004 | * hw - Struct containing variables accessed by shared code | |
5005 | * part_num - Adapter's part number | |
5006 | *****************************************************************************/ | |
5007 | int32_t | |
5008 | e1000_read_part_num(struct e1000_hw *hw, | |
5009 | uint32_t *part_num) | |
5010 | { | |
5011 | uint16_t offset = EEPROM_PBA_BYTE_1; | |
5012 | uint16_t eeprom_data; | |
5013 | ||
5014 | DEBUGFUNC("e1000_read_part_num"); | |
5015 | ||
5016 | /* Get word 0 from EEPROM */ | |
5017 | if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { | |
5018 | DEBUGOUT("EEPROM Read Error\n"); | |
5019 | return -E1000_ERR_EEPROM; | |
5020 | } | |
5021 | /* Save word 0 in upper half of part_num */ | |
5022 | *part_num = (uint32_t) (eeprom_data << 16); | |
5023 | ||
5024 | /* Get word 1 from EEPROM */ | |
5025 | if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { | |
5026 | DEBUGOUT("EEPROM Read Error\n"); | |
5027 | return -E1000_ERR_EEPROM; | |
5028 | } | |
5029 | /* Save word 1 in lower half of part_num */ | |
5030 | *part_num |= eeprom_data; | |
5031 | ||
5032 | return E1000_SUCCESS; | |
5033 | } | |
5034 | ||
5035 | /****************************************************************************** | |
5036 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the | |
5037 | * second function of dual function devices | |
5038 | * | |
5039 | * hw - Struct containing variables accessed by shared code | |
5040 | *****************************************************************************/ | |
5041 | int32_t | |
5042 | e1000_read_mac_addr(struct e1000_hw * hw) | |
5043 | { | |
5044 | uint16_t offset; | |
5045 | uint16_t eeprom_data, i; | |
5046 | ||
5047 | DEBUGFUNC("e1000_read_mac_addr"); | |
5048 | ||
5049 | for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) { | |
5050 | offset = i >> 1; | |
5051 | if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { | |
5052 | DEBUGOUT("EEPROM Read Error\n"); | |
5053 | return -E1000_ERR_EEPROM; | |
5054 | } | |
5055 | hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); | |
5056 | hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); | |
5057 | } | |
96838a40 | 5058 | |
868d5309 MC |
5059 | switch (hw->mac_type) { |
5060 | default: | |
5061 | break; | |
5062 | case e1000_82546: | |
5063 | case e1000_82546_rev_3: | |
5064 | case e1000_82571: | |
6418ecc6 | 5065 | case e1000_80003es2lan: |
868d5309 | 5066 | if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) |
1da177e4 | 5067 | hw->perm_mac_addr[5] ^= 0x01; |
868d5309 MC |
5068 | break; |
5069 | } | |
1da177e4 LT |
5070 | |
5071 | for(i = 0; i < NODE_ADDRESS_SIZE; i++) | |
5072 | hw->mac_addr[i] = hw->perm_mac_addr[i]; | |
5073 | return E1000_SUCCESS; | |
5074 | } | |
5075 | ||
5076 | /****************************************************************************** | |
5077 | * Initializes receive address filters. | |
5078 | * | |
5079 | * hw - Struct containing variables accessed by shared code | |
5080 | * | |
5081 | * Places the MAC address in receive address register 0 and clears the rest | |
5082 | * of the receive addresss registers. Clears the multicast table. Assumes | |
5083 | * the receiver is in reset when the routine is called. | |
5084 | *****************************************************************************/ | |
3ad2cc67 | 5085 | static void |
1da177e4 LT |
5086 | e1000_init_rx_addrs(struct e1000_hw *hw) |
5087 | { | |
5088 | uint32_t i; | |
2d7edb92 | 5089 | uint32_t rar_num; |
1da177e4 LT |
5090 | |
5091 | DEBUGFUNC("e1000_init_rx_addrs"); | |
5092 | ||
5093 | /* Setup the receive address. */ | |
5094 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); | |
5095 | ||
5096 | e1000_rar_set(hw, hw->mac_addr, 0); | |
5097 | ||
2d7edb92 | 5098 | rar_num = E1000_RAR_ENTRIES; |
868d5309 MC |
5099 | |
5100 | /* Reserve a spot for the Locally Administered Address to work around | |
5101 | * an 82571 issue in which a reset on one port will reload the MAC on | |
5102 | * the other port. */ | |
5103 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) | |
5104 | rar_num -= 1; | |
1da177e4 LT |
5105 | /* Zero out the other 15 receive addresses. */ |
5106 | DEBUGOUT("Clearing RAR[1-15]\n"); | |
2d7edb92 | 5107 | for(i = 1; i < rar_num; i++) { |
1da177e4 LT |
5108 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
5109 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); | |
5110 | } | |
5111 | } | |
5112 | ||
3ad2cc67 | 5113 | #if 0 |
1da177e4 LT |
5114 | /****************************************************************************** |
5115 | * Updates the MAC's list of multicast addresses. | |
5116 | * | |
5117 | * hw - Struct containing variables accessed by shared code | |
5118 | * mc_addr_list - the list of new multicast addresses | |
5119 | * mc_addr_count - number of addresses | |
5120 | * pad - number of bytes between addresses in the list | |
5121 | * rar_used_count - offset where to start adding mc addresses into the RAR's | |
5122 | * | |
5123 | * The given list replaces any existing list. Clears the last 15 receive | |
5124 | * address registers and the multicast table. Uses receive address registers | |
5125 | * for the first 15 multicast addresses, and hashes the rest into the | |
5126 | * multicast table. | |
5127 | *****************************************************************************/ | |
5128 | void | |
5129 | e1000_mc_addr_list_update(struct e1000_hw *hw, | |
5130 | uint8_t *mc_addr_list, | |
5131 | uint32_t mc_addr_count, | |
5132 | uint32_t pad, | |
5133 | uint32_t rar_used_count) | |
5134 | { | |
5135 | uint32_t hash_value; | |
5136 | uint32_t i; | |
2d7edb92 MC |
5137 | uint32_t num_rar_entry; |
5138 | uint32_t num_mta_entry; | |
76c224bc | 5139 | |
1da177e4 LT |
5140 | DEBUGFUNC("e1000_mc_addr_list_update"); |
5141 | ||
5142 | /* Set the new number of MC addresses that we are being requested to use. */ | |
5143 | hw->num_mc_addrs = mc_addr_count; | |
5144 | ||
5145 | /* Clear RAR[1-15] */ | |
5146 | DEBUGOUT(" Clearing RAR[1-15]\n"); | |
2d7edb92 | 5147 | num_rar_entry = E1000_RAR_ENTRIES; |
868d5309 MC |
5148 | /* Reserve a spot for the Locally Administered Address to work around |
5149 | * an 82571 issue in which a reset on one port will reload the MAC on | |
5150 | * the other port. */ | |
5151 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) | |
5152 | num_rar_entry -= 1; | |
5153 | ||
2d7edb92 | 5154 | for(i = rar_used_count; i < num_rar_entry; i++) { |
1da177e4 LT |
5155 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
5156 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); | |
5157 | } | |
5158 | ||
5159 | /* Clear the MTA */ | |
5160 | DEBUGOUT(" Clearing MTA\n"); | |
2d7edb92 MC |
5161 | num_mta_entry = E1000_NUM_MTA_REGISTERS; |
5162 | for(i = 0; i < num_mta_entry; i++) { | |
1da177e4 LT |
5163 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
5164 | } | |
5165 | ||
5166 | /* Add the new addresses */ | |
5167 | for(i = 0; i < mc_addr_count; i++) { | |
5168 | DEBUGOUT(" Adding the multicast addresses:\n"); | |
5169 | DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, | |
5170 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], | |
5171 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], | |
5172 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], | |
5173 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], | |
5174 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], | |
5175 | mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); | |
5176 | ||
5177 | hash_value = e1000_hash_mc_addr(hw, | |
5178 | mc_addr_list + | |
5179 | (i * (ETH_LENGTH_OF_ADDRESS + pad))); | |
5180 | ||
5181 | DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); | |
5182 | ||
5183 | /* Place this multicast address in the RAR if there is room, * | |
5184 | * else put it in the MTA | |
5185 | */ | |
2d7edb92 | 5186 | if (rar_used_count < num_rar_entry) { |
1da177e4 LT |
5187 | e1000_rar_set(hw, |
5188 | mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), | |
5189 | rar_used_count); | |
5190 | rar_used_count++; | |
5191 | } else { | |
5192 | e1000_mta_set(hw, hash_value); | |
5193 | } | |
5194 | } | |
5195 | DEBUGOUT("MC Update Complete\n"); | |
5196 | } | |
3ad2cc67 | 5197 | #endif /* 0 */ |
1da177e4 LT |
5198 | |
5199 | /****************************************************************************** | |
5200 | * Hashes an address to determine its location in the multicast table | |
5201 | * | |
5202 | * hw - Struct containing variables accessed by shared code | |
5203 | * mc_addr - the multicast address to hash | |
5204 | *****************************************************************************/ | |
5205 | uint32_t | |
5206 | e1000_hash_mc_addr(struct e1000_hw *hw, | |
5207 | uint8_t *mc_addr) | |
5208 | { | |
5209 | uint32_t hash_value = 0; | |
5210 | ||
5211 | /* The portion of the address that is used for the hash table is | |
5212 | * determined by the mc_filter_type setting. | |
5213 | */ | |
5214 | switch (hw->mc_filter_type) { | |
5215 | /* [0] [1] [2] [3] [4] [5] | |
5216 | * 01 AA 00 12 34 56 | |
5217 | * LSB MSB | |
5218 | */ | |
5219 | case 0: | |
5220 | /* [47:36] i.e. 0x563 for above example address */ | |
5221 | hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); | |
5222 | break; | |
5223 | case 1: | |
5224 | /* [46:35] i.e. 0xAC6 for above example address */ | |
5225 | hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); | |
5226 | break; | |
5227 | case 2: | |
5228 | /* [45:34] i.e. 0x5D8 for above example address */ | |
5229 | hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); | |
5230 | break; | |
5231 | case 3: | |
5232 | /* [43:32] i.e. 0x634 for above example address */ | |
5233 | hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); | |
5234 | break; | |
5235 | } | |
5236 | ||
5237 | hash_value &= 0xFFF; | |
2d7edb92 | 5238 | |
1da177e4 LT |
5239 | return hash_value; |
5240 | } | |
5241 | ||
5242 | /****************************************************************************** | |
5243 | * Sets the bit in the multicast table corresponding to the hash value. | |
5244 | * | |
5245 | * hw - Struct containing variables accessed by shared code | |
5246 | * hash_value - Multicast address hash value | |
5247 | *****************************************************************************/ | |
5248 | void | |
5249 | e1000_mta_set(struct e1000_hw *hw, | |
5250 | uint32_t hash_value) | |
5251 | { | |
5252 | uint32_t hash_bit, hash_reg; | |
5253 | uint32_t mta; | |
5254 | uint32_t temp; | |
5255 | ||
5256 | /* The MTA is a register array of 128 32-bit registers. | |
5257 | * It is treated like an array of 4096 bits. We want to set | |
5258 | * bit BitArray[hash_value]. So we figure out what register | |
5259 | * the bit is in, read it, OR in the new bit, then write | |
5260 | * back the new value. The register is determined by the | |
5261 | * upper 7 bits of the hash value and the bit within that | |
5262 | * register are determined by the lower 5 bits of the value. | |
5263 | */ | |
5264 | hash_reg = (hash_value >> 5) & 0x7F; | |
5265 | hash_bit = hash_value & 0x1F; | |
5266 | ||
5267 | mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); | |
5268 | ||
5269 | mta |= (1 << hash_bit); | |
5270 | ||
5271 | /* If we are on an 82544 and we are trying to write an odd offset | |
5272 | * in the MTA, save off the previous entry before writing and | |
5273 | * restore the old value after writing. | |
5274 | */ | |
5275 | if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { | |
5276 | temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); | |
5277 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); | |
5278 | E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); | |
5279 | } else { | |
5280 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); | |
5281 | } | |
5282 | } | |
5283 | ||
5284 | /****************************************************************************** | |
5285 | * Puts an ethernet address into a receive address register. | |
5286 | * | |
5287 | * hw - Struct containing variables accessed by shared code | |
5288 | * addr - Address to put into receive address register | |
5289 | * index - Receive address register to write | |
5290 | *****************************************************************************/ | |
5291 | void | |
5292 | e1000_rar_set(struct e1000_hw *hw, | |
5293 | uint8_t *addr, | |
5294 | uint32_t index) | |
5295 | { | |
5296 | uint32_t rar_low, rar_high; | |
5297 | ||
5298 | /* HW expects these in little endian so we reverse the byte order | |
5299 | * from network order (big endian) to little endian | |
5300 | */ | |
5301 | rar_low = ((uint32_t) addr[0] | | |
5302 | ((uint32_t) addr[1] << 8) | | |
5303 | ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); | |
8df06e50 | 5304 | rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); |
1da177e4 | 5305 | |
8df06e50 JK |
5306 | /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx |
5307 | * unit hang. | |
5308 | * | |
5309 | * Description: | |
5310 | * If there are any Rx frames queued up or otherwise present in the HW | |
5311 | * before RSS is enabled, and then we enable RSS, the HW Rx unit will | |
5312 | * hang. To work around this issue, we have to disable receives and | |
5313 | * flush out all Rx frames before we enable RSS. To do so, we modify we | |
5314 | * redirect all Rx traffic to manageability and then reset the HW. | |
5315 | * This flushes away Rx frames, and (since the redirections to | |
5316 | * manageability persists across resets) keeps new ones from coming in | |
5317 | * while we work. Then, we clear the Address Valid AV bit for all MAC | |
5318 | * addresses and undo the re-direction to manageability. | |
5319 | * Now, frames are coming in again, but the MAC won't accept them, so | |
5320 | * far so good. We now proceed to initialize RSS (if necessary) and | |
5321 | * configure the Rx unit. Last, we re-enable the AV bits and continue | |
5322 | * on our merry way. | |
5323 | */ | |
5324 | switch (hw->mac_type) { | |
5325 | case e1000_82571: | |
5326 | case e1000_82572: | |
6418ecc6 | 5327 | case e1000_80003es2lan: |
8df06e50 JK |
5328 | if (hw->leave_av_bit_off == TRUE) |
5329 | break; | |
5330 | default: | |
5331 | /* Indicate to hardware the Address is Valid. */ | |
5332 | rar_high |= E1000_RAH_AV; | |
5333 | break; | |
5334 | } | |
1da177e4 LT |
5335 | |
5336 | E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); | |
5337 | E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); | |
5338 | } | |
5339 | ||
5340 | /****************************************************************************** | |
5341 | * Writes a value to the specified offset in the VLAN filter table. | |
5342 | * | |
5343 | * hw - Struct containing variables accessed by shared code | |
5344 | * offset - Offset in VLAN filer table to write | |
5345 | * value - Value to write into VLAN filter table | |
5346 | *****************************************************************************/ | |
5347 | void | |
5348 | e1000_write_vfta(struct e1000_hw *hw, | |
5349 | uint32_t offset, | |
5350 | uint32_t value) | |
5351 | { | |
5352 | uint32_t temp; | |
5353 | ||
5354 | if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { | |
5355 | temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); | |
5356 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | |
5357 | E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); | |
5358 | } else { | |
5359 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); | |
5360 | } | |
5361 | } | |
5362 | ||
5363 | /****************************************************************************** | |
5364 | * Clears the VLAN filer table | |
5365 | * | |
5366 | * hw - Struct containing variables accessed by shared code | |
5367 | *****************************************************************************/ | |
3ad2cc67 | 5368 | static void |
1da177e4 LT |
5369 | e1000_clear_vfta(struct e1000_hw *hw) |
5370 | { | |
5371 | uint32_t offset; | |
2d7edb92 MC |
5372 | uint32_t vfta_value = 0; |
5373 | uint32_t vfta_offset = 0; | |
5374 | uint32_t vfta_bit_in_reg = 0; | |
5375 | ||
5376 | if (hw->mac_type == e1000_82573) { | |
5377 | if (hw->mng_cookie.vlan_id != 0) { | |
5378 | /* The VFTA is a 4096b bit-field, each identifying a single VLAN | |
5379 | * ID. The following operations determine which 32b entry | |
5380 | * (i.e. offset) into the array we want to set the VLAN ID | |
5381 | * (i.e. bit) of the manageability unit. */ | |
5382 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
5383 | E1000_VFTA_ENTRY_SHIFT) & | |
5384 | E1000_VFTA_ENTRY_MASK; | |
5385 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
5386 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
5387 | } | |
5388 | } | |
5389 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
5390 | /* If the offset we want to clear is the same offset of the | |
5391 | * manageability VLAN ID, then clear all bits except that of the | |
5392 | * manageability unit */ | |
5393 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
5394 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); | |
5395 | } | |
1da177e4 LT |
5396 | } |
5397 | ||
3ad2cc67 | 5398 | static int32_t |
1da177e4 LT |
5399 | e1000_id_led_init(struct e1000_hw * hw) |
5400 | { | |
5401 | uint32_t ledctl; | |
5402 | const uint32_t ledctl_mask = 0x000000FF; | |
5403 | const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; | |
5404 | const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; | |
5405 | uint16_t eeprom_data, i, temp; | |
5406 | const uint16_t led_mask = 0x0F; | |
5407 | ||
5408 | DEBUGFUNC("e1000_id_led_init"); | |
5409 | ||
5410 | if(hw->mac_type < e1000_82540) { | |
5411 | /* Nothing to do */ | |
5412 | return E1000_SUCCESS; | |
5413 | } | |
5414 | ||
5415 | ledctl = E1000_READ_REG(hw, LEDCTL); | |
5416 | hw->ledctl_default = ledctl; | |
5417 | hw->ledctl_mode1 = hw->ledctl_default; | |
5418 | hw->ledctl_mode2 = hw->ledctl_default; | |
5419 | ||
5420 | if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { | |
5421 | DEBUGOUT("EEPROM Read Error\n"); | |
5422 | return -E1000_ERR_EEPROM; | |
5423 | } | |
5424 | if((eeprom_data== ID_LED_RESERVED_0000) || | |
5425 | (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; | |
5426 | for(i = 0; i < 4; i++) { | |
5427 | temp = (eeprom_data >> (i << 2)) & led_mask; | |
5428 | switch(temp) { | |
5429 | case ID_LED_ON1_DEF2: | |
5430 | case ID_LED_ON1_ON2: | |
5431 | case ID_LED_ON1_OFF2: | |
5432 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
5433 | hw->ledctl_mode1 |= ledctl_on << (i << 3); | |
5434 | break; | |
5435 | case ID_LED_OFF1_DEF2: | |
5436 | case ID_LED_OFF1_ON2: | |
5437 | case ID_LED_OFF1_OFF2: | |
5438 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); | |
5439 | hw->ledctl_mode1 |= ledctl_off << (i << 3); | |
5440 | break; | |
5441 | default: | |
5442 | /* Do nothing */ | |
5443 | break; | |
5444 | } | |
5445 | switch(temp) { | |
5446 | case ID_LED_DEF1_ON2: | |
5447 | case ID_LED_ON1_ON2: | |
5448 | case ID_LED_OFF1_ON2: | |
5449 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
5450 | hw->ledctl_mode2 |= ledctl_on << (i << 3); | |
5451 | break; | |
5452 | case ID_LED_DEF1_OFF2: | |
5453 | case ID_LED_ON1_OFF2: | |
5454 | case ID_LED_OFF1_OFF2: | |
5455 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); | |
5456 | hw->ledctl_mode2 |= ledctl_off << (i << 3); | |
5457 | break; | |
5458 | default: | |
5459 | /* Do nothing */ | |
5460 | break; | |
5461 | } | |
5462 | } | |
5463 | return E1000_SUCCESS; | |
5464 | } | |
5465 | ||
5466 | /****************************************************************************** | |
5467 | * Prepares SW controlable LED for use and saves the current state of the LED. | |
5468 | * | |
5469 | * hw - Struct containing variables accessed by shared code | |
5470 | *****************************************************************************/ | |
5471 | int32_t | |
5472 | e1000_setup_led(struct e1000_hw *hw) | |
5473 | { | |
5474 | uint32_t ledctl; | |
5475 | int32_t ret_val = E1000_SUCCESS; | |
5476 | ||
5477 | DEBUGFUNC("e1000_setup_led"); | |
5478 | ||
5479 | switch(hw->mac_type) { | |
5480 | case e1000_82542_rev2_0: | |
5481 | case e1000_82542_rev2_1: | |
5482 | case e1000_82543: | |
5483 | case e1000_82544: | |
5484 | /* No setup necessary */ | |
5485 | break; | |
5486 | case e1000_82541: | |
5487 | case e1000_82547: | |
5488 | case e1000_82541_rev_2: | |
5489 | case e1000_82547_rev_2: | |
5490 | /* Turn off PHY Smart Power Down (if enabled) */ | |
5491 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
5492 | &hw->phy_spd_default); | |
5493 | if(ret_val) | |
5494 | return ret_val; | |
5495 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
5496 | (uint16_t)(hw->phy_spd_default & | |
5497 | ~IGP01E1000_GMII_SPD)); | |
5498 | if(ret_val) | |
5499 | return ret_val; | |
5500 | /* Fall Through */ | |
5501 | default: | |
5502 | if(hw->media_type == e1000_media_type_fiber) { | |
5503 | ledctl = E1000_READ_REG(hw, LEDCTL); | |
5504 | /* Save current LEDCTL settings */ | |
5505 | hw->ledctl_default = ledctl; | |
5506 | /* Turn off LED0 */ | |
5507 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | | |
5508 | E1000_LEDCTL_LED0_BLINK | | |
5509 | E1000_LEDCTL_LED0_MODE_MASK); | |
5510 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << | |
5511 | E1000_LEDCTL_LED0_MODE_SHIFT); | |
5512 | E1000_WRITE_REG(hw, LEDCTL, ledctl); | |
5513 | } else if(hw->media_type == e1000_media_type_copper) | |
5514 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); | |
5515 | break; | |
5516 | } | |
5517 | ||
5518 | return E1000_SUCCESS; | |
5519 | } | |
5520 | ||
5521 | /****************************************************************************** | |
5522 | * Restores the saved state of the SW controlable LED. | |
5523 | * | |
5524 | * hw - Struct containing variables accessed by shared code | |
5525 | *****************************************************************************/ | |
5526 | int32_t | |
5527 | e1000_cleanup_led(struct e1000_hw *hw) | |
5528 | { | |
5529 | int32_t ret_val = E1000_SUCCESS; | |
5530 | ||
5531 | DEBUGFUNC("e1000_cleanup_led"); | |
5532 | ||
5533 | switch(hw->mac_type) { | |
5534 | case e1000_82542_rev2_0: | |
5535 | case e1000_82542_rev2_1: | |
5536 | case e1000_82543: | |
5537 | case e1000_82544: | |
5538 | /* No cleanup necessary */ | |
5539 | break; | |
5540 | case e1000_82541: | |
5541 | case e1000_82547: | |
5542 | case e1000_82541_rev_2: | |
5543 | case e1000_82547_rev_2: | |
5544 | /* Turn on PHY Smart Power Down (if previously enabled) */ | |
5545 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, | |
5546 | hw->phy_spd_default); | |
5547 | if(ret_val) | |
5548 | return ret_val; | |
5549 | /* Fall Through */ | |
5550 | default: | |
5551 | /* Restore LEDCTL settings */ | |
5552 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); | |
5553 | break; | |
5554 | } | |
5555 | ||
5556 | return E1000_SUCCESS; | |
5557 | } | |
5558 | ||
5559 | /****************************************************************************** | |
5560 | * Turns on the software controllable LED | |
5561 | * | |
5562 | * hw - Struct containing variables accessed by shared code | |
5563 | *****************************************************************************/ | |
5564 | int32_t | |
5565 | e1000_led_on(struct e1000_hw *hw) | |
5566 | { | |
5567 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); | |
5568 | ||
5569 | DEBUGFUNC("e1000_led_on"); | |
5570 | ||
5571 | switch(hw->mac_type) { | |
5572 | case e1000_82542_rev2_0: | |
5573 | case e1000_82542_rev2_1: | |
5574 | case e1000_82543: | |
5575 | /* Set SW Defineable Pin 0 to turn on the LED */ | |
5576 | ctrl |= E1000_CTRL_SWDPIN0; | |
5577 | ctrl |= E1000_CTRL_SWDPIO0; | |
5578 | break; | |
5579 | case e1000_82544: | |
5580 | if(hw->media_type == e1000_media_type_fiber) { | |
5581 | /* Set SW Defineable Pin 0 to turn on the LED */ | |
5582 | ctrl |= E1000_CTRL_SWDPIN0; | |
5583 | ctrl |= E1000_CTRL_SWDPIO0; | |
5584 | } else { | |
5585 | /* Clear SW Defineable Pin 0 to turn on the LED */ | |
5586 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
5587 | ctrl |= E1000_CTRL_SWDPIO0; | |
5588 | } | |
5589 | break; | |
5590 | default: | |
5591 | if(hw->media_type == e1000_media_type_fiber) { | |
5592 | /* Clear SW Defineable Pin 0 to turn on the LED */ | |
5593 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
5594 | ctrl |= E1000_CTRL_SWDPIO0; | |
5595 | } else if(hw->media_type == e1000_media_type_copper) { | |
5596 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); | |
5597 | return E1000_SUCCESS; | |
5598 | } | |
5599 | break; | |
5600 | } | |
5601 | ||
5602 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
5603 | ||
5604 | return E1000_SUCCESS; | |
5605 | } | |
5606 | ||
5607 | /****************************************************************************** | |
5608 | * Turns off the software controllable LED | |
5609 | * | |
5610 | * hw - Struct containing variables accessed by shared code | |
5611 | *****************************************************************************/ | |
5612 | int32_t | |
5613 | e1000_led_off(struct e1000_hw *hw) | |
5614 | { | |
5615 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); | |
5616 | ||
5617 | DEBUGFUNC("e1000_led_off"); | |
5618 | ||
5619 | switch(hw->mac_type) { | |
5620 | case e1000_82542_rev2_0: | |
5621 | case e1000_82542_rev2_1: | |
5622 | case e1000_82543: | |
5623 | /* Clear SW Defineable Pin 0 to turn off the LED */ | |
5624 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
5625 | ctrl |= E1000_CTRL_SWDPIO0; | |
5626 | break; | |
5627 | case e1000_82544: | |
5628 | if(hw->media_type == e1000_media_type_fiber) { | |
5629 | /* Clear SW Defineable Pin 0 to turn off the LED */ | |
5630 | ctrl &= ~E1000_CTRL_SWDPIN0; | |
5631 | ctrl |= E1000_CTRL_SWDPIO0; | |
5632 | } else { | |
5633 | /* Set SW Defineable Pin 0 to turn off the LED */ | |
5634 | ctrl |= E1000_CTRL_SWDPIN0; | |
5635 | ctrl |= E1000_CTRL_SWDPIO0; | |
5636 | } | |
5637 | break; | |
5638 | default: | |
5639 | if(hw->media_type == e1000_media_type_fiber) { | |
5640 | /* Set SW Defineable Pin 0 to turn off the LED */ | |
5641 | ctrl |= E1000_CTRL_SWDPIN0; | |
5642 | ctrl |= E1000_CTRL_SWDPIO0; | |
5643 | } else if(hw->media_type == e1000_media_type_copper) { | |
5644 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); | |
5645 | return E1000_SUCCESS; | |
5646 | } | |
5647 | break; | |
5648 | } | |
5649 | ||
5650 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
5651 | ||
5652 | return E1000_SUCCESS; | |
5653 | } | |
5654 | ||
5655 | /****************************************************************************** | |
5656 | * Clears all hardware statistics counters. | |
5657 | * | |
5658 | * hw - Struct containing variables accessed by shared code | |
5659 | *****************************************************************************/ | |
3ad2cc67 | 5660 | static void |
1da177e4 LT |
5661 | e1000_clear_hw_cntrs(struct e1000_hw *hw) |
5662 | { | |
5663 | volatile uint32_t temp; | |
5664 | ||
5665 | temp = E1000_READ_REG(hw, CRCERRS); | |
5666 | temp = E1000_READ_REG(hw, SYMERRS); | |
5667 | temp = E1000_READ_REG(hw, MPC); | |
5668 | temp = E1000_READ_REG(hw, SCC); | |
5669 | temp = E1000_READ_REG(hw, ECOL); | |
5670 | temp = E1000_READ_REG(hw, MCC); | |
5671 | temp = E1000_READ_REG(hw, LATECOL); | |
5672 | temp = E1000_READ_REG(hw, COLC); | |
5673 | temp = E1000_READ_REG(hw, DC); | |
5674 | temp = E1000_READ_REG(hw, SEC); | |
5675 | temp = E1000_READ_REG(hw, RLEC); | |
5676 | temp = E1000_READ_REG(hw, XONRXC); | |
5677 | temp = E1000_READ_REG(hw, XONTXC); | |
5678 | temp = E1000_READ_REG(hw, XOFFRXC); | |
5679 | temp = E1000_READ_REG(hw, XOFFTXC); | |
5680 | temp = E1000_READ_REG(hw, FCRUC); | |
5681 | temp = E1000_READ_REG(hw, PRC64); | |
5682 | temp = E1000_READ_REG(hw, PRC127); | |
5683 | temp = E1000_READ_REG(hw, PRC255); | |
5684 | temp = E1000_READ_REG(hw, PRC511); | |
5685 | temp = E1000_READ_REG(hw, PRC1023); | |
5686 | temp = E1000_READ_REG(hw, PRC1522); | |
5687 | temp = E1000_READ_REG(hw, GPRC); | |
5688 | temp = E1000_READ_REG(hw, BPRC); | |
5689 | temp = E1000_READ_REG(hw, MPRC); | |
5690 | temp = E1000_READ_REG(hw, GPTC); | |
5691 | temp = E1000_READ_REG(hw, GORCL); | |
5692 | temp = E1000_READ_REG(hw, GORCH); | |
5693 | temp = E1000_READ_REG(hw, GOTCL); | |
5694 | temp = E1000_READ_REG(hw, GOTCH); | |
5695 | temp = E1000_READ_REG(hw, RNBC); | |
5696 | temp = E1000_READ_REG(hw, RUC); | |
5697 | temp = E1000_READ_REG(hw, RFC); | |
5698 | temp = E1000_READ_REG(hw, ROC); | |
5699 | temp = E1000_READ_REG(hw, RJC); | |
5700 | temp = E1000_READ_REG(hw, TORL); | |
5701 | temp = E1000_READ_REG(hw, TORH); | |
5702 | temp = E1000_READ_REG(hw, TOTL); | |
5703 | temp = E1000_READ_REG(hw, TOTH); | |
5704 | temp = E1000_READ_REG(hw, TPR); | |
5705 | temp = E1000_READ_REG(hw, TPT); | |
5706 | temp = E1000_READ_REG(hw, PTC64); | |
5707 | temp = E1000_READ_REG(hw, PTC127); | |
5708 | temp = E1000_READ_REG(hw, PTC255); | |
5709 | temp = E1000_READ_REG(hw, PTC511); | |
5710 | temp = E1000_READ_REG(hw, PTC1023); | |
5711 | temp = E1000_READ_REG(hw, PTC1522); | |
5712 | temp = E1000_READ_REG(hw, MPTC); | |
5713 | temp = E1000_READ_REG(hw, BPTC); | |
5714 | ||
5715 | if(hw->mac_type < e1000_82543) return; | |
5716 | ||
5717 | temp = E1000_READ_REG(hw, ALGNERRC); | |
5718 | temp = E1000_READ_REG(hw, RXERRC); | |
5719 | temp = E1000_READ_REG(hw, TNCRS); | |
5720 | temp = E1000_READ_REG(hw, CEXTERR); | |
5721 | temp = E1000_READ_REG(hw, TSCTC); | |
5722 | temp = E1000_READ_REG(hw, TSCTFC); | |
5723 | ||
5724 | if(hw->mac_type <= e1000_82544) return; | |
5725 | ||
5726 | temp = E1000_READ_REG(hw, MGTPRC); | |
5727 | temp = E1000_READ_REG(hw, MGTPDC); | |
5728 | temp = E1000_READ_REG(hw, MGTPTC); | |
2d7edb92 MC |
5729 | |
5730 | if(hw->mac_type <= e1000_82547_rev_2) return; | |
5731 | ||
5732 | temp = E1000_READ_REG(hw, IAC); | |
5733 | temp = E1000_READ_REG(hw, ICRXOC); | |
5734 | temp = E1000_READ_REG(hw, ICRXPTC); | |
5735 | temp = E1000_READ_REG(hw, ICRXATC); | |
5736 | temp = E1000_READ_REG(hw, ICTXPTC); | |
5737 | temp = E1000_READ_REG(hw, ICTXATC); | |
5738 | temp = E1000_READ_REG(hw, ICTXQEC); | |
5739 | temp = E1000_READ_REG(hw, ICTXQMTC); | |
5740 | temp = E1000_READ_REG(hw, ICRXDMTC); | |
1da177e4 LT |
5741 | } |
5742 | ||
5743 | /****************************************************************************** | |
5744 | * Resets Adaptive IFS to its default state. | |
5745 | * | |
5746 | * hw - Struct containing variables accessed by shared code | |
5747 | * | |
5748 | * Call this after e1000_init_hw. You may override the IFS defaults by setting | |
5749 | * hw->ifs_params_forced to TRUE. However, you must initialize hw-> | |
5750 | * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio | |
5751 | * before calling this function. | |
5752 | *****************************************************************************/ | |
5753 | void | |
5754 | e1000_reset_adaptive(struct e1000_hw *hw) | |
5755 | { | |
5756 | DEBUGFUNC("e1000_reset_adaptive"); | |
5757 | ||
5758 | if(hw->adaptive_ifs) { | |
5759 | if(!hw->ifs_params_forced) { | |
5760 | hw->current_ifs_val = 0; | |
5761 | hw->ifs_min_val = IFS_MIN; | |
5762 | hw->ifs_max_val = IFS_MAX; | |
5763 | hw->ifs_step_size = IFS_STEP; | |
5764 | hw->ifs_ratio = IFS_RATIO; | |
5765 | } | |
5766 | hw->in_ifs_mode = FALSE; | |
5767 | E1000_WRITE_REG(hw, AIT, 0); | |
5768 | } else { | |
5769 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | |
5770 | } | |
5771 | } | |
5772 | ||
5773 | /****************************************************************************** | |
5774 | * Called during the callback/watchdog routine to update IFS value based on | |
5775 | * the ratio of transmits to collisions. | |
5776 | * | |
5777 | * hw - Struct containing variables accessed by shared code | |
5778 | * tx_packets - Number of transmits since last callback | |
5779 | * total_collisions - Number of collisions since last callback | |
5780 | *****************************************************************************/ | |
5781 | void | |
5782 | e1000_update_adaptive(struct e1000_hw *hw) | |
5783 | { | |
5784 | DEBUGFUNC("e1000_update_adaptive"); | |
5785 | ||
5786 | if(hw->adaptive_ifs) { | |
5787 | if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { | |
5788 | if(hw->tx_packet_delta > MIN_NUM_XMITS) { | |
5789 | hw->in_ifs_mode = TRUE; | |
5790 | if(hw->current_ifs_val < hw->ifs_max_val) { | |
5791 | if(hw->current_ifs_val == 0) | |
5792 | hw->current_ifs_val = hw->ifs_min_val; | |
5793 | else | |
5794 | hw->current_ifs_val += hw->ifs_step_size; | |
5795 | E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); | |
5796 | } | |
5797 | } | |
5798 | } else { | |
5799 | if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { | |
5800 | hw->current_ifs_val = 0; | |
5801 | hw->in_ifs_mode = FALSE; | |
5802 | E1000_WRITE_REG(hw, AIT, 0); | |
5803 | } | |
5804 | } | |
5805 | } else { | |
5806 | DEBUGOUT("Not in Adaptive IFS mode!\n"); | |
5807 | } | |
5808 | } | |
5809 | ||
5810 | /****************************************************************************** | |
5811 | * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT | |
5812 | * | |
5813 | * hw - Struct containing variables accessed by shared code | |
5814 | * frame_len - The length of the frame in question | |
5815 | * mac_addr - The Ethernet destination address of the frame in question | |
5816 | *****************************************************************************/ | |
5817 | void | |
5818 | e1000_tbi_adjust_stats(struct e1000_hw *hw, | |
5819 | struct e1000_hw_stats *stats, | |
5820 | uint32_t frame_len, | |
5821 | uint8_t *mac_addr) | |
5822 | { | |
5823 | uint64_t carry_bit; | |
5824 | ||
5825 | /* First adjust the frame length. */ | |
5826 | frame_len--; | |
5827 | /* We need to adjust the statistics counters, since the hardware | |
5828 | * counters overcount this packet as a CRC error and undercount | |
5829 | * the packet as a good packet | |
5830 | */ | |
5831 | /* This packet should not be counted as a CRC error. */ | |
5832 | stats->crcerrs--; | |
5833 | /* This packet does count as a Good Packet Received. */ | |
5834 | stats->gprc++; | |
5835 | ||
5836 | /* Adjust the Good Octets received counters */ | |
5837 | carry_bit = 0x80000000 & stats->gorcl; | |
5838 | stats->gorcl += frame_len; | |
5839 | /* If the high bit of Gorcl (the low 32 bits of the Good Octets | |
5840 | * Received Count) was one before the addition, | |
5841 | * AND it is zero after, then we lost the carry out, | |
5842 | * need to add one to Gorch (Good Octets Received Count High). | |
5843 | * This could be simplified if all environments supported | |
5844 | * 64-bit integers. | |
5845 | */ | |
5846 | if(carry_bit && ((stats->gorcl & 0x80000000) == 0)) | |
5847 | stats->gorch++; | |
5848 | /* Is this a broadcast or multicast? Check broadcast first, | |
5849 | * since the test for a multicast frame will test positive on | |
5850 | * a broadcast frame. | |
5851 | */ | |
5852 | if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) | |
5853 | /* Broadcast packet */ | |
5854 | stats->bprc++; | |
5855 | else if(*mac_addr & 0x01) | |
5856 | /* Multicast packet */ | |
5857 | stats->mprc++; | |
5858 | ||
5859 | if(frame_len == hw->max_frame_size) { | |
5860 | /* In this case, the hardware has overcounted the number of | |
5861 | * oversize frames. | |
5862 | */ | |
5863 | if(stats->roc > 0) | |
5864 | stats->roc--; | |
5865 | } | |
5866 | ||
5867 | /* Adjust the bin counters when the extra byte put the frame in the | |
5868 | * wrong bin. Remember that the frame_len was adjusted above. | |
5869 | */ | |
5870 | if(frame_len == 64) { | |
5871 | stats->prc64++; | |
5872 | stats->prc127--; | |
5873 | } else if(frame_len == 127) { | |
5874 | stats->prc127++; | |
5875 | stats->prc255--; | |
5876 | } else if(frame_len == 255) { | |
5877 | stats->prc255++; | |
5878 | stats->prc511--; | |
5879 | } else if(frame_len == 511) { | |
5880 | stats->prc511++; | |
5881 | stats->prc1023--; | |
5882 | } else if(frame_len == 1023) { | |
5883 | stats->prc1023++; | |
5884 | stats->prc1522--; | |
5885 | } else if(frame_len == 1522) { | |
5886 | stats->prc1522++; | |
5887 | } | |
5888 | } | |
5889 | ||
5890 | /****************************************************************************** | |
5891 | * Gets the current PCI bus type, speed, and width of the hardware | |
5892 | * | |
5893 | * hw - Struct containing variables accessed by shared code | |
5894 | *****************************************************************************/ | |
5895 | void | |
5896 | e1000_get_bus_info(struct e1000_hw *hw) | |
5897 | { | |
5898 | uint32_t status; | |
5899 | ||
5900 | switch (hw->mac_type) { | |
5901 | case e1000_82542_rev2_0: | |
5902 | case e1000_82542_rev2_1: | |
5903 | hw->bus_type = e1000_bus_type_unknown; | |
5904 | hw->bus_speed = e1000_bus_speed_unknown; | |
5905 | hw->bus_width = e1000_bus_width_unknown; | |
5906 | break; | |
868d5309 | 5907 | case e1000_82572: |
2d7edb92 | 5908 | case e1000_82573: |
fd803241 JK |
5909 | hw->bus_type = e1000_bus_type_pci_express; |
5910 | hw->bus_speed = e1000_bus_speed_2500; | |
5911 | hw->bus_width = e1000_bus_width_pciex_1; | |
5912 | break; | |
5913 | case e1000_82571: | |
6418ecc6 | 5914 | case e1000_80003es2lan: |
2d7edb92 MC |
5915 | hw->bus_type = e1000_bus_type_pci_express; |
5916 | hw->bus_speed = e1000_bus_speed_2500; | |
5917 | hw->bus_width = e1000_bus_width_pciex_4; | |
5918 | break; | |
1da177e4 LT |
5919 | default: |
5920 | status = E1000_READ_REG(hw, STATUS); | |
5921 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? | |
5922 | e1000_bus_type_pcix : e1000_bus_type_pci; | |
5923 | ||
5924 | if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { | |
5925 | hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? | |
5926 | e1000_bus_speed_66 : e1000_bus_speed_120; | |
5927 | } else if(hw->bus_type == e1000_bus_type_pci) { | |
5928 | hw->bus_speed = (status & E1000_STATUS_PCI66) ? | |
5929 | e1000_bus_speed_66 : e1000_bus_speed_33; | |
5930 | } else { | |
5931 | switch (status & E1000_STATUS_PCIX_SPEED) { | |
5932 | case E1000_STATUS_PCIX_SPEED_66: | |
5933 | hw->bus_speed = e1000_bus_speed_66; | |
5934 | break; | |
5935 | case E1000_STATUS_PCIX_SPEED_100: | |
5936 | hw->bus_speed = e1000_bus_speed_100; | |
5937 | break; | |
5938 | case E1000_STATUS_PCIX_SPEED_133: | |
5939 | hw->bus_speed = e1000_bus_speed_133; | |
5940 | break; | |
5941 | default: | |
5942 | hw->bus_speed = e1000_bus_speed_reserved; | |
5943 | break; | |
5944 | } | |
5945 | } | |
5946 | hw->bus_width = (status & E1000_STATUS_BUS64) ? | |
5947 | e1000_bus_width_64 : e1000_bus_width_32; | |
5948 | break; | |
5949 | } | |
5950 | } | |
3ad2cc67 AB |
5951 | |
5952 | #if 0 | |
1da177e4 LT |
5953 | /****************************************************************************** |
5954 | * Reads a value from one of the devices registers using port I/O (as opposed | |
5955 | * memory mapped I/O). Only 82544 and newer devices support port I/O. | |
5956 | * | |
5957 | * hw - Struct containing variables accessed by shared code | |
5958 | * offset - offset to read from | |
5959 | *****************************************************************************/ | |
5960 | uint32_t | |
5961 | e1000_read_reg_io(struct e1000_hw *hw, | |
5962 | uint32_t offset) | |
5963 | { | |
5964 | unsigned long io_addr = hw->io_base; | |
5965 | unsigned long io_data = hw->io_base + 4; | |
5966 | ||
5967 | e1000_io_write(hw, io_addr, offset); | |
5968 | return e1000_io_read(hw, io_data); | |
5969 | } | |
3ad2cc67 | 5970 | #endif /* 0 */ |
1da177e4 LT |
5971 | |
5972 | /****************************************************************************** | |
5973 | * Writes a value to one of the devices registers using port I/O (as opposed to | |
5974 | * memory mapped I/O). Only 82544 and newer devices support port I/O. | |
5975 | * | |
5976 | * hw - Struct containing variables accessed by shared code | |
5977 | * offset - offset to write to | |
5978 | * value - value to write | |
5979 | *****************************************************************************/ | |
3ad2cc67 | 5980 | static void |
1da177e4 LT |
5981 | e1000_write_reg_io(struct e1000_hw *hw, |
5982 | uint32_t offset, | |
5983 | uint32_t value) | |
5984 | { | |
5985 | unsigned long io_addr = hw->io_base; | |
5986 | unsigned long io_data = hw->io_base + 4; | |
5987 | ||
5988 | e1000_io_write(hw, io_addr, offset); | |
5989 | e1000_io_write(hw, io_data, value); | |
5990 | } | |
5991 | ||
5992 | ||
5993 | /****************************************************************************** | |
5994 | * Estimates the cable length. | |
5995 | * | |
5996 | * hw - Struct containing variables accessed by shared code | |
5997 | * min_length - The estimated minimum length | |
5998 | * max_length - The estimated maximum length | |
5999 | * | |
6000 | * returns: - E1000_ERR_XXX | |
6001 | * E1000_SUCCESS | |
6002 | * | |
6003 | * This function always returns a ranged length (minimum & maximum). | |
6004 | * So for M88 phy's, this function interprets the one value returned from the | |
6005 | * register to the minimum and maximum range. | |
6006 | * For IGP phy's, the function calculates the range by the AGC registers. | |
6007 | *****************************************************************************/ | |
3ad2cc67 | 6008 | static int32_t |
1da177e4 LT |
6009 | e1000_get_cable_length(struct e1000_hw *hw, |
6010 | uint16_t *min_length, | |
6011 | uint16_t *max_length) | |
6012 | { | |
6013 | int32_t ret_val; | |
6014 | uint16_t agc_value = 0; | |
6015 | uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE; | |
868d5309 | 6016 | uint16_t max_agc = 0; |
1da177e4 LT |
6017 | uint16_t i, phy_data; |
6018 | uint16_t cable_length; | |
6019 | ||
6020 | DEBUGFUNC("e1000_get_cable_length"); | |
6021 | ||
6022 | *min_length = *max_length = 0; | |
6023 | ||
6024 | /* Use old method for Phy older than IGP */ | |
6025 | if(hw->phy_type == e1000_phy_m88) { | |
2d7edb92 | 6026 | |
1da177e4 LT |
6027 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
6028 | &phy_data); | |
6029 | if(ret_val) | |
6030 | return ret_val; | |
6031 | cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
6032 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
6033 | ||
6034 | /* Convert the enum value to ranged values */ | |
6035 | switch (cable_length) { | |
6036 | case e1000_cable_length_50: | |
6037 | *min_length = 0; | |
6038 | *max_length = e1000_igp_cable_length_50; | |
6039 | break; | |
6040 | case e1000_cable_length_50_80: | |
6041 | *min_length = e1000_igp_cable_length_50; | |
6042 | *max_length = e1000_igp_cable_length_80; | |
6043 | break; | |
6044 | case e1000_cable_length_80_110: | |
6045 | *min_length = e1000_igp_cable_length_80; | |
6046 | *max_length = e1000_igp_cable_length_110; | |
6047 | break; | |
6048 | case e1000_cable_length_110_140: | |
6049 | *min_length = e1000_igp_cable_length_110; | |
6050 | *max_length = e1000_igp_cable_length_140; | |
6051 | break; | |
6052 | case e1000_cable_length_140: | |
6053 | *min_length = e1000_igp_cable_length_140; | |
6054 | *max_length = e1000_igp_cable_length_170; | |
6055 | break; | |
6056 | default: | |
6057 | return -E1000_ERR_PHY; | |
6058 | break; | |
6059 | } | |
6418ecc6 JK |
6060 | } else if (hw->phy_type == e1000_phy_gg82563) { |
6061 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, | |
6062 | &phy_data); | |
6063 | if (ret_val) | |
6064 | return ret_val; | |
6065 | cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; | |
6066 | ||
6067 | switch (cable_length) { | |
6068 | case e1000_gg_cable_length_60: | |
6069 | *min_length = 0; | |
6070 | *max_length = e1000_igp_cable_length_60; | |
6071 | break; | |
6072 | case e1000_gg_cable_length_60_115: | |
6073 | *min_length = e1000_igp_cable_length_60; | |
6074 | *max_length = e1000_igp_cable_length_115; | |
6075 | break; | |
6076 | case e1000_gg_cable_length_115_150: | |
6077 | *min_length = e1000_igp_cable_length_115; | |
6078 | *max_length = e1000_igp_cable_length_150; | |
6079 | break; | |
6080 | case e1000_gg_cable_length_150: | |
6081 | *min_length = e1000_igp_cable_length_150; | |
6082 | *max_length = e1000_igp_cable_length_180; | |
6083 | break; | |
6084 | default: | |
6085 | return -E1000_ERR_PHY; | |
6086 | break; | |
6087 | } | |
1da177e4 LT |
6088 | } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
6089 | uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | |
6090 | {IGP01E1000_PHY_AGC_A, | |
6091 | IGP01E1000_PHY_AGC_B, | |
6092 | IGP01E1000_PHY_AGC_C, | |
6093 | IGP01E1000_PHY_AGC_D}; | |
6094 | /* Read the AGC registers for all channels */ | |
6095 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | |
6096 | ||
6097 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); | |
6098 | if(ret_val) | |
6099 | return ret_val; | |
6100 | ||
6101 | cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; | |
6102 | ||
6103 | /* Array bound check. */ | |
6104 | if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || | |
6105 | (cur_agc == 0)) | |
6106 | return -E1000_ERR_PHY; | |
6107 | ||
6108 | agc_value += cur_agc; | |
6109 | ||
6110 | /* Update minimal AGC value. */ | |
6111 | if(min_agc > cur_agc) | |
6112 | min_agc = cur_agc; | |
6113 | } | |
6114 | ||
6115 | /* Remove the minimal AGC result for length < 50m */ | |
6116 | if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { | |
6117 | agc_value -= min_agc; | |
6118 | ||
6119 | /* Get the average length of the remaining 3 channels */ | |
6120 | agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); | |
6121 | } else { | |
6122 | /* Get the average length of all the 4 channels. */ | |
6123 | agc_value /= IGP01E1000_PHY_CHANNEL_NUM; | |
6124 | } | |
6125 | ||
6126 | /* Set the range of the calculated length. */ | |
6127 | *min_length = ((e1000_igp_cable_length_table[agc_value] - | |
6128 | IGP01E1000_AGC_RANGE) > 0) ? | |
6129 | (e1000_igp_cable_length_table[agc_value] - | |
6130 | IGP01E1000_AGC_RANGE) : 0; | |
6131 | *max_length = e1000_igp_cable_length_table[agc_value] + | |
6132 | IGP01E1000_AGC_RANGE; | |
868d5309 MC |
6133 | } else if (hw->phy_type == e1000_phy_igp_2) { |
6134 | uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | |
6135 | {IGP02E1000_PHY_AGC_A, | |
6136 | IGP02E1000_PHY_AGC_B, | |
6137 | IGP02E1000_PHY_AGC_C, | |
6138 | IGP02E1000_PHY_AGC_D}; | |
6139 | /* Read the AGC registers for all channels */ | |
6140 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
6141 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); | |
6142 | if (ret_val) | |
6143 | return ret_val; | |
6144 | ||
6145 | /* Getting bits 15:9, which represent the combination of course and | |
6146 | * fine gain values. The result is a number that can be put into | |
6147 | * the lookup table to obtain the approximate cable length. */ | |
6148 | cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & | |
6149 | IGP02E1000_AGC_LENGTH_MASK; | |
6150 | ||
6151 | /* Remove min & max AGC values from calculation. */ | |
6152 | if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc]) | |
6153 | min_agc = cur_agc; | |
6154 | if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc]) | |
6155 | max_agc = cur_agc; | |
6156 | ||
6157 | agc_value += e1000_igp_2_cable_length_table[cur_agc]; | |
6158 | } | |
6159 | ||
6160 | agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]); | |
6161 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
6162 | ||
6163 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
6164 | *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
6165 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
6166 | *max_length = agc_value + IGP02E1000_AGC_RANGE; | |
1da177e4 LT |
6167 | } |
6168 | ||
6169 | return E1000_SUCCESS; | |
6170 | } | |
6171 | ||
6172 | /****************************************************************************** | |
6173 | * Check the cable polarity | |
6174 | * | |
6175 | * hw - Struct containing variables accessed by shared code | |
6176 | * polarity - output parameter : 0 - Polarity is not reversed | |
6177 | * 1 - Polarity is reversed. | |
6178 | * | |
6179 | * returns: - E1000_ERR_XXX | |
6180 | * E1000_SUCCESS | |
6181 | * | |
6182 | * For phy's older then IGP, this function simply reads the polarity bit in the | |
6183 | * Phy Status register. For IGP phy's, this bit is valid only if link speed is | |
6184 | * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will | |
6185 | * return 0. If the link speed is 1000 Mbps the polarity status is in the | |
6186 | * IGP01E1000_PHY_PCS_INIT_REG. | |
6187 | *****************************************************************************/ | |
3ad2cc67 | 6188 | static int32_t |
1da177e4 LT |
6189 | e1000_check_polarity(struct e1000_hw *hw, |
6190 | uint16_t *polarity) | |
6191 | { | |
6192 | int32_t ret_val; | |
6193 | uint16_t phy_data; | |
6194 | ||
6195 | DEBUGFUNC("e1000_check_polarity"); | |
6196 | ||
6418ecc6 JK |
6197 | if ((hw->phy_type == e1000_phy_m88) || |
6198 | (hw->phy_type == e1000_phy_gg82563)) { | |
1da177e4 LT |
6199 | /* return the Polarity bit in the Status register. */ |
6200 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, | |
6201 | &phy_data); | |
6202 | if(ret_val) | |
6203 | return ret_val; | |
6204 | *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> | |
6205 | M88E1000_PSSR_REV_POLARITY_SHIFT; | |
2d7edb92 MC |
6206 | } else if(hw->phy_type == e1000_phy_igp || |
6207 | hw->phy_type == e1000_phy_igp_2) { | |
1da177e4 LT |
6208 | /* Read the Status register to check the speed */ |
6209 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, | |
6210 | &phy_data); | |
6211 | if(ret_val) | |
6212 | return ret_val; | |
6213 | ||
6214 | /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to | |
6215 | * find the polarity status */ | |
6216 | if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == | |
6217 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
6218 | ||
6219 | /* Read the GIG initialization PCS register (0x00B4) */ | |
6220 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, | |
6221 | &phy_data); | |
6222 | if(ret_val) | |
6223 | return ret_val; | |
6224 | ||
6225 | /* Check the polarity bits */ | |
6226 | *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0; | |
6227 | } else { | |
6228 | /* For 10 Mbps, read the polarity bit in the status register. (for | |
6229 | * 100 Mbps this bit is always 0) */ | |
6230 | *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; | |
6231 | } | |
6232 | } | |
6233 | return E1000_SUCCESS; | |
6234 | } | |
6235 | ||
6236 | /****************************************************************************** | |
6237 | * Check if Downshift occured | |
6238 | * | |
6239 | * hw - Struct containing variables accessed by shared code | |
6240 | * downshift - output parameter : 0 - No Downshift ocured. | |
6241 | * 1 - Downshift ocured. | |
6242 | * | |
6243 | * returns: - E1000_ERR_XXX | |
76c224bc | 6244 | * E1000_SUCCESS |
1da177e4 LT |
6245 | * |
6246 | * For phy's older then IGP, this function reads the Downshift bit in the Phy | |
6247 | * Specific Status register. For IGP phy's, it reads the Downgrade bit in the | |
6248 | * Link Health register. In IGP this bit is latched high, so the driver must | |
6249 | * read it immediately after link is established. | |
6250 | *****************************************************************************/ | |
3ad2cc67 | 6251 | static int32_t |
1da177e4 LT |
6252 | e1000_check_downshift(struct e1000_hw *hw) |
6253 | { | |
6254 | int32_t ret_val; | |
6255 | uint16_t phy_data; | |
6256 | ||
6257 | DEBUGFUNC("e1000_check_downshift"); | |
6258 | ||
76c224bc | 6259 | if(hw->phy_type == e1000_phy_igp || |
2d7edb92 | 6260 | hw->phy_type == e1000_phy_igp_2) { |
1da177e4 LT |
6261 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
6262 | &phy_data); | |
6263 | if(ret_val) | |
6264 | return ret_val; | |
6265 | ||
6266 | hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; | |
6418ecc6 JK |
6267 | } else if ((hw->phy_type == e1000_phy_m88) || |
6268 | (hw->phy_type == e1000_phy_gg82563)) { | |
1da177e4 LT |
6269 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
6270 | &phy_data); | |
6271 | if(ret_val) | |
6272 | return ret_val; | |
6273 | ||
6274 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> | |
6275 | M88E1000_PSSR_DOWNSHIFT_SHIFT; | |
6276 | } | |
2d7edb92 | 6277 | |
1da177e4 LT |
6278 | return E1000_SUCCESS; |
6279 | } | |
6280 | ||
6281 | /***************************************************************************** | |
6282 | * | |
6283 | * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a | |
6284 | * gigabit link is achieved to improve link quality. | |
6285 | * | |
6286 | * hw: Struct containing variables accessed by shared code | |
6287 | * | |
6288 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
6289 | * E1000_SUCCESS at any other case. | |
6290 | * | |
6291 | ****************************************************************************/ | |
6292 | ||
3ad2cc67 | 6293 | static int32_t |
1da177e4 LT |
6294 | e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
6295 | boolean_t link_up) | |
6296 | { | |
6297 | int32_t ret_val; | |
6298 | uint16_t phy_data, phy_saved_data, speed, duplex, i; | |
6299 | uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = | |
6300 | {IGP01E1000_PHY_AGC_PARAM_A, | |
6301 | IGP01E1000_PHY_AGC_PARAM_B, | |
6302 | IGP01E1000_PHY_AGC_PARAM_C, | |
6303 | IGP01E1000_PHY_AGC_PARAM_D}; | |
6304 | uint16_t min_length, max_length; | |
6305 | ||
6306 | DEBUGFUNC("e1000_config_dsp_after_link_change"); | |
6307 | ||
6308 | if(hw->phy_type != e1000_phy_igp) | |
6309 | return E1000_SUCCESS; | |
6310 | ||
6311 | if(link_up) { | |
6312 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); | |
6313 | if(ret_val) { | |
6314 | DEBUGOUT("Error getting link speed and duplex\n"); | |
6315 | return ret_val; | |
6316 | } | |
6317 | ||
6318 | if(speed == SPEED_1000) { | |
6319 | ||
6320 | e1000_get_cable_length(hw, &min_length, &max_length); | |
6321 | ||
6322 | if((hw->dsp_config_state == e1000_dsp_config_enabled) && | |
6323 | min_length >= e1000_igp_cable_length_50) { | |
6324 | ||
6325 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | |
6326 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], | |
6327 | &phy_data); | |
6328 | if(ret_val) | |
6329 | return ret_val; | |
6330 | ||
6331 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | |
6332 | ||
6333 | ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], | |
6334 | phy_data); | |
6335 | if(ret_val) | |
6336 | return ret_val; | |
6337 | } | |
6338 | hw->dsp_config_state = e1000_dsp_config_activated; | |
6339 | } | |
6340 | ||
6341 | if((hw->ffe_config_state == e1000_ffe_config_enabled) && | |
6342 | (min_length < e1000_igp_cable_length_50)) { | |
6343 | ||
6344 | uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; | |
6345 | uint32_t idle_errs = 0; | |
6346 | ||
6347 | /* clear previous idle error counts */ | |
6348 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, | |
6349 | &phy_data); | |
6350 | if(ret_val) | |
6351 | return ret_val; | |
6352 | ||
6353 | for(i = 0; i < ffe_idle_err_timeout; i++) { | |
6354 | udelay(1000); | |
6355 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, | |
6356 | &phy_data); | |
6357 | if(ret_val) | |
6358 | return ret_val; | |
6359 | ||
6360 | idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); | |
6361 | if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { | |
6362 | hw->ffe_config_state = e1000_ffe_config_active; | |
6363 | ||
6364 | ret_val = e1000_write_phy_reg(hw, | |
6365 | IGP01E1000_PHY_DSP_FFE, | |
6366 | IGP01E1000_PHY_DSP_FFE_CM_CP); | |
6367 | if(ret_val) | |
6368 | return ret_val; | |
6369 | break; | |
6370 | } | |
6371 | ||
6372 | if(idle_errs) | |
6373 | ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; | |
6374 | } | |
6375 | } | |
6376 | } | |
6377 | } else { | |
6378 | if(hw->dsp_config_state == e1000_dsp_config_activated) { | |
6379 | /* Save off the current value of register 0x2F5B to be restored at | |
6380 | * the end of the routines. */ | |
6381 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
6382 | ||
6383 | if(ret_val) | |
6384 | return ret_val; | |
6385 | ||
6386 | /* Disable the PHY transmitter */ | |
6387 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
6388 | ||
6389 | if(ret_val) | |
6390 | return ret_val; | |
6391 | ||
2d7edb92 | 6392 | msec_delay_irq(20); |
1da177e4 LT |
6393 | |
6394 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
6395 | IGP01E1000_IEEE_FORCE_GIGA); | |
6396 | if(ret_val) | |
6397 | return ret_val; | |
6398 | for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { | |
6399 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); | |
6400 | if(ret_val) | |
6401 | return ret_val; | |
6402 | ||
6403 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; | |
6404 | phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; | |
6405 | ||
6406 | ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); | |
6407 | if(ret_val) | |
6408 | return ret_val; | |
6409 | } | |
6410 | ||
6411 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
6412 | IGP01E1000_IEEE_RESTART_AUTONEG); | |
6413 | if(ret_val) | |
6414 | return ret_val; | |
6415 | ||
2d7edb92 | 6416 | msec_delay_irq(20); |
1da177e4 LT |
6417 | |
6418 | /* Now enable the transmitter */ | |
6419 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
6420 | ||
6421 | if(ret_val) | |
6422 | return ret_val; | |
6423 | ||
6424 | hw->dsp_config_state = e1000_dsp_config_enabled; | |
6425 | } | |
6426 | ||
6427 | if(hw->ffe_config_state == e1000_ffe_config_active) { | |
6428 | /* Save off the current value of register 0x2F5B to be restored at | |
6429 | * the end of the routines. */ | |
6430 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); | |
6431 | ||
6432 | if(ret_val) | |
6433 | return ret_val; | |
6434 | ||
6435 | /* Disable the PHY transmitter */ | |
6436 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); | |
6437 | ||
6438 | if(ret_val) | |
6439 | return ret_val; | |
6440 | ||
2d7edb92 | 6441 | msec_delay_irq(20); |
1da177e4 LT |
6442 | |
6443 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
6444 | IGP01E1000_IEEE_FORCE_GIGA); | |
6445 | if(ret_val) | |
6446 | return ret_val; | |
6447 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, | |
6448 | IGP01E1000_PHY_DSP_FFE_DEFAULT); | |
6449 | if(ret_val) | |
6450 | return ret_val; | |
6451 | ||
6452 | ret_val = e1000_write_phy_reg(hw, 0x0000, | |
6453 | IGP01E1000_IEEE_RESTART_AUTONEG); | |
6454 | if(ret_val) | |
6455 | return ret_val; | |
6456 | ||
2d7edb92 | 6457 | msec_delay_irq(20); |
1da177e4 LT |
6458 | |
6459 | /* Now enable the transmitter */ | |
6460 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | |
6461 | ||
6462 | if(ret_val) | |
6463 | return ret_val; | |
6464 | ||
6465 | hw->ffe_config_state = e1000_ffe_config_enabled; | |
6466 | } | |
6467 | } | |
6468 | return E1000_SUCCESS; | |
6469 | } | |
6470 | ||
6471 | /***************************************************************************** | |
6472 | * Set PHY to class A mode | |
6473 | * Assumes the following operations will follow to enable the new class mode. | |
6474 | * 1. Do a PHY soft reset | |
6475 | * 2. Restart auto-negotiation or force link. | |
6476 | * | |
6477 | * hw - Struct containing variables accessed by shared code | |
6478 | ****************************************************************************/ | |
6479 | static int32_t | |
6480 | e1000_set_phy_mode(struct e1000_hw *hw) | |
6481 | { | |
6482 | int32_t ret_val; | |
6483 | uint16_t eeprom_data; | |
6484 | ||
6485 | DEBUGFUNC("e1000_set_phy_mode"); | |
6486 | ||
6487 | if((hw->mac_type == e1000_82545_rev_3) && | |
6488 | (hw->media_type == e1000_media_type_copper)) { | |
6489 | ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); | |
6490 | if(ret_val) { | |
6491 | return ret_val; | |
6492 | } | |
6493 | ||
6494 | if((eeprom_data != EEPROM_RESERVED_WORD) && | |
6495 | (eeprom_data & EEPROM_PHY_CLASS_A)) { | |
6496 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); | |
6497 | if(ret_val) | |
6498 | return ret_val; | |
6499 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); | |
6500 | if(ret_val) | |
6501 | return ret_val; | |
6502 | ||
6503 | hw->phy_reset_disable = FALSE; | |
6504 | } | |
6505 | } | |
6506 | ||
6507 | return E1000_SUCCESS; | |
6508 | } | |
6509 | ||
6510 | /***************************************************************************** | |
6511 | * | |
6512 | * This function sets the lplu state according to the active flag. When | |
6513 | * activating lplu this function also disables smart speed and vise versa. | |
6514 | * lplu will not be activated unless the device autonegotiation advertisment | |
6515 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
6516 | * hw: Struct containing variables accessed by shared code | |
6517 | * active - true to enable lplu false to disable lplu. | |
6518 | * | |
6519 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
6520 | * E1000_SUCCESS at any other case. | |
6521 | * | |
6522 | ****************************************************************************/ | |
6523 | ||
3ad2cc67 | 6524 | static int32_t |
1da177e4 LT |
6525 | e1000_set_d3_lplu_state(struct e1000_hw *hw, |
6526 | boolean_t active) | |
6527 | { | |
6528 | int32_t ret_val; | |
6529 | uint16_t phy_data; | |
6530 | DEBUGFUNC("e1000_set_d3_lplu_state"); | |
6531 | ||
2d7edb92 | 6532 | if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2) |
1da177e4 LT |
6533 | return E1000_SUCCESS; |
6534 | ||
6535 | /* During driver activity LPLU should not be used or it will attain link | |
6536 | * from the lowest speeds starting from 10Mbps. The capability is used for | |
6537 | * Dx transitions and states */ | |
2d7edb92 MC |
6538 | if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { |
6539 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); | |
6540 | if(ret_val) | |
6541 | return ret_val; | |
6542 | } else { | |
6543 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); | |
1da177e4 LT |
6544 | if(ret_val) |
6545 | return ret_val; | |
2d7edb92 MC |
6546 | } |
6547 | ||
6548 | if(!active) { | |
6549 | if(hw->mac_type == e1000_82541_rev_2 || | |
6550 | hw->mac_type == e1000_82547_rev_2) { | |
6551 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; | |
6552 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | |
6553 | if(ret_val) | |
6554 | return ret_val; | |
6555 | } else { | |
6556 | phy_data &= ~IGP02E1000_PM_D3_LPLU; | |
6557 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
6558 | phy_data); | |
6559 | if (ret_val) | |
6560 | return ret_val; | |
6561 | } | |
1da177e4 LT |
6562 | |
6563 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | |
6564 | * Dx states where the power conservation is most important. During | |
6565 | * driver activity we should enable SmartSpeed, so performance is | |
6566 | * maintained. */ | |
6567 | if (hw->smart_speed == e1000_smart_speed_on) { | |
6568 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
6569 | &phy_data); | |
6570 | if(ret_val) | |
6571 | return ret_val; | |
6572 | ||
6573 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
6574 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
6575 | phy_data); | |
6576 | if(ret_val) | |
6577 | return ret_val; | |
6578 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
6579 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
6580 | &phy_data); | |
6581 | if (ret_val) | |
6582 | return ret_val; | |
6583 | ||
6584 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
6585 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
6586 | phy_data); | |
6587 | if(ret_val) | |
6588 | return ret_val; | |
6589 | } | |
6590 | ||
6591 | } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || | |
6592 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || | |
6593 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { | |
6594 | ||
2d7edb92 MC |
6595 | if(hw->mac_type == e1000_82541_rev_2 || |
6596 | hw->mac_type == e1000_82547_rev_2) { | |
6597 | phy_data |= IGP01E1000_GMII_FLEX_SPD; | |
6598 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | |
6599 | if(ret_val) | |
6600 | return ret_val; | |
6601 | } else { | |
6602 | phy_data |= IGP02E1000_PM_D3_LPLU; | |
6603 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | |
6604 | phy_data); | |
6605 | if (ret_val) | |
6606 | return ret_val; | |
6607 | } | |
6608 | ||
6609 | /* When LPLU is enabled we should disable SmartSpeed */ | |
6610 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
6611 | if(ret_val) | |
6612 | return ret_val; | |
6613 | ||
6614 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
6615 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
6616 | if(ret_val) | |
6617 | return ret_val; | |
6618 | ||
6619 | } | |
6620 | return E1000_SUCCESS; | |
6621 | } | |
6622 | ||
6623 | /***************************************************************************** | |
6624 | * | |
6625 | * This function sets the lplu d0 state according to the active flag. When | |
6626 | * activating lplu this function also disables smart speed and vise versa. | |
6627 | * lplu will not be activated unless the device autonegotiation advertisment | |
6628 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | |
6629 | * hw: Struct containing variables accessed by shared code | |
6630 | * active - true to enable lplu false to disable lplu. | |
6631 | * | |
6632 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | |
6633 | * E1000_SUCCESS at any other case. | |
6634 | * | |
6635 | ****************************************************************************/ | |
6636 | ||
3ad2cc67 | 6637 | static int32_t |
2d7edb92 MC |
6638 | e1000_set_d0_lplu_state(struct e1000_hw *hw, |
6639 | boolean_t active) | |
6640 | { | |
6641 | int32_t ret_val; | |
6642 | uint16_t phy_data; | |
6643 | DEBUGFUNC("e1000_set_d0_lplu_state"); | |
6644 | ||
6645 | if(hw->mac_type <= e1000_82547_rev_2) | |
6646 | return E1000_SUCCESS; | |
6647 | ||
6648 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); | |
1da177e4 LT |
6649 | if(ret_val) |
6650 | return ret_val; | |
6651 | ||
2d7edb92 MC |
6652 | if (!active) { |
6653 | phy_data &= ~IGP02E1000_PM_D0_LPLU; | |
6654 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | |
6655 | if (ret_val) | |
6656 | return ret_val; | |
6657 | ||
6658 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | |
6659 | * Dx states where the power conservation is most important. During | |
6660 | * driver activity we should enable SmartSpeed, so performance is | |
6661 | * maintained. */ | |
6662 | if (hw->smart_speed == e1000_smart_speed_on) { | |
6663 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
6664 | &phy_data); | |
6665 | if(ret_val) | |
6666 | return ret_val; | |
6667 | ||
6668 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | |
6669 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
6670 | phy_data); | |
6671 | if(ret_val) | |
6672 | return ret_val; | |
6673 | } else if (hw->smart_speed == e1000_smart_speed_off) { | |
6674 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
6675 | &phy_data); | |
6676 | if (ret_val) | |
6677 | return ret_val; | |
6678 | ||
6679 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
6680 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | |
6681 | phy_data); | |
6682 | if(ret_val) | |
6683 | return ret_val; | |
6684 | } | |
6685 | ||
6686 | ||
6687 | } else { | |
76c224bc AK |
6688 | |
6689 | phy_data |= IGP02E1000_PM_D0_LPLU; | |
2d7edb92 MC |
6690 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
6691 | if (ret_val) | |
6692 | return ret_val; | |
6693 | ||
1da177e4 LT |
6694 | /* When LPLU is enabled we should disable SmartSpeed */ |
6695 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | |
6696 | if(ret_val) | |
6697 | return ret_val; | |
6698 | ||
6699 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
6700 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | |
6701 | if(ret_val) | |
6702 | return ret_val; | |
6703 | ||
6704 | } | |
6705 | return E1000_SUCCESS; | |
6706 | } | |
6707 | ||
6708 | /****************************************************************************** | |
6709 | * Change VCO speed register to improve Bit Error Rate performance of SERDES. | |
6710 | * | |
6711 | * hw - Struct containing variables accessed by shared code | |
6712 | *****************************************************************************/ | |
6713 | static int32_t | |
6714 | e1000_set_vco_speed(struct e1000_hw *hw) | |
6715 | { | |
6716 | int32_t ret_val; | |
6717 | uint16_t default_page = 0; | |
6718 | uint16_t phy_data; | |
6719 | ||
6720 | DEBUGFUNC("e1000_set_vco_speed"); | |
6721 | ||
6722 | switch(hw->mac_type) { | |
6723 | case e1000_82545_rev_3: | |
6724 | case e1000_82546_rev_3: | |
6725 | break; | |
6726 | default: | |
6727 | return E1000_SUCCESS; | |
6728 | } | |
6729 | ||
6730 | /* Set PHY register 30, page 5, bit 8 to 0 */ | |
6731 | ||
6732 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); | |
6733 | if(ret_val) | |
6734 | return ret_val; | |
6735 | ||
6736 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); | |
6737 | if(ret_val) | |
6738 | return ret_val; | |
6739 | ||
6740 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); | |
6741 | if(ret_val) | |
6742 | return ret_val; | |
6743 | ||
6744 | phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; | |
6745 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | |
6746 | if(ret_val) | |
6747 | return ret_val; | |
6748 | ||
6749 | /* Set PHY register 30, page 4, bit 11 to 1 */ | |
6750 | ||
6751 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); | |
6752 | if(ret_val) | |
6753 | return ret_val; | |
6754 | ||
6755 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); | |
6756 | if(ret_val) | |
6757 | return ret_val; | |
6758 | ||
6759 | phy_data |= M88E1000_PHY_VCO_REG_BIT11; | |
6760 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); | |
6761 | if(ret_val) | |
6762 | return ret_val; | |
6763 | ||
6764 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); | |
6765 | if(ret_val) | |
6766 | return ret_val; | |
6767 | ||
6768 | return E1000_SUCCESS; | |
6769 | } | |
6770 | ||
1da177e4 | 6771 | |
2d7edb92 MC |
6772 | /***************************************************************************** |
6773 | * This function reads the cookie from ARC ram. | |
6774 | * | |
6775 | * returns: - E1000_SUCCESS . | |
6776 | ****************************************************************************/ | |
6777 | int32_t | |
6778 | e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) | |
6779 | { | |
6780 | uint8_t i; | |
76c224bc | 6781 | uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; |
2d7edb92 | 6782 | uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; |
1da177e4 | 6783 | |
2d7edb92 MC |
6784 | length = (length >> 2); |
6785 | offset = (offset >> 2); | |
1da177e4 | 6786 | |
2d7edb92 MC |
6787 | for (i = 0; i < length; i++) { |
6788 | *((uint32_t *) buffer + i) = | |
6789 | E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); | |
6790 | } | |
6791 | return E1000_SUCCESS; | |
6792 | } | |
6793 | ||
6794 | ||
6795 | /***************************************************************************** | |
6796 | * This function checks whether the HOST IF is enabled for command operaton | |
6797 | * and also checks whether the previous command is completed. | |
6798 | * It busy waits in case of previous command is not completed. | |
6799 | * | |
76c224bc | 6800 | * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or |
2d7edb92 MC |
6801 | * timeout |
6802 | * - E1000_SUCCESS for success. | |
6803 | ****************************************************************************/ | |
3ad2cc67 | 6804 | static int32_t |
2d7edb92 MC |
6805 | e1000_mng_enable_host_if(struct e1000_hw * hw) |
6806 | { | |
6807 | uint32_t hicr; | |
6808 | uint8_t i; | |
6809 | ||
6810 | /* Check that the host interface is enabled. */ | |
6811 | hicr = E1000_READ_REG(hw, HICR); | |
6812 | if ((hicr & E1000_HICR_EN) == 0) { | |
6813 | DEBUGOUT("E1000_HOST_EN bit disabled.\n"); | |
6814 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
6815 | } | |
6816 | /* check the previous command is completed */ | |
6817 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { | |
6818 | hicr = E1000_READ_REG(hw, HICR); | |
6819 | if (!(hicr & E1000_HICR_C)) | |
6820 | break; | |
6821 | msec_delay_irq(1); | |
6822 | } | |
6823 | ||
76c224bc | 6824 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
2d7edb92 MC |
6825 | DEBUGOUT("Previous command timeout failed .\n"); |
6826 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | |
6827 | } | |
6828 | return E1000_SUCCESS; | |
6829 | } | |
6830 | ||
6831 | /***************************************************************************** | |
6832 | * This function writes the buffer content at the offset given on the host if. | |
6833 | * It also does alignment considerations to do the writes in most efficient way. | |
6834 | * Also fills up the sum of the buffer in *buffer parameter. | |
6835 | * | |
6836 | * returns - E1000_SUCCESS for success. | |
6837 | ****************************************************************************/ | |
3ad2cc67 | 6838 | static int32_t |
2d7edb92 MC |
6839 | e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, |
6840 | uint16_t length, uint16_t offset, uint8_t *sum) | |
6841 | { | |
6842 | uint8_t *tmp; | |
6843 | uint8_t *bufptr = buffer; | |
6844 | uint32_t data; | |
6845 | uint16_t remaining, i, j, prev_bytes; | |
6846 | ||
6847 | /* sum = only sum of the data and it is not checksum */ | |
6848 | ||
6849 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { | |
6850 | return -E1000_ERR_PARAM; | |
6851 | } | |
6852 | ||
6853 | tmp = (uint8_t *)&data; | |
6854 | prev_bytes = offset & 0x3; | |
6855 | offset &= 0xFFFC; | |
6856 | offset >>= 2; | |
6857 | ||
6858 | if (prev_bytes) { | |
6859 | data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); | |
6860 | for (j = prev_bytes; j < sizeof(uint32_t); j++) { | |
6861 | *(tmp + j) = *bufptr++; | |
6862 | *sum += *(tmp + j); | |
6863 | } | |
6864 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); | |
6865 | length -= j - prev_bytes; | |
6866 | offset++; | |
6867 | } | |
6868 | ||
6869 | remaining = length & 0x3; | |
6870 | length -= remaining; | |
6871 | ||
6872 | /* Calculate length in DWORDs */ | |
6873 | length >>= 2; | |
6874 | ||
6875 | /* The device driver writes the relevant command block into the | |
6876 | * ram area. */ | |
6877 | for (i = 0; i < length; i++) { | |
6878 | for (j = 0; j < sizeof(uint32_t); j++) { | |
6879 | *(tmp + j) = *bufptr++; | |
6880 | *sum += *(tmp + j); | |
6881 | } | |
6882 | ||
6883 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | |
6884 | } | |
6885 | if (remaining) { | |
6886 | for (j = 0; j < sizeof(uint32_t); j++) { | |
6887 | if (j < remaining) | |
6888 | *(tmp + j) = *bufptr++; | |
6889 | else | |
6890 | *(tmp + j) = 0; | |
6891 | ||
6892 | *sum += *(tmp + j); | |
6893 | } | |
6894 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | |
6895 | } | |
6896 | ||
6897 | return E1000_SUCCESS; | |
6898 | } | |
6899 | ||
6900 | ||
6901 | /***************************************************************************** | |
6902 | * This function writes the command header after does the checksum calculation. | |
6903 | * | |
6904 | * returns - E1000_SUCCESS for success. | |
6905 | ****************************************************************************/ | |
3ad2cc67 | 6906 | static int32_t |
2d7edb92 MC |
6907 | e1000_mng_write_cmd_header(struct e1000_hw * hw, |
6908 | struct e1000_host_mng_command_header * hdr) | |
6909 | { | |
6910 | uint16_t i; | |
6911 | uint8_t sum; | |
6912 | uint8_t *buffer; | |
6913 | ||
6914 | /* Write the whole command header structure which includes sum of | |
6915 | * the buffer */ | |
6916 | ||
6917 | uint16_t length = sizeof(struct e1000_host_mng_command_header); | |
6918 | ||
6919 | sum = hdr->checksum; | |
6920 | hdr->checksum = 0; | |
6921 | ||
6922 | buffer = (uint8_t *) hdr; | |
6923 | i = length; | |
6924 | while(i--) | |
6925 | sum += buffer[i]; | |
6926 | ||
6927 | hdr->checksum = 0 - sum; | |
6928 | ||
6929 | length >>= 2; | |
6930 | /* The device driver writes the relevant command block into the ram area. */ | |
6931 | for (i = 0; i < length; i++) | |
6932 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); | |
6933 | ||
6934 | return E1000_SUCCESS; | |
6935 | } | |
6936 | ||
6937 | ||
6938 | /***************************************************************************** | |
6939 | * This function indicates to ARC that a new command is pending which completes | |
6940 | * one write operation by the driver. | |
6941 | * | |
6942 | * returns - E1000_SUCCESS for success. | |
6943 | ****************************************************************************/ | |
3ad2cc67 | 6944 | static int32_t |
2d7edb92 MC |
6945 | e1000_mng_write_commit( |
6946 | struct e1000_hw * hw) | |
6947 | { | |
6948 | uint32_t hicr; | |
6949 | ||
6950 | hicr = E1000_READ_REG(hw, HICR); | |
6951 | /* Setting this bit tells the ARC that a new command is pending. */ | |
6952 | E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); | |
6953 | ||
6954 | return E1000_SUCCESS; | |
6955 | } | |
6956 | ||
6957 | ||
6958 | /***************************************************************************** | |
6959 | * This function checks the mode of the firmware. | |
6960 | * | |
6961 | * returns - TRUE when the mode is IAMT or FALSE. | |
6962 | ****************************************************************************/ | |
6963 | boolean_t | |
6964 | e1000_check_mng_mode( | |
6965 | struct e1000_hw *hw) | |
6966 | { | |
6967 | uint32_t fwsm; | |
6968 | ||
6969 | fwsm = E1000_READ_REG(hw, FWSM); | |
6970 | ||
6971 | if((fwsm & E1000_FWSM_MODE_MASK) == | |
6972 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | |
6973 | return TRUE; | |
6974 | ||
6975 | return FALSE; | |
6976 | } | |
6977 | ||
6978 | ||
6979 | /***************************************************************************** | |
6980 | * This function writes the dhcp info . | |
6981 | ****************************************************************************/ | |
6982 | int32_t | |
6983 | e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, | |
6984 | uint16_t length) | |
6985 | { | |
6986 | int32_t ret_val; | |
6987 | struct e1000_host_mng_command_header hdr; | |
6988 | ||
6989 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; | |
6990 | hdr.command_length = length; | |
6991 | hdr.reserved1 = 0; | |
6992 | hdr.reserved2 = 0; | |
6993 | hdr.checksum = 0; | |
6994 | ||
6995 | ret_val = e1000_mng_enable_host_if(hw); | |
6996 | if (ret_val == E1000_SUCCESS) { | |
6997 | ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), | |
6998 | &(hdr.checksum)); | |
6999 | if (ret_val == E1000_SUCCESS) { | |
7000 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); | |
7001 | if (ret_val == E1000_SUCCESS) | |
7002 | ret_val = e1000_mng_write_commit(hw); | |
7003 | } | |
7004 | } | |
7005 | return ret_val; | |
7006 | } | |
7007 | ||
7008 | ||
7009 | /***************************************************************************** | |
7010 | * This function calculates the checksum. | |
7011 | * | |
7012 | * returns - checksum of buffer contents. | |
7013 | ****************************************************************************/ | |
7014 | uint8_t | |
7015 | e1000_calculate_mng_checksum(char *buffer, uint32_t length) | |
7016 | { | |
7017 | uint8_t sum = 0; | |
7018 | uint32_t i; | |
7019 | ||
7020 | if (!buffer) | |
7021 | return 0; | |
7022 | ||
7023 | for (i=0; i < length; i++) | |
7024 | sum += buffer[i]; | |
7025 | ||
7026 | return (uint8_t) (0 - sum); | |
7027 | } | |
7028 | ||
7029 | /***************************************************************************** | |
7030 | * This function checks whether tx pkt filtering needs to be enabled or not. | |
7031 | * | |
7032 | * returns - TRUE for packet filtering or FALSE. | |
7033 | ****************************************************************************/ | |
7034 | boolean_t | |
7035 | e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) | |
7036 | { | |
7037 | /* called in init as well as watchdog timer functions */ | |
7038 | ||
7039 | int32_t ret_val, checksum; | |
7040 | boolean_t tx_filter = FALSE; | |
7041 | struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); | |
7042 | uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); | |
7043 | ||
7044 | if (e1000_check_mng_mode(hw)) { | |
7045 | ret_val = e1000_mng_enable_host_if(hw); | |
7046 | if (ret_val == E1000_SUCCESS) { | |
7047 | ret_val = e1000_host_if_read_cookie(hw, buffer); | |
7048 | if (ret_val == E1000_SUCCESS) { | |
7049 | checksum = hdr->checksum; | |
7050 | hdr->checksum = 0; | |
7051 | if ((hdr->signature == E1000_IAMT_SIGNATURE) && | |
7052 | checksum == e1000_calculate_mng_checksum((char *)buffer, | |
7053 | E1000_MNG_DHCP_COOKIE_LENGTH)) { | |
7054 | if (hdr->status & | |
7055 | E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) | |
7056 | tx_filter = TRUE; | |
7057 | } else | |
7058 | tx_filter = TRUE; | |
7059 | } else | |
7060 | tx_filter = TRUE; | |
7061 | } | |
7062 | } | |
7063 | ||
7064 | hw->tx_pkt_filtering = tx_filter; | |
7065 | return tx_filter; | |
7066 | } | |
7067 | ||
7068 | /****************************************************************************** | |
7069 | * Verifies the hardware needs to allow ARPs to be processed by the host | |
7070 | * | |
7071 | * hw - Struct containing variables accessed by shared code | |
7072 | * | |
7073 | * returns: - TRUE/FALSE | |
7074 | * | |
7075 | *****************************************************************************/ | |
7076 | uint32_t | |
7077 | e1000_enable_mng_pass_thru(struct e1000_hw *hw) | |
7078 | { | |
7079 | uint32_t manc; | |
7080 | uint32_t fwsm, factps; | |
7081 | ||
7082 | if (hw->asf_firmware_present) { | |
7083 | manc = E1000_READ_REG(hw, MANC); | |
7084 | ||
7085 | if (!(manc & E1000_MANC_RCV_TCO_EN) || | |
7086 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) | |
7087 | return FALSE; | |
7088 | if (e1000_arc_subsystem_valid(hw) == TRUE) { | |
7089 | fwsm = E1000_READ_REG(hw, FWSM); | |
7090 | factps = E1000_READ_REG(hw, FACTPS); | |
7091 | ||
7092 | if (((fwsm & E1000_FWSM_MODE_MASK) == | |
7093 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) && | |
7094 | (factps & E1000_FACTPS_MNGCG)) | |
7095 | return TRUE; | |
7096 | } else | |
7097 | if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) | |
7098 | return TRUE; | |
7099 | } | |
7100 | return FALSE; | |
7101 | } | |
7102 | ||
7103 | static int32_t | |
7104 | e1000_polarity_reversal_workaround(struct e1000_hw *hw) | |
7105 | { | |
7106 | int32_t ret_val; | |
7107 | uint16_t mii_status_reg; | |
7108 | uint16_t i; | |
7109 | ||
7110 | /* Polarity reversal workaround for forced 10F/10H links. */ | |
7111 | ||
7112 | /* Disable the transmitter on the PHY */ | |
7113 | ||
7114 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | |
1da177e4 LT |
7115 | if(ret_val) |
7116 | return ret_val; | |
7117 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); | |
7118 | if(ret_val) | |
7119 | return ret_val; | |
7120 | ||
7121 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | |
7122 | if(ret_val) | |
7123 | return ret_val; | |
7124 | ||
7125 | /* This loop will early-out if the NO link condition has been met. */ | |
7126 | for(i = PHY_FORCE_TIME; i > 0; i--) { | |
7127 | /* Read the MII Status Register and wait for Link Status bit | |
7128 | * to be clear. | |
7129 | */ | |
7130 | ||
7131 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
7132 | if(ret_val) | |
7133 | return ret_val; | |
7134 | ||
7135 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
7136 | if(ret_val) | |
7137 | return ret_val; | |
7138 | ||
7139 | if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; | |
7140 | msec_delay_irq(100); | |
7141 | } | |
7142 | ||
7143 | /* Recommended delay time after link has been lost */ | |
7144 | msec_delay_irq(1000); | |
7145 | ||
7146 | /* Now we will re-enable th transmitter on the PHY */ | |
7147 | ||
7148 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); | |
7149 | if(ret_val) | |
7150 | return ret_val; | |
7151 | msec_delay_irq(50); | |
7152 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); | |
7153 | if(ret_val) | |
7154 | return ret_val; | |
7155 | msec_delay_irq(50); | |
7156 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); | |
7157 | if(ret_val) | |
7158 | return ret_val; | |
7159 | msec_delay_irq(50); | |
7160 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); | |
7161 | if(ret_val) | |
7162 | return ret_val; | |
7163 | ||
7164 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); | |
7165 | if(ret_val) | |
7166 | return ret_val; | |
7167 | ||
7168 | /* This loop will early-out if the link condition has been met. */ | |
7169 | for(i = PHY_FORCE_TIME; i > 0; i--) { | |
7170 | /* Read the MII Status Register and wait for Link Status bit | |
7171 | * to be set. | |
7172 | */ | |
7173 | ||
7174 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
7175 | if(ret_val) | |
7176 | return ret_val; | |
7177 | ||
7178 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); | |
7179 | if(ret_val) | |
7180 | return ret_val; | |
7181 | ||
7182 | if(mii_status_reg & MII_SR_LINK_STATUS) break; | |
7183 | msec_delay_irq(100); | |
7184 | } | |
7185 | return E1000_SUCCESS; | |
7186 | } | |
7187 | ||
2d7edb92 MC |
7188 | /*************************************************************************** |
7189 | * | |
7190 | * Disables PCI-Express master access. | |
7191 | * | |
7192 | * hw: Struct containing variables accessed by shared code | |
7193 | * | |
7194 | * returns: - none. | |
7195 | * | |
7196 | ***************************************************************************/ | |
3ad2cc67 | 7197 | static void |
2d7edb92 MC |
7198 | e1000_set_pci_express_master_disable(struct e1000_hw *hw) |
7199 | { | |
7200 | uint32_t ctrl; | |
7201 | ||
7202 | DEBUGFUNC("e1000_set_pci_express_master_disable"); | |
7203 | ||
7204 | if (hw->bus_type != e1000_bus_type_pci_express) | |
7205 | return; | |
7206 | ||
7207 | ctrl = E1000_READ_REG(hw, CTRL); | |
7208 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; | |
7209 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
7210 | } | |
7211 | ||
3ad2cc67 | 7212 | #if 0 |
2d7edb92 MC |
7213 | /*************************************************************************** |
7214 | * | |
7215 | * Enables PCI-Express master access. | |
7216 | * | |
7217 | * hw: Struct containing variables accessed by shared code | |
7218 | * | |
7219 | * returns: - none. | |
7220 | * | |
7221 | ***************************************************************************/ | |
7222 | void | |
7223 | e1000_enable_pciex_master(struct e1000_hw *hw) | |
7224 | { | |
7225 | uint32_t ctrl; | |
7226 | ||
7227 | DEBUGFUNC("e1000_enable_pciex_master"); | |
7228 | ||
7229 | if (hw->bus_type != e1000_bus_type_pci_express) | |
7230 | return; | |
7231 | ||
7232 | ctrl = E1000_READ_REG(hw, CTRL); | |
7233 | ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; | |
7234 | E1000_WRITE_REG(hw, CTRL, ctrl); | |
7235 | } | |
3ad2cc67 | 7236 | #endif /* 0 */ |
2d7edb92 MC |
7237 | |
7238 | /******************************************************************************* | |
7239 | * | |
7240 | * Disables PCI-Express master access and verifies there are no pending requests | |
7241 | * | |
7242 | * hw: Struct containing variables accessed by shared code | |
7243 | * | |
7244 | * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't | |
7245 | * caused the master requests to be disabled. | |
7246 | * E1000_SUCCESS master requests disabled. | |
7247 | * | |
7248 | ******************************************************************************/ | |
7249 | int32_t | |
7250 | e1000_disable_pciex_master(struct e1000_hw *hw) | |
7251 | { | |
7252 | int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ | |
7253 | ||
7254 | DEBUGFUNC("e1000_disable_pciex_master"); | |
7255 | ||
7256 | if (hw->bus_type != e1000_bus_type_pci_express) | |
7257 | return E1000_SUCCESS; | |
7258 | ||
7259 | e1000_set_pci_express_master_disable(hw); | |
7260 | ||
7261 | while(timeout) { | |
7262 | if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) | |
7263 | break; | |
7264 | else | |
7265 | udelay(100); | |
7266 | timeout--; | |
7267 | } | |
7268 | ||
7269 | if(!timeout) { | |
7270 | DEBUGOUT("Master requests are pending.\n"); | |
7271 | return -E1000_ERR_MASTER_REQUESTS_PENDING; | |
7272 | } | |
7273 | ||
7274 | return E1000_SUCCESS; | |
7275 | } | |
7276 | ||
7277 | /******************************************************************************* | |
7278 | * | |
7279 | * Check for EEPROM Auto Read bit done. | |
7280 | * | |
7281 | * hw: Struct containing variables accessed by shared code | |
7282 | * | |
7283 | * returns: - E1000_ERR_RESET if fail to reset MAC | |
7284 | * E1000_SUCCESS at any other case. | |
7285 | * | |
7286 | ******************************************************************************/ | |
3ad2cc67 | 7287 | static int32_t |
2d7edb92 MC |
7288 | e1000_get_auto_rd_done(struct e1000_hw *hw) |
7289 | { | |
7290 | int32_t timeout = AUTO_READ_DONE_TIMEOUT; | |
7291 | ||
7292 | DEBUGFUNC("e1000_get_auto_rd_done"); | |
7293 | ||
7294 | switch (hw->mac_type) { | |
7295 | default: | |
7296 | msec_delay(5); | |
7297 | break; | |
868d5309 MC |
7298 | case e1000_82571: |
7299 | case e1000_82572: | |
2d7edb92 | 7300 | case e1000_82573: |
6418ecc6 | 7301 | case e1000_80003es2lan: |
2d7edb92 MC |
7302 | while(timeout) { |
7303 | if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; | |
7304 | else msec_delay(1); | |
7305 | timeout--; | |
7306 | } | |
7307 | ||
7308 | if(!timeout) { | |
7309 | DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); | |
7310 | return -E1000_ERR_RESET; | |
7311 | } | |
7312 | break; | |
7313 | } | |
7314 | ||
fd803241 JK |
7315 | /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. |
7316 | * Need to wait for PHY configuration completion before accessing NVM | |
7317 | * and PHY. */ | |
7318 | if (hw->mac_type == e1000_82573) | |
7319 | msec_delay(25); | |
7320 | ||
2d7edb92 MC |
7321 | return E1000_SUCCESS; |
7322 | } | |
7323 | ||
7324 | /*************************************************************************** | |
7325 | * Checks if the PHY configuration is done | |
7326 | * | |
7327 | * hw: Struct containing variables accessed by shared code | |
7328 | * | |
7329 | * returns: - E1000_ERR_RESET if fail to reset MAC | |
7330 | * E1000_SUCCESS at any other case. | |
7331 | * | |
7332 | ***************************************************************************/ | |
3ad2cc67 | 7333 | static int32_t |
2d7edb92 MC |
7334 | e1000_get_phy_cfg_done(struct e1000_hw *hw) |
7335 | { | |
868d5309 MC |
7336 | int32_t timeout = PHY_CFG_TIMEOUT; |
7337 | uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; | |
7338 | ||
2d7edb92 MC |
7339 | DEBUGFUNC("e1000_get_phy_cfg_done"); |
7340 | ||
868d5309 MC |
7341 | switch (hw->mac_type) { |
7342 | default: | |
7343 | msec_delay(10); | |
7344 | break; | |
6418ecc6 JK |
7345 | case e1000_80003es2lan: |
7346 | /* Separate *_CFG_DONE_* bit for each port */ | |
7347 | if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) | |
7348 | cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; | |
7349 | /* Fall Through */ | |
868d5309 MC |
7350 | case e1000_82571: |
7351 | case e1000_82572: | |
7352 | while (timeout) { | |
7353 | if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) | |
7354 | break; | |
7355 | else | |
7356 | msec_delay(1); | |
7357 | timeout--; | |
7358 | } | |
7359 | ||
7360 | if (!timeout) { | |
7361 | DEBUGOUT("MNG configuration cycle has not completed.\n"); | |
7362 | return -E1000_ERR_RESET; | |
7363 | } | |
7364 | break; | |
7365 | } | |
2d7edb92 MC |
7366 | |
7367 | return E1000_SUCCESS; | |
7368 | } | |
7369 | ||
7370 | /*************************************************************************** | |
7371 | * | |
7372 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting | |
7373 | * adapter or Eeprom access. | |
7374 | * | |
7375 | * hw: Struct containing variables accessed by shared code | |
7376 | * | |
7377 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. | |
7378 | * E1000_SUCCESS at any other case. | |
7379 | * | |
7380 | ***************************************************************************/ | |
3ad2cc67 | 7381 | static int32_t |
2d7edb92 MC |
7382 | e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) |
7383 | { | |
7384 | int32_t timeout; | |
7385 | uint32_t swsm; | |
7386 | ||
7387 | DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); | |
7388 | ||
7389 | if(!hw->eeprom_semaphore_present) | |
7390 | return E1000_SUCCESS; | |
7391 | ||
6418ecc6 JK |
7392 | if (hw->mac_type == e1000_80003es2lan) { |
7393 | /* Get the SW semaphore. */ | |
7394 | if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) | |
7395 | return -E1000_ERR_EEPROM; | |
7396 | } | |
2d7edb92 MC |
7397 | |
7398 | /* Get the FW semaphore. */ | |
7399 | timeout = hw->eeprom.word_size + 1; | |
7400 | while(timeout) { | |
7401 | swsm = E1000_READ_REG(hw, SWSM); | |
7402 | swsm |= E1000_SWSM_SWESMBI; | |
7403 | E1000_WRITE_REG(hw, SWSM, swsm); | |
7404 | /* if we managed to set the bit we got the semaphore. */ | |
7405 | swsm = E1000_READ_REG(hw, SWSM); | |
7406 | if(swsm & E1000_SWSM_SWESMBI) | |
7407 | break; | |
7408 | ||
7409 | udelay(50); | |
7410 | timeout--; | |
7411 | } | |
7412 | ||
7413 | if(!timeout) { | |
7414 | /* Release semaphores */ | |
7415 | e1000_put_hw_eeprom_semaphore(hw); | |
7416 | DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); | |
7417 | return -E1000_ERR_EEPROM; | |
7418 | } | |
7419 | ||
7420 | return E1000_SUCCESS; | |
7421 | } | |
7422 | ||
7423 | /*************************************************************************** | |
7424 | * This function clears HW semaphore bits. | |
7425 | * | |
7426 | * hw: Struct containing variables accessed by shared code | |
7427 | * | |
7428 | * returns: - None. | |
7429 | * | |
7430 | ***************************************************************************/ | |
3ad2cc67 | 7431 | static void |
2d7edb92 MC |
7432 | e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) |
7433 | { | |
7434 | uint32_t swsm; | |
7435 | ||
7436 | DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); | |
7437 | ||
7438 | if(!hw->eeprom_semaphore_present) | |
7439 | return; | |
7440 | ||
7441 | swsm = E1000_READ_REG(hw, SWSM); | |
6418ecc6 JK |
7442 | if (hw->mac_type == e1000_80003es2lan) { |
7443 | /* Release both semaphores. */ | |
7444 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); | |
7445 | } else | |
868d5309 | 7446 | swsm &= ~(E1000_SWSM_SWESMBI); |
2d7edb92 MC |
7447 | E1000_WRITE_REG(hw, SWSM, swsm); |
7448 | } | |
7449 | ||
6418ecc6 JK |
7450 | /*************************************************************************** |
7451 | * | |
7452 | * Obtaining software semaphore bit (SMBI) before resetting PHY. | |
7453 | * | |
7454 | * hw: Struct containing variables accessed by shared code | |
7455 | * | |
7456 | * returns: - E1000_ERR_RESET if fail to obtain semaphore. | |
7457 | * E1000_SUCCESS at any other case. | |
7458 | * | |
7459 | ***************************************************************************/ | |
7460 | int32_t | |
7461 | e1000_get_software_semaphore(struct e1000_hw *hw) | |
7462 | { | |
7463 | int32_t timeout = hw->eeprom.word_size + 1; | |
7464 | uint32_t swsm; | |
7465 | ||
7466 | DEBUGFUNC("e1000_get_software_semaphore"); | |
7467 | ||
7468 | if (hw->mac_type != e1000_80003es2lan) | |
7469 | return E1000_SUCCESS; | |
7470 | ||
7471 | while(timeout) { | |
7472 | swsm = E1000_READ_REG(hw, SWSM); | |
7473 | /* If SMBI bit cleared, it is now set and we hold the semaphore */ | |
7474 | if(!(swsm & E1000_SWSM_SMBI)) | |
7475 | break; | |
7476 | msec_delay_irq(1); | |
7477 | timeout--; | |
7478 | } | |
7479 | ||
7480 | if(!timeout) { | |
7481 | DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); | |
7482 | return -E1000_ERR_RESET; | |
7483 | } | |
7484 | ||
7485 | return E1000_SUCCESS; | |
7486 | } | |
7487 | ||
7488 | /*************************************************************************** | |
7489 | * | |
7490 | * Release semaphore bit (SMBI). | |
7491 | * | |
7492 | * hw: Struct containing variables accessed by shared code | |
7493 | * | |
7494 | ***************************************************************************/ | |
7495 | void | |
7496 | e1000_release_software_semaphore(struct e1000_hw *hw) | |
7497 | { | |
7498 | uint32_t swsm; | |
7499 | ||
7500 | DEBUGFUNC("e1000_release_software_semaphore"); | |
7501 | ||
7502 | if (hw->mac_type != e1000_80003es2lan) | |
7503 | return; | |
7504 | ||
7505 | swsm = E1000_READ_REG(hw, SWSM); | |
7506 | /* Release the SW semaphores.*/ | |
7507 | swsm &= ~E1000_SWSM_SMBI; | |
7508 | E1000_WRITE_REG(hw, SWSM, swsm); | |
7509 | } | |
7510 | ||
2d7edb92 MC |
7511 | /****************************************************************************** |
7512 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. | |
7513 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to | |
7514 | * the caller to figure out how to deal with it. | |
7515 | * | |
7516 | * hw - Struct containing variables accessed by shared code | |
7517 | * | |
7518 | * returns: - E1000_BLK_PHY_RESET | |
7519 | * E1000_SUCCESS | |
7520 | * | |
7521 | *****************************************************************************/ | |
7522 | int32_t | |
7523 | e1000_check_phy_reset_block(struct e1000_hw *hw) | |
7524 | { | |
7525 | uint32_t manc = 0; | |
96838a40 JB |
7526 | |
7527 | if (hw->mac_type > e1000_82547_rev_2) | |
2d7edb92 MC |
7528 | manc = E1000_READ_REG(hw, MANC); |
7529 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
7530 | E1000_BLK_PHY_RESET : E1000_SUCCESS; | |
7531 | } | |
7532 | ||
3ad2cc67 | 7533 | static uint8_t |
2d7edb92 MC |
7534 | e1000_arc_subsystem_valid(struct e1000_hw *hw) |
7535 | { | |
7536 | uint32_t fwsm; | |
7537 | ||
7538 | /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC | |
7539 | * may not be provided a DMA clock when no manageability features are | |
7540 | * enabled. We do not want to perform any reads/writes to these registers | |
7541 | * if this is the case. We read FWSM to determine the manageability mode. | |
7542 | */ | |
7543 | switch (hw->mac_type) { | |
868d5309 MC |
7544 | case e1000_82571: |
7545 | case e1000_82572: | |
2d7edb92 | 7546 | case e1000_82573: |
6418ecc6 | 7547 | case e1000_80003es2lan: |
2d7edb92 MC |
7548 | fwsm = E1000_READ_REG(hw, FWSM); |
7549 | if((fwsm & E1000_FWSM_MODE_MASK) != 0) | |
7550 | return TRUE; | |
7551 | break; | |
7552 | default: | |
7553 | break; | |
7554 | } | |
7555 | return FALSE; | |
7556 | } | |
7557 | ||
7558 | ||
7559 |