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net: dsa: mv88e6xxx: Cache the port cmode
[linux-2.6-block.git] / drivers / net / dsa / rtl8366rb.c
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d8652956
LW		 1// SPDX-License-Identifier: GPL-2.0
2/* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
3 *
4 * This is a sparsely documented chip, the only viable documentation seems
5 * to be a patched up code drop from the vendor that appear in various
6 * GPL source trees.
7 *
8 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
10 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
11 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
12 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
13 */
14
15#include <linux/bitops.h>
16#include <linux/etherdevice.h>
17#include <linux/interrupt.h>
18#include <linux/irqdomain.h>
19#include <linux/irqchip/chained_irq.h>
20#include <linux/of_irq.h>
21#include <linux/regmap.h>
22
23#include "realtek-smi.h"
24
25#define RTL8366RB_PORT_NUM_CPU 5
26#define RTL8366RB_NUM_PORTS 6
27#define RTL8366RB_PHY_NO_MAX 4
28#define RTL8366RB_PHY_ADDR_MAX 31
29
30/* Switch Global Configuration register */
31#define RTL8366RB_SGCR 0x0000
32#define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
33#define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4)
34#define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
35#define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
36#define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
37#define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
38#define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
39#define RTL8366RB_SGCR_EN_VLAN BIT(13)
40#define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
41
42/* Port Enable Control register */
43#define RTL8366RB_PECR 0x0001
44
45/* Switch Security Control registers */
46#define RTL8366RB_SSCR0 0x0002
47#define RTL8366RB_SSCR1 0x0003
48#define RTL8366RB_SSCR2 0x0004
49#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
50
51/* Port Mirror Control Register */
52#define RTL8366RB_PMCR 0x0007
53#define RTL8366RB_PMCR_SOURCE_PORT(a) (a)
54#define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
55#define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4)
56#define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
57#define RTL8366RB_PMCR_MIRROR_RX BIT(8)
58#define RTL8366RB_PMCR_MIRROR_TX BIT(9)
59#define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
60#define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
61
62/* bits 0..7 = port 0, bits 8..15 = port 1 */
63#define RTL8366RB_PAACR0 0x0010
64/* bits 0..7 = port 2, bits 8..15 = port 3 */
65#define RTL8366RB_PAACR1 0x0011
66/* bits 0..7 = port 4, bits 8..15 = port 5 */
67#define RTL8366RB_PAACR2 0x0012
68#define RTL8366RB_PAACR_SPEED_10M 0
69#define RTL8366RB_PAACR_SPEED_100M 1
70#define RTL8366RB_PAACR_SPEED_1000M 2
71#define RTL8366RB_PAACR_FULL_DUPLEX BIT(2)
72#define RTL8366RB_PAACR_LINK_UP BIT(4)
73#define RTL8366RB_PAACR_TX_PAUSE BIT(5)
74#define RTL8366RB_PAACR_RX_PAUSE BIT(6)
75#define RTL8366RB_PAACR_AN BIT(7)
76
77#define RTL8366RB_PAACR_CPU_PORT (RTL8366RB_PAACR_SPEED_1000M | \
78 RTL8366RB_PAACR_FULL_DUPLEX | \
79 RTL8366RB_PAACR_LINK_UP | \
80 RTL8366RB_PAACR_TX_PAUSE | \
81 RTL8366RB_PAACR_RX_PAUSE)
82
83/* bits 0..7 = port 0, bits 8..15 = port 1 */
84#define RTL8366RB_PSTAT0 0x0014
85/* bits 0..7 = port 2, bits 8..15 = port 3 */
86#define RTL8366RB_PSTAT1 0x0015
87/* bits 0..7 = port 4, bits 8..15 = port 5 */
88#define RTL8366RB_PSTAT2 0x0016
89
90#define RTL8366RB_POWER_SAVING_REG 0x0021
91
92/* CPU port control reg */
93#define RTL8368RB_CPU_CTRL_REG 0x0061
94#define RTL8368RB_CPU_PORTS_MSK 0x00FF
95/* Enables inserting custom tag length/type 0x8899 */
96#define RTL8368RB_CPU_INSTAG BIT(15)
97
98#define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */
99#define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */
100#define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */
101
102#define RTL8366RB_RESET_CTRL_REG 0x0100
103#define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0)
104#define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1)
105
106#define RTL8366RB_CHIP_ID_REG 0x0509
107#define RTL8366RB_CHIP_ID_8366 0x5937
108#define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
109#define RTL8366RB_CHIP_VERSION_MASK 0xf
110
111/* PHY registers control */
112#define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
113#define RTL8366RB_PHY_CTRL_READ BIT(0)
114#define RTL8366RB_PHY_CTRL_WRITE 0
115#define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001
116#define RTL8366RB_PHY_INT_BUSY BIT(0)
117#define RTL8366RB_PHY_EXT_BUSY BIT(4)
118#define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
119#define RTL8366RB_PHY_EXT_CTRL_REG 0x8010
120#define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011
121#define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012
122
123#define RTL8366RB_PHY_REG_MASK 0x1f
124#define RTL8366RB_PHY_PAGE_OFFSET 5
125#define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
126#define RTL8366RB_PHY_NO_OFFSET 9
127#define RTL8366RB_PHY_NO_MASK (0x1f << 9)
128
129#define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
130
131/* LED control registers */
132#define RTL8366RB_LED_BLINKRATE_REG 0x0430
133#define RTL8366RB_LED_BLINKRATE_MASK 0x0007
134#define RTL8366RB_LED_BLINKRATE_28MS 0x0000
135#define RTL8366RB_LED_BLINKRATE_56MS 0x0001
136#define RTL8366RB_LED_BLINKRATE_84MS 0x0002
137#define RTL8366RB_LED_BLINKRATE_111MS 0x0003
138#define RTL8366RB_LED_BLINKRATE_222MS 0x0004
139#define RTL8366RB_LED_BLINKRATE_446MS 0x0005
140
141#define RTL8366RB_LED_CTRL_REG 0x0431
142#define RTL8366RB_LED_OFF 0x0
143#define RTL8366RB_LED_DUP_COL 0x1
144#define RTL8366RB_LED_LINK_ACT 0x2
145#define RTL8366RB_LED_SPD1000 0x3
146#define RTL8366RB_LED_SPD100 0x4
147#define RTL8366RB_LED_SPD10 0x5
148#define RTL8366RB_LED_SPD1000_ACT 0x6
149#define RTL8366RB_LED_SPD100_ACT 0x7
150#define RTL8366RB_LED_SPD10_ACT 0x8
151#define RTL8366RB_LED_SPD100_10_ACT 0x9
152#define RTL8366RB_LED_FIBER 0xa
153#define RTL8366RB_LED_AN_FAULT 0xb
154#define RTL8366RB_LED_LINK_RX 0xc
155#define RTL8366RB_LED_LINK_TX 0xd
156#define RTL8366RB_LED_MASTER 0xe
157#define RTL8366RB_LED_FORCE 0xf
158#define RTL8366RB_LED_0_1_CTRL_REG 0x0432
159#define RTL8366RB_LED_1_OFFSET 6
160#define RTL8366RB_LED_2_3_CTRL_REG 0x0433
161#define RTL8366RB_LED_3_OFFSET 6
162
163#define RTL8366RB_MIB_COUNT 33
164#define RTL8366RB_GLOBAL_MIB_COUNT 1
165#define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
166#define RTL8366RB_MIB_COUNTER_BASE 0x1000
167#define RTL8366RB_MIB_CTRL_REG 0x13F0
168#define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
169#define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
170#define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
171#define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
172#define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
173
174#define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
175#define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
176 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
177#define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
178#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
179
180#define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
181#define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
182
183#define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
184#define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
185#define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
186
187#define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
188
189#define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
190#define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
191#define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
192#define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
193#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
194#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
195#define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
196
197#define RTL8366RB_NUM_VLANS 16
198#define RTL8366RB_NUM_LEDGROUPS 4
199#define RTL8366RB_NUM_VIDS 4096
200#define RTL8366RB_PRIORITYMAX 7
201#define RTL8366RB_FIDMAX 7
202
203#define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */
204#define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */
205#define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */
206#define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */
207#define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */
208
209#define RTL8366RB_PORT_CPU BIT(5) /* CPU port */
210
211#define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
212 RTL8366RB_PORT_2 | \
213 RTL8366RB_PORT_3 | \
214 RTL8366RB_PORT_4 | \
215 RTL8366RB_PORT_5 | \
216 RTL8366RB_PORT_CPU)
217
218#define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
219 RTL8366RB_PORT_2 | \
220 RTL8366RB_PORT_3 | \
221 RTL8366RB_PORT_4 | \
222 RTL8366RB_PORT_5)
223
224#define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
225 RTL8366RB_PORT_2 | \
226 RTL8366RB_PORT_3 | \
227 RTL8366RB_PORT_4)
228
229#define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
230
231/* First configuration word per member config, VID and prio */
232#define RTL8366RB_VLAN_VID_MASK 0xfff
233#define RTL8366RB_VLAN_PRIORITY_SHIFT 12
234#define RTL8366RB_VLAN_PRIORITY_MASK 0x7
235/* Second configuration word per member config, member and untagged */
236#define RTL8366RB_VLAN_UNTAG_SHIFT 8
237#define RTL8366RB_VLAN_UNTAG_MASK 0xff
238#define RTL8366RB_VLAN_MEMBER_MASK 0xff
239/* Third config word per member config, STAG currently unused */
240#define RTL8366RB_VLAN_STAG_MBR_MASK 0xff
241#define RTL8366RB_VLAN_STAG_MBR_SHIFT 8
242#define RTL8366RB_VLAN_STAG_IDX_MASK 0x7
243#define RTL8366RB_VLAN_STAG_IDX_SHIFT 5
244#define RTL8366RB_VLAN_FID_MASK 0x7
245
246/* Port ingress bandwidth control */
247#define RTL8366RB_IB_BASE 0x0200
248#define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum))
249#define RTL8366RB_IB_BDTH_MASK 0x3fff
250#define RTL8366RB_IB_PREIFG BIT(14)
251
252/* Port egress bandwidth control */
253#define RTL8366RB_EB_BASE 0x02d1
254#define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum))
255#define RTL8366RB_EB_BDTH_MASK 0x3fff
256#define RTL8366RB_EB_PREIFG_REG 0x02f8
257#define RTL8366RB_EB_PREIFG BIT(9)
258
259#define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */
260#define RTL8366RB_BDTH_UNIT 64
261#define RTL8366RB_BDTH_REG_DEFAULT 16383
262
263/* QOS */
264#define RTL8366RB_QOS BIT(15)
265/* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
266#define RTL8366RB_QOS_DEFAULT_PREIFG 1
267
268/* Interrupt handling */
269#define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440
270#define RTL8366RB_INTERRUPT_POLARITY BIT(0)
271#define RTL8366RB_P4_RGMII_LED BIT(2)
272#define RTL8366RB_INTERRUPT_MASK_REG 0x0441
273#define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)
274#define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8)
275#define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)
276#define RTL8366RB_INTERRUPT_P4_FIBER BIT(12)
277#define RTL8366RB_INTERRUPT_P4_UTP BIT(13)
278#define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \
279 RTL8366RB_INTERRUPT_ACLEXCEED | \
280 RTL8366RB_INTERRUPT_STORMEXCEED | \
281 RTL8366RB_INTERRUPT_P4_FIBER | \
282 RTL8366RB_INTERRUPT_P4_UTP)
283#define RTL8366RB_INTERRUPT_STATUS_REG 0x0442
284#define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */
285
286/* bits 0..5 enable force when cleared */
287#define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11
288
289#define RTL8366RB_OAM_PARSER_REG 0x0F14
290#define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15
291
292#define RTL8366RB_GREEN_FEATURE_REG 0x0F51
293#define RTL8366RB_GREEN_FEATURE_MSK 0x0007
294#define RTL8366RB_GREEN_FEATURE_TX BIT(0)
295#define RTL8366RB_GREEN_FEATURE_RX BIT(2)
296
297static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
298 { 0, 0, 4, "IfInOctets" },
299 { 0, 4, 4, "EtherStatsOctets" },
300 { 0, 8, 2, "EtherStatsUnderSizePkts" },
301 { 0, 10, 2, "EtherFragments" },
302 { 0, 12, 2, "EtherStatsPkts64Octets" },
303 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
304 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
305 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
306 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
307 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
308 { 0, 24, 2, "EtherOversizeStats" },
309 { 0, 26, 2, "EtherStatsJabbers" },
310 { 0, 28, 2, "IfInUcastPkts" },
311 { 0, 30, 2, "EtherStatsMulticastPkts" },
312 { 0, 32, 2, "EtherStatsBroadcastPkts" },
313 { 0, 34, 2, "EtherStatsDropEvents" },
314 { 0, 36, 2, "Dot3StatsFCSErrors" },
315 { 0, 38, 2, "Dot3StatsSymbolErrors" },
316 { 0, 40, 2, "Dot3InPauseFrames" },
317 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
318 { 0, 44, 4, "IfOutOctets" },
319 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
320 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
321 { 0, 52, 2, "Dot3sDeferredTransmissions" },
322 { 0, 54, 2, "Dot3StatsLateCollisions" },
323 { 0, 56, 2, "EtherStatsCollisions" },
324 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
325 { 0, 60, 2, "Dot3OutPauseFrames" },
326 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
327 { 0, 64, 2, "Dot1dTpPortInDiscards" },
328 { 0, 66, 2, "IfOutUcastPkts" },
329 { 0, 68, 2, "IfOutMulticastPkts" },
330 { 0, 70, 2, "IfOutBroadcastPkts" },
331};
332
333static int rtl8366rb_get_mib_counter(struct realtek_smi *smi,
334 int port,
335 struct rtl8366_mib_counter *mib,
336 u64 *mibvalue)
337{
338 u32 addr, val;
339 int ret;
340 int i;
341
342 addr = RTL8366RB_MIB_COUNTER_BASE +
343 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
344 mib->offset;
345
346 /* Writing access counter address first
347 * then ASIC will prepare 64bits counter wait for being retrived
348 */
349 ret = regmap_write(smi->map, addr, 0); /* Write whatever */
350 if (ret)
351 return ret;
352
353 /* Read MIB control register */
354 ret = regmap_read(smi->map, RTL8366RB_MIB_CTRL_REG, &val);
355 if (ret)
356 return -EIO;
357
358 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
359 return -EBUSY;
360
361 if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
362 return -EIO;
363
364 /* Read each individual MIB 16 bits at the time */
365 *mibvalue = 0;
366 for (i = mib->length; i > 0; i--) {
367 ret = regmap_read(smi->map, addr + (i - 1), &val);
368 if (ret)
369 return ret;
370 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
371 }
372 return 0;
373}
374
375static u32 rtl8366rb_get_irqmask(struct irq_data *d)
376{
377 int line = irqd_to_hwirq(d);
378 u32 val;
379
380 /* For line interrupts we combine link down in bits
381 * 6..11 with link up in bits 0..5 into one interrupt.
382 */
383 if (line < 12)
384 val = BIT(line) | BIT(line + 6);
385 else
386 val = BIT(line);
387 return val;
388}
389
390static void rtl8366rb_mask_irq(struct irq_data *d)
391{
392 struct realtek_smi *smi = irq_data_get_irq_chip_data(d);
393 int ret;
394
395 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_MASK_REG,
396 rtl8366rb_get_irqmask(d), 0);
397 if (ret)
398 dev_err(smi->dev, "could not mask IRQ\n");
399}
400
401static void rtl8366rb_unmask_irq(struct irq_data *d)
402{
403 struct realtek_smi *smi = irq_data_get_irq_chip_data(d);
404 int ret;
405
406 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_MASK_REG,
407 rtl8366rb_get_irqmask(d),
408 rtl8366rb_get_irqmask(d));
409 if (ret)
410 dev_err(smi->dev, "could not unmask IRQ\n");
411}
412
413static irqreturn_t rtl8366rb_irq(int irq, void *data)
414{
415 struct realtek_smi *smi = data;
416 u32 stat;
417 int ret;
418
419 /* This clears the IRQ status register */
420 ret = regmap_read(smi->map, RTL8366RB_INTERRUPT_STATUS_REG,
421 &stat);
422 if (ret) {
423 dev_err(smi->dev, "can't read interrupt status\n");
424 return IRQ_NONE;
425 }
426 stat &= RTL8366RB_INTERRUPT_VALID;
427 if (!stat)
428 return IRQ_NONE;
429 while (stat) {
430 int line = __ffs(stat);
431 int child_irq;
432
433 stat &= ~BIT(line);
434 /* For line interrupts we combine link down in bits
435 * 6..11 with link up in bits 0..5 into one interrupt.
436 */
437 if (line < 12 && line > 5)
438 line -= 5;
439 child_irq = irq_find_mapping(smi->irqdomain, line);
440 handle_nested_irq(child_irq);
441 }
442 return IRQ_HANDLED;
443}
444
445static struct irq_chip rtl8366rb_irq_chip = {
446 .name = "RTL8366RB",
447 .irq_mask = rtl8366rb_mask_irq,
448 .irq_unmask = rtl8366rb_unmask_irq,
449};
450
451static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
452 irq_hw_number_t hwirq)
453{
454 irq_set_chip_data(irq, domain->host_data);
455 irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
456 irq_set_nested_thread(irq, 1);
457 irq_set_noprobe(irq);
458
459 return 0;
460}
461
462static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
463{
464 irq_set_nested_thread(irq, 0);
465 irq_set_chip_and_handler(irq, NULL, NULL);
466 irq_set_chip_data(irq, NULL);
467}
468
469static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
470 .map = rtl8366rb_irq_map,
471 .unmap = rtl8366rb_irq_unmap,
472 .xlate = irq_domain_xlate_onecell,
473};
474
475static int rtl8366rb_setup_cascaded_irq(struct realtek_smi *smi)
476{
477 struct device_node *intc;
478 unsigned long irq_trig;
479 int irq;
480 int ret;
481 u32 val;
482 int i;
483
484 intc = of_get_child_by_name(smi->dev->of_node, "interrupt-controller");
485 if (!intc) {
486 dev_err(smi->dev, "missing child interrupt-controller node\n");
487 return -EINVAL;
488 }
489 /* RB8366RB IRQs cascade off this one */
490 irq = of_irq_get(intc, 0);
491 if (irq <= 0) {
492 dev_err(smi->dev, "failed to get parent IRQ\n");
493 return irq ? irq : -EINVAL;
494 }
495
496 /* This clears the IRQ status register */
497 ret = regmap_read(smi->map, RTL8366RB_INTERRUPT_STATUS_REG,
498 &val);
499 if (ret) {
500 dev_err(smi->dev, "can't read interrupt status\n");
501 return ret;
502 }
503
504 /* Fetch IRQ edge information from the descriptor */
505 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
506 switch (irq_trig) {
507 case IRQF_TRIGGER_RISING:
508 case IRQF_TRIGGER_HIGH:
509 dev_info(smi->dev, "active high/rising IRQ\n");
510 val = 0;
511 break;
512 case IRQF_TRIGGER_FALLING:
513 case IRQF_TRIGGER_LOW:
514 dev_info(smi->dev, "active low/falling IRQ\n");
515 val = RTL8366RB_INTERRUPT_POLARITY;
516 break;
517 }
518 ret = regmap_update_bits(smi->map, RTL8366RB_INTERRUPT_CONTROL_REG,
519 RTL8366RB_INTERRUPT_POLARITY,
520 val);
521 if (ret) {
522 dev_err(smi->dev, "could not configure IRQ polarity\n");
523 return ret;
524 }
525
526 ret = devm_request_threaded_irq(smi->dev, irq, NULL,
527 rtl8366rb_irq, IRQF_ONESHOT,
528 "RTL8366RB", smi);
529 if (ret) {
530 dev_err(smi->dev, "unable to request irq: %d\n", ret);
531 return ret;
532 }
533 smi->irqdomain = irq_domain_add_linear(intc,
534 RTL8366RB_NUM_INTERRUPT,
535 &rtl8366rb_irqdomain_ops,
536 smi);
537 if (!smi->irqdomain) {
538 dev_err(smi->dev, "failed to create IRQ domain\n");
539 return -EINVAL;
540 }
541 for (i = 0; i < smi->num_ports; i++)
542 irq_set_parent(irq_create_mapping(smi->irqdomain, i), irq);
543
544 return 0;
545}
546
547static int rtl8366rb_set_addr(struct realtek_smi *smi)
548{
549 u8 addr[ETH_ALEN];
550 u16 val;
551 int ret;
552
553 eth_random_addr(addr);
554
555 dev_info(smi->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
556 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
557 val = addr[0] << 8 | addr[1];
558 ret = regmap_write(smi->map, RTL8366RB_SMAR0, val);
559 if (ret)
560 return ret;
561 val = addr[2] << 8 | addr[3];
562 ret = regmap_write(smi->map, RTL8366RB_SMAR1, val);
563 if (ret)
564 return ret;
565 val = addr[4] << 8 | addr[5];
566 ret = regmap_write(smi->map, RTL8366RB_SMAR2, val);
567 if (ret)
568 return ret;
569
570 return 0;
571}
572
573/* Found in a vendor driver */
574
575/* For the "version 0" early silicon, appear in most source releases */
576static const u16 rtl8366rb_init_jam_ver_0[] = {
577 0x000B, 0x0001, 0x03A6, 0x0100, 0x03A7, 0x0001, 0x02D1, 0x3FFF,
578 0x02D2, 0x3FFF, 0x02D3, 0x3FFF, 0x02D4, 0x3FFF, 0x02D5, 0x3FFF,
579 0x02D6, 0x3FFF, 0x02D7, 0x3FFF, 0x02D8, 0x3FFF, 0x022B, 0x0688,
580 0x022C, 0x0FAC, 0x03D0, 0x4688, 0x03D1, 0x01F5, 0x0000, 0x0830,
581 0x02F9, 0x0200, 0x02F7, 0x7FFF, 0x02F8, 0x03FF, 0x0080, 0x03E8,
582 0x0081, 0x00CE, 0x0082, 0x00DA, 0x0083, 0x0230, 0xBE0F, 0x2000,
583 0x0231, 0x422A, 0x0232, 0x422A, 0x0233, 0x422A, 0x0234, 0x422A,
584 0x0235, 0x422A, 0x0236, 0x422A, 0x0237, 0x422A, 0x0238, 0x422A,
585 0x0239, 0x422A, 0x023A, 0x422A, 0x023B, 0x422A, 0x023C, 0x422A,
586 0x023D, 0x422A, 0x023E, 0x422A, 0x023F, 0x422A, 0x0240, 0x422A,
587 0x0241, 0x422A, 0x0242, 0x422A, 0x0243, 0x422A, 0x0244, 0x422A,
588 0x0245, 0x422A, 0x0246, 0x422A, 0x0247, 0x422A, 0x0248, 0x422A,
589 0x0249, 0x0146, 0x024A, 0x0146, 0x024B, 0x0146, 0xBE03, 0xC961,
590 0x024D, 0x0146, 0x024E, 0x0146, 0x024F, 0x0146, 0x0250, 0x0146,
591 0xBE64, 0x0226, 0x0252, 0x0146, 0x0253, 0x0146, 0x024C, 0x0146,
592 0x0251, 0x0146, 0x0254, 0x0146, 0xBE62, 0x3FD0, 0x0084, 0x0320,
593 0x0255, 0x0146, 0x0256, 0x0146, 0x0257, 0x0146, 0x0258, 0x0146,
594 0x0259, 0x0146, 0x025A, 0x0146, 0x025B, 0x0146, 0x025C, 0x0146,
595 0x025D, 0x0146, 0x025E, 0x0146, 0x025F, 0x0146, 0x0260, 0x0146,
596 0x0261, 0xA23F, 0x0262, 0x0294, 0x0263, 0xA23F, 0x0264, 0x0294,
597 0x0265, 0xA23F, 0x0266, 0x0294, 0x0267, 0xA23F, 0x0268, 0x0294,
598 0x0269, 0xA23F, 0x026A, 0x0294, 0x026B, 0xA23F, 0x026C, 0x0294,
599 0x026D, 0xA23F, 0x026E, 0x0294, 0x026F, 0xA23F, 0x0270, 0x0294,
600 0x02F5, 0x0048, 0xBE09, 0x0E00, 0xBE1E, 0x0FA0, 0xBE14, 0x8448,
601 0xBE15, 0x1007, 0xBE4A, 0xA284, 0xC454, 0x3F0B, 0xC474, 0x3F0B,
602 0xBE48, 0x3672, 0xBE4B, 0x17A7, 0xBE4C, 0x0B15, 0xBE52, 0x0EDD,
603 0xBE49, 0x8C00, 0xBE5B, 0x785C, 0xBE5C, 0x785C, 0xBE5D, 0x785C,
604 0xBE61, 0x368A, 0xBE63, 0x9B84, 0xC456, 0xCC13, 0xC476, 0xCC13,
605 0xBE65, 0x307D, 0xBE6D, 0x0005, 0xBE6E, 0xE120, 0xBE2E, 0x7BAF,
606};
607
608/* This v1 init sequence is from Belkin F5D8235 U-Boot release */
609static const u16 rtl8366rb_init_jam_ver_1[] = {
610 0x0000, 0x0830, 0x0001, 0x8000, 0x0400, 0x8130, 0xBE78, 0x3C3C,
611 0x0431, 0x5432, 0xBE37, 0x0CE4, 0x02FA, 0xFFDF, 0x02FB, 0xFFE0,
612 0xC44C, 0x1585, 0xC44C, 0x1185, 0xC44C, 0x1585, 0xC46C, 0x1585,
613 0xC46C, 0x1185, 0xC46C, 0x1585, 0xC451, 0x2135, 0xC471, 0x2135,
614 0xBE10, 0x8140, 0xBE15, 0x0007, 0xBE6E, 0xE120, 0xBE69, 0xD20F,
615 0xBE6B, 0x0320, 0xBE24, 0xB000, 0xBE23, 0xFF51, 0xBE22, 0xDF20,
616 0xBE21, 0x0140, 0xBE20, 0x00BB, 0xBE24, 0xB800, 0xBE24, 0x0000,
617 0xBE24, 0x7000, 0xBE23, 0xFF51, 0xBE22, 0xDF60, 0xBE21, 0x0140,
618 0xBE20, 0x0077, 0xBE24, 0x7800, 0xBE24, 0x0000, 0xBE2E, 0x7B7A,
619 0xBE36, 0x0CE4, 0x02F5, 0x0048, 0xBE77, 0x2940, 0x000A, 0x83E0,
620 0xBE79, 0x3C3C, 0xBE00, 0x1340,
621};
622
623/* This v2 init sequence is from Belkin F5D8235 U-Boot release */
624static const u16 rtl8366rb_init_jam_ver_2[] = {
625 0x0450, 0x0000, 0x0400, 0x8130, 0x000A, 0x83ED, 0x0431, 0x5432,
626 0xC44F, 0x6250, 0xC46F, 0x6250, 0xC456, 0x0C14, 0xC476, 0x0C14,
627 0xC44C, 0x1C85, 0xC44C, 0x1885, 0xC44C, 0x1C85, 0xC46C, 0x1C85,
628 0xC46C, 0x1885, 0xC46C, 0x1C85, 0xC44C, 0x0885, 0xC44C, 0x0881,
629 0xC44C, 0x0885, 0xC46C, 0x0885, 0xC46C, 0x0881, 0xC46C, 0x0885,
630 0xBE2E, 0x7BA7, 0xBE36, 0x1000, 0xBE37, 0x1000, 0x8000, 0x0001,
631 0xBE69, 0xD50F, 0x8000, 0x0000, 0xBE69, 0xD50F, 0xBE6E, 0x0320,
632 0xBE77, 0x2940, 0xBE78, 0x3C3C, 0xBE79, 0x3C3C, 0xBE6E, 0xE120,
633 0x8000, 0x0001, 0xBE15, 0x1007, 0x8000, 0x0000, 0xBE15, 0x1007,
634 0xBE14, 0x0448, 0xBE1E, 0x00A0, 0xBE10, 0x8160, 0xBE10, 0x8140,
635 0xBE00, 0x1340, 0x0F51, 0x0010,
636};
637
638/* Appears in a DDWRT code dump */
639static const u16 rtl8366rb_init_jam_ver_3[] = {
640 0x0000, 0x0830, 0x0400, 0x8130, 0x000A, 0x83ED, 0x0431, 0x5432,
641 0x0F51, 0x0017, 0x02F5, 0x0048, 0x02FA, 0xFFDF, 0x02FB, 0xFFE0,
642 0xC456, 0x0C14, 0xC476, 0x0C14, 0xC454, 0x3F8B, 0xC474, 0x3F8B,
643 0xC450, 0x2071, 0xC470, 0x2071, 0xC451, 0x226B, 0xC471, 0x226B,
644 0xC452, 0xA293, 0xC472, 0xA293, 0xC44C, 0x1585, 0xC44C, 0x1185,
645 0xC44C, 0x1585, 0xC46C, 0x1585, 0xC46C, 0x1185, 0xC46C, 0x1585,
646 0xC44C, 0x0185, 0xC44C, 0x0181, 0xC44C, 0x0185, 0xC46C, 0x0185,
647 0xC46C, 0x0181, 0xC46C, 0x0185, 0xBE24, 0xB000, 0xBE23, 0xFF51,
648 0xBE22, 0xDF20, 0xBE21, 0x0140, 0xBE20, 0x00BB, 0xBE24, 0xB800,
649 0xBE24, 0x0000, 0xBE24, 0x7000, 0xBE23, 0xFF51, 0xBE22, 0xDF60,
650 0xBE21, 0x0140, 0xBE20, 0x0077, 0xBE24, 0x7800, 0xBE24, 0x0000,
651 0xBE2E, 0x7BA7, 0xBE36, 0x1000, 0xBE37, 0x1000, 0x8000, 0x0001,
652 0xBE69, 0xD50F, 0x8000, 0x0000, 0xBE69, 0xD50F, 0xBE6B, 0x0320,
653 0xBE77, 0x2800, 0xBE78, 0x3C3C, 0xBE79, 0x3C3C, 0xBE6E, 0xE120,
654 0x8000, 0x0001, 0xBE10, 0x8140, 0x8000, 0x0000, 0xBE10, 0x8140,
655 0xBE15, 0x1007, 0xBE14, 0x0448, 0xBE1E, 0x00A0, 0xBE10, 0x8160,
656 0xBE10, 0x8140, 0xBE00, 0x1340, 0x0450, 0x0000, 0x0401, 0x0000,
657};
658
659/* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
660static const u16 rtl8366rb_init_jam_f5d8235[] = {
661 0x0242, 0x02BF, 0x0245, 0x02BF, 0x0248, 0x02BF, 0x024B, 0x02BF,
662 0x024E, 0x02BF, 0x0251, 0x02BF, 0x0254, 0x0A3F, 0x0256, 0x0A3F,
663 0x0258, 0x0A3F, 0x025A, 0x0A3F, 0x025C, 0x0A3F, 0x025E, 0x0A3F,
664 0x0263, 0x007C, 0x0100, 0x0004, 0xBE5B, 0x3500, 0x800E, 0x200F,
665 0xBE1D, 0x0F00, 0x8001, 0x5011, 0x800A, 0xA2F4, 0x800B, 0x17A3,
666 0xBE4B, 0x17A3, 0xBE41, 0x5011, 0xBE17, 0x2100, 0x8000, 0x8304,
667 0xBE40, 0x8304, 0xBE4A, 0xA2F4, 0x800C, 0xA8D5, 0x8014, 0x5500,
668 0x8015, 0x0004, 0xBE4C, 0xA8D5, 0xBE59, 0x0008, 0xBE09, 0x0E00,
669 0xBE36, 0x1036, 0xBE37, 0x1036, 0x800D, 0x00FF, 0xBE4D, 0x00FF,
670};
671
672/* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
673static const u16 rtl8366rb_init_jam_dgn3500[] = {
674 0x0000, 0x0830, 0x0400, 0x8130, 0x000A, 0x83ED, 0x0F51, 0x0017,
675 0x02F5, 0x0048, 0x02FA, 0xFFDF, 0x02FB, 0xFFE0, 0x0450, 0x0000,
676 0x0401, 0x0000, 0x0431, 0x0960,
677};
678
679/* This jam table activates "green ethernet", which means low power mode
680 * and is claimed to detect the cable length and not use more power than
681 * necessary, and the ports should enter power saving mode 10 seconds after
682 * a cable is disconnected. Seems to always be the same.
683 */
684static const u16 rtl8366rb_green_jam[][2] = {
685 {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
686 {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
687 {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
688};
689
690static int rtl8366rb_setup(struct dsa_switch *ds)
691{
692 struct realtek_smi *smi = ds->priv;
693 const u16 *jam_table;
694 u32 chip_ver = 0;
695 u32 chip_id = 0;
696 int jam_size;
697 u32 val;
698 int ret;
699 int i;
700
701 ret = regmap_read(smi->map, RTL8366RB_CHIP_ID_REG, &chip_id);
702 if (ret) {
703 dev_err(smi->dev, "unable to read chip id\n");
704 return ret;
705 }
706
707 switch (chip_id) {
708 case RTL8366RB_CHIP_ID_8366:
709 break;
710 default:
711 dev_err(smi->dev, "unknown chip id (%04x)\n", chip_id);
712 return -ENODEV;
713 }
714
715 ret = regmap_read(smi->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
716 &chip_ver);
717 if (ret) {
718 dev_err(smi->dev, "unable to read chip version\n");
719 return ret;
720 }
721
722 dev_info(smi->dev, "RTL%04x ver %u chip found\n",
723 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
724
725 /* Do the init dance using the right jam table */
726 switch (chip_ver) {
727 case 0:
728 jam_table = rtl8366rb_init_jam_ver_0;
729 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
730 break;
731 case 1:
732 jam_table = rtl8366rb_init_jam_ver_1;
733 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
734 break;
735 case 2:
736 jam_table = rtl8366rb_init_jam_ver_2;
737 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
738 break;
739 default:
740 jam_table = rtl8366rb_init_jam_ver_3;
741 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
742 break;
743 }
744
745 /* Special jam tables for special routers
746 * TODO: are these necessary? Maintainers, please test
747 * without them, using just the off-the-shelf tables.
748 */
749 if (of_machine_is_compatible("belkin,f5d8235-v1")) {
750 jam_table = rtl8366rb_init_jam_f5d8235;
751 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
752 }
753 if (of_machine_is_compatible("netgear,dgn3500") ||
754 of_machine_is_compatible("netgear,dgn3500b")) {
755 jam_table = rtl8366rb_init_jam_dgn3500;
756 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
757 }
758
759 i = 0;
760 while (i < jam_size) {
761 if ((jam_table[i] & 0xBE00) == 0xBE00) {
762 ret = regmap_read(smi->map,
763 RTL8366RB_PHY_ACCESS_BUSY_REG,
764 &val);
765 if (ret)
766 return ret;
767 if (!(val & RTL8366RB_PHY_INT_BUSY)) {
768 ret = regmap_write(smi->map,
769 RTL8366RB_PHY_ACCESS_CTRL_REG,
770 RTL8366RB_PHY_CTRL_WRITE);
771 if (ret)
772 return ret;
773 }
774 }
775 dev_dbg(smi->dev, "jam %04x into register %04x\n",
776 jam_table[i + 1],
777 jam_table[i]);
778 ret = regmap_write(smi->map,
779 jam_table[i],
780 jam_table[i + 1]);
781 if (ret)
782 return ret;
783 i += 2;
784 }
785
786 /* Set up the "green ethernet" feature */
787 i = 0;
788 while (i < ARRAY_SIZE(rtl8366rb_green_jam)) {
789 ret = regmap_read(smi->map, RTL8366RB_PHY_ACCESS_BUSY_REG,
790 &val);
791 if (ret)
792 return ret;
793 if (!(val & RTL8366RB_PHY_INT_BUSY)) {
794 ret = regmap_write(smi->map,
795 RTL8366RB_PHY_ACCESS_CTRL_REG,
796 RTL8366RB_PHY_CTRL_WRITE);
797 if (ret)
798 return ret;
799 ret = regmap_write(smi->map,
800 rtl8366rb_green_jam[i][0],
801 rtl8366rb_green_jam[i][1]);
802 if (ret)
803 return ret;
804 i++;
805 }
806 }
807 ret = regmap_write(smi->map,
808 RTL8366RB_GREEN_FEATURE_REG,
809 (chip_ver == 1) ? 0x0007 : 0x0003);
810 if (ret)
811 return ret;
812
813 /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
814 ret = regmap_write(smi->map, 0x0c, 0x240);
815 if (ret)
816 return ret;
817 ret = regmap_write(smi->map, 0x0d, 0x240);
818 if (ret)
819 return ret;
820
821 /* Set some random MAC address */
822 ret = rtl8366rb_set_addr(smi);
823 if (ret)
824 return ret;
825
826 /* Enable CPU port and enable inserting CPU tag
827 *
828 * Disabling RTL8368RB_CPU_INSTAG here will change the behaviour
829 * of the switch totally and it will start talking Realtek RRCP
830 * internally. It is probably possible to experiment with this,
831 * but then the kernel needs to understand and handle RRCP first.
832 */
833 ret = regmap_update_bits(smi->map, RTL8368RB_CPU_CTRL_REG,
834 0xFFFF,
835 RTL8368RB_CPU_INSTAG | BIT(smi->cpu_port));
836 if (ret)
837 return ret;
838
839 /* Make sure we default-enable the fixed CPU port */
840 ret = regmap_update_bits(smi->map, RTL8366RB_PECR,
841 BIT(smi->cpu_port),
842 0);
843 if (ret)
844 return ret;
845
846 /* Set maximum packet length to 1536 bytes */
847 ret = regmap_update_bits(smi->map, RTL8366RB_SGCR,
848 RTL8366RB_SGCR_MAX_LENGTH_MASK,
849 RTL8366RB_SGCR_MAX_LENGTH_1536);
850 if (ret)
851 return ret;
852
853 /* Enable learning for all ports */
854 ret = regmap_write(smi->map, RTL8366RB_SSCR0, 0);
855 if (ret)
856 return ret;
857
858 /* Enable auto ageing for all ports */
859 ret = regmap_write(smi->map, RTL8366RB_SSCR1, 0);
860 if (ret)
861 return ret;
862
863 /* Discard VLAN tagged packets if the port is not a member of
864 * the VLAN with which the packets is associated.
865 */
866 ret = regmap_write(smi->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
867 RTL8366RB_PORT_ALL);
868 if (ret)
869 return ret;
870
871 /* Don't drop packets whose DA has not been learned */
872 ret = regmap_update_bits(smi->map, RTL8366RB_SSCR2,
873 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
874 if (ret)
875 return ret;
876
877 /* Set blinking, TODO: make this configurable */
878 ret = regmap_update_bits(smi->map, RTL8366RB_LED_BLINKRATE_REG,
879 RTL8366RB_LED_BLINKRATE_MASK,
880 RTL8366RB_LED_BLINKRATE_56MS);
881 if (ret)
882 return ret;
883
884 /* Set up LED activity:
885 * Each port has 4 LEDs, we configure all ports to the same
886 * behaviour (no individual config) but we can set up each
887 * LED separately.
888 */
889 if (smi->leds_disabled) {
890 /* Turn everything off */
891 regmap_update_bits(smi->map,
892 RTL8366RB_LED_0_1_CTRL_REG,
893 0x0FFF, 0);
894 regmap_update_bits(smi->map,
895 RTL8366RB_LED_2_3_CTRL_REG,
896 0x0FFF, 0);
897 regmap_update_bits(smi->map,
898 RTL8366RB_INTERRUPT_CONTROL_REG,
899 RTL8366RB_P4_RGMII_LED,
900 0);
901 val = RTL8366RB_LED_OFF;
902 } else {
903 /* TODO: make this configurable per LED */
904 val = RTL8366RB_LED_FORCE;
905 }
906 for (i = 0; i < 4; i++) {
907 ret = regmap_update_bits(smi->map,
908 RTL8366RB_LED_CTRL_REG,
909 0xf << (i * 4),
910 val << (i * 4));
911 if (ret)
912 return ret;
913 }
914
915 ret = rtl8366_init_vlan(smi);
916 if (ret)
917 return ret;
918
919 ret = rtl8366rb_setup_cascaded_irq(smi);
920 if (ret)
921 dev_info(smi->dev, "no interrupt support\n");
922
923 ret = realtek_smi_setup_mdio(smi);
924 if (ret) {
925 dev_info(smi->dev, "could not set up MDIO bus\n");
926 return -ENODEV;
927 }
928
929 return 0;
930}
931
932static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
933 int port)
934{
935 /* For now, the RTL switches are handled without any custom tags.
936 *
937 * It is possible to turn on "custom tags" by removing the
938 * RTL8368RB_CPU_INSTAG flag when enabling the port but what it
939 * does is unfamiliar to DSA: ethernet frames of type 8899, the Realtek
940 * Remote Control Protocol (RRCP) start to appear on the CPU port of
941 * the device. So this is not the ordinary few extra bytes in the
942 * frame. Instead it appears that the switch starts to talk Realtek
943 * RRCP internally which means a pretty complex RRCP implementation
944 * decoding and responding the RRCP protocol is needed to exploit this.
945 *
946 * The OpenRRCP project (dormant since 2009) have reverse-egineered
947 * parts of the protocol.
948 */
949 return DSA_TAG_PROTO_NONE;
950}
951
952static void rtl8366rb_adjust_link(struct dsa_switch *ds, int port,
953 struct phy_device *phydev)
954{
955 struct realtek_smi *smi = ds->priv;
956 int ret;
957
958 if (port != smi->cpu_port)
959 return;
960
961 dev_info(smi->dev, "adjust link on CPU port (%d)\n", port);
962
963 /* Force the fixed CPU port into 1Gbit mode, no autonegotiation */
964 ret = regmap_update_bits(smi->map, RTL8366RB_MAC_FORCE_CTRL_REG,
965 BIT(port), BIT(port));
966 if (ret)
967 return;
968
969 ret = regmap_update_bits(smi->map, RTL8366RB_PAACR2,
970 0xFF00U,
971 RTL8366RB_PAACR_CPU_PORT << 8);
972 if (ret)
973 return;
974
975 /* Enable the CPU port */
976 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port),
977 0);
978 if (ret)
979 return;
980}
981
982static void rb8366rb_set_port_led(struct realtek_smi *smi,
983 int port, bool enable)
984{
985 u16 val = enable ? 0x3f : 0;
986 int ret;
987
988 if (smi->leds_disabled)
989 return;
990
991 switch (port) {
992 case 0:
993 ret = regmap_update_bits(smi->map,
994 RTL8366RB_LED_0_1_CTRL_REG,
995 0x3F, val);
996 break;
997 case 1:
998 ret = regmap_update_bits(smi->map,
999 RTL8366RB_LED_0_1_CTRL_REG,
1000 0x3F << RTL8366RB_LED_1_OFFSET,
1001 val << RTL8366RB_LED_1_OFFSET);
1002 break;
1003 case 2:
1004 ret = regmap_update_bits(smi->map,
1005 RTL8366RB_LED_2_3_CTRL_REG,
1006 0x3F, val);
1007 break;
1008 case 3:
1009 ret = regmap_update_bits(smi->map,
1010 RTL8366RB_LED_2_3_CTRL_REG,
1011 0x3F << RTL8366RB_LED_3_OFFSET,
1012 val << RTL8366RB_LED_3_OFFSET);
1013 break;
1014 case 4:
1015 ret = regmap_update_bits(smi->map,
1016 RTL8366RB_INTERRUPT_CONTROL_REG,
1017 RTL8366RB_P4_RGMII_LED,
1018 enable ? RTL8366RB_P4_RGMII_LED : 0);
1019 break;
1020 default:
1021 dev_err(smi->dev, "no LED for port %d\n", port);
1022 return;
1023 }
1024 if (ret)
1025 dev_err(smi->dev, "error updating LED on port %d\n", port);
1026}
1027
1028static int
1029rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1030 struct phy_device *phy)
1031{
1032 struct realtek_smi *smi = ds->priv;
1033 int ret;
1034
1035 dev_dbg(smi->dev, "enable port %d\n", port);
1036 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port),
1037 0);
1038 if (ret)
1039 return ret;
1040
1041 rb8366rb_set_port_led(smi, port, true);
1042 return 0;
1043}
1044
1045static void
1046rtl8366rb_port_disable(struct dsa_switch *ds, int port,
1047 struct phy_device *phy)
1048{
1049 struct realtek_smi *smi = ds->priv;
1050 int ret;
1051
1052 dev_dbg(smi->dev, "disable port %d\n", port);
1053 ret = regmap_update_bits(smi->map, RTL8366RB_PECR, BIT(port),
1054 BIT(port));
1055 if (ret)
1056 return;
1057
1058 rb8366rb_set_port_led(smi, port, false);
1059}
1060
1061static int rtl8366rb_get_vlan_4k(struct realtek_smi *smi, u32 vid,
1062 struct rtl8366_vlan_4k *vlan4k)
1063{
1064 u32 data[3];
1065 int ret;
1066 int i;
1067
1068 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1069
1070 if (vid >= RTL8366RB_NUM_VIDS)
1071 return -EINVAL;
1072
1073 /* write VID */
1074 ret = regmap_write(smi->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1075 vid & RTL8366RB_VLAN_VID_MASK);
1076 if (ret)
1077 return ret;
1078
1079 /* write table access control word */
1080 ret = regmap_write(smi->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1081 RTL8366RB_TABLE_VLAN_READ_CTRL);
1082 if (ret)
1083 return ret;
1084
1085 for (i = 0; i < 3; i++) {
1086 ret = regmap_read(smi->map,
1087 RTL8366RB_VLAN_TABLE_READ_BASE + i,
1088 &data[i]);
1089 if (ret)
1090 return ret;
1091 }
1092
1093 vlan4k->vid = vid;
1094 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1095 RTL8366RB_VLAN_UNTAG_MASK;
1096 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1097 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1098
1099 return 0;
1100}
1101
1102static int rtl8366rb_set_vlan_4k(struct realtek_smi *smi,
1103 const struct rtl8366_vlan_4k *vlan4k)
1104{
1105 u32 data[3];
1106 int ret;
1107 int i;
1108
1109 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1110 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1111 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1112 vlan4k->fid > RTL8366RB_FIDMAX)
1113 return -EINVAL;
1114
1115 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1116 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1117 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1118 RTL8366RB_VLAN_UNTAG_SHIFT);
1119 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1120
1121 for (i = 0; i < 3; i++) {
1122 ret = regmap_write(smi->map,
1123 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1124 data[i]);
1125 if (ret)
1126 return ret;
1127 }
1128
1129 /* write table access control word */
1130 ret = regmap_write(smi->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1131 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1132
1133 return ret;
1134}
1135
1136static int rtl8366rb_get_vlan_mc(struct realtek_smi *smi, u32 index,
1137 struct rtl8366_vlan_mc *vlanmc)
1138{
1139 u32 data[3];
1140 int ret;
1141 int i;
1142
1143 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1144
1145 if (index >= RTL8366RB_NUM_VLANS)
1146 return -EINVAL;
1147
1148 for (i = 0; i < 3; i++) {
1149 ret = regmap_read(smi->map,
1150 RTL8366RB_VLAN_MC_BASE(index) + i,
1151 &data[i]);
1152 if (ret)
1153 return ret;
1154 }
1155
1156 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1157 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1158 RTL8366RB_VLAN_PRIORITY_MASK;
1159 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1160 RTL8366RB_VLAN_UNTAG_MASK;
1161 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1162 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1163
1164 return 0;
1165}
1166
1167static int rtl8366rb_set_vlan_mc(struct realtek_smi *smi, u32 index,
1168 const struct rtl8366_vlan_mc *vlanmc)
1169{
1170 u32 data[3];
1171 int ret;
1172 int i;
1173
1174 if (index >= RTL8366RB_NUM_VLANS ||
1175 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1176 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1177 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1178 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1179 vlanmc->fid > RTL8366RB_FIDMAX)
1180 return -EINVAL;
1181
1182 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1183 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1184 RTL8366RB_VLAN_PRIORITY_SHIFT);
1185 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1186 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1187 RTL8366RB_VLAN_UNTAG_SHIFT);
1188 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1189
1190 for (i = 0; i < 3; i++) {
1191 ret = regmap_write(smi->map,
1192 RTL8366RB_VLAN_MC_BASE(index) + i,
1193 data[i]);
1194 if (ret)
1195 return ret;
1196 }
1197
1198 return 0;
1199}
1200
1201static int rtl8366rb_get_mc_index(struct realtek_smi *smi, int port, int *val)
1202{
1203 u32 data;
1204 int ret;
1205
1206 if (port >= smi->num_ports)
1207 return -EINVAL;
1208
1209 ret = regmap_read(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1210 &data);
1211 if (ret)
1212 return ret;
1213
1214 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1215 RTL8366RB_PORT_VLAN_CTRL_MASK;
1216
1217 return 0;
1218}
1219
1220static int rtl8366rb_set_mc_index(struct realtek_smi *smi, int port, int index)
1221{
1222 if (port >= smi->num_ports || index >= RTL8366RB_NUM_VLANS)
1223 return -EINVAL;
1224
1225 return regmap_update_bits(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1226 RTL8366RB_PORT_VLAN_CTRL_MASK <<
1227 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1228 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1229 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1230}
1231
1232static bool rtl8366rb_is_vlan_valid(struct realtek_smi *smi, unsigned int vlan)
1233{
1234 unsigned int max = RTL8366RB_NUM_VLANS;
1235
1236 if (smi->vlan4k_enabled)
1237 max = RTL8366RB_NUM_VIDS - 1;
1238
1239 if (vlan == 0 || vlan >= max)
1240 return false;
1241
1242 return true;
1243}
1244
1245static int rtl8366rb_enable_vlan(struct realtek_smi *smi, bool enable)
1246{
1247 dev_dbg(smi->dev, "%s VLAN\n", enable ? "enable" : "disable");
1248 return regmap_update_bits(smi->map,
1249 RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1250 enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1251}
1252
1253static int rtl8366rb_enable_vlan4k(struct realtek_smi *smi, bool enable)
1254{
1255 dev_dbg(smi->dev, "%s VLAN 4k\n", enable ? "enable" : "disable");
1256 return regmap_update_bits(smi->map, RTL8366RB_SGCR,
1257 RTL8366RB_SGCR_EN_VLAN_4KTB,
1258 enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1259}
1260
1261static int rtl8366rb_phy_read(struct realtek_smi *smi, int phy, int regnum)
1262{
1263 u32 val;
1264 u32 reg;
1265 int ret;
1266
1267 if (phy > RTL8366RB_PHY_NO_MAX)
1268 return -EINVAL;
1269
1270 ret = regmap_write(smi->map, RTL8366RB_PHY_ACCESS_CTRL_REG,
1271 RTL8366RB_PHY_CTRL_READ);
1272 if (ret)
1273 return ret;
1274
1275 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1276
1277 ret = regmap_write(smi->map, reg, 0);
1278 if (ret) {
1279 dev_err(smi->dev,
1280 "failed to write PHY%d reg %04x @ %04x, ret %d\n",
1281 phy, regnum, reg, ret);
1282 return ret;
1283 }
1284
1285 ret = regmap_read(smi->map, RTL8366RB_PHY_ACCESS_DATA_REG, &val);
1286 if (ret)
1287 return ret;
1288
1289 dev_dbg(smi->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1290 phy, regnum, reg, val);
1291
1292 return val;
1293}
1294
1295static int rtl8366rb_phy_write(struct realtek_smi *smi, int phy, int regnum,
1296 u16 val)
1297{
1298 u32 reg;
1299 int ret;
1300
1301 if (phy > RTL8366RB_PHY_NO_MAX)
1302 return -EINVAL;
1303
1304 ret = regmap_write(smi->map, RTL8366RB_PHY_ACCESS_CTRL_REG,
1305 RTL8366RB_PHY_CTRL_WRITE);
1306 if (ret)
1307 return ret;
1308
1309 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1310
1311 dev_dbg(smi->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1312 phy, regnum, reg, val);
1313
1314 ret = regmap_write(smi->map, reg, val);
1315 if (ret)
1316 return ret;
1317
1318 return 0;
1319}
1320
1321static int rtl8366rb_reset_chip(struct realtek_smi *smi)
1322{
1323 int timeout = 10;
1324 u32 val;
1325 int ret;
1326
1327 realtek_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
1328 RTL8366RB_CHIP_CTRL_RESET_HW);
1329 do {
1330 usleep_range(20000, 25000);
1331 ret = regmap_read(smi->map, RTL8366RB_RESET_CTRL_REG, &val);
1332 if (ret)
1333 return ret;
1334
1335 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1336 break;
1337 } while (--timeout);
1338
1339 if (!timeout) {
1340 dev_err(smi->dev, "timeout waiting for the switch to reset\n");
1341 return -EIO;
1342 }
1343
1344 return 0;
1345}
1346
1347static int rtl8366rb_detect(struct realtek_smi *smi)
1348{
1349 struct device *dev = smi->dev;
1350 int ret;
1351 u32 val;
1352
1353 /* Detect device */
1354 ret = regmap_read(smi->map, 0x5c, &val);
1355 if (ret) {
1356 dev_err(dev, "can't get chip ID (%d)\n", ret);
1357 return ret;
1358 }
1359
1360 switch (val) {
1361 case 0x6027:
1362 dev_info(dev, "found an RTL8366S switch\n");
1363 dev_err(dev, "this switch is not yet supported, submit patches!\n");
1364 return -ENODEV;
1365 case 0x5937:
1366 dev_info(dev, "found an RTL8366RB switch\n");
1367 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1368 smi->num_ports = RTL8366RB_NUM_PORTS;
1369 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1370 smi->mib_counters = rtl8366rb_mib_counters;
1371 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1372 break;
1373 default:
1374 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1375 val);
1376 break;
1377 }
1378
1379 ret = rtl8366rb_reset_chip(smi);
1380 if (ret)
1381 return ret;
1382
1383 return 0;
1384}
1385
1386static const struct dsa_switch_ops rtl8366rb_switch_ops = {
1387 .get_tag_protocol = rtl8366_get_tag_protocol,
1388 .setup = rtl8366rb_setup,
1389 .adjust_link = rtl8366rb_adjust_link,
1390 .get_strings = rtl8366_get_strings,
1391 .get_ethtool_stats = rtl8366_get_ethtool_stats,
1392 .get_sset_count = rtl8366_get_sset_count,
1393 .port_vlan_filtering = rtl8366_vlan_filtering,
1394 .port_vlan_prepare = rtl8366_vlan_prepare,
1395 .port_vlan_add = rtl8366_vlan_add,
1396 .port_vlan_del = rtl8366_vlan_del,
1397 .port_enable = rtl8366rb_port_enable,
1398 .port_disable = rtl8366rb_port_disable,
1399};
1400
1401static const struct realtek_smi_ops rtl8366rb_smi_ops = {
1402 .detect = rtl8366rb_detect,
1403 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1404 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1405 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1406 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1407 .get_mc_index = rtl8366rb_get_mc_index,
1408 .set_mc_index = rtl8366rb_set_mc_index,
1409 .get_mib_counter = rtl8366rb_get_mib_counter,
1410 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1411 .enable_vlan = rtl8366rb_enable_vlan,
1412 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1413 .phy_read = rtl8366rb_phy_read,
1414 .phy_write = rtl8366rb_phy_write,
1415};
1416
1417const struct realtek_smi_variant rtl8366rb_variant = {
1418 .ds_ops = &rtl8366rb_switch_ops,
1419 .ops = &rtl8366rb_smi_ops,
1420 .clk_delay = 10,
1421 .cmd_read = 0xa9,
1422 .cmd_write = 0xa8,
1423};
1424EXPORT_SYMBOL_GPL(rtl8366rb_variant);
Linux 6.x block layer and io_uring tree(s)