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net: dsa: qca8k: extend slave-bus implementations
[linux-2.6-block.git] / drivers / net / dsa / qca8k.c
CommitLineData
63a786a3 1// SPDX-License-Identifier: GPL-2.0
6b93fb46
JC		 2/*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
6b93fb46
JC		 7 */
8
9#include <linux/module.h>
10#include <linux/phy.h>
11#include <linux/netdevice.h>
12#include <net/dsa.h>
6b93fb46
JC		 13#include <linux/of_net.h>
14#include <linux/of_platform.h>
15#include <linux/if_bridge.h>
16#include <linux/mdio.h>
17#include <linux/etherdevice.h>
18
19#include "qca8k.h"
20
21#define MIB_DESC(_s, _o, _n) \
22 { \
23 .size = (_s), \
24 .offset = (_o), \
25 .name = (_n), \
26 }
27
28static const struct qca8k_mib_desc ar8327_mib[] = {
29 MIB_DESC(1, 0x00, "RxBroad"),
30 MIB_DESC(1, 0x04, "RxPause"),
31 MIB_DESC(1, 0x08, "RxMulti"),
32 MIB_DESC(1, 0x0c, "RxFcsErr"),
33 MIB_DESC(1, 0x10, "RxAlignErr"),
34 MIB_DESC(1, 0x14, "RxRunt"),
35 MIB_DESC(1, 0x18, "RxFragment"),
36 MIB_DESC(1, 0x1c, "Rx64Byte"),
37 MIB_DESC(1, 0x20, "Rx128Byte"),
38 MIB_DESC(1, 0x24, "Rx256Byte"),
39 MIB_DESC(1, 0x28, "Rx512Byte"),
40 MIB_DESC(1, 0x2c, "Rx1024Byte"),
41 MIB_DESC(1, 0x30, "Rx1518Byte"),
42 MIB_DESC(1, 0x34, "RxMaxByte"),
43 MIB_DESC(1, 0x38, "RxTooLong"),
44 MIB_DESC(2, 0x3c, "RxGoodByte"),
45 MIB_DESC(2, 0x44, "RxBadByte"),
46 MIB_DESC(1, 0x4c, "RxOverFlow"),
47 MIB_DESC(1, 0x50, "Filtered"),
48 MIB_DESC(1, 0x54, "TxBroad"),
49 MIB_DESC(1, 0x58, "TxPause"),
50 MIB_DESC(1, 0x5c, "TxMulti"),
51 MIB_DESC(1, 0x60, "TxUnderRun"),
52 MIB_DESC(1, 0x64, "Tx64Byte"),
53 MIB_DESC(1, 0x68, "Tx128Byte"),
54 MIB_DESC(1, 0x6c, "Tx256Byte"),
55 MIB_DESC(1, 0x70, "Tx512Byte"),
56 MIB_DESC(1, 0x74, "Tx1024Byte"),
57 MIB_DESC(1, 0x78, "Tx1518Byte"),
58 MIB_DESC(1, 0x7c, "TxMaxByte"),
59 MIB_DESC(1, 0x80, "TxOverSize"),
60 MIB_DESC(2, 0x84, "TxByte"),
61 MIB_DESC(1, 0x8c, "TxCollision"),
62 MIB_DESC(1, 0x90, "TxAbortCol"),
63 MIB_DESC(1, 0x94, "TxMultiCol"),
64 MIB_DESC(1, 0x98, "TxSingleCol"),
65 MIB_DESC(1, 0x9c, "TxExcDefer"),
66 MIB_DESC(1, 0xa0, "TxDefer"),
67 MIB_DESC(1, 0xa4, "TxLateCol"),
68};
69
70/* The 32bit switch registers are accessed indirectly. To achieve this we need
71 * to set the page of the register. Track the last page that was set to reduce
72 * mdio writes
73 */
74static u16 qca8k_current_page = 0xffff;
75
76static void
77qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
78{
79 regaddr >>= 1;
80 *r1 = regaddr & 0x1e;
81
82 regaddr >>= 5;
83 *r2 = regaddr & 0x7;
84
85 regaddr >>= 3;
86 *page = regaddr & 0x3ff;
87}
88
89static u32
90qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
91{
92 u32 val;
93 int ret;
94
95 ret = bus->read(bus, phy_id, regnum);
96 if (ret >= 0) {
97 val = ret;
98 ret = bus->read(bus, phy_id, regnum + 1);
99 val |= ret << 16;
100 }
101
102 if (ret < 0) {
103 dev_err_ratelimited(&bus->dev,
104 "failed to read qca8k 32bit register\n");
105 return ret;
106 }
107
108 return val;
109}
110
111static void
112qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
113{
114 u16 lo, hi;
115 int ret;
116
117 lo = val & 0xffff;
118 hi = (u16)(val >> 16);
119
120 ret = bus->write(bus, phy_id, regnum, lo);
121 if (ret >= 0)
122 ret = bus->write(bus, phy_id, regnum + 1, hi);
123 if (ret < 0)
124 dev_err_ratelimited(&bus->dev,
125 "failed to write qca8k 32bit register\n");
126}
127
128static void
129qca8k_set_page(struct mii_bus *bus, u16 page)
130{
131 if (page == qca8k_current_page)
132 return;
133
134 if (bus->write(bus, 0x18, 0, page) < 0)
135 dev_err_ratelimited(&bus->dev,
136 "failed to set qca8k page\n");
137 qca8k_current_page = page;
138}
139
140static u32
141qca8k_read(struct qca8k_priv *priv, u32 reg)
142{
143 u16 r1, r2, page;
144 u32 val;
145
146 qca8k_split_addr(reg, &r1, &r2, &page);
147
148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
149
150 qca8k_set_page(priv->bus, page);
151 val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
152
153 mutex_unlock(&priv->bus->mdio_lock);
154
155 return val;
156}
157
158static void
159qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
160{
161 u16 r1, r2, page;
162
163 qca8k_split_addr(reg, &r1, &r2, &page);
164
165 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
166
167 qca8k_set_page(priv->bus, page);
168 qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
169
170 mutex_unlock(&priv->bus->mdio_lock);
171}
172
173static u32
174qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
175{
176 u16 r1, r2, page;
177 u32 ret;
178
179 qca8k_split_addr(reg, &r1, &r2, &page);
180
181 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
182
183 qca8k_set_page(priv->bus, page);
184 ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
185 ret &= ~mask;
186 ret |= val;
187 qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);
188
189 mutex_unlock(&priv->bus->mdio_lock);
190
191 return ret;
192}
193
194static void
195qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
196{
197 qca8k_rmw(priv, reg, 0, val);
198}
199
200static void
201qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
202{
203 qca8k_rmw(priv, reg, val, 0);
204}
205
206static int
207qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
208{
209 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
210
211 *val = qca8k_read(priv, reg);
212
213 return 0;
214}
215
216static int
217qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
218{
219 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
220
221 qca8k_write(priv, reg, val);
222
223 return 0;
224}
225
226static const struct regmap_range qca8k_readable_ranges[] = {
227 regmap_reg_range(0x0000, 0x00e4), /* Global control */
228 regmap_reg_range(0x0100, 0x0168), /* EEE control */
229 regmap_reg_range(0x0200, 0x0270), /* Parser control */
230 regmap_reg_range(0x0400, 0x0454), /* ACL */
231 regmap_reg_range(0x0600, 0x0718), /* Lookup */
232 regmap_reg_range(0x0800, 0x0b70), /* QM */
233 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
234 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
235 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
236 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
237 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
238 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
239 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
240 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
241 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
242
243};
244
7e3108fa 245static const struct regmap_access_table qca8k_readable_table = {
6b93fb46
JC		 246 .yes_ranges = qca8k_readable_ranges,
247 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
248};
249
fcfbfd68 250static struct regmap_config qca8k_regmap_config = {
6b93fb46
JC		 251 .reg_bits = 16,
252 .val_bits = 32,
253 .reg_stride = 4,
254 .max_register = 0x16ac, /* end MIB - Port6 range */
255 .reg_read = qca8k_regmap_read,
256 .reg_write = qca8k_regmap_write,
257 .rd_table = &qca8k_readable_table,
258};
259
260static int
261qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
262{
263 unsigned long timeout;
264
265 timeout = jiffies + msecs_to_jiffies(20);
266
267 /* loop until the busy flag has cleared */
268 do {
269 u32 val = qca8k_read(priv, reg);
270 int busy = val & mask;
271
272 if (!busy)
273 break;
274 cond_resched();
275 } while (!time_after_eq(jiffies, timeout));
276
277 return time_after_eq(jiffies, timeout);
278}
279
280static void
281qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
282{
283 u32 reg[4];
284 int i;
285
286 /* load the ARL table into an array */
287 for (i = 0; i < 4; i++)
288 reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
289
290 /* vid - 83:72 */
291 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
292 /* aging - 67:64 */
293 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
294 /* portmask - 54:48 */
295 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
296 /* mac - 47:0 */
297 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
298 fdb->mac[1] = reg[1] & 0xff;
299 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
300 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
301 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
302 fdb->mac[5] = reg[0] & 0xff;
303}
304
305static void
306qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
307 u8 aging)
308{
309 u32 reg[3] = { 0 };
310 int i;
311
312 /* vid - 83:72 */
313 reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
314 /* aging - 67:64 */
315 reg[2] |= aging & QCA8K_ATU_STATUS_M;
316 /* portmask - 54:48 */
317 reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
318 /* mac - 47:0 */
319 reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
320 reg[1] |= mac[1];
321 reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
322 reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
323 reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
324 reg[0] |= mac[5];
325
326 /* load the array into the ARL table */
327 for (i = 0; i < 3; i++)
328 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
329}
330
331static int
332qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
333{
334 u32 reg;
335
336 /* Set the command and FDB index */
337 reg = QCA8K_ATU_FUNC_BUSY;
338 reg |= cmd;
339 if (port >= 0) {
340 reg |= QCA8K_ATU_FUNC_PORT_EN;
341 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
342 }
343
344 /* Write the function register triggering the table access */
345 qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
346
347 /* wait for completion */
348 if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
349 return -1;
350
351 /* Check for table full violation when adding an entry */
352 if (cmd == QCA8K_FDB_LOAD) {
353 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
354 if (reg & QCA8K_ATU_FUNC_FULL)
355 return -1;
356 }
357
358 return 0;
359}
360
361static int
362qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
363{
364 int ret;
365
366 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
367 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
368 if (ret >= 0)
369 qca8k_fdb_read(priv, fdb);
370
371 return ret;
372}
373
374static int
375qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
376 u16 vid, u8 aging)
377{
378 int ret;
379
380 mutex_lock(&priv->reg_mutex);
381 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
382 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
383 mutex_unlock(&priv->reg_mutex);
384
385 return ret;
386}
387
388static int
389qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
390{
391 int ret;
392
393 mutex_lock(&priv->reg_mutex);
394 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
395 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
396 mutex_unlock(&priv->reg_mutex);
397
398 return ret;
399}
400
401static void
402qca8k_fdb_flush(struct qca8k_priv *priv)
403{
404 mutex_lock(&priv->reg_mutex);
405 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
406 mutex_unlock(&priv->reg_mutex);
407}
408
409static void
410qca8k_mib_init(struct qca8k_priv *priv)
411{
412 mutex_lock(&priv->reg_mutex);
413 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
414 qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
415 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
416 qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
417 mutex_unlock(&priv->reg_mutex);
418}
419
420static int
421qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
422{
5ecdd77c 423 u32 reg, val;
6b93fb46
JC		 424
425 switch (port) {
426 case 0:
427 reg = QCA8K_REG_PORT0_PAD_CTRL;
428 break;
429 case 6:
430 reg = QCA8K_REG_PORT6_PAD_CTRL;
431 break;
432 default:
433 pr_err("Can't set PAD_CTRL on port %d\n", port);
434 return -EINVAL;
435 }
436
437 /* Configure a port to be directly connected to an external
438 * PHY or MAC.
439 */
440 switch (mode) {
441 case PHY_INTERFACE_MODE_RGMII:
5ecdd77c
VK		 442 /* RGMII mode means no delay so don't enable the delay */
443 val = QCA8K_PORT_PAD_RGMII_EN;
444 qca8k_write(priv, reg, val);
6b93fb46 445 break;
a968b5e9
VK		 446 case PHY_INTERFACE_MODE_RGMII_ID:
447 /* RGMII_ID needs internal delay. This is enabled through
448 * PORT5_PAD_CTRL for all ports, rather than individual port
449 * registers
450 */
451 qca8k_write(priv, reg,
452 QCA8K_PORT_PAD_RGMII_EN |
453 QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
454 QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
455 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
456 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
457 break;
6b93fb46
JC		 458 case PHY_INTERFACE_MODE_SGMII:
459 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
460 break;
461 default:
462 pr_err("xMII mode %d not supported\n", mode);
463 return -EINVAL;
464 }
465
466 return 0;
467}
468
469static void
470qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
471{
eee1fe64 472 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
6b93fb46
JC		 473
474 /* Port 0 and 6 have no internal PHY */
38222b1a 475 if (port > 0 && port < 6)
6b93fb46
JC		 476 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
477
478 if (enable)
479 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
480 else
481 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
482}
483
db460c54
CL		 484static u32
485qca8k_port_to_phy(int port)
486{
487 /* From Andrew Lunn:
488 * Port 0 has no internal phy.
489 * Port 1 has an internal PHY at MDIO address 0.
490 * Port 2 has an internal PHY at MDIO address 1.
491 * ...
492 * Port 5 has an internal PHY at MDIO address 4.
493 * Port 6 has no internal PHY.
494 */
495
496 return port - 1;
497}
498
499static int
500qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
501{
502 u32 phy, val;
503
504 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
505 return -EINVAL;
506
507 /* callee is responsible for not passing bad ports,
508 * but we still would like to make spills impossible.
509 */
510 phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
511 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
512 QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
513 QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
514 QCA8K_MDIO_MASTER_DATA(data);
515
516 qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
517
518 return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
519 QCA8K_MDIO_MASTER_BUSY);
520}
521
522static int
523qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
524{
525 u32 phy, val;
526
527 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
528 return -EINVAL;
529
530 /* callee is responsible for not passing bad ports,
531 * but we still would like to make spills impossible.
532 */
533 phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
534 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
535 QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
536 QCA8K_MDIO_MASTER_REG_ADDR(regnum);
537
538 qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);
539
540 if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
541 QCA8K_MDIO_MASTER_BUSY))
542 return -ETIMEDOUT;
543
544 val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) &
545 QCA8K_MDIO_MASTER_DATA_MASK);
546
547 return val;
548}
549
550static int
551qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
552{
553 struct qca8k_priv *priv = ds->priv;
554
555 return qca8k_mdio_write(priv, port, regnum, data);
556}
557
558static int
559qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
560{
561 struct qca8k_priv *priv = ds->priv;
562 int ret;
563
564 ret = qca8k_mdio_read(priv, port, regnum);
565
566 if (ret < 0)
567 return 0xffff;
568
569 return ret;
570}
571
572static int
573qca8k_setup_mdio_bus(struct qca8k_priv *priv)
574{
575 u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
576 struct device_node *ports, *port;
577 int err;
578
579 ports = of_get_child_by_name(priv->dev->of_node, "ports");
580 if (!ports)
581 return -EINVAL;
582
583 for_each_available_child_of_node(ports, port) {
584 err = of_property_read_u32(port, "reg", &reg);
585 if (err)
586 return err;
587
588 if (!dsa_is_user_port(priv->ds, reg))
589 continue;
590
591 if (of_property_read_bool(port, "phy-handle"))
592 external_mdio_mask |= BIT(reg);
593 else
594 internal_mdio_mask |= BIT(reg);
595 }
596
597 if (!external_mdio_mask && !internal_mdio_mask) {
598 dev_err(priv->dev, "no PHYs are defined.\n");
599 return -EINVAL;
600 }
601
602 /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
603 * the MDIO_MASTER register also _disconnects_ the external MDC
604 * passthrough to the internal PHYs. It's not possible to use both
605 * configurations at the same time!
606 *
607 * Because this came up during the review process:
608 * If the external mdio-bus driver is capable magically disabling
609 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
610 * accessors for the time being, it would be possible to pull this
611 * off.
612 */
613 if (!!external_mdio_mask && !!internal_mdio_mask) {
614 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
615 return -EINVAL;
616 }
617
618 if (external_mdio_mask) {
619 /* Make sure to disable the internal mdio bus in cases
620 * a dt-overlay and driver reload changed the configuration
621 */
622
623 qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
624 QCA8K_MDIO_MASTER_EN);
625 return 0;
626 }
627
628 priv->ops.phy_read = qca8k_phy_read;
629 priv->ops.phy_write = qca8k_phy_write;
630 return 0;
631}
632
6b93fb46
JC		 633static int
634qca8k_setup(struct dsa_switch *ds)
635{
636 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
637 int ret, i, phy_mode = -1;
79a4ed4f 638 u32 mask;
6b93fb46
JC		 639
640 /* Make sure that port 0 is the cpu port */
641 if (!dsa_is_cpu_port(ds, 0)) {
642 pr_err("port 0 is not the CPU port\n");
643 return -EINVAL;
644 }
645
646 mutex_init(&priv->reg_mutex);
647
648 /* Start by setting up the register mapping */
649 priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
650 &qca8k_regmap_config);
651 if (IS_ERR(priv->regmap))
652 pr_warn("regmap initialization failed");
653
db460c54
CL		 654 ret = qca8k_setup_mdio_bus(priv);
655 if (ret)
656 return ret;
657
6b93fb46 658 /* Initialize CPU port pad mode (xMII type, delays...) */
0abfd494 659 phy_mode = of_get_phy_mode(ds->ports[QCA8K_CPU_PORT].dn);
6b93fb46
JC		 660 if (phy_mode < 0) {
661 pr_err("Can't find phy-mode for master device\n");
662 return phy_mode;
663 }
664 ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
665 if (ret < 0)
666 return ret;
667
79a4ed4f
MV		 668 /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
669 mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
670 QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
671 qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
6b93fb46
JC		 672 qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
673 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
674 qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
675 priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
676
677 /* Enable MIB counters */
678 qca8k_mib_init(priv);
679
680 /* Enable QCA header mode on the cpu port */
681 qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
682 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
683 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
684
685 /* Disable forwarding by default on all ports */
686 for (i = 0; i < QCA8K_NUM_PORTS; i++)
687 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
688 QCA8K_PORT_LOOKUP_MEMBER, 0);
689
690 /* Disable MAC by default on all user ports */
691 for (i = 1; i < QCA8K_NUM_PORTS; i++)
4a5b85ff 692 if (dsa_is_user_port(ds, i))
6b93fb46
JC		 693 qca8k_port_set_status(priv, i, 0);
694
695 /* Forward all unknown frames to CPU port for Linux processing */
696 qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
697 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
698 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
699 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
700 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
701
702 /* Setup connection between CPU port & user ports */
703 for (i = 0; i < DSA_MAX_PORTS; i++) {
704 /* CPU port gets connected to all user ports of the switch */
705 if (dsa_is_cpu_port(ds, i)) {
706 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
02bc6e54 707 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
6b93fb46
JC		 708 }
709
710 /* Invividual user ports get connected to CPU port only */
4a5b85ff 711 if (dsa_is_user_port(ds, i)) {
6b93fb46
JC		 712 int shift = 16 * (i % 2);
713
714 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
715 QCA8K_PORT_LOOKUP_MEMBER,
716 BIT(QCA8K_CPU_PORT));
717
718 /* Enable ARP Auto-learning by default */
719 qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
720 QCA8K_PORT_LOOKUP_LEARN);
721
722 /* For port based vlans to work we need to set the
723 * default egress vid
724 */
725 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
726 0xffff << shift, 1 << shift);
727 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
728 QCA8K_PORT_VLAN_CVID(1) |
729 QCA8K_PORT_VLAN_SVID(1));
730 }
731 }
732
733 /* Flush the FDB table */
734 qca8k_fdb_flush(priv);
735
736 return 0;
737}
738
9bb2289f
MV		 739static void
740qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
741{
742 struct qca8k_priv *priv = ds->priv;
743 u32 reg;
744
745 /* Force fixed-link setting for CPU port, skip others. */
746 if (!phy_is_pseudo_fixed_link(phy))
747 return;
748
749 /* Set port speed */
750 switch (phy->speed) {
751 case 10:
752 reg = QCA8K_PORT_STATUS_SPEED_10;
753 break;
754 case 100:
755 reg = QCA8K_PORT_STATUS_SPEED_100;
756 break;
757 case 1000:
758 reg = QCA8K_PORT_STATUS_SPEED_1000;
759 break;
760 default:
761 dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
762 port, phy->speed);
763 return;
764 }
765
766 /* Set duplex mode */
767 if (phy->duplex == DUPLEX_FULL)
768 reg |= QCA8K_PORT_STATUS_DUPLEX;
769
770 /* Force flow control */
771 if (dsa_is_cpu_port(ds, port))
772 reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
773
774 /* Force link down before changing MAC options */
775 qca8k_port_set_status(priv, port, 0);
776 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
777 qca8k_port_set_status(priv, port, 1);
778}
779
6b93fb46 780static void
89f09048 781qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
6b93fb46
JC		 782{
783 int i;
784
89f09048
FF		 785 if (stringset != ETH_SS_STATS)
786 return;
787
6b93fb46
JC		 788 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
789 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
790 ETH_GSTRING_LEN);
791}
792
793static void
794qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
795 uint64_t *data)
796{
797 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
798 const struct qca8k_mib_desc *mib;
799 u32 reg, i;
800 u64 hi;
801
802 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
803 mib = &ar8327_mib[i];
804 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
805
806 data[i] = qca8k_read(priv, reg);
807 if (mib->size == 2) {
808 hi = qca8k_read(priv, reg + 4);
809 data[i] |= hi << 32;
810 }
811 }
812}
813
814static int
89f09048 815qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
6b93fb46 816{
89f09048
FF		 817 if (sset != ETH_SS_STATS)
818 return 0;
819
6b93fb46
JC		 820 return ARRAY_SIZE(ar8327_mib);
821}
822
46587e4a 823static int
08f50061 824qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
6b93fb46
JC		 825{
826 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
827 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
828 u32 reg;
829
830 mutex_lock(&priv->reg_mutex);
831 reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
46587e4a 832 if (eee->eee_enabled)
6b93fb46
JC		 833 reg |= lpi_en;
834 else
835 reg &= ~lpi_en;
836 qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
837 mutex_unlock(&priv->reg_mutex);
6b93fb46 838
c48f7eb3 839 return 0;
6b93fb46
JC		 840}
841
842static int
08f50061 843qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
6b93fb46 844{
193da90e
VD		 845 /* Nothing to do on the port's MAC */
846 return 0;
6b93fb46
JC		 847}
848
849static void
850qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
851{
852 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
853 u32 stp_state;
854
855 switch (state) {
856 case BR_STATE_DISABLED:
857 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
858 break;
859 case BR_STATE_BLOCKING:
860 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
861 break;
862 case BR_STATE_LISTENING:
863 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
864 break;
865 case BR_STATE_LEARNING:
866 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
867 break;
868 case BR_STATE_FORWARDING:
869 default:
870 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
871 break;
872 }
873
874 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
875 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
876}
877
878static int
922754a4 879qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
6b93fb46
JC		 880{
881 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
882 int port_mask = BIT(QCA8K_CPU_PORT);
883 int i;
884
6b93fb46 885 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
c8652c83 886 if (dsa_to_port(ds, i)->bridge_dev != br)
6b93fb46
JC		 887 continue;
888 /* Add this port to the portvlan mask of the other ports
889 * in the bridge
890 */
891 qca8k_reg_set(priv,
892 QCA8K_PORT_LOOKUP_CTRL(i),
893 BIT(port));
894 if (i != port)
895 port_mask |= BIT(i);
896 }
897 /* Add all other ports to this ports portvlan mask */
898 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
899 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
900
901 return 0;
902}
903
904static void
f123f2fb 905qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
6b93fb46
JC		 906{
907 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
908 int i;
909
910 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
c8652c83 911 if (dsa_to_port(ds, i)->bridge_dev != br)
6b93fb46
JC		 912 continue;
913 /* Remove this port to the portvlan mask of the other ports
914 * in the bridge
915 */
916 qca8k_reg_clear(priv,
917 QCA8K_PORT_LOOKUP_CTRL(i),
918 BIT(port));
919 }
922754a4 920
6b93fb46
JC		 921 /* Set the cpu port to be the only one in the portvlan mask of
922 * this port
923 */
924 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
925 QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
926}
927
928static int
929qca8k_port_enable(struct dsa_switch *ds, int port,
930 struct phy_device *phy)
931{
932 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
933
934 qca8k_port_set_status(priv, port, 1);
935 priv->port_sts[port].enabled = 1;
936
937 return 0;
938}
939
940static void
75104db0 941qca8k_port_disable(struct dsa_switch *ds, int port)
6b93fb46
JC		 942{
943 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
944
945 qca8k_port_set_status(priv, port, 0);
946 priv->port_sts[port].enabled = 0;
947}
948
949static int
950qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
951 u16 port_mask, u16 vid)
952{
953 /* Set the vid to the port vlan id if no vid is set */
954 if (!vid)
955 vid = 1;
956
957 return qca8k_fdb_add(priv, addr, port_mask, vid,
958 QCA8K_ATU_STATUS_STATIC);
959}
960
961static int
6b93fb46 962qca8k_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 963 const unsigned char *addr, u16 vid)
6b93fb46
JC		 964{
965 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
966 u16 port_mask = BIT(port);
967
1b6dd556 968 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
6b93fb46
JC		 969}
970
971static int
972qca8k_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 973 const unsigned char *addr, u16 vid)
6b93fb46
JC		 974{
975 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
976 u16 port_mask = BIT(port);
6b93fb46
JC		 977
978 if (!vid)
979 vid = 1;
980
6c2c1dcb 981 return qca8k_fdb_del(priv, addr, port_mask, vid);
6b93fb46
JC		 982}
983
984static int
985qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 986 dsa_fdb_dump_cb_t *cb, void *data)
6b93fb46
JC		 987{
988 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
989 struct qca8k_fdb _fdb = { 0 };
990 int cnt = QCA8K_NUM_FDB_RECORDS;
2bedde1a 991 bool is_static;
6b93fb46
JC		 992 int ret = 0;
993
994 mutex_lock(&priv->reg_mutex);
995 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
996 if (!_fdb.aging)
997 break;
2bedde1a
AS		 998 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
999 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
6b93fb46
JC		 1000 if (ret)
1001 break;
1002 }
1003 mutex_unlock(&priv->reg_mutex);
1004
1005 return 0;
1006}
1007
1008static enum dsa_tag_protocol
5ed4e3eb 1009qca8k_get_tag_protocol(struct dsa_switch *ds, int port)
6b93fb46
JC		 1010{
1011 return DSA_TAG_PROTO_QCA;
1012}
1013
a82f67af 1014static const struct dsa_switch_ops qca8k_switch_ops = {
6b93fb46
JC		 1015 .get_tag_protocol = qca8k_get_tag_protocol,
1016 .setup = qca8k_setup,
9bb2289f 1017 .adjust_link = qca8k_adjust_link,
6b93fb46 1018 .get_strings = qca8k_get_strings,
6b93fb46
JC		 1019 .get_ethtool_stats = qca8k_get_ethtool_stats,
1020 .get_sset_count = qca8k_get_sset_count,
08f50061
VD		 1021 .get_mac_eee = qca8k_get_mac_eee,
1022 .set_mac_eee = qca8k_set_mac_eee,
6b93fb46
JC		 1023 .port_enable = qca8k_port_enable,
1024 .port_disable = qca8k_port_disable,
1025 .port_stp_state_set = qca8k_port_stp_state_set,
1026 .port_bridge_join = qca8k_port_bridge_join,
1027 .port_bridge_leave = qca8k_port_bridge_leave,
6b93fb46
JC		 1028 .port_fdb_add = qca8k_port_fdb_add,
1029 .port_fdb_del = qca8k_port_fdb_del,
1030 .port_fdb_dump = qca8k_port_fdb_dump,
1031};
1032
1033static int
1034qca8k_sw_probe(struct mdio_device *mdiodev)
1035{
1036 struct qca8k_priv *priv;
1037 u32 id;
1038
1039 /* allocate the private data struct so that we can probe the switches
1040 * ID register
1041 */
1042 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1043 if (!priv)
1044 return -ENOMEM;
1045
1046 priv->bus = mdiodev->bus;
9bb2289f 1047 priv->dev = &mdiodev->dev;
6b93fb46
JC		 1048
1049 /* read the switches ID register */
1050 id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
1051 id >>= QCA8K_MASK_CTRL_ID_S;
1052 id &= QCA8K_MASK_CTRL_ID_M;
1053 if (id != QCA8K_ID_QCA8337)
1054 return -ENODEV;
1055
a0c02161 1056 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
6b93fb46
JC		 1057 if (!priv->ds)
1058 return -ENOMEM;
1059
1060 priv->ds->priv = priv;
db460c54
CL		 1061 priv->ops = qca8k_switch_ops;
1062 priv->ds->ops = &priv->ops;
6b93fb46
JC		 1063 mutex_init(&priv->reg_mutex);
1064 dev_set_drvdata(&mdiodev->dev, priv);
1065
23c9ee49 1066 return dsa_register_switch(priv->ds);
6b93fb46
JC		 1067}
1068
1069static void
1070qca8k_sw_remove(struct mdio_device *mdiodev)
1071{
1072 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
1073 int i;
1074
1075 for (i = 0; i < QCA8K_NUM_PORTS; i++)
1076 qca8k_port_set_status(priv, i, 0);
1077
1078 dsa_unregister_switch(priv->ds);
1079}
1080
1081#ifdef CONFIG_PM_SLEEP
1082static void
1083qca8k_set_pm(struct qca8k_priv *priv, int enable)
1084{
1085 int i;
1086
1087 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1088 if (!priv->port_sts[i].enabled)
1089 continue;
1090
1091 qca8k_port_set_status(priv, i, enable);
1092 }
1093}
1094
1095static int qca8k_suspend(struct device *dev)
1096{
717de370 1097 struct qca8k_priv *priv = dev_get_drvdata(dev);
6b93fb46
JC		 1098
1099 qca8k_set_pm(priv, 0);
1100
1101 return dsa_switch_suspend(priv->ds);
1102}
1103
1104static int qca8k_resume(struct device *dev)
1105{
717de370 1106 struct qca8k_priv *priv = dev_get_drvdata(dev);
6b93fb46
JC		 1107
1108 qca8k_set_pm(priv, 1);
1109
1110 return dsa_switch_resume(priv->ds);
1111}
1112#endif /* CONFIG_PM_SLEEP */
1113
1114static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
1115 qca8k_suspend, qca8k_resume);
1116
1117static const struct of_device_id qca8k_of_match[] = {
64cf8167 1118 { .compatible = "qca,qca8334" },
6b93fb46
JC		 1119 { .compatible = "qca,qca8337" },
1120 { /* sentinel */ },
1121};
1122
1123static struct mdio_driver qca8kmdio_driver = {
1124 .probe = qca8k_sw_probe,
1125 .remove = qca8k_sw_remove,
1126 .mdiodrv.driver = {
1127 .name = "qca8k",
1128 .of_match_table = qca8k_of_match,
1129 .pm = &qca8k_pm_ops,
1130 },
1131};
1132
a084ab33 1133mdio_module_driver(qca8kmdio_driver);
6b93fb46
JC		 1134
1135MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1136MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1137MODULE_LICENSE("GPL v2");
1138MODULE_ALIAS("platform:qca8k");
Linux 6.x block layer and io_uring tree(s)