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net: phy: fix reading fixed phy status
[linux-2.6-block.git] / drivers / net / dsa / qca8k.c
CommitLineData
63a786a3 1// SPDX-License-Identifier: GPL-2.0
6b93fb46
JC		 2/*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
6b93fb46
JC		 7 */
8
9#include <linux/module.h>
10#include <linux/phy.h>
11#include <linux/netdevice.h>
12#include <net/dsa.h>
6b93fb46
JC		 13#include <linux/of_net.h>
14#include <linux/of_platform.h>
15#include <linux/if_bridge.h>
16#include <linux/mdio.h>
17#include <linux/etherdevice.h>
18
19#include "qca8k.h"
20
21#define MIB_DESC(_s, _o, _n) \
22 { \
23 .size = (_s), \
24 .offset = (_o), \
25 .name = (_n), \
26 }
27
28static const struct qca8k_mib_desc ar8327_mib[] = {
29 MIB_DESC(1, 0x00, "RxBroad"),
30 MIB_DESC(1, 0x04, "RxPause"),
31 MIB_DESC(1, 0x08, "RxMulti"),
32 MIB_DESC(1, 0x0c, "RxFcsErr"),
33 MIB_DESC(1, 0x10, "RxAlignErr"),
34 MIB_DESC(1, 0x14, "RxRunt"),
35 MIB_DESC(1, 0x18, "RxFragment"),
36 MIB_DESC(1, 0x1c, "Rx64Byte"),
37 MIB_DESC(1, 0x20, "Rx128Byte"),
38 MIB_DESC(1, 0x24, "Rx256Byte"),
39 MIB_DESC(1, 0x28, "Rx512Byte"),
40 MIB_DESC(1, 0x2c, "Rx1024Byte"),
41 MIB_DESC(1, 0x30, "Rx1518Byte"),
42 MIB_DESC(1, 0x34, "RxMaxByte"),
43 MIB_DESC(1, 0x38, "RxTooLong"),
44 MIB_DESC(2, 0x3c, "RxGoodByte"),
45 MIB_DESC(2, 0x44, "RxBadByte"),
46 MIB_DESC(1, 0x4c, "RxOverFlow"),
47 MIB_DESC(1, 0x50, "Filtered"),
48 MIB_DESC(1, 0x54, "TxBroad"),
49 MIB_DESC(1, 0x58, "TxPause"),
50 MIB_DESC(1, 0x5c, "TxMulti"),
51 MIB_DESC(1, 0x60, "TxUnderRun"),
52 MIB_DESC(1, 0x64, "Tx64Byte"),
53 MIB_DESC(1, 0x68, "Tx128Byte"),
54 MIB_DESC(1, 0x6c, "Tx256Byte"),
55 MIB_DESC(1, 0x70, "Tx512Byte"),
56 MIB_DESC(1, 0x74, "Tx1024Byte"),
57 MIB_DESC(1, 0x78, "Tx1518Byte"),
58 MIB_DESC(1, 0x7c, "TxMaxByte"),
59 MIB_DESC(1, 0x80, "TxOverSize"),
60 MIB_DESC(2, 0x84, "TxByte"),
61 MIB_DESC(1, 0x8c, "TxCollision"),
62 MIB_DESC(1, 0x90, "TxAbortCol"),
63 MIB_DESC(1, 0x94, "TxMultiCol"),
64 MIB_DESC(1, 0x98, "TxSingleCol"),
65 MIB_DESC(1, 0x9c, "TxExcDefer"),
66 MIB_DESC(1, 0xa0, "TxDefer"),
67 MIB_DESC(1, 0xa4, "TxLateCol"),
68};
69
70/* The 32bit switch registers are accessed indirectly. To achieve this we need
71 * to set the page of the register. Track the last page that was set to reduce
72 * mdio writes
73 */
74static u16 qca8k_current_page = 0xffff;
75
76static void
77qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
78{
79 regaddr >>= 1;
80 *r1 = regaddr & 0x1e;
81
82 regaddr >>= 5;
83 *r2 = regaddr & 0x7;
84
85 regaddr >>= 3;
86 *page = regaddr & 0x3ff;
87}
88
89static u32
90qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
91{
92 u32 val;
93 int ret;
94
95 ret = bus->read(bus, phy_id, regnum);
96 if (ret >= 0) {
97 val = ret;
98 ret = bus->read(bus, phy_id, regnum + 1);
99 val |= ret << 16;
100 }
101
102 if (ret < 0) {
103 dev_err_ratelimited(&bus->dev,
104 "failed to read qca8k 32bit register\n");
105 return ret;
106 }
107
108 return val;
109}
110
111static void
112qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
113{
114 u16 lo, hi;
115 int ret;
116
117 lo = val & 0xffff;
118 hi = (u16)(val >> 16);
119
120 ret = bus->write(bus, phy_id, regnum, lo);
121 if (ret >= 0)
122 ret = bus->write(bus, phy_id, regnum + 1, hi);
123 if (ret < 0)
124 dev_err_ratelimited(&bus->dev,
125 "failed to write qca8k 32bit register\n");
126}
127
128static void
129qca8k_set_page(struct mii_bus *bus, u16 page)
130{
131 if (page == qca8k_current_page)
132 return;
133
134 if (bus->write(bus, 0x18, 0, page) < 0)
135 dev_err_ratelimited(&bus->dev,
136 "failed to set qca8k page\n");
137 qca8k_current_page = page;
138}
139
140static u32
141qca8k_read(struct qca8k_priv *priv, u32 reg)
142{
143 u16 r1, r2, page;
144 u32 val;
145
146 qca8k_split_addr(reg, &r1, &r2, &page);
147
148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
149
150 qca8k_set_page(priv->bus, page);
151 val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
152
153 mutex_unlock(&priv->bus->mdio_lock);
154
155 return val;
156}
157
158static void
159qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
160{
161 u16 r1, r2, page;
162
163 qca8k_split_addr(reg, &r1, &r2, &page);
164
165 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
166
167 qca8k_set_page(priv->bus, page);
168 qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
169
170 mutex_unlock(&priv->bus->mdio_lock);
171}
172
173static u32
174qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
175{
176 u16 r1, r2, page;
177 u32 ret;
178
179 qca8k_split_addr(reg, &r1, &r2, &page);
180
181 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
182
183 qca8k_set_page(priv->bus, page);
184 ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
185 ret &= ~mask;
186 ret |= val;
187 qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);
188
189 mutex_unlock(&priv->bus->mdio_lock);
190
191 return ret;
192}
193
194static void
195qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
196{
197 qca8k_rmw(priv, reg, 0, val);
198}
199
200static void
201qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
202{
203 qca8k_rmw(priv, reg, val, 0);
204}
205
206static int
207qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
208{
209 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
210
211 *val = qca8k_read(priv, reg);
212
213 return 0;
214}
215
216static int
217qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
218{
219 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
220
221 qca8k_write(priv, reg, val);
222
223 return 0;
224}
225
226static const struct regmap_range qca8k_readable_ranges[] = {
227 regmap_reg_range(0x0000, 0x00e4), /* Global control */
228 regmap_reg_range(0x0100, 0x0168), /* EEE control */
229 regmap_reg_range(0x0200, 0x0270), /* Parser control */
230 regmap_reg_range(0x0400, 0x0454), /* ACL */
231 regmap_reg_range(0x0600, 0x0718), /* Lookup */
232 regmap_reg_range(0x0800, 0x0b70), /* QM */
233 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
234 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
235 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
236 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
237 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
238 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
239 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
240 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
241 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
242
243};
244
7e3108fa 245static const struct regmap_access_table qca8k_readable_table = {
6b93fb46
JC		 246 .yes_ranges = qca8k_readable_ranges,
247 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
248};
249
fcfbfd68 250static struct regmap_config qca8k_regmap_config = {
6b93fb46
JC		 251 .reg_bits = 16,
252 .val_bits = 32,
253 .reg_stride = 4,
254 .max_register = 0x16ac, /* end MIB - Port6 range */
255 .reg_read = qca8k_regmap_read,
256 .reg_write = qca8k_regmap_write,
257 .rd_table = &qca8k_readable_table,
258};
259
260static int
261qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
262{
263 unsigned long timeout;
264
265 timeout = jiffies + msecs_to_jiffies(20);
266
267 /* loop until the busy flag has cleared */
268 do {
269 u32 val = qca8k_read(priv, reg);
270 int busy = val & mask;
271
272 if (!busy)
273 break;
274 cond_resched();
275 } while (!time_after_eq(jiffies, timeout));
276
277 return time_after_eq(jiffies, timeout);
278}
279
280static void
281qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
282{
283 u32 reg[4];
284 int i;
285
286 /* load the ARL table into an array */
287 for (i = 0; i < 4; i++)
288 reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
289
290 /* vid - 83:72 */
291 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
292 /* aging - 67:64 */
293 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
294 /* portmask - 54:48 */
295 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
296 /* mac - 47:0 */
297 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
298 fdb->mac[1] = reg[1] & 0xff;
299 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
300 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
301 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
302 fdb->mac[5] = reg[0] & 0xff;
303}
304
305static void
306qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
307 u8 aging)
308{
309 u32 reg[3] = { 0 };
310 int i;
311
312 /* vid - 83:72 */
313 reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
314 /* aging - 67:64 */
315 reg[2] |= aging & QCA8K_ATU_STATUS_M;
316 /* portmask - 54:48 */
317 reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
318 /* mac - 47:0 */
319 reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
320 reg[1] |= mac[1];
321 reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
322 reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
323 reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
324 reg[0] |= mac[5];
325
326 /* load the array into the ARL table */
327 for (i = 0; i < 3; i++)
328 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
329}
330
331static int
332qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
333{
334 u32 reg;
335
336 /* Set the command and FDB index */
337 reg = QCA8K_ATU_FUNC_BUSY;
338 reg |= cmd;
339 if (port >= 0) {
340 reg |= QCA8K_ATU_FUNC_PORT_EN;
341 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
342 }
343
344 /* Write the function register triggering the table access */
345 qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
346
347 /* wait for completion */
348 if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
349 return -1;
350
351 /* Check for table full violation when adding an entry */
352 if (cmd == QCA8K_FDB_LOAD) {
353 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
354 if (reg & QCA8K_ATU_FUNC_FULL)
355 return -1;
356 }
357
358 return 0;
359}
360
361static int
362qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
363{
364 int ret;
365
366 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
367 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
368 if (ret >= 0)
369 qca8k_fdb_read(priv, fdb);
370
371 return ret;
372}
373
374static int
375qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
376 u16 vid, u8 aging)
377{
378 int ret;
379
380 mutex_lock(&priv->reg_mutex);
381 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
382 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
383 mutex_unlock(&priv->reg_mutex);
384
385 return ret;
386}
387
388static int
389qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
390{
391 int ret;
392
393 mutex_lock(&priv->reg_mutex);
394 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
395 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
396 mutex_unlock(&priv->reg_mutex);
397
398 return ret;
399}
400
401static void
402qca8k_fdb_flush(struct qca8k_priv *priv)
403{
404 mutex_lock(&priv->reg_mutex);
405 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
406 mutex_unlock(&priv->reg_mutex);
407}
408
409static void
410qca8k_mib_init(struct qca8k_priv *priv)
411{
412 mutex_lock(&priv->reg_mutex);
413 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
414 qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
415 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
416 qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
417 mutex_unlock(&priv->reg_mutex);
418}
419
420static int
421qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
422{
5ecdd77c 423 u32 reg, val;
6b93fb46
JC		 424
425 switch (port) {
426 case 0:
427 reg = QCA8K_REG_PORT0_PAD_CTRL;
428 break;
429 case 6:
430 reg = QCA8K_REG_PORT6_PAD_CTRL;
431 break;
432 default:
433 pr_err("Can't set PAD_CTRL on port %d\n", port);
434 return -EINVAL;
435 }
436
437 /* Configure a port to be directly connected to an external
438 * PHY or MAC.
439 */
440 switch (mode) {
441 case PHY_INTERFACE_MODE_RGMII:
5ecdd77c
VK		 442 /* RGMII mode means no delay so don't enable the delay */
443 val = QCA8K_PORT_PAD_RGMII_EN;
444 qca8k_write(priv, reg, val);
6b93fb46 445 break;
a968b5e9
VK		 446 case PHY_INTERFACE_MODE_RGMII_ID:
447 /* RGMII_ID needs internal delay. This is enabled through
448 * PORT5_PAD_CTRL for all ports, rather than individual port
449 * registers
450 */
451 qca8k_write(priv, reg,
452 QCA8K_PORT_PAD_RGMII_EN |
453 QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |
454 QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));
455 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
456 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
457 break;
6b93fb46
JC		 458 case PHY_INTERFACE_MODE_SGMII:
459 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
460 break;
461 default:
462 pr_err("xMII mode %d not supported\n", mode);
463 return -EINVAL;
464 }
465
466 return 0;
467}
468
469static void
470qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
471{
eee1fe64 472 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
6b93fb46
JC		 473
474 /* Port 0 and 6 have no internal PHY */
38222b1a 475 if (port > 0 && port < 6)
6b93fb46
JC		 476 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
477
478 if (enable)
479 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
480 else
481 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
482}
483
484static int
485qca8k_setup(struct dsa_switch *ds)
486{
487 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
488 int ret, i, phy_mode = -1;
79a4ed4f 489 u32 mask;
6b93fb46
JC		 490
491 /* Make sure that port 0 is the cpu port */
492 if (!dsa_is_cpu_port(ds, 0)) {
493 pr_err("port 0 is not the CPU port\n");
494 return -EINVAL;
495 }
496
497 mutex_init(&priv->reg_mutex);
498
499 /* Start by setting up the register mapping */
500 priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
501 &qca8k_regmap_config);
502 if (IS_ERR(priv->regmap))
503 pr_warn("regmap initialization failed");
504
505 /* Initialize CPU port pad mode (xMII type, delays...) */
0abfd494 506 phy_mode = of_get_phy_mode(ds->ports[QCA8K_CPU_PORT].dn);
6b93fb46
JC		 507 if (phy_mode < 0) {
508 pr_err("Can't find phy-mode for master device\n");
509 return phy_mode;
510 }
511 ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
512 if (ret < 0)
513 return ret;
514
79a4ed4f
MV		 515 /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
516 mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
517 QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
518 qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
6b93fb46
JC		 519 qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
520 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
521 qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
522 priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
523
524 /* Enable MIB counters */
525 qca8k_mib_init(priv);
526
527 /* Enable QCA header mode on the cpu port */
528 qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
529 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
530 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
531
532 /* Disable forwarding by default on all ports */
533 for (i = 0; i < QCA8K_NUM_PORTS; i++)
534 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
535 QCA8K_PORT_LOOKUP_MEMBER, 0);
536
537 /* Disable MAC by default on all user ports */
538 for (i = 1; i < QCA8K_NUM_PORTS; i++)
4a5b85ff 539 if (dsa_is_user_port(ds, i))
6b93fb46
JC		 540 qca8k_port_set_status(priv, i, 0);
541
542 /* Forward all unknown frames to CPU port for Linux processing */
543 qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
544 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
545 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
546 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
547 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
548
549 /* Setup connection between CPU port & user ports */
550 for (i = 0; i < DSA_MAX_PORTS; i++) {
551 /* CPU port gets connected to all user ports of the switch */
552 if (dsa_is_cpu_port(ds, i)) {
553 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
02bc6e54 554 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
6b93fb46
JC		 555 }
556
557 /* Invividual user ports get connected to CPU port only */
4a5b85ff 558 if (dsa_is_user_port(ds, i)) {
6b93fb46
JC		 559 int shift = 16 * (i % 2);
560
561 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
562 QCA8K_PORT_LOOKUP_MEMBER,
563 BIT(QCA8K_CPU_PORT));
564
565 /* Enable ARP Auto-learning by default */
566 qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
567 QCA8K_PORT_LOOKUP_LEARN);
568
569 /* For port based vlans to work we need to set the
570 * default egress vid
571 */
572 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
573 0xffff << shift, 1 << shift);
574 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
575 QCA8K_PORT_VLAN_CVID(1) |
576 QCA8K_PORT_VLAN_SVID(1));
577 }
578 }
579
580 /* Flush the FDB table */
581 qca8k_fdb_flush(priv);
582
583 return 0;
584}
585
9bb2289f
MV		 586static void
587qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
588{
589 struct qca8k_priv *priv = ds->priv;
590 u32 reg;
591
592 /* Force fixed-link setting for CPU port, skip others. */
593 if (!phy_is_pseudo_fixed_link(phy))
594 return;
595
596 /* Set port speed */
597 switch (phy->speed) {
598 case 10:
599 reg = QCA8K_PORT_STATUS_SPEED_10;
600 break;
601 case 100:
602 reg = QCA8K_PORT_STATUS_SPEED_100;
603 break;
604 case 1000:
605 reg = QCA8K_PORT_STATUS_SPEED_1000;
606 break;
607 default:
608 dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
609 port, phy->speed);
610 return;
611 }
612
613 /* Set duplex mode */
614 if (phy->duplex == DUPLEX_FULL)
615 reg |= QCA8K_PORT_STATUS_DUPLEX;
616
617 /* Force flow control */
618 if (dsa_is_cpu_port(ds, port))
619 reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
620
621 /* Force link down before changing MAC options */
622 qca8k_port_set_status(priv, port, 0);
623 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
624 qca8k_port_set_status(priv, port, 1);
625}
626
6b93fb46
JC		 627static int
628qca8k_phy_read(struct dsa_switch *ds, int phy, int regnum)
629{
630 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
631
632 return mdiobus_read(priv->bus, phy, regnum);
633}
634
635static int
636qca8k_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val)
637{
638 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
639
640 return mdiobus_write(priv->bus, phy, regnum, val);
641}
642
643static void
89f09048 644qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
6b93fb46
JC		 645{
646 int i;
647
89f09048
FF		 648 if (stringset != ETH_SS_STATS)
649 return;
650
6b93fb46
JC		 651 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
652 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
653 ETH_GSTRING_LEN);
654}
655
656static void
657qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
658 uint64_t *data)
659{
660 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
661 const struct qca8k_mib_desc *mib;
662 u32 reg, i;
663 u64 hi;
664
665 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
666 mib = &ar8327_mib[i];
667 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
668
669 data[i] = qca8k_read(priv, reg);
670 if (mib->size == 2) {
671 hi = qca8k_read(priv, reg + 4);
672 data[i] |= hi << 32;
673 }
674 }
675}
676
677static int
89f09048 678qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
6b93fb46 679{
89f09048
FF		 680 if (sset != ETH_SS_STATS)
681 return 0;
682
6b93fb46
JC		 683 return ARRAY_SIZE(ar8327_mib);
684}
685
46587e4a 686static int
08f50061 687qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
6b93fb46
JC		 688{
689 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
690 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
691 u32 reg;
692
693 mutex_lock(&priv->reg_mutex);
694 reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
46587e4a 695 if (eee->eee_enabled)
6b93fb46
JC		 696 reg |= lpi_en;
697 else
698 reg &= ~lpi_en;
699 qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
700 mutex_unlock(&priv->reg_mutex);
6b93fb46 701
c48f7eb3 702 return 0;
6b93fb46
JC		 703}
704
705static int
08f50061 706qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
6b93fb46 707{
193da90e
VD		 708 /* Nothing to do on the port's MAC */
709 return 0;
6b93fb46
JC		 710}
711
712static void
713qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
714{
715 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
716 u32 stp_state;
717
718 switch (state) {
719 case BR_STATE_DISABLED:
720 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
721 break;
722 case BR_STATE_BLOCKING:
723 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
724 break;
725 case BR_STATE_LISTENING:
726 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
727 break;
728 case BR_STATE_LEARNING:
729 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
730 break;
731 case BR_STATE_FORWARDING:
732 default:
733 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
734 break;
735 }
736
737 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
738 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
739}
740
741static int
922754a4 742qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
6b93fb46
JC		 743{
744 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
745 int port_mask = BIT(QCA8K_CPU_PORT);
746 int i;
747
6b93fb46 748 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
c8652c83 749 if (dsa_to_port(ds, i)->bridge_dev != br)
6b93fb46
JC		 750 continue;
751 /* Add this port to the portvlan mask of the other ports
752 * in the bridge
753 */
754 qca8k_reg_set(priv,
755 QCA8K_PORT_LOOKUP_CTRL(i),
756 BIT(port));
757 if (i != port)
758 port_mask |= BIT(i);
759 }
760 /* Add all other ports to this ports portvlan mask */
761 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
762 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
763
764 return 0;
765}
766
767static void
f123f2fb 768qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
6b93fb46
JC		 769{
770 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
771 int i;
772
773 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
c8652c83 774 if (dsa_to_port(ds, i)->bridge_dev != br)
6b93fb46
JC		 775 continue;
776 /* Remove this port to the portvlan mask of the other ports
777 * in the bridge
778 */
779 qca8k_reg_clear(priv,
780 QCA8K_PORT_LOOKUP_CTRL(i),
781 BIT(port));
782 }
922754a4 783
6b93fb46
JC		 784 /* Set the cpu port to be the only one in the portvlan mask of
785 * this port
786 */
787 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
788 QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
789}
790
791static int
792qca8k_port_enable(struct dsa_switch *ds, int port,
793 struct phy_device *phy)
794{
795 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
796
797 qca8k_port_set_status(priv, port, 1);
798 priv->port_sts[port].enabled = 1;
799
800 return 0;
801}
802
803static void
804qca8k_port_disable(struct dsa_switch *ds, int port,
805 struct phy_device *phy)
806{
807 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
808
809 qca8k_port_set_status(priv, port, 0);
810 priv->port_sts[port].enabled = 0;
811}
812
813static int
814qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
815 u16 port_mask, u16 vid)
816{
817 /* Set the vid to the port vlan id if no vid is set */
818 if (!vid)
819 vid = 1;
820
821 return qca8k_fdb_add(priv, addr, port_mask, vid,
822 QCA8K_ATU_STATUS_STATIC);
823}
824
825static int
6b93fb46 826qca8k_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 827 const unsigned char *addr, u16 vid)
6b93fb46
JC		 828{
829 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
830 u16 port_mask = BIT(port);
831
1b6dd556 832 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
6b93fb46
JC		 833}
834
835static int
836qca8k_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 837 const unsigned char *addr, u16 vid)
6b93fb46
JC		 838{
839 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
840 u16 port_mask = BIT(port);
6b93fb46
JC		 841
842 if (!vid)
843 vid = 1;
844
6c2c1dcb 845 return qca8k_fdb_del(priv, addr, port_mask, vid);
6b93fb46
JC		 846}
847
848static int
849qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 850 dsa_fdb_dump_cb_t *cb, void *data)
6b93fb46
JC		 851{
852 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
853 struct qca8k_fdb _fdb = { 0 };
854 int cnt = QCA8K_NUM_FDB_RECORDS;
2bedde1a 855 bool is_static;
6b93fb46
JC		 856 int ret = 0;
857
858 mutex_lock(&priv->reg_mutex);
859 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
860 if (!_fdb.aging)
861 break;
2bedde1a
AS		 862 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
863 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
6b93fb46
JC		 864 if (ret)
865 break;
866 }
867 mutex_unlock(&priv->reg_mutex);
868
869 return 0;
870}
871
872static enum dsa_tag_protocol
5ed4e3eb 873qca8k_get_tag_protocol(struct dsa_switch *ds, int port)
6b93fb46
JC		 874{
875 return DSA_TAG_PROTO_QCA;
876}
877
a82f67af 878static const struct dsa_switch_ops qca8k_switch_ops = {
6b93fb46
JC		 879 .get_tag_protocol = qca8k_get_tag_protocol,
880 .setup = qca8k_setup,
9bb2289f 881 .adjust_link = qca8k_adjust_link,
6b93fb46
JC		 882 .get_strings = qca8k_get_strings,
883 .phy_read = qca8k_phy_read,
884 .phy_write = qca8k_phy_write,
885 .get_ethtool_stats = qca8k_get_ethtool_stats,
886 .get_sset_count = qca8k_get_sset_count,
08f50061
VD		 887 .get_mac_eee = qca8k_get_mac_eee,
888 .set_mac_eee = qca8k_set_mac_eee,
6b93fb46
JC		 889 .port_enable = qca8k_port_enable,
890 .port_disable = qca8k_port_disable,
891 .port_stp_state_set = qca8k_port_stp_state_set,
892 .port_bridge_join = qca8k_port_bridge_join,
893 .port_bridge_leave = qca8k_port_bridge_leave,
6b93fb46
JC		 894 .port_fdb_add = qca8k_port_fdb_add,
895 .port_fdb_del = qca8k_port_fdb_del,
896 .port_fdb_dump = qca8k_port_fdb_dump,
897};
898
899static int
900qca8k_sw_probe(struct mdio_device *mdiodev)
901{
902 struct qca8k_priv *priv;
903 u32 id;
904
905 /* allocate the private data struct so that we can probe the switches
906 * ID register
907 */
908 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
909 if (!priv)
910 return -ENOMEM;
911
912 priv->bus = mdiodev->bus;
9bb2289f 913 priv->dev = &mdiodev->dev;
6b93fb46
JC		 914
915 /* read the switches ID register */
916 id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
917 id >>= QCA8K_MASK_CTRL_ID_S;
918 id &= QCA8K_MASK_CTRL_ID_M;
919 if (id != QCA8K_ID_QCA8337)
920 return -ENODEV;
921
a0c02161 922 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
6b93fb46
JC		 923 if (!priv->ds)
924 return -ENOMEM;
925
926 priv->ds->priv = priv;
6b93fb46
JC		 927 priv->ds->ops = &qca8k_switch_ops;
928 mutex_init(&priv->reg_mutex);
929 dev_set_drvdata(&mdiodev->dev, priv);
930
23c9ee49 931 return dsa_register_switch(priv->ds);
6b93fb46
JC		 932}
933
934static void
935qca8k_sw_remove(struct mdio_device *mdiodev)
936{
937 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
938 int i;
939
940 for (i = 0; i < QCA8K_NUM_PORTS; i++)
941 qca8k_port_set_status(priv, i, 0);
942
943 dsa_unregister_switch(priv->ds);
944}
945
946#ifdef CONFIG_PM_SLEEP
947static void
948qca8k_set_pm(struct qca8k_priv *priv, int enable)
949{
950 int i;
951
952 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
953 if (!priv->port_sts[i].enabled)
954 continue;
955
956 qca8k_port_set_status(priv, i, enable);
957 }
958}
959
960static int qca8k_suspend(struct device *dev)
961{
717de370 962 struct qca8k_priv *priv = dev_get_drvdata(dev);
6b93fb46
JC		 963
964 qca8k_set_pm(priv, 0);
965
966 return dsa_switch_suspend(priv->ds);
967}
968
969static int qca8k_resume(struct device *dev)
970{
717de370 971 struct qca8k_priv *priv = dev_get_drvdata(dev);
6b93fb46
JC		 972
973 qca8k_set_pm(priv, 1);
974
975 return dsa_switch_resume(priv->ds);
976}
977#endif /* CONFIG_PM_SLEEP */
978
979static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
980 qca8k_suspend, qca8k_resume);
981
982static const struct of_device_id qca8k_of_match[] = {
64cf8167 983 { .compatible = "qca,qca8334" },
6b93fb46
JC		 984 { .compatible = "qca,qca8337" },
985 { /* sentinel */ },
986};
987
988static struct mdio_driver qca8kmdio_driver = {
989 .probe = qca8k_sw_probe,
990 .remove = qca8k_sw_remove,
991 .mdiodrv.driver = {
992 .name = "qca8k",
993 .of_match_table = qca8k_of_match,
994 .pm = &qca8k_pm_ops,
995 },
996};
997
a084ab33 998mdio_module_driver(qca8kmdio_driver);
6b93fb46
JC		 999
1000MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1001MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1002MODULE_LICENSE("GPL v2");
1003MODULE_ALIAS("platform:qca8k");
Linux 6.x block layer and io_uring tree(s)