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Merge tag 'vfio-v4.6-rc1' of git://github.com/awilliam/linux-vfio
[linux-2.6-block.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
91da11f8
LB		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
19b2f97e 14#include <linux/delay.h>
defb05b9 15#include <linux/etherdevice.h>
dea87024 16#include <linux/ethtool.h>
facd95b2 17#include <linux/if_bridge.h>
19b2f97e 18#include <linux/jiffies.h>
91da11f8 19#include <linux/list.h>
2bbba277 20#include <linux/module.h>
91da11f8 21#include <linux/netdevice.h>
c8c1b39a 22#include <linux/gpio/consumer.h>
91da11f8 23#include <linux/phy.h>
c8f0b869 24#include <net/dsa.h>
1f36faf2 25#include <net/switchdev.h>
91da11f8
LB		 26#include "mv88e6xxx.h"
27
3996a4ff
VD		 28static void assert_smi_lock(struct dsa_switch *ds)
29{
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
31
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
34 dump_stack();
35 }
36}
37
3675c8d7 38/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
44 * registers.
45 */
46static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
47{
48 int ret;
49 int i;
50
51 for (i = 0; i < 16; i++) {
6e899e6c 52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
91da11f8
LB		 53 if (ret < 0)
54 return ret;
55
cca8b133 56 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 57 return 0;
58 }
59
60 return -ETIMEDOUT;
61}
62
b9b37713
VD		 63static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
64 int reg)
91da11f8
LB		 65{
66 int ret;
67
68 if (sw_addr == 0)
6e899e6c 69 return mdiobus_read_nested(bus, addr, reg);
91da11f8 70
3675c8d7 71 /* Wait for the bus to become free. */
91da11f8
LB		 72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
73 if (ret < 0)
74 return ret;
75
3675c8d7 76 /* Transmit the read command. */
6e899e6c
NA		 77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 79 if (ret < 0)
80 return ret;
81
3675c8d7 82 /* Wait for the read command to complete. */
91da11f8
LB		 83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
84 if (ret < 0)
85 return ret;
86
3675c8d7 87 /* Read the data. */
6e899e6c 88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
91da11f8
LB		 89 if (ret < 0)
90 return ret;
91
92 return ret & 0xffff;
93}
94
8d6d09e7 95static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
91da11f8 96{
b184e497 97 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8
LB		 98 int ret;
99
3996a4ff
VD		 100 assert_smi_lock(ds);
101
b184e497
GR		 102 if (bus == NULL)
103 return -EINVAL;
104
b184e497 105 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
bb92ea5e
VD		 106 if (ret < 0)
107 return ret;
108
109 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
110 addr, reg, ret);
111
91da11f8
LB		 112 return ret;
113}
114
8d6d09e7
GR		 115int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
116{
117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
118 int ret;
119
120 mutex_lock(&ps->smi_mutex);
121 ret = _mv88e6xxx_reg_read(ds, addr, reg);
122 mutex_unlock(&ps->smi_mutex);
123
124 return ret;
125}
126
b9b37713
VD		 127static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
128 int reg, u16 val)
91da11f8
LB		 129{
130 int ret;
131
132 if (sw_addr == 0)
6e899e6c 133 return mdiobus_write_nested(bus, addr, reg, val);
91da11f8 134
3675c8d7 135 /* Wait for the bus to become free. */
91da11f8
LB		 136 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
137 if (ret < 0)
138 return ret;
139
3675c8d7 140 /* Transmit the data to write. */
6e899e6c 141 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Transmit the write command. */
6e899e6c
NA		 146 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
147 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 148 if (ret < 0)
149 return ret;
150
3675c8d7 151 /* Wait for the write command to complete. */
91da11f8
LB		 152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
153 if (ret < 0)
154 return ret;
155
156 return 0;
157}
158
8d6d09e7
GR		 159static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
160 u16 val)
91da11f8 161{
b184e497 162 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8 163
3996a4ff
VD		 164 assert_smi_lock(ds);
165
b184e497
GR		 166 if (bus == NULL)
167 return -EINVAL;
168
bb92ea5e
VD		 169 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
170 addr, reg, val);
171
8d6d09e7
GR		 172 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
173}
174
175int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
176{
177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
178 int ret;
179
91da11f8 180 mutex_lock(&ps->smi_mutex);
8d6d09e7 181 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
91da11f8
LB		 182 mutex_unlock(&ps->smi_mutex);
183
184 return ret;
185}
186
2e5f0320
LB		 187int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
188{
cca8b133
AL		 189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
191 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2e5f0320
LB		 192
193 return 0;
194}
195
91da11f8
LB		 196int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
197{
198 int i;
199 int ret;
200
201 for (i = 0; i < 6; i++) {
202 int j;
203
3675c8d7 204 /* Write the MAC address byte. */
cca8b133
AL		 205 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
206 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
91da11f8 207
3675c8d7 208 /* Wait for the write to complete. */
91da11f8 209 for (j = 0; j < 16; j++) {
cca8b133
AL		 210 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
211 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 212 break;
213 }
214 if (j == 16)
215 return -ETIMEDOUT;
216 }
217
218 return 0;
219}
220
fd3a0ee4 221static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
91da11f8
LB		 222{
223 if (addr >= 0)
3898c148 224 return _mv88e6xxx_reg_read(ds, addr, regnum);
91da11f8
LB		 225 return 0xffff;
226}
227
fd3a0ee4
AL		 228static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
229 u16 val)
91da11f8
LB		 230{
231 if (addr >= 0)
3898c148 232 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
91da11f8
LB		 233 return 0;
234}
235
2e5f0320
LB		 236#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
238{
239 int ret;
19b2f97e 240 unsigned long timeout;
2e5f0320 241
cca8b133
AL		 242 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
243 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
244 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 245
19b2f97e
BG		 246 timeout = jiffies + 1 * HZ;
247 while (time_before(jiffies, timeout)) {
cca8b133 248 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 249 usleep_range(1000, 2000);
cca8b133
AL		 250 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
251 GLOBAL_STATUS_PPU_POLLING)
85686581 252 return 0;
2e5f0320
LB		 253 }
254
255 return -ETIMEDOUT;
256}
257
258static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
259{
260 int ret;
19b2f97e 261 unsigned long timeout;
2e5f0320 262
cca8b133
AL		 263 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
264 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 265
19b2f97e
BG		 266 timeout = jiffies + 1 * HZ;
267 while (time_before(jiffies, timeout)) {
cca8b133 268 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 269 usleep_range(1000, 2000);
cca8b133
AL		 270 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
271 GLOBAL_STATUS_PPU_POLLING)
85686581 272 return 0;
2e5f0320
LB		 273 }
274
275 return -ETIMEDOUT;
276}
277
278static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
279{
280 struct mv88e6xxx_priv_state *ps;
281
282 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
283 if (mutex_trylock(&ps->ppu_mutex)) {
85686581 284 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
2e5f0320 285
85686581
BG		 286 if (mv88e6xxx_ppu_enable(ds) == 0)
287 ps->ppu_disabled = 0;
288 mutex_unlock(&ps->ppu_mutex);
2e5f0320
LB		 289 }
290}
291
292static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
293{
294 struct mv88e6xxx_priv_state *ps = (void *)_ps;
295
296 schedule_work(&ps->ppu_work);
297}
298
299static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
300{
a22adce5 301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 302 int ret;
303
304 mutex_lock(&ps->ppu_mutex);
305
3675c8d7 306 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
309 * it.
310 */
311 if (!ps->ppu_disabled) {
85686581
BG		 312 ret = mv88e6xxx_ppu_disable(ds);
313 if (ret < 0) {
314 mutex_unlock(&ps->ppu_mutex);
315 return ret;
316 }
317 ps->ppu_disabled = 1;
2e5f0320 318 } else {
85686581
BG		 319 del_timer(&ps->ppu_timer);
320 ret = 0;
2e5f0320
LB		 321 }
322
323 return ret;
324}
325
326static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
327{
a22adce5 328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 329
3675c8d7 330 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 331 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
332 mutex_unlock(&ps->ppu_mutex);
333}
334
335void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
336{
a22adce5 337 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 338
339 mutex_init(&ps->ppu_mutex);
340 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
341 init_timer(&ps->ppu_timer);
342 ps->ppu_timer.data = (unsigned long)ps;
343 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
344}
345
346int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
347{
348 int ret;
349
350 ret = mv88e6xxx_ppu_access_get(ds);
351 if (ret >= 0) {
85686581
BG		 352 ret = mv88e6xxx_reg_read(ds, addr, regnum);
353 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 354 }
355
356 return ret;
357}
358
359int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
360 int regnum, u16 val)
361{
362 int ret;
363
364 ret = mv88e6xxx_ppu_access_get(ds);
365 if (ret >= 0) {
85686581
BG		 366 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
367 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 368 }
369
370 return ret;
371}
372#endif
373
54d792f2
AL		 374static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
375{
376 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
377
378 switch (ps->id) {
379 case PORT_SWITCH_ID_6031:
380 case PORT_SWITCH_ID_6061:
381 case PORT_SWITCH_ID_6035:
382 case PORT_SWITCH_ID_6065:
383 return true;
384 }
385 return false;
386}
387
388static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
389{
390 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
391
392 switch (ps->id) {
393 case PORT_SWITCH_ID_6092:
394 case PORT_SWITCH_ID_6095:
395 return true;
396 }
397 return false;
398}
399
400static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
401{
402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
403
404 switch (ps->id) {
405 case PORT_SWITCH_ID_6046:
406 case PORT_SWITCH_ID_6085:
407 case PORT_SWITCH_ID_6096:
408 case PORT_SWITCH_ID_6097:
409 return true;
410 }
411 return false;
412}
413
414static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
415{
416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
417
418 switch (ps->id) {
419 case PORT_SWITCH_ID_6123:
420 case PORT_SWITCH_ID_6161:
421 case PORT_SWITCH_ID_6165:
422 return true;
423 }
424 return false;
425}
426
427static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
428{
429 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
430
431 switch (ps->id) {
432 case PORT_SWITCH_ID_6121:
433 case PORT_SWITCH_ID_6122:
434 case PORT_SWITCH_ID_6152:
435 case PORT_SWITCH_ID_6155:
436 case PORT_SWITCH_ID_6182:
437 case PORT_SWITCH_ID_6185:
438 case PORT_SWITCH_ID_6108:
439 case PORT_SWITCH_ID_6131:
440 return true;
441 }
442 return false;
443}
444
c22995c5 445static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
7c3d0d67
AK		 446{
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
448
449 switch (ps->id) {
450 case PORT_SWITCH_ID_6320:
451 case PORT_SWITCH_ID_6321:
452 return true;
453 }
454 return false;
455}
456
54d792f2
AL		 457static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
458{
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
460
461 switch (ps->id) {
462 case PORT_SWITCH_ID_6171:
463 case PORT_SWITCH_ID_6175:
464 case PORT_SWITCH_ID_6350:
465 case PORT_SWITCH_ID_6351:
466 return true;
467 }
468 return false;
469}
470
f3a8b6b6
AL		 471static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
472{
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
474
475 switch (ps->id) {
f3a8b6b6
AL		 476 case PORT_SWITCH_ID_6172:
477 case PORT_SWITCH_ID_6176:
54d792f2
AL		 478 case PORT_SWITCH_ID_6240:
479 case PORT_SWITCH_ID_6352:
f3a8b6b6
AL		 480 return true;
481 }
482 return false;
483}
484
dea87024
AL		 485/* We expect the switch to perform auto negotiation if there is a real
486 * phy. However, in the case of a fixed link phy, we force the port
487 * settings from the fixed link settings.
488 */
489void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
490 struct phy_device *phydev)
491{
492 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 493 u32 reg;
494 int ret;
dea87024
AL		 495
496 if (!phy_is_pseudo_fixed_link(phydev))
497 return;
498
499 mutex_lock(&ps->smi_mutex);
500
501 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
502 if (ret < 0)
503 goto out;
504
505 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
506 PORT_PCS_CTRL_FORCE_LINK |
507 PORT_PCS_CTRL_DUPLEX_FULL |
508 PORT_PCS_CTRL_FORCE_DUPLEX |
509 PORT_PCS_CTRL_UNFORCED);
510
511 reg |= PORT_PCS_CTRL_FORCE_LINK;
512 if (phydev->link)
513 reg |= PORT_PCS_CTRL_LINK_UP;
514
515 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
516 goto out;
517
518 switch (phydev->speed) {
519 case SPEED_1000:
520 reg |= PORT_PCS_CTRL_1000;
521 break;
522 case SPEED_100:
523 reg |= PORT_PCS_CTRL_100;
524 break;
525 case SPEED_10:
526 reg |= PORT_PCS_CTRL_10;
527 break;
528 default:
529 pr_info("Unknown speed");
530 goto out;
531 }
532
533 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
534 if (phydev->duplex == DUPLEX_FULL)
535 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
536
e7e72ac0
AL		 537 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
538 (port >= ps->num_ports - 2)) {
539 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
540 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
542 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
543 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
544 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
545 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
546 }
dea87024
AL		 547 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
548
549out:
550 mutex_unlock(&ps->smi_mutex);
551}
552
31888234 553static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
91da11f8
LB		 554{
555 int ret;
556 int i;
557
558 for (i = 0; i < 10; i++) {
31888234 559 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 560 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 561 return 0;
562 }
563
564 return -ETIMEDOUT;
565}
566
31888234 567static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
91da11f8
LB		 568{
569 int ret;
570
7c3d0d67 571 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
f3a8b6b6
AL		 572 port = (port + 1) << 5;
573
3675c8d7 574 /* Snapshot the hardware statistics counters for this port. */
31888234
AL		 575 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
576 GLOBAL_STATS_OP_CAPTURE_PORT |
577 GLOBAL_STATS_OP_HIST_RX_TX | port);
578 if (ret < 0)
579 return ret;
91da11f8 580
3675c8d7 581 /* Wait for the snapshotting to complete. */
31888234 582 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 583 if (ret < 0)
584 return ret;
585
586 return 0;
587}
588
31888234 589static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
91da11f8
LB		 590{
591 u32 _val;
592 int ret;
593
594 *val = 0;
595
31888234
AL		 596 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
597 GLOBAL_STATS_OP_READ_CAPTURED |
598 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 599 if (ret < 0)
600 return;
601
31888234 602 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 603 if (ret < 0)
604 return;
605
31888234 606 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 607 if (ret < 0)
608 return;
609
610 _val = ret << 16;
611
31888234 612 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 613 if (ret < 0)
614 return;
615
616 *val = _val | ret;
617}
618
e413e7e1 619static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 620 { "in_good_octets", 8, 0x00, BANK0, },
621 { "in_bad_octets", 4, 0x02, BANK0, },
622 { "in_unicast", 4, 0x04, BANK0, },
623 { "in_broadcasts", 4, 0x06, BANK0, },
624 { "in_multicasts", 4, 0x07, BANK0, },
625 { "in_pause", 4, 0x16, BANK0, },
626 { "in_undersize", 4, 0x18, BANK0, },
627 { "in_fragments", 4, 0x19, BANK0, },
628 { "in_oversize", 4, 0x1a, BANK0, },
629 { "in_jabber", 4, 0x1b, BANK0, },
630 { "in_rx_error", 4, 0x1c, BANK0, },
631 { "in_fcs_error", 4, 0x1d, BANK0, },
632 { "out_octets", 8, 0x0e, BANK0, },
633 { "out_unicast", 4, 0x10, BANK0, },
634 { "out_broadcasts", 4, 0x13, BANK0, },
635 { "out_multicasts", 4, 0x12, BANK0, },
636 { "out_pause", 4, 0x15, BANK0, },
637 { "excessive", 4, 0x11, BANK0, },
638 { "collisions", 4, 0x1e, BANK0, },
639 { "deferred", 4, 0x05, BANK0, },
640 { "single", 4, 0x14, BANK0, },
641 { "multiple", 4, 0x17, BANK0, },
642 { "out_fcs_error", 4, 0x03, BANK0, },
643 { "late", 4, 0x1f, BANK0, },
644 { "hist_64bytes", 4, 0x08, BANK0, },
645 { "hist_65_127bytes", 4, 0x09, BANK0, },
646 { "hist_128_255bytes", 4, 0x0a, BANK0, },
647 { "hist_256_511bytes", 4, 0x0b, BANK0, },
648 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
649 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
650 { "sw_in_discards", 4, 0x10, PORT, },
651 { "sw_in_filtered", 2, 0x12, PORT, },
652 { "sw_out_filtered", 2, 0x13, PORT, },
653 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
662 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
663 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
664 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
665 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
666 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
667 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
668 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
669 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
670 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
671 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
672 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
673 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
674 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
675 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
676 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
677 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 679};
680
f5e2ed02
AL		 681static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
682 struct mv88e6xxx_hw_stat *stat)
e413e7e1 683{
f5e2ed02
AL		 684 switch (stat->type) {
685 case BANK0:
e413e7e1 686 return true;
f5e2ed02
AL		 687 case BANK1:
688 return mv88e6xxx_6320_family(ds);
689 case PORT:
690 return mv88e6xxx_6095_family(ds) ||
691 mv88e6xxx_6185_family(ds) ||
692 mv88e6xxx_6097_family(ds) ||
693 mv88e6xxx_6165_family(ds) ||
694 mv88e6xxx_6351_family(ds) ||
695 mv88e6xxx_6352_family(ds);
91da11f8 696 }
f5e2ed02 697 return false;
91da11f8
LB		 698}
699
80c4627b 700static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
f5e2ed02 701 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 702 int port)
703{
80c4627b
AL		 704 u32 low;
705 u32 high = 0;
706 int ret;
707 u64 value;
708
f5e2ed02
AL		 709 switch (s->type) {
710 case PORT:
711 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
80c4627b
AL		 712 if (ret < 0)
713 return UINT64_MAX;
714
715 low = ret;
716 if (s->sizeof_stat == 4) {
717 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
f5e2ed02 718 s->reg + 1);
80c4627b
AL		 719 if (ret < 0)
720 return UINT64_MAX;
721 high = ret;
722 }
f5e2ed02
AL		 723 break;
724 case BANK0:
725 case BANK1:
80c4627b
AL		 726 _mv88e6xxx_stats_read(ds, s->reg, &low);
727 if (s->sizeof_stat == 8)
728 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
729 }
730 value = (((u64)high) << 16) | low;
731 return value;
732}
733
f5e2ed02 734void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
91da11f8 735{
f5e2ed02
AL		 736 struct mv88e6xxx_hw_stat *stat;
737 int i, j;
91da11f8 738
f5e2ed02
AL		 739 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
740 stat = &mv88e6xxx_hw_stats[i];
741 if (mv88e6xxx_has_stat(ds, stat)) {
742 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
743 ETH_GSTRING_LEN);
744 j++;
745 }
91da11f8 746 }
e413e7e1
AL		 747}
748
749int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
750{
f5e2ed02
AL		 751 struct mv88e6xxx_hw_stat *stat;
752 int i, j;
753
754 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
755 stat = &mv88e6xxx_hw_stats[i];
756 if (mv88e6xxx_has_stat(ds, stat))
757 j++;
758 }
759 return j;
e413e7e1
AL		 760}
761
762void
763mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
764 int port, uint64_t *data)
765{
f5e2ed02
AL		 766 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
767 struct mv88e6xxx_hw_stat *stat;
768 int ret;
769 int i, j;
770
771 mutex_lock(&ps->smi_mutex);
772
773 ret = _mv88e6xxx_stats_snapshot(ds, port);
774 if (ret < 0) {
775 mutex_unlock(&ps->smi_mutex);
776 return;
777 }
778 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
779 stat = &mv88e6xxx_hw_stats[i];
780 if (mv88e6xxx_has_stat(ds, stat)) {
781 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
782 j++;
783 }
784 }
785
786 mutex_unlock(&ps->smi_mutex);
e413e7e1
AL		 787}
788
a1ab91f3
GR		 789int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
790{
791 return 32 * sizeof(u16);
792}
793
794void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
795 struct ethtool_regs *regs, void *_p)
796{
797 u16 *p = _p;
798 int i;
799
800 regs->version = 0;
801
802 memset(p, 0xff, 32 * sizeof(u16));
803
804 for (i = 0; i < 32; i++) {
805 int ret;
806
807 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
808 if (ret >= 0)
809 p[i] = ret;
810 }
811}
812
3898c148
AL		 813static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
814 u16 mask)
f3044683
AL		 815{
816 unsigned long timeout = jiffies + HZ / 10;
817
818 while (time_before(jiffies, timeout)) {
819 int ret;
820
3898c148
AL		 821 ret = _mv88e6xxx_reg_read(ds, reg, offset);
822 if (ret < 0)
823 return ret;
f3044683
AL		 824 if (!(ret & mask))
825 return 0;
826
827 usleep_range(1000, 2000);
828 }
829 return -ETIMEDOUT;
830}
831
3898c148
AL		 832static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
833{
834 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
835 int ret;
836
837 mutex_lock(&ps->smi_mutex);
838 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
839 mutex_unlock(&ps->smi_mutex);
840
841 return ret;
842}
843
844static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
f3044683 845{
3898c148
AL		 846 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
847 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 848}
849
850int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
851{
cca8b133
AL		 852 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
853 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 854}
855
856int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
857{
cca8b133
AL		 858 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
859 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 860}
861
facd95b2
GR		 862static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
863{
cca8b133
AL		 864 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
865 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 866}
867
fd3a0ee4
AL		 868static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
869 int regnum)
f3044683
AL		 870{
871 int ret;
872
3898c148
AL		 873 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
874 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
875 regnum);
876 if (ret < 0)
877 return ret;
f3044683 878
3898c148 879 ret = _mv88e6xxx_phy_wait(ds);
f3044683
AL		 880 if (ret < 0)
881 return ret;
882
3898c148 883 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
f3044683
AL		 884}
885
fd3a0ee4
AL		 886static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
887 int regnum, u16 val)
f3044683 888{
3898c148
AL		 889 int ret;
890
891 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
892 if (ret < 0)
893 return ret;
f3044683 894
3898c148
AL		 895 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
896 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
897 regnum);
898
899 return _mv88e6xxx_phy_wait(ds);
f3044683
AL		 900}
901
11b3b45d
GR		 902int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
903{
2f40c698 904 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 905 int reg;
906
3898c148 907 mutex_lock(&ps->smi_mutex);
2f40c698
AL		 908
909 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
11b3b45d 910 if (reg < 0)
2f40c698 911 goto out;
11b3b45d
GR		 912
913 e->eee_enabled = !!(reg & 0x0200);
914 e->tx_lpi_enabled = !!(reg & 0x0100);
915
3898c148 916 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
11b3b45d 917 if (reg < 0)
2f40c698 918 goto out;
11b3b45d 919
cca8b133 920 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 921 reg = 0;
11b3b45d 922
2f40c698 923out:
3898c148 924 mutex_unlock(&ps->smi_mutex);
2f40c698 925 return reg;
11b3b45d
GR		 926}
927
928int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
929 struct phy_device *phydev, struct ethtool_eee *e)
930{
2f40c698
AL		 931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
932 int reg;
11b3b45d
GR		 933 int ret;
934
3898c148 935 mutex_lock(&ps->smi_mutex);
11b3b45d 936
2f40c698
AL		 937 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
938 if (ret < 0)
939 goto out;
940
941 reg = ret & ~0x0300;
942 if (e->eee_enabled)
943 reg |= 0x0200;
944 if (e->tx_lpi_enabled)
945 reg |= 0x0100;
946
947 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
948out:
3898c148 949 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 950
951 return ret;
11b3b45d
GR		 952}
953
70cc99d1 954static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
facd95b2
GR		 955{
956 int ret;
957
cca8b133 958 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 959 if (ret < 0)
960 return ret;
961
962 return _mv88e6xxx_atu_wait(ds);
963}
964
37705b73
VD		 965static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
966 struct mv88e6xxx_atu_entry *entry)
967{
968 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
969
970 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
971 unsigned int mask, shift;
972
973 if (entry->trunk) {
974 data |= GLOBAL_ATU_DATA_TRUNK;
975 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
976 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
977 } else {
978 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
979 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
980 }
981
982 data |= (entry->portv_trunkid << shift) & mask;
983 }
984
985 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
986}
987
7fb5e755
VD		 988static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
989 struct mv88e6xxx_atu_entry *entry,
990 bool static_too)
facd95b2 991{
7fb5e755
VD		 992 int op;
993 int err;
facd95b2 994
7fb5e755
VD		 995 err = _mv88e6xxx_atu_wait(ds);
996 if (err)
997 return err;
facd95b2 998
7fb5e755
VD		 999 err = _mv88e6xxx_atu_data_write(ds, entry);
1000 if (err)
1001 return err;
1002
1003 if (entry->fid) {
1004 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1005 entry->fid);
1006 if (err)
1007 return err;
1008
1009 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1010 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1011 } else {
1012 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1013 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1014 }
1015
1016 return _mv88e6xxx_atu_cmd(ds, op);
1017}
1018
1019static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1020{
1021 struct mv88e6xxx_atu_entry entry = {
1022 .fid = fid,
1023 .state = 0, /* EntryState bits must be 0 */
1024 };
70cc99d1 1025
7fb5e755
VD		 1026 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1027}
1028
9f4d55d2
VD		 1029static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1030 int to_port, bool static_too)
1031{
1032 struct mv88e6xxx_atu_entry entry = {
1033 .trunk = false,
1034 .fid = fid,
1035 };
1036
1037 /* EntryState bits must be 0xF */
1038 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1039
1040 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1041 entry.portv_trunkid = (to_port & 0x0f) << 4;
1042 entry.portv_trunkid |= from_port & 0x0f;
1043
1044 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1045}
1046
1047static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1048 bool static_too)
1049{
1050 /* Destination port 0xF means remove the entries */
1051 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1052}
1053
facd95b2
GR		 1054static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1055{
1056 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
c3ffe6d2 1057 int reg, ret = 0;
facd95b2
GR		 1058 u8 oldstate;
1059
1060 mutex_lock(&ps->smi_mutex);
1061
cca8b133 1062 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
538cc282
GR		 1063 if (reg < 0) {
1064 ret = reg;
facd95b2 1065 goto abort;
538cc282 1066 }
facd95b2 1067
cca8b133 1068 oldstate = reg & PORT_CONTROL_STATE_MASK;
facd95b2
GR		 1069 if (oldstate != state) {
1070 /* Flush forwarding database if we're moving a port
1071 * from Learning or Forwarding state to Disabled or
1072 * Blocking or Listening state.
1073 */
cca8b133
AL		 1074 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1075 state <= PORT_CONTROL_STATE_BLOCKING) {
2b8157b1 1076 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
facd95b2
GR		 1077 if (ret)
1078 goto abort;
1079 }
cca8b133
AL		 1080 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1081 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1082 reg);
facd95b2
GR		 1083 }
1084
1085abort:
1086 mutex_unlock(&ps->smi_mutex);
1087 return ret;
1088}
1089
ede8098d
VD		 1090static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch *ds, int port,
1091 u16 output_ports)
facd95b2
GR		 1092{
1093 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
ede8098d
VD		 1094 const u16 mask = (1 << ps->num_ports) - 1;
1095 int reg;
facd95b2 1096
ede8098d
VD		 1097 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1098 if (reg < 0)
1099 return reg;
facd95b2 1100
ede8098d
VD		 1101 reg &= ~mask;
1102 reg |= output_ports & mask;
facd95b2 1103
ede8098d 1104 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1105}
1106
facd95b2
GR		 1107int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1108{
1109 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1110 int stp_state;
1111
1112 switch (state) {
1113 case BR_STATE_DISABLED:
cca8b133 1114 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1115 break;
1116 case BR_STATE_BLOCKING:
1117 case BR_STATE_LISTENING:
cca8b133 1118 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1119 break;
1120 case BR_STATE_LEARNING:
cca8b133 1121 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1122 break;
1123 case BR_STATE_FORWARDING:
1124 default:
cca8b133 1125 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1126 break;
1127 }
1128
1129 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1130
1131 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1132 * so we can not update the port state directly but need to schedule it.
1133 */
1134 ps->port_state[port] = stp_state;
1135 set_bit(port, &ps->port_state_update_mask);
1136 schedule_work(&ps->bridge_work);
1137
1138 return 0;
1139}
1140
76e398a6
VD		 1141static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1142{
1143 int ret;
1144
1145 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1146 if (ret < 0)
1147 return ret;
1148
1149 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1150
1151 return 0;
1152}
1153
b8fee957
VD		 1154int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1155{
1156 int ret;
1157
1158 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1159 if (ret < 0)
1160 return ret;
1161
1162 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1163
1164 return 0;
1165}
1166
76e398a6 1167static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
0d3b33e6 1168{
76e398a6 1169 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
0d3b33e6
VD		 1170 pvid & PORT_DEFAULT_VLAN_MASK);
1171}
1172
6b17e864
VD		 1173static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1174{
1175 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1176 GLOBAL_VTU_OP_BUSY);
1177}
1178
1179static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1180{
1181 int ret;
1182
1183 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1184 if (ret < 0)
1185 return ret;
1186
1187 return _mv88e6xxx_vtu_wait(ds);
1188}
1189
1190static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1191{
1192 int ret;
1193
1194 ret = _mv88e6xxx_vtu_wait(ds);
1195 if (ret < 0)
1196 return ret;
1197
1198 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1199}
1200
b8fee957
VD		 1201static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1202 struct mv88e6xxx_vtu_stu_entry *entry,
1203 unsigned int nibble_offset)
1204{
1205 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1206 u16 regs[3];
1207 int i;
1208 int ret;
1209
1210 for (i = 0; i < 3; ++i) {
1211 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1212 GLOBAL_VTU_DATA_0_3 + i);
1213 if (ret < 0)
1214 return ret;
1215
1216 regs[i] = ret;
1217 }
1218
1219 for (i = 0; i < ps->num_ports; ++i) {
1220 unsigned int shift = (i % 4) * 4 + nibble_offset;
1221 u16 reg = regs[i / 4];
1222
1223 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1224 }
1225
1226 return 0;
1227}
1228
7dad08d7
VD		 1229static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1230 struct mv88e6xxx_vtu_stu_entry *entry,
1231 unsigned int nibble_offset)
1232{
1233 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1234 u16 regs[3] = { 0 };
1235 int i;
1236 int ret;
1237
1238 for (i = 0; i < ps->num_ports; ++i) {
1239 unsigned int shift = (i % 4) * 4 + nibble_offset;
1240 u8 data = entry->data[i];
1241
1242 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1243 }
1244
1245 for (i = 0; i < 3; ++i) {
1246 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1247 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1248 if (ret < 0)
1249 return ret;
1250 }
1251
1252 return 0;
1253}
1254
36d04ba1
VD		 1255static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1256{
1257 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1258 vid & GLOBAL_VTU_VID_MASK);
1259}
1260
1261static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
b8fee957
VD		 1262 struct mv88e6xxx_vtu_stu_entry *entry)
1263{
1264 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1265 int ret;
1266
1267 ret = _mv88e6xxx_vtu_wait(ds);
1268 if (ret < 0)
1269 return ret;
1270
b8fee957
VD		 1271 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1272 if (ret < 0)
1273 return ret;
1274
1275 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1276 if (ret < 0)
1277 return ret;
1278
1279 next.vid = ret & GLOBAL_VTU_VID_MASK;
1280 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1281
1282 if (next.valid) {
1283 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1284 if (ret < 0)
1285 return ret;
1286
1287 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1288 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1289 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1290 GLOBAL_VTU_FID);
1291 if (ret < 0)
1292 return ret;
1293
1294 next.fid = ret & GLOBAL_VTU_FID_MASK;
1295
1296 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1297 GLOBAL_VTU_SID);
1298 if (ret < 0)
1299 return ret;
1300
1301 next.sid = ret & GLOBAL_VTU_SID_MASK;
1302 }
1303 }
1304
1305 *entry = next;
1306 return 0;
1307}
1308
7dad08d7
VD		 1309static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1310 struct mv88e6xxx_vtu_stu_entry *entry)
1311{
1312 u16 reg = 0;
1313 int ret;
1314
1315 ret = _mv88e6xxx_vtu_wait(ds);
1316 if (ret < 0)
1317 return ret;
1318
1319 if (!entry->valid)
1320 goto loadpurge;
1321
1322 /* Write port member tags */
1323 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1324 if (ret < 0)
1325 return ret;
1326
1327 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1328 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1329 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1330 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1331 if (ret < 0)
1332 return ret;
1333
1334 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1335 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1336 if (ret < 0)
1337 return ret;
1338 }
1339
1340 reg = GLOBAL_VTU_VID_VALID;
1341loadpurge:
1342 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1343 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1344 if (ret < 0)
1345 return ret;
1346
1347 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1348}
1349
0d3b33e6
VD		 1350static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1351 struct mv88e6xxx_vtu_stu_entry *entry)
1352{
1353 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1354 int ret;
1355
1356 ret = _mv88e6xxx_vtu_wait(ds);
1357 if (ret < 0)
1358 return ret;
1359
1360 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1361 sid & GLOBAL_VTU_SID_MASK);
1362 if (ret < 0)
1363 return ret;
1364
1365 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1366 if (ret < 0)
1367 return ret;
1368
1369 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1370 if (ret < 0)
1371 return ret;
1372
1373 next.sid = ret & GLOBAL_VTU_SID_MASK;
1374
1375 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1376 if (ret < 0)
1377 return ret;
1378
1379 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1380
1381 if (next.valid) {
1382 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1383 if (ret < 0)
1384 return ret;
1385 }
1386
1387 *entry = next;
1388 return 0;
1389}
1390
1391static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1392 struct mv88e6xxx_vtu_stu_entry *entry)
1393{
1394 u16 reg = 0;
1395 int ret;
1396
1397 ret = _mv88e6xxx_vtu_wait(ds);
1398 if (ret < 0)
1399 return ret;
1400
1401 if (!entry->valid)
1402 goto loadpurge;
1403
1404 /* Write port states */
1405 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1406 if (ret < 0)
1407 return ret;
1408
1409 reg = GLOBAL_VTU_VID_VALID;
1410loadpurge:
1411 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1412 if (ret < 0)
1413 return ret;
1414
1415 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1416 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1417 if (ret < 0)
1418 return ret;
1419
1420 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1421}
1422
1423static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid,
1424 struct mv88e6xxx_vtu_stu_entry *entry)
1425{
1426 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1427 struct mv88e6xxx_vtu_stu_entry vlan = {
1428 .valid = true,
1429 .vid = vid,
f02bdffc 1430 .fid = vid, /* We use one FID per VLAN */
0d3b33e6
VD		 1431 };
1432 int i;
1433
3d131f07 1434 /* exclude all ports except the CPU and DSA ports */
0d3b33e6 1435 for (i = 0; i < ps->num_ports; ++i)
3d131f07
VD		 1436 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1437 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1438 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6
VD		 1439
1440 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1441 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1442 struct mv88e6xxx_vtu_stu_entry vstp;
1443 int err;
1444
1445 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1446 * implemented, only one STU entry is needed to cover all VTU
1447 * entries. Thus, validate the SID 0.
1448 */
1449 vlan.sid = 0;
1450 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1451 if (err)
1452 return err;
1453
1454 if (vstp.sid != vlan.sid || !vstp.valid) {
1455 memset(&vstp, 0, sizeof(vstp));
1456 vstp.valid = true;
1457 vstp.sid = vlan.sid;
1458
1459 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1460 if (err)
1461 return err;
1462 }
1463
7c400018
VD		 1464 /* Clear all MAC addresses from the new database */
1465 err = _mv88e6xxx_atu_flush(ds, vlan.fid, true);
0d3b33e6
VD		 1466 if (err)
1467 return err;
0d3b33e6
VD		 1468 }
1469
1470 *entry = vlan;
1471 return 0;
1472}
1473
76e398a6
VD		 1474int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1475 const struct switchdev_obj_port_vlan *vlan,
1476 struct switchdev_trans *trans)
1477{
e79a8bcb
VD		 1478 /* We reserve a few VLANs to isolate unbridged ports */
1479 if (vlan->vid_end >= 4000)
1480 return -EOPNOTSUPP;
1481
76e398a6
VD		 1482 /* We don't need any dynamic resource from the kernel (yet),
1483 * so skip the prepare phase.
1484 */
1485 return 0;
1486}
1487
1488static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1489 bool untagged)
0d3b33e6 1490{
0d3b33e6
VD		 1491 struct mv88e6xxx_vtu_stu_entry vlan;
1492 int err;
1493
36d04ba1
VD		 1494 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1495 if (err)
76e398a6 1496 return err;
36d04ba1
VD		 1497
1498 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
0d3b33e6 1499 if (err)
76e398a6 1500 return err;
0d3b33e6
VD		 1501
1502 if (vlan.vid != vid || !vlan.valid) {
1503 err = _mv88e6xxx_vlan_init(ds, vid, &vlan);
1504 if (err)
76e398a6 1505 return err;
0d3b33e6
VD		 1506 }
1507
1508 vlan.data[port] = untagged ?
1509 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1510 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1511
76e398a6
VD		 1512 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1513}
1514
1515int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1516 const struct switchdev_obj_port_vlan *vlan,
1517 struct switchdev_trans *trans)
1518{
1519 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1520 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1521 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1522 u16 vid;
1523 int err = 0;
1524
1525 mutex_lock(&ps->smi_mutex);
1526
1527 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1528 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1529 if (err)
1530 goto unlock;
1531 }
1532
1533 /* no PVID with ranges, otherwise it's a bug */
1534 if (pvid)
db0e51af 1535 err = _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end);
0d3b33e6
VD		 1536unlock:
1537 mutex_unlock(&ps->smi_mutex);
1538
1539 return err;
1540}
1541
76e398a6 1542static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
7dad08d7
VD		 1543{
1544 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1545 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1546 int i, err;
1547
36d04ba1
VD		 1548 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1549 if (err)
76e398a6 1550 return err;
36d04ba1
VD		 1551
1552 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
7dad08d7 1553 if (err)
76e398a6 1554 return err;
7dad08d7
VD		 1555
1556 if (vlan.vid != vid || !vlan.valid ||
76e398a6 1557 vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1558 return -EOPNOTSUPP;
7dad08d7
VD		 1559
1560 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1561
1562 /* keep the VLAN unless all ports are excluded */
f02bdffc 1563 vlan.valid = false;
7dad08d7 1564 for (i = 0; i < ps->num_ports; ++i) {
3d131f07 1565 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1566 continue;
1567
1568 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1569 vlan.valid = true;
7dad08d7
VD		 1570 break;
1571 }
1572 }
1573
7dad08d7 1574 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
76e398a6
VD		 1575 if (err)
1576 return err;
1577
1578 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1579}
1580
1581int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1582 const struct switchdev_obj_port_vlan *vlan)
1583{
1584 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
66d9cd0f 1585 const u16 defpvid = 4000 + ds->index * DSA_MAX_PORTS + port;
76e398a6
VD		 1586 u16 pvid, vid;
1587 int err = 0;
1588
1589 mutex_lock(&ps->smi_mutex);
1590
1591 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
7dad08d7
VD		 1592 if (err)
1593 goto unlock;
1594
76e398a6
VD		 1595 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1596 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1597 if (err)
1598 goto unlock;
1599
1600 if (vid == pvid) {
66d9cd0f
VD		 1601 /* restore reserved VLAN ID */
1602 err = _mv88e6xxx_port_pvid_set(ds, port, defpvid);
76e398a6
VD		 1603 if (err)
1604 goto unlock;
1605 }
1606 }
1607
7dad08d7
VD		 1608unlock:
1609 mutex_unlock(&ps->smi_mutex);
1610
1611 return err;
1612}
1613
b8fee957
VD		 1614int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid,
1615 unsigned long *ports, unsigned long *untagged)
1616{
1617 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1618 struct mv88e6xxx_vtu_stu_entry next;
1619 int port;
1620 int err;
1621
1622 if (*vid == 4095)
1623 return -ENOENT;
1624
1625 mutex_lock(&ps->smi_mutex);
36d04ba1
VD		 1626 err = _mv88e6xxx_vtu_vid_write(ds, *vid);
1627 if (err)
1628 goto unlock;
1629
1630 err = _mv88e6xxx_vtu_getnext(ds, &next);
1631unlock:
b8fee957
VD		 1632 mutex_unlock(&ps->smi_mutex);
1633
1634 if (err)
1635 return err;
1636
1637 if (!next.valid)
1638 return -ENOENT;
1639
1640 *vid = next.vid;
1641
1642 for (port = 0; port < ps->num_ports; ++port) {
1643 clear_bit(port, ports);
1644 clear_bit(port, untagged);
1645
3d131f07 1646 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
b8fee957
VD		 1647 continue;
1648
1649 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED ||
1650 next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1651 set_bit(port, ports);
1652
1653 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1654 set_bit(port, untagged);
1655 }
1656
1657 return 0;
1658}
1659
c5723ac5
VD		 1660static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1661 const unsigned char *addr)
defb05b9
GR		 1662{
1663 int i, ret;
1664
1665 for (i = 0; i < 3; i++) {
cca8b133
AL		 1666 ret = _mv88e6xxx_reg_write(
1667 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1668 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 1669 if (ret < 0)
1670 return ret;
1671 }
1672
1673 return 0;
1674}
1675
c5723ac5 1676static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
defb05b9
GR		 1677{
1678 int i, ret;
1679
1680 for (i = 0; i < 3; i++) {
cca8b133
AL		 1681 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1682 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 1683 if (ret < 0)
1684 return ret;
1685 addr[i * 2] = ret >> 8;
1686 addr[i * 2 + 1] = ret & 0xff;
1687 }
1688
1689 return 0;
1690}
1691
fd231c82
VD		 1692static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1693 struct mv88e6xxx_atu_entry *entry)
defb05b9 1694{
6630e236
VD		 1695 int ret;
1696
defb05b9
GR		 1697 ret = _mv88e6xxx_atu_wait(ds);
1698 if (ret < 0)
1699 return ret;
1700
fd231c82 1701 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
defb05b9
GR		 1702 if (ret < 0)
1703 return ret;
1704
37705b73 1705 ret = _mv88e6xxx_atu_data_write(ds, entry);
fd231c82 1706 if (ret < 0)
87820510
VD		 1707 return ret;
1708
70cc99d1
VD		 1709 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1710 if (ret < 0)
1711 return ret;
1712
1713 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 1714}
87820510 1715
fd231c82
VD		 1716static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1717 const unsigned char *addr, u16 vid,
1718 u8 state)
1719{
1720 struct mv88e6xxx_atu_entry entry = { 0 };
fd231c82 1721
f02bdffc 1722 entry.fid = vid; /* We use one FID per VLAN */
fd231c82
VD		 1723 entry.state = state;
1724 ether_addr_copy(entry.mac, addr);
1725 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1726 entry.trunk = false;
1727 entry.portv_trunkid = BIT(port);
1728 }
1729
1730 return _mv88e6xxx_atu_load(ds, &entry);
87820510
VD		 1731}
1732
146a3206
VD		 1733int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1734 const struct switchdev_obj_port_fdb *fdb,
1735 struct switchdev_trans *trans)
1736{
f02bdffc
VD		 1737 /* We don't use per-port FDB */
1738 if (fdb->vid == 0)
1739 return -EOPNOTSUPP;
1740
146a3206
VD		 1741 /* We don't need any dynamic resource from the kernel (yet),
1742 * so skip the prepare phase.
1743 */
1744 return 0;
1745}
1746
cdf09697 1747int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1f36faf2
VD		 1748 const struct switchdev_obj_port_fdb *fdb,
1749 struct switchdev_trans *trans)
87820510 1750{
1f36faf2 1751 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 1752 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1753 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 1754 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 1755 int ret;
1756
1757 mutex_lock(&ps->smi_mutex);
1f36faf2 1758 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
87820510
VD		 1759 mutex_unlock(&ps->smi_mutex);
1760
1761 return ret;
1762}
1763
cdf09697 1764int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
8057b3e7 1765 const struct switchdev_obj_port_fdb *fdb)
87820510
VD		 1766{
1767 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 1768 int ret;
1769
1770 mutex_lock(&ps->smi_mutex);
8057b3e7 1771 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
cdf09697 1772 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 1773 mutex_unlock(&ps->smi_mutex);
1774
1775 return ret;
1776}
1777
1d194046 1778static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1d194046 1779 struct mv88e6xxx_atu_entry *entry)
6630e236 1780{
1d194046
VD		 1781 struct mv88e6xxx_atu_entry next = { 0 };
1782 int ret;
1783
1784 next.fid = fid;
defb05b9 1785
cdf09697
DM		 1786 ret = _mv88e6xxx_atu_wait(ds);
1787 if (ret < 0)
1788 return ret;
6630e236 1789
70cc99d1
VD		 1790 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1791 if (ret < 0)
1792 return ret;
1793
1794 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 1795 if (ret < 0)
1796 return ret;
6630e236 1797
1d194046
VD		 1798 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1799 if (ret < 0)
1800 return ret;
6630e236 1801
1d194046 1802 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 1803 if (ret < 0)
1804 return ret;
6630e236 1805
1d194046
VD		 1806 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1807 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1808 unsigned int mask, shift;
1809
1810 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1811 next.trunk = true;
1812 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1813 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1814 } else {
1815 next.trunk = false;
1816 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1817 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1818 }
1819
1820 next.portv_trunkid = (ret & mask) >> shift;
1821 }
cdf09697 1822
1d194046 1823 *entry = next;
cdf09697
DM		 1824 return 0;
1825}
1826
f33475bd
VD		 1827int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1828 struct switchdev_obj_port_fdb *fdb,
1829 int (*cb)(struct switchdev_obj *obj))
1830{
1831 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1832 struct mv88e6xxx_vtu_stu_entry vlan = {
1833 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
1834 };
1835 int err;
1836
1837 mutex_lock(&ps->smi_mutex);
1838
1839 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
1840 if (err)
1841 goto unlock;
1842
1843 do {
1844 struct mv88e6xxx_atu_entry addr = {
1845 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
1846 };
1847
1848 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1849 if (err)
1850 goto unlock;
1851
1852 if (!vlan.valid)
1853 break;
1854
1855 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
1856 if (err)
1857 goto unlock;
1858
1859 do {
1860 err = _mv88e6xxx_atu_getnext(ds, vlan.fid, &addr);
1861 if (err)
1862 goto unlock;
1863
1864 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1865 break;
1866
1867 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
1868 bool is_static = addr.state ==
1869 (is_multicast_ether_addr(addr.mac) ?
1870 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1871 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1872
1873 fdb->vid = vlan.vid;
1874 ether_addr_copy(fdb->addr, addr.mac);
1875 fdb->ndm_state = is_static ? NUD_NOARP :
1876 NUD_REACHABLE;
1877
1878 err = cb(&fdb->obj);
1879 if (err)
1880 goto unlock;
1881 }
1882 } while (!is_broadcast_ether_addr(addr.mac));
1883
1884 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1885
1886unlock:
1887 mutex_unlock(&ps->smi_mutex);
1888
1889 return err;
1890}
1891
e79a8bcb
VD		 1892int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, u32 members)
1893{
66d9cd0f 1894 return 0;
e79a8bcb
VD		 1895}
1896
1897int mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, u32 members)
66d9cd0f
VD		 1898{
1899 return 0;
1900}
1901
1902static int mv88e6xxx_setup_port_default_vlan(struct dsa_switch *ds, int port)
e79a8bcb
VD		 1903{
1904 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1905 const u16 pvid = 4000 + ds->index * DSA_MAX_PORTS + port;
1906 int err;
1907
e79a8bcb
VD		 1908 mutex_lock(&ps->smi_mutex);
1909 err = _mv88e6xxx_port_vlan_add(ds, port, pvid, true);
1910 if (!err)
1911 err = _mv88e6xxx_port_pvid_set(ds, port, pvid);
1912 mutex_unlock(&ps->smi_mutex);
1913 return err;
1914}
1915
facd95b2
GR		 1916static void mv88e6xxx_bridge_work(struct work_struct *work)
1917{
1918 struct mv88e6xxx_priv_state *ps;
1919 struct dsa_switch *ds;
1920 int port;
1921
1922 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1923 ds = ((struct dsa_switch *)ps) - 1;
1924
1925 while (ps->port_state_update_mask) {
1926 port = __ffs(ps->port_state_update_mask);
1927 clear_bit(port, &ps->port_state_update_mask);
1928 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1929 }
1930}
1931
dbde9e66 1932static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
d827e88a
GR		 1933{
1934 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f02bdffc 1935 int ret;
54d792f2 1936 u16 reg;
d827e88a
GR		 1937
1938 mutex_lock(&ps->smi_mutex);
1939
54d792f2
AL		 1940 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1941 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1942 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
7c3d0d67 1943 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 1944 /* MAC Forcing register: don't force link, speed,
1945 * duplex or flow control state to any particular
1946 * values on physical ports, but force the CPU port
1947 * and all DSA ports to their maximum bandwidth and
1948 * full duplex.
1949 */
1950 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 1951 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 1952 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 1953 reg |= PORT_PCS_CTRL_FORCE_LINK |
1954 PORT_PCS_CTRL_LINK_UP |
1955 PORT_PCS_CTRL_DUPLEX_FULL |
1956 PORT_PCS_CTRL_FORCE_DUPLEX;
1957 if (mv88e6xxx_6065_family(ds))
1958 reg |= PORT_PCS_CTRL_100;
1959 else
1960 reg |= PORT_PCS_CTRL_1000;
1961 } else {
1962 reg |= PORT_PCS_CTRL_UNFORCED;
1963 }
1964
1965 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1966 PORT_PCS_CTRL, reg);
1967 if (ret)
1968 goto abort;
1969 }
1970
1971 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1972 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1973 * tunneling, determine priority by looking at 802.1p and IP
1974 * priority fields (IP prio has precedence), and set STP state
1975 * to Forwarding.
1976 *
1977 * If this is the CPU link, use DSA or EDSA tagging depending
1978 * on which tagging mode was configured.
1979 *
1980 * If this is a link to another switch, use DSA tagging mode.
1981 *
1982 * If this is the upstream port for this switch, enable
1983 * forwarding of unknown unicasts and multicasts.
1984 */
1985 reg = 0;
1986 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1987 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1988 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 1989 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 1990 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1991 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1992 PORT_CONTROL_STATE_FORWARDING;
1993 if (dsa_is_cpu_port(ds, port)) {
1994 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1995 reg |= PORT_CONTROL_DSA_TAG;
1996 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 1997 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1998 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 1999 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2000 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2001 else
2002 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2003 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2004 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2005 }
2006
2007 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2008 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2009 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2010 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2011 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2012 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2013 }
2014 }
6083ce71
AL		 2015 if (dsa_is_dsa_port(ds, port)) {
2016 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2017 reg |= PORT_CONTROL_DSA_TAG;
2018 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2019 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2020 mv88e6xxx_6320_family(ds)) {
54d792f2 2021 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2022 }
2023
54d792f2
AL		 2024 if (port == dsa_upstream_port(ds))
2025 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2026 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2027 }
2028 if (reg) {
2029 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2030 PORT_CONTROL, reg);
2031 if (ret)
2032 goto abort;
2033 }
2034
8efdda4a
VD		 2035 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2036 * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
2037 * untagged frames on this port, do a destination address lookup on all
2038 * received packets as usual, disable ARP mirroring and don't send a
2039 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2040 */
2041 reg = 0;
2042 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2043 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67 2044 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2045 reg = PORT_CONTROL_2_MAP_DA;
2046
2047 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67 2048 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2049 reg |= PORT_CONTROL_2_JUMBO_10240;
2050
2051 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2052 /* Set the upstream port this port should use */
2053 reg |= dsa_upstream_port(ds);
2054 /* enable forwarding of unknown multicast addresses to
2055 * the upstream port
2056 */
2057 if (port == dsa_upstream_port(ds))
2058 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2059 }
2060
5fe7f680 2061 reg |= PORT_CONTROL_2_8021Q_SECURE;
8efdda4a 2062
54d792f2
AL		 2063 if (reg) {
2064 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2065 PORT_CONTROL_2, reg);
2066 if (ret)
2067 goto abort;
2068 }
2069
2070 /* Port Association Vector: when learning source addresses
2071 * of packets, add the address to the address database using
2072 * a port bitmap that has only the bit for this port set and
2073 * the other bits clear.
2074 */
4c7ea3c0
AL		 2075 reg = 1 << port;
2076 /* Disable learning for DSA and CPU ports */
2077 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2078 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2079
2080 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
54d792f2
AL		 2081 if (ret)
2082 goto abort;
2083
2084 /* Egress rate control 2: disable egress rate control. */
2085 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2086 0x0000);
2087 if (ret)
2088 goto abort;
2089
2090 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2091 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2092 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2093 /* Do not limit the period of time that this port can
2094 * be paused for by the remote end or the period of
2095 * time that this port can pause the remote end.
2096 */
2097 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2098 PORT_PAUSE_CTRL, 0x0000);
2099 if (ret)
2100 goto abort;
2101
2102 /* Port ATU control: disable limiting the number of
2103 * address database entries that this port is allowed
2104 * to use.
2105 */
2106 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2107 PORT_ATU_CONTROL, 0x0000);
2108 /* Priority Override: disable DA, SA and VTU priority
2109 * override.
2110 */
2111 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2112 PORT_PRI_OVERRIDE, 0x0000);
2113 if (ret)
2114 goto abort;
2115
2116 /* Port Ethertype: use the Ethertype DSA Ethertype
2117 * value.
2118 */
2119 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2120 PORT_ETH_TYPE, ETH_P_EDSA);
2121 if (ret)
2122 goto abort;
2123 /* Tag Remap: use an identity 802.1p prio -> switch
2124 * prio mapping.
2125 */
2126 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2127 PORT_TAG_REGMAP_0123, 0x3210);
2128 if (ret)
2129 goto abort;
2130
2131 /* Tag Remap 2: use an identity 802.1p prio -> switch
2132 * prio mapping.
2133 */
2134 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2135 PORT_TAG_REGMAP_4567, 0x7654);
2136 if (ret)
2137 goto abort;
2138 }
2139
2140 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2141 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2142 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2143 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2144 /* Rate Control: disable ingress rate limiting. */
2145 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2146 PORT_RATE_CONTROL, 0x0001);
2147 if (ret)
2148 goto abort;
2149 }
2150
366f0a0f
GR		 2151 /* Port Control 1: disable trunking, disable sending
2152 * learning messages to this port.
d827e88a 2153 */
614f03fc 2154 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a
GR		 2155 if (ret)
2156 goto abort;
2157
f02bdffc 2158 /* Port based VLAN map: do not give each port its own address
5fe7f680 2159 * database, and allow every port to egress frames on all other ports.
d827e88a 2160 */
5fe7f680 2161 reg = BIT(ps->num_ports) - 1; /* all ports */
be1faa92
VD		 2162 reg &= ~BIT(port); /* except itself */
2163 ret = _mv88e6xxx_port_vlan_map_set(ds, port, reg);
d827e88a
GR		 2164 if (ret)
2165 goto abort;
2166
2167 /* Default VLAN ID and priority: don't set a default VLAN
2168 * ID, and set the default packet priority to zero.
2169 */
47cf1e65
VD		 2170 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2171 0x0000);
d827e88a
GR		 2172abort:
2173 mutex_unlock(&ps->smi_mutex);
2174 return ret;
2175}
2176
dbde9e66
AL		 2177int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2178{
2179 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2180 int ret;
2181 int i;
2182
2183 for (i = 0; i < ps->num_ports; i++) {
2184 ret = mv88e6xxx_setup_port(ds, i);
2185 if (ret < 0)
2186 return ret;
e79a8bcb
VD		 2187
2188 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2189 continue;
2190
66d9cd0f 2191 ret = mv88e6xxx_setup_port_default_vlan(ds, i);
e79a8bcb
VD		 2192 if (ret < 0)
2193 return ret;
dbde9e66
AL		 2194 }
2195 return 0;
2196}
2197
acdaffcc
GR		 2198int mv88e6xxx_setup_common(struct dsa_switch *ds)
2199{
2200 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2201
2202 mutex_init(&ps->smi_mutex);
acdaffcc 2203
cca8b133 2204 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
a8f064c6 2205
facd95b2
GR		 2206 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2207
acdaffcc
GR		 2208 return 0;
2209}
2210
54d792f2
AL		 2211int mv88e6xxx_setup_global(struct dsa_switch *ds)
2212{
2213 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
24751e29 2214 int ret;
54d792f2
AL		 2215 int i;
2216
2217 /* Set the default address aging time to 5 minutes, and
2218 * enable address learn messages to be sent to all message
2219 * ports.
2220 */
2221 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2222 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2223
2224 /* Configure the IP ToS mapping registers. */
2225 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2226 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2227 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2228 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2229 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2230 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2231 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2232 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2233
2234 /* Configure the IEEE 802.1p priority mapping register. */
2235 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2236
2237 /* Send all frames with destination addresses matching
2238 * 01:80:c2:00:00:0x to the CPU port.
2239 */
2240 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2241
2242 /* Ignore removed tag data on doubly tagged packets, disable
2243 * flow control messages, force flow control priority to the
2244 * highest, and send all special multicast frames to the CPU
2245 * port at the highest priority.
2246 */
2247 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2248 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2249 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2250
2251 /* Program the DSA routing table. */
2252 for (i = 0; i < 32; i++) {
2253 int nexthop = 0x1f;
2254
2255 if (ds->pd->rtable &&
2256 i != ds->index && i < ds->dst->pd->nr_chips)
2257 nexthop = ds->pd->rtable[i] & 0x1f;
2258
2259 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2260 GLOBAL2_DEVICE_MAPPING_UPDATE |
2261 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2262 nexthop);
2263 }
2264
2265 /* Clear all trunk masks. */
2266 for (i = 0; i < 8; i++)
2267 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2268 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2269 ((1 << ps->num_ports) - 1));
2270
2271 /* Clear all trunk mappings. */
2272 for (i = 0; i < 16; i++)
2273 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2274 GLOBAL2_TRUNK_MAPPING_UPDATE |
2275 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2276
2277 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2278 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2279 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2280 /* Send all frames with destination addresses matching
2281 * 01:80:c2:00:00:2x to the CPU port.
2282 */
2283 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2284
2285 /* Initialise cross-chip port VLAN table to reset
2286 * defaults.
2287 */
2288 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2289
2290 /* Clear the priority override table. */
2291 for (i = 0; i < 16; i++)
2292 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2293 0x8000 | (i << 8));
2294 }
2295
2296 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2297 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2298 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2299 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2300 /* Disable ingress rate limiting by resetting all
2301 * ingress rate limit registers to their initial
2302 * state.
2303 */
2304 for (i = 0; i < ps->num_ports; i++)
2305 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2306 0x9000 | (i << 8));
2307 }
2308
db687a56
AL		 2309 /* Clear the statistics counters for all ports */
2310 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2311
2312 /* Wait for the flush to complete. */
24751e29
VD		 2313 mutex_lock(&ps->smi_mutex);
2314 ret = _mv88e6xxx_stats_wait(ds);
6b17e864
VD		 2315 if (ret < 0)
2316 goto unlock;
2317
c161d0a5
VD		 2318 /* Clear all ATU entries */
2319 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2320 if (ret < 0)
2321 goto unlock;
2322
6b17e864
VD		 2323 /* Clear all the VTU and STU entries */
2324 ret = _mv88e6xxx_vtu_stu_flush(ds);
2325unlock:
24751e29 2326 mutex_unlock(&ps->smi_mutex);
db687a56 2327
24751e29 2328 return ret;
54d792f2
AL		 2329}
2330
143a8307
AL		 2331int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2332{
2333 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2334 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
c8c1b39a 2335 struct gpio_desc *gpiod = ds->pd->reset;
143a8307
AL		 2336 unsigned long timeout;
2337 int ret;
2338 int i;
2339
2340 /* Set all ports to the disabled state. */
2341 for (i = 0; i < ps->num_ports; i++) {
cca8b133
AL		 2342 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2343 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
143a8307
AL		 2344 }
2345
2346 /* Wait for transmit queues to drain. */
2347 usleep_range(2000, 4000);
2348
c8c1b39a
AL		 2349 /* If there is a gpio connected to the reset pin, toggle it */
2350 if (gpiod) {
2351 gpiod_set_value_cansleep(gpiod, 1);
2352 usleep_range(10000, 20000);
2353 gpiod_set_value_cansleep(gpiod, 0);
2354 usleep_range(10000, 20000);
2355 }
2356
143a8307
AL		 2357 /* Reset the switch. Keep the PPU active if requested. The PPU
2358 * needs to be active to support indirect phy register access
2359 * through global registers 0x18 and 0x19.
2360 */
2361 if (ppu_active)
2362 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2363 else
2364 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2365
2366 /* Wait up to one second for reset to complete. */
2367 timeout = jiffies + 1 * HZ;
2368 while (time_before(jiffies, timeout)) {
2369 ret = REG_READ(REG_GLOBAL, 0x00);
2370 if ((ret & is_reset) == is_reset)
2371 break;
2372 usleep_range(1000, 2000);
2373 }
2374 if (time_after(jiffies, timeout))
2375 return -ETIMEDOUT;
2376
2377 return 0;
2378}
2379
49143585
AL		 2380int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2381{
2382 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2383 int ret;
2384
3898c148 2385 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2386 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
49143585
AL		 2387 if (ret < 0)
2388 goto error;
fd3a0ee4 2389 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
49143585 2390error:
fd3a0ee4 2391 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
3898c148 2392 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2393 return ret;
2394}
2395
2396int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2397 int reg, int val)
2398{
2399 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2400 int ret;
2401
3898c148 2402 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2403 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
49143585
AL		 2404 if (ret < 0)
2405 goto error;
2406
fd3a0ee4 2407 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
49143585 2408error:
fd3a0ee4 2409 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
3898c148 2410 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2411 return ret;
2412}
2413
2414static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2415{
2416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2417
2418 if (port >= 0 && port < ps->num_ports)
2419 return port;
2420 return -EINVAL;
2421}
2422
2423int
2424mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2425{
2426 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2427 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2428 int ret;
2429
2430 if (addr < 0)
2431 return addr;
2432
3898c148 2433 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2434 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
3898c148 2435 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2436 return ret;
2437}
2438
2439int
2440mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2441{
2442 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2443 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2444 int ret;
2445
2446 if (addr < 0)
2447 return addr;
2448
3898c148 2449 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2450 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
3898c148 2451 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2452 return ret;
2453}
2454
2455int
2456mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2457{
2458 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2459 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2460 int ret;
2461
2462 if (addr < 0)
2463 return addr;
2464
3898c148 2465 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2466 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
3898c148 2467 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2468 return ret;
2469}
2470
2471int
2472mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2473 u16 val)
2474{
2475 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2476 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2477 int ret;
2478
2479 if (addr < 0)
2480 return addr;
2481
3898c148 2482 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2483 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
3898c148 2484 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2485 return ret;
2486}
2487
c22995c5
GR		 2488#ifdef CONFIG_NET_DSA_HWMON
2489
2490static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2491{
2492 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2493 int ret;
2494 int val;
2495
2496 *temp = 0;
2497
2498 mutex_lock(&ps->smi_mutex);
2499
2500 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2501 if (ret < 0)
2502 goto error;
2503
2504 /* Enable temperature sensor */
2505 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2506 if (ret < 0)
2507 goto error;
2508
2509 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2510 if (ret < 0)
2511 goto error;
2512
2513 /* Wait for temperature to stabilize */
2514 usleep_range(10000, 12000);
2515
2516 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2517 if (val < 0) {
2518 ret = val;
2519 goto error;
2520 }
2521
2522 /* Disable temperature sensor */
2523 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2524 if (ret < 0)
2525 goto error;
2526
2527 *temp = ((val & 0x1f) - 5) * 5;
2528
2529error:
2530 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2531 mutex_unlock(&ps->smi_mutex);
2532 return ret;
2533}
2534
2535static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2536{
2537 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2538 int ret;
2539
2540 *temp = 0;
2541
2542 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2543 if (ret < 0)
2544 return ret;
2545
2546 *temp = (ret & 0xff) - 25;
2547
2548 return 0;
2549}
2550
2551int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2552{
2553 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2554 return mv88e63xx_get_temp(ds, temp);
2555
2556 return mv88e61xx_get_temp(ds, temp);
2557}
2558
2559int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2560{
2561 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2562 int ret;
2563
2564 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2565 return -EOPNOTSUPP;
2566
2567 *temp = 0;
2568
2569 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2570 if (ret < 0)
2571 return ret;
2572
2573 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2574
2575 return 0;
2576}
2577
2578int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2579{
2580 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2581 int ret;
2582
2583 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2584 return -EOPNOTSUPP;
2585
2586 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2587 if (ret < 0)
2588 return ret;
2589 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2590 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2591 (ret & 0xe0ff) | (temp << 8));
2592}
2593
2594int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2595{
2596 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2597 int ret;
2598
2599 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2600 return -EOPNOTSUPP;
2601
2602 *alarm = false;
2603
2604 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2605 if (ret < 0)
2606 return ret;
2607
2608 *alarm = !!(ret & 0x40);
2609
2610 return 0;
2611}
2612#endif /* CONFIG_NET_DSA_HWMON */
2613
b9b37713
VD		 2614char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
2615 const struct mv88e6xxx_switch_id *table,
2616 unsigned int num)
2617{
2618 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
2619 int i, ret;
2620
2621 if (!bus)
2622 return NULL;
2623
2624 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
2625 if (ret < 0)
2626 return NULL;
2627
2628 /* Look up the exact switch ID */
2629 for (i = 0; i < num; ++i)
2630 if (table[i].id == ret)
2631 return table[i].name;
2632
2633 /* Look up only the product number */
2634 for (i = 0; i < num; ++i) {
2635 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
2636 dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
2637 ret & PORT_SWITCH_ID_REV_MASK,
2638 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
2639 return table[i].name;
2640 }
2641 }
2642
2643 return NULL;
2644}
2645
98e67308
BH		 2646static int __init mv88e6xxx_init(void)
2647{
2648#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2649 register_switch_driver(&mv88e6131_switch_driver);
2650#endif
2651#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2652 register_switch_driver(&mv88e6123_61_65_switch_driver);
42f27253 2653#endif
3ad50cca
GR		 2654#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2655 register_switch_driver(&mv88e6352_switch_driver);
2656#endif
42f27253
AL		 2657#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2658 register_switch_driver(&mv88e6171_switch_driver);
98e67308
BH		 2659#endif
2660 return 0;
2661}
2662module_init(mv88e6xxx_init);
2663
2664static void __exit mv88e6xxx_cleanup(void)
2665{
42f27253
AL		 2666#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2667 unregister_switch_driver(&mv88e6171_switch_driver);
2668#endif
4212b543
VD		 2669#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2670 unregister_switch_driver(&mv88e6352_switch_driver);
2671#endif
98e67308
BH		 2672#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2673 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2674#endif
2675#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2676 unregister_switch_driver(&mv88e6131_switch_driver);
2677#endif
2678}
2679module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 2680
2681MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2682MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2683MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)