[linux-block.git] / drivers / net / dsa / mv88e6xxx / serdes.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Marvell 88E6xxx SERDES manipulation, via SMI bus
 *
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
 */

#ifndef _MV88E6XXX_SERDES_H
#define _MV88E6XXX_SERDES_H

#include "chip.h"

struct phylink_link_state;

#define MV88E6352_ADDR_SERDES		0x0f
#define MV88E6352_SERDES_PAGE_FIBER	0x01
#define MV88E6352_SERDES_IRQ		0x0b
#define MV88E6352_SERDES_INT_ENABLE	0x12
#define MV88E6352_SERDES_INT_SPEED_CHANGE	BIT(14)
#define MV88E6352_SERDES_INT_DUPLEX_CHANGE	BIT(13)
#define MV88E6352_SERDES_INT_PAGE_RX		BIT(12)
#define MV88E6352_SERDES_INT_AN_COMPLETE	BIT(11)
#define MV88E6352_SERDES_INT_LINK_CHANGE	BIT(10)
#define MV88E6352_SERDES_INT_SYMBOL_ERROR	BIT(9)
#define MV88E6352_SERDES_INT_FALSE_CARRIER	BIT(8)
#define MV88E6352_SERDES_INT_FIFO_OVER_UNDER	BIT(7)
#define MV88E6352_SERDES_INT_FIBRE_ENERGY	BIT(4)
#define MV88E6352_SERDES_INT_STATUS	0x13

#define MV88E6352_SERDES_SPEC_CTRL2	0x1a
#define MV88E6352_SERDES_OUT_AMP_MASK		0x0007

#define MV88E6341_PORT5_LANE		0x15

#define MV88E6390_PORT9_LANE0		0x09
#define MV88E6390_PORT9_LANE1		0x12
#define MV88E6390_PORT9_LANE2		0x13
#define MV88E6390_PORT9_LANE3		0x14
#define MV88E6390_PORT10_LANE0		0x0a
#define MV88E6390_PORT10_LANE1		0x15
#define MV88E6390_PORT10_LANE2		0x16
#define MV88E6390_PORT10_LANE3		0x17

/* 10GBASE-R and 10GBASE-X4/X2 */
#define MV88E6390_10G_CTRL1		(0x1000 + MDIO_CTRL1)
#define MV88E6390_10G_STAT1		(0x1000 + MDIO_STAT1)
#define MV88E6390_10G_INT_ENABLE	0x9001
#define MV88E6390_10G_INT_LINK_DOWN	BIT(3)
#define MV88E6390_10G_INT_LINK_UP	BIT(2)
#define MV88E6390_10G_INT_STATUS	0x9003
#define MV88E6393X_10G_INT_ENABLE	0x9000
#define MV88E6393X_10G_INT_LINK_CHANGE	BIT(2)
#define MV88E6393X_10G_INT_STATUS	0x9001

/* USXGMII */
#define MV88E6390_USXGMII_LP_STATUS       0xf0a2
#define MV88E6390_USXGMII_PHY_STATUS      0xf0a6

/* 1000BASE-X and SGMII */
#define MV88E6390_SGMII_BMCR		(0x2000 + MII_BMCR)
#define MV88E6390_SGMII_BMSR		(0x2000 + MII_BMSR)
#define MV88E6390_SGMII_ADVERTISE	(0x2000 + MII_ADVERTISE)
#define MV88E6390_SGMII_LPA		(0x2000 + MII_LPA)
#define MV88E6390_SGMII_INT_ENABLE	0xa001
#define MV88E6390_SGMII_INT_SPEED_CHANGE	BIT(14)
#define MV88E6390_SGMII_INT_DUPLEX_CHANGE	BIT(13)
#define MV88E6390_SGMII_INT_PAGE_RX		BIT(12)
#define MV88E6390_SGMII_INT_AN_COMPLETE		BIT(11)
#define MV88E6390_SGMII_INT_LINK_DOWN		BIT(10)
#define MV88E6390_SGMII_INT_LINK_UP		BIT(9)
#define MV88E6390_SGMII_INT_SYMBOL_ERROR	BIT(8)
#define MV88E6390_SGMII_INT_FALSE_CARRIER	BIT(7)
#define MV88E6390_SGMII_INT_STATUS	0xa002
#define MV88E6390_SGMII_PHY_STATUS	0xa003
#define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK	GENMASK(15, 14)
#define MV88E6390_SGMII_PHY_STATUS_SPEED_1000	0x8000
#define MV88E6390_SGMII_PHY_STATUS_SPEED_100	0x4000
#define MV88E6390_SGMII_PHY_STATUS_SPEED_10	0x0000
#define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL	BIT(13)
#define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
#define MV88E6390_SGMII_PHY_STATUS_LINK		BIT(10)
#define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE	BIT(3)
#define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE	BIT(2)

/* Packet generator pad packet checker */
#define MV88E6390_PG_CONTROL		0xf010
#define MV88E6390_PG_CONTROL_ENABLE_PC		BIT(0)

#define MV88E6393X_PORT0_LANE			0x00
#define MV88E6393X_PORT9_LANE			0x09
#define MV88E6393X_PORT10_LANE			0x0a

/* Port Operational Configuration */
#define MV88E6393X_SERDES_POC			0xf002
#define MV88E6393X_SERDES_POC_PCS_1000BASEX	0x0000
#define MV88E6393X_SERDES_POC_PCS_2500BASEX	0x0001
#define MV88E6393X_SERDES_POC_PCS_SGMII_PHY	0x0002
#define MV88E6393X_SERDES_POC_PCS_SGMII_MAC	0x0003
#define MV88E6393X_SERDES_POC_PCS_5GBASER	0x0004
#define MV88E6393X_SERDES_POC_PCS_10GBASER	0x0005
#define MV88E6393X_SERDES_POC_PCS_USXGMII_PHY	0x0006
#define MV88E6393X_SERDES_POC_PCS_USXGMII_MAC	0x0007
#define MV88E6393X_SERDES_POC_PCS_MASK		0x0007
#define MV88E6393X_SERDES_POC_RESET		BIT(15)
#define MV88E6393X_SERDES_POC_PDOWN		BIT(5)
#define MV88E6393X_SERDES_POC_AN		BIT(3)
#define MV88E6393X_SERDES_CTRL1			0xf003
#define MV88E6393X_SERDES_CTRL1_TX_PDOWN	BIT(9)
#define MV88E6393X_SERDES_CTRL1_RX_PDOWN	BIT(8)

#define MV88E6393X_ERRATA_4_8_REG		0xF074
#define MV88E6393X_ERRATA_4_8_BIT		BIT(14)

int mv88e6xxx_pcs_decode_state(struct device *dev, u16 bmsr, u16 lpa,
			       u16 status, struct phylink_link_state *state);

int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
					  int port);
unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
					  int port);
int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
				 int port, uint8_t *data);
size_t mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
				  uint64_t *data);
int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
				 int port, uint8_t *data);
size_t mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
				  uint64_t *data);

int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);

int mv88e6352_serdes_set_tx_amplitude(struct mv88e6xxx_chip *chip, int port,
				      int val);

/* Return the (first) SERDES lane address a port is using, -errno otherwise. */
static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
					    int port)
{
	if (!chip->info->ops->serdes_get_lane)
		return -EOPNOTSUPP;

	return chip->info->ops->serdes_get_lane(chip, port);
}

static inline unsigned int
mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
{
	if (!chip->info->ops->serdes_irq_mapping)
		return 0;

	return chip->info->ops->serdes_irq_mapping(chip, port);
}

extern const struct mv88e6xxx_pcs_ops mv88e6185_pcs_ops;
extern const struct mv88e6xxx_pcs_ops mv88e6352_pcs_ops;
extern const struct mv88e6xxx_pcs_ops mv88e6390_pcs_ops;
extern const struct mv88e6xxx_pcs_ops mv88e6393x_pcs_ops;

#endif
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
6d91782f AL	2	/*
	3	* Marvell 88E6xxx SERDES manipulation, via SMI bus
	4	*
	5	* Copyright (c) 2008 Marvell Semiconductor
	6	*
	7	* Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
6d91782f AL	8	*/
	9
	10	#ifndef _MV88E6XXX_SERDES_H
	11	#define _MV88E6XXX_SERDES_H
	12
4d5f2ba7	13	#include "chip.h"
6d91782f	14
05407b0e RKO	15	struct phylink_link_state;
05407b0e RKO	16
6d91782f AL	17	#define MV88E6352_ADDR_SERDES 0x0f
6d91782f AL	18	#define MV88E6352_SERDES_PAGE_FIBER 0x01
4382172f AL	19	#define MV88E6352_SERDES_IRQ 0x0b
	20	#define MV88E6352_SERDES_INT_ENABLE 0x12
	21	#define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14)
	22	#define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13)
	23	#define MV88E6352_SERDES_INT_PAGE_RX BIT(12)
	24	#define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11)
	25	#define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10)
	26	#define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9)
	27	#define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8)
	28	#define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7)
	29	#define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4)
	30	#define MV88E6352_SERDES_INT_STATUS 0x13
	31
926eae60 HB	32	#define MV88E6352_SERDES_SPEC_CTRL2 0x1a
926eae60 HB	33	#define MV88E6352_SERDES_OUT_AMP_MASK 0x0007
6d91782f	34
d3cf7d8f	35	#define MV88E6341_PORT5_LANE 0x15
5bafeb6e	36
6335e9f2 AL	37	#define MV88E6390_PORT9_LANE0 0x09
	38	#define MV88E6390_PORT9_LANE1 0x12
	39	#define MV88E6390_PORT9_LANE2 0x13
	40	#define MV88E6390_PORT9_LANE3 0x14
	41	#define MV88E6390_PORT10_LANE0 0x0a
	42	#define MV88E6390_PORT10_LANE1 0x15
	43	#define MV88E6390_PORT10_LANE2 0x16
	44	#define MV88E6390_PORT10_LANE3 0x17
6335e9f2 AL	45
6335e9f2 AL	46	/* 10GBASE-R and 10GBASE-X4/X2 */
bf604bc9	47	#define MV88E6390_10G_CTRL1 (0x1000 + MDIO_CTRL1)
7019bba4	48	#define MV88E6390_10G_STAT1 (0x1000 + MDIO_STAT1)
e5b732a2 RKO	49	#define MV88E6390_10G_INT_ENABLE 0x9001
	50	#define MV88E6390_10G_INT_LINK_DOWN BIT(3)
	51	#define MV88E6390_10G_INT_LINK_UP BIT(2)
	52	#define MV88E6390_10G_INT_STATUS 0x9003
de776d0d PS	53	#define MV88E6393X_10G_INT_ENABLE 0x9000
	54	#define MV88E6393X_10G_INT_LINK_CHANGE BIT(2)
	55	#define MV88E6393X_10G_INT_STATUS 0x9001
6335e9f2	56
4a562127 MS	57	/* USXGMII */
	58	#define MV88E6390_USXGMII_LP_STATUS 0xf0a2
	59	#define MV88E6390_USXGMII_PHY_STATUS 0xf0a6
	60
6335e9f2	61	/* 1000BASE-X and SGMII */
4c8b7350	62	#define MV88E6390_SGMII_BMCR (0x2000 + MII_BMCR)
7e0e6243	63	#define MV88E6390_SGMII_BMSR (0x2000 + MII_BMSR)
a5a6858b RK	64	#define MV88E6390_SGMII_ADVERTISE (0x2000 + MII_ADVERTISE)
a5a6858b RK	65	#define MV88E6390_SGMII_LPA (0x2000 + MII_LPA)
efd1ba6a AL	66	#define MV88E6390_SGMII_INT_ENABLE 0xa001
	67	#define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14)
	68	#define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13)
	69	#define MV88E6390_SGMII_INT_PAGE_RX BIT(12)
	70	#define MV88E6390_SGMII_INT_AN_COMPLETE BIT(11)
	71	#define MV88E6390_SGMII_INT_LINK_DOWN BIT(10)
	72	#define MV88E6390_SGMII_INT_LINK_UP BIT(9)
	73	#define MV88E6390_SGMII_INT_SYMBOL_ERROR BIT(8)
	74	#define MV88E6390_SGMII_INT_FALSE_CARRIER BIT(7)
	75	#define MV88E6390_SGMII_INT_STATUS 0xa002
72d8b4fd HK	76	#define MV88E6390_SGMII_PHY_STATUS 0xa003
	77	#define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK GENMASK(15, 14)
	78	#define MV88E6390_SGMII_PHY_STATUS_SPEED_1000 0x8000
	79	#define MV88E6390_SGMII_PHY_STATUS_SPEED_100 0x4000
	80	#define MV88E6390_SGMII_PHY_STATUS_SPEED_10 0x0000
	81	#define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL BIT(13)
	82	#define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
	83	#define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10)
a5a6858b RK	84	#define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE BIT(3)
a5a6858b RK	85	#define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2)
6335e9f2	86
0df95287 NY	87	/* Packet generator pad packet checker */
	88	#define MV88E6390_PG_CONTROL 0xf010
	89	#define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0)
	90
de776d0d PS	91	#define MV88E6393X_PORT0_LANE 0x00
	92	#define MV88E6393X_PORT9_LANE 0x09
	93	#define MV88E6393X_PORT10_LANE 0x0a
	94
	95	/* Port Operational Configuration */
	96	#define MV88E6393X_SERDES_POC 0xf002
	97	#define MV88E6393X_SERDES_POC_PCS_1000BASEX 0x0000
	98	#define MV88E6393X_SERDES_POC_PCS_2500BASEX 0x0001
	99	#define MV88E6393X_SERDES_POC_PCS_SGMII_PHY 0x0002
	100	#define MV88E6393X_SERDES_POC_PCS_SGMII_MAC 0x0003
	101	#define MV88E6393X_SERDES_POC_PCS_5GBASER 0x0004
	102	#define MV88E6393X_SERDES_POC_PCS_10GBASER 0x0005
	103	#define MV88E6393X_SERDES_POC_PCS_USXGMII_PHY 0x0006
	104	#define MV88E6393X_SERDES_POC_PCS_USXGMII_MAC 0x0007
	105	#define MV88E6393X_SERDES_POC_PCS_MASK 0x0007
	106	#define MV88E6393X_SERDES_POC_RESET BIT(15)
	107	#define MV88E6393X_SERDES_POC_PDOWN BIT(5)
163000db	108	#define MV88E6393X_SERDES_POC_AN BIT(3)
7527d662 MB	109	#define MV88E6393X_SERDES_CTRL1 0xf003
	110	#define MV88E6393X_SERDES_CTRL1_TX_PDOWN BIT(9)
	111	#define MV88E6393X_SERDES_CTRL1_RX_PDOWN BIT(8)
de776d0d PS	112
	113	#define MV88E6393X_ERRATA_4_8_REG 0xF074
	114	#define MV88E6393X_ERRATA_4_8_BIT BIT(14)
	115
05407b0e RKO	116	int mv88e6xxx_pcs_decode_state(struct device *dev, u16 bmsr, u16 lpa,
	117	u16 status, struct phylink_link_state *state);
	118
193c5b26	119	int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
193c5b26 PS	120	int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
193c5b26 PS	121	int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
de776d0d	122	int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
4241ef52 VD	123	unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
	124	int port);
	125	unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
	126	int port);
cda9f4aa	127	int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
65f60e45 AL	128	int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
65f60e45 AL	129	int port, uint8_t *data);
fc82a08a TW	130	size_t mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
fc82a08a TW	131	uint64_t *data);
0df95287 NY	132	int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
	133	int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
	134	int port, uint8_t *data);
fc82a08a TW	135	size_t mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
fc82a08a TW	136	uint64_t *data);
4382172f	137
d3f88a24 AL	138	int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
d3f88a24 AL	139	void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip chip, int port, void _p);
bf3504ce AL	140	int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
bf3504ce AL	141	void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip chip, int port, void _p);
d3f88a24	142
926eae60 HB	143	int mv88e6352_serdes_set_tx_amplitude(struct mv88e6xxx_chip *chip, int port,
	144	int val);
	145
193c5b26 PS	146	/* Return the (first) SERDES lane address a port is using, -errno otherwise. */
	147	static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
	148	int port)
5122d4ec VD	149	{
5122d4ec VD	150	if (!chip->info->ops->serdes_get_lane)
193c5b26	151	return -EOPNOTSUPP;
5122d4ec VD	152
	153	return chip->info->ops->serdes_get_lane(chip, port);
	154	}
	155
4241ef52 VD	156	static inline unsigned int
	157	mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
	158	{
	159	if (!chip->info->ops->serdes_irq_mapping)
	160	return 0;
	161
	162	return chip->info->ops->serdes_irq_mapping(chip, port);
	163	}
734447d4	164
4aabe35c	165	extern const struct mv88e6xxx_pcs_ops mv88e6185_pcs_ops;
85764555	166	extern const struct mv88e6xxx_pcs_ops mv88e6352_pcs_ops;
e5b732a2 RKO	167	extern const struct mv88e6xxx_pcs_ops mv88e6390_pcs_ops;
e5b732a2 RKO	168	extern const struct mv88e6xxx_pcs_ops mv88e6393x_pcs_ops;
4aabe35c	169
6d91782f	170	#endif