[linux-2.6-block.git] / drivers / net / dsa / mv88e6xxx / ptp.c

/*
 * Marvell 88E6xxx Switch PTP support
 *
 * Copyright (c) 2008 Marvell Semiconductor
 *
 * Copyright (c) 2017 National Instruments
 *      Erik Hons <erik.hons@ni.com>
 *      Brandon Streiff <brandon.streiff@ni.com>
 *      Dane Wagner <dane.wagner@ni.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include "chip.h"
#include "global2.h"
#include "hwtstamp.h"
#include "ptp.h"

/* Raw timestamps are in units of 8-ns clock periods. */
#define CC_SHIFT	28
#define CC_MULT		(8 << CC_SHIFT)
#define CC_MULT_NUM	(1 << 9)
#define CC_MULT_DEM	15625ULL

#define TAI_EVENT_WORK_INTERVAL msecs_to_jiffies(100)

#define cc_to_chip(cc) container_of(cc, struct mv88e6xxx_chip, tstamp_cc)
#define dw_overflow_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
					     overflow_work)
#define dw_tai_event_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
					      tai_event_work)

static int mv88e6xxx_tai_read(struct mv88e6xxx_chip *chip, int addr,
			      u16 *data, int len)
{
	if (!chip->info->ops->avb_ops->tai_read)
		return -EOPNOTSUPP;

	return chip->info->ops->avb_ops->tai_read(chip, addr, data, len);
}

static int mv88e6xxx_tai_write(struct mv88e6xxx_chip *chip, int addr, u16 data)
{
	if (!chip->info->ops->avb_ops->tai_write)
		return -EOPNOTSUPP;

	return chip->info->ops->avb_ops->tai_write(chip, addr, data);
}

/* TODO: places where this are called should be using pinctrl */
static int mv88e6352_set_gpio_func(struct mv88e6xxx_chip *chip, int pin,
				   int func, int input)
{
	int err;

	if (!chip->info->ops->gpio_ops)
		return -EOPNOTSUPP;

	err = chip->info->ops->gpio_ops->set_dir(chip, pin, input);
	if (err)
		return err;

	return chip->info->ops->gpio_ops->set_pctl(chip, pin, func);
}

static u64 mv88e6352_ptp_clock_read(const struct cyclecounter *cc)
{
	struct mv88e6xxx_chip *chip = cc_to_chip(cc);
	u16 phc_time[2];
	int err;

	err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_TIME_LO, phc_time,
				 ARRAY_SIZE(phc_time));
	if (err)
		return 0;
	else
		return ((u32)phc_time[1] << 16) | phc_time[0];
}

static u64 mv88e6165_ptp_clock_read(const struct cyclecounter *cc)
{
	struct mv88e6xxx_chip *chip = cc_to_chip(cc);
	u16 phc_time[2];
	int err;

	err = mv88e6xxx_tai_read(chip, MV88E6XXX_PTP_GC_TIME_LO, phc_time,
				 ARRAY_SIZE(phc_time));
	if (err)
		return 0;
	else
		return ((u32)phc_time[1] << 16) | phc_time[0];
}

/* mv88e6352_config_eventcap - configure TAI event capture
 * @event: PTP_CLOCK_PPS (internal) or PTP_CLOCK_EXTTS (external)
 * @rising: zero for falling-edge trigger, else rising-edge trigger
 *
 * This will also reset the capture sequence counter.
 */
static int mv88e6352_config_eventcap(struct mv88e6xxx_chip *chip, int event,
				     int rising)
{
	u16 global_config;
	u16 cap_config;
	int err;

	chip->evcap_config = MV88E6XXX_TAI_CFG_CAP_OVERWRITE |
			     MV88E6XXX_TAI_CFG_CAP_CTR_START;
	if (!rising)
		chip->evcap_config |= MV88E6XXX_TAI_CFG_EVREQ_FALLING;

	global_config = (chip->evcap_config | chip->trig_config);
	err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_CFG, global_config);
	if (err)
		return err;

	if (event == PTP_CLOCK_PPS) {
		cap_config = MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG;
	} else if (event == PTP_CLOCK_EXTTS) {
		/* if STATUS_CAP_TRIG is unset we capture PTP_EVREQ events */
		cap_config = 0;
	} else {
		return -EINVAL;
	}

	/* Write the capture config; this also clears the capture counter */
	err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS,
				  cap_config);

	return err;
}

static void mv88e6352_tai_event_work(struct work_struct *ugly)
{
	struct delayed_work *dw = to_delayed_work(ugly);
	struct mv88e6xxx_chip *chip = dw_tai_event_to_chip(dw);
	struct ptp_clock_event ev;
	u16 status[4];
	u32 raw_ts;
	int err;

	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_EVENT_STATUS,
				 status, ARRAY_SIZE(status));
	mutex_unlock(&chip->reg_lock);

	if (err) {
		dev_err(chip->dev, "failed to read TAI status register\n");
		return;
	}
	if (status[0] & MV88E6XXX_TAI_EVENT_STATUS_ERROR) {
		dev_warn(chip->dev, "missed event capture\n");
		return;
	}
	if (!(status[0] & MV88E6XXX_TAI_EVENT_STATUS_VALID))
		goto out;

	raw_ts = ((u32)status[2] << 16) | status[1];

	/* Clear the valid bit so the next timestamp can come in */
	status[0] &= ~MV88E6XXX_TAI_EVENT_STATUS_VALID;
	mutex_lock(&chip->reg_lock);
	err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, status[0]);
	mutex_unlock(&chip->reg_lock);

	/* This is an external timestamp */
	ev.type = PTP_CLOCK_EXTTS;

	/* We only have one timestamping channel. */
	ev.index = 0;
	mutex_lock(&chip->reg_lock);
	ev.timestamp = timecounter_cyc2time(&chip->tstamp_tc, raw_ts);
	mutex_unlock(&chip->reg_lock);

	ptp_clock_event(chip->ptp_clock, &ev);
out:
	schedule_delayed_work(&chip->tai_event_work, TAI_EVENT_WORK_INTERVAL);
}

static int mv88e6xxx_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
{
	struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
	int neg_adj = 0;
	u32 diff, mult;
	u64 adj;

	if (scaled_ppm < 0) {
		neg_adj = 1;
		scaled_ppm = -scaled_ppm;
	}
	mult = CC_MULT;
	adj = CC_MULT_NUM;
	adj *= scaled_ppm;
	diff = div_u64(adj, CC_MULT_DEM);

	mutex_lock(&chip->reg_lock);

	timecounter_read(&chip->tstamp_tc);
	chip->tstamp_cc.mult = neg_adj ? mult - diff : mult + diff;

	mutex_unlock(&chip->reg_lock);

	return 0;
}

static int mv88e6xxx_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
	struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);

	mutex_lock(&chip->reg_lock);
	timecounter_adjtime(&chip->tstamp_tc, delta);
	mutex_unlock(&chip->reg_lock);

	return 0;
}

static int mv88e6xxx_ptp_gettime(struct ptp_clock_info *ptp,
				 struct timespec64 *ts)
{
	struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
	u64 ns;

	mutex_lock(&chip->reg_lock);
	ns = timecounter_read(&chip->tstamp_tc);
	mutex_unlock(&chip->reg_lock);

	*ts = ns_to_timespec64(ns);

	return 0;
}

static int mv88e6xxx_ptp_settime(struct ptp_clock_info *ptp,
				 const struct timespec64 *ts)
{
	struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
	u64 ns;

	ns = timespec64_to_ns(ts);

	mutex_lock(&chip->reg_lock);
	timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, ns);
	mutex_unlock(&chip->reg_lock);

	return 0;
}

static int mv88e6352_ptp_enable_extts(struct mv88e6xxx_chip *chip,
				      struct ptp_clock_request *rq, int on)
{
	int rising = (rq->extts.flags & PTP_RISING_EDGE);
	int func;
	int pin;
	int err;

	pin = ptp_find_pin(chip->ptp_clock, PTP_PF_EXTTS, rq->extts.index);

	if (pin < 0)
		return -EBUSY;

	mutex_lock(&chip->reg_lock);

	if (on) {
		func = MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ;

		err = mv88e6352_set_gpio_func(chip, pin, func, true);
		if (err)
			goto out;

		schedule_delayed_work(&chip->tai_event_work,
				      TAI_EVENT_WORK_INTERVAL);

		err = mv88e6352_config_eventcap(chip, PTP_CLOCK_EXTTS, rising);
	} else {
		func = MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO;

		err = mv88e6352_set_gpio_func(chip, pin, func, true);

		cancel_delayed_work_sync(&chip->tai_event_work);
	}

out:
	mutex_unlock(&chip->reg_lock);

	return err;
}

static int mv88e6352_ptp_enable(struct ptp_clock_info *ptp,
				struct ptp_clock_request *rq, int on)
{
	struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);

	switch (rq->type) {
	case PTP_CLK_REQ_EXTTS:
		return mv88e6352_ptp_enable_extts(chip, rq, on);
	default:
		return -EOPNOTSUPP;
	}
}

static int mv88e6352_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
				enum ptp_pin_function func, unsigned int chan)
{
	switch (func) {
	case PTP_PF_NONE:
	case PTP_PF_EXTTS:
		break;
	case PTP_PF_PEROUT:
	case PTP_PF_PHYSYNC:
		return -EOPNOTSUPP;
	}
	return 0;
}

const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {
	.clock_read = mv88e6352_ptp_clock_read,
	.ptp_enable = mv88e6352_ptp_enable,
	.ptp_verify = mv88e6352_ptp_verify,
	.event_work = mv88e6352_tai_event_work,
	.port_enable = mv88e6352_hwtstamp_port_enable,
	.port_disable = mv88e6352_hwtstamp_port_disable,
	.n_ext_ts = 1,
	.arr0_sts_reg = MV88E6XXX_PORT_PTP_ARR0_STS,
	.arr1_sts_reg = MV88E6XXX_PORT_PTP_ARR1_STS,
	.dep_sts_reg = MV88E6XXX_PORT_PTP_DEP_STS,
	.rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
		(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
		(1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
		(1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
		(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
		(1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
		(1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
		(1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
		(1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
		(1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
};

const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {
	.clock_read = mv88e6165_ptp_clock_read,
	.global_enable = mv88e6165_global_enable,
	.global_disable = mv88e6165_global_disable,
	.arr0_sts_reg = MV88E6165_PORT_PTP_ARR0_STS,
	.arr1_sts_reg = MV88E6165_PORT_PTP_ARR1_STS,
	.dep_sts_reg = MV88E6165_PORT_PTP_DEP_STS,
	.rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
		(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
		(1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
		(1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
		(1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
		(1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
		(1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
};

static u64 mv88e6xxx_ptp_clock_read(const struct cyclecounter *cc)
{
	struct mv88e6xxx_chip *chip = cc_to_chip(cc);

	if (chip->info->ops->ptp_ops->clock_read)
		return chip->info->ops->ptp_ops->clock_read(cc);

	return 0;
}

/* With a 125MHz input clock, the 32-bit timestamp counter overflows in ~34.3
 * seconds; this task forces periodic reads so that we don't miss any.
 */
#define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 16)
static void mv88e6xxx_ptp_overflow_check(struct work_struct *work)
{
	struct delayed_work *dw = to_delayed_work(work);
	struct mv88e6xxx_chip *chip = dw_overflow_to_chip(dw);
	struct timespec64 ts;

	mv88e6xxx_ptp_gettime(&chip->ptp_clock_info, &ts);

	schedule_delayed_work(&chip->overflow_work,
			      MV88E6XXX_TAI_OVERFLOW_PERIOD);
}

int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip)
{
	const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
	int i;

	/* Set up the cycle counter */
	memset(&chip->tstamp_cc, 0, sizeof(chip->tstamp_cc));
	chip->tstamp_cc.read	= mv88e6xxx_ptp_clock_read;
	chip->tstamp_cc.mask	= CYCLECOUNTER_MASK(32);
	chip->tstamp_cc.mult	= CC_MULT;
	chip->tstamp_cc.shift	= CC_SHIFT;

	timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc,
			 ktime_to_ns(ktime_get_real()));

	INIT_DELAYED_WORK(&chip->overflow_work, mv88e6xxx_ptp_overflow_check);
	if (ptp_ops->event_work)
		INIT_DELAYED_WORK(&chip->tai_event_work, ptp_ops->event_work);

	chip->ptp_clock_info.owner = THIS_MODULE;
	snprintf(chip->ptp_clock_info.name, sizeof(chip->ptp_clock_info.name),
		 dev_name(chip->dev));
	chip->ptp_clock_info.max_adj	= 1000000;

	chip->ptp_clock_info.n_ext_ts	= ptp_ops->n_ext_ts;
	chip->ptp_clock_info.n_per_out	= 0;
	chip->ptp_clock_info.n_pins	= mv88e6xxx_num_gpio(chip);
	chip->ptp_clock_info.pps	= 0;

	for (i = 0; i < chip->ptp_clock_info.n_pins; ++i) {
		struct ptp_pin_desc *ppd = &chip->pin_config[i];

		snprintf(ppd->name, sizeof(ppd->name), "mv88e6xxx_gpio%d", i);
		ppd->index = i;
		ppd->func = PTP_PF_NONE;
	}
	chip->ptp_clock_info.pin_config = chip->pin_config;

	chip->ptp_clock_info.adjfine	= mv88e6xxx_ptp_adjfine;
	chip->ptp_clock_info.adjtime	= mv88e6xxx_ptp_adjtime;
	chip->ptp_clock_info.gettime64	= mv88e6xxx_ptp_gettime;
	chip->ptp_clock_info.settime64	= mv88e6xxx_ptp_settime;
	chip->ptp_clock_info.enable	= ptp_ops->ptp_enable;
	chip->ptp_clock_info.verify	= ptp_ops->ptp_verify;
	chip->ptp_clock_info.do_aux_work = mv88e6xxx_hwtstamp_work;

	chip->ptp_clock = ptp_clock_register(&chip->ptp_clock_info, chip->dev);
	if (IS_ERR(chip->ptp_clock))
		return PTR_ERR(chip->ptp_clock);

	schedule_delayed_work(&chip->overflow_work,
			      MV88E6XXX_TAI_OVERFLOW_PERIOD);

	return 0;
}

void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip)
{
	if (chip->ptp_clock) {
		cancel_delayed_work_sync(&chip->overflow_work);
		if (chip->info->ops->ptp_ops->event_work)
			cancel_delayed_work_sync(&chip->tai_event_work);

		ptp_clock_unregister(chip->ptp_clock);
		chip->ptp_clock = NULL;
	}
}
Commit	Line	Data
2fa8d3af BS	1	/*
	2	* Marvell 88E6xxx Switch PTP support
	3	*
	4	* Copyright (c) 2008 Marvell Semiconductor
	5	*
	6	* Copyright (c) 2017 National Instruments
	7	* Erik Hons <erik.hons@ni.com>
	8	* Brandon Streiff <brandon.streiff@ni.com>
	9	* Dane Wagner <dane.wagner@ni.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#include "chip.h"
	18	#include "global2.h"
ffc705de	19	#include "hwtstamp.h"
2fa8d3af BS	20	#include "ptp.h"
	21
	22	/* Raw timestamps are in units of 8-ns clock periods. */
	23	#define CC_SHIFT 28
	24	#define CC_MULT (8 << CC_SHIFT)
	25	#define CC_MULT_NUM (1 << 9)
	26	#define CC_MULT_DEM 15625ULL
	27
	28	#define TAI_EVENT_WORK_INTERVAL msecs_to_jiffies(100)
	29
	30	#define cc_to_chip(cc) container_of(cc, struct mv88e6xxx_chip, tstamp_cc)
2fa8d3af BS	31	#define dw_overflow_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
2fa8d3af BS	32	overflow_work)
4eb3be29 BS	33	#define dw_tai_event_to_chip(dw) container_of(dw, struct mv88e6xxx_chip, \
4eb3be29 BS	34	tai_event_work)
2fa8d3af BS	35
	36	static int mv88e6xxx_tai_read(struct mv88e6xxx_chip *chip, int addr,
	37	u16 *data, int len)
	38	{
	39	if (!chip->info->ops->avb_ops->tai_read)
	40	return -EOPNOTSUPP;
	41
	42	return chip->info->ops->avb_ops->tai_read(chip, addr, data, len);
	43	}
	44
4eb3be29 BS	45	static int mv88e6xxx_tai_write(struct mv88e6xxx_chip *chip, int addr, u16 data)
	46	{
	47	if (!chip->info->ops->avb_ops->tai_write)
	48	return -EOPNOTSUPP;
	49
	50	return chip->info->ops->avb_ops->tai_write(chip, addr, data);
	51	}
	52
	53	/* TODO: places where this are called should be using pinctrl */
6d2ac8ee	54	static int mv88e6352_set_gpio_func(struct mv88e6xxx_chip *chip, int pin,
4eb3be29 BS	55	int func, int input)
	56	{
	57	int err;
	58
	59	if (!chip->info->ops->gpio_ops)
	60	return -EOPNOTSUPP;
	61
	62	err = chip->info->ops->gpio_ops->set_dir(chip, pin, input);
	63	if (err)
	64	return err;
	65
	66	return chip->info->ops->gpio_ops->set_pctl(chip, pin, func);
	67	}
	68
6d2ac8ee	69	static u64 mv88e6352_ptp_clock_read(const struct cyclecounter *cc)
2fa8d3af BS	70	{
	71	struct mv88e6xxx_chip *chip = cc_to_chip(cc);
	72	u16 phc_time[2];
	73	int err;
	74
	75	err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_TIME_LO, phc_time,
	76	ARRAY_SIZE(phc_time));
	77	if (err)
	78	return 0;
	79	else
	80	return ((u32)phc_time[1] << 16) \| phc_time[0];
	81	}
	82
dfa54348 AL	83	static u64 mv88e6165_ptp_clock_read(const struct cyclecounter *cc)
	84	{
	85	struct mv88e6xxx_chip *chip = cc_to_chip(cc);
	86	u16 phc_time[2];
	87	int err;
	88
	89	err = mv88e6xxx_tai_read(chip, MV88E6XXX_PTP_GC_TIME_LO, phc_time,
	90	ARRAY_SIZE(phc_time));
	91	if (err)
	92	return 0;
	93	else
	94	return ((u32)phc_time[1] << 16) \| phc_time[0];
	95	}
	96
6d2ac8ee	97	/* mv88e6352_config_eventcap - configure TAI event capture
4eb3be29 BS	98	* @event: PTP_CLOCK_PPS (internal) or PTP_CLOCK_EXTTS (external)
	99	* @rising: zero for falling-edge trigger, else rising-edge trigger
	100	*
	101	* This will also reset the capture sequence counter.
	102	*/
6d2ac8ee	103	static int mv88e6352_config_eventcap(struct mv88e6xxx_chip *chip, int event,
4eb3be29 BS	104	int rising)
	105	{
	106	u16 global_config;
	107	u16 cap_config;
	108	int err;
	109
	110	chip->evcap_config = MV88E6XXX_TAI_CFG_CAP_OVERWRITE \|
	111	MV88E6XXX_TAI_CFG_CAP_CTR_START;
	112	if (!rising)
	113	chip->evcap_config \|= MV88E6XXX_TAI_CFG_EVREQ_FALLING;
	114
	115	global_config = (chip->evcap_config \| chip->trig_config);
	116	err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_CFG, global_config);
	117	if (err)
	118	return err;
	119
	120	if (event == PTP_CLOCK_PPS) {
	121	cap_config = MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG;
	122	} else if (event == PTP_CLOCK_EXTTS) {
	123	/* if STATUS_CAP_TRIG is unset we capture PTP_EVREQ events */
	124	cap_config = 0;
	125	} else {
	126	return -EINVAL;
	127	}
	128
	129	/* Write the capture config; this also clears the capture counter */
	130	err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS,
	131	cap_config);
	132
	133	return err;
	134	}
	135
6d2ac8ee	136	static void mv88e6352_tai_event_work(struct work_struct *ugly)
4eb3be29 BS	137	{
	138	struct delayed_work *dw = to_delayed_work(ugly);
	139	struct mv88e6xxx_chip *chip = dw_tai_event_to_chip(dw);
	140	struct ptp_clock_event ev;
	141	u16 status[4];
	142	u32 raw_ts;
	143	int err;
	144
	145	mutex_lock(&chip->reg_lock);
	146	err = mv88e6xxx_tai_read(chip, MV88E6XXX_TAI_EVENT_STATUS,
	147	status, ARRAY_SIZE(status));
	148	mutex_unlock(&chip->reg_lock);
	149
	150	if (err) {
	151	dev_err(chip->dev, "failed to read TAI status register\n");
	152	return;
	153	}
	154	if (status[0] & MV88E6XXX_TAI_EVENT_STATUS_ERROR) {
	155	dev_warn(chip->dev, "missed event capture\n");
	156	return;
	157	}
	158	if (!(status[0] & MV88E6XXX_TAI_EVENT_STATUS_VALID))
	159	goto out;
	160
	161	raw_ts = ((u32)status[2] << 16) \| status[1];
	162
	163	/* Clear the valid bit so the next timestamp can come in */
	164	status[0] &= ~MV88E6XXX_TAI_EVENT_STATUS_VALID;
	165	mutex_lock(&chip->reg_lock);
	166	err = mv88e6xxx_tai_write(chip, MV88E6XXX_TAI_EVENT_STATUS, status[0]);
	167	mutex_unlock(&chip->reg_lock);
	168
	169	/* This is an external timestamp */
	170	ev.type = PTP_CLOCK_EXTTS;
	171
	172	/* We only have one timestamping channel. */
	173	ev.index = 0;
	174	mutex_lock(&chip->reg_lock);
	175	ev.timestamp = timecounter_cyc2time(&chip->tstamp_tc, raw_ts);
	176	mutex_unlock(&chip->reg_lock);
	177
	178	ptp_clock_event(chip->ptp_clock, &ev);
	179	out:
	180	schedule_delayed_work(&chip->tai_event_work, TAI_EVENT_WORK_INTERVAL);
	181	}
	182
2fa8d3af BS	183	static int mv88e6xxx_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
	184	{
	185	struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
	186	int neg_adj = 0;
	187	u32 diff, mult;
	188	u64 adj;
	189
	190	if (scaled_ppm < 0) {
	191	neg_adj = 1;
	192	scaled_ppm = -scaled_ppm;
	193	}
	194	mult = CC_MULT;
	195	adj = CC_MULT_NUM;
	196	adj *= scaled_ppm;
	197	diff = div_u64(adj, CC_MULT_DEM);
	198
	199	mutex_lock(&chip->reg_lock);
	200
	201	timecounter_read(&chip->tstamp_tc);
	202	chip->tstamp_cc.mult = neg_adj ? mult - diff : mult + diff;
	203
	204	mutex_unlock(&chip->reg_lock);
	205
	206	return 0;
	207	}
	208
	209	static int mv88e6xxx_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
	210	{
	211	struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
	212
	213	mutex_lock(&chip->reg_lock);
	214	timecounter_adjtime(&chip->tstamp_tc, delta);
	215	mutex_unlock(&chip->reg_lock);
	216
	217	return 0;
	218	}
	219
	220	static int mv88e6xxx_ptp_gettime(struct ptp_clock_info *ptp,
	221	struct timespec64 *ts)
	222	{
	223	struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
	224	u64 ns;
	225
	226	mutex_lock(&chip->reg_lock);
	227	ns = timecounter_read(&chip->tstamp_tc);
	228	mutex_unlock(&chip->reg_lock);
	229
	230	*ts = ns_to_timespec64(ns);
	231
	232	return 0;
	233	}
	234
	235	static int mv88e6xxx_ptp_settime(struct ptp_clock_info *ptp,
	236	const struct timespec64 *ts)
	237	{
	238	struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
	239	u64 ns;
	240
	241	ns = timespec64_to_ns(ts);
	242
	243	mutex_lock(&chip->reg_lock);
	244	timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, ns);
	245	mutex_unlock(&chip->reg_lock);
	246
247	return 0;
248	}
249
6d2ac8ee	250	static int mv88e6352_ptp_enable_extts(struct mv88e6xxx_chip *chip,
4eb3be29 BS	251	struct ptp_clock_request *rq, int on)
	252	{
	253	int rising = (rq->extts.flags & PTP_RISING_EDGE);
	254	int func;
	255	int pin;
	256	int err;
	257
	258	pin = ptp_find_pin(chip->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
	259
	260	if (pin < 0)
	261	return -EBUSY;
	262
	263	mutex_lock(&chip->reg_lock);
	264
	265	if (on) {
	266	func = MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ;
	267
6d2ac8ee	268	err = mv88e6352_set_gpio_func(chip, pin, func, true);
4eb3be29 BS	269	if (err)
	270	goto out;
	271
	272	schedule_delayed_work(&chip->tai_event_work,
	273	TAI_EVENT_WORK_INTERVAL);
	274
6d2ac8ee	275	err = mv88e6352_config_eventcap(chip, PTP_CLOCK_EXTTS, rising);
4eb3be29 BS	276	} else {
	277	func = MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO;
	278
6d2ac8ee	279	err = mv88e6352_set_gpio_func(chip, pin, func, true);
4eb3be29 BS	280
	281	cancel_delayed_work_sync(&chip->tai_event_work);
	282	}
	283
	284	out:
	285	mutex_unlock(&chip->reg_lock);
	286
	287	return err;
	288	}
	289
6d2ac8ee	290	static int mv88e6352_ptp_enable(struct ptp_clock_info *ptp,
2fa8d3af BS	291	struct ptp_clock_request *rq, int on)
2fa8d3af BS	292	{
4eb3be29 BS	293	struct mv88e6xxx_chip *chip = ptp_to_chip(ptp);
	294
	295	switch (rq->type) {
	296	case PTP_CLK_REQ_EXTTS:
6d2ac8ee	297	return mv88e6352_ptp_enable_extts(chip, rq, on);
4eb3be29 BS	298	default:
	299	return -EOPNOTSUPP;
	300	}
2fa8d3af BS	301	}
2fa8d3af BS	302
6d2ac8ee	303	static int mv88e6352_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
2fa8d3af BS	304	enum ptp_pin_function func, unsigned int chan)
2fa8d3af BS	305	{
4eb3be29 BS	306	switch (func) {
	307	case PTP_PF_NONE:
	308	case PTP_PF_EXTTS:
	309	break;
	310	case PTP_PF_PEROUT:
	311	case PTP_PF_PHYSYNC:
	312	return -EOPNOTSUPP;
	313	}
	314	return 0;
2fa8d3af BS	315	}
2fa8d3af BS	316
6d2ac8ee AL	317	const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {
	318	.clock_read = mv88e6352_ptp_clock_read,
	319	.ptp_enable = mv88e6352_ptp_enable,
	320	.ptp_verify = mv88e6352_ptp_verify,
	321	.event_work = mv88e6352_tai_event_work,
ffc705de AL	322	.port_enable = mv88e6352_hwtstamp_port_enable,
ffc705de AL	323	.port_disable = mv88e6352_hwtstamp_port_disable,
6d2ac8ee	324	.n_ext_ts = 1,
ffc705de AL	325	.arr0_sts_reg = MV88E6XXX_PORT_PTP_ARR0_STS,
	326	.arr1_sts_reg = MV88E6XXX_PORT_PTP_ARR1_STS,
	327	.dep_sts_reg = MV88E6XXX_PORT_PTP_DEP_STS,
48cb5e03 AL	328	.rx_filters = (1 << HWTSTAMP_FILTER_NONE) \|
	329	(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) \|
	330	(1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) \|
	331	(1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) \|
	332	(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) \|
	333	(1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) \|
	334	(1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) \|
	335	(1 << HWTSTAMP_FILTER_PTP_V2_EVENT) \|
	336	(1 << HWTSTAMP_FILTER_PTP_V2_SYNC) \|
	337	(1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
6d2ac8ee AL	338	};
6d2ac8ee AL	339
dfa54348 AL	340	const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {
dfa54348 AL	341	.clock_read = mv88e6165_ptp_clock_read,
e2294a8b AL	342	.global_enable = mv88e6165_global_enable,
	343	.global_disable = mv88e6165_global_disable,
	344	.arr0_sts_reg = MV88E6165_PORT_PTP_ARR0_STS,
	345	.arr1_sts_reg = MV88E6165_PORT_PTP_ARR1_STS,
	346	.dep_sts_reg = MV88E6165_PORT_PTP_DEP_STS,
	347	.rx_filters = (1 << HWTSTAMP_FILTER_NONE) \|
	348	(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) \|
	349	(1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) \|
	350	(1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) \|
	351	(1 << HWTSTAMP_FILTER_PTP_V2_EVENT) \|
	352	(1 << HWTSTAMP_FILTER_PTP_V2_SYNC) \|
	353	(1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ),
dfa54348 AL	354	};
dfa54348 AL	355
6d2ac8ee AL	356	static u64 mv88e6xxx_ptp_clock_read(const struct cyclecounter *cc)
	357	{
	358	struct mv88e6xxx_chip *chip = cc_to_chip(cc);
	359
	360	if (chip->info->ops->ptp_ops->clock_read)
	361	return chip->info->ops->ptp_ops->clock_read(cc);
	362
	363	return 0;
	364	}
	365
2fa8d3af BS	366	/* With a 125MHz input clock, the 32-bit timestamp counter overflows in ~34.3
	367	* seconds; this task forces periodic reads so that we don't miss any.
	368	*/
	369	#define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 16)
	370	static void mv88e6xxx_ptp_overflow_check(struct work_struct *work)
	371	{
	372	struct delayed_work *dw = to_delayed_work(work);
	373	struct mv88e6xxx_chip *chip = dw_overflow_to_chip(dw);
	374	struct timespec64 ts;
	375
	376	mv88e6xxx_ptp_gettime(&chip->ptp_clock_info, &ts);
	377
	378	schedule_delayed_work(&chip->overflow_work,
	379	MV88E6XXX_TAI_OVERFLOW_PERIOD);
	380	}
	381
	382	int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip)
	383	{
6d2ac8ee	384	const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
4eb3be29 BS	385	int i;
4eb3be29 BS	386
2fa8d3af BS	387	/* Set up the cycle counter */
	388	memset(&chip->tstamp_cc, 0, sizeof(chip->tstamp_cc));
	389	chip->tstamp_cc.read = mv88e6xxx_ptp_clock_read;
	390	chip->tstamp_cc.mask = CYCLECOUNTER_MASK(32);
	391	chip->tstamp_cc.mult = CC_MULT;
	392	chip->tstamp_cc.shift = CC_SHIFT;
	393
	394	timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc,
	395	ktime_to_ns(ktime_get_real()));
	396
	397	INIT_DELAYED_WORK(&chip->overflow_work, mv88e6xxx_ptp_overflow_check);
6d2ac8ee AL	398	if (ptp_ops->event_work)
6d2ac8ee AL	399	INIT_DELAYED_WORK(&chip->tai_event_work, ptp_ops->event_work);
2fa8d3af BS	400
	401	chip->ptp_clock_info.owner = THIS_MODULE;
	402	snprintf(chip->ptp_clock_info.name, sizeof(chip->ptp_clock_info.name),
	403	dev_name(chip->dev));
	404	chip->ptp_clock_info.max_adj = 1000000;
	405
6d2ac8ee	406	chip->ptp_clock_info.n_ext_ts = ptp_ops->n_ext_ts;
4eb3be29 BS	407	chip->ptp_clock_info.n_per_out = 0;
	408	chip->ptp_clock_info.n_pins = mv88e6xxx_num_gpio(chip);
	409	chip->ptp_clock_info.pps = 0;
	410
	411	for (i = 0; i < chip->ptp_clock_info.n_pins; ++i) {
	412	struct ptp_pin_desc *ppd = &chip->pin_config[i];
	413
	414	snprintf(ppd->name, sizeof(ppd->name), "mv88e6xxx_gpio%d", i);
	415	ppd->index = i;
	416	ppd->func = PTP_PF_NONE;
	417	}
	418	chip->ptp_clock_info.pin_config = chip->pin_config;
	419
2fa8d3af BS	420	chip->ptp_clock_info.adjfine = mv88e6xxx_ptp_adjfine;
	421	chip->ptp_clock_info.adjtime = mv88e6xxx_ptp_adjtime;
	422	chip->ptp_clock_info.gettime64 = mv88e6xxx_ptp_gettime;
	423	chip->ptp_clock_info.settime64 = mv88e6xxx_ptp_settime;
6d2ac8ee AL	424	chip->ptp_clock_info.enable = ptp_ops->ptp_enable;
6d2ac8ee AL	425	chip->ptp_clock_info.verify = ptp_ops->ptp_verify;
c6fe0ad2	426	chip->ptp_clock_info.do_aux_work = mv88e6xxx_hwtstamp_work;
2fa8d3af BS	427
	428	chip->ptp_clock = ptp_clock_register(&chip->ptp_clock_info, chip->dev);
	429	if (IS_ERR(chip->ptp_clock))
	430	return PTR_ERR(chip->ptp_clock);
	431
	432	schedule_delayed_work(&chip->overflow_work,
	433	MV88E6XXX_TAI_OVERFLOW_PERIOD);
	434
	435	return 0;
	436	}
	437
	438	void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip)
	439	{
	440	if (chip->ptp_clock) {
	441	cancel_delayed_work_sync(&chip->overflow_work);
6d2ac8ee AL	442	if (chip->info->ops->ptp_ops->event_work)
6d2ac8ee AL	443	cancel_delayed_work_sync(&chip->tai_event_work);
2fa8d3af BS	444
	445	ptp_clock_unregister(chip->ptp_clock);
	446	chip->ptp_clock = NULL;
	447	}
	448	}