projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 18abed21 VD |
2 | /* |
| 3 | * Marvell 88E6xxx Switch Port Registers support | |
| 4 | * | |
| 5 | * Copyright (c) 2008 Marvell Semiconductor | |
| 6 | * | |
| 4333d619 VD |
7 | * Copyright (c) 2016-2017 Savoir-faire Linux Inc. |
| 8 | * Vivien Didelot <vivien.didelot@savoirfairelinux.com> | |
| 18abed21 VD |
9 | */ |
| 10 | ||
| 11 | #ifndef _MV88E6XXX_PORT_H | |
| 12 | #define _MV88E6XXX_PORT_H | |
| 13 | ||
| 4d5f2ba7 | 14 | #include "chip.h" |
| 18abed21 | 15 | |
| 5f83dc93 VD |
16 | /* Offset 0x00: Port Status Register */ |
| 17 | #define MV88E6XXX_PORT_STS 0x00 | |
| 18 | #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 | |
| 19 | #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 | |
| 20 | #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 | |
| 21 | #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 | |
| ce91c453 RV |
22 | #define MV88E6250_PORT_STS_LINK 0x1000 |
| 23 | #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00 | |
| 24 | #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800 | |
| 25 | #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900 | |
| 26 | #define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a00 | |
| 27 | #define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b00 | |
| a4e38990 MS |
28 | /* - Modes with PHY suffix use output instead of input clock |
| 29 | * - Modes without RMII or RGMII use MII | |
| 30 | * - Modes without speed do not have a fixed speed specified in the manual | |
| 31 | * ("DC to x MHz" - variable clock support?) | |
| 32 | */ | |
| 33 | #define MV88E6250_PORT_STS_PORTMODE_MII_DISABLED 0x0000 | |
| 34 | #define MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII 0x0100 | |
| 35 | #define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY 0x0200 | |
| 36 | #define MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY 0x0400 | |
| 37 | #define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL 0x0600 | |
| 38 | #define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL 0x0700 | |
| 39 | #define MV88E6250_PORT_STS_PORTMODE_MII_HALF 0x0800 | |
| 40 | #define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY 0x0900 | |
| 41 | #define MV88E6250_PORT_STS_PORTMODE_MII_FULL 0x0a00 | |
| 42 | #define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY 0x0b00 | |
| 43 | #define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY 0x0c00 | |
| 44 | #define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY 0x0d00 | |
| 45 | #define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY 0x0e00 | |
| 46 | #define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY 0x0f00 | |
| 5f83dc93 VD |
47 | #define MV88E6XXX_PORT_STS_LINK 0x0800 |
| 48 | #define MV88E6XXX_PORT_STS_DUPLEX 0x0400 | |
| 49 | #define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 | |
| 50 | #define MV88E6XXX_PORT_STS_SPEED_10 0x0000 | |
| 51 | #define MV88E6XXX_PORT_STS_SPEED_100 0x0100 | |
| 52 | #define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 | |
| c9a2356f | 53 | #define MV88E6XXX_PORT_STS_SPEED_10000 0x0300 |
| 5f83dc93 VD |
54 | #define MV88E6352_PORT_STS_EEE 0x0040 |
| 55 | #define MV88E6165_PORT_STS_AM_DIS 0x0040 | |
| 56 | #define MV88E6185_PORT_STS_MGMII 0x0040 | |
| 57 | #define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 | |
| 58 | #define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 | |
| 59 | #define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f | |
| d4ebf12b RKO |
60 | #define MV88E6XXX_PORT_STS_CMODE_MII_PHY 0x0001 |
| 61 | #define MV88E6XXX_PORT_STS_CMODE_MII 0x0002 | |
| 62 | #define MV88E6XXX_PORT_STS_CMODE_GMII 0x0003 | |
| 63 | #define MV88E6XXX_PORT_STS_CMODE_RMII_PHY 0x0004 | |
| 64 | #define MV88E6XXX_PORT_STS_CMODE_RMII 0x0005 | |
| 927441ad | 65 | #define MV88E6XXX_PORT_STS_CMODE_RGMII 0x0007 |
| 3bbb8867 MB |
66 | #define MV88E6XXX_PORT_STS_CMODE_100BASEX 0x0008 |
| 67 | #define MV88E6XXX_PORT_STS_CMODE_1000BASEX 0x0009 | |
| 5f83dc93 VD |
68 | #define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a |
| 69 | #define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b | |
| 70 | #define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c | |
| 71 | #define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d | |
| de776d0d PS |
72 | #define MV88E6393X_PORT_STS_CMODE_5GBASER 0x000c |
| 73 | #define MV88E6393X_PORT_STS_CMODE_10GBASER 0x000d | |
| 74 | #define MV88E6393X_PORT_STS_CMODE_USXGMII 0x000e | |
| 6c422e34 RK |
75 | #define MV88E6185_PORT_STS_CDUPLEX 0x0008 |
| 76 | #define MV88E6185_PORT_STS_CMODE_MASK 0x0007 | |
| 77 | #define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000 | |
| 78 | #define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001 | |
| 79 | #define MV88E6185_PORT_STS_CMODE_MII_100 0x0002 | |
| 80 | #define MV88E6185_PORT_STS_CMODE_MII_10 0x0003 | |
| 81 | #define MV88E6185_PORT_STS_CMODE_SERDES 0x0004 | |
| 82 | #define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005 | |
| 83 | #define MV88E6185_PORT_STS_CMODE_PHY 0x0006 | |
| 84 | #define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007 | |
| 5f83dc93 | 85 | |
| 5ee55577 VD |
86 | /* Offset 0x01: MAC (or PCS or Physical) Control Register */ |
| 87 | #define MV88E6XXX_PORT_MAC_CTL 0x01 | |
| 88 | #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 | |
| 89 | #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 | |
| 6c422e34 | 90 | #define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000 |
| 5ee55577 VD |
91 | #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 |
| 92 | #define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 | |
| 93 | #define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 | |
| de776d0d PS |
94 | #define MV88E6XXX_PORT_MAC_CTL_EEE 0x0200 |
| 95 | #define MV88E6XXX_PORT_MAC_CTL_FORCE_EEE 0x0100 | |
| 6c422e34 RK |
96 | #define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400 |
| 97 | #define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200 | |
| 98 | #define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100 | |
| 5ee55577 VD |
99 | #define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 |
| 100 | #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 | |
| 101 | #define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 | |
| 102 | #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 | |
| 103 | #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 | |
| 104 | #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 | |
| 105 | #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 | |
| 106 | #define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 | |
| 107 | #define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 | |
| 108 | #define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 | |
| 109 | #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 | |
| 110 | #define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 | |
| 111 | #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 | |
| 112 | ||
| 6c96bbfd VD |
113 | /* Offset 0x02: Jamming Control Register */ |
| 114 | #define MV88E6097_PORT_JAM_CTL 0x02 | |
| 115 | #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 | |
| 116 | #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff | |
| 117 | ||
| 118 | /* Offset 0x02: Flow Control Register */ | |
| 119 | #define MV88E6390_PORT_FLOW_CTL 0x02 | |
| 120 | #define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 | |
| 121 | #define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 | |
| 122 | #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 | |
| 123 | #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 | |
| 124 | #define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff | |
| 125 | ||
| 107fcc10 VD |
126 | /* Offset 0x03: Switch Identifier Register */ |
| 127 | #define MV88E6XXX_PORT_SWITCH_ID 0x03 | |
| 128 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0 | |
| 71d94a43 | 129 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6020 0x0200 |
| 372188c8 | 130 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6071 0x0710 |
| 107fcc10 VD |
131 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0 |
| 132 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950 | |
| 133 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990 | |
| 134 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00 | |
| 135 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10 | |
| 136 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060 | |
| 137 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150 | |
| 138 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210 | |
| 139 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610 | |
| 140 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650 | |
| 141 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710 | |
| 142 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720 | |
| 143 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750 | |
| 144 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 | |
| 145 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 | |
| 146 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 | |
| de776d0d PS |
147 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X 0x1920 |
| 148 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X 0x1930 | |
| 107fcc10 | 149 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 |
| 49022647 | 150 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200 |
| 107fcc10 | 151 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 |
| 1f71836f | 152 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500 |
| 12899f29 | 153 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610 |
| 107fcc10 VD |
154 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900 |
| 155 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100 | |
| 156 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400 | |
| 157 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410 | |
| 158 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520 | |
| 159 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 | |
| 160 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 | |
| 161 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 | |
| de776d0d | 162 | #define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X 0x3930 |
| 107fcc10 VD |
163 | #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f |
| 164 | ||
| a89b433b VD |
165 | /* Offset 0x04: Port Control Register */ |
| 166 | #define MV88E6XXX_PORT_CTL0 0x04 | |
| 167 | #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 | |
| 34ea415f HS |
168 | #define MV88E6XXX_PORT_CTL0_SA_FILT_MASK 0xc000 |
| 169 | #define MV88E6XXX_PORT_CTL0_SA_FILT_DISABLED 0x0000 | |
| 170 | #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK 0x4000 | |
| 171 | #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_UNLOCK 0x8000 | |
| 172 | #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_CPU 0xc000 | |
| a89b433b VD |
173 | #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 |
| 174 | #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000 | |
| 175 | #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000 | |
| 176 | #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000 | |
| 177 | #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 | |
| 178 | #define MV88E6XXX_PORT_CTL0_HEADER 0x0800 | |
| 179 | #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 | |
| 180 | #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 | |
| 181 | #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300 | |
| 182 | #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000 | |
| 183 | #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100 | |
| 184 | #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200 | |
| 185 | #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300 | |
| 186 | #define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 | |
| 187 | #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080 | |
| 188 | #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040 | |
| 189 | #define MV88E6185_PORT_CTL0_USE_IP 0x0020 | |
| 190 | #define MV88E6185_PORT_CTL0_USE_TAG 0x0010 | |
| 191 | #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004 | |
| a8b659e7 VO |
192 | #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC 0x0004 |
| 193 | #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC 0x0008 | |
| a89b433b VD |
194 | #define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 |
| 195 | #define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000 | |
| 196 | #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001 | |
| 197 | #define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 | |
| 198 | #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 | |
| 199 | ||
| cd985bbf VD |
200 | /* Offset 0x05: Port Control 1 */ |
| 201 | #define MV88E6XXX_PORT_CTL1 0x05 | |
| 202 | #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000 | |
| 57e661aa TW |
203 | #define MV88E6XXX_PORT_CTL1_TRUNK_PORT 0x4000 |
| 204 | #define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK 0x0f00 | |
| 205 | #define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT 8 | |
| cd985bbf VD |
206 | #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff |
| 207 | ||
| 7e5cc5f1 VD |
208 | /* Offset 0x06: Port Based VLAN Map */ |
| 209 | #define MV88E6XXX_PORT_BASE_VLAN 0x06 | |
| 210 | #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000 | |
| 211 | ||
| b7929fb3 VD |
212 | /* Offset 0x07: Default Port VLAN ID & Priority */ |
| 213 | #define MV88E6XXX_PORT_DEFAULT_VLAN 0x07 | |
| 214 | #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff | |
| 215 | ||
| 81c6edb2 VD |
216 | /* Offset 0x08: Port Control 2 Register */ |
| 217 | #define MV88E6XXX_PORT_CTL2 0x08 | |
| 218 | #define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000 | |
| 219 | #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000 | |
| 220 | #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000 | |
| 221 | #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000 | |
| 222 | #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000 | |
| 223 | #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000 | |
| 224 | #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000 | |
| 225 | #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000 | |
| 226 | #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00 | |
| 227 | #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000 | |
| 228 | #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400 | |
| 229 | #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800 | |
| 230 | #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00 | |
| 231 | #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200 | |
| 232 | #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100 | |
| 233 | #define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080 | |
| 234 | #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040 | |
| 235 | #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020 | |
| 236 | #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010 | |
| 237 | #define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f | |
| 238 | ||
| 2cb8cb14 VD |
239 | /* Offset 0x09: Egress Rate Control */ |
| 240 | #define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09 | |
| 241 | ||
| 242 | /* Offset 0x0A: Egress Rate Control 2 */ | |
| 243 | #define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a | |
| 244 | ||
| 2a4614e4 VD |
245 | /* Offset 0x0B: Port Association Vector */ |
| 246 | #define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b | |
| 247 | #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000 | |
| 248 | #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000 | |
| 249 | #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000 | |
| 250 | #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000 | |
| 251 | #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800 | |
| 252 | ||
| b8109594 VD |
253 | /* Offset 0x0C: Port ATU Control */ |
| 254 | #define MV88E6XXX_PORT_ATU_CTL 0x0c | |
| 255 | ||
| 256 | /* Offset 0x0D: Priority Override Register */ | |
| 257 | #define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d | |
| 258 | ||
| 259 | /* Offset 0x0E: Policy Control Register */ | |
| f3a2cd32 VD |
260 | #define MV88E6XXX_PORT_POLICY_CTL 0x0e |
| 261 | #define MV88E6XXX_PORT_POLICY_CTL_DA_MASK 0xc000 | |
| 262 | #define MV88E6XXX_PORT_POLICY_CTL_SA_MASK 0x3000 | |
| 263 | #define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK 0x0c00 | |
| 264 | #define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK 0x0300 | |
| 265 | #define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK 0x00c0 | |
| 266 | #define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK 0x0030 | |
| 267 | #define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK 0x000c | |
| 268 | #define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK 0x0003 | |
| 269 | #define MV88E6XXX_PORT_POLICY_CTL_NORMAL 0x0000 | |
| 270 | #define MV88E6XXX_PORT_POLICY_CTL_MIRROR 0x0001 | |
| 271 | #define MV88E6XXX_PORT_POLICY_CTL_TRAP 0x0002 | |
| 272 | #define MV88E6XXX_PORT_POLICY_CTL_DISCARD 0x0003 | |
| b8109594 | 273 | |
| de776d0d PS |
274 | /* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */ |
| 275 | #define MV88E6393X_PORT_POLICY_MGMT_CTL 0x0e | |
| 276 | #define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE 0x8000 | |
| 277 | #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK 0x3f00 | |
| 278 | #define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK 0x00ff | |
| 279 | #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO 0x2000 | |
| 280 | #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI 0x2100 | |
| 281 | #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO 0x2400 | |
| 282 | #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI 0x2500 | |
| 283 | #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST 0x3000 | |
| 284 | #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST 0x3800 | |
| 285 | #define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI 0x00e0 | |
| 286 | ||
| b8109594 VD |
287 | /* Offset 0x0F: Port Special Ether Type */ |
| 288 | #define MV88E6XXX_PORT_ETH_TYPE 0x0f | |
| 289 | #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100 | |
| 290 | ||
| 291 | /* Offset 0x10: InDiscards Low Counter */ | |
| 292 | #define MV88E6XXX_PORT_IN_DISCARD_LO 0x10 | |
| 293 | ||
| de776d0d PS |
294 | /* Offset 0x10: Extended Port Control Command */ |
| 295 | #define MV88E6393X_PORT_EPC_CMD 0x10 | |
| 296 | #define MV88E6393X_PORT_EPC_CMD_BUSY 0x8000 | |
| 1323e0c6 | 297 | #define MV88E6393X_PORT_EPC_CMD_WRITE 0x3000 |
| de776d0d PS |
298 | #define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE 0x02 |
| 299 | ||
| 300 | /* Offset 0x11: Extended Port Control Data */ | |
| 301 | #define MV88E6393X_PORT_EPC_DATA 0x11 | |
| 302 | ||
| b8109594 VD |
303 | /* Offset 0x11: InDiscards High Counter */ |
| 304 | #define MV88E6XXX_PORT_IN_DISCARD_HI 0x11 | |
| 305 | ||
| 306 | /* Offset 0x12: InFiltered Counter */ | |
| 307 | #define MV88E6XXX_PORT_IN_FILTERED 0x12 | |
| 308 | ||
| 309 | /* Offset 0x13: OutFiltered Counter */ | |
| 310 | #define MV88E6XXX_PORT_OUT_FILTERED 0x13 | |
| 311 | ||
| 8009df9e VD |
312 | /* Offset 0x18: IEEE Priority Mapping Table */ |
| 313 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18 | |
| 314 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 | |
| ddcbabf4 | 315 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000 |
| 8009df9e VD |
316 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000 |
| 317 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000 | |
| 318 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000 | |
| 319 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000 | |
| 320 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000 | |
| 321 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000 | |
| 322 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000 | |
| ddcbabf4 VD |
323 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00 |
| 324 | #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff | |
| 8009df9e VD |
325 | |
| 326 | /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */ | |
| 327 | #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18 | |
| 328 | ||
| 329 | /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */ | |
| 330 | #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19 | |
| d2a160b5 | 331 | |
| ea89098e | 332 | /* Offset 0x1a: Magic undocumented errata register */ |
| 60907013 MB |
333 | #define MV88E6XXX_PORT_RESERVED_1A 0x1a |
| 334 | #define MV88E6XXX_PORT_RESERVED_1A_BUSY 0x8000 | |
| 335 | #define MV88E6XXX_PORT_RESERVED_1A_WRITE 0x4000 | |
| 336 | #define MV88E6XXX_PORT_RESERVED_1A_READ 0x0000 | |
| 337 | #define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT 5 | |
| 338 | #define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT 10 | |
| 339 | #define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT 0x04 | |
| 340 | #define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT 0x05 | |
| 7a3007d2 MB |
341 | #define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE 0x8000 |
| 342 | #define MV88E6341_PORT_RESERVED_1A_SGMII_AN 0x2000 | |
| ea89098e | 343 | |
| 18abed21 VD |
344 | int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, |
| 345 | u16 *val); | |
| 346 | int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, | |
| 347 | u16 val); | |
| de776d0d PS |
348 | int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, |
| 349 | int bit, int val); | |
| 18abed21 | 350 | |
| 54186b91 AL |
351 | int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, |
| 352 | int pause); | |
| 91e87045 SB |
353 | int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, |
| 354 | phy_interface_t mode); | |
| a0a0f622 VD |
355 | int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, |
| 356 | phy_interface_t mode); | |
| 357 | int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, | |
| 358 | phy_interface_t mode); | |
| 359 | ||
| 08ef7f10 VD |
360 | int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); |
| 361 | ||
| 4efe7662 CP |
362 | int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); |
| 363 | int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); | |
| 364 | ||
| f365c6f7 RK |
365 | int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, |
| 366 | int speed, int duplex); | |
| 367 | int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, | |
| 368 | int speed, int duplex); | |
| 369 | int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, | |
| 370 | int speed, int duplex); | |
| 371 | int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, | |
| 372 | int speed, int duplex); | |
| 373 | int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, | |
| 374 | int speed, int duplex); | |
| 375 | int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, | |
| 376 | int speed, int duplex); | |
| de776d0d PS |
377 | int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, |
| 378 | int speed, int duplex); | |
| 96a2b40c | 379 | |
| 18e1b742 AL |
380 | phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip, |
| 381 | int port); | |
| 382 | phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip, | |
| 383 | int port); | |
| 384 | phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip, | |
| 385 | int port); | |
| 386 | phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip, | |
| 387 | int port); | |
| 7cbbee05 | 388 | |
| e28def33 VD |
389 | int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); |
| 390 | ||
| 5a7921f4 VD |
391 | int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); |
| 392 | ||
| b4e48c50 VD |
393 | int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); |
| 394 | int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); | |
| 395 | ||
| 77064f37 VD |
396 | int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); |
| 397 | int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); | |
| 398 | ||
| 34ea415f HS |
399 | int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, |
| 400 | bool locked); | |
| 401 | ||
| 385a0995 VD |
402 | int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, |
| 403 | u16 mode); | |
| ef0a7318 AL |
404 | int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); |
| 405 | int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); | |
| 56995cbc | 406 | int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, |
| 31bef4e9 | 407 | enum mv88e6xxx_egress_mode mode); |
| 56995cbc AL |
408 | int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, |
| 409 | enum mv88e6xxx_frame_mode mode); | |
| 410 | int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, | |
| 411 | enum mv88e6xxx_frame_mode mode); | |
| a8b659e7 VO |
412 | int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, |
| 413 | int port, bool unicast); | |
| 414 | int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, | |
| 415 | int port, bool multicast); | |
| 416 | int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, | |
| 417 | bool unicast); | |
| 418 | int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, | |
| 419 | bool multicast); | |
| f3a2cd32 VD |
420 | int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, |
| 421 | enum mv88e6xxx_policy_mapping mapping, | |
| 422 | enum mv88e6xxx_policy_action action); | |
| 6584b260 MB |
423 | int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, |
| 424 | enum mv88e6xxx_policy_mapping mapping, | |
| 425 | enum mv88e6xxx_policy_action action); | |
| 56995cbc AL |
426 | int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, |
| 427 | u16 etype); | |
| de776d0d PS |
428 | int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, |
| 429 | enum mv88e6xxx_egress_direction direction, | |
| 430 | int port); | |
| 431 | int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, | |
| 432 | int upstream_port); | |
| 433 | int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); | |
| 434 | int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, | |
| 435 | u16 etype); | |
| ea698f4f VD |
436 | int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, |
| 437 | bool message_port); | |
| 57e661aa TW |
438 | int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, |
| 439 | bool trunk, u8 id); | |
| cd782656 VD |
440 | int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, |
| 441 | size_t size); | |
| ef70b111 AL |
442 | int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); |
| 443 | int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); | |
| 041bd545 TW |
444 | int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, |
| 445 | u16 pav); | |
| 0898432c VD |
446 | int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, |
| 447 | u8 out); | |
| 448 | int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, | |
| 449 | u8 out); | |
| 7a3007d2 MB |
450 | int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, |
| 451 | phy_interface_t mode); | |
| fdc71eea AL |
452 | int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, |
| 453 | phy_interface_t mode); | |
| f39908d3 | 454 | int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, |
| de776d0d PS |
455 | phy_interface_t mode); |
| 456 | int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, | |
| f39908d3 | 457 | phy_interface_t mode); |
| 2d2e1dd2 AL |
458 | int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); |
| 459 | int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); | |
| 8b6836d8 VO |
460 | int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, |
| 461 | bool drop_untagged); | |
| 7af4a361 | 462 | int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map); |
| a23b2961 AL |
463 | int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, |
| 464 | int upstream_port); | |
| f0942e00 IT |
465 | int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, |
| 466 | enum mv88e6xxx_egress_direction direction, | |
| 467 | bool mirror); | |
| c8c94891 VD |
468 | |
| 469 | int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); | |
| 9dbfb4e1 | 470 | int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); |
| c8c94891 | 471 | |
| 60907013 MB |
472 | int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block, |
| 473 | int port, int reg, u16 val); | |
| 474 | int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip); | |
| 475 | int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port, | |
| 476 | int reg, u16 *val); | |
| 477 | ||
| 18abed21 | 478 | #endif /* _MV88E6XXX_PORT_H */ |