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net: dsa: mv88e6xxx: Refactor setting of jumbo frames
[linux-2.6-block.git] / drivers / net / dsa / mv88e6xxx / port.c
CommitLineData
18abed21
VD		 1/*
2 * Marvell 88E6xxx Switch Port Registers support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include "mv88e6xxx.h"
15#include "port.h"
16
17int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
18 u16 *val)
19{
20 int addr = chip->info->port_base_addr + port;
21
22 return mv88e6xxx_read(chip, addr, reg, val);
23}
24
25int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
26 u16 val)
27{
28 int addr = chip->info->port_base_addr + port;
29
30 return mv88e6xxx_write(chip, addr, reg, val);
31}
e28def33 32
08ef7f10
VD		 33/* Offset 0x01: MAC (or PCS or Physical) Control Register
34 *
35 * Link, Duplex and Flow Control have one force bit, one value bit.
96a2b40c
VD		 36 *
37 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
38 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
39 * Newer chips need a ForcedSpd bit 13 set to consider the value.
08ef7f10
VD		 40 */
41
a0a0f622
VD		 42static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
43 phy_interface_t mode)
44{
45 u16 reg;
46 int err;
47
48 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
49 if (err)
50 return err;
51
52 reg &= ~(PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
53 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
54
55 switch (mode) {
56 case PHY_INTERFACE_MODE_RGMII_RXID:
57 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
58 break;
59 case PHY_INTERFACE_MODE_RGMII_TXID:
60 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
61 break;
62 case PHY_INTERFACE_MODE_RGMII_ID:
63 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
64 PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
65 break;
fedf1865 66 case PHY_INTERFACE_MODE_RGMII:
a0a0f622 67 break;
fedf1865
AL		 68 default:
69 return 0;
a0a0f622
VD		 70 }
71
72 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
73 if (err)
74 return err;
75
76 netdev_dbg(chip->ds->ports[port].netdev, "delay RXCLK %s, TXCLK %s\n",
77 reg & PORT_PCS_CTRL_RGMII_DELAY_RXCLK ? "yes" : "no",
78 reg & PORT_PCS_CTRL_RGMII_DELAY_TXCLK ? "yes" : "no");
79
80 return 0;
81}
82
83int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
84 phy_interface_t mode)
85{
86 if (port < 5)
87 return -EOPNOTSUPP;
88
89 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
90}
91
92int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
93 phy_interface_t mode)
94{
95 if (port != 0)
96 return -EOPNOTSUPP;
97
98 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
99}
100
08ef7f10
VD		 101int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
102{
103 u16 reg;
104 int err;
105
106 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
107 if (err)
108 return err;
109
110 reg &= ~(PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP);
111
112 switch (link) {
113 case LINK_FORCED_DOWN:
114 reg |= PORT_PCS_CTRL_FORCE_LINK;
115 break;
116 case LINK_FORCED_UP:
117 reg |= PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP;
118 break;
119 case LINK_UNFORCED:
120 /* normal link detection */
121 break;
122 default:
123 return -EINVAL;
124 }
125
126 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
127 if (err)
128 return err;
129
130 netdev_dbg(chip->ds->ports[port].netdev, "%s link %s\n",
131 reg & PORT_PCS_CTRL_FORCE_LINK ? "Force" : "Unforce",
132 reg & PORT_PCS_CTRL_LINK_UP ? "up" : "down");
133
134 return 0;
135}
136
7f1ae07b
VD		 137int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
138{
139 u16 reg;
140 int err;
141
142 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
143 if (err)
144 return err;
145
146 reg &= ~(PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL);
147
148 switch (dup) {
149 case DUPLEX_HALF:
150 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
151 break;
152 case DUPLEX_FULL:
153 reg |= PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL;
154 break;
155 case DUPLEX_UNFORCED:
156 /* normal duplex detection */
157 break;
158 default:
159 return -EINVAL;
160 }
161
162 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
163 if (err)
164 return err;
165
166 netdev_dbg(chip->ds->ports[port].netdev, "%s %s duplex\n",
167 reg & PORT_PCS_CTRL_FORCE_DUPLEX ? "Force" : "Unforce",
168 reg & PORT_PCS_CTRL_DUPLEX_FULL ? "full" : "half");
169
170 return 0;
171}
172
96a2b40c
VD		 173static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
174 int speed, bool alt_bit, bool force_bit)
175{
176 u16 reg, ctrl;
177 int err;
178
179 switch (speed) {
180 case 10:
181 ctrl = PORT_PCS_CTRL_SPEED_10;
182 break;
183 case 100:
184 ctrl = PORT_PCS_CTRL_SPEED_100;
185 break;
186 case 200:
187 if (alt_bit)
188 ctrl = PORT_PCS_CTRL_SPEED_100 | PORT_PCS_CTRL_ALTSPEED;
189 else
190 ctrl = PORT_PCS_CTRL_SPEED_200;
191 break;
192 case 1000:
193 ctrl = PORT_PCS_CTRL_SPEED_1000;
194 break;
195 case 2500:
196 ctrl = PORT_PCS_CTRL_SPEED_1000 | PORT_PCS_CTRL_ALTSPEED;
197 break;
198 case 10000:
199 /* all bits set, fall through... */
200 case SPEED_UNFORCED:
201 ctrl = PORT_PCS_CTRL_SPEED_UNFORCED;
202 break;
203 default:
204 return -EOPNOTSUPP;
205 }
206
207 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
208 if (err)
209 return err;
210
211 reg &= ~PORT_PCS_CTRL_SPEED_MASK;
212 if (alt_bit)
213 reg &= ~PORT_PCS_CTRL_ALTSPEED;
214 if (force_bit) {
215 reg &= ~PORT_PCS_CTRL_FORCE_SPEED;
0b6e3d03 216 if (speed != SPEED_UNFORCED)
96a2b40c
VD		 217 ctrl |= PORT_PCS_CTRL_FORCE_SPEED;
218 }
219 reg |= ctrl;
220
221 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
222 if (err)
223 return err;
224
225 if (speed)
226 netdev_dbg(chip->ds->ports[port].netdev,
227 "Speed set to %d Mbps\n", speed);
228 else
229 netdev_dbg(chip->ds->ports[port].netdev, "Speed unforced\n");
230
231 return 0;
232}
233
234/* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
235int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
236{
237 if (speed == SPEED_MAX)
238 speed = 200;
239
240 if (speed > 200)
241 return -EOPNOTSUPP;
242
243 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
244 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
245}
246
247/* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
248int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
249{
250 if (speed == SPEED_MAX)
251 speed = 1000;
252
253 if (speed == 200 || speed > 1000)
254 return -EOPNOTSUPP;
255
256 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
257}
258
259/* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
260int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
261{
262 if (speed == SPEED_MAX)
263 speed = 1000;
264
265 if (speed > 1000)
266 return -EOPNOTSUPP;
267
268 if (speed == 200 && port < 5)
269 return -EOPNOTSUPP;
270
271 return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
272}
273
274/* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
275int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
276{
277 if (speed == SPEED_MAX)
278 speed = port < 9 ? 1000 : 2500;
279
280 if (speed > 2500)
281 return -EOPNOTSUPP;
282
283 if (speed == 200 && port != 0)
284 return -EOPNOTSUPP;
285
286 if (speed == 2500 && port < 9)
287 return -EOPNOTSUPP;
288
289 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
290}
291
292/* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
293int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
294{
295 if (speed == SPEED_MAX)
296 speed = port < 9 ? 1000 : 10000;
297
298 if (speed == 200 && port != 0)
299 return -EOPNOTSUPP;
300
301 if (speed >= 2500 && port < 9)
302 return -EOPNOTSUPP;
303
304 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
305}
306
e28def33
VD		 307/* Offset 0x04: Port Control Register */
308
309static const char * const mv88e6xxx_port_state_names[] = {
310 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
311 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
312 [PORT_CONTROL_STATE_LEARNING] = "Learning",
313 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
314};
315
316int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
317{
318 u16 reg;
319 int err;
320
321 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
322 if (err)
323 return err;
324
325 reg &= ~PORT_CONTROL_STATE_MASK;
326 reg |= state;
327
328 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
329 if (err)
330 return err;
331
332 netdev_dbg(chip->ds->ports[port].netdev, "PortState set to %s\n",
333 mv88e6xxx_port_state_names[state]);
334
335 return 0;
336}
5a7921f4 337
56995cbc
AL		 338int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
339 u16 mode)
340{
341 int err;
342 u16 reg;
343
344 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
345 if (err)
346 return err;
347
348 reg &= ~PORT_CONTROL_EGRESS_MASK;
349 reg |= mode;
350
351 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
352}
353
354int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
355 enum mv88e6xxx_frame_mode mode)
356{
357 int err;
358 u16 reg;
359
360 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
361 if (err)
362 return err;
363
364 reg &= ~PORT_CONTROL_FRAME_MODE_DSA;
365
366 switch (mode) {
367 case MV88E6XXX_FRAME_MODE_NORMAL:
368 reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
369 break;
370 case MV88E6XXX_FRAME_MODE_DSA:
371 reg |= PORT_CONTROL_FRAME_MODE_DSA;
372 break;
373 default:
374 return -EINVAL;
375 }
376
377 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
378}
379
380int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
381 enum mv88e6xxx_frame_mode mode)
382{
383 int err;
384 u16 reg;
385
386 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
387 if (err)
388 return err;
389
390 reg &= ~PORT_CONTROL_FRAME_MASK;
391
392 switch (mode) {
393 case MV88E6XXX_FRAME_MODE_NORMAL:
394 reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
395 break;
396 case MV88E6XXX_FRAME_MODE_DSA:
397 reg |= PORT_CONTROL_FRAME_MODE_DSA;
398 break;
399 case MV88E6XXX_FRAME_MODE_PROVIDER:
400 reg |= PORT_CONTROL_FRAME_MODE_PROVIDER;
401 break;
402 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
403 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
404 break;
405 default:
406 return -EINVAL;
407 }
408
409 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
410}
411
412int mv88e6085_port_set_egress_unknowns(struct mv88e6xxx_chip *chip, int port,
413 bool on)
414{
415 int err;
416 u16 reg;
417
418 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
419 if (err)
420 return err;
421
422 if (on)
423 reg |= PORT_CONTROL_FORWARD_UNKNOWN;
424 else
425 reg &= ~PORT_CONTROL_FORWARD_UNKNOWN;
426
427 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
428}
429
430int mv88e6351_port_set_egress_unknowns(struct mv88e6xxx_chip *chip, int port,
431 bool on)
432{
433 int err;
434 u16 reg;
435
436 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
437 if (err)
438 return err;
439
440 if (on)
441 reg |= PORT_CONTROL_EGRESS_ALL_UNKNOWN_DA;
442 else
443 reg &= ~PORT_CONTROL_EGRESS_ALL_UNKNOWN_DA;
444
445 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
446}
447
b4e48c50
VD		 448/* Offset 0x05: Port Control 1 */
449
5a7921f4
VD		 450/* Offset 0x06: Port Based VLAN Map */
451
452int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
453{
454 const u16 mask = GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
455 u16 reg;
456 int err;
457
458 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
459 if (err)
460 return err;
461
462 reg &= ~mask;
463 reg |= map & mask;
464
465 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
466 if (err)
467 return err;
468
469 netdev_dbg(chip->ds->ports[port].netdev, "VLANTable set to %.3x\n",
470 map);
471
472 return 0;
473}
b4e48c50
VD		 474
475int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
476{
477 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
478 u16 reg;
479 int err;
480
481 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
482 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
483 if (err)
484 return err;
485
486 *fid = (reg & 0xf000) >> 12;
487
488 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
489 if (upper_mask) {
490 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg);
491 if (err)
492 return err;
493
494 *fid |= (reg & upper_mask) << 4;
495 }
496
497 return 0;
498}
499
500int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
501{
502 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
503 u16 reg;
504 int err;
505
506 if (fid >= mv88e6xxx_num_databases(chip))
507 return -EINVAL;
508
509 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
510 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
511 if (err)
512 return err;
513
514 reg &= 0x0fff;
515 reg |= (fid & 0x000f) << 12;
516
517 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
518 if (err)
519 return err;
520
521 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
522 if (upper_mask) {
523 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg);
524 if (err)
525 return err;
526
527 reg &= ~upper_mask;
528 reg |= (fid >> 4) & upper_mask;
529
530 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
531 if (err)
532 return err;
533 }
534
535 netdev_dbg(chip->ds->ports[port].netdev, "FID set to %u\n", fid);
536
537 return 0;
538}
77064f37
VD		 539
540/* Offset 0x07: Default Port VLAN ID & Priority */
541
542int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
543{
544 u16 reg;
545 int err;
546
547 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, &reg);
548 if (err)
549 return err;
550
551 *pvid = reg & PORT_DEFAULT_VLAN_MASK;
552
553 return 0;
554}
555
556int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
557{
558 u16 reg;
559 int err;
560
561 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, &reg);
562 if (err)
563 return err;
564
565 reg &= ~PORT_DEFAULT_VLAN_MASK;
566 reg |= pvid & PORT_DEFAULT_VLAN_MASK;
567
568 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
569 if (err)
570 return err;
571
572 netdev_dbg(chip->ds->ports[port].netdev, "DefaultVID set to %u\n",
573 pvid);
574
575 return 0;
576}
385a0995
VD		 577
578/* Offset 0x08: Port Control 2 Register */
579
580static const char * const mv88e6xxx_port_8021q_mode_names[] = {
581 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
582 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
583 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
584 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
585};
586
587int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
588 u16 mode)
589{
590 u16 reg;
591 int err;
592
593 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
594 if (err)
595 return err;
596
597 reg &= ~PORT_CONTROL_2_8021Q_MASK;
598 reg |= mode & PORT_CONTROL_2_8021Q_MASK;
599
600 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
601 if (err)
602 return err;
603
604 netdev_dbg(chip->ds->ports[port].netdev, "802.1QMode set to %s\n",
605 mv88e6xxx_port_8021q_mode_names[mode]);
606
607 return 0;
608}
ef0a7318 609
5f436666
AL		 610int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port)
611{
612 u16 reg;
613 int err;
614
615 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
616 if (err)
617 return err;
618
619 reg |= PORT_CONTROL_2_JUMBO_10240;
620
621 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
622}
623
56995cbc
AL		 624/* Offset 0x0f: Port Ether type */
625
626int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
627 u16 etype)
628{
629 return mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, etype);
630}
631
ef0a7318
AL		 632/* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
633 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
634 */
635
636int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
637{
638 int err;
639
640 /* Use a direct priority mapping for all IEEE tagged frames */
641 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, 0x3210);
642 if (err)
643 return err;
644
645 return mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, 0x7654);
646}
647
648static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
649 int port, u16 table,
650 u8 pointer, u16 data)
651{
652 u16 reg;
653
654 reg = PORT_IEEE_PRIO_MAP_TABLE_UPDATE |
655 table |
656 (pointer << PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT) |
657 data;
658
659 return mv88e6xxx_port_write(chip, port, PORT_IEEE_PRIO_MAP_TABLE, reg);
660}
661
662int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
663{
664 int err, i;
665
666 for (i = 0; i <= 7; i++) {
667 err = mv88e6xxx_port_ieeepmt_write(
668 chip, port, PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP,
669 i, (i | i << 4));
670 if (err)
671 return err;
672
673 err = mv88e6xxx_port_ieeepmt_write(
674 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP,
675 i, i);
676 if (err)
677 return err;
678
679 err = mv88e6xxx_port_ieeepmt_write(
680 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP,
681 i, i);
682 if (err)
683 return err;
684
685 err = mv88e6xxx_port_ieeepmt_write(
686 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP,
687 i, i);
688 if (err)
689 return err;
690 }
691
692 return 0;
693}
Linux 6.x block layer and io_uring tree(s)