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Merge tag 'for-linus-4.18-ofs' of git://git.kernel.org/pub/scm/linux/kernel/git/hubca...
[linux-2.6-block.git] / drivers / net / dsa / mv88e6xxx / global1.c
CommitLineData
a935c052
VD		 1/*
2 * Marvell 88E6xxx Switch Global (1) Registers support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
4333d619
VD		 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
a935c052
VD		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
101515c8
VD		 15#include <linux/bitfield.h>
16
4d5f2ba7 17#include "chip.h"
a935c052
VD		 18#include "global1.h"
19
20int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
21{
22 int addr = chip->info->global1_addr;
23
24 return mv88e6xxx_read(chip, addr, reg, val);
25}
26
27int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
28{
29 int addr = chip->info->global1_addr;
30
31 return mv88e6xxx_write(chip, addr, reg, val);
32}
33
34int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
35{
36 return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask);
37}
a605a0fe 38
17e708ba
VD		 39/* Offset 0x00: Switch Global Status Register */
40
a199d8b6
VD		 41static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
42{
43 u16 state;
44 int i, err;
45
46 for (i = 0; i < 16; i++) {
82466921 47 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
a199d8b6
VD		 48 if (err)
49 return err;
50
51 /* Check the value of the PPUState bits 15:14 */
82466921
VD		 52 state &= MV88E6185_G1_STS_PPU_STATE_MASK;
53 if (state != MV88E6185_G1_STS_PPU_STATE_POLLING)
a199d8b6
VD		 54 return 0;
55
56 usleep_range(1000, 2000);
57 }
58
59 return -ETIMEDOUT;
60}
61
17e708ba
VD		 62static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
63{
64 u16 state;
65 int i, err;
66
67 for (i = 0; i < 16; ++i) {
82466921 68 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
17e708ba
VD		 69 if (err)
70 return err;
71
72 /* Check the value of the PPUState bits 15:14 */
82466921
VD		 73 state &= MV88E6185_G1_STS_PPU_STATE_MASK;
74 if (state == MV88E6185_G1_STS_PPU_STATE_POLLING)
17e708ba
VD		 75 return 0;
76
77 usleep_range(1000, 2000);
78 }
79
80 return -ETIMEDOUT;
81}
82
83static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
84{
85 u16 state;
86 int i, err;
87
88 for (i = 0; i < 16; ++i) {
82466921 89 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
17e708ba
VD		 90 if (err)
91 return err;
92
93 /* Check the value of the PPUState (or InitState) bit 15 */
82466921 94 if (state & MV88E6352_G1_STS_PPU_STATE)
17e708ba
VD		 95 return 0;
96
97 usleep_range(1000, 2000);
98 }
99
100 return -ETIMEDOUT;
101}
102
103static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
104{
105 const unsigned long timeout = jiffies + 1 * HZ;
106 u16 val;
107 int err;
108
109 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11
110 * is set to a one when all units inside the device (ATU, VTU, etc.)
111 * have finished their initialization and are ready to accept frames.
112 */
113 while (time_before(jiffies, timeout)) {
82466921 114 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
17e708ba
VD		 115 if (err)
116 return err;
117
82466921 118 if (val & MV88E6XXX_G1_STS_INIT_READY)
17e708ba
VD		 119 break;
120
121 usleep_range(1000, 2000);
122 }
123
124 if (time_after(jiffies, timeout))
125 return -ETIMEDOUT;
126
127 return 0;
128}
129
4b0c4817
VD		 130/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
131 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
132 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
133 */
134int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
135{
136 u16 reg;
137 int err;
138
139 reg = (addr[0] << 8) | addr[1];
140 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
141 if (err)
142 return err;
143
144 reg = (addr[2] << 8) | addr[3];
145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
146 if (err)
147 return err;
148
149 reg = (addr[4] << 8) | addr[5];
150 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
151 if (err)
152 return err;
153
154 return 0;
155}
156
17e708ba
VD		 157/* Offset 0x04: Switch Global Control Register */
158
159int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
160{
161 u16 val;
162 int err;
163
164 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
165 * the PPU, including re-doing PHY detection and initialization
166 */
d77f4321 167 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
17e708ba
VD		 168 if (err)
169 return err;
170
d77f4321
VD		 171 val |= MV88E6XXX_G1_CTL1_SW_RESET;
172 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
17e708ba 173
d77f4321 174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
17e708ba
VD		 175 if (err)
176 return err;
177
178 err = mv88e6xxx_g1_wait_init_ready(chip);
179 if (err)
180 return err;
181
182 return mv88e6185_g1_wait_ppu_polling(chip);
183}
184
185int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
186{
187 u16 val;
188 int err;
189
190 /* Set the SWReset bit 15 */
d77f4321 191 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
17e708ba
VD		 192 if (err)
193 return err;
194
d77f4321 195 val |= MV88E6XXX_G1_CTL1_SW_RESET;
17e708ba 196
d77f4321 197 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
17e708ba
VD		 198 if (err)
199 return err;
200
201 err = mv88e6xxx_g1_wait_init_ready(chip);
202 if (err)
203 return err;
204
205 return mv88e6352_g1_wait_ppu_polling(chip);
206}
207
a199d8b6
VD		 208int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
209{
210 u16 val;
211 int err;
212
d77f4321 213 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
a199d8b6
VD		 214 if (err)
215 return err;
216
d77f4321 217 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
a199d8b6 218
d77f4321 219 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
a199d8b6
VD		 220 if (err)
221 return err;
222
223 return mv88e6185_g1_wait_ppu_polling(chip);
224}
225
226int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
227{
228 u16 val;
229 int err;
230
d77f4321 231 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
a199d8b6
VD		 232 if (err)
233 return err;
234
d77f4321 235 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
a199d8b6 236
d77f4321 237 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
a199d8b6
VD		 238 if (err)
239 return err;
240
241 return mv88e6185_g1_wait_ppu_disabled(chip);
242}
243
93e18d61
VD		 244/* Offset 0x10: IP-PRI Mapping Register 0
245 * Offset 0x11: IP-PRI Mapping Register 1
246 * Offset 0x12: IP-PRI Mapping Register 2
247 * Offset 0x13: IP-PRI Mapping Register 3
248 * Offset 0x14: IP-PRI Mapping Register 4
249 * Offset 0x15: IP-PRI Mapping Register 5
250 * Offset 0x16: IP-PRI Mapping Register 6
251 * Offset 0x17: IP-PRI Mapping Register 7
252 */
253
254int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
255{
256 int err;
257
258 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
259 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
260 if (err)
261 return err;
262
263 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
264 if (err)
265 return err;
266
267 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
268 if (err)
269 return err;
270
271 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
272 if (err)
273 return err;
274
275 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
276 if (err)
277 return err;
278
279 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
280 if (err)
281 return err;
282
283 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
284 if (err)
285 return err;
286
287 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
288 if (err)
289 return err;
290
291 return 0;
292}
293
294/* Offset 0x18: IEEE-PRI Register */
295
296int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
297{
298 /* Reset the IEEE Tag priorities to defaults */
299 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
300}
301
33641994
AL		 302/* Offset 0x1a: Monitor Control */
303/* Offset 0x1a: Monitor & MGMT Control on some devices */
304
305int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
306{
307 u16 reg;
308 int err;
309
101515c8 310 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, &reg);
33641994
AL		 311 if (err)
312 return err;
313
101515c8
VD		 314 reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
315 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
33641994 316
101515c8
VD		 317 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
318 port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
33641994 319
101515c8 320 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
33641994
AL		 321}
322
323/* Older generations also call this the ARP destination. It has been
324 * generalized in more modern devices such that more than ARP can
325 * egress it
326 */
327int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
328{
329 u16 reg;
330 int err;
331
101515c8 332 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, &reg);
33641994
AL		 333 if (err)
334 return err;
335
101515c8
VD		 336 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
337 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
33641994 338
101515c8 339 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
33641994
AL		 340}
341
342static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
343 u16 pointer, u8 data)
344{
345 u16 reg;
346
101515c8 347 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
33641994 348
101515c8 349 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
33641994
AL		 350}
351
352int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
353{
101515c8 354 u16 ptr;
33641994
AL		 355 int err;
356
101515c8
VD		 357 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
358 err = mv88e6390_g1_monitor_write(chip, ptr, port);
33641994
AL		 359 if (err)
360 return err;
361
101515c8
VD		 362 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
363 err = mv88e6390_g1_monitor_write(chip, ptr, port);
364 if (err)
365 return err;
366
367 return 0;
33641994
AL		 368}
369
370int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
371{
101515c8
VD		 372 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
373
374 return mv88e6390_g1_monitor_write(chip, ptr, port);
33641994
AL		 375}
376
6e55f698
AL		 377int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
378{
101515c8 379 u16 ptr;
6e55f698
AL		 380 int err;
381
382 /* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */
101515c8
VD		 383 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO;
384 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
6e55f698
AL		 385 if (err)
386 return err;
387
388 /* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */
101515c8
VD		 389 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI;
390 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
6e55f698
AL		 391 if (err)
392 return err;
393
394 /* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */
101515c8
VD		 395 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO;
396 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
6e55f698
AL		 397 if (err)
398 return err;
399
400 /* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */
101515c8
VD		 401 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI;
402 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
403 if (err)
404 return err;
405
406 return 0;
6e55f698
AL		 407}
408
de227387
AL		 409/* Offset 0x1c: Global Control 2 */
410
02317e68
VD		 411static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
412 u16 val)
413{
414 u16 reg;
415 int err;
416
417 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, &reg);
418 if (err)
419 return err;
420
421 reg &= ~mask;
422 reg |= val & mask;
423
424 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
425}
426
427int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
428{
429 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
430
431 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
432}
433
9e5baf9b
VD		 434int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
435{
436 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
437 MV88E6085_G1_CTL2_RM_ENABLE, 0);
438}
439
440int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
441{
442 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
443 MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
444}
445
446int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
447{
448 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
449 MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
450}
451
de227387
AL		 452int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
453{
408d2deb
VD		 454 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
455 MV88E6390_G1_CTL2_HIST_MODE_RX |
456 MV88E6390_G1_CTL2_HIST_MODE_TX);
de227387
AL		 457}
458
23c98919
VD		 459int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
460{
461 return mv88e6xxx_g1_ctl2_mask(chip,
462 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
463 index);
464}
465
de227387
AL		 466/* Offset 0x1d: Statistics Operation 2 */
467
7f9ef3af 468int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
a605a0fe 469{
57d1ef38
VD		 470 return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP,
471 MV88E6XXX_G1_STATS_OP_BUSY);
a605a0fe
AL		 472}
473
40cff8fc
AL		 474int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
475{
476 u16 val;
477 int err;
478
479 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
480 if (err)
481 return err;
482
483 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
484
485 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
486
487 return err;
488}
489
a605a0fe
AL		 490int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
491{
492 int err;
493
494 /* Snapshot the hardware statistics counters for this port. */
57d1ef38
VD		 495 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
496 MV88E6XXX_G1_STATS_OP_BUSY |
497 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
498 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
a605a0fe
AL		 499 if (err)
500 return err;
501
502 /* Wait for the snapshotting to complete. */
503 return mv88e6xxx_g1_stats_wait(chip);
504}
505
506int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
507{
508 port = (port + 1) << 5;
509
510 return mv88e6xxx_g1_stats_snapshot(chip, port);
511}
79523473
AL		 512
513int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
514{
515 int err;
516
517 port = (port + 1) << 5;
518
519 /* Snapshot the hardware statistics counters for this port. */
57d1ef38
VD		 520 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
521 MV88E6XXX_G1_STATS_OP_BUSY |
522 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
79523473
AL		 523 if (err)
524 return err;
525
526 /* Wait for the snapshotting to complete. */
527 return mv88e6xxx_g1_stats_wait(chip);
528}
7f9ef3af
AL		 529
530void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
531{
532 u32 value;
533 u16 reg;
534 int err;
535
536 *val = 0;
537
57d1ef38
VD		 538 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
539 MV88E6XXX_G1_STATS_OP_BUSY |
540 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
7f9ef3af
AL		 541 if (err)
542 return;
543
544 err = mv88e6xxx_g1_stats_wait(chip);
545 if (err)
546 return;
547
57d1ef38 548 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, &reg);
7f9ef3af
AL		 549 if (err)
550 return;
551
552 value = reg << 16;
553
57d1ef38 554 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, &reg);
7f9ef3af
AL		 555 if (err)
556 return;
557
558 *val = value | reg;
559}
40cff8fc
AL		 560
561int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
562{
563 int err;
564 u16 val;
565
566 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
567 if (err)
568 return err;
569
570 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
571
572 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
573 if (err)
574 return err;
575
576 /* Wait for the flush to complete. */
577 return mv88e6xxx_g1_stats_wait(chip);
578}
Linux 6.x block layer and io_uring tree(s)