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net: dsa: keep the bridge_dev and bridge_num as part of the same structure
[linux-block.git] / drivers / net / dsa / mv88e6xxx / chip.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
91da11f8 2/*
0d3cd4b6
VD		 3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
91da11f8
LB		 5 * Copyright (c) 2008 Marvell Semiconductor
6 *
14c7b3c3
AL		 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
4333d619
VD		 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
91da11f8
LB		 11 */
12
19fb7f69 13#include <linux/bitfield.h>
19b2f97e 14#include <linux/delay.h>
5bded825 15#include <linux/dsa/mv88e6xxx.h>
defb05b9 16#include <linux/etherdevice.h>
dea87024 17#include <linux/ethtool.h>
facd95b2 18#include <linux/if_bridge.h>
dc30c35b
AL		 19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
19b2f97e 22#include <linux/jiffies.h>
91da11f8 23#include <linux/list.h>
14c7b3c3 24#include <linux/mdio.h>
2bbba277 25#include <linux/module.h>
caac8545 26#include <linux/of_device.h>
dc30c35b 27#include <linux/of_irq.h>
b516d453 28#include <linux/of_mdio.h>
877b7cb0 29#include <linux/platform_data/mv88e6xxx.h>
91da11f8 30#include <linux/netdevice.h>
c8c1b39a 31#include <linux/gpio/consumer.h>
c9a2356f 32#include <linux/phylink.h>
c8f0b869 33#include <net/dsa.h>
ec561276 34
4d5f2ba7 35#include "chip.h"
9dd43aa2 36#include "devlink.h"
a935c052 37#include "global1.h"
ec561276 38#include "global2.h"
c6fe0ad2 39#include "hwtstamp.h"
10fa5bfc 40#include "phy.h"
18abed21 41#include "port.h"
2fa8d3af 42#include "ptp.h"
6d91782f 43#include "serdes.h"
e7ba0fad 44#include "smi.h"
91da11f8 45
fad09c73 46static void assert_reg_lock(struct mv88e6xxx_chip *chip)
3996a4ff 47{
fad09c73
VD		 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
3996a4ff
VD		 50 dump_stack();
51 }
52}
53
ec561276 54int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
914b32f6
VD		 55{
56 int err;
57
fad09c73 58 assert_reg_lock(chip);
914b32f6 59
fad09c73 60 err = mv88e6xxx_smi_read(chip, addr, reg, val);
914b32f6
VD		 61 if (err)
62 return err;
63
fad09c73 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
914b32f6
VD		 65 addr, reg, *val);
66
67 return 0;
68}
69
ec561276 70int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
91da11f8 71{
914b32f6
VD		 72 int err;
73
fad09c73 74 assert_reg_lock(chip);
91da11f8 75
fad09c73 76 err = mv88e6xxx_smi_write(chip, addr, reg, val);
914b32f6
VD		 77 if (err)
78 return err;
79
fad09c73 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 81 addr, reg, val);
82
914b32f6
VD		 83 return 0;
84}
85
683f2244
VD		 86int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88{
89 u16 data;
90 int err;
91 int i;
92
93 /* There's no bus specific operation to wait for a mask */
94 for (i = 0; i < 16; i++) {
95 err = mv88e6xxx_read(chip, addr, reg, &data);
96 if (err)
97 return err;
98
99 if ((data & mask) == val)
100 return 0;
101
102 usleep_range(1000, 2000);
103 }
104
105 dev_err(chip->dev, "Timeout while waiting for switch\n");
106 return -ETIMEDOUT;
107}
108
19fb7f69
VD		 109int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
110 int bit, int val)
111{
112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
113 val ? BIT(bit) : 0x0000);
114}
115
10fa5bfc 116struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
a3c53be5
AL		 117{
118 struct mv88e6xxx_mdio_bus *mdio_bus;
119
120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
121 list);
122 if (!mdio_bus)
123 return NULL;
124
125 return mdio_bus->bus;
126}
127
dc30c35b
AL		 128static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
129{
130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
131 unsigned int n = d->hwirq;
132
133 chip->g1_irq.masked |= (1 << n);
134}
135
136static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
137{
138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
139 unsigned int n = d->hwirq;
140
141 chip->g1_irq.masked &= ~(1 << n);
142}
143
294d711e 144static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
dc30c35b 145{
dc30c35b
AL		 146 unsigned int nhandled = 0;
147 unsigned int sub_irq;
148 unsigned int n;
149 u16 reg;
7c0db24c 150 u16 ctl1;
dc30c35b
AL		 151 int err;
152
c9acece0 153 mv88e6xxx_reg_lock(chip);
82466921 154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
c9acece0 155 mv88e6xxx_reg_unlock(chip);
dc30c35b
AL		 156
157 if (err)
158 goto out;
159
7c0db24c
JDA		 160 do {
161 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
162 if (reg & (1 << n)) {
163 sub_irq = irq_find_mapping(chip->g1_irq.domain,
164 n);
165 handle_nested_irq(sub_irq);
166 ++nhandled;
167 }
dc30c35b 168 }
7c0db24c 169
c9acece0 170 mv88e6xxx_reg_lock(chip);
7c0db24c
JDA		 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
172 if (err)
173 goto unlock;
174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
175unlock:
c9acece0 176 mv88e6xxx_reg_unlock(chip);
7c0db24c
JDA		 177 if (err)
178 goto out;
179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
180 } while (reg & ctl1);
181
dc30c35b
AL		 182out:
183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
184}
185
294d711e
AL		 186static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
187{
188 struct mv88e6xxx_chip *chip = dev_id;
189
190 return mv88e6xxx_g1_irq_thread_work(chip);
191}
192
dc30c35b
AL		 193static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
194{
195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
196
c9acece0 197 mv88e6xxx_reg_lock(chip);
dc30c35b
AL		 198}
199
200static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
201{
202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
204 u16 reg;
205 int err;
206
d77f4321 207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
dc30c35b
AL		 208 if (err)
209 goto out;
210
211 reg &= ~mask;
212 reg |= (~chip->g1_irq.masked & mask);
213
d77f4321 214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
dc30c35b
AL		 215 if (err)
216 goto out;
217
218out:
c9acece0 219 mv88e6xxx_reg_unlock(chip);
dc30c35b
AL		 220}
221
6eb15e21 222static const struct irq_chip mv88e6xxx_g1_irq_chip = {
dc30c35b
AL		 223 .name = "mv88e6xxx-g1",
224 .irq_mask = mv88e6xxx_g1_irq_mask,
225 .irq_unmask = mv88e6xxx_g1_irq_unmask,
226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
228};
229
230static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
231 unsigned int irq,
232 irq_hw_number_t hwirq)
233{
234 struct mv88e6xxx_chip *chip = d->host_data;
235
236 irq_set_chip_data(irq, d->host_data);
237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
238 irq_set_noprobe(irq);
239
240 return 0;
241}
242
243static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
244 .map = mv88e6xxx_g1_irq_domain_map,
245 .xlate = irq_domain_xlate_twocell,
246};
247
3d82475a 248/* To be called with reg_lock held */
294d711e 249static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
dc30c35b
AL		 250{
251 int irq, virq;
3460a577
AL		 252 u16 mask;
253
d77f4321 254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
3d5fdba1 255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3460a577 257
5edef2f2 258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
a3db3d3a 259 virq = irq_find_mapping(chip->g1_irq.domain, irq);
dc30c35b
AL		 260 irq_dispose_mapping(virq);
261 }
262
a3db3d3a 263 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 264}
265
294d711e
AL		 266static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
267{
3d82475a
UKK		 268 /*
269 * free_irq must be called without reg_lock taken because the irq
270 * handler takes this lock, too.
271 */
294d711e 272 free_irq(chip->irq, chip);
3d82475a 273
c9acece0 274 mv88e6xxx_reg_lock(chip);
3d82475a 275 mv88e6xxx_g1_irq_free_common(chip);
c9acece0 276 mv88e6xxx_reg_unlock(chip);
294d711e
AL		 277}
278
279static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
dc30c35b 280{
3dd0ef05
AL		 281 int err, irq, virq;
282 u16 reg, mask;
dc30c35b
AL		 283
284 chip->g1_irq.nirqs = chip->info->g1_irqs;
285 chip->g1_irq.domain = irq_domain_add_simple(
286 NULL, chip->g1_irq.nirqs, 0,
287 &mv88e6xxx_g1_irq_domain_ops, chip);
288 if (!chip->g1_irq.domain)
289 return -ENOMEM;
290
291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
292 irq_create_mapping(chip->g1_irq.domain, irq);
293
294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
295 chip->g1_irq.masked = ~0;
296
d77f4321 297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
dc30c35b 298 if (err)
3dd0ef05 299 goto out_mapping;
dc30c35b 300
3dd0ef05 301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
dc30c35b 302
d77f4321 303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
dc30c35b 304 if (err)
3dd0ef05 305 goto out_disable;
dc30c35b
AL		 306
307 /* Reading the interrupt status clears (most of) them */
82466921 308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
dc30c35b 309 if (err)
3dd0ef05 310 goto out_disable;
dc30c35b 311
dc30c35b
AL		 312 return 0;
313
3dd0ef05 314out_disable:
3d5fdba1 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
d77f4321 316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
3dd0ef05
AL		 317
318out_mapping:
319 for (irq = 0; irq < 16; irq++) {
320 virq = irq_find_mapping(chip->g1_irq.domain, irq);
321 irq_dispose_mapping(virq);
322 }
323
324 irq_domain_remove(chip->g1_irq.domain);
dc30c35b
AL		 325
326 return err;
327}
328
294d711e
AL		 329static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
330{
f6d9758b
AL		 331 static struct lock_class_key lock_key;
332 static struct lock_class_key request_key;
294d711e
AL		 333 int err;
334
335 err = mv88e6xxx_g1_irq_setup_common(chip);
336 if (err)
337 return err;
338
f6d9758b
AL		 339 /* These lock classes tells lockdep that global 1 irqs are in
340 * a different category than their parent GPIO, so it won't
341 * report false recursion.
342 */
343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
344
3095383a
AL		 345 snprintf(chip->irq_name, sizeof(chip->irq_name),
346 "mv88e6xxx-%s", dev_name(chip->dev));
347
c9acece0 348 mv88e6xxx_reg_unlock(chip);
294d711e
AL		 349 err = request_threaded_irq(chip->irq, NULL,
350 mv88e6xxx_g1_irq_thread_fn,
0340376e 351 IRQF_ONESHOT | IRQF_SHARED,
3095383a 352 chip->irq_name, chip);
c9acece0 353 mv88e6xxx_reg_lock(chip);
294d711e
AL		 354 if (err)
355 mv88e6xxx_g1_irq_free_common(chip);
356
357 return err;
358}
359
360static void mv88e6xxx_irq_poll(struct kthread_work *work)
361{
362 struct mv88e6xxx_chip *chip = container_of(work,
363 struct mv88e6xxx_chip,
364 irq_poll_work.work);
365 mv88e6xxx_g1_irq_thread_work(chip);
366
367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
368 msecs_to_jiffies(100));
369}
370
371static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
372{
373 int err;
374
375 err = mv88e6xxx_g1_irq_setup_common(chip);
376 if (err)
377 return err;
378
379 kthread_init_delayed_work(&chip->irq_poll_work,
380 mv88e6xxx_irq_poll);
381
3f8b8696 382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
294d711e
AL		 383 if (IS_ERR(chip->kworker))
384 return PTR_ERR(chip->kworker);
385
386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
387 msecs_to_jiffies(100));
388
389 return 0;
390}
391
392static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
393{
394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
395 kthread_destroy_worker(chip->kworker);
3d82475a 396
c9acece0 397 mv88e6xxx_reg_lock(chip);
3d82475a 398 mv88e6xxx_g1_irq_free_common(chip);
c9acece0 399 mv88e6xxx_reg_unlock(chip);
294d711e
AL		 400}
401
64d47d50
RK		 402static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
403 int port, phy_interface_t interface)
404{
405 int err;
406
407 if (chip->info->ops->port_set_rgmii_delay) {
408 err = chip->info->ops->port_set_rgmii_delay(chip, port,
409 interface);
410 if (err && err != -EOPNOTSUPP)
411 return err;
412 }
413
414 if (chip->info->ops->port_set_cmode) {
415 err = chip->info->ops->port_set_cmode(chip, port,
416 interface);
417 if (err && err != -EOPNOTSUPP)
418 return err;
419 }
420
421 return 0;
422}
423
a5a6858b
RK		 424static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
425 int link, int speed, int duplex, int pause,
426 phy_interface_t mode)
d78343d2
VD		 427{
428 int err;
429
430 if (!chip->info->ops->port_set_link)
431 return 0;
432
433 /* Port's MAC control must not be changed unless the link is down */
43c8e0ae 434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
d78343d2
VD		 435 if (err)
436 return err;
437
f365c6f7
RK		 438 if (chip->info->ops->port_set_speed_duplex) {
439 err = chip->info->ops->port_set_speed_duplex(chip, port,
440 speed, duplex);
d78343d2
VD		 441 if (err && err != -EOPNOTSUPP)
442 goto restore_link;
443 }
444
7cbbee05
AL		 445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
446 mode = chip->info->ops->port_max_speed_mode(port);
447
54186b91
AL		 448 if (chip->info->ops->port_set_pause) {
449 err = chip->info->ops->port_set_pause(chip, port, pause);
450 if (err)
451 goto restore_link;
452 }
453
64d47d50 454 err = mv88e6xxx_port_config_interface(chip, port, mode);
d78343d2
VD		 455restore_link:
456 if (chip->info->ops->port_set_link(chip, port, link))
774439e5 457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
d78343d2
VD		 458
459 return err;
460}
461
d700ec41
MV		 462static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
463{
464 struct mv88e6xxx_chip *chip = ds->priv;
465
466 return port < chip->info->num_internal_phys;
467}
468
5d5b231d
RK		 469static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
470{
471 u16 reg;
472 int err;
473
474 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
475 if (err) {
476 dev_err(chip->dev,
477 "p%d: %s: failed to read port status\n",
478 port, __func__);
479 return err;
480 }
481
482 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
483}
484
a5a6858b
RK		 485static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
486 struct phylink_link_state *state)
487{
488 struct mv88e6xxx_chip *chip = ds->priv;
193c5b26 489 int lane;
a5a6858b
RK		 490 int err;
491
492 mv88e6xxx_reg_lock(chip);
493 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 494 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
a5a6858b
RK		 495 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
496 state);
497 else
498 err = -EOPNOTSUPP;
499 mv88e6xxx_reg_unlock(chip);
500
501 return err;
502}
503
504static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
505 unsigned int mode,
506 phy_interface_t interface,
507 const unsigned long *advertise)
508{
509 const struct mv88e6xxx_ops *ops = chip->info->ops;
193c5b26 510 int lane;
a5a6858b
RK		 511
512 if (ops->serdes_pcs_config) {
513 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 514 if (lane >= 0)
a5a6858b
RK		 515 return ops->serdes_pcs_config(chip, port, lane, mode,
516 interface, advertise);
517 }
518
519 return 0;
520}
521
522static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
523{
524 struct mv88e6xxx_chip *chip = ds->priv;
525 const struct mv88e6xxx_ops *ops;
526 int err = 0;
193c5b26 527 int lane;
a5a6858b
RK		 528
529 ops = chip->info->ops;
530
531 if (ops->serdes_pcs_an_restart) {
532 mv88e6xxx_reg_lock(chip);
533 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 534 if (lane >= 0)
a5a6858b
RK		 535 err = ops->serdes_pcs_an_restart(chip, port, lane);
536 mv88e6xxx_reg_unlock(chip);
537
538 if (err)
539 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
540 }
541}
542
543static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
544 unsigned int mode,
545 int speed, int duplex)
546{
547 const struct mv88e6xxx_ops *ops = chip->info->ops;
193c5b26 548 int lane;
a5a6858b
RK		 549
550 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
551 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 552 if (lane >= 0)
a5a6858b
RK		 553 return ops->serdes_pcs_link_up(chip, port, lane,
554 speed, duplex);
555 }
556
557 return 0;
558}
559
6c422e34
RK		 560static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
561 unsigned long *mask,
562 struct phylink_link_state *state)
563{
564 if (!phy_interface_mode_is_8023z(state->interface)) {
565 /* 10M and 100M are only supported in non-802.3z mode */
566 phylink_set(mask, 10baseT_Half);
567 phylink_set(mask, 10baseT_Full);
568 phylink_set(mask, 100baseT_Half);
569 phylink_set(mask, 100baseT_Full);
570 }
571}
572
573static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
574 unsigned long *mask,
575 struct phylink_link_state *state)
576{
577 /* FIXME: if the port is in 1000Base-X mode, then it only supports
578 * 1000M FD speeds. In this case, CMODE will indicate 5.
579 */
580 phylink_set(mask, 1000baseT_Full);
581 phylink_set(mask, 1000baseX_Full);
582
583 mv88e6065_phylink_validate(chip, port, mask, state);
584}
585
e3af71a3
MB		 586static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
587 unsigned long *mask,
588 struct phylink_link_state *state)
589{
590 if (port >= 5)
591 phylink_set(mask, 2500baseX_Full);
592
593 /* No ethtool bits for 200Mbps */
594 phylink_set(mask, 1000baseT_Full);
595 phylink_set(mask, 1000baseX_Full);
596
597 mv88e6065_phylink_validate(chip, port, mask, state);
598}
599
6c422e34
RK		 600static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
601 unsigned long *mask,
602 struct phylink_link_state *state)
603{
604 /* No ethtool bits for 200Mbps */
605 phylink_set(mask, 1000baseT_Full);
606 phylink_set(mask, 1000baseX_Full);
607
608 mv88e6065_phylink_validate(chip, port, mask, state);
609}
610
611static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
612 unsigned long *mask,
613 struct phylink_link_state *state)
614{
ec26016b 615 if (port >= 9) {
6c422e34 616 phylink_set(mask, 2500baseX_Full);
ec26016b
AL		 617 phylink_set(mask, 2500baseT_Full);
618 }
6c422e34
RK		 619
620 /* No ethtool bits for 200Mbps */
621 phylink_set(mask, 1000baseT_Full);
622 phylink_set(mask, 1000baseX_Full);
623
624 mv88e6065_phylink_validate(chip, port, mask, state);
625}
626
627static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
628 unsigned long *mask,
629 struct phylink_link_state *state)
630{
631 if (port >= 9) {
632 phylink_set(mask, 10000baseT_Full);
633 phylink_set(mask, 10000baseKR_Full);
634 }
635
636 mv88e6390_phylink_validate(chip, port, mask, state);
637}
638
de776d0d
PS		 639static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
640 unsigned long *mask,
641 struct phylink_link_state *state)
642{
dc2fc9f0
MB		 643 bool is_6191x =
644 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
645
646 if (((port == 0 || port == 9) && !is_6191x) || port == 10) {
de776d0d
PS		 647 phylink_set(mask, 10000baseT_Full);
648 phylink_set(mask, 10000baseKR_Full);
649 phylink_set(mask, 10000baseCR_Full);
650 phylink_set(mask, 10000baseSR_Full);
651 phylink_set(mask, 10000baseLR_Full);
652 phylink_set(mask, 10000baseLRM_Full);
653 phylink_set(mask, 10000baseER_Full);
654 phylink_set(mask, 5000baseT_Full);
655 phylink_set(mask, 2500baseX_Full);
656 phylink_set(mask, 2500baseT_Full);
657 }
658
659 phylink_set(mask, 1000baseT_Full);
660 phylink_set(mask, 1000baseX_Full);
661
662 mv88e6065_phylink_validate(chip, port, mask, state);
663}
664
c9a2356f
RK		 665static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
666 unsigned long *supported,
667 struct phylink_link_state *state)
668{
6c422e34
RK		 669 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
670 struct mv88e6xxx_chip *chip = ds->priv;
671
672 /* Allow all the expected bits */
673 phylink_set(mask, Autoneg);
674 phylink_set(mask, Pause);
675 phylink_set_port_modes(mask);
676
677 if (chip->info->ops->phylink_validate)
678 chip->info->ops->phylink_validate(chip, port, mask, state);
679
4973056c
SA		 680 linkmode_and(supported, supported, mask);
681 linkmode_and(state->advertising, state->advertising, mask);
6c422e34
RK		 682
683 /* We can only operate at 2500BaseX or 1000BaseX. If requested
684 * to advertise both, only report advertising at 2500BaseX.
685 */
686 phylink_helper_basex_speed(state);
c9a2356f
RK		 687}
688
c9a2356f
RK		 689static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
690 unsigned int mode,
691 const struct phylink_link_state *state)
692{
693 struct mv88e6xxx_chip *chip = ds->priv;
fad58190 694 struct mv88e6xxx_port *p;
64d47d50 695 int err;
c9a2356f 696
fad58190
RK		 697 p = &chip->ports[port];
698
64d47d50
RK		 699 /* FIXME: is this the correct test? If we're in fixed mode on an
700 * internal port, why should we process this any different from
701 * PHY mode? On the other hand, the port may be automedia between
702 * an internal PHY and the serdes...
703 */
d700ec41 704 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
c9a2356f
RK		 705 return;
706
c9acece0 707 mv88e6xxx_reg_lock(chip);
fad58190
RK		 708 /* In inband mode, the link may come up at any time while the link
709 * is not forced down. Force the link down while we reconfigure the
710 * interface mode.
64d47d50 711 */
fad58190
RK		 712 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
713 chip->info->ops->port_set_link)
714 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
715
64d47d50 716 err = mv88e6xxx_port_config_interface(chip, port, state->interface);
a5a6858b
RK		 717 if (err && err != -EOPNOTSUPP)
718 goto err_unlock;
719
720 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
721 state->advertising);
722 /* FIXME: we should restart negotiation if something changed - which
723 * is something we get if we convert to using phylinks PCS operations.
724 */
725 if (err > 0)
726 err = 0;
727
fad58190
RK		 728 /* Undo the forced down state above after completing configuration
729 * irrespective of its state on entry, which allows the link to come up.
730 */
731 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
732 chip->info->ops->port_set_link)
733 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
734
735 p->interface = state->interface;
736
a5a6858b 737err_unlock:
c9acece0 738 mv88e6xxx_reg_unlock(chip);
c9a2356f
RK		 739
740 if (err && err != -EOPNOTSUPP)
64d47d50 741 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
c9a2356f
RK		 742}
743
30c4a5b0
RK		 744static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
745 unsigned int mode,
746 phy_interface_t interface)
c9a2356f
RK		 747{
748 struct mv88e6xxx_chip *chip = ds->priv;
30c4a5b0
RK		 749 const struct mv88e6xxx_ops *ops;
750 int err = 0;
c9a2356f 751
30c4a5b0 752 ops = chip->info->ops;
c9a2356f 753
5d5b231d 754 mv88e6xxx_reg_lock(chip);
4a3e0aed
MZ		 755 /* Internal PHYs propagate their configuration directly to the MAC.
756 * External PHYs depend on whether the PPU is enabled for this port.
757 */
758 if (((!mv88e6xxx_phy_is_internal(ds, port) &&
759 !mv88e6xxx_port_ppu_updates(chip, port)) ||
4efe7662
CP		 760 mode == MLO_AN_FIXED) && ops->port_sync_link)
761 err = ops->port_sync_link(chip, port, mode, false);
5d5b231d 762 mv88e6xxx_reg_unlock(chip);
c9a2356f 763
5d5b231d
RK		 764 if (err)
765 dev_err(chip->dev,
766 "p%d: failed to force MAC link down\n", port);
c9a2356f
RK		 767}
768
769static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
770 unsigned int mode, phy_interface_t interface,
5b502a7b
RK		 771 struct phy_device *phydev,
772 int speed, int duplex,
773 bool tx_pause, bool rx_pause)
c9a2356f 774{
30c4a5b0
RK		 775 struct mv88e6xxx_chip *chip = ds->priv;
776 const struct mv88e6xxx_ops *ops;
777 int err = 0;
778
779 ops = chip->info->ops;
780
5d5b231d 781 mv88e6xxx_reg_lock(chip);
4a3e0aed
MZ		 782 /* Internal PHYs propagate their configuration directly to the MAC.
783 * External PHYs depend on whether the PPU is enabled for this port.
784 */
785 if ((!mv88e6xxx_phy_is_internal(ds, port) &&
786 !mv88e6xxx_port_ppu_updates(chip, port)) ||
787 mode == MLO_AN_FIXED) {
30c4a5b0
RK		 788 /* FIXME: for an automedia port, should we force the link
789 * down here - what if the link comes up due to "other" media
790 * while we're bringing the port up, how is the exclusivity
a5a6858b 791 * handled in the Marvell hardware? E.g. port 2 on 88E6390
30c4a5b0
RK		 792 * shared between internal PHY and Serdes.
793 */
a5a6858b
RK		 794 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
795 duplex);
796 if (err)
797 goto error;
798
f365c6f7
RK		 799 if (ops->port_set_speed_duplex) {
800 err = ops->port_set_speed_duplex(chip, port,
801 speed, duplex);
30c4a5b0
RK		 802 if (err && err != -EOPNOTSUPP)
803 goto error;
804 }
805
4efe7662
CP		 806 if (ops->port_sync_link)
807 err = ops->port_sync_link(chip, port, mode, true);
5d5b231d 808 }
30c4a5b0 809error:
5d5b231d 810 mv88e6xxx_reg_unlock(chip);
30c4a5b0 811
5d5b231d
RK		 812 if (err && err != -EOPNOTSUPP)
813 dev_err(ds->dev,
814 "p%d: failed to configure MAC link up\n", port);
c9a2356f
RK		 815}
816
a605a0fe 817static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
91da11f8 818{
a605a0fe
AL		 819 if (!chip->info->ops->stats_snapshot)
820 return -EOPNOTSUPP;
91da11f8 821
a605a0fe 822 return chip->info->ops->stats_snapshot(chip, port);
91da11f8
LB		 823}
824
e413e7e1 825static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
dfafe449
AL		 826 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
827 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
828 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
829 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
830 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
831 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
832 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
833 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
834 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
835 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
836 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
837 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
838 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
839 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
840 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
841 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
842 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
843 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
844 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
845 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
846 { "single", 4, 0x14, STATS_TYPE_BANK0, },
847 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
848 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
849 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
850 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
851 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
852 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
853 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
854 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
855 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
856 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
857 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
858 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
859 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
860 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
861 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
862 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
863 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
864 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
865 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
866 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
867 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
868 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
869 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
870 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
871 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
872 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
873 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
874 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
875 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
876 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
877 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
878 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
879 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
880 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
881 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
882 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
883 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
884 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
e413e7e1
AL		 885};
886
fad09c73 887static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
f5e2ed02 888 struct mv88e6xxx_hw_stat *s,
e0d8b615
AL		 889 int port, u16 bank1_select,
890 u16 histogram)
80c4627b 891{
80c4627b
AL		 892 u32 low;
893 u32 high = 0;
dfafe449 894 u16 reg = 0;
0e7b9925 895 int err;
80c4627b
AL		 896 u64 value;
897
f5e2ed02 898 switch (s->type) {
dfafe449 899 case STATS_TYPE_PORT:
0e7b9925
AL		 900 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
901 if (err)
6c3442f5 902 return U64_MAX;
80c4627b 903
0e7b9925 904 low = reg;
cda9f4aa 905 if (s->size == 4) {
0e7b9925
AL		 906 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
907 if (err)
6c3442f5 908 return U64_MAX;
84b3fd1f 909 low |= ((u32)reg) << 16;
80c4627b 910 }
f5e2ed02 911 break;
dfafe449 912 case STATS_TYPE_BANK1:
e0d8b615 913 reg = bank1_select;
df561f66 914 fallthrough;
dfafe449 915 case STATS_TYPE_BANK0:
e0d8b615 916 reg |= s->reg | histogram;
7f9ef3af 917 mv88e6xxx_g1_stats_read(chip, reg, &low);
cda9f4aa 918 if (s->size == 8)
7f9ef3af 919 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
9fc3e4dc
GS		 920 break;
921 default:
6c3442f5 922 return U64_MAX;
80c4627b 923 }
6e46e2d8 924 value = (((u64)high) << 32) | low;
80c4627b
AL		 925 return value;
926}
927
436fe17d
AL		 928static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
929 uint8_t *data, int types)
91da11f8 930{
f5e2ed02
AL		 931 struct mv88e6xxx_hw_stat *stat;
932 int i, j;
91da11f8 933
f5e2ed02
AL		 934 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
935 stat = &mv88e6xxx_hw_stats[i];
dfafe449 936 if (stat->type & types) {
f5e2ed02
AL		 937 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
938 ETH_GSTRING_LEN);
939 j++;
940 }
91da11f8 941 }
436fe17d
AL		 942
943 return j;
e413e7e1
AL		 944}
945
436fe17d
AL		 946static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
947 uint8_t *data)
dfafe449 948{
436fe17d
AL		 949 return mv88e6xxx_stats_get_strings(chip, data,
950 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
dfafe449
AL		 951}
952
1f71836f
RV		 953static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
954 uint8_t *data)
955{
956 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
957}
958
436fe17d
AL		 959static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
960 uint8_t *data)
dfafe449 961{
436fe17d
AL		 962 return mv88e6xxx_stats_get_strings(chip, data,
963 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
dfafe449
AL		 964}
965
65f60e45
AL		 966static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
967 "atu_member_violation",
968 "atu_miss_violation",
969 "atu_full_violation",
970 "vtu_member_violation",
971 "vtu_miss_violation",
972};
973
974static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
975{
976 unsigned int i;
977
978 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
979 strlcpy(data + i * ETH_GSTRING_LEN,
980 mv88e6xxx_atu_vtu_stats_strings[i],
981 ETH_GSTRING_LEN);
982}
983
dfafe449 984static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
89f09048 985 u32 stringset, uint8_t *data)
e413e7e1 986{
04bed143 987 struct mv88e6xxx_chip *chip = ds->priv;
436fe17d 988 int count = 0;
dfafe449 989
89f09048
FF		 990 if (stringset != ETH_SS_STATS)
991 return;
992
c9acece0 993 mv88e6xxx_reg_lock(chip);
c6c8cd5e 994
dfafe449 995 if (chip->info->ops->stats_get_strings)
436fe17d
AL		 996 count = chip->info->ops->stats_get_strings(chip, data);
997
998 if (chip->info->ops->serdes_get_strings) {
999 data += count * ETH_GSTRING_LEN;
65f60e45 1000 count = chip->info->ops->serdes_get_strings(chip, port, data);
436fe17d 1001 }
c6c8cd5e 1002
65f60e45
AL		 1003 data += count * ETH_GSTRING_LEN;
1004 mv88e6xxx_atu_vtu_get_strings(data);
1005
c9acece0 1006 mv88e6xxx_reg_unlock(chip);
dfafe449
AL		 1007}
1008
1009static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1010 int types)
1011{
f5e2ed02
AL		 1012 struct mv88e6xxx_hw_stat *stat;
1013 int i, j;
1014
1015 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1016 stat = &mv88e6xxx_hw_stats[i];
dfafe449 1017 if (stat->type & types)
f5e2ed02
AL		 1018 j++;
1019 }
1020 return j;
e413e7e1
AL		 1021}
1022
dfafe449
AL		 1023static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1024{
1025 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1026 STATS_TYPE_PORT);
1027}
1028
1f71836f
RV		 1029static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1030{
1031 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1032}
1033
dfafe449
AL		 1034static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1035{
1036 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1037 STATS_TYPE_BANK1);
1038}
1039
89f09048 1040static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
dfafe449
AL		 1041{
1042 struct mv88e6xxx_chip *chip = ds->priv;
436fe17d
AL		 1043 int serdes_count = 0;
1044 int count = 0;
dfafe449 1045
89f09048
FF		 1046 if (sset != ETH_SS_STATS)
1047 return 0;
1048
c9acece0 1049 mv88e6xxx_reg_lock(chip);
dfafe449 1050 if (chip->info->ops->stats_get_sset_count)
436fe17d
AL		 1051 count = chip->info->ops->stats_get_sset_count(chip);
1052 if (count < 0)
1053 goto out;
1054
1055 if (chip->info->ops->serdes_get_sset_count)
1056 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1057 port);
65f60e45 1058 if (serdes_count < 0) {
436fe17d 1059 count = serdes_count;
65f60e45
AL		 1060 goto out;
1061 }
1062 count += serdes_count;
1063 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1064
436fe17d 1065out:
c9acece0 1066 mv88e6xxx_reg_unlock(chip);
dfafe449 1067
436fe17d 1068 return count;
dfafe449
AL		 1069}
1070
436fe17d
AL		 1071static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1072 uint64_t *data, int types,
1073 u16 bank1_select, u16 histogram)
052f947f
AL		 1074{
1075 struct mv88e6xxx_hw_stat *stat;
1076 int i, j;
1077
1078 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1079 stat = &mv88e6xxx_hw_stats[i];
1080 if (stat->type & types) {
c9acece0 1081 mv88e6xxx_reg_lock(chip);
e0d8b615
AL		 1082 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1083 bank1_select,
1084 histogram);
c9acece0 1085 mv88e6xxx_reg_unlock(chip);
377cda13 1086
052f947f
AL		 1087 j++;
1088 }
1089 }
436fe17d 1090 return j;
052f947f
AL		 1091}
1092
436fe17d
AL		 1093static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1094 uint64_t *data)
052f947f
AL		 1095{
1096 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 1097 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
57d1ef38 1098 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
052f947f
AL		 1099}
1100
1f71836f
RV		 1101static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1102 uint64_t *data)
1103{
1104 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1105 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1106}
1107
436fe17d
AL		 1108static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1109 uint64_t *data)
052f947f
AL		 1110{
1111 return mv88e6xxx_stats_get_stats(chip, port, data,
e0d8b615 1112 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 1113 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1114 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
e0d8b615
AL		 1115}
1116
436fe17d
AL		 1117static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1118 uint64_t *data)
e0d8b615
AL		 1119{
1120 return mv88e6xxx_stats_get_stats(chip, port, data,
1121 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
57d1ef38
VD		 1122 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1123 0);
052f947f
AL		 1124}
1125
65f60e45
AL		 1126static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1127 uint64_t *data)
1128{
1129 *data++ = chip->ports[port].atu_member_violation;
1130 *data++ = chip->ports[port].atu_miss_violation;
1131 *data++ = chip->ports[port].atu_full_violation;
1132 *data++ = chip->ports[port].vtu_member_violation;
1133 *data++ = chip->ports[port].vtu_miss_violation;
1134}
1135
052f947f
AL		 1136static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1137 uint64_t *data)
1138{
436fe17d
AL		 1139 int count = 0;
1140
052f947f 1141 if (chip->info->ops->stats_get_stats)
436fe17d
AL		 1142 count = chip->info->ops->stats_get_stats(chip, port, data);
1143
c9acece0 1144 mv88e6xxx_reg_lock(chip);
436fe17d
AL		 1145 if (chip->info->ops->serdes_get_stats) {
1146 data += count;
65f60e45 1147 count = chip->info->ops->serdes_get_stats(chip, port, data);
436fe17d 1148 }
65f60e45
AL		 1149 data += count;
1150 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
c9acece0 1151 mv88e6xxx_reg_unlock(chip);
052f947f
AL		 1152}
1153
f81ec90f
VD		 1154static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1155 uint64_t *data)
e413e7e1 1156{
04bed143 1157 struct mv88e6xxx_chip *chip = ds->priv;
f5e2ed02 1158 int ret;
f5e2ed02 1159
c9acece0 1160 mv88e6xxx_reg_lock(chip);
f5e2ed02 1161
a605a0fe 1162 ret = mv88e6xxx_stats_snapshot(chip, port);
c9acece0 1163 mv88e6xxx_reg_unlock(chip);
377cda13
AL		 1164
1165 if (ret < 0)
f5e2ed02 1166 return;
052f947f
AL		 1167
1168 mv88e6xxx_get_stats(chip, port, data);
f5e2ed02 1169
e413e7e1
AL		 1170}
1171
f81ec90f 1172static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
a1ab91f3 1173{
0d30bbd0
AL		 1174 struct mv88e6xxx_chip *chip = ds->priv;
1175 int len;
1176
1177 len = 32 * sizeof(u16);
1178 if (chip->info->ops->serdes_get_regs_len)
1179 len += chip->info->ops->serdes_get_regs_len(chip, port);
1180
1181 return len;
a1ab91f3
GR		 1182}
1183
f81ec90f
VD		 1184static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1185 struct ethtool_regs *regs, void *_p)
a1ab91f3 1186{
04bed143 1187 struct mv88e6xxx_chip *chip = ds->priv;
0e7b9925
AL		 1188 int err;
1189 u16 reg;
a1ab91f3
GR		 1190 u16 *p = _p;
1191 int i;
1192
a5f39326 1193 regs->version = chip->info->prod_num;
a1ab91f3
GR		 1194
1195 memset(p, 0xff, 32 * sizeof(u16));
1196
c9acece0 1197 mv88e6xxx_reg_lock(chip);
23062513 1198
a1ab91f3 1199 for (i = 0; i < 32; i++) {
a1ab91f3 1200
0e7b9925
AL		 1201 err = mv88e6xxx_port_read(chip, port, i, &reg);
1202 if (!err)
1203 p[i] = reg;
a1ab91f3 1204 }
23062513 1205
0d30bbd0
AL		 1206 if (chip->info->ops->serdes_get_regs)
1207 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1208
c9acece0 1209 mv88e6xxx_reg_unlock(chip);
a1ab91f3
GR		 1210}
1211
08f50061
VD		 1212static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1213 struct ethtool_eee *e)
68b8f60c 1214{
5480db69
VD		 1215 /* Nothing to do on the port's MAC */
1216 return 0;
11b3b45d
GR		 1217}
1218
08f50061
VD		 1219static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1220 struct ethtool_eee *e)
11b3b45d 1221{
5480db69
VD		 1222 /* Nothing to do on the port's MAC */
1223 return 0;
11b3b45d
GR		 1224}
1225
9dc8b13e 1226/* Mask of the local ports allowed to receive frames from a given fabric port */
e5887a2a 1227static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
facd95b2 1228{
9dc8b13e
VD		 1229 struct dsa_switch *ds = chip->ds;
1230 struct dsa_switch_tree *dst = ds->dst;
65144067 1231 struct dsa_port *dp, *other_dp;
9dc8b13e 1232 bool found = false;
e5887a2a 1233 u16 pvlan;
b7666efe 1234
ce5df689
VO		 1235 /* dev is a physical switch */
1236 if (dev <= dst->last_switch) {
1237 list_for_each_entry(dp, &dst->ports, list) {
1238 if (dp->ds->index == dev && dp->index == port) {
1239 /* dp might be a DSA link or a user port, so it
65144067
VO		 1240 * might or might not have a bridge.
1241 * Use the "found" variable for both cases.
ce5df689 1242 */
ce5df689
VO		 1243 found = true;
1244 break;
1245 }
1246 }
1247 /* dev is a virtual bridge */
1248 } else {
1249 list_for_each_entry(dp, &dst->ports, list) {
41fb0cf1
VO		 1250 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1251
1252 if (!bridge_num)
ce5df689
VO		 1253 continue;
1254
41fb0cf1 1255 if (bridge_num + dst->last_switch != dev)
ce5df689
VO		 1256 continue;
1257
9dc8b13e
VD		 1258 found = true;
1259 break;
1260 }
1261 }
e5887a2a 1262
ce5df689 1263 /* Prevent frames from unknown switch or virtual bridge */
9dc8b13e 1264 if (!found)
e5887a2a
VD		 1265 return 0;
1266
1267 /* Frames from DSA links and CPU ports can egress any local port */
9dc8b13e 1268 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
e5887a2a
VD		 1269 return mv88e6xxx_port_mask(chip);
1270
e5887a2a
VD		 1271 pvlan = 0;
1272
1273 /* Frames from user ports can egress any local DSA links and CPU ports,
1274 * as well as any local member of their bridge group.
1275 */
65144067
VO		 1276 dsa_switch_for_each_port(other_dp, ds)
1277 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1278 other_dp->type == DSA_PORT_TYPE_DSA ||
41fb0cf1 1279 dsa_port_bridge_same(dp, other_dp))
65144067 1280 pvlan |= BIT(other_dp->index);
e5887a2a
VD		 1281
1282 return pvlan;
1283}
1284
240ea3ef 1285static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
e5887a2a
VD		 1286{
1287 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
b7666efe
VD		 1288
1289 /* prevent frames from going back out of the port they came in on */
1290 output_ports &= ~BIT(port);
facd95b2 1291
5a7921f4 1292 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
facd95b2
GR		 1293}
1294
f81ec90f
VD		 1295static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1296 u8 state)
facd95b2 1297{
04bed143 1298 struct mv88e6xxx_chip *chip = ds->priv;
553eb544 1299 int err;
facd95b2 1300
c9acece0 1301 mv88e6xxx_reg_lock(chip);
f894c29c 1302 err = mv88e6xxx_port_set_state(chip, port, state);
c9acece0 1303 mv88e6xxx_reg_unlock(chip);
553eb544
VD		 1304
1305 if (err)
774439e5 1306 dev_err(ds->dev, "p%d: failed to update state\n", port);
facd95b2
GR		 1307}
1308
93e18d61
VD		 1309static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1310{
1311 int err;
1312
1313 if (chip->info->ops->ieee_pri_map) {
1314 err = chip->info->ops->ieee_pri_map(chip);
1315 if (err)
1316 return err;
1317 }
1318
1319 if (chip->info->ops->ip_pri_map) {
1320 err = chip->info->ops->ip_pri_map(chip);
1321 if (err)
1322 return err;
1323 }
1324
1325 return 0;
1326}
1327
c7f047b6
VD		 1328static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1329{
c5f51765 1330 struct dsa_switch *ds = chip->ds;
c7f047b6
VD		 1331 int target, port;
1332 int err;
1333
1334 if (!chip->info->global2_addr)
1335 return 0;
1336
1337 /* Initialize the routing port to the 32 possible target devices */
1338 for (target = 0; target < 32; target++) {
c5f51765
VD		 1339 port = dsa_routing_port(ds, target);
1340 if (port == ds->num_ports)
1341 port = 0x1f;
c7f047b6
VD		 1342
1343 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1344 if (err)
1345 return err;
1346 }
1347
02317e68
VD		 1348 if (chip->info->ops->set_cascade_port) {
1349 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1350 err = chip->info->ops->set_cascade_port(chip, port);
1351 if (err)
1352 return err;
1353 }
1354
23c98919
VD		 1355 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1356 if (err)
1357 return err;
1358
c7f047b6
VD		 1359 return 0;
1360}
1361
b28f872d
VD		 1362static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1363{
1364 /* Clear all trunk masks and mapping */
1365 if (chip->info->global2_addr)
1366 return mv88e6xxx_g2_trunk_clear(chip);
1367
1368 return 0;
1369}
1370
9e5baf9b
VD		 1371static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1372{
1373 if (chip->info->ops->rmu_disable)
1374 return chip->info->ops->rmu_disable(chip);
1375
1376 return 0;
1377}
1378
9e907d73
VD		 1379static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1380{
1381 if (chip->info->ops->pot_clear)
1382 return chip->info->ops->pot_clear(chip);
1383
1384 return 0;
1385}
1386
51c901a7
VD		 1387static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1388{
1389 if (chip->info->ops->mgmt_rsvd2cpu)
1390 return chip->info->ops->mgmt_rsvd2cpu(chip);
1391
1392 return 0;
1393}
1394
a2ac29d2
VD		 1395static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1396{
c3a7d4ad
VD		 1397 int err;
1398
daefc943
VD		 1399 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1400 if (err)
1401 return err;
1402
49506a9b
RV		 1403 /* The chips that have a "learn2all" bit in Global1, ATU
1404 * Control are precisely those whose port registers have a
1405 * Message Port bit in Port Control 1 and hence implement
1406 * ->port_setup_message_port.
1407 */
1408 if (chip->info->ops->port_setup_message_port) {
1409 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1410 if (err)
1411 return err;
1412 }
c3a7d4ad 1413
a2ac29d2
VD		 1414 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1415}
1416
cd8da8bb
VD		 1417static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1418{
1419 int port;
1420 int err;
1421
1422 if (!chip->info->ops->irl_init_all)
1423 return 0;
1424
1425 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1426 /* Disable ingress rate limiting by resetting all per port
1427 * ingress rate limit resources to their initial state.
1428 */
1429 err = chip->info->ops->irl_init_all(chip, port);
1430 if (err)
1431 return err;
1432 }
1433
1434 return 0;
1435}
1436
04a69a17
VD		 1437static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1438{
1439 if (chip->info->ops->set_switch_mac) {
1440 u8 addr[ETH_ALEN];
1441
1442 eth_random_addr(addr);
1443
1444 return chip->info->ops->set_switch_mac(chip, addr);
1445 }
1446
1447 return 0;
1448}
1449
17a1594e
VD		 1450static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1451{
57e661aa
TW		 1452 struct dsa_switch_tree *dst = chip->ds->dst;
1453 struct dsa_switch *ds;
1454 struct dsa_port *dp;
17a1594e
VD		 1455 u16 pvlan = 0;
1456
1457 if (!mv88e6xxx_has_pvt(chip))
d14939be 1458 return 0;
17a1594e
VD		 1459
1460 /* Skip the local source device, which uses in-chip port VLAN */
57e661aa 1461 if (dev != chip->ds->index) {
aec5ac88 1462 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
17a1594e 1463
57e661aa
TW		 1464 ds = dsa_switch_find(dst->index, dev);
1465 dp = ds ? dsa_to_port(ds, port) : NULL;
1466 if (dp && dp->lag_dev) {
1467 /* As the PVT is used to limit flooding of
1468 * FORWARD frames, which use the LAG ID as the
1469 * source port, we must translate dev/port to
1470 * the special "LAG device" in the PVT, using
1471 * the LAG ID as the port number.
1472 */
78e70dbc 1473 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
57e661aa
TW		 1474 port = dsa_lag_id(dst, dp->lag_dev);
1475 }
1476 }
1477
17a1594e
VD		 1478 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1479}
1480
81228996
VD		 1481static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1482{
17a1594e
VD		 1483 int dev, port;
1484 int err;
1485
81228996
VD		 1486 if (!mv88e6xxx_has_pvt(chip))
1487 return 0;
1488
1489 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1490 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1491 */
17a1594e
VD		 1492 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1493 if (err)
1494 return err;
1495
1496 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1497 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1498 err = mv88e6xxx_pvt_map(chip, dev, port);
1499 if (err)
1500 return err;
1501 }
1502 }
1503
1504 return 0;
81228996
VD		 1505}
1506
749efcb8
VD		 1507static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1508{
1509 struct mv88e6xxx_chip *chip = ds->priv;
1510 int err;
1511
ffcec3f2
TW		 1512 if (dsa_to_port(ds, port)->lag_dev)
1513 /* Hardware is incapable of fast-aging a LAG through a
1514 * regular ATU move operation. Until we have something
1515 * more fancy in place this is a no-op.
1516 */
1517 return;
1518
c9acece0 1519 mv88e6xxx_reg_lock(chip);
e606ca36 1520 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
c9acece0 1521 mv88e6xxx_reg_unlock(chip);
749efcb8
VD		 1522
1523 if (err)
774439e5 1524 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
749efcb8
VD		 1525}
1526
b486d7c9
VD		 1527static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1528{
e545f865 1529 if (!mv88e6xxx_max_vid(chip))
b486d7c9
VD		 1530 return 0;
1531
1532 return mv88e6xxx_g1_vtu_flush(chip);
1533}
1534
34065c58
TW		 1535static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1536 struct mv88e6xxx_vtu_entry *entry)
f1394b78 1537{
34065c58
TW		 1538 int err;
1539
f1394b78
VD		 1540 if (!chip->info->ops->vtu_getnext)
1541 return -EOPNOTSUPP;
1542
34065c58
TW		 1543 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1544 entry->valid = false;
1545
1546 err = chip->info->ops->vtu_getnext(chip, entry);
1547
1548 if (entry->vid != vid)
1549 entry->valid = false;
1550
1551 return err;
f1394b78
VD		 1552}
1553
d89ef4b8
TW		 1554static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1555 int (*cb)(struct mv88e6xxx_chip *chip,
1556 const struct mv88e6xxx_vtu_entry *entry,
1557 void *priv),
1558 void *priv)
1559{
1560 struct mv88e6xxx_vtu_entry entry = {
1561 .vid = mv88e6xxx_max_vid(chip),
1562 .valid = false,
1563 };
1564 int err;
1565
1566 if (!chip->info->ops->vtu_getnext)
1567 return -EOPNOTSUPP;
1568
1569 do {
1570 err = chip->info->ops->vtu_getnext(chip, &entry);
1571 if (err)
1572 return err;
1573
1574 if (!entry.valid)
1575 break;
1576
1577 err = cb(chip, &entry, priv);
1578 if (err)
1579 return err;
1580 } while (entry.vid < mv88e6xxx_max_vid(chip));
1581
1582 return 0;
1583}
1584
0ad5daf6
VD		 1585static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1586 struct mv88e6xxx_vtu_entry *entry)
1587{
1588 if (!chip->info->ops->vtu_loadpurge)
1589 return -EOPNOTSUPP;
1590
1591 return chip->info->ops->vtu_loadpurge(chip, entry);
1592}
1593
d89ef4b8
TW		 1594static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1595 const struct mv88e6xxx_vtu_entry *entry,
1596 void *_fid_bitmap)
1597{
1598 unsigned long *fid_bitmap = _fid_bitmap;
1599
1600 set_bit(entry->fid, fid_bitmap);
1601 return 0;
1602}
1603
90b6dbdf 1604int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
3285f9e8 1605{
2db9ce1f 1606 int i, err;
90b6dbdf 1607 u16 fid;
3285f9e8
VD		 1608
1609 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1610
2db9ce1f 1611 /* Set every FID bit used by the (un)bridged ports */
370b4ffb 1612 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
90b6dbdf 1613 err = mv88e6xxx_port_get_fid(chip, i, &fid);
2db9ce1f
VD		 1614 if (err)
1615 return err;
1616
90b6dbdf 1617 set_bit(fid, fid_bitmap);
2db9ce1f
VD		 1618 }
1619
3285f9e8 1620 /* Set every FID bit used by the VLAN entries */
d89ef4b8 1621 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
90b6dbdf
AL		 1622}
1623
1624static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1625{
1626 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1627 int err;
1628
1629 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1630 if (err)
1631 return err;
1632
3285f9e8
VD		 1633 /* The reset value 0x000 is used to indicate that multiple address
1634 * databases are not needed. Return the next positive available.
1635 */
1636 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
fad09c73 1637 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
3285f9e8
VD		 1638 return -ENOSPC;
1639
1640 /* Clear the database */
daefc943 1641 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
3285f9e8
VD		 1642}
1643
da9c359e 1644static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
b7a9e0da 1645 u16 vid)
da9c359e 1646{
0493fa79 1647 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
04bed143 1648 struct mv88e6xxx_chip *chip = ds->priv;
425d2d37 1649 struct mv88e6xxx_vtu_entry vlan;
0493fa79 1650 int err;
da9c359e 1651
db06ae41 1652 /* DSA and CPU ports have to be members of multiple vlans */
0493fa79 1653 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
db06ae41
AL		 1654 return 0;
1655
34065c58 1656 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
b7a9e0da
VO		 1657 if (err)
1658 return err;
da9c359e 1659
b7a9e0da
VO		 1660 if (!vlan.valid)
1661 return 0;
da9c359e 1662
0493fa79 1663 dsa_switch_for_each_user_port(other_dp, ds) {
41fb0cf1
VO		 1664 struct net_device *other_br;
1665
0493fa79 1666 if (vlan.member[other_dp->index] ==
b7a9e0da
VO		 1667 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1668 continue;
da9c359e 1669
41fb0cf1 1670 if (dsa_port_bridge_same(dp, other_dp))
b7a9e0da 1671 break; /* same bridge, check next VLAN */
da9c359e 1672
41fb0cf1
VO		 1673 other_br = dsa_port_bridge_dev_get(other_dp);
1674 if (!other_br)
b7a9e0da 1675 continue;
66e2809d 1676
b7a9e0da 1677 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
41fb0cf1 1678 port, vlan.vid, other_dp->index, netdev_name(other_br));
b7a9e0da
VO		 1679 return -EOPNOTSUPP;
1680 }
da9c359e 1681
7095a4c4 1682 return 0;
da9c359e
VD		 1683}
1684
8b6836d8
VO		 1685static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
1686{
1687 struct dsa_port *dp = dsa_to_port(chip->ds, port);
41fb0cf1 1688 struct net_device *br = dsa_port_bridge_dev_get(dp);
8b6836d8 1689 struct mv88e6xxx_port *p = &chip->ports[port];
5bded825 1690 u16 pvid = MV88E6XXX_VID_STANDALONE;
8b6836d8 1691 bool drop_untagged = false;
8b6836d8
VO		 1692 int err;
1693
41fb0cf1
VO		 1694 if (br) {
1695 if (br_vlan_enabled(br)) {
5bded825
VO		 1696 pvid = p->bridge_pvid.vid;
1697 drop_untagged = !p->bridge_pvid.valid;
1698 } else {
1699 pvid = MV88E6XXX_VID_BRIDGED;
1700 }
8b6836d8
VO		 1701 }
1702
1703 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
1704 if (err)
1705 return err;
1706
1707 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
1708}
1709
f81ec90f 1710static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
89153ed6
VO		 1711 bool vlan_filtering,
1712 struct netlink_ext_ack *extack)
214cdb99 1713{
04bed143 1714 struct mv88e6xxx_chip *chip = ds->priv;
81c6edb2
VD		 1715 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1716 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
0e7b9925 1717 int err;
214cdb99 1718
bae33f2b
VO		 1719 if (!mv88e6xxx_max_vid(chip))
1720 return -EOPNOTSUPP;
54d77b5b 1721
c9acece0 1722 mv88e6xxx_reg_lock(chip);
8b6836d8 1723
385a0995 1724 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
8b6836d8
VO		 1725 if (err)
1726 goto unlock;
1727
1728 err = mv88e6xxx_port_commit_pvid(chip, port);
1729 if (err)
1730 goto unlock;
1731
1732unlock:
c9acece0 1733 mv88e6xxx_reg_unlock(chip);
214cdb99 1734
0e7b9925 1735 return err;
214cdb99
VD		 1736}
1737
57d32310
VD		 1738static int
1739mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
80e02360 1740 const struct switchdev_obj_port_vlan *vlan)
76e398a6 1741{
04bed143 1742 struct mv88e6xxx_chip *chip = ds->priv;
da9c359e
VD		 1743 int err;
1744
e545f865 1745 if (!mv88e6xxx_max_vid(chip))
54d77b5b
VD		 1746 return -EOPNOTSUPP;
1747
da9c359e
VD		 1748 /* If the requested port doesn't belong to the same bridge as the VLAN
1749 * members, do not support it (yet) and fallback to software VLAN.
1750 */
7095a4c4 1751 mv88e6xxx_reg_lock(chip);
b7a9e0da 1752 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
7095a4c4 1753 mv88e6xxx_reg_unlock(chip);
da9c359e 1754
7095a4c4 1755 return err;
76e398a6
VD		 1756}
1757
a4c93ae1
AL		 1758static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1759 const unsigned char *addr, u16 vid,
1760 u8 state)
1761{
a4c93ae1 1762 struct mv88e6xxx_atu_entry entry;
5ef8d249
VD		 1763 struct mv88e6xxx_vtu_entry vlan;
1764 u16 fid;
a4c93ae1
AL		 1765 int err;
1766
5bded825
VO		 1767 /* Ports have two private address databases: one for when the port is
1768 * standalone and one for when the port is under a bridge and the
1769 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
1770 * address database to remain 100% empty, so we never load an ATU entry
1771 * into a standalone port's database. Therefore, translate the null
1772 * VLAN ID into the port's database used for VLAN-unaware bridging.
1773 */
5ef8d249 1774 if (vid == 0) {
5bded825 1775 fid = MV88E6XXX_FID_BRIDGED;
5ef8d249 1776 } else {
34065c58 1777 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
5ef8d249
VD		 1778 if (err)
1779 return err;
1780
1781 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
34065c58 1782 if (!vlan.valid)
5ef8d249
VD		 1783 return -EOPNOTSUPP;
1784
1785 fid = vlan.fid;
1786 }
a4c93ae1 1787
d8291a95 1788 entry.state = 0;
a4c93ae1
AL		 1789 ether_addr_copy(entry.mac, addr);
1790 eth_addr_dec(entry.mac);
1791
5ef8d249 1792 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
a4c93ae1
AL		 1793 if (err)
1794 return err;
1795
1796 /* Initialize a fresh ATU entry if it isn't found */
d8291a95 1797 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
a4c93ae1
AL		 1798 memset(&entry, 0, sizeof(entry));
1799 ether_addr_copy(entry.mac, addr);
1800 }
1801
1802 /* Purge the ATU entry only if no port is using it anymore */
d8291a95 1803 if (!state) {
a4c93ae1
AL		 1804 entry.portvec &= ~BIT(port);
1805 if (!entry.portvec)
d8291a95 1806 entry.state = 0;
a4c93ae1 1807 } else {
f72f2fb8
DQ		 1808 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1809 entry.portvec = BIT(port);
1810 else
1811 entry.portvec |= BIT(port);
1812
a4c93ae1
AL		 1813 entry.state = state;
1814 }
1815
5ef8d249 1816 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
a4c93ae1
AL		 1817}
1818
da7dc875
VD		 1819static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1820 const struct mv88e6xxx_policy *policy)
1821{
1822 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1823 enum mv88e6xxx_policy_action action = policy->action;
1824 const u8 *addr = policy->addr;
1825 u16 vid = policy->vid;
1826 u8 state;
1827 int err;
1828 int id;
1829
1830 if (!chip->info->ops->port_set_policy)
1831 return -EOPNOTSUPP;
1832
1833 switch (mapping) {
1834 case MV88E6XXX_POLICY_MAPPING_DA:
1835 case MV88E6XXX_POLICY_MAPPING_SA:
1836 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1837 state = 0; /* Dissociate the port and address */
1838 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1839 is_multicast_ether_addr(addr))
1840 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1841 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1842 is_unicast_ether_addr(addr))
1843 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1844 else
1845 return -EOPNOTSUPP;
1846
1847 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1848 state);
1849 if (err)
1850 return err;
1851 break;
1852 default:
1853 return -EOPNOTSUPP;
1854 }
1855
1856 /* Skip the port's policy clearing if the mapping is still in use */
1857 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1858 idr_for_each_entry(&chip->policies, policy, id)
1859 if (policy->port == port &&
1860 policy->mapping == mapping &&
1861 policy->action != action)
1862 return 0;
1863
1864 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1865}
1866
1867static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1868 struct ethtool_rx_flow_spec *fs)
1869{
1870 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1871 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1872 enum mv88e6xxx_policy_mapping mapping;
1873 enum mv88e6xxx_policy_action action;
1874 struct mv88e6xxx_policy *policy;
1875 u16 vid = 0;
1876 u8 *addr;
1877 int err;
1878 int id;
1879
1880 if (fs->location != RX_CLS_LOC_ANY)
1881 return -EINVAL;
1882
1883 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1884 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1885 else
1886 return -EOPNOTSUPP;
1887
1888 switch (fs->flow_type & ~FLOW_EXT) {
1889 case ETHER_FLOW:
1890 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1891 is_zero_ether_addr(mac_mask->h_source)) {
1892 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1893 addr = mac_entry->h_dest;
1894 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1895 !is_zero_ether_addr(mac_mask->h_source)) {
1896 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1897 addr = mac_entry->h_source;
1898 } else {
1899 /* Cannot support DA and SA mapping in the same rule */
1900 return -EOPNOTSUPP;
1901 }
1902 break;
1903 default:
1904 return -EOPNOTSUPP;
1905 }
1906
1907 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
04844280 1908 if (fs->m_ext.vlan_tci != htons(0xffff))
da7dc875
VD		 1909 return -EOPNOTSUPP;
1910 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1911 }
1912
1913 idr_for_each_entry(&chip->policies, policy, id) {
1914 if (policy->port == port && policy->mapping == mapping &&
1915 policy->action == action && policy->vid == vid &&
1916 ether_addr_equal(policy->addr, addr))
1917 return -EEXIST;
1918 }
1919
1920 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1921 if (!policy)
1922 return -ENOMEM;
1923
1924 fs->location = 0;
1925 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1926 GFP_KERNEL);
1927 if (err) {
1928 devm_kfree(chip->dev, policy);
1929 return err;
1930 }
1931
1932 memcpy(&policy->fs, fs, sizeof(*fs));
1933 ether_addr_copy(policy->addr, addr);
1934 policy->mapping = mapping;
1935 policy->action = action;
1936 policy->port = port;
1937 policy->vid = vid;
1938
1939 err = mv88e6xxx_policy_apply(chip, port, policy);
1940 if (err) {
1941 idr_remove(&chip->policies, fs->location);
1942 devm_kfree(chip->dev, policy);
1943 return err;
1944 }
1945
1946 return 0;
1947}
1948
1949static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1950 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1951{
1952 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1953 struct mv88e6xxx_chip *chip = ds->priv;
1954 struct mv88e6xxx_policy *policy;
1955 int err;
1956 int id;
1957
1958 mv88e6xxx_reg_lock(chip);
1959
1960 switch (rxnfc->cmd) {
1961 case ETHTOOL_GRXCLSRLCNT:
1962 rxnfc->data = 0;
1963 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1964 rxnfc->rule_cnt = 0;
1965 idr_for_each_entry(&chip->policies, policy, id)
1966 if (policy->port == port)
1967 rxnfc->rule_cnt++;
1968 err = 0;
1969 break;
1970 case ETHTOOL_GRXCLSRULE:
1971 err = -ENOENT;
1972 policy = idr_find(&chip->policies, fs->location);
1973 if (policy) {
1974 memcpy(fs, &policy->fs, sizeof(*fs));
1975 err = 0;
1976 }
1977 break;
1978 case ETHTOOL_GRXCLSRLALL:
1979 rxnfc->data = 0;
1980 rxnfc->rule_cnt = 0;
1981 idr_for_each_entry(&chip->policies, policy, id)
1982 if (policy->port == port)
1983 rule_locs[rxnfc->rule_cnt++] = id;
1984 err = 0;
1985 break;
1986 default:
1987 err = -EOPNOTSUPP;
1988 break;
1989 }
1990
1991 mv88e6xxx_reg_unlock(chip);
1992
1993 return err;
1994}
1995
1996static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1997 struct ethtool_rxnfc *rxnfc)
1998{
1999 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2000 struct mv88e6xxx_chip *chip = ds->priv;
2001 struct mv88e6xxx_policy *policy;
2002 int err;
2003
2004 mv88e6xxx_reg_lock(chip);
2005
2006 switch (rxnfc->cmd) {
2007 case ETHTOOL_SRXCLSRLINS:
2008 err = mv88e6xxx_policy_insert(chip, port, fs);
2009 break;
2010 case ETHTOOL_SRXCLSRLDEL:
2011 err = -ENOENT;
2012 policy = idr_remove(&chip->policies, fs->location);
2013 if (policy) {
2014 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2015 err = mv88e6xxx_policy_apply(chip, port, policy);
2016 devm_kfree(chip->dev, policy);
2017 }
2018 break;
2019 default:
2020 err = -EOPNOTSUPP;
2021 break;
2022 }
2023
2024 mv88e6xxx_reg_unlock(chip);
2025
2026 return err;
2027}
2028
87fa886e
AL		 2029static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2030 u16 vid)
2031{
87fa886e 2032 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
0806dd46
TW		 2033 u8 broadcast[ETH_ALEN];
2034
2035 eth_broadcast_addr(broadcast);
87fa886e
AL		 2036
2037 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2038}
2039
2040static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2041{
2042 int port;
2043 int err;
2044
2045 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
8d1d8298
TW		 2046 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2047 struct net_device *brport;
2048
2049 if (dsa_is_unused_port(chip->ds, port))
2050 continue;
2051
2052 brport = dsa_port_to_bridge_port(dp);
2053 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2054 /* Skip bridged user ports where broadcast
2055 * flooding is disabled.
2056 */
2057 continue;
2058
87fa886e
AL		 2059 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2060 if (err)
2061 return err;
2062 }
2063
2064 return 0;
2065}
2066
8d1d8298
TW		 2067struct mv88e6xxx_port_broadcast_sync_ctx {
2068 int port;
2069 bool flood;
2070};
2071
2072static int
2073mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2074 const struct mv88e6xxx_vtu_entry *vlan,
2075 void *_ctx)
2076{
2077 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2078 u8 broadcast[ETH_ALEN];
2079 u8 state;
2080
2081 if (ctx->flood)
2082 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2083 else
2084 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2085
2086 eth_broadcast_addr(broadcast);
2087
2088 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2089 vlan->vid, state);
2090}
2091
2092static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2093 bool flood)
2094{
2095 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2096 .port = port,
2097 .flood = flood,
2098 };
2099 struct mv88e6xxx_vtu_entry vid0 = {
2100 .vid = 0,
2101 };
2102 int err;
2103
2104 /* Update the port's private database... */
2105 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2106 if (err)
2107 return err;
2108
2109 /* ...and the database for all VLANs. */
2110 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2111 &ctx);
2112}
2113
b1ac6fb4 2114static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
933b4425 2115 u16 vid, u8 member, bool warn)
0d3b33e6 2116{
b1ac6fb4 2117 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
b4e47c0f 2118 struct mv88e6xxx_vtu_entry vlan;
b1ac6fb4 2119 int i, err;
0d3b33e6 2120
34065c58 2121 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
87fa886e
AL		 2122 if (err)
2123 return err;
2124
34065c58 2125 if (!vlan.valid) {
b1ac6fb4
VD		 2126 memset(&vlan, 0, sizeof(vlan));
2127
2128 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2129 if (err)
2130 return err;
2131
2132 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2133 if (i == port)
2134 vlan.member[i] = member;
2135 else
2136 vlan.member[i] = non_member;
2137
2138 vlan.vid = vid;
2139 vlan.valid = true;
2140
2141 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2142 if (err)
2143 return err;
2144
2145 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2146 if (err)
2147 return err;
2148 } else if (vlan.member[port] != member) {
2149 vlan.member[port] = member;
2150
2151 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2152 if (err)
2153 return err;
933b4425 2154 } else if (warn) {
b1ac6fb4
VD		 2155 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2156 port, vid);
2157 }
2158
2159 return 0;
76e398a6
VD		 2160}
2161
1958d581 2162static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 2163 const struct switchdev_obj_port_vlan *vlan,
2164 struct netlink_ext_ack *extack)
76e398a6 2165{
04bed143 2166 struct mv88e6xxx_chip *chip = ds->priv;
76e398a6
VD		 2167 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2168 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
8b6836d8 2169 struct mv88e6xxx_port *p = &chip->ports[port];
933b4425 2170 bool warn;
c91498e1 2171 u8 member;
1958d581 2172 int err;
76e398a6 2173
b8b79c41
EG		 2174 if (!vlan->vid)
2175 return 0;
2176
1958d581
VO		 2177 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2178 if (err)
2179 return err;
54d77b5b 2180
c91498e1 2181 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
7ec60d6e 2182 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
c91498e1 2183 else if (untagged)
7ec60d6e 2184 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
c91498e1 2185 else
7ec60d6e 2186 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
c91498e1 2187
933b4425
RK		 2188 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2189 * and then the CPU port. Do not warn for duplicates for the CPU port.
2190 */
2191 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2192
c9acece0 2193 mv88e6xxx_reg_lock(chip);
76e398a6 2194
1958d581
VO		 2195 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2196 if (err) {
b7a9e0da
VO		 2197 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2198 vlan->vid, untagged ? 'u' : 't');
1958d581
VO		 2199 goto out;
2200 }
76e398a6 2201
1958d581 2202 if (pvid) {
8b6836d8
VO		 2203 p->bridge_pvid.vid = vlan->vid;
2204 p->bridge_pvid.valid = true;
2205
2206 err = mv88e6xxx_port_commit_pvid(chip, port);
2207 if (err)
2208 goto out;
2209 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2210 /* The old pvid was reinstalled as a non-pvid VLAN */
2211 p->bridge_pvid.valid = false;
2212
2213 err = mv88e6xxx_port_commit_pvid(chip, port);
2214 if (err)
1958d581 2215 goto out;
1958d581 2216 }
8b6836d8 2217
1958d581 2218out:
c9acece0 2219 mv88e6xxx_reg_unlock(chip);
1958d581
VO		 2220
2221 return err;
0d3b33e6
VD		 2222}
2223
52109892
VD		 2224static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2225 int port, u16 vid)
7dad08d7 2226{
b4e47c0f 2227 struct mv88e6xxx_vtu_entry vlan;
7dad08d7
VD		 2228 int i, err;
2229
52109892 2230 if (!vid)
c92c7413 2231 return 0;
52109892 2232
34065c58 2233 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
7dad08d7 2234 if (err)
76e398a6 2235 return err;
7dad08d7 2236
52109892
VD		 2237 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2238 * tell switchdev that this VLAN is likely handled in software.
2239 */
34065c58 2240 if (!vlan.valid ||
52109892 2241 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 2242 return -EOPNOTSUPP;
7dad08d7 2243
7ec60d6e 2244 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
7dad08d7
VD		 2245
2246 /* keep the VLAN unless all ports are excluded */
f02bdffc 2247 vlan.valid = false;
370b4ffb 2248 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
7ec60d6e
VD		 2249 if (vlan.member[i] !=
2250 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 2251 vlan.valid = true;
7dad08d7
VD		 2252 break;
2253 }
2254 }
2255
0ad5daf6 2256 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
76e398a6
VD		 2257 if (err)
2258 return err;
2259
e606ca36 2260 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
76e398a6
VD		 2261}
2262
f81ec90f
VD		 2263static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2264 const struct switchdev_obj_port_vlan *vlan)
76e398a6 2265{
04bed143 2266 struct mv88e6xxx_chip *chip = ds->priv;
8b6836d8 2267 struct mv88e6xxx_port *p = &chip->ports[port];
76e398a6 2268 int err = 0;
b7a9e0da 2269 u16 pvid;
76e398a6 2270
e545f865 2271 if (!mv88e6xxx_max_vid(chip))
54d77b5b
VD		 2272 return -EOPNOTSUPP;
2273
c9acece0 2274 mv88e6xxx_reg_lock(chip);
76e398a6 2275
77064f37 2276 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
7dad08d7
VD		 2277 if (err)
2278 goto unlock;
2279
b7a9e0da
VO		 2280 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2281 if (err)
2282 goto unlock;
2283
2284 if (vlan->vid == pvid) {
8b6836d8
VO		 2285 p->bridge_pvid.valid = false;
2286
2287 err = mv88e6xxx_port_commit_pvid(chip, port);
76e398a6
VD		 2288 if (err)
2289 goto unlock;
76e398a6
VD		 2290 }
2291
7dad08d7 2292unlock:
c9acece0 2293 mv88e6xxx_reg_unlock(chip);
7dad08d7
VD		 2294
2295 return err;
2296}
2297
1b6dd556
AS		 2298static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2299 const unsigned char *addr, u16 vid)
87820510 2300{
04bed143 2301 struct mv88e6xxx_chip *chip = ds->priv;
1b6dd556 2302 int err;
87820510 2303
c9acece0 2304 mv88e6xxx_reg_lock(chip);
1b6dd556
AS		 2305 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2306 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
c9acece0 2307 mv88e6xxx_reg_unlock(chip);
1b6dd556
AS		 2308
2309 return err;
87820510
VD		 2310}
2311
f81ec90f 2312static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 2313 const unsigned char *addr, u16 vid)
87820510 2314{
04bed143 2315 struct mv88e6xxx_chip *chip = ds->priv;
83dabd1f 2316 int err;
87820510 2317
c9acece0 2318 mv88e6xxx_reg_lock(chip);
d8291a95 2319 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
c9acece0 2320 mv88e6xxx_reg_unlock(chip);
87820510 2321
83dabd1f 2322 return err;
87820510
VD		 2323}
2324
83dabd1f
VD		 2325static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2326 u16 fid, u16 vid, int port,
2bedde1a 2327 dsa_fdb_dump_cb_t *cb, void *data)
74b6ba0d 2328{
dabc1a96 2329 struct mv88e6xxx_atu_entry addr;
2bedde1a 2330 bool is_static;
74b6ba0d
VD		 2331 int err;
2332
d8291a95 2333 addr.state = 0;
dabc1a96 2334 eth_broadcast_addr(addr.mac);
74b6ba0d
VD		 2335
2336 do {
dabc1a96 2337 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
74b6ba0d 2338 if (err)
83dabd1f 2339 return err;
74b6ba0d 2340
d8291a95 2341 if (!addr.state)
74b6ba0d
VD		 2342 break;
2343
01bd96c8 2344 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
83dabd1f
VD		 2345 continue;
2346
2bedde1a
AS		 2347 if (!is_unicast_ether_addr(addr.mac))
2348 continue;
83dabd1f 2349
2bedde1a
AS		 2350 is_static = (addr.state ==
2351 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2352 err = cb(addr.mac, vid, is_static, data);
83dabd1f
VD		 2353 if (err)
2354 return err;
74b6ba0d
VD		 2355 } while (!is_broadcast_ether_addr(addr.mac));
2356
2357 return err;
2358}
2359
d89ef4b8
TW		 2360struct mv88e6xxx_port_db_dump_vlan_ctx {
2361 int port;
2362 dsa_fdb_dump_cb_t *cb;
2363 void *data;
2364};
2365
2366static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2367 const struct mv88e6xxx_vtu_entry *entry,
2368 void *_data)
2369{
2370 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2371
2372 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2373 ctx->port, ctx->cb, ctx->data);
2374}
2375
83dabd1f 2376static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2bedde1a 2377 dsa_fdb_dump_cb_t *cb, void *data)
f33475bd 2378{
d89ef4b8
TW		 2379 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2380 .port = port,
2381 .cb = cb,
2382 .data = data,
2383 };
2db9ce1f 2384 u16 fid;
f33475bd
VD		 2385 int err;
2386
2db9ce1f 2387 /* Dump port's default Filtering Information Database (VLAN ID 0) */
b4e48c50 2388 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2db9ce1f 2389 if (err)
83dabd1f 2390 return err;
2db9ce1f 2391
2bedde1a 2392 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2db9ce1f 2393 if (err)
83dabd1f 2394 return err;
2db9ce1f 2395
d89ef4b8 2396 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
83dabd1f
VD		 2397}
2398
2399static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 2400 dsa_fdb_dump_cb_t *cb, void *data)
83dabd1f 2401{
04bed143 2402 struct mv88e6xxx_chip *chip = ds->priv;
fcf15367
VD		 2403 int err;
2404
c9acece0 2405 mv88e6xxx_reg_lock(chip);
fcf15367 2406 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
c9acece0 2407 mv88e6xxx_reg_unlock(chip);
83dabd1f 2408
fcf15367 2409 return err;
f33475bd
VD		 2410}
2411
240ea3ef 2412static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
d3eed0e5 2413 struct dsa_bridge bridge)
e79a8bcb 2414{
ef2025ec
VD		 2415 struct dsa_switch *ds = chip->ds;
2416 struct dsa_switch_tree *dst = ds->dst;
2417 struct dsa_port *dp;
240ea3ef 2418 int err;
466dfa07 2419
ef2025ec 2420 list_for_each_entry(dp, &dst->ports, list) {
d3eed0e5 2421 if (dsa_port_offloads_bridge(dp, &bridge)) {
ef2025ec
VD		 2422 if (dp->ds == ds) {
2423 /* This is a local bridge group member,
2424 * remap its Port VLAN Map.
2425 */
2426 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2427 if (err)
2428 return err;
2429 } else {
2430 /* This is an external bridge group member,
2431 * remap its cross-chip Port VLAN Table entry.
2432 */
2433 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2434 dp->index);
e96a6e02
VD		 2435 if (err)
2436 return err;
2437 }
2438 }
2439 }
2440
240ea3ef
VD		 2441 return 0;
2442}
2443
2444static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
d3eed0e5 2445 struct dsa_bridge bridge)
240ea3ef
VD		 2446{
2447 struct mv88e6xxx_chip *chip = ds->priv;
2448 int err;
2449
c9acece0 2450 mv88e6xxx_reg_lock(chip);
5bded825 2451
d3eed0e5 2452 err = mv88e6xxx_bridge_map(chip, bridge);
5bded825
VO		 2453 if (err)
2454 goto unlock;
2455
2456 err = mv88e6xxx_port_commit_pvid(chip, port);
2457 if (err)
2458 goto unlock;
2459
2460unlock:
c9acece0 2461 mv88e6xxx_reg_unlock(chip);
a6692754 2462
466dfa07 2463 return err;
e79a8bcb
VD		 2464}
2465
f123f2fb 2466static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
d3eed0e5 2467 struct dsa_bridge bridge)
66d9cd0f 2468{
04bed143 2469 struct mv88e6xxx_chip *chip = ds->priv;
5bded825 2470 int err;
466dfa07 2471
c9acece0 2472 mv88e6xxx_reg_lock(chip);
5bded825 2473
d3eed0e5 2474 if (mv88e6xxx_bridge_map(chip, bridge) ||
240ea3ef
VD		 2475 mv88e6xxx_port_vlan_map(chip, port))
2476 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
5bded825
VO		 2477
2478 err = mv88e6xxx_port_commit_pvid(chip, port);
2479 if (err)
2480 dev_err(ds->dev,
2481 "port %d failed to restore standalone pvid: %pe\n",
2482 port, ERR_PTR(err));
2483
c9acece0 2484 mv88e6xxx_reg_unlock(chip);
66d9cd0f
VD		 2485}
2486
f66a6a69
VO		 2487static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2488 int tree_index, int sw_index,
d3eed0e5 2489 int port, struct dsa_bridge bridge)
aec5ac88
VD		 2490{
2491 struct mv88e6xxx_chip *chip = ds->priv;
2492 int err;
2493
f66a6a69
VO		 2494 if (tree_index != ds->dst->index)
2495 return 0;
2496
c9acece0 2497 mv88e6xxx_reg_lock(chip);
f66a6a69 2498 err = mv88e6xxx_pvt_map(chip, sw_index, port);
c9acece0 2499 mv88e6xxx_reg_unlock(chip);
aec5ac88
VD		 2500
2501 return err;
2502}
2503
f66a6a69
VO		 2504static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2505 int tree_index, int sw_index,
d3eed0e5 2506 int port, struct dsa_bridge bridge)
aec5ac88
VD		 2507{
2508 struct mv88e6xxx_chip *chip = ds->priv;
2509
f66a6a69
VO		 2510 if (tree_index != ds->dst->index)
2511 return;
2512
c9acece0 2513 mv88e6xxx_reg_lock(chip);
f66a6a69 2514 if (mv88e6xxx_pvt_map(chip, sw_index, port))
aec5ac88 2515 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
c9acece0 2516 mv88e6xxx_reg_unlock(chip);
aec5ac88
VD		 2517}
2518
ce5df689
VO		 2519/* Treat the software bridge as a virtual single-port switch behind the
2520 * CPU and map in the PVT. First dst->last_switch elements are taken by
2521 * physical switches, so start from beyond that range.
2522 */
2523static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
3f9bb030 2524 unsigned int bridge_num)
ce5df689 2525{
3f9bb030 2526 u8 dev = bridge_num + ds->dst->last_switch;
ce5df689
VO		 2527 struct mv88e6xxx_chip *chip = ds->priv;
2528 int err;
2529
2530 mv88e6xxx_reg_lock(chip);
2531 err = mv88e6xxx_pvt_map(chip, dev, 0);
2532 mv88e6xxx_reg_unlock(chip);
2533
2534 return err;
2535}
2536
2537static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port,
d3eed0e5 2538 struct dsa_bridge bridge)
ce5df689 2539{
d3eed0e5 2540 return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
ce5df689
VO		 2541}
2542
2543static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port,
d3eed0e5 2544 struct dsa_bridge bridge)
ce5df689
VO		 2545{
2546 int err;
2547
d3eed0e5 2548 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
ce5df689
VO		 2549 if (err) {
2550 dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n",
2551 ERR_PTR(err));
2552 }
2553}
2554
17e708ba
VD		 2555static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2556{
2557 if (chip->info->ops->reset)
2558 return chip->info->ops->reset(chip);
2559
2560 return 0;
2561}
2562
309eca6d
VD		 2563static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2564{
2565 struct gpio_desc *gpiod = chip->reset;
2566
2567 /* If there is a GPIO connected to the reset pin, toggle it */
2568 if (gpiod) {
2569 gpiod_set_value_cansleep(gpiod, 1);
2570 usleep_range(10000, 20000);
2571 gpiod_set_value_cansleep(gpiod, 0);
2572 usleep_range(10000, 20000);
a3dcb3e7
AL		 2573
2574 mv88e6xxx_g1_wait_eeprom_done(chip);
309eca6d
VD		 2575 }
2576}
2577
4ac4b5a6 2578static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
552238b5 2579{
4ac4b5a6 2580 int i, err;
552238b5 2581
4ac4b5a6 2582 /* Set all ports to the Disabled state */
370b4ffb 2583 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
f894c29c 2584 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
0e7b9925
AL		 2585 if (err)
2586 return err;
552238b5
VD		 2587 }
2588
4ac4b5a6
VD		 2589 /* Wait for transmit queues to drain,
2590 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2591 */
552238b5
VD		 2592 usleep_range(2000, 4000);
2593
4ac4b5a6
VD		 2594 return 0;
2595}
2596
2597static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2598{
4ac4b5a6
VD		 2599 int err;
2600
2601 err = mv88e6xxx_disable_ports(chip);
2602 if (err)
2603 return err;
2604
309eca6d 2605 mv88e6xxx_hardware_reset(chip);
552238b5 2606
17e708ba 2607 return mv88e6xxx_software_reset(chip);
552238b5
VD		 2608}
2609
4314557c 2610static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
31bef4e9
VD		 2611 enum mv88e6xxx_frame_mode frame,
2612 enum mv88e6xxx_egress_mode egress, u16 etype)
56995cbc
AL		 2613{
2614 int err;
2615
4314557c
VD		 2616 if (!chip->info->ops->port_set_frame_mode)
2617 return -EOPNOTSUPP;
2618
2619 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
56995cbc
AL		 2620 if (err)
2621 return err;
2622
4314557c
VD		 2623 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2624 if (err)
2625 return err;
2626
2627 if (chip->info->ops->port_set_ether_type)
2628 return chip->info->ops->port_set_ether_type(chip, port, etype);
2629
2630 return 0;
56995cbc
AL		 2631}
2632
4314557c 2633static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
56995cbc 2634{
4314557c 2635 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
31bef4e9 2636 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 2637 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 2638}
56995cbc 2639
4314557c
VD		 2640static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2641{
2642 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
31bef4e9 2643 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
b8109594 2644 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
4314557c 2645}
56995cbc 2646
4314557c
VD		 2647static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2648{
2649 return mv88e6xxx_set_port_mode(chip, port,
2650 MV88E6XXX_FRAME_MODE_ETHERTYPE,
31bef4e9
VD		 2651 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2652 ETH_P_EDSA);
4314557c 2653}
56995cbc 2654
4314557c
VD		 2655static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2656{
2657 if (dsa_is_dsa_port(chip->ds, port))
2658 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2659
2b3e9891 2660 if (dsa_is_user_port(chip->ds, port))
4314557c 2661 return mv88e6xxx_set_port_mode_normal(chip, port);
56995cbc 2662
4314557c 2663 /* Setup CPU port mode depending on its supported tag format */
670bb80f 2664 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
4314557c 2665 return mv88e6xxx_set_port_mode_dsa(chip, port);
56995cbc 2666
670bb80f 2667 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
4314557c 2668 return mv88e6xxx_set_port_mode_edsa(chip, port);
56995cbc 2669
4314557c 2670 return -EINVAL;
56995cbc
AL		 2671}
2672
601aeed3 2673static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
56995cbc 2674{
601aeed3 2675 bool message = dsa_is_dsa_port(chip->ds, port);
56995cbc 2676
601aeed3 2677 return mv88e6xxx_port_set_message_port(chip, port, message);
4314557c 2678}
56995cbc 2679
601aeed3 2680static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
4314557c 2681{
a8b659e7 2682 int err;
56995cbc 2683
a8b659e7 2684 if (chip->info->ops->port_set_ucast_flood) {
7b9f16fe 2685 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
a8b659e7
VO		 2686 if (err)
2687 return err;
2688 }
2689 if (chip->info->ops->port_set_mcast_flood) {
7b9f16fe 2690 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
a8b659e7
VO		 2691 if (err)
2692 return err;
2693 }
ea698f4f 2694
407308f6 2695 return 0;
ea698f4f
VD		 2696}
2697
45de77ff
VD		 2698static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2699{
2700 struct mv88e6xxx_port *mvp = dev_id;
2701 struct mv88e6xxx_chip *chip = mvp->chip;
2702 irqreturn_t ret = IRQ_NONE;
2703 int port = mvp->port;
193c5b26 2704 int lane;
45de77ff
VD		 2705
2706 mv88e6xxx_reg_lock(chip);
2707 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 2708 if (lane >= 0)
45de77ff
VD		 2709 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2710 mv88e6xxx_reg_unlock(chip);
2711
2712 return ret;
2713}
2714
2715static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
193c5b26 2716 int lane)
45de77ff
VD		 2717{
2718 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2719 unsigned int irq;
2720 int err;
2721
2722 /* Nothing to request if this SERDES port has no IRQ */
2723 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2724 if (!irq)
2725 return 0;
2726
e6f2f6b8
AL		 2727 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2728 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2729
45de77ff
VD		 2730 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2731 mv88e6xxx_reg_unlock(chip);
2732 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
e6f2f6b8
AL		 2733 IRQF_ONESHOT, dev_id->serdes_irq_name,
2734 dev_id);
45de77ff
VD		 2735 mv88e6xxx_reg_lock(chip);
2736 if (err)
2737 return err;
2738
2739 dev_id->serdes_irq = irq;
2740
2741 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2742}
2743
2744static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
193c5b26 2745 int lane)
45de77ff
VD		 2746{
2747 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2748 unsigned int irq = dev_id->serdes_irq;
2749 int err;
2750
2751 /* Nothing to free if no IRQ has been requested */
2752 if (!irq)
2753 return 0;
2754
2755 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2756
2757 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2758 mv88e6xxx_reg_unlock(chip);
2759 free_irq(irq, dev_id);
2760 mv88e6xxx_reg_lock(chip);
2761
2762 dev_id->serdes_irq = 0;
2763
2764 return err;
2765}
2766
6d91782f
AL		 2767static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2768 bool on)
2769{
193c5b26 2770 int lane;
fc0bc019 2771 int err;
04aca993 2772
dc272f60 2773 lane = mv88e6xxx_serdes_get_lane(chip, port);
193c5b26 2774 if (lane < 0)
fc0bc019
VD		 2775 return 0;
2776
2777 if (on) {
dc272f60 2778 err = mv88e6xxx_serdes_power_up(chip, port, lane);
fc0bc019
VD		 2779 if (err)
2780 return err;
2781
45de77ff 2782 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
fc0bc019 2783 } else {
45de77ff
VD		 2784 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2785 if (err)
2786 return err;
fc0bc019 2787
dc272f60 2788 err = mv88e6xxx_serdes_power_down(chip, port, lane);
fc0bc019
VD		 2789 }
2790
2791 return err;
6d91782f
AL		 2792}
2793
2fda45f0
MB		 2794static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
2795 enum mv88e6xxx_egress_direction direction,
2796 int port)
2797{
2798 int err;
2799
2800 if (!chip->info->ops->set_egress_port)
2801 return -EOPNOTSUPP;
2802
2803 err = chip->info->ops->set_egress_port(chip, direction, port);
2804 if (err)
2805 return err;
2806
2807 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
2808 chip->ingress_dest_port = port;
2809 else
2810 chip->egress_dest_port = port;
2811
2812 return 0;
2813}
2814
fa371c80
VD		 2815static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2816{
2817 struct dsa_switch *ds = chip->ds;
2818 int upstream_port;
2819 int err;
2820
07073c79 2821 upstream_port = dsa_upstream_port(ds, port);
fa371c80
VD		 2822 if (chip->info->ops->port_set_upstream_port) {
2823 err = chip->info->ops->port_set_upstream_port(chip, port,
2824 upstream_port);
2825 if (err)
2826 return err;
2827 }
2828
0ea54dda
VD		 2829 if (port == upstream_port) {
2830 if (chip->info->ops->set_cpu_port) {
2831 err = chip->info->ops->set_cpu_port(chip,
2832 upstream_port);
2833 if (err)
2834 return err;
2835 }
2836
2fda45f0 2837 err = mv88e6xxx_set_egress_port(chip,
5c74c54c
IT		 2838 MV88E6XXX_EGRESS_DIR_INGRESS,
2839 upstream_port);
2fda45f0
MB		 2840 if (err && err != -EOPNOTSUPP)
2841 return err;
5c74c54c 2842
2fda45f0 2843 err = mv88e6xxx_set_egress_port(chip,
5c74c54c
IT		 2844 MV88E6XXX_EGRESS_DIR_EGRESS,
2845 upstream_port);
2fda45f0
MB		 2846 if (err && err != -EOPNOTSUPP)
2847 return err;
0ea54dda
VD		 2848 }
2849
fa371c80
VD		 2850 return 0;
2851}
2852
fad09c73 2853static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
d827e88a 2854{
fad09c73 2855 struct dsa_switch *ds = chip->ds;
0e7b9925 2856 int err;
54d792f2 2857 u16 reg;
d827e88a 2858
7b898469
AL		 2859 chip->ports[port].chip = chip;
2860 chip->ports[port].port = port;
2861
d78343d2
VD		 2862 /* MAC Forcing register: don't force link, speed, duplex or flow control
2863 * state to any particular values on physical ports, but force the CPU
2864 * port and all DSA ports to their maximum bandwidth and full duplex.
2865 */
2866 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2867 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2868 SPEED_MAX, DUPLEX_FULL,
54186b91 2869 PAUSE_OFF,
d78343d2
VD		 2870 PHY_INTERFACE_MODE_NA);
2871 else
2872 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2873 SPEED_UNFORCED, DUPLEX_UNFORCED,
54186b91 2874 PAUSE_ON,
d78343d2
VD		 2875 PHY_INTERFACE_MODE_NA);
2876 if (err)
2877 return err;
54d792f2
AL		 2878
2879 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2880 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2881 * tunneling, determine priority by looking at 802.1p and IP
2882 * priority fields (IP prio has precedence), and set STP state
2883 * to Forwarding.
2884 *
2885 * If this is the CPU link, use DSA or EDSA tagging depending
2886 * on which tagging mode was configured.
2887 *
2888 * If this is a link to another switch, use DSA tagging mode.
2889 *
2890 * If this is the upstream port for this switch, enable
2891 * forwarding of unknown unicasts and multicasts.
2892 */
a89b433b
VD		 2893 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2894 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2895 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2896 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
56995cbc
AL		 2897 if (err)
2898 return err;
6083ce71 2899
601aeed3 2900 err = mv88e6xxx_setup_port_mode(chip, port);
56995cbc
AL		 2901 if (err)
2902 return err;
54d792f2 2903
601aeed3 2904 err = mv88e6xxx_setup_egress_floods(chip, port);
4314557c
VD		 2905 if (err)
2906 return err;
2907
b92ce2f5
AL		 2908 /* Port Control 2: don't force a good FCS, set the MTU size to
2909 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2910 * untagged frames on this port, do a destination address lookup on all
2911 * received packets as usual, disable ARP mirroring and don't send a
2912 * copy of all transmitted/received frames on this port to the CPU.
54d792f2 2913 */
a23b2961
AL		 2914 err = mv88e6xxx_port_set_map_da(chip, port);
2915 if (err)
2916 return err;
8efdda4a 2917
fa371c80
VD		 2918 err = mv88e6xxx_setup_upstream_port(chip, port);
2919 if (err)
2920 return err;
54d792f2 2921
a23b2961 2922 err = mv88e6xxx_port_set_8021q_mode(chip, port,
81c6edb2 2923 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
a23b2961
AL		 2924 if (err)
2925 return err;
2926
5bded825
VO		 2927 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
2928 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
2929 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
2930 * as the private PVID on ports under a VLAN-unaware bridge.
2931 * Shared (DSA and CPU) ports must also be members of it, to translate
2932 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
2933 * relying on their port default FID.
2934 */
2935 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
2936 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED,
2937 false);
2938 if (err)
2939 return err;
2940
cd782656 2941 if (chip->info->ops->port_set_jumbo_size) {
b92ce2f5 2942 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
5f436666
AL		 2943 if (err)
2944 return err;
2945 }
2946
041bd545
TW		 2947 /* Port Association Vector: disable automatic address learning
2948 * on all user ports since they start out in standalone
2949 * mode. When joining a bridge, learning will be configured to
2950 * match the bridge port settings. Enable learning on all
2951 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
2952 * learning process.
2953 *
2954 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
2955 * and RefreshLocked. I.e. setup standard automatic learning.
54d792f2 2956 */
041bd545 2957 if (dsa_is_user_port(ds, port))
65fa4027 2958 reg = 0;
041bd545
TW		 2959 else
2960 reg = 1 << port;
4c7ea3c0 2961
2a4614e4
VD		 2962 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2963 reg);
0e7b9925
AL		 2964 if (err)
2965 return err;
54d792f2
AL		 2966
2967 /* Egress rate control 2: disable egress rate control. */
2cb8cb14
VD		 2968 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2969 0x0000);
0e7b9925
AL		 2970 if (err)
2971 return err;
54d792f2 2972
0898432c
VD		 2973 if (chip->info->ops->port_pause_limit) {
2974 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
0e7b9925
AL		 2975 if (err)
2976 return err;
b35d322a 2977 }
54d792f2 2978
c8c94891
VD		 2979 if (chip->info->ops->port_disable_learn_limit) {
2980 err = chip->info->ops->port_disable_learn_limit(chip, port);
2981 if (err)
2982 return err;
2983 }
2984
9dbfb4e1
VD		 2985 if (chip->info->ops->port_disable_pri_override) {
2986 err = chip->info->ops->port_disable_pri_override(chip, port);
0e7b9925
AL		 2987 if (err)
2988 return err;
ef0a7318 2989 }
2bbb33be 2990
ef0a7318
AL		 2991 if (chip->info->ops->port_tag_remap) {
2992 err = chip->info->ops->port_tag_remap(chip, port);
0e7b9925
AL		 2993 if (err)
2994 return err;
54d792f2
AL		 2995 }
2996
ef70b111
AL		 2997 if (chip->info->ops->port_egress_rate_limiting) {
2998 err = chip->info->ops->port_egress_rate_limiting(chip, port);
0e7b9925
AL		 2999 if (err)
3000 return err;
54d792f2
AL		 3001 }
3002
121b8fe2
HF		 3003 if (chip->info->ops->port_setup_message_port) {
3004 err = chip->info->ops->port_setup_message_port(chip, port);
3005 if (err)
3006 return err;
3007 }
d827e88a 3008
207afda1 3009 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 3010 * database, and allow bidirectional communication between the
3011 * CPU and DSA port(s), and the other ports.
d827e88a 3012 */
5bded825 3013 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
0e7b9925
AL		 3014 if (err)
3015 return err;
2db9ce1f 3016
240ea3ef 3017 err = mv88e6xxx_port_vlan_map(chip, port);
0e7b9925
AL		 3018 if (err)
3019 return err;
d827e88a
GR		 3020
3021 /* Default VLAN ID and priority: don't set a default VLAN
3022 * ID, and set the default packet priority to zero.
3023 */
b7929fb3 3024 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
dbde9e66
AL		 3025}
3026
2a550aec
AL		 3027static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3028{
3029 struct mv88e6xxx_chip *chip = ds->priv;
3030
3031 if (chip->info->ops->port_set_jumbo_size)
b9c587fe 3032 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
1baf0fac 3033 else if (chip->info->ops->set_max_frame_size)
b9c587fe
AL		 3034 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3035 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
2a550aec
AL		 3036}
3037
3038static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3039{
3040 struct mv88e6xxx_chip *chip = ds->priv;
3041 int ret = 0;
3042
b9c587fe
AL		 3043 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3044 new_mtu += EDSA_HLEN;
3045
2a550aec
AL		 3046 mv88e6xxx_reg_lock(chip);
3047 if (chip->info->ops->port_set_jumbo_size)
3048 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
1baf0fac
CP		 3049 else if (chip->info->ops->set_max_frame_size)
3050 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2a550aec
AL		 3051 else
3052 if (new_mtu > 1522)
3053 ret = -EINVAL;
3054 mv88e6xxx_reg_unlock(chip);
3055
3056 return ret;
3057}
3058
04aca993
AL		 3059static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
3060 struct phy_device *phydev)
3061{
3062 struct mv88e6xxx_chip *chip = ds->priv;
523a8904 3063 int err;
04aca993 3064
c9acece0 3065 mv88e6xxx_reg_lock(chip);
523a8904 3066 err = mv88e6xxx_serdes_power(chip, port, true);
c9acece0 3067 mv88e6xxx_reg_unlock(chip);
04aca993
AL		 3068
3069 return err;
3070}
3071
75104db0 3072static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
04aca993
AL		 3073{
3074 struct mv88e6xxx_chip *chip = ds->priv;
3075
c9acece0 3076 mv88e6xxx_reg_lock(chip);
523a8904
VD		 3077 if (mv88e6xxx_serdes_power(chip, port, false))
3078 dev_err(chip->dev, "failed to power off SERDES\n");
c9acece0 3079 mv88e6xxx_reg_unlock(chip);
04aca993
AL		 3080}
3081
2cfcd964
VD		 3082static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3083 unsigned int ageing_time)
3084{
04bed143 3085 struct mv88e6xxx_chip *chip = ds->priv;
2cfcd964
VD		 3086 int err;
3087
c9acece0 3088 mv88e6xxx_reg_lock(chip);
720c6343 3089 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
c9acece0 3090 mv88e6xxx_reg_unlock(chip);
2cfcd964
VD		 3091
3092 return err;
3093}
3094
447b1bb8 3095static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
acdaffcc 3096{
552238b5 3097 int err;
54d792f2 3098
de227387 3099 /* Initialize the statistics unit */
447b1bb8
VD		 3100 if (chip->info->ops->stats_set_histogram) {
3101 err = chip->info->ops->stats_set_histogram(chip);
3102 if (err)
3103 return err;
3104 }
de227387 3105
40cff8fc 3106 return mv88e6xxx_g1_stats_clear(chip);
9729934c
VD		 3107}
3108
ea89098e
AL		 3109/* Check if the errata has already been applied. */
3110static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3111{
3112 int port;
3113 int err;
3114 u16 val;
3115
3116 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
60907013 3117 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
ea89098e
AL		 3118 if (err) {
3119 dev_err(chip->dev,
3120 "Error reading hidden register: %d\n", err);
3121 return false;
3122 }
3123 if (val != 0x01c0)
3124 return false;
3125 }
3126
3127 return true;
3128}
3129
3130/* The 6390 copper ports have an errata which require poking magic
3131 * values into undocumented hidden registers and then performing a
3132 * software reset.
3133 */
3134static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3135{
3136 int port;
3137 int err;
3138
3139 if (mv88e6390_setup_errata_applied(chip))
3140 return 0;
3141
3142 /* Set the ports into blocking mode */
3143 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3144 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3145 if (err)
3146 return err;
3147 }
3148
3149 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
60907013 3150 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
ea89098e
AL		 3151 if (err)
3152 return err;
3153 }
3154
3155 return mv88e6xxx_software_reset(chip);
3156}
3157
23e8b470
AL		 3158static void mv88e6xxx_teardown(struct dsa_switch *ds)
3159{
3160 mv88e6xxx_teardown_devlink_params(ds);
e0c69ca7 3161 dsa_devlink_resources_unregister(ds);
fd292c18 3162 mv88e6xxx_teardown_devlink_regions_global(ds);
23e8b470
AL		 3163}
3164
f81ec90f 3165static int mv88e6xxx_setup(struct dsa_switch *ds)
08a01261 3166{
04bed143 3167 struct mv88e6xxx_chip *chip = ds->priv;
2d2e1dd2 3168 u8 cmode;
08a01261 3169 int err;
a1a6a4d1
VD		 3170 int i;
3171
fad09c73 3172 chip->ds = ds;
a3c53be5 3173 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
08a01261 3174
ce5df689
VO		 3175 /* Since virtual bridges are mapped in the PVT, the number we support
3176 * depends on the physical switch topology. We need to let DSA figure
3177 * that out and therefore we cannot set this at dsa_register_switch()
3178 * time.
3179 */
3180 if (mv88e6xxx_has_pvt(chip))
947c8746
VO		 3181 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3182 ds->dst->last_switch - 1;
ce5df689 3183
c9acece0 3184 mv88e6xxx_reg_lock(chip);
08a01261 3185
ea89098e
AL		 3186 if (chip->info->ops->setup_errata) {
3187 err = chip->info->ops->setup_errata(chip);
3188 if (err)
3189 goto unlock;
3190 }
3191
2d2e1dd2
AL		 3192 /* Cache the cmode of each port. */
3193 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3194 if (chip->info->ops->port_get_cmode) {
3195 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3196 if (err)
e29129fc 3197 goto unlock;
2d2e1dd2
AL		 3198
3199 chip->ports[i].cmode = cmode;
3200 }
3201 }
3202
5bded825
VO		 3203 err = mv88e6xxx_vtu_setup(chip);
3204 if (err)
3205 goto unlock;
3206
9729934c 3207 /* Setup Switch Port Registers */
370b4ffb 3208 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
b759f528
VD		 3209 if (dsa_is_unused_port(ds, i))
3210 continue;
3211
c857486a 3212 /* Prevent the use of an invalid port. */
b759f528 3213 if (mv88e6xxx_is_invalid_port(chip, i)) {
c857486a
HF		 3214 dev_err(chip->dev, "port %d is invalid\n", i);
3215 err = -EINVAL;
3216 goto unlock;
3217 }
3218
9729934c
VD		 3219 err = mv88e6xxx_setup_port(chip, i);
3220 if (err)
3221 goto unlock;
3222 }
3223
cd8da8bb
VD		 3224 err = mv88e6xxx_irl_setup(chip);
3225 if (err)
3226 goto unlock;
3227
04a69a17
VD		 3228 err = mv88e6xxx_mac_setup(chip);
3229 if (err)
3230 goto unlock;
3231
1b17aedf
VD		 3232 err = mv88e6xxx_phy_setup(chip);
3233 if (err)
3234 goto unlock;
3235
81228996
VD		 3236 err = mv88e6xxx_pvt_setup(chip);
3237 if (err)
3238 goto unlock;
3239
a2ac29d2
VD		 3240 err = mv88e6xxx_atu_setup(chip);
3241 if (err)
3242 goto unlock;
3243
87fa886e
AL		 3244 err = mv88e6xxx_broadcast_setup(chip, 0);
3245 if (err)
3246 goto unlock;
3247
9e907d73
VD		 3248 err = mv88e6xxx_pot_setup(chip);
3249 if (err)
3250 goto unlock;
3251
9e5baf9b
VD		 3252 err = mv88e6xxx_rmu_setup(chip);
3253 if (err)
3254 goto unlock;
3255
51c901a7
VD		 3256 err = mv88e6xxx_rsvd2cpu_setup(chip);
3257 if (err)
3258 goto unlock;
6e55f698 3259
b28f872d
VD		 3260 err = mv88e6xxx_trunk_setup(chip);
3261 if (err)
3262 goto unlock;
3263
c7f047b6
VD		 3264 err = mv88e6xxx_devmap_setup(chip);
3265 if (err)
3266 goto unlock;
3267
93e18d61
VD		 3268 err = mv88e6xxx_pri_setup(chip);
3269 if (err)
3270 goto unlock;
3271
c6fe0ad2 3272 /* Setup PTP Hardware Clock and timestamping */
2fa8d3af
BS		 3273 if (chip->info->ptp_support) {
3274 err = mv88e6xxx_ptp_setup(chip);
3275 if (err)
3276 goto unlock;
c6fe0ad2
BS		 3277
3278 err = mv88e6xxx_hwtstamp_setup(chip);
3279 if (err)
3280 goto unlock;
2fa8d3af
BS		 3281 }
3282
447b1bb8
VD		 3283 err = mv88e6xxx_stats_setup(chip);
3284 if (err)
3285 goto unlock;
3286
6b17e864 3287unlock:
c9acece0 3288 mv88e6xxx_reg_unlock(chip);
db687a56 3289
e0c69ca7
AL		 3290 if (err)
3291 return err;
3292
3293 /* Have to be called without holding the register lock, since
3294 * they take the devlink lock, and we later take the locks in
3295 * the reverse order when getting/setting parameters or
3296 * resource occupancy.
23e8b470 3297 */
e0c69ca7
AL		 3298 err = mv88e6xxx_setup_devlink_resources(ds);
3299 if (err)
3300 return err;
3301
3302 err = mv88e6xxx_setup_devlink_params(ds);
3303 if (err)
bfb25542
AL		 3304 goto out_resources;
3305
fd292c18 3306 err = mv88e6xxx_setup_devlink_regions_global(ds);
bfb25542
AL		 3307 if (err)
3308 goto out_params;
3309
3310 return 0;
3311
3312out_params:
3313 mv88e6xxx_teardown_devlink_params(ds);
3314out_resources:
3315 dsa_devlink_resources_unregister(ds);
e0c69ca7
AL		 3316
3317 return err;
54d792f2
AL		 3318}
3319
fd292c18
VO		 3320static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3321{
3322 return mv88e6xxx_setup_devlink_regions_port(ds, port);
3323}
3324
3325static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3326{
3327 mv88e6xxx_teardown_devlink_regions_port(ds, port);
3328}
3329
1fe976d3
PR		 3330/* prod_id for switch families which do not have a PHY model number */
3331static const u16 family_prod_id_table[] = {
3332 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3333 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
c5d015b0 3334 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
1fe976d3
PR		 3335};
3336
e57e5e77 3337static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
fd3a0ee4 3338{
0dd12d54
AL		 3339 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3340 struct mv88e6xxx_chip *chip = mdio_bus->chip;
1fe976d3 3341 u16 prod_id;
e57e5e77
VD		 3342 u16 val;
3343 int err;
fd3a0ee4 3344
ee26a228
AL		 3345 if (!chip->info->ops->phy_read)
3346 return -EOPNOTSUPP;
3347
c9acece0 3348 mv88e6xxx_reg_lock(chip);
ee26a228 3349 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
c9acece0 3350 mv88e6xxx_reg_unlock(chip);
e57e5e77 3351
1fe976d3
PR		 3352 /* Some internal PHYs don't have a model number. */
3353 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3354 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3355 prod_id = family_prod_id_table[chip->info->family];
3356 if (prod_id)
3357 val |= prod_id >> 4;
da9f3301
AL		 3358 }
3359
e57e5e77 3360 return err ? err : val;
fd3a0ee4
AL		 3361}
3362
e57e5e77 3363static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
fd3a0ee4 3364{
0dd12d54
AL		 3365 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3366 struct mv88e6xxx_chip *chip = mdio_bus->chip;
e57e5e77 3367 int err;
fd3a0ee4 3368
ee26a228
AL		 3369 if (!chip->info->ops->phy_write)
3370 return -EOPNOTSUPP;
3371
c9acece0 3372 mv88e6xxx_reg_lock(chip);
ee26a228 3373 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
c9acece0 3374 mv88e6xxx_reg_unlock(chip);
e57e5e77
VD		 3375
3376 return err;
fd3a0ee4
AL		 3377}
3378
fad09c73 3379static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
a3c53be5
AL		 3380 struct device_node *np,
3381 bool external)
b516d453
AL		 3382{
3383 static int index;
0dd12d54 3384 struct mv88e6xxx_mdio_bus *mdio_bus;
b516d453
AL		 3385 struct mii_bus *bus;
3386 int err;
3387
2510babc 3388 if (external) {
c9acece0 3389 mv88e6xxx_reg_lock(chip);
2510babc 3390 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
c9acece0 3391 mv88e6xxx_reg_unlock(chip);
2510babc
AL		 3392
3393 if (err)
3394 return err;
3395 }
3396
0dd12d54 3397 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
b516d453
AL		 3398 if (!bus)
3399 return -ENOMEM;
3400
0dd12d54 3401 mdio_bus = bus->priv;
a3c53be5 3402 mdio_bus->bus = bus;
0dd12d54 3403 mdio_bus->chip = chip;
a3c53be5
AL		 3404 INIT_LIST_HEAD(&mdio_bus->list);
3405 mdio_bus->external = external;
0dd12d54 3406
b516d453
AL		 3407 if (np) {
3408 bus->name = np->full_name;
f7ce9103 3409 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
b516d453
AL		 3410 } else {
3411 bus->name = "mv88e6xxx SMI";
3412 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3413 }
3414
3415 bus->read = mv88e6xxx_mdio_read;
3416 bus->write = mv88e6xxx_mdio_write;
fad09c73 3417 bus->parent = chip->dev;
b516d453 3418
6f88284f
AL		 3419 if (!external) {
3420 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3421 if (err)
3422 return err;
3423 }
3424
00e798c7 3425 err = of_mdiobus_register(bus, np);
b516d453 3426 if (err) {
fad09c73 3427 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
6f88284f 3428 mv88e6xxx_g2_irq_mdio_free(chip, bus);
a3c53be5 3429 return err;
b516d453 3430 }
a3c53be5
AL		 3431
3432 if (external)
3433 list_add_tail(&mdio_bus->list, &chip->mdios);
3434 else
3435 list_add(&mdio_bus->list, &chip->mdios);
b516d453
AL		 3436
3437 return 0;
a3c53be5 3438}
b516d453 3439
3126aeec
AL		 3440static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3441
3442{
3443 struct mv88e6xxx_mdio_bus *mdio_bus;
3444 struct mii_bus *bus;
3445
3446 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3447 bus = mdio_bus->bus;
3448
6f88284f
AL		 3449 if (!mdio_bus->external)
3450 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3451
3126aeec
AL		 3452 mdiobus_unregister(bus);
3453 }
3454}
3455
a3c53be5
AL		 3456static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3457 struct device_node *np)
3458{
a3c53be5
AL		 3459 struct device_node *child;
3460 int err;
3461
3462 /* Always register one mdio bus for the internal/default mdio
3463 * bus. This maybe represented in the device tree, but is
3464 * optional.
3465 */
3466 child = of_get_child_by_name(np, "mdio");
3467 err = mv88e6xxx_mdio_register(chip, child, false);
3468 if (err)
3469 return err;
3470
3471 /* Walk the device tree, and see if there are any other nodes
3472 * which say they are compatible with the external mdio
3473 * bus.
3474 */
3475 for_each_available_child_of_node(np, child) {
ceb96fae
AL		 3476 if (of_device_is_compatible(
3477 child, "marvell,mv88e6xxx-mdio-external")) {
a3c53be5 3478 err = mv88e6xxx_mdio_register(chip, child, true);
3126aeec
AL		 3479 if (err) {
3480 mv88e6xxx_mdios_unregister(chip);
78e42040 3481 of_node_put(child);
a3c53be5 3482 return err;
3126aeec 3483 }
a3c53be5
AL		 3484 }
3485 }
3486
3487 return 0;
b516d453
AL		 3488}
3489
855b1932
VD		 3490static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3491{
04bed143 3492 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3493
3494 return chip->eeprom_len;
3495}
3496
855b1932
VD		 3497static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3498 struct ethtool_eeprom *eeprom, u8 *data)
3499{
04bed143 3500 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3501 int err;
3502
ee4dc2e7
VD		 3503 if (!chip->info->ops->get_eeprom)
3504 return -EOPNOTSUPP;
855b1932 3505
c9acece0 3506 mv88e6xxx_reg_lock(chip);
ee4dc2e7 3507 err = chip->info->ops->get_eeprom(chip, eeprom, data);
c9acece0 3508 mv88e6xxx_reg_unlock(chip);
855b1932
VD		 3509
3510 if (err)
3511 return err;
3512
3513 eeprom->magic = 0xc3ec4951;
3514
3515 return 0;
3516}
3517
855b1932
VD		 3518static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3519 struct ethtool_eeprom *eeprom, u8 *data)
3520{
04bed143 3521 struct mv88e6xxx_chip *chip = ds->priv;
855b1932
VD		 3522 int err;
3523
ee4dc2e7
VD		 3524 if (!chip->info->ops->set_eeprom)
3525 return -EOPNOTSUPP;
3526
855b1932
VD		 3527 if (eeprom->magic != 0xc3ec4951)
3528 return -EINVAL;
3529
c9acece0 3530 mv88e6xxx_reg_lock(chip);
ee4dc2e7 3531 err = chip->info->ops->set_eeprom(chip, eeprom, data);
c9acece0 3532 mv88e6xxx_reg_unlock(chip);
855b1932
VD		 3533
3534 return err;
3535}
3536
b3469dd8 3537static const struct mv88e6xxx_ops mv88e6085_ops = {
4b325d8c 3538 /* MV88E6XXX_FAMILY_6097 */
93e18d61
VD		 3539 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3540 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3541 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3542 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 3543 .phy_read = mv88e6185_phy_ppu_read,
3544 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 3545 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3546 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 3547 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3548 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3549 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3550 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3551 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3552 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3553 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3554 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3555 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3556 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3557 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3558 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3559 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3560 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3561 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3562 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3563 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3564 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3565 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3566 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3567 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3568 .pot_clear = mv88e6xxx_g2_pot_clear,
a199d8b6
VD		 3569 .ppu_enable = mv88e6185_g1_ppu_enable,
3570 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3571 .reset = mv88e6185_g1_reset,
9e5baf9b 3572 .rmu_disable = mv88e6085_g1_rmu_disable,
f1394b78 3573 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3574 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 3575 .phylink_validate = mv88e6185_phylink_validate,
1baf0fac 3576 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
b3469dd8
VD		 3577};
3578
3579static const struct mv88e6xxx_ops mv88e6095_ops = {
4b325d8c 3580 /* MV88E6XXX_FAMILY_6095 */
93e18d61
VD		 3581 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3582 .ip_pri_map = mv88e6085_g1_ip_pri_map,
b073d4e2 3583 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 3584 .phy_read = mv88e6185_phy_ppu_read,
3585 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 3586 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3587 .port_sync_link = mv88e6185_port_sync_link,
f365c6f7 3588 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
56995cbc 3589 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a8b659e7
VO		 3590 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3591 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
a23b2961 3592 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2d2e1dd2 3593 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3594 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3595 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3596 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3597 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3598 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3599 .stats_get_stats = mv88e6095_stats_get_stats,
51c901a7 3600 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
f5be107c
CP		 3601 .serdes_power = mv88e6185_serdes_power,
3602 .serdes_get_lane = mv88e6185_serdes_get_lane,
3603 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
a199d8b6
VD		 3604 .ppu_enable = mv88e6185_g1_ppu_enable,
3605 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3606 .reset = mv88e6185_g1_reset,
f1394b78 3607 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 3608 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
6c422e34 3609 .phylink_validate = mv88e6185_phylink_validate,
1baf0fac 3610 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
b3469dd8
VD		 3611};
3612
7d381a02 3613static const struct mv88e6xxx_ops mv88e6097_ops = {
15da3cc8 3614 /* MV88E6XXX_FAMILY_6097 */
93e18d61
VD		 3615 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3616 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3617 .irl_init_all = mv88e6352_g2_irl_init_all,
7d381a02
SE		 3618 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3619 .phy_read = mv88e6xxx_g2_smi_phy_read,
3620 .phy_write = mv88e6xxx_g2_smi_phy_write,
3621 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3622 .port_sync_link = mv88e6185_port_sync_link,
f365c6f7 3623 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3624 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3625 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3626 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3627 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3628 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3629 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
0898432c 3630 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3631 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3632 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3633 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3634 .port_setup_message_port = mv88e6xxx_setup_message_port,
7d381a02 3635 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3636 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
7d381a02
SE		 3637 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3638 .stats_get_strings = mv88e6095_stats_get_strings,
3639 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3640 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3641 .set_egress_port = mv88e6095_g1_set_egress_port,
91eaa475 3642 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3643 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
f5be107c
CP		 3644 .serdes_power = mv88e6185_serdes_power,
3645 .serdes_get_lane = mv88e6185_serdes_get_lane,
3646 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
5c19bc8b
CP		 3647 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3648 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3649 .serdes_irq_status = mv88e6097_serdes_irq_status,
9e907d73 3650 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3651 .reset = mv88e6352_g1_reset,
9e5baf9b 3652 .rmu_disable = mv88e6085_g1_rmu_disable,
f1394b78 3653 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3654 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 3655 .phylink_validate = mv88e6185_phylink_validate,
1baf0fac 3656 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
7d381a02
SE		 3657};
3658
b3469dd8 3659static const struct mv88e6xxx_ops mv88e6123_ops = {
4b325d8c 3660 /* MV88E6XXX_FAMILY_6165 */
93e18d61
VD		 3661 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3662 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3663 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3664 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 3665 .phy_read = mv88e6xxx_g2_smi_phy_read,
3666 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3667 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3668 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 3669 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
56995cbc 3670 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a8b659e7
VO		 3671 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3672 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
c8c94891 3673 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3674 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3675 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3676 .port_setup_message_port = mv88e6xxx_setup_message_port,
0ac64c39 3677 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3678 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3679 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3680 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3681 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3682 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3683 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3684 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3685 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3686 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3687 .reset = mv88e6352_g1_reset,
23e8b470
AL		 3688 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3689 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3690 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3691 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 3692 .phylink_validate = mv88e6185_phylink_validate,
1baf0fac 3693 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
b3469dd8
VD		 3694};
3695
3696static const struct mv88e6xxx_ops mv88e6131_ops = {
4b325d8c 3697 /* MV88E6XXX_FAMILY_6185 */
93e18d61
VD		 3698 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3699 .ip_pri_map = mv88e6085_g1_ip_pri_map,
b073d4e2 3700 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 3701 .phy_read = mv88e6185_phy_ppu_read,
3702 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 3703 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3704 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 3705 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3706 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3707 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3708 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3709 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
56995cbc 3710 .port_set_ether_type = mv88e6351_port_set_ether_type,
a23b2961 3711 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
cd782656 3712 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3713 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3714 .port_pause_limit = mv88e6097_port_pause_limit,
54186b91 3715 .port_set_pause = mv88e6185_port_set_pause,
2d2e1dd2 3716 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3717 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3718 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3719 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3720 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3721 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3722 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3723 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3724 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3725 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3726 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
a199d8b6 3727 .ppu_enable = mv88e6185_g1_ppu_enable,
02317e68 3728 .set_cascade_port = mv88e6185_g1_set_cascade_port,
a199d8b6 3729 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 3730 .reset = mv88e6185_g1_reset,
f1394b78 3731 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 3732 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
6c422e34 3733 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 3734};
3735
990e27b0
VD		 3736static const struct mv88e6xxx_ops mv88e6141_ops = {
3737 /* MV88E6XXX_FAMILY_6341 */
93e18d61
VD		 3738 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3739 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3740 .irl_init_all = mv88e6352_g2_irl_init_all,
990e27b0
VD		 3741 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3742 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3743 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3744 .phy_read = mv88e6xxx_g2_smi_phy_read,
3745 .phy_write = mv88e6xxx_g2_smi_phy_write,
3746 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3747 .port_sync_link = mv88e6xxx_port_sync_link,
990e27b0 3748 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 3749 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
7cbbee05 3750 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
990e27b0 3751 .port_tag_remap = mv88e6095_port_tag_remap,
7da467d8 3752 .port_set_policy = mv88e6352_port_set_policy,
990e27b0 3753 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3754 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3755 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
990e27b0 3756 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3757 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
990e27b0 3758 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3759 .port_pause_limit = mv88e6097_port_pause_limit,
990e27b0
VD		 3760 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3761 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3762 .port_get_cmode = mv88e6352_port_get_cmode,
7a3007d2 3763 .port_set_cmode = mv88e6341_port_set_cmode,
121b8fe2 3764 .port_setup_message_port = mv88e6xxx_setup_message_port,
990e27b0 3765 .stats_snapshot = mv88e6390_g1_stats_snapshot,
11527f3c 3766 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
990e27b0
VD		 3767 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3768 .stats_get_strings = mv88e6320_stats_get_strings,
3769 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 3770 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3771 .set_egress_port = mv88e6390_g1_set_egress_port,
990e27b0
VD		 3772 .watchdog_ops = &mv88e6390_watchdog_ops,
3773 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 3774 .pot_clear = mv88e6xxx_g2_pot_clear,
990e27b0 3775 .reset = mv88e6352_g1_reset,
37094887 3776 .rmu_disable = mv88e6390_g1_rmu_disable,
c07fff34
MB		 3777 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3778 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3779 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3780 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
d3cf7d8f
MB		 3781 .serdes_power = mv88e6390_serdes_power,
3782 .serdes_get_lane = mv88e6341_serdes_get_lane,
a5a6858b
RK		 3783 /* Check status register pause & lpa register */
3784 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3785 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3786 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3787 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 3788 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 3789 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 3790 .serdes_irq_status = mv88e6390_serdes_irq_status,
a73ccd61 3791 .gpio_ops = &mv88e6352_gpio_ops,
a03b98d6
MB		 3792 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
3793 .serdes_get_strings = mv88e6390_serdes_get_strings,
3794 .serdes_get_stats = mv88e6390_serdes_get_stats,
953b0dcb
MB		 3795 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3796 .serdes_get_regs = mv88e6390_serdes_get_regs,
e3af71a3 3797 .phylink_validate = mv88e6341_phylink_validate,
990e27b0
VD		 3798};
3799
b3469dd8 3800static const struct mv88e6xxx_ops mv88e6161_ops = {
4b325d8c 3801 /* MV88E6XXX_FAMILY_6165 */
93e18d61
VD		 3802 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3803 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3804 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3805 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
ec8378bb
AL		 3806 .phy_read = mv88e6xxx_g2_smi_phy_read,
3807 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3808 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3809 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 3810 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3811 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3812 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3813 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3814 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3815 .port_set_ether_type = mv88e6351_port_set_ether_type,
ef70b111 3816 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3817 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3818 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3819 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3820 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3821 .port_setup_message_port = mv88e6xxx_setup_message_port,
a6da21bb 3822 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3823 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3824 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3825 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3826 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3827 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3828 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3829 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3830 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3831 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3832 .reset = mv88e6352_g1_reset,
23e8b470
AL		 3833 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3834 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3835 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3836 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
a469a612 3837 .avb_ops = &mv88e6165_avb_ops,
dfa54348 3838 .ptp_ops = &mv88e6165_ptp_ops,
6c422e34 3839 .phylink_validate = mv88e6185_phylink_validate,
fe230361 3840 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
b3469dd8
VD		 3841};
3842
3843static const struct mv88e6xxx_ops mv88e6165_ops = {
4b325d8c 3844 /* MV88E6XXX_FAMILY_6165 */
93e18d61
VD		 3845 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3846 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3847 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3848 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
efb3e74d
AL		 3849 .phy_read = mv88e6165_phy_read,
3850 .phy_write = mv88e6165_phy_write,
08ef7f10 3851 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3852 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 3853 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
c8c94891 3854 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3855 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3856 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 3857 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3858 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 3859 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3860 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3861 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3862 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3863 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3864 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3865 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3866 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3867 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3868 .reset = mv88e6352_g1_reset,
23e8b470
AL		 3869 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3870 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3871 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3872 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
a469a612 3873 .avb_ops = &mv88e6165_avb_ops,
dfa54348 3874 .ptp_ops = &mv88e6165_ptp_ops,
6c422e34 3875 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 3876};
3877
3878static const struct mv88e6xxx_ops mv88e6171_ops = {
4b325d8c 3879 /* MV88E6XXX_FAMILY_6351 */
93e18d61
VD		 3880 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3881 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3882 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3883 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3884 .phy_read = mv88e6xxx_g2_smi_phy_read,
3885 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3886 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3887 .port_sync_link = mv88e6xxx_port_sync_link,
94d66ae6 3888 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 3889 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3890 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3891 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3892 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3893 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3894 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3895 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3896 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3897 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3898 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3899 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3900 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 3901 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3902 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3903 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3904 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3905 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3906 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3907 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3908 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3909 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3910 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3911 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3912 .reset = mv88e6352_g1_reset,
23e8b470
AL		 3913 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3914 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3915 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3916 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 3917 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 3918};
3919
3920static const struct mv88e6xxx_ops mv88e6172_ops = {
4b325d8c 3921 /* MV88E6XXX_FAMILY_6352 */
93e18d61
VD		 3922 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3923 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3924 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 3925 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3926 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 3927 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3928 .phy_read = mv88e6xxx_g2_smi_phy_read,
3929 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3930 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3931 .port_sync_link = mv88e6xxx_port_sync_link,
a0a0f622 3932 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 3933 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
ef0a7318 3934 .port_tag_remap = mv88e6095_port_tag_remap,
f3a2cd32 3935 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 3936 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3937 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3938 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3939 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3940 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3941 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3942 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3943 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3944 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3945 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 3946 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3947 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 3948 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 3949 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3950 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 3951 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 3952 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3953 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 3954 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 3955 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 3956 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 3957 .reset = mv88e6352_g1_reset,
9e5baf9b 3958 .rmu_disable = mv88e6352_g1_rmu_disable,
23e8b470
AL		 3959 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3960 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 3961 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 3962 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
9db4a725 3963 .serdes_get_lane = mv88e6352_serdes_get_lane,
a5a6858b
RK		 3964 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3965 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3966 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3967 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
6d91782f 3968 .serdes_power = mv88e6352_serdes_power,
d3f88a24
AL		 3969 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3970 .serdes_get_regs = mv88e6352_serdes_get_regs,
a73ccd61 3971 .gpio_ops = &mv88e6352_gpio_ops,
6c422e34 3972 .phylink_validate = mv88e6352_phylink_validate,
b3469dd8
VD		 3973};
3974
3975static const struct mv88e6xxx_ops mv88e6175_ops = {
4b325d8c 3976 /* MV88E6XXX_FAMILY_6351 */
93e18d61
VD		 3977 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3978 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 3979 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 3980 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 3981 .phy_read = mv88e6xxx_g2_smi_phy_read,
3982 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 3983 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 3984 .port_sync_link = mv88e6xxx_port_sync_link,
94d66ae6 3985 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 3986 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 3987 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 3988 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 3989 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3990 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 3991 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 3992 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 3993 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 3994 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 3995 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 3996 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 3997 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 3998 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 3999 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4000 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4001 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4002 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4003 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4004 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4005 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4006 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4007 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4008 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4009 .reset = mv88e6352_g1_reset,
23e8b470
AL		 4010 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4011 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4012 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4013 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 4014 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 4015};
4016
4017static const struct mv88e6xxx_ops mv88e6176_ops = {
4b325d8c 4018 /* MV88E6XXX_FAMILY_6352 */
93e18d61
VD		 4019 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4020 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4021 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 4022 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4023 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 4024 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4025 .phy_read = mv88e6xxx_g2_smi_phy_read,
4026 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4027 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4028 .port_sync_link = mv88e6xxx_port_sync_link,
a0a0f622 4029 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4030 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
ef0a7318 4031 .port_tag_remap = mv88e6095_port_tag_remap,
f3a2cd32 4032 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4033 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4034 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4035 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4036 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4037 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4038 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4039 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4040 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4041 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4042 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4043 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4044 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4045 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4046 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4047 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4048 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4049 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4050 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4051 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4052 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4053 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4054 .reset = mv88e6352_g1_reset,
9e5baf9b 4055 .rmu_disable = mv88e6352_g1_rmu_disable,
23e8b470
AL		 4056 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4057 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4058 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4059 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
9db4a725 4060 .serdes_get_lane = mv88e6352_serdes_get_lane,
a5a6858b
RK		 4061 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4062 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4063 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4064 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
6d91782f 4065 .serdes_power = mv88e6352_serdes_power,
4241ef52 4066 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
61a46b41 4067 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
907b9b9f 4068 .serdes_irq_status = mv88e6352_serdes_irq_status,
d3f88a24
AL		 4069 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4070 .serdes_get_regs = mv88e6352_serdes_get_regs,
a73ccd61 4071 .gpio_ops = &mv88e6352_gpio_ops,
6c422e34 4072 .phylink_validate = mv88e6352_phylink_validate,
b3469dd8
VD		 4073};
4074
4075static const struct mv88e6xxx_ops mv88e6185_ops = {
4b325d8c 4076 /* MV88E6XXX_FAMILY_6185 */
93e18d61
VD		 4077 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4078 .ip_pri_map = mv88e6085_g1_ip_pri_map,
b073d4e2 4079 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
7e20cfb5
VD		 4080 .phy_read = mv88e6185_phy_ppu_read,
4081 .phy_write = mv88e6185_phy_ppu_write,
08ef7f10 4082 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4083 .port_sync_link = mv88e6185_port_sync_link,
f365c6f7 4084 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
56995cbc 4085 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
a8b659e7
VO		 4086 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4087 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
ef70b111 4088 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
a23b2961 4089 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
54186b91 4090 .port_set_pause = mv88e6185_port_set_pause,
2d2e1dd2 4091 .port_get_cmode = mv88e6185_port_get_cmode,
121b8fe2 4092 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4093 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
40cff8fc 4094 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4095 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4096 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4097 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4098 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4099 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4100 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4101 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
f5be107c
CP		 4102 .serdes_power = mv88e6185_serdes_power,
4103 .serdes_get_lane = mv88e6185_serdes_get_lane,
4104 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
02317e68 4105 .set_cascade_port = mv88e6185_g1_set_cascade_port,
a199d8b6
VD		 4106 .ppu_enable = mv88e6185_g1_ppu_enable,
4107 .ppu_disable = mv88e6185_g1_ppu_disable,
17e708ba 4108 .reset = mv88e6185_g1_reset,
f1394b78 4109 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 4110 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
6c422e34 4111 .phylink_validate = mv88e6185_phylink_validate,
1baf0fac 4112 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
b3469dd8
VD		 4113};
4114
1a3b39ec 4115static const struct mv88e6xxx_ops mv88e6190_ops = {
4b325d8c 4116 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4117 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4118 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4119 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4120 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4121 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4122 .phy_read = mv88e6xxx_g2_smi_phy_read,
4123 .phy_write = mv88e6xxx_g2_smi_phy_write,
4124 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4125 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4126 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4127 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
7cbbee05 4128 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
ef0a7318 4129 .port_tag_remap = mv88e6390_port_tag_remap,
f3a2cd32 4130 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4131 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4132 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4133 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4134 .port_set_ether_type = mv88e6351_port_set_ether_type,
e8b34c67 4135 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
0898432c 4136 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4137 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4138 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4139 .port_get_cmode = mv88e6352_port_get_cmode,
fdc71eea 4140 .port_set_cmode = mv88e6390_port_set_cmode,
121b8fe2 4141 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4142 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4143 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4144 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4145 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4146 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4147 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4148 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4149 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4150 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4151 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4152 .reset = mv88e6352_g1_reset,
9e5baf9b 4153 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4154 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4155 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4156 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4157 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 4158 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4159 .serdes_get_lane = mv88e6390_serdes_get_lane,
a5a6858b
RK		 4160 /* Check status register pause & lpa register */
4161 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4162 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4163 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4164 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4165 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4166 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4167 .serdes_irq_status = mv88e6390_serdes_irq_status,
4262c38d
AL		 4168 .serdes_get_strings = mv88e6390_serdes_get_strings,
4169 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4170 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4171 .serdes_get_regs = mv88e6390_serdes_get_regs,
a73ccd61 4172 .gpio_ops = &mv88e6352_gpio_ops,
6c422e34 4173 .phylink_validate = mv88e6390_phylink_validate,
1a3b39ec
AL		 4174};
4175
4176static const struct mv88e6xxx_ops mv88e6190x_ops = {
4b325d8c 4177 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4178 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4179 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4180 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4181 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4182 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4183 .phy_read = mv88e6xxx_g2_smi_phy_read,
4184 .phy_write = mv88e6xxx_g2_smi_phy_write,
4185 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4186 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4187 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4188 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
7cbbee05 4189 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
ef0a7318 4190 .port_tag_remap = mv88e6390_port_tag_remap,
f3a2cd32 4191 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4192 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4193 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4194 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4195 .port_set_ether_type = mv88e6351_port_set_ether_type,
e8b34c67 4196 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
0898432c 4197 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4198 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4199 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4200 .port_get_cmode = mv88e6352_port_get_cmode,
fdc71eea 4201 .port_set_cmode = mv88e6390x_port_set_cmode,
121b8fe2 4202 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4203 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4204 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4205 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4206 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4207 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4208 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4209 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4210 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4211 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4212 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4213 .reset = mv88e6352_g1_reset,
9e5baf9b 4214 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4215 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4216 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4217 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4218 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
d3cf7d8f 4219 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4220 .serdes_get_lane = mv88e6390x_serdes_get_lane,
a5a6858b
RK		 4221 /* Check status register pause & lpa register */
4222 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4223 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4224 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4225 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4226 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4227 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4228 .serdes_irq_status = mv88e6390_serdes_irq_status,
4262c38d
AL		 4229 .serdes_get_strings = mv88e6390_serdes_get_strings,
4230 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4231 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4232 .serdes_get_regs = mv88e6390_serdes_get_regs,
a73ccd61 4233 .gpio_ops = &mv88e6352_gpio_ops,
6c422e34 4234 .phylink_validate = mv88e6390x_phylink_validate,
1a3b39ec
AL		 4235};
4236
4237static const struct mv88e6xxx_ops mv88e6191_ops = {
4b325d8c 4238 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4239 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4240 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4241 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4242 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4243 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4244 .phy_read = mv88e6xxx_g2_smi_phy_read,
4245 .phy_write = mv88e6xxx_g2_smi_phy_write,
4246 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4247 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4248 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4249 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
7cbbee05 4250 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
ef0a7318 4251 .port_tag_remap = mv88e6390_port_tag_remap,
56995cbc 4252 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4253 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4254 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4255 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 4256 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4257 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4258 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4259 .port_get_cmode = mv88e6352_port_get_cmode,
fdc71eea 4260 .port_set_cmode = mv88e6390_port_set_cmode,
121b8fe2 4261 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4262 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4263 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4264 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4265 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4266 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4267 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4268 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4269 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4270 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4271 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4272 .reset = mv88e6352_g1_reset,
9e5baf9b 4273 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4274 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4275 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4276 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4277 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 4278 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4279 .serdes_get_lane = mv88e6390_serdes_get_lane,
a5a6858b
RK		 4280 /* Check status register pause & lpa register */
4281 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4282 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4283 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4284 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4285 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4286 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4287 .serdes_irq_status = mv88e6390_serdes_irq_status,
4262c38d
AL		 4288 .serdes_get_strings = mv88e6390_serdes_get_strings,
4289 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4290 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4291 .serdes_get_regs = mv88e6390_serdes_get_regs,
6d2ac8ee
AL		 4292 .avb_ops = &mv88e6390_avb_ops,
4293 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4294 .phylink_validate = mv88e6390_phylink_validate,
1a3b39ec
AL		 4295};
4296
b3469dd8 4297static const struct mv88e6xxx_ops mv88e6240_ops = {
4b325d8c 4298 /* MV88E6XXX_FAMILY_6352 */
93e18d61
VD		 4299 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4300 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4301 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 4302 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4303 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 4304 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4305 .phy_read = mv88e6xxx_g2_smi_phy_read,
4306 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4307 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4308 .port_sync_link = mv88e6xxx_port_sync_link,
a0a0f622 4309 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4310 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
ef0a7318 4311 .port_tag_remap = mv88e6095_port_tag_remap,
f3a2cd32 4312 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4313 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4314 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4315 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4316 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4317 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4318 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4319 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4320 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4321 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4322 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4323 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4324 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4325 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4326 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4327 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4328 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4329 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4330 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4331 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4332 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4333 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4334 .reset = mv88e6352_g1_reset,
9e5baf9b 4335 .rmu_disable = mv88e6352_g1_rmu_disable,
23e8b470
AL		 4336 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4337 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4338 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4339 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
9db4a725 4340 .serdes_get_lane = mv88e6352_serdes_get_lane,
a5a6858b
RK		 4341 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4342 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4343 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4344 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
6d91782f 4345 .serdes_power = mv88e6352_serdes_power,
4241ef52 4346 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
61a46b41 4347 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
907b9b9f 4348 .serdes_irq_status = mv88e6352_serdes_irq_status,
d3f88a24
AL		 4349 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4350 .serdes_get_regs = mv88e6352_serdes_get_regs,
a73ccd61 4351 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4352 .avb_ops = &mv88e6352_avb_ops,
6d2ac8ee 4353 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4354 .phylink_validate = mv88e6352_phylink_validate,
b3469dd8
VD		 4355};
4356
1f71836f
RV		 4357static const struct mv88e6xxx_ops mv88e6250_ops = {
4358 /* MV88E6XXX_FAMILY_6250 */
4359 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4360 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4361 .irl_init_all = mv88e6352_g2_irl_init_all,
4362 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4363 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4364 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4365 .phy_read = mv88e6xxx_g2_smi_phy_read,
4366 .phy_write = mv88e6xxx_g2_smi_phy_write,
4367 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4368 .port_sync_link = mv88e6xxx_port_sync_link,
1f71836f 4369 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4370 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
1f71836f
RV		 4371 .port_tag_remap = mv88e6095_port_tag_remap,
4372 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4373 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4374 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
1f71836f
RV		 4375 .port_set_ether_type = mv88e6351_port_set_ether_type,
4376 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4377 .port_pause_limit = mv88e6097_port_pause_limit,
4378 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
1f71836f
RV		 4379 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4380 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4381 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4382 .stats_get_strings = mv88e6250_stats_get_strings,
4383 .stats_get_stats = mv88e6250_stats_get_stats,
4384 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4385 .set_egress_port = mv88e6095_g1_set_egress_port,
4386 .watchdog_ops = &mv88e6250_watchdog_ops,
4387 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4388 .pot_clear = mv88e6xxx_g2_pot_clear,
4389 .reset = mv88e6250_g1_reset,
67c9ed1c 4390 .vtu_getnext = mv88e6185_g1_vtu_getnext,
b28f3f3c 4391 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
71509614
HF		 4392 .avb_ops = &mv88e6352_avb_ops,
4393 .ptp_ops = &mv88e6250_ptp_ops,
1f71836f
RV		 4394 .phylink_validate = mv88e6065_phylink_validate,
4395};
4396
1a3b39ec 4397static const struct mv88e6xxx_ops mv88e6290_ops = {
4b325d8c 4398 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4399 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4400 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4401 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4402 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4403 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4404 .phy_read = mv88e6xxx_g2_smi_phy_read,
4405 .phy_write = mv88e6xxx_g2_smi_phy_write,
4406 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4407 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4408 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4409 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
7cbbee05 4410 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
ef0a7318 4411 .port_tag_remap = mv88e6390_port_tag_remap,
f3a2cd32 4412 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4413 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4414 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4415 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4416 .port_set_ether_type = mv88e6351_port_set_ether_type,
0898432c 4417 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4418 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4419 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4420 .port_get_cmode = mv88e6352_port_get_cmode,
fdc71eea 4421 .port_set_cmode = mv88e6390_port_set_cmode,
121b8fe2 4422 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4423 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4424 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4425 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4426 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4427 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4428 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4429 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4430 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4431 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4432 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4433 .reset = mv88e6352_g1_reset,
9e5baf9b 4434 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4435 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4436 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4437 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4438 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 4439 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4440 .serdes_get_lane = mv88e6390_serdes_get_lane,
a5a6858b
RK		 4441 /* Check status register pause & lpa register */
4442 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4443 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4444 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4445 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4446 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4447 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4448 .serdes_irq_status = mv88e6390_serdes_irq_status,
4262c38d
AL		 4449 .serdes_get_strings = mv88e6390_serdes_get_strings,
4450 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4451 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4452 .serdes_get_regs = mv88e6390_serdes_get_regs,
a73ccd61 4453 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4454 .avb_ops = &mv88e6390_avb_ops,
6d2ac8ee 4455 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4456 .phylink_validate = mv88e6390_phylink_validate,
1a3b39ec
AL		 4457};
4458
b3469dd8 4459static const struct mv88e6xxx_ops mv88e6320_ops = {
4b325d8c 4460 /* MV88E6XXX_FAMILY_6320 */
93e18d61
VD		 4461 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4462 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4463 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 4464 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4465 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 4466 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4467 .phy_read = mv88e6xxx_g2_smi_phy_read,
4468 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4469 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4470 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 4471 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 4472 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 4473 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4474 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4475 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4476 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4477 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4478 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4479 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4480 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4481 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4482 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4483 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4484 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4485 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4486 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4487 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 4488 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 4489 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4490 .set_egress_port = mv88e6095_g1_set_egress_port,
9c7f37e5 4491 .watchdog_ops = &mv88e6390_watchdog_ops,
51c901a7 4492 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4493 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4494 .reset = mv88e6352_g1_reset,
f1394b78 4495 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 4496 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
a73ccd61 4497 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4498 .avb_ops = &mv88e6352_avb_ops,
6d2ac8ee 4499 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4500 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 4501};
4502
4503static const struct mv88e6xxx_ops mv88e6321_ops = {
bd807204 4504 /* MV88E6XXX_FAMILY_6320 */
93e18d61
VD		 4505 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4506 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4507 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 4508 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4509 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 4510 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4511 .phy_read = mv88e6xxx_g2_smi_phy_read,
4512 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4513 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4514 .port_sync_link = mv88e6xxx_port_sync_link,
f365c6f7 4515 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 4516 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 4517 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4518 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4519 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4520 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4521 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4522 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4523 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4524 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4525 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4526 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4527 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4528 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4529 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4530 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4531 .stats_get_strings = mv88e6320_stats_get_strings,
052f947f 4532 .stats_get_stats = mv88e6320_stats_get_stats,
fa8d1179
VD		 4533 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4534 .set_egress_port = mv88e6095_g1_set_egress_port,
9c7f37e5 4535 .watchdog_ops = &mv88e6390_watchdog_ops,
17e708ba 4536 .reset = mv88e6352_g1_reset,
f1394b78 4537 .vtu_getnext = mv88e6185_g1_vtu_getnext,
0ad5daf6 4538 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
a73ccd61 4539 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4540 .avb_ops = &mv88e6352_avb_ops,
6d2ac8ee 4541 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4542 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 4543};
4544
16e329ae
VD		 4545static const struct mv88e6xxx_ops mv88e6341_ops = {
4546 /* MV88E6XXX_FAMILY_6341 */
93e18d61
VD		 4547 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4548 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4549 .irl_init_all = mv88e6352_g2_irl_init_all,
16e329ae
VD		 4550 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4551 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4552 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4553 .phy_read = mv88e6xxx_g2_smi_phy_read,
4554 .phy_write = mv88e6xxx_g2_smi_phy_write,
4555 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4556 .port_sync_link = mv88e6xxx_port_sync_link,
16e329ae 4557 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4558 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
7cbbee05 4559 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
16e329ae 4560 .port_tag_remap = mv88e6095_port_tag_remap,
7da467d8 4561 .port_set_policy = mv88e6352_port_set_policy,
16e329ae 4562 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4563 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4564 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
16e329ae 4565 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4566 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
16e329ae 4567 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4568 .port_pause_limit = mv88e6097_port_pause_limit,
16e329ae
VD		 4569 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4570 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4571 .port_get_cmode = mv88e6352_port_get_cmode,
7a3007d2 4572 .port_set_cmode = mv88e6341_port_set_cmode,
121b8fe2 4573 .port_setup_message_port = mv88e6xxx_setup_message_port,
16e329ae 4574 .stats_snapshot = mv88e6390_g1_stats_snapshot,
11527f3c 4575 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
16e329ae
VD		 4576 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4577 .stats_get_strings = mv88e6320_stats_get_strings,
4578 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4579 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4580 .set_egress_port = mv88e6390_g1_set_egress_port,
16e329ae
VD		 4581 .watchdog_ops = &mv88e6390_watchdog_ops,
4582 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4583 .pot_clear = mv88e6xxx_g2_pot_clear,
16e329ae 4584 .reset = mv88e6352_g1_reset,
37094887 4585 .rmu_disable = mv88e6390_g1_rmu_disable,
c07fff34
MB		 4586 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4587 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4588 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4589 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
d3cf7d8f
MB		 4590 .serdes_power = mv88e6390_serdes_power,
4591 .serdes_get_lane = mv88e6341_serdes_get_lane,
a5a6858b
RK		 4592 /* Check status register pause & lpa register */
4593 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4594 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4595 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4596 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4597 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4598 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4599 .serdes_irq_status = mv88e6390_serdes_irq_status,
a73ccd61 4600 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4601 .avb_ops = &mv88e6390_avb_ops,
6d2ac8ee 4602 .ptp_ops = &mv88e6352_ptp_ops,
a03b98d6
MB		 4603 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4604 .serdes_get_strings = mv88e6390_serdes_get_strings,
4605 .serdes_get_stats = mv88e6390_serdes_get_stats,
953b0dcb
MB		 4606 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4607 .serdes_get_regs = mv88e6390_serdes_get_regs,
e3af71a3 4608 .phylink_validate = mv88e6341_phylink_validate,
16e329ae
VD		 4609};
4610
b3469dd8 4611static const struct mv88e6xxx_ops mv88e6350_ops = {
4b325d8c 4612 /* MV88E6XXX_FAMILY_6351 */
93e18d61
VD		 4613 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4614 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4615 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 4616 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4617 .phy_read = mv88e6xxx_g2_smi_phy_read,
4618 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4619 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4620 .port_sync_link = mv88e6xxx_port_sync_link,
94d66ae6 4621 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4622 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 4623 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 4624 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4625 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4626 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4627 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4628 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4629 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4630 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4631 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4632 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4633 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4634 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4635 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4636 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4637 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4638 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4639 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4640 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4641 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4642 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4643 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4644 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4645 .reset = mv88e6352_g1_reset,
23e8b470
AL		 4646 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4647 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4648 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4649 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
6c422e34 4650 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 4651};
4652
4653static const struct mv88e6xxx_ops mv88e6351_ops = {
4b325d8c 4654 /* MV88E6XXX_FAMILY_6351 */
93e18d61
VD		 4655 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4656 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4657 .irl_init_all = mv88e6352_g2_irl_init_all,
b073d4e2 4658 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4659 .phy_read = mv88e6xxx_g2_smi_phy_read,
4660 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4661 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4662 .port_sync_link = mv88e6xxx_port_sync_link,
94d66ae6 4663 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4664 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
ef0a7318 4665 .port_tag_remap = mv88e6095_port_tag_remap,
56995cbc 4666 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4667 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4668 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4669 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4670 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4671 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4672 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4673 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4674 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4675 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4676 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4677 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4678 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4679 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4680 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4681 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4682 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4683 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4684 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4685 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4686 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4687 .reset = mv88e6352_g1_reset,
23e8b470
AL		 4688 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4689 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4690 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4691 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
0d632c3d 4692 .avb_ops = &mv88e6352_avb_ops,
6d2ac8ee 4693 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4694 .phylink_validate = mv88e6185_phylink_validate,
b3469dd8
VD		 4695};
4696
4697static const struct mv88e6xxx_ops mv88e6352_ops = {
4b325d8c 4698 /* MV88E6XXX_FAMILY_6352 */
93e18d61
VD		 4699 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4700 .ip_pri_map = mv88e6085_g1_ip_pri_map,
cd8da8bb 4701 .irl_init_all = mv88e6352_g2_irl_init_all,
ee4dc2e7
VD		 4702 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4703 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
b073d4e2 4704 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
b3469dd8
VD		 4705 .phy_read = mv88e6xxx_g2_smi_phy_read,
4706 .phy_write = mv88e6xxx_g2_smi_phy_write,
08ef7f10 4707 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4708 .port_sync_link = mv88e6xxx_port_sync_link,
a0a0f622 4709 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
f365c6f7 4710 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
ef0a7318 4711 .port_tag_remap = mv88e6095_port_tag_remap,
f3a2cd32 4712 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4713 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4714 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4715 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4716 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4717 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4718 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4719 .port_pause_limit = mv88e6097_port_pause_limit,
c8c94891 4720 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4721 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4722 .port_get_cmode = mv88e6352_port_get_cmode,
121b8fe2 4723 .port_setup_message_port = mv88e6xxx_setup_message_port,
a605a0fe 4724 .stats_snapshot = mv88e6320_g1_stats_snapshot,
40cff8fc 4725 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
dfafe449
AL		 4726 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4727 .stats_get_strings = mv88e6095_stats_get_strings,
052f947f 4728 .stats_get_stats = mv88e6095_stats_get_stats,
fa8d1179
VD		 4729 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4730 .set_egress_port = mv88e6095_g1_set_egress_port,
fcd25166 4731 .watchdog_ops = &mv88e6097_watchdog_ops,
51c901a7 4732 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
9e907d73 4733 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4734 .reset = mv88e6352_g1_reset,
9e5baf9b 4735 .rmu_disable = mv88e6352_g1_rmu_disable,
23e8b470
AL		 4736 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4737 .atu_set_hash = mv88e6165_g1_atu_set_hash,
f1394b78 4738 .vtu_getnext = mv88e6352_g1_vtu_getnext,
0ad5daf6 4739 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
9db4a725 4740 .serdes_get_lane = mv88e6352_serdes_get_lane,
a5a6858b
RK		 4741 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4742 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4743 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4744 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
6d91782f 4745 .serdes_power = mv88e6352_serdes_power,
4241ef52 4746 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
61a46b41 4747 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
907b9b9f 4748 .serdes_irq_status = mv88e6352_serdes_irq_status,
a73ccd61 4749 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4750 .avb_ops = &mv88e6352_avb_ops,
6d2ac8ee 4751 .ptp_ops = &mv88e6352_ptp_ops,
cda9f4aa
AL		 4752 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4753 .serdes_get_strings = mv88e6352_serdes_get_strings,
4754 .serdes_get_stats = mv88e6352_serdes_get_stats,
d3f88a24
AL		 4755 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4756 .serdes_get_regs = mv88e6352_serdes_get_regs,
6c422e34 4757 .phylink_validate = mv88e6352_phylink_validate,
b3469dd8
VD		 4758};
4759
1a3b39ec 4760static const struct mv88e6xxx_ops mv88e6390_ops = {
4b325d8c 4761 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4762 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4763 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4764 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4765 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4766 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4767 .phy_read = mv88e6xxx_g2_smi_phy_read,
4768 .phy_write = mv88e6xxx_g2_smi_phy_write,
4769 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4770 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4771 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4772 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
7cbbee05 4773 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
ef0a7318 4774 .port_tag_remap = mv88e6390_port_tag_remap,
f3a2cd32 4775 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4776 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4777 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4778 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4779 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4780 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4781 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4782 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4783 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4784 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4785 .port_get_cmode = mv88e6352_port_get_cmode,
fdc71eea 4786 .port_set_cmode = mv88e6390_port_set_cmode,
121b8fe2 4787 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4788 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4789 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4790 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4791 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4792 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4793 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4794 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4795 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4796 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4797 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4798 .reset = mv88e6352_g1_reset,
9e5baf9b 4799 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4800 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4801 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4802 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4803 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
6335e9f2 4804 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4805 .serdes_get_lane = mv88e6390_serdes_get_lane,
a5a6858b
RK		 4806 /* Check status register pause & lpa register */
4807 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4808 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4809 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4810 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4811 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4812 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4813 .serdes_irq_status = mv88e6390_serdes_irq_status,
a73ccd61 4814 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4815 .avb_ops = &mv88e6390_avb_ops,
6d2ac8ee 4816 .ptp_ops = &mv88e6352_ptp_ops,
0df95287
NY		 4817 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4818 .serdes_get_strings = mv88e6390_serdes_get_strings,
4819 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4820 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4821 .serdes_get_regs = mv88e6390_serdes_get_regs,
6c422e34 4822 .phylink_validate = mv88e6390_phylink_validate,
1a3b39ec
AL		 4823};
4824
4825static const struct mv88e6xxx_ops mv88e6390x_ops = {
4b325d8c 4826 /* MV88E6XXX_FAMILY_6390 */
ea89098e 4827 .setup_errata = mv88e6390_setup_errata,
cd8da8bb 4828 .irl_init_all = mv88e6390_g2_irl_init_all,
98fc3c6f
VD		 4829 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4830 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
1a3b39ec
AL		 4831 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4832 .phy_read = mv88e6xxx_g2_smi_phy_read,
4833 .phy_write = mv88e6xxx_g2_smi_phy_write,
4834 .port_set_link = mv88e6xxx_port_set_link,
4efe7662 4835 .port_sync_link = mv88e6xxx_port_sync_link,
1a3b39ec 4836 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
f365c6f7 4837 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
7cbbee05 4838 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
ef0a7318 4839 .port_tag_remap = mv88e6390_port_tag_remap,
f3a2cd32 4840 .port_set_policy = mv88e6352_port_set_policy,
56995cbc 4841 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
a8b659e7
VO		 4842 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4843 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
56995cbc 4844 .port_set_ether_type = mv88e6351_port_set_ether_type,
cd782656 4845 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
ef70b111 4846 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
0898432c 4847 .port_pause_limit = mv88e6390_port_pause_limit,
c8c94891 4848 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
9dbfb4e1 4849 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2d2e1dd2 4850 .port_get_cmode = mv88e6352_port_get_cmode,
b3dce4da 4851 .port_set_cmode = mv88e6390x_port_set_cmode,
121b8fe2 4852 .port_setup_message_port = mv88e6xxx_setup_message_port,
79523473 4853 .stats_snapshot = mv88e6390_g1_stats_snapshot,
de227387 4854 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
dfafe449
AL		 4855 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4856 .stats_get_strings = mv88e6320_stats_get_strings,
e0d8b615 4857 .stats_get_stats = mv88e6390_stats_get_stats,
fa8d1179
VD		 4858 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4859 .set_egress_port = mv88e6390_g1_set_egress_port,
61303736 4860 .watchdog_ops = &mv88e6390_watchdog_ops,
6e55f698 4861 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
9e907d73 4862 .pot_clear = mv88e6xxx_g2_pot_clear,
17e708ba 4863 .reset = mv88e6352_g1_reset,
9e5baf9b 4864 .rmu_disable = mv88e6390_g1_rmu_disable,
23e8b470
AL		 4865 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4866 .atu_set_hash = mv88e6165_g1_atu_set_hash,
931d1822
VD		 4867 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4868 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
d3cf7d8f 4869 .serdes_power = mv88e6390_serdes_power,
17deaf5c 4870 .serdes_get_lane = mv88e6390x_serdes_get_lane,
a5a6858b
RK		 4871 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4872 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4873 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4874 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4241ef52 4875 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
61a46b41 4876 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
907b9b9f 4877 .serdes_irq_status = mv88e6390_serdes_irq_status,
4262c38d
AL		 4878 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4879 .serdes_get_strings = mv88e6390_serdes_get_strings,
4880 .serdes_get_stats = mv88e6390_serdes_get_stats,
bf3504ce
AL		 4881 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4882 .serdes_get_regs = mv88e6390_serdes_get_regs,
a73ccd61 4883 .gpio_ops = &mv88e6352_gpio_ops,
0d632c3d 4884 .avb_ops = &mv88e6390_avb_ops,
6d2ac8ee 4885 .ptp_ops = &mv88e6352_ptp_ops,
6c422e34 4886 .phylink_validate = mv88e6390x_phylink_validate,
1a3b39ec
AL		 4887};
4888
de776d0d
PS		 4889static const struct mv88e6xxx_ops mv88e6393x_ops = {
4890 /* MV88E6XXX_FAMILY_6393 */
4891 .setup_errata = mv88e6393x_serdes_setup_errata,
4892 .irl_init_all = mv88e6390_g2_irl_init_all,
4893 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4894 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4895 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4896 .phy_read = mv88e6xxx_g2_smi_phy_read,
4897 .phy_write = mv88e6xxx_g2_smi_phy_write,
4898 .port_set_link = mv88e6xxx_port_set_link,
4899 .port_sync_link = mv88e6xxx_port_sync_link,
4900 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4901 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4902 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4903 .port_tag_remap = mv88e6390_port_tag_remap,
6584b260 4904 .port_set_policy = mv88e6393x_port_set_policy,
de776d0d
PS		 4905 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4906 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4907 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4908 .port_set_ether_type = mv88e6393x_port_set_ether_type,
4909 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4910 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4911 .port_pause_limit = mv88e6390_port_pause_limit,
4912 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4913 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4914 .port_get_cmode = mv88e6352_port_get_cmode,
4915 .port_set_cmode = mv88e6393x_port_set_cmode,
4916 .port_setup_message_port = mv88e6xxx_setup_message_port,
4917 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4918 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4919 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4920 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4921 .stats_get_strings = mv88e6320_stats_get_strings,
4922 .stats_get_stats = mv88e6390_stats_get_stats,
4923 /* .set_cpu_port is missing because this family does not support a global
4924 * CPU port, only per port CPU port which is set via
4925 * .port_set_upstream_port method.
4926 */
4927 .set_egress_port = mv88e6393x_set_egress_port,
4928 .watchdog_ops = &mv88e6390_watchdog_ops,
4929 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4930 .pot_clear = mv88e6xxx_g2_pot_clear,
4931 .reset = mv88e6352_g1_reset,
4932 .rmu_disable = mv88e6390_g1_rmu_disable,
4933 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4934 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4935 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4936 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4937 .serdes_power = mv88e6393x_serdes_power,
4938 .serdes_get_lane = mv88e6393x_serdes_get_lane,
4939 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4940 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4941 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4942 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4943 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4944 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4945 .serdes_irq_status = mv88e6393x_serdes_irq_status,
4946 /* TODO: serdes stats */
4947 .gpio_ops = &mv88e6352_gpio_ops,
4948 .avb_ops = &mv88e6390_avb_ops,
4949 .ptp_ops = &mv88e6352_ptp_ops,
4950 .phylink_validate = mv88e6393x_phylink_validate,
4951};
4952
f81ec90f
VD		 4953static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4954 [MV88E6085] = {
107fcc10 4955 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
f81ec90f
VD		 4956 .family = MV88E6XXX_FAMILY_6097,
4957 .name = "Marvell 88E6085",
4958 .num_databases = 4096,
d9ea5620 4959 .num_macs = 8192,
f81ec90f 4960 .num_ports = 10,
bc393155 4961 .num_internal_phys = 5,
3cf3c846 4962 .max_vid = 4095,
9dddd478 4963 .port_base_addr = 0x10,
9255bacd 4964 .phy_base_addr = 0x0,
a935c052 4965 .global1_addr = 0x1b,
9069c13a 4966 .global2_addr = 0x1c,
acddbd21 4967 .age_time_coeff = 15000,
dc30c35b 4968 .g1_irqs = 8,
d6c5e6af 4969 .g2_irqs = 10,
e606ca36 4970 .atu_move_port_mask = 0xf,
f3645652 4971 .pvt = true,
b3e05aa1 4972 .multi_chip = true,
b3469dd8 4973 .ops = &mv88e6085_ops,
f81ec90f
VD		 4974 },
4975
4976 [MV88E6095] = {
107fcc10 4977 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
f81ec90f
VD		 4978 .family = MV88E6XXX_FAMILY_6095,
4979 .name = "Marvell 88E6095/88E6095F",
4980 .num_databases = 256,
d9ea5620 4981 .num_macs = 8192,
f81ec90f 4982 .num_ports = 11,
bc393155 4983 .num_internal_phys = 0,
3cf3c846 4984 .max_vid = 4095,
9dddd478 4985 .port_base_addr = 0x10,
9255bacd 4986 .phy_base_addr = 0x0,
a935c052 4987 .global1_addr = 0x1b,
9069c13a 4988 .global2_addr = 0x1c,
acddbd21 4989 .age_time_coeff = 15000,
dc30c35b 4990 .g1_irqs = 8,
e606ca36 4991 .atu_move_port_mask = 0xf,
b3e05aa1 4992 .multi_chip = true,
b3469dd8 4993 .ops = &mv88e6095_ops,
f81ec90f
VD		 4994 },
4995
7d381a02 4996 [MV88E6097] = {
107fcc10 4997 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
7d381a02
SE		 4998 .family = MV88E6XXX_FAMILY_6097,
4999 .name = "Marvell 88E6097/88E6097F",
5000 .num_databases = 4096,
d9ea5620 5001 .num_macs = 8192,
7d381a02 5002 .num_ports = 11,
bc393155 5003 .num_internal_phys = 8,
3cf3c846 5004 .max_vid = 4095,
7d381a02 5005 .port_base_addr = 0x10,
9255bacd 5006 .phy_base_addr = 0x0,
7d381a02 5007 .global1_addr = 0x1b,
9069c13a 5008 .global2_addr = 0x1c,
7d381a02 5009 .age_time_coeff = 15000,
c534178b 5010 .g1_irqs = 8,
d6c5e6af 5011 .g2_irqs = 10,
e606ca36 5012 .atu_move_port_mask = 0xf,
f3645652 5013 .pvt = true,
b3e05aa1 5014 .multi_chip = true,
670bb80f 5015 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
7d381a02
SE		 5016 .ops = &mv88e6097_ops,
5017 },
5018
f81ec90f 5019 [MV88E6123] = {
107fcc10 5020 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
f81ec90f
VD		 5021 .family = MV88E6XXX_FAMILY_6165,
5022 .name = "Marvell 88E6123",
5023 .num_databases = 4096,
d9ea5620 5024 .num_macs = 1024,
f81ec90f 5025 .num_ports = 3,
bc393155 5026 .num_internal_phys = 5,
3cf3c846 5027 .max_vid = 4095,
9dddd478 5028 .port_base_addr = 0x10,
9255bacd 5029 .phy_base_addr = 0x0,
a935c052 5030 .global1_addr = 0x1b,
9069c13a 5031 .global2_addr = 0x1c,
acddbd21 5032 .age_time_coeff = 15000,
dc30c35b 5033 .g1_irqs = 9,
d6c5e6af 5034 .g2_irqs = 10,
e606ca36 5035 .atu_move_port_mask = 0xf,
f3645652 5036 .pvt = true,
b3e05aa1 5037 .multi_chip = true,
670bb80f 5038 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5039 .ops = &mv88e6123_ops,
f81ec90f
VD		 5040 },
5041
5042 [MV88E6131] = {
107fcc10 5043 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
f81ec90f
VD		 5044 .family = MV88E6XXX_FAMILY_6185,
5045 .name = "Marvell 88E6131",
5046 .num_databases = 256,
d9ea5620 5047 .num_macs = 8192,
f81ec90f 5048 .num_ports = 8,
bc393155 5049 .num_internal_phys = 0,
3cf3c846 5050 .max_vid = 4095,
9dddd478 5051 .port_base_addr = 0x10,
9255bacd 5052 .phy_base_addr = 0x0,
a935c052 5053 .global1_addr = 0x1b,
9069c13a 5054 .global2_addr = 0x1c,
acddbd21 5055 .age_time_coeff = 15000,
dc30c35b 5056 .g1_irqs = 9,
e606ca36 5057 .atu_move_port_mask = 0xf,
b3e05aa1 5058 .multi_chip = true,
b3469dd8 5059 .ops = &mv88e6131_ops,
f81ec90f
VD		 5060 },
5061
990e27b0 5062 [MV88E6141] = {
107fcc10 5063 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
990e27b0 5064 .family = MV88E6XXX_FAMILY_6341,
79a68b26 5065 .name = "Marvell 88E6141",
990e27b0 5066 .num_databases = 4096,
d9ea5620 5067 .num_macs = 2048,
990e27b0 5068 .num_ports = 6,
bc393155 5069 .num_internal_phys = 5,
a73ccd61 5070 .num_gpio = 11,
3cf3c846 5071 .max_vid = 4095,
990e27b0 5072 .port_base_addr = 0x10,
9255bacd 5073 .phy_base_addr = 0x10,
990e27b0 5074 .global1_addr = 0x1b,
9069c13a 5075 .global2_addr = 0x1c,
990e27b0
VD		 5076 .age_time_coeff = 3750,
5077 .atu_move_port_mask = 0x1f,
adfccf11 5078 .g1_irqs = 9,
d6c5e6af 5079 .g2_irqs = 10,
f3645652 5080 .pvt = true,
b3e05aa1 5081 .multi_chip = true,
670bb80f 5082 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
990e27b0
VD		 5083 .ops = &mv88e6141_ops,
5084 },
5085
f81ec90f 5086 [MV88E6161] = {
107fcc10 5087 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
f81ec90f
VD		 5088 .family = MV88E6XXX_FAMILY_6165,
5089 .name = "Marvell 88E6161",
5090 .num_databases = 4096,
d9ea5620 5091 .num_macs = 1024,
f81ec90f 5092 .num_ports = 6,
bc393155 5093 .num_internal_phys = 5,
3cf3c846 5094 .max_vid = 4095,
9dddd478 5095 .port_base_addr = 0x10,
9255bacd 5096 .phy_base_addr = 0x0,
a935c052 5097 .global1_addr = 0x1b,
9069c13a 5098 .global2_addr = 0x1c,
acddbd21 5099 .age_time_coeff = 15000,
dc30c35b 5100 .g1_irqs = 9,
d6c5e6af 5101 .g2_irqs = 10,
e606ca36 5102 .atu_move_port_mask = 0xf,
f3645652 5103 .pvt = true,
b3e05aa1 5104 .multi_chip = true,
670bb80f 5105 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
dfa54348 5106 .ptp_support = true,
b3469dd8 5107 .ops = &mv88e6161_ops,
f81ec90f
VD		 5108 },
5109
5110 [MV88E6165] = {
107fcc10 5111 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
f81ec90f
VD		 5112 .family = MV88E6XXX_FAMILY_6165,
5113 .name = "Marvell 88E6165",
5114 .num_databases = 4096,
d9ea5620 5115 .num_macs = 8192,
f81ec90f 5116 .num_ports = 6,
bc393155 5117 .num_internal_phys = 0,
3cf3c846 5118 .max_vid = 4095,
9dddd478 5119 .port_base_addr = 0x10,
9255bacd 5120 .phy_base_addr = 0x0,
a935c052 5121 .global1_addr = 0x1b,
9069c13a 5122 .global2_addr = 0x1c,
acddbd21 5123 .age_time_coeff = 15000,
dc30c35b 5124 .g1_irqs = 9,
d6c5e6af 5125 .g2_irqs = 10,
e606ca36 5126 .atu_move_port_mask = 0xf,
f3645652 5127 .pvt = true,
b3e05aa1 5128 .multi_chip = true,
dfa54348 5129 .ptp_support = true,
b3469dd8 5130 .ops = &mv88e6165_ops,
f81ec90f
VD		 5131 },
5132
5133 [MV88E6171] = {
107fcc10 5134 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
f81ec90f
VD		 5135 .family = MV88E6XXX_FAMILY_6351,
5136 .name = "Marvell 88E6171",
5137 .num_databases = 4096,
d9ea5620 5138 .num_macs = 8192,
f81ec90f 5139 .num_ports = 7,
bc393155 5140 .num_internal_phys = 5,
3cf3c846 5141 .max_vid = 4095,
9dddd478 5142 .port_base_addr = 0x10,
9255bacd 5143 .phy_base_addr = 0x0,
a935c052 5144 .global1_addr = 0x1b,
9069c13a 5145 .global2_addr = 0x1c,
acddbd21 5146 .age_time_coeff = 15000,
dc30c35b 5147 .g1_irqs = 9,
d6c5e6af 5148 .g2_irqs = 10,
e606ca36 5149 .atu_move_port_mask = 0xf,
f3645652 5150 .pvt = true,
b3e05aa1 5151 .multi_chip = true,
670bb80f 5152 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5153 .ops = &mv88e6171_ops,
f81ec90f
VD		 5154 },
5155
5156 [MV88E6172] = {
107fcc10 5157 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
f81ec90f
VD		 5158 .family = MV88E6XXX_FAMILY_6352,
5159 .name = "Marvell 88E6172",
5160 .num_databases = 4096,
d9ea5620 5161 .num_macs = 8192,
f81ec90f 5162 .num_ports = 7,
bc393155 5163 .num_internal_phys = 5,
a73ccd61 5164 .num_gpio = 15,
3cf3c846 5165 .max_vid = 4095,
9dddd478 5166 .port_base_addr = 0x10,
9255bacd 5167 .phy_base_addr = 0x0,
a935c052 5168 .global1_addr = 0x1b,
9069c13a 5169 .global2_addr = 0x1c,
acddbd21 5170 .age_time_coeff = 15000,
dc30c35b 5171 .g1_irqs = 9,
d6c5e6af 5172 .g2_irqs = 10,
e606ca36 5173 .atu_move_port_mask = 0xf,
f3645652 5174 .pvt = true,
b3e05aa1 5175 .multi_chip = true,
670bb80f 5176 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5177 .ops = &mv88e6172_ops,
f81ec90f
VD		 5178 },
5179
5180 [MV88E6175] = {
107fcc10 5181 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
f81ec90f
VD		 5182 .family = MV88E6XXX_FAMILY_6351,
5183 .name = "Marvell 88E6175",
5184 .num_databases = 4096,
d9ea5620 5185 .num_macs = 8192,
f81ec90f 5186 .num_ports = 7,
bc393155 5187 .num_internal_phys = 5,
3cf3c846 5188 .max_vid = 4095,
9dddd478 5189 .port_base_addr = 0x10,
9255bacd 5190 .phy_base_addr = 0x0,
a935c052 5191 .global1_addr = 0x1b,
9069c13a 5192 .global2_addr = 0x1c,
acddbd21 5193 .age_time_coeff = 15000,
dc30c35b 5194 .g1_irqs = 9,
d6c5e6af 5195 .g2_irqs = 10,
e606ca36 5196 .atu_move_port_mask = 0xf,
f3645652 5197 .pvt = true,
b3e05aa1 5198 .multi_chip = true,
670bb80f 5199 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5200 .ops = &mv88e6175_ops,
f81ec90f
VD		 5201 },
5202
5203 [MV88E6176] = {
107fcc10 5204 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
f81ec90f
VD		 5205 .family = MV88E6XXX_FAMILY_6352,
5206 .name = "Marvell 88E6176",
5207 .num_databases = 4096,
d9ea5620 5208 .num_macs = 8192,
f81ec90f 5209 .num_ports = 7,
bc393155 5210 .num_internal_phys = 5,
a73ccd61 5211 .num_gpio = 15,
3cf3c846 5212 .max_vid = 4095,
9dddd478 5213 .port_base_addr = 0x10,
9255bacd 5214 .phy_base_addr = 0x0,
a935c052 5215 .global1_addr = 0x1b,
9069c13a 5216 .global2_addr = 0x1c,
acddbd21 5217 .age_time_coeff = 15000,
dc30c35b 5218 .g1_irqs = 9,
d6c5e6af 5219 .g2_irqs = 10,
e606ca36 5220 .atu_move_port_mask = 0xf,
f3645652 5221 .pvt = true,
b3e05aa1 5222 .multi_chip = true,
670bb80f 5223 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5224 .ops = &mv88e6176_ops,
f81ec90f
VD		 5225 },
5226
5227 [MV88E6185] = {
107fcc10 5228 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
f81ec90f
VD		 5229 .family = MV88E6XXX_FAMILY_6185,
5230 .name = "Marvell 88E6185",
5231 .num_databases = 256,
d9ea5620 5232 .num_macs = 8192,
f81ec90f 5233 .num_ports = 10,
bc393155 5234 .num_internal_phys = 0,
3cf3c846 5235 .max_vid = 4095,
9dddd478 5236 .port_base_addr = 0x10,
9255bacd 5237 .phy_base_addr = 0x0,
a935c052 5238 .global1_addr = 0x1b,
9069c13a 5239 .global2_addr = 0x1c,
acddbd21 5240 .age_time_coeff = 15000,
dc30c35b 5241 .g1_irqs = 8,
e606ca36 5242 .atu_move_port_mask = 0xf,
b3e05aa1 5243 .multi_chip = true,
670bb80f 5244 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5245 .ops = &mv88e6185_ops,
f81ec90f
VD		 5246 },
5247
1a3b39ec 5248 [MV88E6190] = {
107fcc10 5249 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
1a3b39ec
AL		 5250 .family = MV88E6XXX_FAMILY_6390,
5251 .name = "Marvell 88E6190",
5252 .num_databases = 4096,
d9ea5620 5253 .num_macs = 16384,
1a3b39ec 5254 .num_ports = 11, /* 10 + Z80 */
95150f29 5255 .num_internal_phys = 9,
a73ccd61 5256 .num_gpio = 16,
931d1822 5257 .max_vid = 8191,
1a3b39ec 5258 .port_base_addr = 0x0,
9255bacd 5259 .phy_base_addr = 0x0,
1a3b39ec 5260 .global1_addr = 0x1b,
9069c13a 5261 .global2_addr = 0x1c,
b91e055c 5262 .age_time_coeff = 3750,
1a3b39ec 5263 .g1_irqs = 9,
d6c5e6af 5264 .g2_irqs = 14,
f3645652 5265 .pvt = true,
b3e05aa1 5266 .multi_chip = true,
e606ca36 5267 .atu_move_port_mask = 0x1f,
1a3b39ec
AL		 5268 .ops = &mv88e6190_ops,
5269 },
5270
5271 [MV88E6190X] = {
107fcc10 5272 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
1a3b39ec
AL		 5273 .family = MV88E6XXX_FAMILY_6390,
5274 .name = "Marvell 88E6190X",
5275 .num_databases = 4096,
d9ea5620 5276 .num_macs = 16384,
1a3b39ec 5277 .num_ports = 11, /* 10 + Z80 */
95150f29 5278 .num_internal_phys = 9,
a73ccd61 5279 .num_gpio = 16,
931d1822 5280 .max_vid = 8191,
1a3b39ec 5281 .port_base_addr = 0x0,
9255bacd 5282 .phy_base_addr = 0x0,
1a3b39ec 5283 .global1_addr = 0x1b,
9069c13a 5284 .global2_addr = 0x1c,
b91e055c 5285 .age_time_coeff = 3750,
1a3b39ec 5286 .g1_irqs = 9,
d6c5e6af 5287 .g2_irqs = 14,
e606ca36 5288 .atu_move_port_mask = 0x1f,
f3645652 5289 .pvt = true,
b3e05aa1 5290 .multi_chip = true,
1a3b39ec
AL		 5291 .ops = &mv88e6190x_ops,
5292 },
5293
5294 [MV88E6191] = {
107fcc10 5295 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
1a3b39ec
AL		 5296 .family = MV88E6XXX_FAMILY_6390,
5297 .name = "Marvell 88E6191",
5298 .num_databases = 4096,
d9ea5620 5299 .num_macs = 16384,
1a3b39ec 5300 .num_ports = 11, /* 10 + Z80 */
95150f29 5301 .num_internal_phys = 9,
931d1822 5302 .max_vid = 8191,
1a3b39ec 5303 .port_base_addr = 0x0,
9255bacd 5304 .phy_base_addr = 0x0,
1a3b39ec 5305 .global1_addr = 0x1b,
9069c13a 5306 .global2_addr = 0x1c,
b91e055c 5307 .age_time_coeff = 3750,
443d5a1b 5308 .g1_irqs = 9,
d6c5e6af 5309 .g2_irqs = 14,
e606ca36 5310 .atu_move_port_mask = 0x1f,
f3645652 5311 .pvt = true,
b3e05aa1 5312 .multi_chip = true,
2fa8d3af 5313 .ptp_support = true,
2cf4cefb 5314 .ops = &mv88e6191_ops,
1a3b39ec
AL		 5315 },
5316
de776d0d
PS		 5317 [MV88E6191X] = {
5318 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5319 .family = MV88E6XXX_FAMILY_6393,
5320 .name = "Marvell 88E6191X",
5321 .num_databases = 4096,
5322 .num_ports = 11, /* 10 + Z80 */
5323 .num_internal_phys = 9,
5324 .max_vid = 8191,
5325 .port_base_addr = 0x0,
5326 .phy_base_addr = 0x0,
5327 .global1_addr = 0x1b,
5328 .global2_addr = 0x1c,
5329 .age_time_coeff = 3750,
5330 .g1_irqs = 10,
5331 .g2_irqs = 14,
5332 .atu_move_port_mask = 0x1f,
5333 .pvt = true,
5334 .multi_chip = true,
de776d0d
PS		 5335 .ptp_support = true,
5336 .ops = &mv88e6393x_ops,
5337 },
5338
5339 [MV88E6193X] = {
5340 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5341 .family = MV88E6XXX_FAMILY_6393,
5342 .name = "Marvell 88E6193X",
5343 .num_databases = 4096,
5344 .num_ports = 11, /* 10 + Z80 */
5345 .num_internal_phys = 9,
5346 .max_vid = 8191,
5347 .port_base_addr = 0x0,
5348 .phy_base_addr = 0x0,
5349 .global1_addr = 0x1b,
5350 .global2_addr = 0x1c,
5351 .age_time_coeff = 3750,
5352 .g1_irqs = 10,
5353 .g2_irqs = 14,
5354 .atu_move_port_mask = 0x1f,
5355 .pvt = true,
5356 .multi_chip = true,
de776d0d
PS		 5357 .ptp_support = true,
5358 .ops = &mv88e6393x_ops,
5359 },
5360
49022647
HF		 5361 [MV88E6220] = {
5362 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5363 .family = MV88E6XXX_FAMILY_6250,
5364 .name = "Marvell 88E6220",
5365 .num_databases = 64,
5366
5367 /* Ports 2-4 are not routed to pins
5368 * => usable ports 0, 1, 5, 6
5369 */
5370 .num_ports = 7,
5371 .num_internal_phys = 2,
c857486a 5372 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
49022647
HF		 5373 .max_vid = 4095,
5374 .port_base_addr = 0x08,
5375 .phy_base_addr = 0x00,
5376 .global1_addr = 0x0f,
5377 .global2_addr = 0x07,
5378 .age_time_coeff = 15000,
5379 .g1_irqs = 9,
5380 .g2_irqs = 10,
5381 .atu_move_port_mask = 0xf,
5382 .dual_chip = true,
71509614 5383 .ptp_support = true,
49022647
HF		 5384 .ops = &mv88e6250_ops,
5385 },
5386
f81ec90f 5387 [MV88E6240] = {
107fcc10 5388 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
f81ec90f
VD		 5389 .family = MV88E6XXX_FAMILY_6352,
5390 .name = "Marvell 88E6240",
5391 .num_databases = 4096,
d9ea5620 5392 .num_macs = 8192,
f81ec90f 5393 .num_ports = 7,
bc393155 5394 .num_internal_phys = 5,
a73ccd61 5395 .num_gpio = 15,
3cf3c846 5396 .max_vid = 4095,
9dddd478 5397 .port_base_addr = 0x10,
9255bacd 5398 .phy_base_addr = 0x0,
a935c052 5399 .global1_addr = 0x1b,
9069c13a 5400 .global2_addr = 0x1c,
acddbd21 5401 .age_time_coeff = 15000,
dc30c35b 5402 .g1_irqs = 9,
d6c5e6af 5403 .g2_irqs = 10,
e606ca36 5404 .atu_move_port_mask = 0xf,
f3645652 5405 .pvt = true,
b3e05aa1 5406 .multi_chip = true,
670bb80f 5407 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
2fa8d3af 5408 .ptp_support = true,
b3469dd8 5409 .ops = &mv88e6240_ops,
f81ec90f
VD		 5410 },
5411
1f71836f
RV		 5412 [MV88E6250] = {
5413 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5414 .family = MV88E6XXX_FAMILY_6250,
5415 .name = "Marvell 88E6250",
5416 .num_databases = 64,
5417 .num_ports = 7,
5418 .num_internal_phys = 5,
5419 .max_vid = 4095,
5420 .port_base_addr = 0x08,
5421 .phy_base_addr = 0x00,
5422 .global1_addr = 0x0f,
5423 .global2_addr = 0x07,
5424 .age_time_coeff = 15000,
5425 .g1_irqs = 9,
5426 .g2_irqs = 10,
5427 .atu_move_port_mask = 0xf,
5428 .dual_chip = true,
71509614 5429 .ptp_support = true,
1f71836f
RV		 5430 .ops = &mv88e6250_ops,
5431 },
5432
1a3b39ec 5433 [MV88E6290] = {
107fcc10 5434 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
1a3b39ec
AL		 5435 .family = MV88E6XXX_FAMILY_6390,
5436 .name = "Marvell 88E6290",
5437 .num_databases = 4096,
5438 .num_ports = 11, /* 10 + Z80 */
95150f29 5439 .num_internal_phys = 9,
a73ccd61 5440 .num_gpio = 16,
931d1822 5441 .max_vid = 8191,
1a3b39ec 5442 .port_base_addr = 0x0,
9255bacd 5443 .phy_base_addr = 0x0,
1a3b39ec 5444 .global1_addr = 0x1b,
9069c13a 5445 .global2_addr = 0x1c,
b91e055c 5446 .age_time_coeff = 3750,
1a3b39ec 5447 .g1_irqs = 9,
d6c5e6af 5448 .g2_irqs = 14,
e606ca36 5449 .atu_move_port_mask = 0x1f,
f3645652 5450 .pvt = true,
b3e05aa1 5451 .multi_chip = true,
2fa8d3af 5452 .ptp_support = true,
1a3b39ec
AL		 5453 .ops = &mv88e6290_ops,
5454 },
5455
f81ec90f 5456 [MV88E6320] = {
107fcc10 5457 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
f81ec90f
VD		 5458 .family = MV88E6XXX_FAMILY_6320,
5459 .name = "Marvell 88E6320",
5460 .num_databases = 4096,
d9ea5620 5461 .num_macs = 8192,
f81ec90f 5462 .num_ports = 7,
bc393155 5463 .num_internal_phys = 5,
a73ccd61 5464 .num_gpio = 15,
3cf3c846 5465 .max_vid = 4095,
9dddd478 5466 .port_base_addr = 0x10,
9255bacd 5467 .phy_base_addr = 0x0,
a935c052 5468 .global1_addr = 0x1b,
9069c13a 5469 .global2_addr = 0x1c,
acddbd21 5470 .age_time_coeff = 15000,
dc30c35b 5471 .g1_irqs = 8,
bc393155 5472 .g2_irqs = 10,
e606ca36 5473 .atu_move_port_mask = 0xf,
f3645652 5474 .pvt = true,
b3e05aa1 5475 .multi_chip = true,
670bb80f 5476 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
2fa8d3af 5477 .ptp_support = true,
b3469dd8 5478 .ops = &mv88e6320_ops,
f81ec90f
VD		 5479 },
5480
5481 [MV88E6321] = {
107fcc10 5482 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
f81ec90f
VD		 5483 .family = MV88E6XXX_FAMILY_6320,
5484 .name = "Marvell 88E6321",
5485 .num_databases = 4096,
d9ea5620 5486 .num_macs = 8192,
f81ec90f 5487 .num_ports = 7,
bc393155 5488 .num_internal_phys = 5,
a73ccd61 5489 .num_gpio = 15,
3cf3c846 5490 .max_vid = 4095,
9dddd478 5491 .port_base_addr = 0x10,
9255bacd 5492 .phy_base_addr = 0x0,
a935c052 5493 .global1_addr = 0x1b,
9069c13a 5494 .global2_addr = 0x1c,
acddbd21 5495 .age_time_coeff = 15000,
dc30c35b 5496 .g1_irqs = 8,
bc393155 5497 .g2_irqs = 10,
e606ca36 5498 .atu_move_port_mask = 0xf,
b3e05aa1 5499 .multi_chip = true,
670bb80f 5500 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
2fa8d3af 5501 .ptp_support = true,
b3469dd8 5502 .ops = &mv88e6321_ops,
f81ec90f
VD		 5503 },
5504
a75961d0 5505 [MV88E6341] = {
107fcc10 5506 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
a75961d0
GC		 5507 .family = MV88E6XXX_FAMILY_6341,
5508 .name = "Marvell 88E6341",
5509 .num_databases = 4096,
d9ea5620 5510 .num_macs = 2048,
bc393155 5511 .num_internal_phys = 5,
a75961d0 5512 .num_ports = 6,
a73ccd61 5513 .num_gpio = 11,
3cf3c846 5514 .max_vid = 4095,
a75961d0 5515 .port_base_addr = 0x10,
9255bacd 5516 .phy_base_addr = 0x10,
a75961d0 5517 .global1_addr = 0x1b,
9069c13a 5518 .global2_addr = 0x1c,
a75961d0 5519 .age_time_coeff = 3750,
e606ca36 5520 .atu_move_port_mask = 0x1f,
adfccf11 5521 .g1_irqs = 9,
d6c5e6af 5522 .g2_irqs = 10,
f3645652 5523 .pvt = true,
b3e05aa1 5524 .multi_chip = true,
670bb80f 5525 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
2fa8d3af 5526 .ptp_support = true,
a75961d0
GC		 5527 .ops = &mv88e6341_ops,
5528 },
5529
f81ec90f 5530 [MV88E6350] = {
107fcc10 5531 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
f81ec90f
VD		 5532 .family = MV88E6XXX_FAMILY_6351,
5533 .name = "Marvell 88E6350",
5534 .num_databases = 4096,
d9ea5620 5535 .num_macs = 8192,
f81ec90f 5536 .num_ports = 7,
bc393155 5537 .num_internal_phys = 5,
3cf3c846 5538 .max_vid = 4095,
9dddd478 5539 .port_base_addr = 0x10,
9255bacd 5540 .phy_base_addr = 0x0,
a935c052 5541 .global1_addr = 0x1b,
9069c13a 5542 .global2_addr = 0x1c,
acddbd21 5543 .age_time_coeff = 15000,
dc30c35b 5544 .g1_irqs = 9,
d6c5e6af 5545 .g2_irqs = 10,
e606ca36 5546 .atu_move_port_mask = 0xf,
f3645652 5547 .pvt = true,
b3e05aa1 5548 .multi_chip = true,
670bb80f 5549 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5550 .ops = &mv88e6350_ops,
f81ec90f
VD		 5551 },
5552
5553 [MV88E6351] = {
107fcc10 5554 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
f81ec90f
VD		 5555 .family = MV88E6XXX_FAMILY_6351,
5556 .name = "Marvell 88E6351",
5557 .num_databases = 4096,
d9ea5620 5558 .num_macs = 8192,
f81ec90f 5559 .num_ports = 7,
bc393155 5560 .num_internal_phys = 5,
3cf3c846 5561 .max_vid = 4095,
9dddd478 5562 .port_base_addr = 0x10,
9255bacd 5563 .phy_base_addr = 0x0,
a935c052 5564 .global1_addr = 0x1b,
9069c13a 5565 .global2_addr = 0x1c,
acddbd21 5566 .age_time_coeff = 15000,
dc30c35b 5567 .g1_irqs = 9,
d6c5e6af 5568 .g2_irqs = 10,
e606ca36 5569 .atu_move_port_mask = 0xf,
f3645652 5570 .pvt = true,
b3e05aa1 5571 .multi_chip = true,
670bb80f 5572 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
b3469dd8 5573 .ops = &mv88e6351_ops,
f81ec90f
VD		 5574 },
5575
5576 [MV88E6352] = {
107fcc10 5577 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
f81ec90f
VD		 5578 .family = MV88E6XXX_FAMILY_6352,
5579 .name = "Marvell 88E6352",
5580 .num_databases = 4096,
d9ea5620 5581 .num_macs = 8192,
f81ec90f 5582 .num_ports = 7,
bc393155 5583 .num_internal_phys = 5,
a73ccd61 5584 .num_gpio = 15,
3cf3c846 5585 .max_vid = 4095,
9dddd478 5586 .port_base_addr = 0x10,
9255bacd 5587 .phy_base_addr = 0x0,
a935c052 5588 .global1_addr = 0x1b,
9069c13a 5589 .global2_addr = 0x1c,
acddbd21 5590 .age_time_coeff = 15000,
dc30c35b 5591 .g1_irqs = 9,
d6c5e6af 5592 .g2_irqs = 10,
e606ca36 5593 .atu_move_port_mask = 0xf,
f3645652 5594 .pvt = true,
b3e05aa1 5595 .multi_chip = true,
670bb80f 5596 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
2fa8d3af 5597 .ptp_support = true,
b3469dd8 5598 .ops = &mv88e6352_ops,
f81ec90f 5599 },
1a3b39ec 5600 [MV88E6390] = {
107fcc10 5601 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
1a3b39ec
AL		 5602 .family = MV88E6XXX_FAMILY_6390,
5603 .name = "Marvell 88E6390",
5604 .num_databases = 4096,
d9ea5620 5605 .num_macs = 16384,
1a3b39ec 5606 .num_ports = 11, /* 10 + Z80 */
95150f29 5607 .num_internal_phys = 9,
a73ccd61 5608 .num_gpio = 16,
931d1822 5609 .max_vid = 8191,
1a3b39ec 5610 .port_base_addr = 0x0,
9255bacd 5611 .phy_base_addr = 0x0,
1a3b39ec 5612 .global1_addr = 0x1b,
9069c13a 5613 .global2_addr = 0x1c,
b91e055c 5614 .age_time_coeff = 3750,
1a3b39ec 5615 .g1_irqs = 9,
d6c5e6af 5616 .g2_irqs = 14,
e606ca36 5617 .atu_move_port_mask = 0x1f,
f3645652 5618 .pvt = true,
b3e05aa1 5619 .multi_chip = true,
670bb80f 5620 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
2fa8d3af 5621 .ptp_support = true,
1a3b39ec
AL		 5622 .ops = &mv88e6390_ops,
5623 },
5624 [MV88E6390X] = {
107fcc10 5625 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
1a3b39ec
AL		 5626 .family = MV88E6XXX_FAMILY_6390,
5627 .name = "Marvell 88E6390X",
5628 .num_databases = 4096,
d9ea5620 5629 .num_macs = 16384,
1a3b39ec 5630 .num_ports = 11, /* 10 + Z80 */
95150f29 5631 .num_internal_phys = 9,
a73ccd61 5632 .num_gpio = 16,
931d1822 5633 .max_vid = 8191,
1a3b39ec 5634 .port_base_addr = 0x0,
9255bacd 5635 .phy_base_addr = 0x0,
1a3b39ec 5636 .global1_addr = 0x1b,
9069c13a 5637 .global2_addr = 0x1c,
b91e055c 5638 .age_time_coeff = 3750,
1a3b39ec 5639 .g1_irqs = 9,
d6c5e6af 5640 .g2_irqs = 14,
e606ca36 5641 .atu_move_port_mask = 0x1f,
f3645652 5642 .pvt = true,
b3e05aa1 5643 .multi_chip = true,
670bb80f 5644 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
2fa8d3af 5645 .ptp_support = true,
1a3b39ec
AL		 5646 .ops = &mv88e6390x_ops,
5647 },
de776d0d
PS		 5648
5649 [MV88E6393X] = {
5650 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5651 .family = MV88E6XXX_FAMILY_6393,
5652 .name = "Marvell 88E6393X",
5653 .num_databases = 4096,
5654 .num_ports = 11, /* 10 + Z80 */
5655 .num_internal_phys = 9,
5656 .max_vid = 8191,
5657 .port_base_addr = 0x0,
5658 .phy_base_addr = 0x0,
5659 .global1_addr = 0x1b,
5660 .global2_addr = 0x1c,
5661 .age_time_coeff = 3750,
5662 .g1_irqs = 10,
5663 .g2_irqs = 14,
5664 .atu_move_port_mask = 0x1f,
5665 .pvt = true,
5666 .multi_chip = true,
de776d0d
PS		 5667 .ptp_support = true,
5668 .ops = &mv88e6393x_ops,
5669 },
f81ec90f
VD		 5670};
5671
5f7c0367 5672static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
b9b37713 5673{
a439c061 5674 int i;
b9b37713 5675
5f7c0367
VD		 5676 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5677 if (mv88e6xxx_table[i].prod_num == prod_num)
5678 return &mv88e6xxx_table[i];
b9b37713 5679
b9b37713
VD		 5680 return NULL;
5681}
5682
fad09c73 5683static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
bc46a3d5
VD		 5684{
5685 const struct mv88e6xxx_info *info;
8f6345b2
VD		 5686 unsigned int prod_num, rev;
5687 u16 id;
5688 int err;
bc46a3d5 5689
c9acece0 5690 mv88e6xxx_reg_lock(chip);
107fcc10 5691 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
c9acece0 5692 mv88e6xxx_reg_unlock(chip);
8f6345b2
VD		 5693 if (err)
5694 return err;
bc46a3d5 5695
107fcc10
VD		 5696 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5697 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
bc46a3d5
VD		 5698
5699 info = mv88e6xxx_lookup_info(prod_num);
5700 if (!info)
5701 return -ENODEV;
5702
caac8545 5703 /* Update the compatible info with the probed one */
fad09c73 5704 chip->info = info;
bc46a3d5 5705
fad09c73
VD		 5706 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5707 chip->info->prod_num, chip->info->name, rev);
bc46a3d5
VD		 5708
5709 return 0;
5710}
5711
fad09c73 5712static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
469d729f 5713{
fad09c73 5714 struct mv88e6xxx_chip *chip;
469d729f 5715
fad09c73
VD		 5716 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5717 if (!chip)
469d729f
VD		 5718 return NULL;
5719
fad09c73 5720 chip->dev = dev;
469d729f 5721
fad09c73 5722 mutex_init(&chip->reg_lock);
a3c53be5 5723 INIT_LIST_HEAD(&chip->mdios);
da7dc875 5724 idr_init(&chip->policies);
469d729f 5725
fad09c73 5726 return chip;
469d729f
VD		 5727}
5728
5ed4e3eb 5729static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4d776482
FF		 5730 int port,
5731 enum dsa_tag_protocol m)
7b314362 5732{
04bed143 5733 struct mv88e6xxx_chip *chip = ds->priv;
2bbb33be 5734
670bb80f 5735 return chip->tag_protocol;
7b314362
AL		 5736}
5737
9a99bef5
TW		 5738static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port,
5739 enum dsa_tag_protocol proto)
5740{
5741 struct mv88e6xxx_chip *chip = ds->priv;
5742 enum dsa_tag_protocol old_protocol;
5743 int err;
5744
5745 switch (proto) {
5746 case DSA_TAG_PROTO_EDSA:
5747 switch (chip->info->edsa_support) {
5748 case MV88E6XXX_EDSA_UNSUPPORTED:
5749 return -EPROTONOSUPPORT;
5750 case MV88E6XXX_EDSA_UNDOCUMENTED:
5751 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
5752 fallthrough;
5753 case MV88E6XXX_EDSA_SUPPORTED:
5754 break;
5755 }
5756 break;
5757 case DSA_TAG_PROTO_DSA:
5758 break;
5759 default:
5760 return -EPROTONOSUPPORT;
5761 }
5762
5763 old_protocol = chip->tag_protocol;
5764 chip->tag_protocol = proto;
5765
5766 mv88e6xxx_reg_lock(chip);
5767 err = mv88e6xxx_setup_port_mode(chip, port);
5768 mv88e6xxx_reg_unlock(chip);
5769
5770 if (err)
5771 chip->tag_protocol = old_protocol;
5772
5773 return err;
5774}
5775
a52b2da7
VO		 5776static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5777 const struct switchdev_obj_port_mdb *mdb)
7df8fbdd 5778{
04bed143 5779 struct mv88e6xxx_chip *chip = ds->priv;
a52b2da7 5780 int err;
7df8fbdd 5781
c9acece0 5782 mv88e6xxx_reg_lock(chip);
a52b2da7
VO		 5783 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5784 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
c9acece0 5785 mv88e6xxx_reg_unlock(chip);
a52b2da7
VO		 5786
5787 return err;
7df8fbdd
VD		 5788}
5789
5790static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5791 const struct switchdev_obj_port_mdb *mdb)
5792{
04bed143 5793 struct mv88e6xxx_chip *chip = ds->priv;
7df8fbdd
VD		 5794 int err;
5795
c9acece0 5796 mv88e6xxx_reg_lock(chip);
d8291a95 5797 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
c9acece0 5798 mv88e6xxx_reg_unlock(chip);
7df8fbdd
VD		 5799
5800 return err;
5801}
5802
f0942e00
IT		 5803static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5804 struct dsa_mall_mirror_tc_entry *mirror,
5805 bool ingress)
5806{
5807 enum mv88e6xxx_egress_direction direction = ingress ?
5808 MV88E6XXX_EGRESS_DIR_INGRESS :
5809 MV88E6XXX_EGRESS_DIR_EGRESS;
5810 struct mv88e6xxx_chip *chip = ds->priv;
5811 bool other_mirrors = false;
5812 int i;
5813 int err;
5814
f0942e00
IT		 5815 mutex_lock(&chip->reg_lock);
5816 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5817 mirror->to_local_port) {
5818 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5819 other_mirrors |= ingress ?
5820 chip->ports[i].mirror_ingress :
5821 chip->ports[i].mirror_egress;
5822
5823 /* Can't change egress port when other mirror is active */
5824 if (other_mirrors) {
5825 err = -EBUSY;
5826 goto out;
5827 }
5828
2fda45f0
MB		 5829 err = mv88e6xxx_set_egress_port(chip, direction,
5830 mirror->to_local_port);
f0942e00
IT		 5831 if (err)
5832 goto out;
5833 }
5834
5835 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5836out:
5837 mutex_unlock(&chip->reg_lock);
5838
5839 return err;
5840}
5841
5842static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5843 struct dsa_mall_mirror_tc_entry *mirror)
5844{
5845 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5846 MV88E6XXX_EGRESS_DIR_INGRESS :
5847 MV88E6XXX_EGRESS_DIR_EGRESS;
5848 struct mv88e6xxx_chip *chip = ds->priv;
5849 bool other_mirrors = false;
5850 int i;
5851
5852 mutex_lock(&chip->reg_lock);
5853 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5854 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5855
5856 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5857 other_mirrors |= mirror->ingress ?
5858 chip->ports[i].mirror_ingress :
5859 chip->ports[i].mirror_egress;
5860
5861 /* Reset egress port when no other mirror is active */
5862 if (!other_mirrors) {
2fda45f0
MB		 5863 if (mv88e6xxx_set_egress_port(chip, direction,
5864 dsa_upstream_port(ds, port)))
f0942e00
IT		 5865 dev_err(ds->dev, "failed to set egress port\n");
5866 }
5867
5868 mutex_unlock(&chip->reg_lock);
5869}
5870
a8b659e7
VO		 5871static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
5872 struct switchdev_brport_flags flags,
5873 struct netlink_ext_ack *extack)
5874{
5875 struct mv88e6xxx_chip *chip = ds->priv;
5876 const struct mv88e6xxx_ops *ops;
5877
8d1d8298
TW		 5878 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
5879 BR_BCAST_FLOOD))
a8b659e7
VO		 5880 return -EINVAL;
5881
5882 ops = chip->info->ops;
5883
5884 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
5885 return -EINVAL;
5886
5887 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
5888 return -EINVAL;
5889
5890 return 0;
5891}
5892
5893static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
5894 struct switchdev_brport_flags flags,
5895 struct netlink_ext_ack *extack)
4f85901f
RK		 5896{
5897 struct mv88e6xxx_chip *chip = ds->priv;
5898 int err = -EOPNOTSUPP;
5899
c9acece0 5900 mv88e6xxx_reg_lock(chip);
a8b659e7 5901
041bd545
TW		 5902 if (flags.mask & BR_LEARNING) {
5903 bool learning = !!(flags.val & BR_LEARNING);
5904 u16 pav = learning ? (1 << port) : 0;
5905
5906 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
5907 if (err)
5908 goto out;
041bd545
TW		 5909 }
5910
a8b659e7
VO		 5911 if (flags.mask & BR_FLOOD) {
5912 bool unicast = !!(flags.val & BR_FLOOD);
5913
5914 err = chip->info->ops->port_set_ucast_flood(chip, port,
5915 unicast);
5916 if (err)
5917 goto out;
5918 }
5919
5920 if (flags.mask & BR_MCAST_FLOOD) {
5921 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
5922
5923 err = chip->info->ops->port_set_mcast_flood(chip, port,
5924 multicast);
5925 if (err)
5926 goto out;
5927 }
5928
8d1d8298
TW		 5929 if (flags.mask & BR_BCAST_FLOOD) {
5930 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
5931
5932 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
5933 if (err)
5934 goto out;
5935 }
5936
a8b659e7
VO		 5937out:
5938 mv88e6xxx_reg_unlock(chip);
5939
5940 return err;
5941}
5942
57e661aa
TW		 5943static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
5944 struct net_device *lag,
5945 struct netdev_lag_upper_info *info)
5946{
b80dc51b 5947 struct mv88e6xxx_chip *chip = ds->priv;
57e661aa
TW		 5948 struct dsa_port *dp;
5949 int id, members = 0;
5950
b80dc51b
TW		 5951 if (!mv88e6xxx_has_lag(chip))
5952 return false;
5953
57e661aa
TW		 5954 id = dsa_lag_id(ds->dst, lag);
5955 if (id < 0 || id >= ds->num_lag_ids)
5956 return false;
5957
5958 dsa_lag_foreach_port(dp, ds->dst, lag)
5959 /* Includes the port joining the LAG */
5960 members++;
5961
5962 if (members > 8)
5963 return false;
5964
5965 /* We could potentially relax this to include active
5966 * backup in the future.
5967 */
5968 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
5969 return false;
5970
5971 /* Ideally we would also validate that the hash type matches
5972 * the hardware. Alas, this is always set to unknown on team
5973 * interfaces.
5974 */
5975 return true;
5976}
5977
5978static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
5979{
5980 struct mv88e6xxx_chip *chip = ds->priv;
5981 struct dsa_port *dp;
5982 u16 map = 0;
5983 int id;
5984
5985 id = dsa_lag_id(ds->dst, lag);
5986
5987 /* Build the map of all ports to distribute flows destined for
5988 * this LAG. This can be either a local user port, or a DSA
5989 * port if the LAG port is on a remote chip.
5990 */
5991 dsa_lag_foreach_port(dp, ds->dst, lag)
5992 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
5993
5994 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
5995}
5996
5997static const u8 mv88e6xxx_lag_mask_table[8][8] = {
5998 /* Row number corresponds to the number of active members in a
5999 * LAG. Each column states which of the eight hash buckets are
6000 * mapped to the column:th port in the LAG.
6001 *
6002 * Example: In a LAG with three active ports, the second port
6003 * ([2][1]) would be selected for traffic mapped to buckets
6004 * 3,4,5 (0x38).
6005 */
6006 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6007 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6008 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6009 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6010 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6011 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6012 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6013 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6014};
6015
6016static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6017 int num_tx, int nth)
6018{
6019 u8 active = 0;
6020 int i;
6021
6022 num_tx = num_tx <= 8 ? num_tx : 8;
6023 if (nth < num_tx)
6024 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6025
6026 for (i = 0; i < 8; i++) {
6027 if (BIT(i) & active)
6028 mask[i] |= BIT(port);
6029 }
6030}
6031
6032static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6033{
6034 struct mv88e6xxx_chip *chip = ds->priv;
6035 unsigned int id, num_tx;
6036 struct net_device *lag;
6037 struct dsa_port *dp;
6038 int i, err, nth;
6039 u16 mask[8];
6040 u16 ivec;
6041
6042 /* Assume no port is a member of any LAG. */
6043 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6044
6045 /* Disable all masks for ports that _are_ members of a LAG. */
6046 list_for_each_entry(dp, &ds->dst->ports, list) {
6047 if (!dp->lag_dev || dp->ds != ds)
6048 continue;
6049
6050 ivec &= ~BIT(dp->index);
6051 }
6052
6053 for (i = 0; i < 8; i++)
6054 mask[i] = ivec;
6055
6056 /* Enable the correct subset of masks for all LAG ports that
6057 * are in the Tx set.
6058 */
6059 dsa_lags_foreach_id(id, ds->dst) {
6060 lag = dsa_lag_dev(ds->dst, id);
6061 if (!lag)
6062 continue;
6063
6064 num_tx = 0;
6065 dsa_lag_foreach_port(dp, ds->dst, lag) {
6066 if (dp->lag_tx_enabled)
6067 num_tx++;
6068 }
6069
6070 if (!num_tx)
6071 continue;
6072
6073 nth = 0;
6074 dsa_lag_foreach_port(dp, ds->dst, lag) {
6075 if (!dp->lag_tx_enabled)
6076 continue;
6077
6078 if (dp->ds == ds)
6079 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6080 num_tx, nth);
6081
6082 nth++;
6083 }
6084 }
6085
6086 for (i = 0; i < 8; i++) {
6087 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6088 if (err)
6089 return err;
6090 }
6091
6092 return 0;
6093}
6094
6095static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6096 struct net_device *lag)
6097{
6098 int err;
6099
6100 err = mv88e6xxx_lag_sync_masks(ds);
6101
6102 if (!err)
6103 err = mv88e6xxx_lag_sync_map(ds, lag);
6104
6105 return err;
6106}
6107
6108static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6109{
6110 struct mv88e6xxx_chip *chip = ds->priv;
6111 int err;
6112
6113 mv88e6xxx_reg_lock(chip);
6114 err = mv88e6xxx_lag_sync_masks(ds);
6115 mv88e6xxx_reg_unlock(chip);
6116 return err;
6117}
6118
6119static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6120 struct net_device *lag,
6121 struct netdev_lag_upper_info *info)
6122{
6123 struct mv88e6xxx_chip *chip = ds->priv;
6124 int err, id;
6125
6126 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6127 return -EOPNOTSUPP;
6128
6129 id = dsa_lag_id(ds->dst, lag);
6130
6131 mv88e6xxx_reg_lock(chip);
6132
6133 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6134 if (err)
6135 goto err_unlock;
6136
6137 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6138 if (err)
6139 goto err_clear_trunk;
6140
6141 mv88e6xxx_reg_unlock(chip);
6142 return 0;
6143
6144err_clear_trunk:
6145 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6146err_unlock:
6147 mv88e6xxx_reg_unlock(chip);
6148 return err;
6149}
6150
6151static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6152 struct net_device *lag)
6153{
6154 struct mv88e6xxx_chip *chip = ds->priv;
6155 int err_sync, err_trunk;
6156
6157 mv88e6xxx_reg_lock(chip);
6158 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6159 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6160 mv88e6xxx_reg_unlock(chip);
6161 return err_sync ? : err_trunk;
6162}
6163
6164static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6165 int port)
6166{
6167 struct mv88e6xxx_chip *chip = ds->priv;
6168 int err;
6169
6170 mv88e6xxx_reg_lock(chip);
6171 err = mv88e6xxx_lag_sync_masks(ds);
6172 mv88e6xxx_reg_unlock(chip);
6173 return err;
6174}
6175
6176static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6177 int port, struct net_device *lag,
6178 struct netdev_lag_upper_info *info)
6179{
6180 struct mv88e6xxx_chip *chip = ds->priv;
6181 int err;
6182
6183 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6184 return -EOPNOTSUPP;
6185
6186 mv88e6xxx_reg_lock(chip);
6187
6188 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6189 if (err)
6190 goto unlock;
6191
6192 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6193
6194unlock:
6195 mv88e6xxx_reg_unlock(chip);
6196 return err;
6197}
6198
6199static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6200 int port, struct net_device *lag)
6201{
6202 struct mv88e6xxx_chip *chip = ds->priv;
6203 int err_sync, err_pvt;
6204
6205 mv88e6xxx_reg_lock(chip);
6206 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6207 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6208 mv88e6xxx_reg_unlock(chip);
6209 return err_sync ? : err_pvt;
6210}
6211
a82f67af 6212static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
7b314362 6213 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
9a99bef5 6214 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
f81ec90f 6215 .setup = mv88e6xxx_setup,
23e8b470 6216 .teardown = mv88e6xxx_teardown,
fd292c18
VO		 6217 .port_setup = mv88e6xxx_port_setup,
6218 .port_teardown = mv88e6xxx_port_teardown,
c9a2356f 6219 .phylink_validate = mv88e6xxx_validate,
a5a6858b 6220 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
c9a2356f 6221 .phylink_mac_config = mv88e6xxx_mac_config,
a5a6858b 6222 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
c9a2356f
RK		 6223 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6224 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
f81ec90f
VD		 6225 .get_strings = mv88e6xxx_get_strings,
6226 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6227 .get_sset_count = mv88e6xxx_get_sset_count,
04aca993
AL		 6228 .port_enable = mv88e6xxx_port_enable,
6229 .port_disable = mv88e6xxx_port_disable,
2a550aec
AL		 6230 .port_max_mtu = mv88e6xxx_get_max_mtu,
6231 .port_change_mtu = mv88e6xxx_change_mtu,
08f50061
VD		 6232 .get_mac_eee = mv88e6xxx_get_mac_eee,
6233 .set_mac_eee = mv88e6xxx_set_mac_eee,
f8cd8753 6234 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
f81ec90f
VD		 6235 .get_eeprom = mv88e6xxx_get_eeprom,
6236 .set_eeprom = mv88e6xxx_set_eeprom,
6237 .get_regs_len = mv88e6xxx_get_regs_len,
6238 .get_regs = mv88e6xxx_get_regs,
da7dc875
VD		 6239 .get_rxnfc = mv88e6xxx_get_rxnfc,
6240 .set_rxnfc = mv88e6xxx_set_rxnfc,
2cfcd964 6241 .set_ageing_time = mv88e6xxx_set_ageing_time,
f81ec90f
VD		 6242 .port_bridge_join = mv88e6xxx_port_bridge_join,
6243 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
a8b659e7
VO		 6244 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6245 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
f81ec90f 6246 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
749efcb8 6247 .port_fast_age = mv88e6xxx_port_fast_age,
f81ec90f 6248 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
f81ec90f
VD		 6249 .port_vlan_add = mv88e6xxx_port_vlan_add,
6250 .port_vlan_del = mv88e6xxx_port_vlan_del,
f81ec90f
VD		 6251 .port_fdb_add = mv88e6xxx_port_fdb_add,
6252 .port_fdb_del = mv88e6xxx_port_fdb_del,
6253 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
7df8fbdd
VD		 6254 .port_mdb_add = mv88e6xxx_port_mdb_add,
6255 .port_mdb_del = mv88e6xxx_port_mdb_del,
f0942e00
IT		 6256 .port_mirror_add = mv88e6xxx_port_mirror_add,
6257 .port_mirror_del = mv88e6xxx_port_mirror_del,
aec5ac88
VD		 6258 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6259 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
c6fe0ad2
BS		 6260 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6261 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6262 .port_txtstamp = mv88e6xxx_port_txtstamp,
6263 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6264 .get_ts_info = mv88e6xxx_get_ts_info,
23e8b470
AL		 6265 .devlink_param_get = mv88e6xxx_devlink_param_get,
6266 .devlink_param_set = mv88e6xxx_devlink_param_set,
93157307 6267 .devlink_info_get = mv88e6xxx_devlink_info_get,
57e661aa
TW		 6268 .port_lag_change = mv88e6xxx_port_lag_change,
6269 .port_lag_join = mv88e6xxx_port_lag_join,
6270 .port_lag_leave = mv88e6xxx_port_lag_leave,
6271 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6272 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6273 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
ce5df689
VO		 6274 .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload,
6275 .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload,
f81ec90f
VD		 6276};
6277
55ed0ce0 6278static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 6279{
fad09c73 6280 struct device *dev = chip->dev;
b7e66a5f
VD		 6281 struct dsa_switch *ds;
6282
7e99e347 6283 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
b7e66a5f
VD		 6284 if (!ds)
6285 return -ENOMEM;
6286
7e99e347
VD		 6287 ds->dev = dev;
6288 ds->num_ports = mv88e6xxx_num_ports(chip);
fad09c73 6289 ds->priv = chip;
877b7cb0 6290 ds->dev = dev;
9d490b4e 6291 ds->ops = &mv88e6xxx_switch_ops;
9ff74f24
VD		 6292 ds->ageing_time_min = chip->info->age_time_coeff;
6293 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
b7e66a5f 6294
57e661aa
TW		 6295 /* Some chips support up to 32, but that requires enabling the
6296 * 5-bit port mode, which we do not support. 640k^W16 ought to
6297 * be enough for anyone.
6298 */
b80dc51b 6299 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
57e661aa 6300
b7e66a5f
VD		 6301 dev_set_drvdata(dev, ds);
6302
23c9ee49 6303 return dsa_register_switch(ds);
b7e66a5f
VD		 6304}
6305
fad09c73 6306static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
b7e66a5f 6307{
fad09c73 6308 dsa_unregister_switch(chip->ds);
b7e66a5f
VD		 6309}
6310
877b7cb0
AL		 6311static const void *pdata_device_get_match_data(struct device *dev)
6312{
6313 const struct of_device_id *matches = dev->driver->of_match_table;
6314 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6315
6316 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6317 matches++) {
6318 if (!strcmp(pdata->compatible, matches->compatible))
6319 return matches->data;
6320 }
6321 return NULL;
6322}
6323
bcd3d9d9
MR		 6324/* There is no suspend to RAM support at DSA level yet, the switch configuration
6325 * would be lost after a power cycle so prevent it to be suspended.
6326 */
6327static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6328{
6329 return -EOPNOTSUPP;
6330}
6331
6332static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6333{
6334 return 0;
6335}
6336
6337static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6338
57d32310 6339static int mv88e6xxx_probe(struct mdio_device *mdiodev)
98e67308 6340{
877b7cb0 6341 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7ddae24f 6342 const struct mv88e6xxx_info *compat_info = NULL;
14c7b3c3 6343 struct device *dev = &mdiodev->dev;
f8cd8753 6344 struct device_node *np = dev->of_node;
fad09c73 6345 struct mv88e6xxx_chip *chip;
877b7cb0 6346 int port;
52638f71 6347 int err;
14c7b3c3 6348
7bb8c996
AL		 6349 if (!np && !pdata)
6350 return -EINVAL;
6351
877b7cb0
AL		 6352 if (np)
6353 compat_info = of_device_get_match_data(dev);
6354
6355 if (pdata) {
6356 compat_info = pdata_device_get_match_data(dev);
6357
6358 if (!pdata->netdev)
6359 return -EINVAL;
6360
6361 for (port = 0; port < DSA_MAX_PORTS; port++) {
6362 if (!(pdata->enabled_ports & (1 << port)))
6363 continue;
6364 if (strcmp(pdata->cd.port_names[port], "cpu"))
6365 continue;
6366 pdata->cd.netdev[port] = &pdata->netdev->dev;
6367 break;
6368 }
6369 }
6370
caac8545
VD		 6371 if (!compat_info)
6372 return -EINVAL;
6373
fad09c73 6374 chip = mv88e6xxx_alloc_chip(dev);
877b7cb0
AL		 6375 if (!chip) {
6376 err = -ENOMEM;
6377 goto out;
6378 }
14c7b3c3 6379
fad09c73 6380 chip->info = compat_info;
caac8545 6381
fad09c73 6382 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4a70c4ab 6383 if (err)
877b7cb0 6384 goto out;
14c7b3c3 6385
b4308f04 6386 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
877b7cb0
AL		 6387 if (IS_ERR(chip->reset)) {
6388 err = PTR_ERR(chip->reset);
6389 goto out;
6390 }
7b75e49d
BS		 6391 if (chip->reset)
6392 usleep_range(1000, 2000);
b4308f04 6393
fad09c73 6394 err = mv88e6xxx_detect(chip);
bc46a3d5 6395 if (err)
877b7cb0 6396 goto out;
14c7b3c3 6397
670bb80f
TW		 6398 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6399 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6400 else
6401 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6402
e57e5e77
VD		 6403 mv88e6xxx_phy_init(chip);
6404
00baabe5
AL		 6405 if (chip->info->ops->get_eeprom) {
6406 if (np)
6407 of_property_read_u32(np, "eeprom-length",
6408 &chip->eeprom_len);
6409 else
6410 chip->eeprom_len = pdata->eeprom_len;
6411 }
f8cd8753 6412
c9acece0 6413 mv88e6xxx_reg_lock(chip);
dc30c35b 6414 err = mv88e6xxx_switch_reset(chip);
c9acece0 6415 mv88e6xxx_reg_unlock(chip);
dc30c35b
AL		 6416 if (err)
6417 goto out;
6418
a27415de
AL		 6419 if (np) {
6420 chip->irq = of_irq_get(np, 0);
6421 if (chip->irq == -EPROBE_DEFER) {
6422 err = chip->irq;
6423 goto out;
6424 }
dc30c35b
AL		 6425 }
6426
a27415de
AL		 6427 if (pdata)
6428 chip->irq = pdata->irq;
6429
294d711e 6430 /* Has to be performed before the MDIO bus is created, because
a708767e 6431 * the PHYs will link their interrupts to these interrupt
294d711e
AL		 6432 * controllers
6433 */
c9acece0 6434 mv88e6xxx_reg_lock(chip);
294d711e 6435 if (chip->irq > 0)
dc30c35b 6436 err = mv88e6xxx_g1_irq_setup(chip);
294d711e
AL		 6437 else
6438 err = mv88e6xxx_irq_poll_setup(chip);
c9acece0 6439 mv88e6xxx_reg_unlock(chip);
0977644c 6440
294d711e
AL		 6441 if (err)
6442 goto out;
62eb1162 6443
294d711e
AL		 6444 if (chip->info->g2_irqs > 0) {
6445 err = mv88e6xxx_g2_irq_setup(chip);
62eb1162 6446 if (err)
294d711e 6447 goto out_g1_irq;
dc30c35b
AL		 6448 }
6449
294d711e
AL		 6450 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
6451 if (err)
6452 goto out_g2_irq;
6453
6454 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
6455 if (err)
6456 goto out_g1_atu_prob_irq;
6457
a3c53be5 6458 err = mv88e6xxx_mdios_register(chip, np);
b516d453 6459 if (err)
62eb1162 6460 goto out_g1_vtu_prob_irq;
b516d453 6461
55ed0ce0 6462 err = mv88e6xxx_register_switch(chip);
dc30c35b
AL		 6463 if (err)
6464 goto out_mdio;
83c0afae 6465
98e67308 6466 return 0;
dc30c35b
AL		 6467
6468out_mdio:
a3c53be5 6469 mv88e6xxx_mdios_unregister(chip);
62eb1162 6470out_g1_vtu_prob_irq:
294d711e 6471 mv88e6xxx_g1_vtu_prob_irq_free(chip);
0977644c 6472out_g1_atu_prob_irq:
294d711e 6473 mv88e6xxx_g1_atu_prob_irq_free(chip);
dc30c35b 6474out_g2_irq:
294d711e 6475 if (chip->info->g2_irqs > 0)
dc30c35b
AL		 6476 mv88e6xxx_g2_irq_free(chip);
6477out_g1_irq:
294d711e 6478 if (chip->irq > 0)
46712644 6479 mv88e6xxx_g1_irq_free(chip);
294d711e
AL		 6480 else
6481 mv88e6xxx_irq_poll_free(chip);
dc30c35b 6482out:
877b7cb0
AL		 6483 if (pdata)
6484 dev_put(pdata->netdev);
6485
dc30c35b 6486 return err;
98e67308 6487}
14c7b3c3
AL		 6488
6489static void mv88e6xxx_remove(struct mdio_device *mdiodev)
6490{
6491 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
0650bf52
VO		 6492 struct mv88e6xxx_chip *chip;
6493
6494 if (!ds)
6495 return;
6496
6497 chip = ds->priv;
14c7b3c3 6498
c6fe0ad2
BS		 6499 if (chip->info->ptp_support) {
6500 mv88e6xxx_hwtstamp_free(chip);
2fa8d3af 6501 mv88e6xxx_ptp_free(chip);
c6fe0ad2 6502 }
2fa8d3af 6503
930188ce 6504 mv88e6xxx_phy_destroy(chip);
fad09c73 6505 mv88e6xxx_unregister_switch(chip);
a3c53be5 6506 mv88e6xxx_mdios_unregister(chip);
dc30c35b 6507
76f38f1f
AL		 6508 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6509 mv88e6xxx_g1_atu_prob_irq_free(chip);
6510
6511 if (chip->info->g2_irqs > 0)
6512 mv88e6xxx_g2_irq_free(chip);
6513
76f38f1f 6514 if (chip->irq > 0)
46712644 6515 mv88e6xxx_g1_irq_free(chip);
76f38f1f
AL		 6516 else
6517 mv88e6xxx_irq_poll_free(chip);
0650bf52
VO		 6518
6519 dev_set_drvdata(&mdiodev->dev, NULL);
6520}
6521
6522static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
6523{
6524 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
6525
6526 if (!ds)
6527 return;
6528
6529 dsa_switch_shutdown(ds);
6530
6531 dev_set_drvdata(&mdiodev->dev, NULL);
14c7b3c3
AL		 6532}
6533
6534static const struct of_device_id mv88e6xxx_of_match[] = {
caac8545
VD		 6535 {
6536 .compatible = "marvell,mv88e6085",
6537 .data = &mv88e6xxx_table[MV88E6085],
6538 },
1a3b39ec
AL		 6539 {
6540 .compatible = "marvell,mv88e6190",
6541 .data = &mv88e6xxx_table[MV88E6190],
6542 },
1f71836f
RV		 6543 {
6544 .compatible = "marvell,mv88e6250",
6545 .data = &mv88e6xxx_table[MV88E6250],
6546 },
14c7b3c3
AL		 6547 { /* sentinel */ },
6548};
6549
6550MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
6551
6552static struct mdio_driver mv88e6xxx_driver = {
6553 .probe = mv88e6xxx_probe,
6554 .remove = mv88e6xxx_remove,
0650bf52 6555 .shutdown = mv88e6xxx_shutdown,
14c7b3c3
AL		 6556 .mdiodrv.driver = {
6557 .name = "mv88e6085",
6558 .of_match_table = mv88e6xxx_of_match,
bcd3d9d9 6559 .pm = &mv88e6xxx_pm_ops,
14c7b3c3
AL		 6560 },
6561};
6562
7324d50e 6563mdio_module_driver(mv88e6xxx_driver);
3d825ede
BH		 6564
6565MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
6566MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
6567MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)