Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
91da11f8 | 2 | /* |
0d3cd4b6 VD |
3 | * Marvell 88e6xxx Ethernet switch single-chip support |
4 | * | |
91da11f8 LB |
5 | * Copyright (c) 2008 Marvell Semiconductor |
6 | * | |
14c7b3c3 AL |
7 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
8 | * | |
4333d619 VD |
9 | * Copyright (c) 2016-2017 Savoir-faire Linux Inc. |
10 | * Vivien Didelot <vivien.didelot@savoirfairelinux.com> | |
91da11f8 LB |
11 | */ |
12 | ||
19fb7f69 | 13 | #include <linux/bitfield.h> |
19b2f97e | 14 | #include <linux/delay.h> |
5bded825 | 15 | #include <linux/dsa/mv88e6xxx.h> |
defb05b9 | 16 | #include <linux/etherdevice.h> |
dea87024 | 17 | #include <linux/ethtool.h> |
facd95b2 | 18 | #include <linux/if_bridge.h> |
dc30c35b AL |
19 | #include <linux/interrupt.h> |
20 | #include <linux/irq.h> | |
21 | #include <linux/irqdomain.h> | |
19b2f97e | 22 | #include <linux/jiffies.h> |
91da11f8 | 23 | #include <linux/list.h> |
14c7b3c3 | 24 | #include <linux/mdio.h> |
2bbba277 | 25 | #include <linux/module.h> |
caac8545 | 26 | #include <linux/of_device.h> |
dc30c35b | 27 | #include <linux/of_irq.h> |
b516d453 | 28 | #include <linux/of_mdio.h> |
877b7cb0 | 29 | #include <linux/platform_data/mv88e6xxx.h> |
91da11f8 | 30 | #include <linux/netdevice.h> |
c8c1b39a | 31 | #include <linux/gpio/consumer.h> |
c9a2356f | 32 | #include <linux/phylink.h> |
c8f0b869 | 33 | #include <net/dsa.h> |
ec561276 | 34 | |
4d5f2ba7 | 35 | #include "chip.h" |
9dd43aa2 | 36 | #include "devlink.h" |
a935c052 | 37 | #include "global1.h" |
ec561276 | 38 | #include "global2.h" |
c6fe0ad2 | 39 | #include "hwtstamp.h" |
10fa5bfc | 40 | #include "phy.h" |
18abed21 | 41 | #include "port.h" |
2fa8d3af | 42 | #include "ptp.h" |
6d91782f | 43 | #include "serdes.h" |
e7ba0fad | 44 | #include "smi.h" |
91da11f8 | 45 | |
fad09c73 | 46 | static void assert_reg_lock(struct mv88e6xxx_chip *chip) |
3996a4ff | 47 | { |
fad09c73 VD |
48 | if (unlikely(!mutex_is_locked(&chip->reg_lock))) { |
49 | dev_err(chip->dev, "Switch registers lock not held!\n"); | |
3996a4ff VD |
50 | dump_stack(); |
51 | } | |
52 | } | |
53 | ||
ec561276 | 54 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) |
914b32f6 VD |
55 | { |
56 | int err; | |
57 | ||
fad09c73 | 58 | assert_reg_lock(chip); |
914b32f6 | 59 | |
fad09c73 | 60 | err = mv88e6xxx_smi_read(chip, addr, reg, val); |
914b32f6 VD |
61 | if (err) |
62 | return err; | |
63 | ||
fad09c73 | 64 | dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
914b32f6 VD |
65 | addr, reg, *val); |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
ec561276 | 70 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) |
91da11f8 | 71 | { |
914b32f6 VD |
72 | int err; |
73 | ||
fad09c73 | 74 | assert_reg_lock(chip); |
91da11f8 | 75 | |
fad09c73 | 76 | err = mv88e6xxx_smi_write(chip, addr, reg, val); |
914b32f6 VD |
77 | if (err) |
78 | return err; | |
79 | ||
fad09c73 | 80 | dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
bb92ea5e VD |
81 | addr, reg, val); |
82 | ||
914b32f6 VD |
83 | return 0; |
84 | } | |
85 | ||
683f2244 VD |
86 | int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, |
87 | u16 mask, u16 val) | |
88 | { | |
89 | u16 data; | |
90 | int err; | |
91 | int i; | |
92 | ||
93 | /* There's no bus specific operation to wait for a mask */ | |
94 | for (i = 0; i < 16; i++) { | |
95 | err = mv88e6xxx_read(chip, addr, reg, &data); | |
96 | if (err) | |
97 | return err; | |
98 | ||
99 | if ((data & mask) == val) | |
100 | return 0; | |
101 | ||
102 | usleep_range(1000, 2000); | |
103 | } | |
104 | ||
105 | dev_err(chip->dev, "Timeout while waiting for switch\n"); | |
106 | return -ETIMEDOUT; | |
107 | } | |
108 | ||
19fb7f69 VD |
109 | int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, |
110 | int bit, int val) | |
111 | { | |
112 | return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), | |
113 | val ? BIT(bit) : 0x0000); | |
114 | } | |
115 | ||
10fa5bfc | 116 | struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) |
a3c53be5 AL |
117 | { |
118 | struct mv88e6xxx_mdio_bus *mdio_bus; | |
119 | ||
120 | mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, | |
121 | list); | |
122 | if (!mdio_bus) | |
123 | return NULL; | |
124 | ||
125 | return mdio_bus->bus; | |
126 | } | |
127 | ||
dc30c35b AL |
128 | static void mv88e6xxx_g1_irq_mask(struct irq_data *d) |
129 | { | |
130 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
131 | unsigned int n = d->hwirq; | |
132 | ||
133 | chip->g1_irq.masked |= (1 << n); | |
134 | } | |
135 | ||
136 | static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) | |
137 | { | |
138 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
139 | unsigned int n = d->hwirq; | |
140 | ||
141 | chip->g1_irq.masked &= ~(1 << n); | |
142 | } | |
143 | ||
294d711e | 144 | static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) |
dc30c35b | 145 | { |
dc30c35b AL |
146 | unsigned int nhandled = 0; |
147 | unsigned int sub_irq; | |
148 | unsigned int n; | |
149 | u16 reg; | |
7c0db24c | 150 | u16 ctl1; |
dc30c35b AL |
151 | int err; |
152 | ||
c9acece0 | 153 | mv88e6xxx_reg_lock(chip); |
82466921 | 154 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); |
c9acece0 | 155 | mv88e6xxx_reg_unlock(chip); |
dc30c35b AL |
156 | |
157 | if (err) | |
158 | goto out; | |
159 | ||
7c0db24c JDA |
160 | do { |
161 | for (n = 0; n < chip->g1_irq.nirqs; ++n) { | |
162 | if (reg & (1 << n)) { | |
163 | sub_irq = irq_find_mapping(chip->g1_irq.domain, | |
164 | n); | |
165 | handle_nested_irq(sub_irq); | |
166 | ++nhandled; | |
167 | } | |
dc30c35b | 168 | } |
7c0db24c | 169 | |
c9acece0 | 170 | mv88e6xxx_reg_lock(chip); |
7c0db24c JDA |
171 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); |
172 | if (err) | |
173 | goto unlock; | |
174 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); | |
175 | unlock: | |
c9acece0 | 176 | mv88e6xxx_reg_unlock(chip); |
7c0db24c JDA |
177 | if (err) |
178 | goto out; | |
179 | ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); | |
180 | } while (reg & ctl1); | |
181 | ||
dc30c35b AL |
182 | out: |
183 | return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); | |
184 | } | |
185 | ||
294d711e AL |
186 | static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) |
187 | { | |
188 | struct mv88e6xxx_chip *chip = dev_id; | |
189 | ||
190 | return mv88e6xxx_g1_irq_thread_work(chip); | |
191 | } | |
192 | ||
dc30c35b AL |
193 | static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) |
194 | { | |
195 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
196 | ||
c9acece0 | 197 | mv88e6xxx_reg_lock(chip); |
dc30c35b AL |
198 | } |
199 | ||
200 | static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) | |
201 | { | |
202 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); | |
203 | u16 mask = GENMASK(chip->g1_irq.nirqs, 0); | |
204 | u16 reg; | |
205 | int err; | |
206 | ||
d77f4321 | 207 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); |
dc30c35b AL |
208 | if (err) |
209 | goto out; | |
210 | ||
211 | reg &= ~mask; | |
212 | reg |= (~chip->g1_irq.masked & mask); | |
213 | ||
d77f4321 | 214 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); |
dc30c35b AL |
215 | if (err) |
216 | goto out; | |
217 | ||
218 | out: | |
c9acece0 | 219 | mv88e6xxx_reg_unlock(chip); |
dc30c35b AL |
220 | } |
221 | ||
6eb15e21 | 222 | static const struct irq_chip mv88e6xxx_g1_irq_chip = { |
dc30c35b AL |
223 | .name = "mv88e6xxx-g1", |
224 | .irq_mask = mv88e6xxx_g1_irq_mask, | |
225 | .irq_unmask = mv88e6xxx_g1_irq_unmask, | |
226 | .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, | |
227 | .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, | |
228 | }; | |
229 | ||
230 | static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, | |
231 | unsigned int irq, | |
232 | irq_hw_number_t hwirq) | |
233 | { | |
234 | struct mv88e6xxx_chip *chip = d->host_data; | |
235 | ||
236 | irq_set_chip_data(irq, d->host_data); | |
237 | irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); | |
238 | irq_set_noprobe(irq); | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
243 | static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { | |
244 | .map = mv88e6xxx_g1_irq_domain_map, | |
245 | .xlate = irq_domain_xlate_twocell, | |
246 | }; | |
247 | ||
3d82475a | 248 | /* To be called with reg_lock held */ |
294d711e | 249 | static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) |
dc30c35b AL |
250 | { |
251 | int irq, virq; | |
3460a577 AL |
252 | u16 mask; |
253 | ||
d77f4321 | 254 | mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); |
3d5fdba1 | 255 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
d77f4321 | 256 | mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); |
3460a577 | 257 | |
5edef2f2 | 258 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { |
a3db3d3a | 259 | virq = irq_find_mapping(chip->g1_irq.domain, irq); |
dc30c35b AL |
260 | irq_dispose_mapping(virq); |
261 | } | |
262 | ||
a3db3d3a | 263 | irq_domain_remove(chip->g1_irq.domain); |
dc30c35b AL |
264 | } |
265 | ||
294d711e AL |
266 | static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) |
267 | { | |
3d82475a UKK |
268 | /* |
269 | * free_irq must be called without reg_lock taken because the irq | |
270 | * handler takes this lock, too. | |
271 | */ | |
294d711e | 272 | free_irq(chip->irq, chip); |
3d82475a | 273 | |
c9acece0 | 274 | mv88e6xxx_reg_lock(chip); |
3d82475a | 275 | mv88e6xxx_g1_irq_free_common(chip); |
c9acece0 | 276 | mv88e6xxx_reg_unlock(chip); |
294d711e AL |
277 | } |
278 | ||
279 | static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) | |
dc30c35b | 280 | { |
3dd0ef05 AL |
281 | int err, irq, virq; |
282 | u16 reg, mask; | |
dc30c35b AL |
283 | |
284 | chip->g1_irq.nirqs = chip->info->g1_irqs; | |
285 | chip->g1_irq.domain = irq_domain_add_simple( | |
286 | NULL, chip->g1_irq.nirqs, 0, | |
287 | &mv88e6xxx_g1_irq_domain_ops, chip); | |
288 | if (!chip->g1_irq.domain) | |
289 | return -ENOMEM; | |
290 | ||
291 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) | |
292 | irq_create_mapping(chip->g1_irq.domain, irq); | |
293 | ||
294 | chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; | |
295 | chip->g1_irq.masked = ~0; | |
296 | ||
d77f4321 | 297 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); |
dc30c35b | 298 | if (err) |
3dd0ef05 | 299 | goto out_mapping; |
dc30c35b | 300 | |
3dd0ef05 | 301 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
dc30c35b | 302 | |
d77f4321 | 303 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); |
dc30c35b | 304 | if (err) |
3dd0ef05 | 305 | goto out_disable; |
dc30c35b AL |
306 | |
307 | /* Reading the interrupt status clears (most of) them */ | |
82466921 | 308 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); |
dc30c35b | 309 | if (err) |
3dd0ef05 | 310 | goto out_disable; |
dc30c35b | 311 | |
dc30c35b AL |
312 | return 0; |
313 | ||
3dd0ef05 | 314 | out_disable: |
3d5fdba1 | 315 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
d77f4321 | 316 | mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); |
3dd0ef05 AL |
317 | |
318 | out_mapping: | |
319 | for (irq = 0; irq < 16; irq++) { | |
320 | virq = irq_find_mapping(chip->g1_irq.domain, irq); | |
321 | irq_dispose_mapping(virq); | |
322 | } | |
323 | ||
324 | irq_domain_remove(chip->g1_irq.domain); | |
dc30c35b AL |
325 | |
326 | return err; | |
327 | } | |
328 | ||
294d711e AL |
329 | static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) |
330 | { | |
f6d9758b AL |
331 | static struct lock_class_key lock_key; |
332 | static struct lock_class_key request_key; | |
294d711e AL |
333 | int err; |
334 | ||
335 | err = mv88e6xxx_g1_irq_setup_common(chip); | |
336 | if (err) | |
337 | return err; | |
338 | ||
f6d9758b AL |
339 | /* These lock classes tells lockdep that global 1 irqs are in |
340 | * a different category than their parent GPIO, so it won't | |
341 | * report false recursion. | |
342 | */ | |
343 | irq_set_lockdep_class(chip->irq, &lock_key, &request_key); | |
344 | ||
3095383a AL |
345 | snprintf(chip->irq_name, sizeof(chip->irq_name), |
346 | "mv88e6xxx-%s", dev_name(chip->dev)); | |
347 | ||
c9acece0 | 348 | mv88e6xxx_reg_unlock(chip); |
294d711e AL |
349 | err = request_threaded_irq(chip->irq, NULL, |
350 | mv88e6xxx_g1_irq_thread_fn, | |
0340376e | 351 | IRQF_ONESHOT | IRQF_SHARED, |
3095383a | 352 | chip->irq_name, chip); |
c9acece0 | 353 | mv88e6xxx_reg_lock(chip); |
294d711e AL |
354 | if (err) |
355 | mv88e6xxx_g1_irq_free_common(chip); | |
356 | ||
357 | return err; | |
358 | } | |
359 | ||
360 | static void mv88e6xxx_irq_poll(struct kthread_work *work) | |
361 | { | |
362 | struct mv88e6xxx_chip *chip = container_of(work, | |
363 | struct mv88e6xxx_chip, | |
364 | irq_poll_work.work); | |
365 | mv88e6xxx_g1_irq_thread_work(chip); | |
366 | ||
367 | kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, | |
368 | msecs_to_jiffies(100)); | |
369 | } | |
370 | ||
371 | static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) | |
372 | { | |
373 | int err; | |
374 | ||
375 | err = mv88e6xxx_g1_irq_setup_common(chip); | |
376 | if (err) | |
377 | return err; | |
378 | ||
379 | kthread_init_delayed_work(&chip->irq_poll_work, | |
380 | mv88e6xxx_irq_poll); | |
381 | ||
3f8b8696 | 382 | chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); |
294d711e AL |
383 | if (IS_ERR(chip->kworker)) |
384 | return PTR_ERR(chip->kworker); | |
385 | ||
386 | kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, | |
387 | msecs_to_jiffies(100)); | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
392 | static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) | |
393 | { | |
394 | kthread_cancel_delayed_work_sync(&chip->irq_poll_work); | |
395 | kthread_destroy_worker(chip->kworker); | |
3d82475a | 396 | |
c9acece0 | 397 | mv88e6xxx_reg_lock(chip); |
3d82475a | 398 | mv88e6xxx_g1_irq_free_common(chip); |
c9acece0 | 399 | mv88e6xxx_reg_unlock(chip); |
294d711e AL |
400 | } |
401 | ||
64d47d50 RK |
402 | static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, |
403 | int port, phy_interface_t interface) | |
404 | { | |
405 | int err; | |
406 | ||
407 | if (chip->info->ops->port_set_rgmii_delay) { | |
408 | err = chip->info->ops->port_set_rgmii_delay(chip, port, | |
409 | interface); | |
410 | if (err && err != -EOPNOTSUPP) | |
411 | return err; | |
412 | } | |
413 | ||
414 | if (chip->info->ops->port_set_cmode) { | |
415 | err = chip->info->ops->port_set_cmode(chip, port, | |
416 | interface); | |
417 | if (err && err != -EOPNOTSUPP) | |
418 | return err; | |
419 | } | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
a5a6858b RK |
424 | static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, |
425 | int link, int speed, int duplex, int pause, | |
426 | phy_interface_t mode) | |
d78343d2 VD |
427 | { |
428 | int err; | |
429 | ||
430 | if (!chip->info->ops->port_set_link) | |
431 | return 0; | |
432 | ||
433 | /* Port's MAC control must not be changed unless the link is down */ | |
43c8e0ae | 434 | err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); |
d78343d2 VD |
435 | if (err) |
436 | return err; | |
437 | ||
f365c6f7 RK |
438 | if (chip->info->ops->port_set_speed_duplex) { |
439 | err = chip->info->ops->port_set_speed_duplex(chip, port, | |
440 | speed, duplex); | |
d78343d2 VD |
441 | if (err && err != -EOPNOTSUPP) |
442 | goto restore_link; | |
443 | } | |
444 | ||
7cbbee05 AL |
445 | if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) |
446 | mode = chip->info->ops->port_max_speed_mode(port); | |
447 | ||
54186b91 AL |
448 | if (chip->info->ops->port_set_pause) { |
449 | err = chip->info->ops->port_set_pause(chip, port, pause); | |
450 | if (err) | |
451 | goto restore_link; | |
452 | } | |
453 | ||
64d47d50 | 454 | err = mv88e6xxx_port_config_interface(chip, port, mode); |
d78343d2 VD |
455 | restore_link: |
456 | if (chip->info->ops->port_set_link(chip, port, link)) | |
774439e5 | 457 | dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); |
d78343d2 VD |
458 | |
459 | return err; | |
460 | } | |
461 | ||
d700ec41 MV |
462 | static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) |
463 | { | |
464 | struct mv88e6xxx_chip *chip = ds->priv; | |
465 | ||
466 | return port < chip->info->num_internal_phys; | |
467 | } | |
468 | ||
5d5b231d RK |
469 | static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) |
470 | { | |
471 | u16 reg; | |
472 | int err; | |
473 | ||
474 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); | |
475 | if (err) { | |
476 | dev_err(chip->dev, | |
477 | "p%d: %s: failed to read port status\n", | |
478 | port, __func__); | |
479 | return err; | |
480 | } | |
481 | ||
482 | return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); | |
483 | } | |
484 | ||
a5a6858b RK |
485 | static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, |
486 | struct phylink_link_state *state) | |
487 | { | |
488 | struct mv88e6xxx_chip *chip = ds->priv; | |
193c5b26 | 489 | int lane; |
a5a6858b RK |
490 | int err; |
491 | ||
492 | mv88e6xxx_reg_lock(chip); | |
493 | lane = mv88e6xxx_serdes_get_lane(chip, port); | |
193c5b26 | 494 | if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) |
a5a6858b RK |
495 | err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, |
496 | state); | |
497 | else | |
498 | err = -EOPNOTSUPP; | |
499 | mv88e6xxx_reg_unlock(chip); | |
500 | ||
501 | return err; | |
502 | } | |
503 | ||
504 | static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, | |
505 | unsigned int mode, | |
506 | phy_interface_t interface, | |
507 | const unsigned long *advertise) | |
508 | { | |
509 | const struct mv88e6xxx_ops *ops = chip->info->ops; | |
193c5b26 | 510 | int lane; |
a5a6858b RK |
511 | |
512 | if (ops->serdes_pcs_config) { | |
513 | lane = mv88e6xxx_serdes_get_lane(chip, port); | |
193c5b26 | 514 | if (lane >= 0) |
a5a6858b RK |
515 | return ops->serdes_pcs_config(chip, port, lane, mode, |
516 | interface, advertise); | |
517 | } | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) | |
523 | { | |
524 | struct mv88e6xxx_chip *chip = ds->priv; | |
525 | const struct mv88e6xxx_ops *ops; | |
526 | int err = 0; | |
193c5b26 | 527 | int lane; |
a5a6858b RK |
528 | |
529 | ops = chip->info->ops; | |
530 | ||
531 | if (ops->serdes_pcs_an_restart) { | |
532 | mv88e6xxx_reg_lock(chip); | |
533 | lane = mv88e6xxx_serdes_get_lane(chip, port); | |
193c5b26 | 534 | if (lane >= 0) |
a5a6858b RK |
535 | err = ops->serdes_pcs_an_restart(chip, port, lane); |
536 | mv88e6xxx_reg_unlock(chip); | |
537 | ||
538 | if (err) | |
539 | dev_err(ds->dev, "p%d: failed to restart AN\n", port); | |
540 | } | |
541 | } | |
542 | ||
543 | static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, | |
544 | unsigned int mode, | |
545 | int speed, int duplex) | |
546 | { | |
547 | const struct mv88e6xxx_ops *ops = chip->info->ops; | |
193c5b26 | 548 | int lane; |
a5a6858b RK |
549 | |
550 | if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { | |
551 | lane = mv88e6xxx_serdes_get_lane(chip, port); | |
193c5b26 | 552 | if (lane >= 0) |
a5a6858b RK |
553 | return ops->serdes_pcs_link_up(chip, port, lane, |
554 | speed, duplex); | |
555 | } | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
6c422e34 RK |
560 | static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
561 | unsigned long *mask, | |
562 | struct phylink_link_state *state) | |
563 | { | |
564 | if (!phy_interface_mode_is_8023z(state->interface)) { | |
565 | /* 10M and 100M are only supported in non-802.3z mode */ | |
566 | phylink_set(mask, 10baseT_Half); | |
567 | phylink_set(mask, 10baseT_Full); | |
568 | phylink_set(mask, 100baseT_Half); | |
569 | phylink_set(mask, 100baseT_Full); | |
570 | } | |
571 | } | |
572 | ||
573 | static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, | |
574 | unsigned long *mask, | |
575 | struct phylink_link_state *state) | |
576 | { | |
577 | /* FIXME: if the port is in 1000Base-X mode, then it only supports | |
578 | * 1000M FD speeds. In this case, CMODE will indicate 5. | |
579 | */ | |
580 | phylink_set(mask, 1000baseT_Full); | |
581 | phylink_set(mask, 1000baseX_Full); | |
582 | ||
583 | mv88e6065_phylink_validate(chip, port, mask, state); | |
584 | } | |
585 | ||
e3af71a3 MB |
586 | static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
587 | unsigned long *mask, | |
588 | struct phylink_link_state *state) | |
589 | { | |
590 | if (port >= 5) | |
591 | phylink_set(mask, 2500baseX_Full); | |
592 | ||
593 | /* No ethtool bits for 200Mbps */ | |
594 | phylink_set(mask, 1000baseT_Full); | |
595 | phylink_set(mask, 1000baseX_Full); | |
596 | ||
597 | mv88e6065_phylink_validate(chip, port, mask, state); | |
598 | } | |
599 | ||
6c422e34 RK |
600 | static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
601 | unsigned long *mask, | |
602 | struct phylink_link_state *state) | |
603 | { | |
604 | /* No ethtool bits for 200Mbps */ | |
605 | phylink_set(mask, 1000baseT_Full); | |
606 | phylink_set(mask, 1000baseX_Full); | |
607 | ||
608 | mv88e6065_phylink_validate(chip, port, mask, state); | |
609 | } | |
610 | ||
611 | static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, | |
612 | unsigned long *mask, | |
613 | struct phylink_link_state *state) | |
614 | { | |
ec26016b | 615 | if (port >= 9) { |
6c422e34 | 616 | phylink_set(mask, 2500baseX_Full); |
ec26016b AL |
617 | phylink_set(mask, 2500baseT_Full); |
618 | } | |
6c422e34 RK |
619 | |
620 | /* No ethtool bits for 200Mbps */ | |
621 | phylink_set(mask, 1000baseT_Full); | |
622 | phylink_set(mask, 1000baseX_Full); | |
623 | ||
624 | mv88e6065_phylink_validate(chip, port, mask, state); | |
625 | } | |
626 | ||
627 | static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, | |
628 | unsigned long *mask, | |
629 | struct phylink_link_state *state) | |
630 | { | |
631 | if (port >= 9) { | |
632 | phylink_set(mask, 10000baseT_Full); | |
633 | phylink_set(mask, 10000baseKR_Full); | |
634 | } | |
635 | ||
636 | mv88e6390_phylink_validate(chip, port, mask, state); | |
637 | } | |
638 | ||
de776d0d PS |
639 | static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, |
640 | unsigned long *mask, | |
641 | struct phylink_link_state *state) | |
642 | { | |
643 | if (port == 0 || port == 9 || port == 10) { | |
644 | phylink_set(mask, 10000baseT_Full); | |
645 | phylink_set(mask, 10000baseKR_Full); | |
646 | phylink_set(mask, 10000baseCR_Full); | |
647 | phylink_set(mask, 10000baseSR_Full); | |
648 | phylink_set(mask, 10000baseLR_Full); | |
649 | phylink_set(mask, 10000baseLRM_Full); | |
650 | phylink_set(mask, 10000baseER_Full); | |
651 | phylink_set(mask, 5000baseT_Full); | |
652 | phylink_set(mask, 2500baseX_Full); | |
653 | phylink_set(mask, 2500baseT_Full); | |
654 | } | |
655 | ||
656 | phylink_set(mask, 1000baseT_Full); | |
657 | phylink_set(mask, 1000baseX_Full); | |
658 | ||
659 | mv88e6065_phylink_validate(chip, port, mask, state); | |
660 | } | |
661 | ||
c9a2356f RK |
662 | static void mv88e6xxx_validate(struct dsa_switch *ds, int port, |
663 | unsigned long *supported, | |
664 | struct phylink_link_state *state) | |
665 | { | |
6c422e34 RK |
666 | __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; |
667 | struct mv88e6xxx_chip *chip = ds->priv; | |
668 | ||
669 | /* Allow all the expected bits */ | |
670 | phylink_set(mask, Autoneg); | |
671 | phylink_set(mask, Pause); | |
672 | phylink_set_port_modes(mask); | |
673 | ||
674 | if (chip->info->ops->phylink_validate) | |
675 | chip->info->ops->phylink_validate(chip, port, mask, state); | |
676 | ||
4973056c SA |
677 | linkmode_and(supported, supported, mask); |
678 | linkmode_and(state->advertising, state->advertising, mask); | |
6c422e34 RK |
679 | |
680 | /* We can only operate at 2500BaseX or 1000BaseX. If requested | |
681 | * to advertise both, only report advertising at 2500BaseX. | |
682 | */ | |
683 | phylink_helper_basex_speed(state); | |
c9a2356f RK |
684 | } |
685 | ||
c9a2356f RK |
686 | static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, |
687 | unsigned int mode, | |
688 | const struct phylink_link_state *state) | |
689 | { | |
690 | struct mv88e6xxx_chip *chip = ds->priv; | |
fad58190 | 691 | struct mv88e6xxx_port *p; |
64d47d50 | 692 | int err; |
c9a2356f | 693 | |
fad58190 RK |
694 | p = &chip->ports[port]; |
695 | ||
64d47d50 RK |
696 | /* FIXME: is this the correct test? If we're in fixed mode on an |
697 | * internal port, why should we process this any different from | |
698 | * PHY mode? On the other hand, the port may be automedia between | |
699 | * an internal PHY and the serdes... | |
700 | */ | |
d700ec41 | 701 | if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) |
c9a2356f RK |
702 | return; |
703 | ||
c9acece0 | 704 | mv88e6xxx_reg_lock(chip); |
fad58190 RK |
705 | /* In inband mode, the link may come up at any time while the link |
706 | * is not forced down. Force the link down while we reconfigure the | |
707 | * interface mode. | |
64d47d50 | 708 | */ |
fad58190 RK |
709 | if (mode == MLO_AN_INBAND && p->interface != state->interface && |
710 | chip->info->ops->port_set_link) | |
711 | chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); | |
712 | ||
64d47d50 | 713 | err = mv88e6xxx_port_config_interface(chip, port, state->interface); |
a5a6858b RK |
714 | if (err && err != -EOPNOTSUPP) |
715 | goto err_unlock; | |
716 | ||
717 | err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, | |
718 | state->advertising); | |
719 | /* FIXME: we should restart negotiation if something changed - which | |
720 | * is something we get if we convert to using phylinks PCS operations. | |
721 | */ | |
722 | if (err > 0) | |
723 | err = 0; | |
724 | ||
fad58190 RK |
725 | /* Undo the forced down state above after completing configuration |
726 | * irrespective of its state on entry, which allows the link to come up. | |
727 | */ | |
728 | if (mode == MLO_AN_INBAND && p->interface != state->interface && | |
729 | chip->info->ops->port_set_link) | |
730 | chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); | |
731 | ||
732 | p->interface = state->interface; | |
733 | ||
a5a6858b | 734 | err_unlock: |
c9acece0 | 735 | mv88e6xxx_reg_unlock(chip); |
c9a2356f RK |
736 | |
737 | if (err && err != -EOPNOTSUPP) | |
64d47d50 | 738 | dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); |
c9a2356f RK |
739 | } |
740 | ||
30c4a5b0 RK |
741 | static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, |
742 | unsigned int mode, | |
743 | phy_interface_t interface) | |
c9a2356f RK |
744 | { |
745 | struct mv88e6xxx_chip *chip = ds->priv; | |
30c4a5b0 RK |
746 | const struct mv88e6xxx_ops *ops; |
747 | int err = 0; | |
c9a2356f | 748 | |
30c4a5b0 | 749 | ops = chip->info->ops; |
c9a2356f | 750 | |
5d5b231d | 751 | mv88e6xxx_reg_lock(chip); |
4a3e0aed MZ |
752 | /* Internal PHYs propagate their configuration directly to the MAC. |
753 | * External PHYs depend on whether the PPU is enabled for this port. | |
754 | */ | |
755 | if (((!mv88e6xxx_phy_is_internal(ds, port) && | |
756 | !mv88e6xxx_port_ppu_updates(chip, port)) || | |
4efe7662 CP |
757 | mode == MLO_AN_FIXED) && ops->port_sync_link) |
758 | err = ops->port_sync_link(chip, port, mode, false); | |
5d5b231d | 759 | mv88e6xxx_reg_unlock(chip); |
c9a2356f | 760 | |
5d5b231d RK |
761 | if (err) |
762 | dev_err(chip->dev, | |
763 | "p%d: failed to force MAC link down\n", port); | |
c9a2356f RK |
764 | } |
765 | ||
766 | static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, | |
767 | unsigned int mode, phy_interface_t interface, | |
5b502a7b RK |
768 | struct phy_device *phydev, |
769 | int speed, int duplex, | |
770 | bool tx_pause, bool rx_pause) | |
c9a2356f | 771 | { |
30c4a5b0 RK |
772 | struct mv88e6xxx_chip *chip = ds->priv; |
773 | const struct mv88e6xxx_ops *ops; | |
774 | int err = 0; | |
775 | ||
776 | ops = chip->info->ops; | |
777 | ||
5d5b231d | 778 | mv88e6xxx_reg_lock(chip); |
4a3e0aed MZ |
779 | /* Internal PHYs propagate their configuration directly to the MAC. |
780 | * External PHYs depend on whether the PPU is enabled for this port. | |
781 | */ | |
782 | if ((!mv88e6xxx_phy_is_internal(ds, port) && | |
783 | !mv88e6xxx_port_ppu_updates(chip, port)) || | |
784 | mode == MLO_AN_FIXED) { | |
30c4a5b0 RK |
785 | /* FIXME: for an automedia port, should we force the link |
786 | * down here - what if the link comes up due to "other" media | |
787 | * while we're bringing the port up, how is the exclusivity | |
a5a6858b | 788 | * handled in the Marvell hardware? E.g. port 2 on 88E6390 |
30c4a5b0 RK |
789 | * shared between internal PHY and Serdes. |
790 | */ | |
a5a6858b RK |
791 | err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, |
792 | duplex); | |
793 | if (err) | |
794 | goto error; | |
795 | ||
f365c6f7 RK |
796 | if (ops->port_set_speed_duplex) { |
797 | err = ops->port_set_speed_duplex(chip, port, | |
798 | speed, duplex); | |
30c4a5b0 RK |
799 | if (err && err != -EOPNOTSUPP) |
800 | goto error; | |
801 | } | |
802 | ||
4efe7662 CP |
803 | if (ops->port_sync_link) |
804 | err = ops->port_sync_link(chip, port, mode, true); | |
5d5b231d | 805 | } |
30c4a5b0 | 806 | error: |
5d5b231d | 807 | mv88e6xxx_reg_unlock(chip); |
30c4a5b0 | 808 | |
5d5b231d RK |
809 | if (err && err != -EOPNOTSUPP) |
810 | dev_err(ds->dev, | |
811 | "p%d: failed to configure MAC link up\n", port); | |
c9a2356f RK |
812 | } |
813 | ||
a605a0fe | 814 | static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) |
91da11f8 | 815 | { |
a605a0fe AL |
816 | if (!chip->info->ops->stats_snapshot) |
817 | return -EOPNOTSUPP; | |
91da11f8 | 818 | |
a605a0fe | 819 | return chip->info->ops->stats_snapshot(chip, port); |
91da11f8 LB |
820 | } |
821 | ||
e413e7e1 | 822 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
dfafe449 AL |
823 | { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, |
824 | { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, | |
825 | { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, | |
826 | { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, | |
827 | { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, | |
828 | { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, | |
829 | { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, | |
830 | { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, | |
831 | { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, | |
832 | { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, | |
833 | { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, | |
834 | { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, | |
835 | { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, | |
836 | { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, | |
837 | { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, | |
838 | { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, | |
839 | { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, | |
840 | { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, | |
841 | { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, | |
842 | { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, | |
843 | { "single", 4, 0x14, STATS_TYPE_BANK0, }, | |
844 | { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, | |
845 | { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, | |
846 | { "late", 4, 0x1f, STATS_TYPE_BANK0, }, | |
847 | { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, | |
848 | { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, | |
849 | { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, | |
850 | { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, | |
851 | { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, | |
852 | { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, | |
853 | { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, | |
854 | { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, | |
855 | { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, | |
856 | { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, | |
857 | { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, | |
858 | { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, | |
859 | { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, | |
860 | { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, | |
861 | { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, | |
862 | { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, | |
863 | { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, | |
864 | { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, | |
865 | { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, | |
866 | { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, | |
867 | { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, | |
868 | { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, | |
869 | { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, | |
870 | { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, | |
871 | { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, | |
872 | { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, | |
873 | { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, | |
874 | { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, | |
875 | { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, | |
876 | { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, | |
877 | { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, | |
878 | { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, | |
879 | { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, | |
880 | { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, | |
881 | { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, | |
e413e7e1 AL |
882 | }; |
883 | ||
fad09c73 | 884 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, |
f5e2ed02 | 885 | struct mv88e6xxx_hw_stat *s, |
e0d8b615 AL |
886 | int port, u16 bank1_select, |
887 | u16 histogram) | |
80c4627b | 888 | { |
80c4627b AL |
889 | u32 low; |
890 | u32 high = 0; | |
dfafe449 | 891 | u16 reg = 0; |
0e7b9925 | 892 | int err; |
80c4627b AL |
893 | u64 value; |
894 | ||
f5e2ed02 | 895 | switch (s->type) { |
dfafe449 | 896 | case STATS_TYPE_PORT: |
0e7b9925 AL |
897 | err = mv88e6xxx_port_read(chip, port, s->reg, ®); |
898 | if (err) | |
6c3442f5 | 899 | return U64_MAX; |
80c4627b | 900 | |
0e7b9925 | 901 | low = reg; |
cda9f4aa | 902 | if (s->size == 4) { |
0e7b9925 AL |
903 | err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); |
904 | if (err) | |
6c3442f5 | 905 | return U64_MAX; |
84b3fd1f | 906 | low |= ((u32)reg) << 16; |
80c4627b | 907 | } |
f5e2ed02 | 908 | break; |
dfafe449 | 909 | case STATS_TYPE_BANK1: |
e0d8b615 | 910 | reg = bank1_select; |
df561f66 | 911 | fallthrough; |
dfafe449 | 912 | case STATS_TYPE_BANK0: |
e0d8b615 | 913 | reg |= s->reg | histogram; |
7f9ef3af | 914 | mv88e6xxx_g1_stats_read(chip, reg, &low); |
cda9f4aa | 915 | if (s->size == 8) |
7f9ef3af | 916 | mv88e6xxx_g1_stats_read(chip, reg + 1, &high); |
9fc3e4dc GS |
917 | break; |
918 | default: | |
6c3442f5 | 919 | return U64_MAX; |
80c4627b | 920 | } |
6e46e2d8 | 921 | value = (((u64)high) << 32) | low; |
80c4627b AL |
922 | return value; |
923 | } | |
924 | ||
436fe17d AL |
925 | static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, |
926 | uint8_t *data, int types) | |
91da11f8 | 927 | { |
f5e2ed02 AL |
928 | struct mv88e6xxx_hw_stat *stat; |
929 | int i, j; | |
91da11f8 | 930 | |
f5e2ed02 AL |
931 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
932 | stat = &mv88e6xxx_hw_stats[i]; | |
dfafe449 | 933 | if (stat->type & types) { |
f5e2ed02 AL |
934 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
935 | ETH_GSTRING_LEN); | |
936 | j++; | |
937 | } | |
91da11f8 | 938 | } |
436fe17d AL |
939 | |
940 | return j; | |
e413e7e1 AL |
941 | } |
942 | ||
436fe17d AL |
943 | static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, |
944 | uint8_t *data) | |
dfafe449 | 945 | { |
436fe17d AL |
946 | return mv88e6xxx_stats_get_strings(chip, data, |
947 | STATS_TYPE_BANK0 | STATS_TYPE_PORT); | |
dfafe449 AL |
948 | } |
949 | ||
1f71836f RV |
950 | static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, |
951 | uint8_t *data) | |
952 | { | |
953 | return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); | |
954 | } | |
955 | ||
436fe17d AL |
956 | static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, |
957 | uint8_t *data) | |
dfafe449 | 958 | { |
436fe17d AL |
959 | return mv88e6xxx_stats_get_strings(chip, data, |
960 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1); | |
dfafe449 AL |
961 | } |
962 | ||
65f60e45 AL |
963 | static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { |
964 | "atu_member_violation", | |
965 | "atu_miss_violation", | |
966 | "atu_full_violation", | |
967 | "vtu_member_violation", | |
968 | "vtu_miss_violation", | |
969 | }; | |
970 | ||
971 | static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) | |
972 | { | |
973 | unsigned int i; | |
974 | ||
975 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) | |
976 | strlcpy(data + i * ETH_GSTRING_LEN, | |
977 | mv88e6xxx_atu_vtu_stats_strings[i], | |
978 | ETH_GSTRING_LEN); | |
979 | } | |
980 | ||
dfafe449 | 981 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, |
89f09048 | 982 | u32 stringset, uint8_t *data) |
e413e7e1 | 983 | { |
04bed143 | 984 | struct mv88e6xxx_chip *chip = ds->priv; |
436fe17d | 985 | int count = 0; |
dfafe449 | 986 | |
89f09048 FF |
987 | if (stringset != ETH_SS_STATS) |
988 | return; | |
989 | ||
c9acece0 | 990 | mv88e6xxx_reg_lock(chip); |
c6c8cd5e | 991 | |
dfafe449 | 992 | if (chip->info->ops->stats_get_strings) |
436fe17d AL |
993 | count = chip->info->ops->stats_get_strings(chip, data); |
994 | ||
995 | if (chip->info->ops->serdes_get_strings) { | |
996 | data += count * ETH_GSTRING_LEN; | |
65f60e45 | 997 | count = chip->info->ops->serdes_get_strings(chip, port, data); |
436fe17d | 998 | } |
c6c8cd5e | 999 | |
65f60e45 AL |
1000 | data += count * ETH_GSTRING_LEN; |
1001 | mv88e6xxx_atu_vtu_get_strings(data); | |
1002 | ||
c9acece0 | 1003 | mv88e6xxx_reg_unlock(chip); |
dfafe449 AL |
1004 | } |
1005 | ||
1006 | static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, | |
1007 | int types) | |
1008 | { | |
f5e2ed02 AL |
1009 | struct mv88e6xxx_hw_stat *stat; |
1010 | int i, j; | |
1011 | ||
1012 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
1013 | stat = &mv88e6xxx_hw_stats[i]; | |
dfafe449 | 1014 | if (stat->type & types) |
f5e2ed02 AL |
1015 | j++; |
1016 | } | |
1017 | return j; | |
e413e7e1 AL |
1018 | } |
1019 | ||
dfafe449 AL |
1020 | static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
1021 | { | |
1022 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | | |
1023 | STATS_TYPE_PORT); | |
1024 | } | |
1025 | ||
1f71836f RV |
1026 | static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
1027 | { | |
1028 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); | |
1029 | } | |
1030 | ||
dfafe449 AL |
1031 | static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
1032 | { | |
1033 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | | |
1034 | STATS_TYPE_BANK1); | |
1035 | } | |
1036 | ||
89f09048 | 1037 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) |
dfafe449 AL |
1038 | { |
1039 | struct mv88e6xxx_chip *chip = ds->priv; | |
436fe17d AL |
1040 | int serdes_count = 0; |
1041 | int count = 0; | |
dfafe449 | 1042 | |
89f09048 FF |
1043 | if (sset != ETH_SS_STATS) |
1044 | return 0; | |
1045 | ||
c9acece0 | 1046 | mv88e6xxx_reg_lock(chip); |
dfafe449 | 1047 | if (chip->info->ops->stats_get_sset_count) |
436fe17d AL |
1048 | count = chip->info->ops->stats_get_sset_count(chip); |
1049 | if (count < 0) | |
1050 | goto out; | |
1051 | ||
1052 | if (chip->info->ops->serdes_get_sset_count) | |
1053 | serdes_count = chip->info->ops->serdes_get_sset_count(chip, | |
1054 | port); | |
65f60e45 | 1055 | if (serdes_count < 0) { |
436fe17d | 1056 | count = serdes_count; |
65f60e45 AL |
1057 | goto out; |
1058 | } | |
1059 | count += serdes_count; | |
1060 | count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); | |
1061 | ||
436fe17d | 1062 | out: |
c9acece0 | 1063 | mv88e6xxx_reg_unlock(chip); |
dfafe449 | 1064 | |
436fe17d | 1065 | return count; |
dfafe449 AL |
1066 | } |
1067 | ||
436fe17d AL |
1068 | static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
1069 | uint64_t *data, int types, | |
1070 | u16 bank1_select, u16 histogram) | |
052f947f AL |
1071 | { |
1072 | struct mv88e6xxx_hw_stat *stat; | |
1073 | int i, j; | |
1074 | ||
1075 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { | |
1076 | stat = &mv88e6xxx_hw_stats[i]; | |
1077 | if (stat->type & types) { | |
c9acece0 | 1078 | mv88e6xxx_reg_lock(chip); |
e0d8b615 AL |
1079 | data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, |
1080 | bank1_select, | |
1081 | histogram); | |
c9acece0 | 1082 | mv88e6xxx_reg_unlock(chip); |
377cda13 | 1083 | |
052f947f AL |
1084 | j++; |
1085 | } | |
1086 | } | |
436fe17d | 1087 | return j; |
052f947f AL |
1088 | } |
1089 | ||
436fe17d AL |
1090 | static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
1091 | uint64_t *data) | |
052f947f AL |
1092 | { |
1093 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
e0d8b615 | 1094 | STATS_TYPE_BANK0 | STATS_TYPE_PORT, |
57d1ef38 | 1095 | 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); |
052f947f AL |
1096 | } |
1097 | ||
1f71836f RV |
1098 | static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
1099 | uint64_t *data) | |
1100 | { | |
1101 | return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, | |
1102 | 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); | |
1103 | } | |
1104 | ||
436fe17d AL |
1105 | static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
1106 | uint64_t *data) | |
052f947f AL |
1107 | { |
1108 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
e0d8b615 | 1109 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1, |
57d1ef38 VD |
1110 | MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, |
1111 | MV88E6XXX_G1_STATS_OP_HIST_RX_TX); | |
e0d8b615 AL |
1112 | } |
1113 | ||
436fe17d AL |
1114 | static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
1115 | uint64_t *data) | |
e0d8b615 AL |
1116 | { |
1117 | return mv88e6xxx_stats_get_stats(chip, port, data, | |
1118 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1, | |
57d1ef38 VD |
1119 | MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, |
1120 | 0); | |
052f947f AL |
1121 | } |
1122 | ||
65f60e45 AL |
1123 | static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, |
1124 | uint64_t *data) | |
1125 | { | |
1126 | *data++ = chip->ports[port].atu_member_violation; | |
1127 | *data++ = chip->ports[port].atu_miss_violation; | |
1128 | *data++ = chip->ports[port].atu_full_violation; | |
1129 | *data++ = chip->ports[port].vtu_member_violation; | |
1130 | *data++ = chip->ports[port].vtu_miss_violation; | |
1131 | } | |
1132 | ||
052f947f AL |
1133 | static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, |
1134 | uint64_t *data) | |
1135 | { | |
436fe17d AL |
1136 | int count = 0; |
1137 | ||
052f947f | 1138 | if (chip->info->ops->stats_get_stats) |
436fe17d AL |
1139 | count = chip->info->ops->stats_get_stats(chip, port, data); |
1140 | ||
c9acece0 | 1141 | mv88e6xxx_reg_lock(chip); |
436fe17d AL |
1142 | if (chip->info->ops->serdes_get_stats) { |
1143 | data += count; | |
65f60e45 | 1144 | count = chip->info->ops->serdes_get_stats(chip, port, data); |
436fe17d | 1145 | } |
65f60e45 AL |
1146 | data += count; |
1147 | mv88e6xxx_atu_vtu_get_stats(chip, port, data); | |
c9acece0 | 1148 | mv88e6xxx_reg_unlock(chip); |
052f947f AL |
1149 | } |
1150 | ||
f81ec90f VD |
1151 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
1152 | uint64_t *data) | |
e413e7e1 | 1153 | { |
04bed143 | 1154 | struct mv88e6xxx_chip *chip = ds->priv; |
f5e2ed02 | 1155 | int ret; |
f5e2ed02 | 1156 | |
c9acece0 | 1157 | mv88e6xxx_reg_lock(chip); |
f5e2ed02 | 1158 | |
a605a0fe | 1159 | ret = mv88e6xxx_stats_snapshot(chip, port); |
c9acece0 | 1160 | mv88e6xxx_reg_unlock(chip); |
377cda13 AL |
1161 | |
1162 | if (ret < 0) | |
f5e2ed02 | 1163 | return; |
052f947f AL |
1164 | |
1165 | mv88e6xxx_get_stats(chip, port, data); | |
f5e2ed02 | 1166 | |
e413e7e1 AL |
1167 | } |
1168 | ||
f81ec90f | 1169 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
a1ab91f3 | 1170 | { |
0d30bbd0 AL |
1171 | struct mv88e6xxx_chip *chip = ds->priv; |
1172 | int len; | |
1173 | ||
1174 | len = 32 * sizeof(u16); | |
1175 | if (chip->info->ops->serdes_get_regs_len) | |
1176 | len += chip->info->ops->serdes_get_regs_len(chip, port); | |
1177 | ||
1178 | return len; | |
a1ab91f3 GR |
1179 | } |
1180 | ||
f81ec90f VD |
1181 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
1182 | struct ethtool_regs *regs, void *_p) | |
a1ab91f3 | 1183 | { |
04bed143 | 1184 | struct mv88e6xxx_chip *chip = ds->priv; |
0e7b9925 AL |
1185 | int err; |
1186 | u16 reg; | |
a1ab91f3 GR |
1187 | u16 *p = _p; |
1188 | int i; | |
1189 | ||
a5f39326 | 1190 | regs->version = chip->info->prod_num; |
a1ab91f3 GR |
1191 | |
1192 | memset(p, 0xff, 32 * sizeof(u16)); | |
1193 | ||
c9acece0 | 1194 | mv88e6xxx_reg_lock(chip); |
23062513 | 1195 | |
a1ab91f3 | 1196 | for (i = 0; i < 32; i++) { |
a1ab91f3 | 1197 | |
0e7b9925 AL |
1198 | err = mv88e6xxx_port_read(chip, port, i, ®); |
1199 | if (!err) | |
1200 | p[i] = reg; | |
a1ab91f3 | 1201 | } |
23062513 | 1202 | |
0d30bbd0 AL |
1203 | if (chip->info->ops->serdes_get_regs) |
1204 | chip->info->ops->serdes_get_regs(chip, port, &p[i]); | |
1205 | ||
c9acece0 | 1206 | mv88e6xxx_reg_unlock(chip); |
a1ab91f3 GR |
1207 | } |
1208 | ||
08f50061 VD |
1209 | static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, |
1210 | struct ethtool_eee *e) | |
68b8f60c | 1211 | { |
5480db69 VD |
1212 | /* Nothing to do on the port's MAC */ |
1213 | return 0; | |
11b3b45d GR |
1214 | } |
1215 | ||
08f50061 VD |
1216 | static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, |
1217 | struct ethtool_eee *e) | |
11b3b45d | 1218 | { |
5480db69 VD |
1219 | /* Nothing to do on the port's MAC */ |
1220 | return 0; | |
11b3b45d GR |
1221 | } |
1222 | ||
9dc8b13e | 1223 | /* Mask of the local ports allowed to receive frames from a given fabric port */ |
e5887a2a | 1224 | static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) |
facd95b2 | 1225 | { |
9dc8b13e VD |
1226 | struct dsa_switch *ds = chip->ds; |
1227 | struct dsa_switch_tree *dst = ds->dst; | |
e5887a2a | 1228 | struct net_device *br; |
9dc8b13e VD |
1229 | struct dsa_port *dp; |
1230 | bool found = false; | |
e5887a2a | 1231 | u16 pvlan; |
b7666efe | 1232 | |
ce5df689 VO |
1233 | /* dev is a physical switch */ |
1234 | if (dev <= dst->last_switch) { | |
1235 | list_for_each_entry(dp, &dst->ports, list) { | |
1236 | if (dp->ds->index == dev && dp->index == port) { | |
1237 | /* dp might be a DSA link or a user port, so it | |
1238 | * might or might not have a bridge_dev | |
1239 | * pointer. Use the "found" variable for both | |
1240 | * cases. | |
1241 | */ | |
1242 | br = dp->bridge_dev; | |
1243 | found = true; | |
1244 | break; | |
1245 | } | |
1246 | } | |
1247 | /* dev is a virtual bridge */ | |
1248 | } else { | |
1249 | list_for_each_entry(dp, &dst->ports, list) { | |
1250 | if (dp->bridge_num < 0) | |
1251 | continue; | |
1252 | ||
1253 | if (dp->bridge_num + 1 + dst->last_switch != dev) | |
1254 | continue; | |
1255 | ||
1256 | br = dp->bridge_dev; | |
9dc8b13e VD |
1257 | found = true; |
1258 | break; | |
1259 | } | |
1260 | } | |
e5887a2a | 1261 | |
ce5df689 | 1262 | /* Prevent frames from unknown switch or virtual bridge */ |
9dc8b13e | 1263 | if (!found) |
e5887a2a VD |
1264 | return 0; |
1265 | ||
1266 | /* Frames from DSA links and CPU ports can egress any local port */ | |
9dc8b13e | 1267 | if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) |
e5887a2a VD |
1268 | return mv88e6xxx_port_mask(chip); |
1269 | ||
e5887a2a VD |
1270 | pvlan = 0; |
1271 | ||
1272 | /* Frames from user ports can egress any local DSA links and CPU ports, | |
1273 | * as well as any local member of their bridge group. | |
1274 | */ | |
9dc8b13e VD |
1275 | list_for_each_entry(dp, &dst->ports, list) |
1276 | if (dp->ds == ds && | |
1277 | (dp->type == DSA_PORT_TYPE_CPU || | |
1278 | dp->type == DSA_PORT_TYPE_DSA || | |
1279 | (br && dp->bridge_dev == br))) | |
1280 | pvlan |= BIT(dp->index); | |
e5887a2a VD |
1281 | |
1282 | return pvlan; | |
1283 | } | |
1284 | ||
240ea3ef | 1285 | static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) |
e5887a2a VD |
1286 | { |
1287 | u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); | |
b7666efe VD |
1288 | |
1289 | /* prevent frames from going back out of the port they came in on */ | |
1290 | output_ports &= ~BIT(port); | |
facd95b2 | 1291 | |
5a7921f4 | 1292 | return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); |
facd95b2 GR |
1293 | } |
1294 | ||
f81ec90f VD |
1295 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
1296 | u8 state) | |
facd95b2 | 1297 | { |
04bed143 | 1298 | struct mv88e6xxx_chip *chip = ds->priv; |
553eb544 | 1299 | int err; |
facd95b2 | 1300 | |
c9acece0 | 1301 | mv88e6xxx_reg_lock(chip); |
f894c29c | 1302 | err = mv88e6xxx_port_set_state(chip, port, state); |
c9acece0 | 1303 | mv88e6xxx_reg_unlock(chip); |
553eb544 VD |
1304 | |
1305 | if (err) | |
774439e5 | 1306 | dev_err(ds->dev, "p%d: failed to update state\n", port); |
facd95b2 GR |
1307 | } |
1308 | ||
93e18d61 VD |
1309 | static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) |
1310 | { | |
1311 | int err; | |
1312 | ||
1313 | if (chip->info->ops->ieee_pri_map) { | |
1314 | err = chip->info->ops->ieee_pri_map(chip); | |
1315 | if (err) | |
1316 | return err; | |
1317 | } | |
1318 | ||
1319 | if (chip->info->ops->ip_pri_map) { | |
1320 | err = chip->info->ops->ip_pri_map(chip); | |
1321 | if (err) | |
1322 | return err; | |
1323 | } | |
1324 | ||
1325 | return 0; | |
1326 | } | |
1327 | ||
c7f047b6 VD |
1328 | static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) |
1329 | { | |
c5f51765 | 1330 | struct dsa_switch *ds = chip->ds; |
c7f047b6 VD |
1331 | int target, port; |
1332 | int err; | |
1333 | ||
1334 | if (!chip->info->global2_addr) | |
1335 | return 0; | |
1336 | ||
1337 | /* Initialize the routing port to the 32 possible target devices */ | |
1338 | for (target = 0; target < 32; target++) { | |
c5f51765 VD |
1339 | port = dsa_routing_port(ds, target); |
1340 | if (port == ds->num_ports) | |
1341 | port = 0x1f; | |
c7f047b6 VD |
1342 | |
1343 | err = mv88e6xxx_g2_device_mapping_write(chip, target, port); | |
1344 | if (err) | |
1345 | return err; | |
1346 | } | |
1347 | ||
02317e68 VD |
1348 | if (chip->info->ops->set_cascade_port) { |
1349 | port = MV88E6XXX_CASCADE_PORT_MULTIPLE; | |
1350 | err = chip->info->ops->set_cascade_port(chip, port); | |
1351 | if (err) | |
1352 | return err; | |
1353 | } | |
1354 | ||
23c98919 VD |
1355 | err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); |
1356 | if (err) | |
1357 | return err; | |
1358 | ||
c7f047b6 VD |
1359 | return 0; |
1360 | } | |
1361 | ||
b28f872d VD |
1362 | static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) |
1363 | { | |
1364 | /* Clear all trunk masks and mapping */ | |
1365 | if (chip->info->global2_addr) | |
1366 | return mv88e6xxx_g2_trunk_clear(chip); | |
1367 | ||
1368 | return 0; | |
1369 | } | |
1370 | ||
9e5baf9b VD |
1371 | static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) |
1372 | { | |
1373 | if (chip->info->ops->rmu_disable) | |
1374 | return chip->info->ops->rmu_disable(chip); | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
9e907d73 VD |
1379 | static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) |
1380 | { | |
1381 | if (chip->info->ops->pot_clear) | |
1382 | return chip->info->ops->pot_clear(chip); | |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | ||
51c901a7 VD |
1387 | static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) |
1388 | { | |
1389 | if (chip->info->ops->mgmt_rsvd2cpu) | |
1390 | return chip->info->ops->mgmt_rsvd2cpu(chip); | |
1391 | ||
1392 | return 0; | |
1393 | } | |
1394 | ||
a2ac29d2 VD |
1395 | static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) |
1396 | { | |
c3a7d4ad VD |
1397 | int err; |
1398 | ||
daefc943 VD |
1399 | err = mv88e6xxx_g1_atu_flush(chip, 0, true); |
1400 | if (err) | |
1401 | return err; | |
1402 | ||
49506a9b RV |
1403 | /* The chips that have a "learn2all" bit in Global1, ATU |
1404 | * Control are precisely those whose port registers have a | |
1405 | * Message Port bit in Port Control 1 and hence implement | |
1406 | * ->port_setup_message_port. | |
1407 | */ | |
1408 | if (chip->info->ops->port_setup_message_port) { | |
1409 | err = mv88e6xxx_g1_atu_set_learn2all(chip, true); | |
1410 | if (err) | |
1411 | return err; | |
1412 | } | |
c3a7d4ad | 1413 | |
a2ac29d2 VD |
1414 | return mv88e6xxx_g1_atu_set_age_time(chip, 300000); |
1415 | } | |
1416 | ||
cd8da8bb VD |
1417 | static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) |
1418 | { | |
1419 | int port; | |
1420 | int err; | |
1421 | ||
1422 | if (!chip->info->ops->irl_init_all) | |
1423 | return 0; | |
1424 | ||
1425 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { | |
1426 | /* Disable ingress rate limiting by resetting all per port | |
1427 | * ingress rate limit resources to their initial state. | |
1428 | */ | |
1429 | err = chip->info->ops->irl_init_all(chip, port); | |
1430 | if (err) | |
1431 | return err; | |
1432 | } | |
1433 | ||
1434 | return 0; | |
1435 | } | |
1436 | ||
04a69a17 VD |
1437 | static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) |
1438 | { | |
1439 | if (chip->info->ops->set_switch_mac) { | |
1440 | u8 addr[ETH_ALEN]; | |
1441 | ||
1442 | eth_random_addr(addr); | |
1443 | ||
1444 | return chip->info->ops->set_switch_mac(chip, addr); | |
1445 | } | |
1446 | ||
1447 | return 0; | |
1448 | } | |
1449 | ||
17a1594e VD |
1450 | static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) |
1451 | { | |
57e661aa TW |
1452 | struct dsa_switch_tree *dst = chip->ds->dst; |
1453 | struct dsa_switch *ds; | |
1454 | struct dsa_port *dp; | |
17a1594e VD |
1455 | u16 pvlan = 0; |
1456 | ||
1457 | if (!mv88e6xxx_has_pvt(chip)) | |
d14939be | 1458 | return 0; |
17a1594e VD |
1459 | |
1460 | /* Skip the local source device, which uses in-chip port VLAN */ | |
57e661aa | 1461 | if (dev != chip->ds->index) { |
aec5ac88 | 1462 | pvlan = mv88e6xxx_port_vlan(chip, dev, port); |
17a1594e | 1463 | |
57e661aa TW |
1464 | ds = dsa_switch_find(dst->index, dev); |
1465 | dp = ds ? dsa_to_port(ds, port) : NULL; | |
1466 | if (dp && dp->lag_dev) { | |
1467 | /* As the PVT is used to limit flooding of | |
1468 | * FORWARD frames, which use the LAG ID as the | |
1469 | * source port, we must translate dev/port to | |
1470 | * the special "LAG device" in the PVT, using | |
1471 | * the LAG ID as the port number. | |
1472 | */ | |
78e70dbc | 1473 | dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; |
57e661aa TW |
1474 | port = dsa_lag_id(dst, dp->lag_dev); |
1475 | } | |
1476 | } | |
1477 | ||
17a1594e VD |
1478 | return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); |
1479 | } | |
1480 | ||
81228996 VD |
1481 | static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) |
1482 | { | |
17a1594e VD |
1483 | int dev, port; |
1484 | int err; | |
1485 | ||
81228996 VD |
1486 | if (!mv88e6xxx_has_pvt(chip)) |
1487 | return 0; | |
1488 | ||
1489 | /* Clear 5 Bit Port for usage with Marvell Link Street devices: | |
1490 | * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. | |
1491 | */ | |
17a1594e VD |
1492 | err = mv88e6xxx_g2_misc_4_bit_port(chip); |
1493 | if (err) | |
1494 | return err; | |
1495 | ||
1496 | for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { | |
1497 | for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { | |
1498 | err = mv88e6xxx_pvt_map(chip, dev, port); | |
1499 | if (err) | |
1500 | return err; | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | return 0; | |
81228996 VD |
1505 | } |
1506 | ||
749efcb8 VD |
1507 | static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) |
1508 | { | |
1509 | struct mv88e6xxx_chip *chip = ds->priv; | |
1510 | int err; | |
1511 | ||
ffcec3f2 TW |
1512 | if (dsa_to_port(ds, port)->lag_dev) |
1513 | /* Hardware is incapable of fast-aging a LAG through a | |
1514 | * regular ATU move operation. Until we have something | |
1515 | * more fancy in place this is a no-op. | |
1516 | */ | |
1517 | return; | |
1518 | ||
c9acece0 | 1519 | mv88e6xxx_reg_lock(chip); |
e606ca36 | 1520 | err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); |
c9acece0 | 1521 | mv88e6xxx_reg_unlock(chip); |
749efcb8 VD |
1522 | |
1523 | if (err) | |
774439e5 | 1524 | dev_err(ds->dev, "p%d: failed to flush ATU\n", port); |
749efcb8 VD |
1525 | } |
1526 | ||
b486d7c9 VD |
1527 | static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) |
1528 | { | |
e545f865 | 1529 | if (!mv88e6xxx_max_vid(chip)) |
b486d7c9 VD |
1530 | return 0; |
1531 | ||
1532 | return mv88e6xxx_g1_vtu_flush(chip); | |
1533 | } | |
1534 | ||
34065c58 TW |
1535 | static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, |
1536 | struct mv88e6xxx_vtu_entry *entry) | |
f1394b78 | 1537 | { |
34065c58 TW |
1538 | int err; |
1539 | ||
f1394b78 VD |
1540 | if (!chip->info->ops->vtu_getnext) |
1541 | return -EOPNOTSUPP; | |
1542 | ||
34065c58 TW |
1543 | entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); |
1544 | entry->valid = false; | |
1545 | ||
1546 | err = chip->info->ops->vtu_getnext(chip, entry); | |
1547 | ||
1548 | if (entry->vid != vid) | |
1549 | entry->valid = false; | |
1550 | ||
1551 | return err; | |
f1394b78 VD |
1552 | } |
1553 | ||
d89ef4b8 TW |
1554 | static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, |
1555 | int (*cb)(struct mv88e6xxx_chip *chip, | |
1556 | const struct mv88e6xxx_vtu_entry *entry, | |
1557 | void *priv), | |
1558 | void *priv) | |
1559 | { | |
1560 | struct mv88e6xxx_vtu_entry entry = { | |
1561 | .vid = mv88e6xxx_max_vid(chip), | |
1562 | .valid = false, | |
1563 | }; | |
1564 | int err; | |
1565 | ||
1566 | if (!chip->info->ops->vtu_getnext) | |
1567 | return -EOPNOTSUPP; | |
1568 | ||
1569 | do { | |
1570 | err = chip->info->ops->vtu_getnext(chip, &entry); | |
1571 | if (err) | |
1572 | return err; | |
1573 | ||
1574 | if (!entry.valid) | |
1575 | break; | |
1576 | ||
1577 | err = cb(chip, &entry, priv); | |
1578 | if (err) | |
1579 | return err; | |
1580 | } while (entry.vid < mv88e6xxx_max_vid(chip)); | |
1581 | ||
1582 | return 0; | |
1583 | } | |
1584 | ||
0ad5daf6 VD |
1585 | static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
1586 | struct mv88e6xxx_vtu_entry *entry) | |
1587 | { | |
1588 | if (!chip->info->ops->vtu_loadpurge) | |
1589 | return -EOPNOTSUPP; | |
1590 | ||
1591 | return chip->info->ops->vtu_loadpurge(chip, entry); | |
1592 | } | |
1593 | ||
d89ef4b8 TW |
1594 | static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, |
1595 | const struct mv88e6xxx_vtu_entry *entry, | |
1596 | void *_fid_bitmap) | |
1597 | { | |
1598 | unsigned long *fid_bitmap = _fid_bitmap; | |
1599 | ||
1600 | set_bit(entry->fid, fid_bitmap); | |
1601 | return 0; | |
1602 | } | |
1603 | ||
90b6dbdf | 1604 | int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) |
3285f9e8 | 1605 | { |
2db9ce1f | 1606 | int i, err; |
90b6dbdf | 1607 | u16 fid; |
3285f9e8 VD |
1608 | |
1609 | bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); | |
1610 | ||
2db9ce1f | 1611 | /* Set every FID bit used by the (un)bridged ports */ |
370b4ffb | 1612 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
90b6dbdf | 1613 | err = mv88e6xxx_port_get_fid(chip, i, &fid); |
2db9ce1f VD |
1614 | if (err) |
1615 | return err; | |
1616 | ||
90b6dbdf | 1617 | set_bit(fid, fid_bitmap); |
2db9ce1f VD |
1618 | } |
1619 | ||
3285f9e8 | 1620 | /* Set every FID bit used by the VLAN entries */ |
d89ef4b8 | 1621 | return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); |
90b6dbdf AL |
1622 | } |
1623 | ||
1624 | static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) | |
1625 | { | |
1626 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); | |
1627 | int err; | |
1628 | ||
1629 | err = mv88e6xxx_fid_map(chip, fid_bitmap); | |
1630 | if (err) | |
1631 | return err; | |
1632 | ||
3285f9e8 VD |
1633 | /* The reset value 0x000 is used to indicate that multiple address |
1634 | * databases are not needed. Return the next positive available. | |
1635 | */ | |
1636 | *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); | |
fad09c73 | 1637 | if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) |
3285f9e8 VD |
1638 | return -ENOSPC; |
1639 | ||
1640 | /* Clear the database */ | |
daefc943 | 1641 | return mv88e6xxx_g1_atu_flush(chip, *fid, true); |
3285f9e8 VD |
1642 | } |
1643 | ||
da9c359e | 1644 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
b7a9e0da | 1645 | u16 vid) |
da9c359e | 1646 | { |
04bed143 | 1647 | struct mv88e6xxx_chip *chip = ds->priv; |
425d2d37 | 1648 | struct mv88e6xxx_vtu_entry vlan; |
da9c359e VD |
1649 | int i, err; |
1650 | ||
db06ae41 AL |
1651 | /* DSA and CPU ports have to be members of multiple vlans */ |
1652 | if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) | |
1653 | return 0; | |
1654 | ||
34065c58 | 1655 | err = mv88e6xxx_vtu_get(chip, vid, &vlan); |
b7a9e0da VO |
1656 | if (err) |
1657 | return err; | |
da9c359e | 1658 | |
b7a9e0da VO |
1659 | if (!vlan.valid) |
1660 | return 0; | |
da9c359e | 1661 | |
b7a9e0da VO |
1662 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
1663 | if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) | |
1664 | continue; | |
da9c359e | 1665 | |
b7a9e0da VO |
1666 | if (!dsa_to_port(ds, i)->slave) |
1667 | continue; | |
66e2809d | 1668 | |
b7a9e0da VO |
1669 | if (vlan.member[i] == |
1670 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) | |
1671 | continue; | |
da9c359e | 1672 | |
b7a9e0da VO |
1673 | if (dsa_to_port(ds, i)->bridge_dev == |
1674 | dsa_to_port(ds, port)->bridge_dev) | |
1675 | break; /* same bridge, check next VLAN */ | |
da9c359e | 1676 | |
b7a9e0da VO |
1677 | if (!dsa_to_port(ds, i)->bridge_dev) |
1678 | continue; | |
66e2809d | 1679 | |
b7a9e0da VO |
1680 | dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", |
1681 | port, vlan.vid, i, | |
1682 | netdev_name(dsa_to_port(ds, i)->bridge_dev)); | |
1683 | return -EOPNOTSUPP; | |
1684 | } | |
da9c359e | 1685 | |
7095a4c4 | 1686 | return 0; |
da9c359e VD |
1687 | } |
1688 | ||
8b6836d8 VO |
1689 | static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) |
1690 | { | |
1691 | struct dsa_port *dp = dsa_to_port(chip->ds, port); | |
1692 | struct mv88e6xxx_port *p = &chip->ports[port]; | |
5bded825 | 1693 | u16 pvid = MV88E6XXX_VID_STANDALONE; |
8b6836d8 | 1694 | bool drop_untagged = false; |
8b6836d8 VO |
1695 | int err; |
1696 | ||
5bded825 VO |
1697 | if (dp->bridge_dev) { |
1698 | if (br_vlan_enabled(dp->bridge_dev)) { | |
1699 | pvid = p->bridge_pvid.vid; | |
1700 | drop_untagged = !p->bridge_pvid.valid; | |
1701 | } else { | |
1702 | pvid = MV88E6XXX_VID_BRIDGED; | |
1703 | } | |
8b6836d8 VO |
1704 | } |
1705 | ||
1706 | err = mv88e6xxx_port_set_pvid(chip, port, pvid); | |
1707 | if (err) | |
1708 | return err; | |
1709 | ||
1710 | return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); | |
1711 | } | |
1712 | ||
f81ec90f | 1713 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
89153ed6 VO |
1714 | bool vlan_filtering, |
1715 | struct netlink_ext_ack *extack) | |
214cdb99 | 1716 | { |
04bed143 | 1717 | struct mv88e6xxx_chip *chip = ds->priv; |
81c6edb2 VD |
1718 | u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : |
1719 | MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; | |
0e7b9925 | 1720 | int err; |
214cdb99 | 1721 | |
bae33f2b VO |
1722 | if (!mv88e6xxx_max_vid(chip)) |
1723 | return -EOPNOTSUPP; | |
54d77b5b | 1724 | |
c9acece0 | 1725 | mv88e6xxx_reg_lock(chip); |
8b6836d8 | 1726 | |
385a0995 | 1727 | err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); |
8b6836d8 VO |
1728 | if (err) |
1729 | goto unlock; | |
1730 | ||
1731 | err = mv88e6xxx_port_commit_pvid(chip, port); | |
1732 | if (err) | |
1733 | goto unlock; | |
1734 | ||
1735 | unlock: | |
c9acece0 | 1736 | mv88e6xxx_reg_unlock(chip); |
214cdb99 | 1737 | |
0e7b9925 | 1738 | return err; |
214cdb99 VD |
1739 | } |
1740 | ||
57d32310 VD |
1741 | static int |
1742 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, | |
80e02360 | 1743 | const struct switchdev_obj_port_vlan *vlan) |
76e398a6 | 1744 | { |
04bed143 | 1745 | struct mv88e6xxx_chip *chip = ds->priv; |
da9c359e VD |
1746 | int err; |
1747 | ||
e545f865 | 1748 | if (!mv88e6xxx_max_vid(chip)) |
54d77b5b VD |
1749 | return -EOPNOTSUPP; |
1750 | ||
da9c359e VD |
1751 | /* If the requested port doesn't belong to the same bridge as the VLAN |
1752 | * members, do not support it (yet) and fallback to software VLAN. | |
1753 | */ | |
7095a4c4 | 1754 | mv88e6xxx_reg_lock(chip); |
b7a9e0da | 1755 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); |
7095a4c4 | 1756 | mv88e6xxx_reg_unlock(chip); |
da9c359e | 1757 | |
7095a4c4 | 1758 | return err; |
76e398a6 VD |
1759 | } |
1760 | ||
a4c93ae1 AL |
1761 | static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, |
1762 | const unsigned char *addr, u16 vid, | |
1763 | u8 state) | |
1764 | { | |
a4c93ae1 | 1765 | struct mv88e6xxx_atu_entry entry; |
5ef8d249 VD |
1766 | struct mv88e6xxx_vtu_entry vlan; |
1767 | u16 fid; | |
a4c93ae1 AL |
1768 | int err; |
1769 | ||
5bded825 VO |
1770 | /* Ports have two private address databases: one for when the port is |
1771 | * standalone and one for when the port is under a bridge and the | |
1772 | * 802.1Q mode is disabled. When the port is standalone, DSA wants its | |
1773 | * address database to remain 100% empty, so we never load an ATU entry | |
1774 | * into a standalone port's database. Therefore, translate the null | |
1775 | * VLAN ID into the port's database used for VLAN-unaware bridging. | |
1776 | */ | |
5ef8d249 | 1777 | if (vid == 0) { |
5bded825 | 1778 | fid = MV88E6XXX_FID_BRIDGED; |
5ef8d249 | 1779 | } else { |
34065c58 | 1780 | err = mv88e6xxx_vtu_get(chip, vid, &vlan); |
5ef8d249 VD |
1781 | if (err) |
1782 | return err; | |
1783 | ||
1784 | /* switchdev expects -EOPNOTSUPP to honor software VLANs */ | |
34065c58 | 1785 | if (!vlan.valid) |
5ef8d249 VD |
1786 | return -EOPNOTSUPP; |
1787 | ||
1788 | fid = vlan.fid; | |
1789 | } | |
a4c93ae1 | 1790 | |
d8291a95 | 1791 | entry.state = 0; |
a4c93ae1 AL |
1792 | ether_addr_copy(entry.mac, addr); |
1793 | eth_addr_dec(entry.mac); | |
1794 | ||
5ef8d249 | 1795 | err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); |
a4c93ae1 AL |
1796 | if (err) |
1797 | return err; | |
1798 | ||
1799 | /* Initialize a fresh ATU entry if it isn't found */ | |
d8291a95 | 1800 | if (!entry.state || !ether_addr_equal(entry.mac, addr)) { |
a4c93ae1 AL |
1801 | memset(&entry, 0, sizeof(entry)); |
1802 | ether_addr_copy(entry.mac, addr); | |
1803 | } | |
1804 | ||
1805 | /* Purge the ATU entry only if no port is using it anymore */ | |
d8291a95 | 1806 | if (!state) { |
a4c93ae1 AL |
1807 | entry.portvec &= ~BIT(port); |
1808 | if (!entry.portvec) | |
d8291a95 | 1809 | entry.state = 0; |
a4c93ae1 | 1810 | } else { |
f72f2fb8 DQ |
1811 | if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) |
1812 | entry.portvec = BIT(port); | |
1813 | else | |
1814 | entry.portvec |= BIT(port); | |
1815 | ||
a4c93ae1 AL |
1816 | entry.state = state; |
1817 | } | |
1818 | ||
5ef8d249 | 1819 | return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); |
a4c93ae1 AL |
1820 | } |
1821 | ||
da7dc875 VD |
1822 | static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, |
1823 | const struct mv88e6xxx_policy *policy) | |
1824 | { | |
1825 | enum mv88e6xxx_policy_mapping mapping = policy->mapping; | |
1826 | enum mv88e6xxx_policy_action action = policy->action; | |
1827 | const u8 *addr = policy->addr; | |
1828 | u16 vid = policy->vid; | |
1829 | u8 state; | |
1830 | int err; | |
1831 | int id; | |
1832 | ||
1833 | if (!chip->info->ops->port_set_policy) | |
1834 | return -EOPNOTSUPP; | |
1835 | ||
1836 | switch (mapping) { | |
1837 | case MV88E6XXX_POLICY_MAPPING_DA: | |
1838 | case MV88E6XXX_POLICY_MAPPING_SA: | |
1839 | if (action == MV88E6XXX_POLICY_ACTION_NORMAL) | |
1840 | state = 0; /* Dissociate the port and address */ | |
1841 | else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && | |
1842 | is_multicast_ether_addr(addr)) | |
1843 | state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; | |
1844 | else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && | |
1845 | is_unicast_ether_addr(addr)) | |
1846 | state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; | |
1847 | else | |
1848 | return -EOPNOTSUPP; | |
1849 | ||
1850 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, | |
1851 | state); | |
1852 | if (err) | |
1853 | return err; | |
1854 | break; | |
1855 | default: | |
1856 | return -EOPNOTSUPP; | |
1857 | } | |
1858 | ||
1859 | /* Skip the port's policy clearing if the mapping is still in use */ | |
1860 | if (action == MV88E6XXX_POLICY_ACTION_NORMAL) | |
1861 | idr_for_each_entry(&chip->policies, policy, id) | |
1862 | if (policy->port == port && | |
1863 | policy->mapping == mapping && | |
1864 | policy->action != action) | |
1865 | return 0; | |
1866 | ||
1867 | return chip->info->ops->port_set_policy(chip, port, mapping, action); | |
1868 | } | |
1869 | ||
1870 | static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, | |
1871 | struct ethtool_rx_flow_spec *fs) | |
1872 | { | |
1873 | struct ethhdr *mac_entry = &fs->h_u.ether_spec; | |
1874 | struct ethhdr *mac_mask = &fs->m_u.ether_spec; | |
1875 | enum mv88e6xxx_policy_mapping mapping; | |
1876 | enum mv88e6xxx_policy_action action; | |
1877 | struct mv88e6xxx_policy *policy; | |
1878 | u16 vid = 0; | |
1879 | u8 *addr; | |
1880 | int err; | |
1881 | int id; | |
1882 | ||
1883 | if (fs->location != RX_CLS_LOC_ANY) | |
1884 | return -EINVAL; | |
1885 | ||
1886 | if (fs->ring_cookie == RX_CLS_FLOW_DISC) | |
1887 | action = MV88E6XXX_POLICY_ACTION_DISCARD; | |
1888 | else | |
1889 | return -EOPNOTSUPP; | |
1890 | ||
1891 | switch (fs->flow_type & ~FLOW_EXT) { | |
1892 | case ETHER_FLOW: | |
1893 | if (!is_zero_ether_addr(mac_mask->h_dest) && | |
1894 | is_zero_ether_addr(mac_mask->h_source)) { | |
1895 | mapping = MV88E6XXX_POLICY_MAPPING_DA; | |
1896 | addr = mac_entry->h_dest; | |
1897 | } else if (is_zero_ether_addr(mac_mask->h_dest) && | |
1898 | !is_zero_ether_addr(mac_mask->h_source)) { | |
1899 | mapping = MV88E6XXX_POLICY_MAPPING_SA; | |
1900 | addr = mac_entry->h_source; | |
1901 | } else { | |
1902 | /* Cannot support DA and SA mapping in the same rule */ | |
1903 | return -EOPNOTSUPP; | |
1904 | } | |
1905 | break; | |
1906 | default: | |
1907 | return -EOPNOTSUPP; | |
1908 | } | |
1909 | ||
1910 | if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { | |
04844280 | 1911 | if (fs->m_ext.vlan_tci != htons(0xffff)) |
da7dc875 VD |
1912 | return -EOPNOTSUPP; |
1913 | vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; | |
1914 | } | |
1915 | ||
1916 | idr_for_each_entry(&chip->policies, policy, id) { | |
1917 | if (policy->port == port && policy->mapping == mapping && | |
1918 | policy->action == action && policy->vid == vid && | |
1919 | ether_addr_equal(policy->addr, addr)) | |
1920 | return -EEXIST; | |
1921 | } | |
1922 | ||
1923 | policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); | |
1924 | if (!policy) | |
1925 | return -ENOMEM; | |
1926 | ||
1927 | fs->location = 0; | |
1928 | err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, | |
1929 | GFP_KERNEL); | |
1930 | if (err) { | |
1931 | devm_kfree(chip->dev, policy); | |
1932 | return err; | |
1933 | } | |
1934 | ||
1935 | memcpy(&policy->fs, fs, sizeof(*fs)); | |
1936 | ether_addr_copy(policy->addr, addr); | |
1937 | policy->mapping = mapping; | |
1938 | policy->action = action; | |
1939 | policy->port = port; | |
1940 | policy->vid = vid; | |
1941 | ||
1942 | err = mv88e6xxx_policy_apply(chip, port, policy); | |
1943 | if (err) { | |
1944 | idr_remove(&chip->policies, fs->location); | |
1945 | devm_kfree(chip->dev, policy); | |
1946 | return err; | |
1947 | } | |
1948 | ||
1949 | return 0; | |
1950 | } | |
1951 | ||
1952 | static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, | |
1953 | struct ethtool_rxnfc *rxnfc, u32 *rule_locs) | |
1954 | { | |
1955 | struct ethtool_rx_flow_spec *fs = &rxnfc->fs; | |
1956 | struct mv88e6xxx_chip *chip = ds->priv; | |
1957 | struct mv88e6xxx_policy *policy; | |
1958 | int err; | |
1959 | int id; | |
1960 | ||
1961 | mv88e6xxx_reg_lock(chip); | |
1962 | ||
1963 | switch (rxnfc->cmd) { | |
1964 | case ETHTOOL_GRXCLSRLCNT: | |
1965 | rxnfc->data = 0; | |
1966 | rxnfc->data |= RX_CLS_LOC_SPECIAL; | |
1967 | rxnfc->rule_cnt = 0; | |
1968 | idr_for_each_entry(&chip->policies, policy, id) | |
1969 | if (policy->port == port) | |
1970 | rxnfc->rule_cnt++; | |
1971 | err = 0; | |
1972 | break; | |
1973 | case ETHTOOL_GRXCLSRULE: | |
1974 | err = -ENOENT; | |
1975 | policy = idr_find(&chip->policies, fs->location); | |
1976 | if (policy) { | |
1977 | memcpy(fs, &policy->fs, sizeof(*fs)); | |
1978 | err = 0; | |
1979 | } | |
1980 | break; | |
1981 | case ETHTOOL_GRXCLSRLALL: | |
1982 | rxnfc->data = 0; | |
1983 | rxnfc->rule_cnt = 0; | |
1984 | idr_for_each_entry(&chip->policies, policy, id) | |
1985 | if (policy->port == port) | |
1986 | rule_locs[rxnfc->rule_cnt++] = id; | |
1987 | err = 0; | |
1988 | break; | |
1989 | default: | |
1990 | err = -EOPNOTSUPP; | |
1991 | break; | |
1992 | } | |
1993 | ||
1994 | mv88e6xxx_reg_unlock(chip); | |
1995 | ||
1996 | return err; | |
1997 | } | |
1998 | ||
1999 | static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, | |
2000 | struct ethtool_rxnfc *rxnfc) | |
2001 | { | |
2002 | struct ethtool_rx_flow_spec *fs = &rxnfc->fs; | |
2003 | struct mv88e6xxx_chip *chip = ds->priv; | |
2004 | struct mv88e6xxx_policy *policy; | |
2005 | int err; | |
2006 | ||
2007 | mv88e6xxx_reg_lock(chip); | |
2008 | ||
2009 | switch (rxnfc->cmd) { | |
2010 | case ETHTOOL_SRXCLSRLINS: | |
2011 | err = mv88e6xxx_policy_insert(chip, port, fs); | |
2012 | break; | |
2013 | case ETHTOOL_SRXCLSRLDEL: | |
2014 | err = -ENOENT; | |
2015 | policy = idr_remove(&chip->policies, fs->location); | |
2016 | if (policy) { | |
2017 | policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; | |
2018 | err = mv88e6xxx_policy_apply(chip, port, policy); | |
2019 | devm_kfree(chip->dev, policy); | |
2020 | } | |
2021 | break; | |
2022 | default: | |
2023 | err = -EOPNOTSUPP; | |
2024 | break; | |
2025 | } | |
2026 | ||
2027 | mv88e6xxx_reg_unlock(chip); | |
2028 | ||
2029 | return err; | |
2030 | } | |
2031 | ||
87fa886e AL |
2032 | static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, |
2033 | u16 vid) | |
2034 | { | |
87fa886e | 2035 | u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; |
0806dd46 TW |
2036 | u8 broadcast[ETH_ALEN]; |
2037 | ||
2038 | eth_broadcast_addr(broadcast); | |
87fa886e AL |
2039 | |
2040 | return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); | |
2041 | } | |
2042 | ||
2043 | static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) | |
2044 | { | |
2045 | int port; | |
2046 | int err; | |
2047 | ||
2048 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { | |
8d1d8298 TW |
2049 | struct dsa_port *dp = dsa_to_port(chip->ds, port); |
2050 | struct net_device *brport; | |
2051 | ||
2052 | if (dsa_is_unused_port(chip->ds, port)) | |
2053 | continue; | |
2054 | ||
2055 | brport = dsa_port_to_bridge_port(dp); | |
2056 | if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) | |
2057 | /* Skip bridged user ports where broadcast | |
2058 | * flooding is disabled. | |
2059 | */ | |
2060 | continue; | |
2061 | ||
87fa886e AL |
2062 | err = mv88e6xxx_port_add_broadcast(chip, port, vid); |
2063 | if (err) | |
2064 | return err; | |
2065 | } | |
2066 | ||
2067 | return 0; | |
2068 | } | |
2069 | ||
8d1d8298 TW |
2070 | struct mv88e6xxx_port_broadcast_sync_ctx { |
2071 | int port; | |
2072 | bool flood; | |
2073 | }; | |
2074 | ||
2075 | static int | |
2076 | mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, | |
2077 | const struct mv88e6xxx_vtu_entry *vlan, | |
2078 | void *_ctx) | |
2079 | { | |
2080 | struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; | |
2081 | u8 broadcast[ETH_ALEN]; | |
2082 | u8 state; | |
2083 | ||
2084 | if (ctx->flood) | |
2085 | state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; | |
2086 | else | |
2087 | state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; | |
2088 | ||
2089 | eth_broadcast_addr(broadcast); | |
2090 | ||
2091 | return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, | |
2092 | vlan->vid, state); | |
2093 | } | |
2094 | ||
2095 | static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, | |
2096 | bool flood) | |
2097 | { | |
2098 | struct mv88e6xxx_port_broadcast_sync_ctx ctx = { | |
2099 | .port = port, | |
2100 | .flood = flood, | |
2101 | }; | |
2102 | struct mv88e6xxx_vtu_entry vid0 = { | |
2103 | .vid = 0, | |
2104 | }; | |
2105 | int err; | |
2106 | ||
2107 | /* Update the port's private database... */ | |
2108 | err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); | |
2109 | if (err) | |
2110 | return err; | |
2111 | ||
2112 | /* ...and the database for all VLANs. */ | |
2113 | return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, | |
2114 | &ctx); | |
2115 | } | |
2116 | ||
b1ac6fb4 | 2117 | static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, |
933b4425 | 2118 | u16 vid, u8 member, bool warn) |
0d3b33e6 | 2119 | { |
b1ac6fb4 | 2120 | const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
b4e47c0f | 2121 | struct mv88e6xxx_vtu_entry vlan; |
b1ac6fb4 | 2122 | int i, err; |
0d3b33e6 | 2123 | |
34065c58 | 2124 | err = mv88e6xxx_vtu_get(chip, vid, &vlan); |
87fa886e AL |
2125 | if (err) |
2126 | return err; | |
2127 | ||
34065c58 | 2128 | if (!vlan.valid) { |
b1ac6fb4 VD |
2129 | memset(&vlan, 0, sizeof(vlan)); |
2130 | ||
2131 | err = mv88e6xxx_atu_new(chip, &vlan.fid); | |
2132 | if (err) | |
2133 | return err; | |
2134 | ||
2135 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) | |
2136 | if (i == port) | |
2137 | vlan.member[i] = member; | |
2138 | else | |
2139 | vlan.member[i] = non_member; | |
2140 | ||
2141 | vlan.vid = vid; | |
2142 | vlan.valid = true; | |
2143 | ||
2144 | err = mv88e6xxx_vtu_loadpurge(chip, &vlan); | |
2145 | if (err) | |
2146 | return err; | |
2147 | ||
2148 | err = mv88e6xxx_broadcast_setup(chip, vlan.vid); | |
2149 | if (err) | |
2150 | return err; | |
2151 | } else if (vlan.member[port] != member) { | |
2152 | vlan.member[port] = member; | |
2153 | ||
2154 | err = mv88e6xxx_vtu_loadpurge(chip, &vlan); | |
2155 | if (err) | |
2156 | return err; | |
933b4425 | 2157 | } else if (warn) { |
b1ac6fb4 VD |
2158 | dev_info(chip->dev, "p%d: already a member of VLAN %d\n", |
2159 | port, vid); | |
2160 | } | |
2161 | ||
2162 | return 0; | |
76e398a6 VD |
2163 | } |
2164 | ||
1958d581 | 2165 | static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
31046a5f VO |
2166 | const struct switchdev_obj_port_vlan *vlan, |
2167 | struct netlink_ext_ack *extack) | |
76e398a6 | 2168 | { |
04bed143 | 2169 | struct mv88e6xxx_chip *chip = ds->priv; |
76e398a6 VD |
2170 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; |
2171 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; | |
8b6836d8 | 2172 | struct mv88e6xxx_port *p = &chip->ports[port]; |
933b4425 | 2173 | bool warn; |
c91498e1 | 2174 | u8 member; |
1958d581 | 2175 | int err; |
76e398a6 | 2176 | |
b8b79c41 EG |
2177 | if (!vlan->vid) |
2178 | return 0; | |
2179 | ||
1958d581 VO |
2180 | err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); |
2181 | if (err) | |
2182 | return err; | |
54d77b5b | 2183 | |
c91498e1 | 2184 | if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) |
7ec60d6e | 2185 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; |
c91498e1 | 2186 | else if (untagged) |
7ec60d6e | 2187 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; |
c91498e1 | 2188 | else |
7ec60d6e | 2189 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; |
c91498e1 | 2190 | |
933b4425 RK |
2191 | /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port |
2192 | * and then the CPU port. Do not warn for duplicates for the CPU port. | |
2193 | */ | |
2194 | warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); | |
2195 | ||
c9acece0 | 2196 | mv88e6xxx_reg_lock(chip); |
76e398a6 | 2197 | |
1958d581 VO |
2198 | err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); |
2199 | if (err) { | |
b7a9e0da VO |
2200 | dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, |
2201 | vlan->vid, untagged ? 'u' : 't'); | |
1958d581 VO |
2202 | goto out; |
2203 | } | |
76e398a6 | 2204 | |
1958d581 | 2205 | if (pvid) { |
8b6836d8 VO |
2206 | p->bridge_pvid.vid = vlan->vid; |
2207 | p->bridge_pvid.valid = true; | |
2208 | ||
2209 | err = mv88e6xxx_port_commit_pvid(chip, port); | |
2210 | if (err) | |
2211 | goto out; | |
2212 | } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { | |
2213 | /* The old pvid was reinstalled as a non-pvid VLAN */ | |
2214 | p->bridge_pvid.valid = false; | |
2215 | ||
2216 | err = mv88e6xxx_port_commit_pvid(chip, port); | |
2217 | if (err) | |
1958d581 | 2218 | goto out; |
1958d581 | 2219 | } |
8b6836d8 | 2220 | |
1958d581 | 2221 | out: |
c9acece0 | 2222 | mv88e6xxx_reg_unlock(chip); |
1958d581 VO |
2223 | |
2224 | return err; | |
0d3b33e6 VD |
2225 | } |
2226 | ||
52109892 VD |
2227 | static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, |
2228 | int port, u16 vid) | |
7dad08d7 | 2229 | { |
b4e47c0f | 2230 | struct mv88e6xxx_vtu_entry vlan; |
7dad08d7 VD |
2231 | int i, err; |
2232 | ||
52109892 | 2233 | if (!vid) |
c92c7413 | 2234 | return 0; |
52109892 | 2235 | |
34065c58 | 2236 | err = mv88e6xxx_vtu_get(chip, vid, &vlan); |
7dad08d7 | 2237 | if (err) |
76e398a6 | 2238 | return err; |
7dad08d7 | 2239 | |
52109892 VD |
2240 | /* If the VLAN doesn't exist in hardware or the port isn't a member, |
2241 | * tell switchdev that this VLAN is likely handled in software. | |
2242 | */ | |
34065c58 | 2243 | if (!vlan.valid || |
52109892 | 2244 | vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
3c06f08b | 2245 | return -EOPNOTSUPP; |
7dad08d7 | 2246 | |
7ec60d6e | 2247 | vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
7dad08d7 VD |
2248 | |
2249 | /* keep the VLAN unless all ports are excluded */ | |
f02bdffc | 2250 | vlan.valid = false; |
370b4ffb | 2251 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
7ec60d6e VD |
2252 | if (vlan.member[i] != |
2253 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { | |
f02bdffc | 2254 | vlan.valid = true; |
7dad08d7 VD |
2255 | break; |
2256 | } | |
2257 | } | |
2258 | ||
0ad5daf6 | 2259 | err = mv88e6xxx_vtu_loadpurge(chip, &vlan); |
76e398a6 VD |
2260 | if (err) |
2261 | return err; | |
2262 | ||
e606ca36 | 2263 | return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); |
76e398a6 VD |
2264 | } |
2265 | ||
f81ec90f VD |
2266 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
2267 | const struct switchdev_obj_port_vlan *vlan) | |
76e398a6 | 2268 | { |
04bed143 | 2269 | struct mv88e6xxx_chip *chip = ds->priv; |
8b6836d8 | 2270 | struct mv88e6xxx_port *p = &chip->ports[port]; |
76e398a6 | 2271 | int err = 0; |
b7a9e0da | 2272 | u16 pvid; |
76e398a6 | 2273 | |
e545f865 | 2274 | if (!mv88e6xxx_max_vid(chip)) |
54d77b5b VD |
2275 | return -EOPNOTSUPP; |
2276 | ||
c9acece0 | 2277 | mv88e6xxx_reg_lock(chip); |
76e398a6 | 2278 | |
77064f37 | 2279 | err = mv88e6xxx_port_get_pvid(chip, port, &pvid); |
7dad08d7 VD |
2280 | if (err) |
2281 | goto unlock; | |
2282 | ||
b7a9e0da VO |
2283 | err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); |
2284 | if (err) | |
2285 | goto unlock; | |
2286 | ||
2287 | if (vlan->vid == pvid) { | |
8b6836d8 VO |
2288 | p->bridge_pvid.valid = false; |
2289 | ||
2290 | err = mv88e6xxx_port_commit_pvid(chip, port); | |
76e398a6 VD |
2291 | if (err) |
2292 | goto unlock; | |
76e398a6 VD |
2293 | } |
2294 | ||
7dad08d7 | 2295 | unlock: |
c9acece0 | 2296 | mv88e6xxx_reg_unlock(chip); |
7dad08d7 VD |
2297 | |
2298 | return err; | |
2299 | } | |
2300 | ||
1b6dd556 AS |
2301 | static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
2302 | const unsigned char *addr, u16 vid) | |
87820510 | 2303 | { |
04bed143 | 2304 | struct mv88e6xxx_chip *chip = ds->priv; |
1b6dd556 | 2305 | int err; |
87820510 | 2306 | |
c9acece0 | 2307 | mv88e6xxx_reg_lock(chip); |
1b6dd556 AS |
2308 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, |
2309 | MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); | |
c9acece0 | 2310 | mv88e6xxx_reg_unlock(chip); |
1b6dd556 AS |
2311 | |
2312 | return err; | |
87820510 VD |
2313 | } |
2314 | ||
f81ec90f | 2315 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
6c2c1dcb | 2316 | const unsigned char *addr, u16 vid) |
87820510 | 2317 | { |
04bed143 | 2318 | struct mv88e6xxx_chip *chip = ds->priv; |
83dabd1f | 2319 | int err; |
87820510 | 2320 | |
c9acece0 | 2321 | mv88e6xxx_reg_lock(chip); |
d8291a95 | 2322 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); |
c9acece0 | 2323 | mv88e6xxx_reg_unlock(chip); |
87820510 | 2324 | |
83dabd1f | 2325 | return err; |
87820510 VD |
2326 | } |
2327 | ||
83dabd1f VD |
2328 | static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, |
2329 | u16 fid, u16 vid, int port, | |
2bedde1a | 2330 | dsa_fdb_dump_cb_t *cb, void *data) |
74b6ba0d | 2331 | { |
dabc1a96 | 2332 | struct mv88e6xxx_atu_entry addr; |
2bedde1a | 2333 | bool is_static; |
74b6ba0d VD |
2334 | int err; |
2335 | ||
d8291a95 | 2336 | addr.state = 0; |
dabc1a96 | 2337 | eth_broadcast_addr(addr.mac); |
74b6ba0d VD |
2338 | |
2339 | do { | |
dabc1a96 | 2340 | err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); |
74b6ba0d | 2341 | if (err) |
83dabd1f | 2342 | return err; |
74b6ba0d | 2343 | |
d8291a95 | 2344 | if (!addr.state) |
74b6ba0d VD |
2345 | break; |
2346 | ||
01bd96c8 | 2347 | if (addr.trunk || (addr.portvec & BIT(port)) == 0) |
83dabd1f VD |
2348 | continue; |
2349 | ||
2bedde1a AS |
2350 | if (!is_unicast_ether_addr(addr.mac)) |
2351 | continue; | |
83dabd1f | 2352 | |
2bedde1a AS |
2353 | is_static = (addr.state == |
2354 | MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); | |
2355 | err = cb(addr.mac, vid, is_static, data); | |
83dabd1f VD |
2356 | if (err) |
2357 | return err; | |
74b6ba0d VD |
2358 | } while (!is_broadcast_ether_addr(addr.mac)); |
2359 | ||
2360 | return err; | |
2361 | } | |
2362 | ||
d89ef4b8 TW |
2363 | struct mv88e6xxx_port_db_dump_vlan_ctx { |
2364 | int port; | |
2365 | dsa_fdb_dump_cb_t *cb; | |
2366 | void *data; | |
2367 | }; | |
2368 | ||
2369 | static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, | |
2370 | const struct mv88e6xxx_vtu_entry *entry, | |
2371 | void *_data) | |
2372 | { | |
2373 | struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; | |
2374 | ||
2375 | return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, | |
2376 | ctx->port, ctx->cb, ctx->data); | |
2377 | } | |
2378 | ||
83dabd1f | 2379 | static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, |
2bedde1a | 2380 | dsa_fdb_dump_cb_t *cb, void *data) |
f33475bd | 2381 | { |
d89ef4b8 TW |
2382 | struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { |
2383 | .port = port, | |
2384 | .cb = cb, | |
2385 | .data = data, | |
2386 | }; | |
2db9ce1f | 2387 | u16 fid; |
f33475bd VD |
2388 | int err; |
2389 | ||
2db9ce1f | 2390 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
b4e48c50 | 2391 | err = mv88e6xxx_port_get_fid(chip, port, &fid); |
2db9ce1f | 2392 | if (err) |
83dabd1f | 2393 | return err; |
2db9ce1f | 2394 | |
2bedde1a | 2395 | err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); |
2db9ce1f | 2396 | if (err) |
83dabd1f | 2397 | return err; |
2db9ce1f | 2398 | |
d89ef4b8 | 2399 | return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); |
83dabd1f VD |
2400 | } |
2401 | ||
2402 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, | |
2bedde1a | 2403 | dsa_fdb_dump_cb_t *cb, void *data) |
83dabd1f | 2404 | { |
04bed143 | 2405 | struct mv88e6xxx_chip *chip = ds->priv; |
fcf15367 VD |
2406 | int err; |
2407 | ||
c9acece0 | 2408 | mv88e6xxx_reg_lock(chip); |
fcf15367 | 2409 | err = mv88e6xxx_port_db_dump(chip, port, cb, data); |
c9acece0 | 2410 | mv88e6xxx_reg_unlock(chip); |
83dabd1f | 2411 | |
fcf15367 | 2412 | return err; |
f33475bd VD |
2413 | } |
2414 | ||
240ea3ef VD |
2415 | static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, |
2416 | struct net_device *br) | |
e79a8bcb | 2417 | { |
ef2025ec VD |
2418 | struct dsa_switch *ds = chip->ds; |
2419 | struct dsa_switch_tree *dst = ds->dst; | |
2420 | struct dsa_port *dp; | |
240ea3ef | 2421 | int err; |
466dfa07 | 2422 | |
ef2025ec VD |
2423 | list_for_each_entry(dp, &dst->ports, list) { |
2424 | if (dp->bridge_dev == br) { | |
2425 | if (dp->ds == ds) { | |
2426 | /* This is a local bridge group member, | |
2427 | * remap its Port VLAN Map. | |
2428 | */ | |
2429 | err = mv88e6xxx_port_vlan_map(chip, dp->index); | |
2430 | if (err) | |
2431 | return err; | |
2432 | } else { | |
2433 | /* This is an external bridge group member, | |
2434 | * remap its cross-chip Port VLAN Table entry. | |
2435 | */ | |
2436 | err = mv88e6xxx_pvt_map(chip, dp->ds->index, | |
2437 | dp->index); | |
e96a6e02 VD |
2438 | if (err) |
2439 | return err; | |
2440 | } | |
2441 | } | |
2442 | } | |
2443 | ||
240ea3ef VD |
2444 | return 0; |
2445 | } | |
2446 | ||
2447 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, | |
2448 | struct net_device *br) | |
2449 | { | |
2450 | struct mv88e6xxx_chip *chip = ds->priv; | |
2451 | int err; | |
2452 | ||
c9acece0 | 2453 | mv88e6xxx_reg_lock(chip); |
5bded825 | 2454 | |
240ea3ef | 2455 | err = mv88e6xxx_bridge_map(chip, br); |
5bded825 VO |
2456 | if (err) |
2457 | goto unlock; | |
2458 | ||
2459 | err = mv88e6xxx_port_commit_pvid(chip, port); | |
2460 | if (err) | |
2461 | goto unlock; | |
2462 | ||
2463 | unlock: | |
c9acece0 | 2464 | mv88e6xxx_reg_unlock(chip); |
a6692754 | 2465 | |
466dfa07 | 2466 | return err; |
e79a8bcb VD |
2467 | } |
2468 | ||
f123f2fb VD |
2469 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, |
2470 | struct net_device *br) | |
66d9cd0f | 2471 | { |
04bed143 | 2472 | struct mv88e6xxx_chip *chip = ds->priv; |
5bded825 | 2473 | int err; |
466dfa07 | 2474 | |
c9acece0 | 2475 | mv88e6xxx_reg_lock(chip); |
5bded825 | 2476 | |
240ea3ef VD |
2477 | if (mv88e6xxx_bridge_map(chip, br) || |
2478 | mv88e6xxx_port_vlan_map(chip, port)) | |
2479 | dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); | |
5bded825 VO |
2480 | |
2481 | err = mv88e6xxx_port_commit_pvid(chip, port); | |
2482 | if (err) | |
2483 | dev_err(ds->dev, | |
2484 | "port %d failed to restore standalone pvid: %pe\n", | |
2485 | port, ERR_PTR(err)); | |
2486 | ||
c9acece0 | 2487 | mv88e6xxx_reg_unlock(chip); |
66d9cd0f VD |
2488 | } |
2489 | ||
f66a6a69 VO |
2490 | static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, |
2491 | int tree_index, int sw_index, | |
aec5ac88 VD |
2492 | int port, struct net_device *br) |
2493 | { | |
2494 | struct mv88e6xxx_chip *chip = ds->priv; | |
2495 | int err; | |
2496 | ||
f66a6a69 VO |
2497 | if (tree_index != ds->dst->index) |
2498 | return 0; | |
2499 | ||
c9acece0 | 2500 | mv88e6xxx_reg_lock(chip); |
f66a6a69 | 2501 | err = mv88e6xxx_pvt_map(chip, sw_index, port); |
c9acece0 | 2502 | mv88e6xxx_reg_unlock(chip); |
aec5ac88 VD |
2503 | |
2504 | return err; | |
2505 | } | |
2506 | ||
f66a6a69 VO |
2507 | static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, |
2508 | int tree_index, int sw_index, | |
aec5ac88 VD |
2509 | int port, struct net_device *br) |
2510 | { | |
2511 | struct mv88e6xxx_chip *chip = ds->priv; | |
2512 | ||
f66a6a69 VO |
2513 | if (tree_index != ds->dst->index) |
2514 | return; | |
2515 | ||
c9acece0 | 2516 | mv88e6xxx_reg_lock(chip); |
f66a6a69 | 2517 | if (mv88e6xxx_pvt_map(chip, sw_index, port)) |
aec5ac88 | 2518 | dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); |
c9acece0 | 2519 | mv88e6xxx_reg_unlock(chip); |
aec5ac88 VD |
2520 | } |
2521 | ||
ce5df689 VO |
2522 | /* Treat the software bridge as a virtual single-port switch behind the |
2523 | * CPU and map in the PVT. First dst->last_switch elements are taken by | |
2524 | * physical switches, so start from beyond that range. | |
2525 | */ | |
2526 | static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, | |
2527 | int bridge_num) | |
2528 | { | |
2529 | u8 dev = bridge_num + ds->dst->last_switch + 1; | |
2530 | struct mv88e6xxx_chip *chip = ds->priv; | |
2531 | int err; | |
2532 | ||
2533 | mv88e6xxx_reg_lock(chip); | |
2534 | err = mv88e6xxx_pvt_map(chip, dev, 0); | |
2535 | mv88e6xxx_reg_unlock(chip); | |
2536 | ||
2537 | return err; | |
2538 | } | |
2539 | ||
2540 | static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port, | |
2541 | struct net_device *br, | |
2542 | int bridge_num) | |
2543 | { | |
2544 | return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); | |
2545 | } | |
2546 | ||
2547 | static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port, | |
2548 | struct net_device *br, | |
2549 | int bridge_num) | |
2550 | { | |
2551 | int err; | |
2552 | ||
2553 | err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); | |
2554 | if (err) { | |
2555 | dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n", | |
2556 | ERR_PTR(err)); | |
2557 | } | |
2558 | } | |
2559 | ||
17e708ba VD |
2560 | static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) |
2561 | { | |
2562 | if (chip->info->ops->reset) | |
2563 | return chip->info->ops->reset(chip); | |
2564 | ||
2565 | return 0; | |
2566 | } | |
2567 | ||
309eca6d VD |
2568 | static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) |
2569 | { | |
2570 | struct gpio_desc *gpiod = chip->reset; | |
2571 | ||
2572 | /* If there is a GPIO connected to the reset pin, toggle it */ | |
2573 | if (gpiod) { | |
2574 | gpiod_set_value_cansleep(gpiod, 1); | |
2575 | usleep_range(10000, 20000); | |
2576 | gpiod_set_value_cansleep(gpiod, 0); | |
2577 | usleep_range(10000, 20000); | |
a3dcb3e7 AL |
2578 | |
2579 | mv88e6xxx_g1_wait_eeprom_done(chip); | |
309eca6d VD |
2580 | } |
2581 | } | |
2582 | ||
4ac4b5a6 | 2583 | static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) |
552238b5 | 2584 | { |
4ac4b5a6 | 2585 | int i, err; |
552238b5 | 2586 | |
4ac4b5a6 | 2587 | /* Set all ports to the Disabled state */ |
370b4ffb | 2588 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
f894c29c | 2589 | err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); |
0e7b9925 AL |
2590 | if (err) |
2591 | return err; | |
552238b5 VD |
2592 | } |
2593 | ||
4ac4b5a6 VD |
2594 | /* Wait for transmit queues to drain, |
2595 | * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. | |
2596 | */ | |
552238b5 VD |
2597 | usleep_range(2000, 4000); |
2598 | ||
4ac4b5a6 VD |
2599 | return 0; |
2600 | } | |
2601 | ||
2602 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) | |
2603 | { | |
4ac4b5a6 VD |
2604 | int err; |
2605 | ||
2606 | err = mv88e6xxx_disable_ports(chip); | |
2607 | if (err) | |
2608 | return err; | |
2609 | ||
309eca6d | 2610 | mv88e6xxx_hardware_reset(chip); |
552238b5 | 2611 | |
17e708ba | 2612 | return mv88e6xxx_software_reset(chip); |
552238b5 VD |
2613 | } |
2614 | ||
4314557c | 2615 | static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, |
31bef4e9 VD |
2616 | enum mv88e6xxx_frame_mode frame, |
2617 | enum mv88e6xxx_egress_mode egress, u16 etype) | |
56995cbc AL |
2618 | { |
2619 | int err; | |
2620 | ||
4314557c VD |
2621 | if (!chip->info->ops->port_set_frame_mode) |
2622 | return -EOPNOTSUPP; | |
2623 | ||
2624 | err = mv88e6xxx_port_set_egress_mode(chip, port, egress); | |
56995cbc AL |
2625 | if (err) |
2626 | return err; | |
2627 | ||
4314557c VD |
2628 | err = chip->info->ops->port_set_frame_mode(chip, port, frame); |
2629 | if (err) | |
2630 | return err; | |
2631 | ||
2632 | if (chip->info->ops->port_set_ether_type) | |
2633 | return chip->info->ops->port_set_ether_type(chip, port, etype); | |
2634 | ||
2635 | return 0; | |
56995cbc AL |
2636 | } |
2637 | ||
4314557c | 2638 | static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) |
56995cbc | 2639 | { |
4314557c | 2640 | return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, |
31bef4e9 | 2641 | MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
b8109594 | 2642 | MV88E6XXX_PORT_ETH_TYPE_DEFAULT); |
4314557c | 2643 | } |
56995cbc | 2644 | |
4314557c VD |
2645 | static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) |
2646 | { | |
2647 | return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, | |
31bef4e9 | 2648 | MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
b8109594 | 2649 | MV88E6XXX_PORT_ETH_TYPE_DEFAULT); |
4314557c | 2650 | } |
56995cbc | 2651 | |
4314557c VD |
2652 | static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) |
2653 | { | |
2654 | return mv88e6xxx_set_port_mode(chip, port, | |
2655 | MV88E6XXX_FRAME_MODE_ETHERTYPE, | |
31bef4e9 VD |
2656 | MV88E6XXX_EGRESS_MODE_ETHERTYPE, |
2657 | ETH_P_EDSA); | |
4314557c | 2658 | } |
56995cbc | 2659 | |
4314557c VD |
2660 | static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) |
2661 | { | |
2662 | if (dsa_is_dsa_port(chip->ds, port)) | |
2663 | return mv88e6xxx_set_port_mode_dsa(chip, port); | |
56995cbc | 2664 | |
2b3e9891 | 2665 | if (dsa_is_user_port(chip->ds, port)) |
4314557c | 2666 | return mv88e6xxx_set_port_mode_normal(chip, port); |
56995cbc | 2667 | |
4314557c | 2668 | /* Setup CPU port mode depending on its supported tag format */ |
670bb80f | 2669 | if (chip->tag_protocol == DSA_TAG_PROTO_DSA) |
4314557c | 2670 | return mv88e6xxx_set_port_mode_dsa(chip, port); |
56995cbc | 2671 | |
670bb80f | 2672 | if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) |
4314557c | 2673 | return mv88e6xxx_set_port_mode_edsa(chip, port); |
56995cbc | 2674 | |
4314557c | 2675 | return -EINVAL; |
56995cbc AL |
2676 | } |
2677 | ||
601aeed3 | 2678 | static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) |
56995cbc | 2679 | { |
601aeed3 | 2680 | bool message = dsa_is_dsa_port(chip->ds, port); |
56995cbc | 2681 | |
601aeed3 | 2682 | return mv88e6xxx_port_set_message_port(chip, port, message); |
4314557c | 2683 | } |
56995cbc | 2684 | |
601aeed3 | 2685 | static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) |
4314557c | 2686 | { |
a8b659e7 | 2687 | int err; |
56995cbc | 2688 | |
a8b659e7 | 2689 | if (chip->info->ops->port_set_ucast_flood) { |
7b9f16fe | 2690 | err = chip->info->ops->port_set_ucast_flood(chip, port, true); |
a8b659e7 VO |
2691 | if (err) |
2692 | return err; | |
2693 | } | |
2694 | if (chip->info->ops->port_set_mcast_flood) { | |
7b9f16fe | 2695 | err = chip->info->ops->port_set_mcast_flood(chip, port, true); |
a8b659e7 VO |
2696 | if (err) |
2697 | return err; | |
2698 | } | |
ea698f4f | 2699 | |
407308f6 | 2700 | return 0; |
ea698f4f VD |
2701 | } |
2702 | ||
45de77ff VD |
2703 | static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) |
2704 | { | |
2705 | struct mv88e6xxx_port *mvp = dev_id; | |
2706 | struct mv88e6xxx_chip *chip = mvp->chip; | |
2707 | irqreturn_t ret = IRQ_NONE; | |
2708 | int port = mvp->port; | |
193c5b26 | 2709 | int lane; |
45de77ff VD |
2710 | |
2711 | mv88e6xxx_reg_lock(chip); | |
2712 | lane = mv88e6xxx_serdes_get_lane(chip, port); | |
193c5b26 | 2713 | if (lane >= 0) |
45de77ff VD |
2714 | ret = mv88e6xxx_serdes_irq_status(chip, port, lane); |
2715 | mv88e6xxx_reg_unlock(chip); | |
2716 | ||
2717 | return ret; | |
2718 | } | |
2719 | ||
2720 | static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, | |
193c5b26 | 2721 | int lane) |
45de77ff VD |
2722 | { |
2723 | struct mv88e6xxx_port *dev_id = &chip->ports[port]; | |
2724 | unsigned int irq; | |
2725 | int err; | |
2726 | ||
2727 | /* Nothing to request if this SERDES port has no IRQ */ | |
2728 | irq = mv88e6xxx_serdes_irq_mapping(chip, port); | |
2729 | if (!irq) | |
2730 | return 0; | |
2731 | ||
e6f2f6b8 AL |
2732 | snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), |
2733 | "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); | |
2734 | ||
45de77ff VD |
2735 | /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ |
2736 | mv88e6xxx_reg_unlock(chip); | |
2737 | err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, | |
e6f2f6b8 AL |
2738 | IRQF_ONESHOT, dev_id->serdes_irq_name, |
2739 | dev_id); | |
45de77ff VD |
2740 | mv88e6xxx_reg_lock(chip); |
2741 | if (err) | |
2742 | return err; | |
2743 | ||
2744 | dev_id->serdes_irq = irq; | |
2745 | ||
2746 | return mv88e6xxx_serdes_irq_enable(chip, port, lane); | |
2747 | } | |
2748 | ||
2749 | static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, | |
193c5b26 | 2750 | int lane) |
45de77ff VD |
2751 | { |
2752 | struct mv88e6xxx_port *dev_id = &chip->ports[port]; | |
2753 | unsigned int irq = dev_id->serdes_irq; | |
2754 | int err; | |
2755 | ||
2756 | /* Nothing to free if no IRQ has been requested */ | |
2757 | if (!irq) | |
2758 | return 0; | |
2759 | ||
2760 | err = mv88e6xxx_serdes_irq_disable(chip, port, lane); | |
2761 | ||
2762 | /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ | |
2763 | mv88e6xxx_reg_unlock(chip); | |
2764 | free_irq(irq, dev_id); | |
2765 | mv88e6xxx_reg_lock(chip); | |
2766 | ||
2767 | dev_id->serdes_irq = 0; | |
2768 | ||
2769 | return err; | |
2770 | } | |
2771 | ||
6d91782f AL |
2772 | static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, |
2773 | bool on) | |
2774 | { | |
193c5b26 | 2775 | int lane; |
fc0bc019 | 2776 | int err; |
04aca993 | 2777 | |
dc272f60 | 2778 | lane = mv88e6xxx_serdes_get_lane(chip, port); |
193c5b26 | 2779 | if (lane < 0) |
fc0bc019 VD |
2780 | return 0; |
2781 | ||
2782 | if (on) { | |
dc272f60 | 2783 | err = mv88e6xxx_serdes_power_up(chip, port, lane); |
fc0bc019 VD |
2784 | if (err) |
2785 | return err; | |
2786 | ||
45de77ff | 2787 | err = mv88e6xxx_serdes_irq_request(chip, port, lane); |
fc0bc019 | 2788 | } else { |
45de77ff VD |
2789 | err = mv88e6xxx_serdes_irq_free(chip, port, lane); |
2790 | if (err) | |
2791 | return err; | |
fc0bc019 | 2792 | |
dc272f60 | 2793 | err = mv88e6xxx_serdes_power_down(chip, port, lane); |
fc0bc019 VD |
2794 | } |
2795 | ||
2796 | return err; | |
6d91782f AL |
2797 | } |
2798 | ||
2fda45f0 MB |
2799 | static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, |
2800 | enum mv88e6xxx_egress_direction direction, | |
2801 | int port) | |
2802 | { | |
2803 | int err; | |
2804 | ||
2805 | if (!chip->info->ops->set_egress_port) | |
2806 | return -EOPNOTSUPP; | |
2807 | ||
2808 | err = chip->info->ops->set_egress_port(chip, direction, port); | |
2809 | if (err) | |
2810 | return err; | |
2811 | ||
2812 | if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) | |
2813 | chip->ingress_dest_port = port; | |
2814 | else | |
2815 | chip->egress_dest_port = port; | |
2816 | ||
2817 | return 0; | |
2818 | } | |
2819 | ||
fa371c80 VD |
2820 | static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) |
2821 | { | |
2822 | struct dsa_switch *ds = chip->ds; | |
2823 | int upstream_port; | |
2824 | int err; | |
2825 | ||
07073c79 | 2826 | upstream_port = dsa_upstream_port(ds, port); |
fa371c80 VD |
2827 | if (chip->info->ops->port_set_upstream_port) { |
2828 | err = chip->info->ops->port_set_upstream_port(chip, port, | |
2829 | upstream_port); | |
2830 | if (err) | |
2831 | return err; | |
2832 | } | |
2833 | ||
0ea54dda VD |
2834 | if (port == upstream_port) { |
2835 | if (chip->info->ops->set_cpu_port) { | |
2836 | err = chip->info->ops->set_cpu_port(chip, | |
2837 | upstream_port); | |
2838 | if (err) | |
2839 | return err; | |
2840 | } | |
2841 | ||
2fda45f0 | 2842 | err = mv88e6xxx_set_egress_port(chip, |
5c74c54c IT |
2843 | MV88E6XXX_EGRESS_DIR_INGRESS, |
2844 | upstream_port); | |
2fda45f0 MB |
2845 | if (err && err != -EOPNOTSUPP) |
2846 | return err; | |
5c74c54c | 2847 | |
2fda45f0 | 2848 | err = mv88e6xxx_set_egress_port(chip, |
5c74c54c IT |
2849 | MV88E6XXX_EGRESS_DIR_EGRESS, |
2850 | upstream_port); | |
2fda45f0 MB |
2851 | if (err && err != -EOPNOTSUPP) |
2852 | return err; | |
0ea54dda VD |
2853 | } |
2854 | ||
fa371c80 VD |
2855 | return 0; |
2856 | } | |
2857 | ||
fad09c73 | 2858 | static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) |
d827e88a | 2859 | { |
fad09c73 | 2860 | struct dsa_switch *ds = chip->ds; |
0e7b9925 | 2861 | int err; |
54d792f2 | 2862 | u16 reg; |
d827e88a | 2863 | |
7b898469 AL |
2864 | chip->ports[port].chip = chip; |
2865 | chip->ports[port].port = port; | |
2866 | ||
d78343d2 VD |
2867 | /* MAC Forcing register: don't force link, speed, duplex or flow control |
2868 | * state to any particular values on physical ports, but force the CPU | |
2869 | * port and all DSA ports to their maximum bandwidth and full duplex. | |
2870 | */ | |
2871 | if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) | |
2872 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, | |
2873 | SPEED_MAX, DUPLEX_FULL, | |
54186b91 | 2874 | PAUSE_OFF, |
d78343d2 VD |
2875 | PHY_INTERFACE_MODE_NA); |
2876 | else | |
2877 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, | |
2878 | SPEED_UNFORCED, DUPLEX_UNFORCED, | |
54186b91 | 2879 | PAUSE_ON, |
d78343d2 VD |
2880 | PHY_INTERFACE_MODE_NA); |
2881 | if (err) | |
2882 | return err; | |
54d792f2 AL |
2883 | |
2884 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, | |
2885 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN | |
2886 | * tunneling, determine priority by looking at 802.1p and IP | |
2887 | * priority fields (IP prio has precedence), and set STP state | |
2888 | * to Forwarding. | |
2889 | * | |
2890 | * If this is the CPU link, use DSA or EDSA tagging depending | |
2891 | * on which tagging mode was configured. | |
2892 | * | |
2893 | * If this is a link to another switch, use DSA tagging mode. | |
2894 | * | |
2895 | * If this is the upstream port for this switch, enable | |
2896 | * forwarding of unknown unicasts and multicasts. | |
2897 | */ | |
a89b433b VD |
2898 | reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | |
2899 | MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | | |
2900 | MV88E6XXX_PORT_CTL0_STATE_FORWARDING; | |
2901 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); | |
56995cbc AL |
2902 | if (err) |
2903 | return err; | |
6083ce71 | 2904 | |
601aeed3 | 2905 | err = mv88e6xxx_setup_port_mode(chip, port); |
56995cbc AL |
2906 | if (err) |
2907 | return err; | |
54d792f2 | 2908 | |
601aeed3 | 2909 | err = mv88e6xxx_setup_egress_floods(chip, port); |
4314557c VD |
2910 | if (err) |
2911 | return err; | |
2912 | ||
b92ce2f5 AL |
2913 | /* Port Control 2: don't force a good FCS, set the MTU size to |
2914 | * 10222 bytes, disable 802.1q tags checking, don't discard tagged or | |
8efdda4a VD |
2915 | * untagged frames on this port, do a destination address lookup on all |
2916 | * received packets as usual, disable ARP mirroring and don't send a | |
2917 | * copy of all transmitted/received frames on this port to the CPU. | |
54d792f2 | 2918 | */ |
a23b2961 AL |
2919 | err = mv88e6xxx_port_set_map_da(chip, port); |
2920 | if (err) | |
2921 | return err; | |
8efdda4a | 2922 | |
fa371c80 VD |
2923 | err = mv88e6xxx_setup_upstream_port(chip, port); |
2924 | if (err) | |
2925 | return err; | |
54d792f2 | 2926 | |
a23b2961 | 2927 | err = mv88e6xxx_port_set_8021q_mode(chip, port, |
81c6edb2 | 2928 | MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); |
a23b2961 AL |
2929 | if (err) |
2930 | return err; | |
2931 | ||
5bded825 VO |
2932 | /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the |
2933 | * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as | |
2934 | * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used | |
2935 | * as the private PVID on ports under a VLAN-unaware bridge. | |
2936 | * Shared (DSA and CPU) ports must also be members of it, to translate | |
2937 | * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of | |
2938 | * relying on their port default FID. | |
2939 | */ | |
2940 | err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, | |
2941 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED, | |
2942 | false); | |
2943 | if (err) | |
2944 | return err; | |
2945 | ||
cd782656 | 2946 | if (chip->info->ops->port_set_jumbo_size) { |
b92ce2f5 | 2947 | err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); |
5f436666 AL |
2948 | if (err) |
2949 | return err; | |
2950 | } | |
2951 | ||
041bd545 TW |
2952 | /* Port Association Vector: disable automatic address learning |
2953 | * on all user ports since they start out in standalone | |
2954 | * mode. When joining a bridge, learning will be configured to | |
2955 | * match the bridge port settings. Enable learning on all | |
2956 | * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the | |
2957 | * learning process. | |
2958 | * | |
2959 | * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, | |
2960 | * and RefreshLocked. I.e. setup standard automatic learning. | |
54d792f2 | 2961 | */ |
041bd545 | 2962 | if (dsa_is_user_port(ds, port)) |
65fa4027 | 2963 | reg = 0; |
041bd545 TW |
2964 | else |
2965 | reg = 1 << port; | |
4c7ea3c0 | 2966 | |
2a4614e4 VD |
2967 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, |
2968 | reg); | |
0e7b9925 AL |
2969 | if (err) |
2970 | return err; | |
54d792f2 AL |
2971 | |
2972 | /* Egress rate control 2: disable egress rate control. */ | |
2cb8cb14 VD |
2973 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, |
2974 | 0x0000); | |
0e7b9925 AL |
2975 | if (err) |
2976 | return err; | |
54d792f2 | 2977 | |
0898432c VD |
2978 | if (chip->info->ops->port_pause_limit) { |
2979 | err = chip->info->ops->port_pause_limit(chip, port, 0, 0); | |
0e7b9925 AL |
2980 | if (err) |
2981 | return err; | |
b35d322a | 2982 | } |
54d792f2 | 2983 | |
c8c94891 VD |
2984 | if (chip->info->ops->port_disable_learn_limit) { |
2985 | err = chip->info->ops->port_disable_learn_limit(chip, port); | |
2986 | if (err) | |
2987 | return err; | |
2988 | } | |
2989 | ||
9dbfb4e1 VD |
2990 | if (chip->info->ops->port_disable_pri_override) { |
2991 | err = chip->info->ops->port_disable_pri_override(chip, port); | |
0e7b9925 AL |
2992 | if (err) |
2993 | return err; | |
ef0a7318 | 2994 | } |
2bbb33be | 2995 | |
ef0a7318 AL |
2996 | if (chip->info->ops->port_tag_remap) { |
2997 | err = chip->info->ops->port_tag_remap(chip, port); | |
0e7b9925 AL |
2998 | if (err) |
2999 | return err; | |
54d792f2 AL |
3000 | } |
3001 | ||
ef70b111 AL |
3002 | if (chip->info->ops->port_egress_rate_limiting) { |
3003 | err = chip->info->ops->port_egress_rate_limiting(chip, port); | |
0e7b9925 AL |
3004 | if (err) |
3005 | return err; | |
54d792f2 AL |
3006 | } |
3007 | ||
121b8fe2 HF |
3008 | if (chip->info->ops->port_setup_message_port) { |
3009 | err = chip->info->ops->port_setup_message_port(chip, port); | |
3010 | if (err) | |
3011 | return err; | |
3012 | } | |
d827e88a | 3013 | |
207afda1 | 3014 | /* Port based VLAN map: give each port the same default address |
b7666efe VD |
3015 | * database, and allow bidirectional communication between the |
3016 | * CPU and DSA port(s), and the other ports. | |
d827e88a | 3017 | */ |
5bded825 | 3018 | err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); |
0e7b9925 AL |
3019 | if (err) |
3020 | return err; | |
2db9ce1f | 3021 | |
240ea3ef | 3022 | err = mv88e6xxx_port_vlan_map(chip, port); |
0e7b9925 AL |
3023 | if (err) |
3024 | return err; | |
d827e88a GR |
3025 | |
3026 | /* Default VLAN ID and priority: don't set a default VLAN | |
3027 | * ID, and set the default packet priority to zero. | |
3028 | */ | |
b7929fb3 | 3029 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); |
dbde9e66 AL |
3030 | } |
3031 | ||
2a550aec AL |
3032 | static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) |
3033 | { | |
3034 | struct mv88e6xxx_chip *chip = ds->priv; | |
3035 | ||
3036 | if (chip->info->ops->port_set_jumbo_size) | |
b9c587fe | 3037 | return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; |
1baf0fac | 3038 | else if (chip->info->ops->set_max_frame_size) |
b9c587fe AL |
3039 | return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; |
3040 | return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; | |
2a550aec AL |
3041 | } |
3042 | ||
3043 | static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) | |
3044 | { | |
3045 | struct mv88e6xxx_chip *chip = ds->priv; | |
3046 | int ret = 0; | |
3047 | ||
b9c587fe AL |
3048 | if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) |
3049 | new_mtu += EDSA_HLEN; | |
3050 | ||
2a550aec AL |
3051 | mv88e6xxx_reg_lock(chip); |
3052 | if (chip->info->ops->port_set_jumbo_size) | |
3053 | ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); | |
1baf0fac CP |
3054 | else if (chip->info->ops->set_max_frame_size) |
3055 | ret = chip->info->ops->set_max_frame_size(chip, new_mtu); | |
2a550aec AL |
3056 | else |
3057 | if (new_mtu > 1522) | |
3058 | ret = -EINVAL; | |
3059 | mv88e6xxx_reg_unlock(chip); | |
3060 | ||
3061 | return ret; | |
3062 | } | |
3063 | ||
04aca993 AL |
3064 | static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, |
3065 | struct phy_device *phydev) | |
3066 | { | |
3067 | struct mv88e6xxx_chip *chip = ds->priv; | |
523a8904 | 3068 | int err; |
04aca993 | 3069 | |
c9acece0 | 3070 | mv88e6xxx_reg_lock(chip); |
523a8904 | 3071 | err = mv88e6xxx_serdes_power(chip, port, true); |
c9acece0 | 3072 | mv88e6xxx_reg_unlock(chip); |
04aca993 AL |
3073 | |
3074 | return err; | |
3075 | } | |
3076 | ||
75104db0 | 3077 | static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) |
04aca993 AL |
3078 | { |
3079 | struct mv88e6xxx_chip *chip = ds->priv; | |
3080 | ||
c9acece0 | 3081 | mv88e6xxx_reg_lock(chip); |
523a8904 VD |
3082 | if (mv88e6xxx_serdes_power(chip, port, false)) |
3083 | dev_err(chip->dev, "failed to power off SERDES\n"); | |
c9acece0 | 3084 | mv88e6xxx_reg_unlock(chip); |
04aca993 AL |
3085 | } |
3086 | ||
2cfcd964 VD |
3087 | static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, |
3088 | unsigned int ageing_time) | |
3089 | { | |
04bed143 | 3090 | struct mv88e6xxx_chip *chip = ds->priv; |
2cfcd964 VD |
3091 | int err; |
3092 | ||
c9acece0 | 3093 | mv88e6xxx_reg_lock(chip); |
720c6343 | 3094 | err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); |
c9acece0 | 3095 | mv88e6xxx_reg_unlock(chip); |
2cfcd964 VD |
3096 | |
3097 | return err; | |
3098 | } | |
3099 | ||
447b1bb8 | 3100 | static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) |
acdaffcc | 3101 | { |
552238b5 | 3102 | int err; |
54d792f2 | 3103 | |
de227387 | 3104 | /* Initialize the statistics unit */ |
447b1bb8 VD |
3105 | if (chip->info->ops->stats_set_histogram) { |
3106 | err = chip->info->ops->stats_set_histogram(chip); | |
3107 | if (err) | |
3108 | return err; | |
3109 | } | |
de227387 | 3110 | |
40cff8fc | 3111 | return mv88e6xxx_g1_stats_clear(chip); |
9729934c VD |
3112 | } |
3113 | ||
ea89098e AL |
3114 | /* Check if the errata has already been applied. */ |
3115 | static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) | |
3116 | { | |
3117 | int port; | |
3118 | int err; | |
3119 | u16 val; | |
3120 | ||
3121 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { | |
60907013 | 3122 | err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); |
ea89098e AL |
3123 | if (err) { |
3124 | dev_err(chip->dev, | |
3125 | "Error reading hidden register: %d\n", err); | |
3126 | return false; | |
3127 | } | |
3128 | if (val != 0x01c0) | |
3129 | return false; | |
3130 | } | |
3131 | ||
3132 | return true; | |
3133 | } | |
3134 | ||
3135 | /* The 6390 copper ports have an errata which require poking magic | |
3136 | * values into undocumented hidden registers and then performing a | |
3137 | * software reset. | |
3138 | */ | |
3139 | static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) | |
3140 | { | |
3141 | int port; | |
3142 | int err; | |
3143 | ||
3144 | if (mv88e6390_setup_errata_applied(chip)) | |
3145 | return 0; | |
3146 | ||
3147 | /* Set the ports into blocking mode */ | |
3148 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { | |
3149 | err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); | |
3150 | if (err) | |
3151 | return err; | |
3152 | } | |
3153 | ||
3154 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { | |
60907013 | 3155 | err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); |
ea89098e AL |
3156 | if (err) |
3157 | return err; | |
3158 | } | |
3159 | ||
3160 | return mv88e6xxx_software_reset(chip); | |
3161 | } | |
3162 | ||
23e8b470 AL |
3163 | static void mv88e6xxx_teardown(struct dsa_switch *ds) |
3164 | { | |
3165 | mv88e6xxx_teardown_devlink_params(ds); | |
e0c69ca7 | 3166 | dsa_devlink_resources_unregister(ds); |
fd292c18 | 3167 | mv88e6xxx_teardown_devlink_regions_global(ds); |
23e8b470 AL |
3168 | } |
3169 | ||
f81ec90f | 3170 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
08a01261 | 3171 | { |
04bed143 | 3172 | struct mv88e6xxx_chip *chip = ds->priv; |
2d2e1dd2 | 3173 | u8 cmode; |
08a01261 | 3174 | int err; |
a1a6a4d1 VD |
3175 | int i; |
3176 | ||
fad09c73 | 3177 | chip->ds = ds; |
a3c53be5 | 3178 | ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); |
08a01261 | 3179 | |
ce5df689 VO |
3180 | /* Since virtual bridges are mapped in the PVT, the number we support |
3181 | * depends on the physical switch topology. We need to let DSA figure | |
3182 | * that out and therefore we cannot set this at dsa_register_switch() | |
3183 | * time. | |
3184 | */ | |
3185 | if (mv88e6xxx_has_pvt(chip)) | |
3186 | ds->num_fwd_offloading_bridges = MV88E6XXX_MAX_PVT_SWITCHES - | |
3187 | ds->dst->last_switch - 1; | |
3188 | ||
c9acece0 | 3189 | mv88e6xxx_reg_lock(chip); |
08a01261 | 3190 | |
ea89098e AL |
3191 | if (chip->info->ops->setup_errata) { |
3192 | err = chip->info->ops->setup_errata(chip); | |
3193 | if (err) | |
3194 | goto unlock; | |
3195 | } | |
3196 | ||
2d2e1dd2 AL |
3197 | /* Cache the cmode of each port. */ |
3198 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { | |
3199 | if (chip->info->ops->port_get_cmode) { | |
3200 | err = chip->info->ops->port_get_cmode(chip, i, &cmode); | |
3201 | if (err) | |
e29129fc | 3202 | goto unlock; |
2d2e1dd2 AL |
3203 | |
3204 | chip->ports[i].cmode = cmode; | |
3205 | } | |
3206 | } | |
3207 | ||
5bded825 VO |
3208 | err = mv88e6xxx_vtu_setup(chip); |
3209 | if (err) | |
3210 | goto unlock; | |
3211 | ||
9729934c | 3212 | /* Setup Switch Port Registers */ |
370b4ffb | 3213 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
b759f528 VD |
3214 | if (dsa_is_unused_port(ds, i)) |
3215 | continue; | |
3216 | ||
c857486a | 3217 | /* Prevent the use of an invalid port. */ |
b759f528 | 3218 | if (mv88e6xxx_is_invalid_port(chip, i)) { |
c857486a HF |
3219 | dev_err(chip->dev, "port %d is invalid\n", i); |
3220 | err = -EINVAL; | |
3221 | goto unlock; | |
3222 | } | |
3223 | ||
9729934c VD |
3224 | err = mv88e6xxx_setup_port(chip, i); |
3225 | if (err) | |
3226 | goto unlock; | |
3227 | } | |
3228 | ||
cd8da8bb VD |
3229 | err = mv88e6xxx_irl_setup(chip); |
3230 | if (err) | |
3231 | goto unlock; | |
3232 | ||
04a69a17 VD |
3233 | err = mv88e6xxx_mac_setup(chip); |
3234 | if (err) | |
3235 | goto unlock; | |
3236 | ||
1b17aedf VD |
3237 | err = mv88e6xxx_phy_setup(chip); |
3238 | if (err) | |
3239 | goto unlock; | |
3240 | ||
81228996 VD |
3241 | err = mv88e6xxx_pvt_setup(chip); |
3242 | if (err) | |
3243 | goto unlock; | |
3244 | ||
a2ac29d2 VD |
3245 | err = mv88e6xxx_atu_setup(chip); |
3246 | if (err) | |
3247 | goto unlock; | |
3248 | ||
87fa886e AL |
3249 | err = mv88e6xxx_broadcast_setup(chip, 0); |
3250 | if (err) | |
3251 | goto unlock; | |
3252 | ||
9e907d73 VD |
3253 | err = mv88e6xxx_pot_setup(chip); |
3254 | if (err) | |
3255 | goto unlock; | |
3256 | ||
9e5baf9b VD |
3257 | err = mv88e6xxx_rmu_setup(chip); |
3258 | if (err) | |
3259 | goto unlock; | |
3260 | ||
51c901a7 VD |
3261 | err = mv88e6xxx_rsvd2cpu_setup(chip); |
3262 | if (err) | |
3263 | goto unlock; | |
6e55f698 | 3264 | |
b28f872d VD |
3265 | err = mv88e6xxx_trunk_setup(chip); |
3266 | if (err) | |
3267 | goto unlock; | |
3268 | ||
c7f047b6 VD |
3269 | err = mv88e6xxx_devmap_setup(chip); |
3270 | if (err) | |
3271 | goto unlock; | |
3272 | ||
93e18d61 VD |
3273 | err = mv88e6xxx_pri_setup(chip); |
3274 | if (err) | |
3275 | goto unlock; | |
3276 | ||
c6fe0ad2 | 3277 | /* Setup PTP Hardware Clock and timestamping */ |
2fa8d3af BS |
3278 | if (chip->info->ptp_support) { |
3279 | err = mv88e6xxx_ptp_setup(chip); | |
3280 | if (err) | |
3281 | goto unlock; | |
c6fe0ad2 BS |
3282 | |
3283 | err = mv88e6xxx_hwtstamp_setup(chip); | |
3284 | if (err) | |
3285 | goto unlock; | |
2fa8d3af BS |
3286 | } |
3287 | ||
447b1bb8 VD |
3288 | err = mv88e6xxx_stats_setup(chip); |
3289 | if (err) | |
3290 | goto unlock; | |
3291 | ||
6b17e864 | 3292 | unlock: |
c9acece0 | 3293 | mv88e6xxx_reg_unlock(chip); |
db687a56 | 3294 | |
e0c69ca7 AL |
3295 | if (err) |
3296 | return err; | |
3297 | ||
3298 | /* Have to be called without holding the register lock, since | |
3299 | * they take the devlink lock, and we later take the locks in | |
3300 | * the reverse order when getting/setting parameters or | |
3301 | * resource occupancy. | |
23e8b470 | 3302 | */ |
e0c69ca7 AL |
3303 | err = mv88e6xxx_setup_devlink_resources(ds); |
3304 | if (err) | |
3305 | return err; | |
3306 | ||
3307 | err = mv88e6xxx_setup_devlink_params(ds); | |
3308 | if (err) | |
bfb25542 AL |
3309 | goto out_resources; |
3310 | ||
fd292c18 | 3311 | err = mv88e6xxx_setup_devlink_regions_global(ds); |
bfb25542 AL |
3312 | if (err) |
3313 | goto out_params; | |
3314 | ||
3315 | return 0; | |
3316 | ||
3317 | out_params: | |
3318 | mv88e6xxx_teardown_devlink_params(ds); | |
3319 | out_resources: | |
3320 | dsa_devlink_resources_unregister(ds); | |
e0c69ca7 AL |
3321 | |
3322 | return err; | |
54d792f2 AL |
3323 | } |
3324 | ||
fd292c18 VO |
3325 | static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) |
3326 | { | |
3327 | return mv88e6xxx_setup_devlink_regions_port(ds, port); | |
3328 | } | |
3329 | ||
3330 | static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) | |
3331 | { | |
3332 | mv88e6xxx_teardown_devlink_regions_port(ds, port); | |
3333 | } | |
3334 | ||
1fe976d3 PR |
3335 | /* prod_id for switch families which do not have a PHY model number */ |
3336 | static const u16 family_prod_id_table[] = { | |
3337 | [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, | |
3338 | [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, | |
c5d015b0 | 3339 | [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, |
1fe976d3 PR |
3340 | }; |
3341 | ||
e57e5e77 | 3342 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) |
fd3a0ee4 | 3343 | { |
0dd12d54 AL |
3344 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
3345 | struct mv88e6xxx_chip *chip = mdio_bus->chip; | |
1fe976d3 | 3346 | u16 prod_id; |
e57e5e77 VD |
3347 | u16 val; |
3348 | int err; | |
fd3a0ee4 | 3349 | |
ee26a228 AL |
3350 | if (!chip->info->ops->phy_read) |
3351 | return -EOPNOTSUPP; | |
3352 | ||
c9acece0 | 3353 | mv88e6xxx_reg_lock(chip); |
ee26a228 | 3354 | err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); |
c9acece0 | 3355 | mv88e6xxx_reg_unlock(chip); |
e57e5e77 | 3356 | |
1fe976d3 PR |
3357 | /* Some internal PHYs don't have a model number. */ |
3358 | if (reg == MII_PHYSID2 && !(val & 0x3f0) && | |
3359 | chip->info->family < ARRAY_SIZE(family_prod_id_table)) { | |
3360 | prod_id = family_prod_id_table[chip->info->family]; | |
3361 | if (prod_id) | |
3362 | val |= prod_id >> 4; | |
da9f3301 AL |
3363 | } |
3364 | ||
e57e5e77 | 3365 | return err ? err : val; |
fd3a0ee4 AL |
3366 | } |
3367 | ||
e57e5e77 | 3368 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
fd3a0ee4 | 3369 | { |
0dd12d54 AL |
3370 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
3371 | struct mv88e6xxx_chip *chip = mdio_bus->chip; | |
e57e5e77 | 3372 | int err; |
fd3a0ee4 | 3373 | |
ee26a228 AL |
3374 | if (!chip->info->ops->phy_write) |
3375 | return -EOPNOTSUPP; | |
3376 | ||
c9acece0 | 3377 | mv88e6xxx_reg_lock(chip); |
ee26a228 | 3378 | err = chip->info->ops->phy_write(chip, bus, phy, reg, val); |
c9acece0 | 3379 | mv88e6xxx_reg_unlock(chip); |
e57e5e77 VD |
3380 | |
3381 | return err; | |
fd3a0ee4 AL |
3382 | } |
3383 | ||
fad09c73 | 3384 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, |
a3c53be5 AL |
3385 | struct device_node *np, |
3386 | bool external) | |
b516d453 AL |
3387 | { |
3388 | static int index; | |
0dd12d54 | 3389 | struct mv88e6xxx_mdio_bus *mdio_bus; |
b516d453 AL |
3390 | struct mii_bus *bus; |
3391 | int err; | |
3392 | ||
2510babc | 3393 | if (external) { |
c9acece0 | 3394 | mv88e6xxx_reg_lock(chip); |
2510babc | 3395 | err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); |
c9acece0 | 3396 | mv88e6xxx_reg_unlock(chip); |
2510babc AL |
3397 | |
3398 | if (err) | |
3399 | return err; | |
3400 | } | |
3401 | ||
0dd12d54 | 3402 | bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); |
b516d453 AL |
3403 | if (!bus) |
3404 | return -ENOMEM; | |
3405 | ||
0dd12d54 | 3406 | mdio_bus = bus->priv; |
a3c53be5 | 3407 | mdio_bus->bus = bus; |
0dd12d54 | 3408 | mdio_bus->chip = chip; |
a3c53be5 AL |
3409 | INIT_LIST_HEAD(&mdio_bus->list); |
3410 | mdio_bus->external = external; | |
0dd12d54 | 3411 | |
b516d453 AL |
3412 | if (np) { |
3413 | bus->name = np->full_name; | |
f7ce9103 | 3414 | snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); |
b516d453 AL |
3415 | } else { |
3416 | bus->name = "mv88e6xxx SMI"; | |
3417 | snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); | |
3418 | } | |
3419 | ||
3420 | bus->read = mv88e6xxx_mdio_read; | |
3421 | bus->write = mv88e6xxx_mdio_write; | |
fad09c73 | 3422 | bus->parent = chip->dev; |
b516d453 | 3423 | |
6f88284f AL |
3424 | if (!external) { |
3425 | err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); | |
3426 | if (err) | |
3427 | return err; | |
3428 | } | |
3429 | ||
00e798c7 | 3430 | err = of_mdiobus_register(bus, np); |
b516d453 | 3431 | if (err) { |
fad09c73 | 3432 | dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); |
6f88284f | 3433 | mv88e6xxx_g2_irq_mdio_free(chip, bus); |
a3c53be5 | 3434 | return err; |
b516d453 | 3435 | } |
a3c53be5 AL |
3436 | |
3437 | if (external) | |
3438 | list_add_tail(&mdio_bus->list, &chip->mdios); | |
3439 | else | |
3440 | list_add(&mdio_bus->list, &chip->mdios); | |
b516d453 AL |
3441 | |
3442 | return 0; | |
a3c53be5 | 3443 | } |
b516d453 | 3444 | |
3126aeec AL |
3445 | static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) |
3446 | ||
3447 | { | |
3448 | struct mv88e6xxx_mdio_bus *mdio_bus; | |
3449 | struct mii_bus *bus; | |
3450 | ||
3451 | list_for_each_entry(mdio_bus, &chip->mdios, list) { | |
3452 | bus = mdio_bus->bus; | |
3453 | ||
6f88284f AL |
3454 | if (!mdio_bus->external) |
3455 | mv88e6xxx_g2_irq_mdio_free(chip, bus); | |
3456 | ||
3126aeec AL |
3457 | mdiobus_unregister(bus); |
3458 | } | |
3459 | } | |
3460 | ||
a3c53be5 AL |
3461 | static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, |
3462 | struct device_node *np) | |
3463 | { | |
a3c53be5 AL |
3464 | struct device_node *child; |
3465 | int err; | |
3466 | ||
3467 | /* Always register one mdio bus for the internal/default mdio | |
3468 | * bus. This maybe represented in the device tree, but is | |
3469 | * optional. | |
3470 | */ | |
3471 | child = of_get_child_by_name(np, "mdio"); | |
3472 | err = mv88e6xxx_mdio_register(chip, child, false); | |
3473 | if (err) | |
3474 | return err; | |
3475 | ||
3476 | /* Walk the device tree, and see if there are any other nodes | |
3477 | * which say they are compatible with the external mdio | |
3478 | * bus. | |
3479 | */ | |
3480 | for_each_available_child_of_node(np, child) { | |
ceb96fae AL |
3481 | if (of_device_is_compatible( |
3482 | child, "marvell,mv88e6xxx-mdio-external")) { | |
a3c53be5 | 3483 | err = mv88e6xxx_mdio_register(chip, child, true); |
3126aeec AL |
3484 | if (err) { |
3485 | mv88e6xxx_mdios_unregister(chip); | |
78e42040 | 3486 | of_node_put(child); |
a3c53be5 | 3487 | return err; |
3126aeec | 3488 | } |
a3c53be5 AL |
3489 | } |
3490 | } | |
3491 | ||
3492 | return 0; | |
b516d453 AL |
3493 | } |
3494 | ||
855b1932 VD |
3495 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
3496 | { | |
04bed143 | 3497 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3498 | |
3499 | return chip->eeprom_len; | |
3500 | } | |
3501 | ||
855b1932 VD |
3502 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
3503 | struct ethtool_eeprom *eeprom, u8 *data) | |
3504 | { | |
04bed143 | 3505 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3506 | int err; |
3507 | ||
ee4dc2e7 VD |
3508 | if (!chip->info->ops->get_eeprom) |
3509 | return -EOPNOTSUPP; | |
855b1932 | 3510 | |
c9acece0 | 3511 | mv88e6xxx_reg_lock(chip); |
ee4dc2e7 | 3512 | err = chip->info->ops->get_eeprom(chip, eeprom, data); |
c9acece0 | 3513 | mv88e6xxx_reg_unlock(chip); |
855b1932 VD |
3514 | |
3515 | if (err) | |
3516 | return err; | |
3517 | ||
3518 | eeprom->magic = 0xc3ec4951; | |
3519 | ||
3520 | return 0; | |
3521 | } | |
3522 | ||
855b1932 VD |
3523 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
3524 | struct ethtool_eeprom *eeprom, u8 *data) | |
3525 | { | |
04bed143 | 3526 | struct mv88e6xxx_chip *chip = ds->priv; |
855b1932 VD |
3527 | int err; |
3528 | ||
ee4dc2e7 VD |
3529 | if (!chip->info->ops->set_eeprom) |
3530 | return -EOPNOTSUPP; | |
3531 | ||
855b1932 VD |
3532 | if (eeprom->magic != 0xc3ec4951) |
3533 | return -EINVAL; | |
3534 | ||
c9acece0 | 3535 | mv88e6xxx_reg_lock(chip); |
ee4dc2e7 | 3536 | err = chip->info->ops->set_eeprom(chip, eeprom, data); |
c9acece0 | 3537 | mv88e6xxx_reg_unlock(chip); |
855b1932 VD |
3538 | |
3539 | return err; | |
3540 | } | |
3541 | ||
b3469dd8 | 3542 | static const struct mv88e6xxx_ops mv88e6085_ops = { |
4b325d8c | 3543 | /* MV88E6XXX_FAMILY_6097 */ |
93e18d61 VD |
3544 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3545 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 3546 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 3547 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
3548 | .phy_read = mv88e6185_phy_ppu_read, |
3549 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 3550 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 3551 | .port_sync_link = mv88e6xxx_port_sync_link, |
f365c6f7 | 3552 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
ef0a7318 | 3553 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3554 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
3555 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
3556 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 3557 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
ef70b111 | 3558 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3559 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3560 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3561 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 3562 | .port_get_cmode = mv88e6185_port_get_cmode, |
121b8fe2 | 3563 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 3564 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 3565 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3566 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3567 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3568 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3569 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3570 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3571 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3572 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 3573 | .pot_clear = mv88e6xxx_g2_pot_clear, |
a199d8b6 VD |
3574 | .ppu_enable = mv88e6185_g1_ppu_enable, |
3575 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 3576 | .reset = mv88e6185_g1_reset, |
9e5baf9b | 3577 | .rmu_disable = mv88e6085_g1_rmu_disable, |
f1394b78 | 3578 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3579 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6c422e34 | 3580 | .phylink_validate = mv88e6185_phylink_validate, |
1baf0fac | 3581 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
b3469dd8 VD |
3582 | }; |
3583 | ||
3584 | static const struct mv88e6xxx_ops mv88e6095_ops = { | |
4b325d8c | 3585 | /* MV88E6XXX_FAMILY_6095 */ |
93e18d61 VD |
3586 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3587 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
b073d4e2 | 3588 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
3589 | .phy_read = mv88e6185_phy_ppu_read, |
3590 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 3591 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 3592 | .port_sync_link = mv88e6185_port_sync_link, |
f365c6f7 | 3593 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
56995cbc | 3594 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
a8b659e7 VO |
3595 | .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, |
3596 | .port_set_mcast_flood = mv88e6185_port_set_default_forward, | |
a23b2961 | 3597 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
2d2e1dd2 | 3598 | .port_get_cmode = mv88e6185_port_get_cmode, |
121b8fe2 | 3599 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 3600 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 3601 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3602 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3603 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3604 | .stats_get_stats = mv88e6095_stats_get_stats, |
51c901a7 | 3605 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
f5be107c CP |
3606 | .serdes_power = mv88e6185_serdes_power, |
3607 | .serdes_get_lane = mv88e6185_serdes_get_lane, | |
3608 | .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, | |
a199d8b6 VD |
3609 | .ppu_enable = mv88e6185_g1_ppu_enable, |
3610 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 3611 | .reset = mv88e6185_g1_reset, |
f1394b78 | 3612 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 3613 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
6c422e34 | 3614 | .phylink_validate = mv88e6185_phylink_validate, |
1baf0fac | 3615 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
b3469dd8 VD |
3616 | }; |
3617 | ||
7d381a02 | 3618 | static const struct mv88e6xxx_ops mv88e6097_ops = { |
15da3cc8 | 3619 | /* MV88E6XXX_FAMILY_6097 */ |
93e18d61 VD |
3620 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3621 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 3622 | .irl_init_all = mv88e6352_g2_irl_init_all, |
7d381a02 SE |
3623 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
3624 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3625 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3626 | .port_set_link = mv88e6xxx_port_set_link, | |
4efe7662 | 3627 | .port_sync_link = mv88e6185_port_sync_link, |
f365c6f7 | 3628 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
ef0a7318 | 3629 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3630 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
3631 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
3632 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 3633 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
ef70b111 | 3634 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
0898432c | 3635 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3636 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3637 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 3638 | .port_get_cmode = mv88e6185_port_get_cmode, |
121b8fe2 | 3639 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
7d381a02 | 3640 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 3641 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
7d381a02 SE |
3642 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3643 | .stats_get_strings = mv88e6095_stats_get_strings, | |
3644 | .stats_get_stats = mv88e6095_stats_get_stats, | |
fa8d1179 VD |
3645 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3646 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
91eaa475 | 3647 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3648 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
f5be107c CP |
3649 | .serdes_power = mv88e6185_serdes_power, |
3650 | .serdes_get_lane = mv88e6185_serdes_get_lane, | |
3651 | .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, | |
5c19bc8b CP |
3652 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
3653 | .serdes_irq_enable = mv88e6097_serdes_irq_enable, | |
3654 | .serdes_irq_status = mv88e6097_serdes_irq_status, | |
9e907d73 | 3655 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3656 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 3657 | .rmu_disable = mv88e6085_g1_rmu_disable, |
f1394b78 | 3658 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3659 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6c422e34 | 3660 | .phylink_validate = mv88e6185_phylink_validate, |
1baf0fac | 3661 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
7d381a02 SE |
3662 | }; |
3663 | ||
b3469dd8 | 3664 | static const struct mv88e6xxx_ops mv88e6123_ops = { |
4b325d8c | 3665 | /* MV88E6XXX_FAMILY_6165 */ |
93e18d61 VD |
3666 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3667 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 3668 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 3669 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
ec8378bb AL |
3670 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3671 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3672 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 3673 | .port_sync_link = mv88e6xxx_port_sync_link, |
f365c6f7 | 3674 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
56995cbc | 3675 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
a8b659e7 VO |
3676 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
3677 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
c8c94891 | 3678 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3679 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 3680 | .port_get_cmode = mv88e6185_port_get_cmode, |
121b8fe2 | 3681 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
0ac64c39 | 3682 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 3683 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3684 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3685 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3686 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3687 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3688 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3689 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3690 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 3691 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3692 | .reset = mv88e6352_g1_reset, |
23e8b470 AL |
3693 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
3694 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 3695 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3696 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6c422e34 | 3697 | .phylink_validate = mv88e6185_phylink_validate, |
1baf0fac | 3698 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
b3469dd8 VD |
3699 | }; |
3700 | ||
3701 | static const struct mv88e6xxx_ops mv88e6131_ops = { | |
4b325d8c | 3702 | /* MV88E6XXX_FAMILY_6185 */ |
93e18d61 VD |
3703 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3704 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
b073d4e2 | 3705 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
3706 | .phy_read = mv88e6185_phy_ppu_read, |
3707 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 3708 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 3709 | .port_sync_link = mv88e6xxx_port_sync_link, |
f365c6f7 | 3710 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
ef0a7318 | 3711 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3712 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
3713 | .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, |
3714 | .port_set_mcast_flood = mv88e6185_port_set_default_forward, | |
56995cbc | 3715 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
a23b2961 | 3716 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
cd782656 | 3717 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3718 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3719 | .port_pause_limit = mv88e6097_port_pause_limit, |
54186b91 | 3720 | .port_set_pause = mv88e6185_port_set_pause, |
2d2e1dd2 | 3721 | .port_get_cmode = mv88e6185_port_get_cmode, |
121b8fe2 | 3722 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 3723 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 3724 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3725 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3726 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3727 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3728 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3729 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3730 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3731 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
a199d8b6 | 3732 | .ppu_enable = mv88e6185_g1_ppu_enable, |
02317e68 | 3733 | .set_cascade_port = mv88e6185_g1_set_cascade_port, |
a199d8b6 | 3734 | .ppu_disable = mv88e6185_g1_ppu_disable, |
17e708ba | 3735 | .reset = mv88e6185_g1_reset, |
f1394b78 | 3736 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 3737 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
6c422e34 | 3738 | .phylink_validate = mv88e6185_phylink_validate, |
b3469dd8 VD |
3739 | }; |
3740 | ||
990e27b0 VD |
3741 | static const struct mv88e6xxx_ops mv88e6141_ops = { |
3742 | /* MV88E6XXX_FAMILY_6341 */ | |
93e18d61 VD |
3743 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3744 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 3745 | .irl_init_all = mv88e6352_g2_irl_init_all, |
990e27b0 VD |
3746 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
3747 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
3748 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | |
3749 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
3750 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
3751 | .port_set_link = mv88e6xxx_port_set_link, | |
4efe7662 | 3752 | .port_sync_link = mv88e6xxx_port_sync_link, |
990e27b0 | 3753 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
f365c6f7 | 3754 | .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, |
7cbbee05 | 3755 | .port_max_speed_mode = mv88e6341_port_max_speed_mode, |
990e27b0 | 3756 | .port_tag_remap = mv88e6095_port_tag_remap, |
7da467d8 | 3757 | .port_set_policy = mv88e6352_port_set_policy, |
990e27b0 | 3758 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
3759 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
3760 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
990e27b0 | 3761 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3762 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
990e27b0 | 3763 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3764 | .port_pause_limit = mv88e6097_port_pause_limit, |
990e27b0 VD |
3765 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
3766 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, | |
2d2e1dd2 | 3767 | .port_get_cmode = mv88e6352_port_get_cmode, |
7a3007d2 | 3768 | .port_set_cmode = mv88e6341_port_set_cmode, |
121b8fe2 | 3769 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
990e27b0 | 3770 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
11527f3c | 3771 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
990e27b0 VD |
3772 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
3773 | .stats_get_strings = mv88e6320_stats_get_strings, | |
3774 | .stats_get_stats = mv88e6390_stats_get_stats, | |
fa8d1179 VD |
3775 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
3776 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
990e27b0 VD |
3777 | .watchdog_ops = &mv88e6390_watchdog_ops, |
3778 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, | |
9e907d73 | 3779 | .pot_clear = mv88e6xxx_g2_pot_clear, |
990e27b0 | 3780 | .reset = mv88e6352_g1_reset, |
37094887 | 3781 | .rmu_disable = mv88e6390_g1_rmu_disable, |
c07fff34 MB |
3782 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
3783 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 3784 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3785 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
d3cf7d8f MB |
3786 | .serdes_power = mv88e6390_serdes_power, |
3787 | .serdes_get_lane = mv88e6341_serdes_get_lane, | |
a5a6858b RK |
3788 | /* Check status register pause & lpa register */ |
3789 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, | |
3790 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, | |
3791 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, | |
3792 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, | |
4241ef52 | 3793 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
61a46b41 | 3794 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
907b9b9f | 3795 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
a73ccd61 | 3796 | .gpio_ops = &mv88e6352_gpio_ops, |
a03b98d6 MB |
3797 | .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, |
3798 | .serdes_get_strings = mv88e6390_serdes_get_strings, | |
3799 | .serdes_get_stats = mv88e6390_serdes_get_stats, | |
953b0dcb MB |
3800 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
3801 | .serdes_get_regs = mv88e6390_serdes_get_regs, | |
e3af71a3 | 3802 | .phylink_validate = mv88e6341_phylink_validate, |
990e27b0 VD |
3803 | }; |
3804 | ||
b3469dd8 | 3805 | static const struct mv88e6xxx_ops mv88e6161_ops = { |
4b325d8c | 3806 | /* MV88E6XXX_FAMILY_6165 */ |
93e18d61 VD |
3807 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3808 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 3809 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 3810 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
ec8378bb AL |
3811 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3812 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3813 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 3814 | .port_sync_link = mv88e6xxx_port_sync_link, |
f365c6f7 | 3815 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
ef0a7318 | 3816 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3817 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
3818 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
3819 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 3820 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
ef70b111 | 3821 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3822 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3823 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3824 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 3825 | .port_get_cmode = mv88e6185_port_get_cmode, |
121b8fe2 | 3826 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a6da21bb | 3827 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 3828 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3829 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3830 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3831 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3832 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3833 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3834 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3835 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 3836 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3837 | .reset = mv88e6352_g1_reset, |
23e8b470 AL |
3838 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
3839 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 3840 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3841 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
a469a612 | 3842 | .avb_ops = &mv88e6165_avb_ops, |
dfa54348 | 3843 | .ptp_ops = &mv88e6165_ptp_ops, |
6c422e34 | 3844 | .phylink_validate = mv88e6185_phylink_validate, |
fe230361 | 3845 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
b3469dd8 VD |
3846 | }; |
3847 | ||
3848 | static const struct mv88e6xxx_ops mv88e6165_ops = { | |
4b325d8c | 3849 | /* MV88E6XXX_FAMILY_6165 */ |
93e18d61 VD |
3850 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3851 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 3852 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 3853 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
efb3e74d AL |
3854 | .phy_read = mv88e6165_phy_read, |
3855 | .phy_write = mv88e6165_phy_write, | |
08ef7f10 | 3856 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 3857 | .port_sync_link = mv88e6xxx_port_sync_link, |
f365c6f7 | 3858 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
c8c94891 | 3859 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3860 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 3861 | .port_get_cmode = mv88e6185_port_get_cmode, |
121b8fe2 | 3862 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 3863 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 3864 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3865 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3866 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3867 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3868 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3869 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3870 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3871 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 3872 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3873 | .reset = mv88e6352_g1_reset, |
23e8b470 AL |
3874 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
3875 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 3876 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3877 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
a469a612 | 3878 | .avb_ops = &mv88e6165_avb_ops, |
dfa54348 | 3879 | .ptp_ops = &mv88e6165_ptp_ops, |
6c422e34 | 3880 | .phylink_validate = mv88e6185_phylink_validate, |
b3469dd8 VD |
3881 | }; |
3882 | ||
3883 | static const struct mv88e6xxx_ops mv88e6171_ops = { | |
4b325d8c | 3884 | /* MV88E6XXX_FAMILY_6351 */ |
93e18d61 VD |
3885 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3886 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 3887 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 3888 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3889 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3890 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3891 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 3892 | .port_sync_link = mv88e6xxx_port_sync_link, |
94d66ae6 | 3893 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
f365c6f7 | 3894 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
ef0a7318 | 3895 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3896 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
3897 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
3898 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 3899 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3900 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3901 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3902 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3903 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3904 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 3905 | .port_get_cmode = mv88e6352_port_get_cmode, |
121b8fe2 | 3906 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 3907 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 3908 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3909 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3910 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3911 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3912 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3913 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3914 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3915 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 3916 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3917 | .reset = mv88e6352_g1_reset, |
23e8b470 AL |
3918 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
3919 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 3920 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3921 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6c422e34 | 3922 | .phylink_validate = mv88e6185_phylink_validate, |
b3469dd8 VD |
3923 | }; |
3924 | ||
3925 | static const struct mv88e6xxx_ops mv88e6172_ops = { | |
4b325d8c | 3926 | /* MV88E6XXX_FAMILY_6352 */ |
93e18d61 VD |
3927 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3928 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 3929 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
3930 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
3931 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 3932 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3933 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3934 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3935 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 3936 | .port_sync_link = mv88e6xxx_port_sync_link, |
a0a0f622 | 3937 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
f365c6f7 | 3938 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
ef0a7318 | 3939 | .port_tag_remap = mv88e6095_port_tag_remap, |
f3a2cd32 | 3940 | .port_set_policy = mv88e6352_port_set_policy, |
56995cbc | 3941 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
3942 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
3943 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 3944 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3945 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3946 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3947 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 3948 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 3949 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 3950 | .port_get_cmode = mv88e6352_port_get_cmode, |
121b8fe2 | 3951 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 3952 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 3953 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
3954 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
3955 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 3956 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
3957 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
3958 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 3959 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 3960 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 3961 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 3962 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 3963 | .rmu_disable = mv88e6352_g1_rmu_disable, |
23e8b470 AL |
3964 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
3965 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 3966 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 3967 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
9db4a725 | 3968 | .serdes_get_lane = mv88e6352_serdes_get_lane, |
a5a6858b RK |
3969 | .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, |
3970 | .serdes_pcs_config = mv88e6352_serdes_pcs_config, | |
3971 | .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, | |
3972 | .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, | |
6d91782f | 3973 | .serdes_power = mv88e6352_serdes_power, |
d3f88a24 AL |
3974 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
3975 | .serdes_get_regs = mv88e6352_serdes_get_regs, | |
a73ccd61 | 3976 | .gpio_ops = &mv88e6352_gpio_ops, |
6c422e34 | 3977 | .phylink_validate = mv88e6352_phylink_validate, |
b3469dd8 VD |
3978 | }; |
3979 | ||
3980 | static const struct mv88e6xxx_ops mv88e6175_ops = { | |
4b325d8c | 3981 | /* MV88E6XXX_FAMILY_6351 */ |
93e18d61 VD |
3982 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
3983 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 3984 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 3985 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
3986 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
3987 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 3988 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 3989 | .port_sync_link = mv88e6xxx_port_sync_link, |
94d66ae6 | 3990 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
f365c6f7 | 3991 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
ef0a7318 | 3992 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 3993 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
3994 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
3995 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 3996 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 3997 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 3998 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 3999 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 4000 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4001 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4002 | .port_get_cmode = mv88e6352_port_get_cmode, |
121b8fe2 | 4003 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 4004 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 4005 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
4006 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4007 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 4008 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
4009 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4010 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 4011 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 4012 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 4013 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4014 | .reset = mv88e6352_g1_reset, |
23e8b470 AL |
4015 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4016 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 4017 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 4018 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6c422e34 | 4019 | .phylink_validate = mv88e6185_phylink_validate, |
b3469dd8 VD |
4020 | }; |
4021 | ||
4022 | static const struct mv88e6xxx_ops mv88e6176_ops = { | |
4b325d8c | 4023 | /* MV88E6XXX_FAMILY_6352 */ |
93e18d61 VD |
4024 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4025 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 4026 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
4027 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
4028 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 4029 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
4030 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
4031 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 4032 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 4033 | .port_sync_link = mv88e6xxx_port_sync_link, |
a0a0f622 | 4034 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
f365c6f7 | 4035 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
ef0a7318 | 4036 | .port_tag_remap = mv88e6095_port_tag_remap, |
f3a2cd32 | 4037 | .port_set_policy = mv88e6352_port_set_policy, |
56995cbc | 4038 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4039 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4040 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4041 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 4042 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 4043 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 4044 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 4045 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4046 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4047 | .port_get_cmode = mv88e6352_port_get_cmode, |
121b8fe2 | 4048 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 4049 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 4050 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
4051 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4052 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 4053 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
4054 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4055 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 4056 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 4057 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 4058 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4059 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 4060 | .rmu_disable = mv88e6352_g1_rmu_disable, |
23e8b470 AL |
4061 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4062 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 4063 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 4064 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
9db4a725 | 4065 | .serdes_get_lane = mv88e6352_serdes_get_lane, |
a5a6858b RK |
4066 | .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, |
4067 | .serdes_pcs_config = mv88e6352_serdes_pcs_config, | |
4068 | .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, | |
4069 | .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, | |
6d91782f | 4070 | .serdes_power = mv88e6352_serdes_power, |
4241ef52 | 4071 | .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, |
61a46b41 | 4072 | .serdes_irq_enable = mv88e6352_serdes_irq_enable, |
907b9b9f | 4073 | .serdes_irq_status = mv88e6352_serdes_irq_status, |
d3f88a24 AL |
4074 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
4075 | .serdes_get_regs = mv88e6352_serdes_get_regs, | |
a73ccd61 | 4076 | .gpio_ops = &mv88e6352_gpio_ops, |
6c422e34 | 4077 | .phylink_validate = mv88e6352_phylink_validate, |
b3469dd8 VD |
4078 | }; |
4079 | ||
4080 | static const struct mv88e6xxx_ops mv88e6185_ops = { | |
4b325d8c | 4081 | /* MV88E6XXX_FAMILY_6185 */ |
93e18d61 VD |
4082 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4083 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
b073d4e2 | 4084 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
7e20cfb5 VD |
4085 | .phy_read = mv88e6185_phy_ppu_read, |
4086 | .phy_write = mv88e6185_phy_ppu_write, | |
08ef7f10 | 4087 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 4088 | .port_sync_link = mv88e6185_port_sync_link, |
f365c6f7 | 4089 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
56995cbc | 4090 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
a8b659e7 VO |
4091 | .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, |
4092 | .port_set_mcast_flood = mv88e6185_port_set_default_forward, | |
ef70b111 | 4093 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
a23b2961 | 4094 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
54186b91 | 4095 | .port_set_pause = mv88e6185_port_set_pause, |
2d2e1dd2 | 4096 | .port_get_cmode = mv88e6185_port_get_cmode, |
121b8fe2 | 4097 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 4098 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
40cff8fc | 4099 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
4100 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4101 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 4102 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
4103 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4104 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 4105 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 4106 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
f5be107c CP |
4107 | .serdes_power = mv88e6185_serdes_power, |
4108 | .serdes_get_lane = mv88e6185_serdes_get_lane, | |
4109 | .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, | |
02317e68 | 4110 | .set_cascade_port = mv88e6185_g1_set_cascade_port, |
a199d8b6 VD |
4111 | .ppu_enable = mv88e6185_g1_ppu_enable, |
4112 | .ppu_disable = mv88e6185_g1_ppu_disable, | |
17e708ba | 4113 | .reset = mv88e6185_g1_reset, |
f1394b78 | 4114 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 4115 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
6c422e34 | 4116 | .phylink_validate = mv88e6185_phylink_validate, |
1baf0fac | 4117 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
b3469dd8 VD |
4118 | }; |
4119 | ||
1a3b39ec | 4120 | static const struct mv88e6xxx_ops mv88e6190_ops = { |
4b325d8c | 4121 | /* MV88E6XXX_FAMILY_6390 */ |
ea89098e | 4122 | .setup_errata = mv88e6390_setup_errata, |
cd8da8bb | 4123 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
4124 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4125 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
4126 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4127 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
4128 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
4129 | .port_set_link = mv88e6xxx_port_set_link, | |
4efe7662 | 4130 | .port_sync_link = mv88e6xxx_port_sync_link, |
1a3b39ec | 4131 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
f365c6f7 | 4132 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
7cbbee05 | 4133 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
ef0a7318 | 4134 | .port_tag_remap = mv88e6390_port_tag_remap, |
f3a2cd32 | 4135 | .port_set_policy = mv88e6352_port_set_policy, |
56995cbc | 4136 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4137 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4138 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4139 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
e8b34c67 | 4140 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
0898432c | 4141 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 4142 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4143 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4144 | .port_get_cmode = mv88e6352_port_get_cmode, |
fdc71eea | 4145 | .port_set_cmode = mv88e6390_port_set_cmode, |
121b8fe2 | 4146 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
79523473 | 4147 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 4148 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
4149 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4150 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 4151 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
4152 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4153 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 4154 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 4155 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 4156 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4157 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 4158 | .rmu_disable = mv88e6390_g1_rmu_disable, |
23e8b470 AL |
4159 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4160 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
931d1822 VD |
4161 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
4162 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 4163 | .serdes_power = mv88e6390_serdes_power, |
17deaf5c | 4164 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
a5a6858b RK |
4165 | /* Check status register pause & lpa register */ |
4166 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, | |
4167 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, | |
4168 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, | |
4169 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, | |
4241ef52 | 4170 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
61a46b41 | 4171 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
907b9b9f | 4172 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
4262c38d AL |
4173 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
4174 | .serdes_get_stats = mv88e6390_serdes_get_stats, | |
bf3504ce AL |
4175 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4176 | .serdes_get_regs = mv88e6390_serdes_get_regs, | |
a73ccd61 | 4177 | .gpio_ops = &mv88e6352_gpio_ops, |
6c422e34 | 4178 | .phylink_validate = mv88e6390_phylink_validate, |
1a3b39ec AL |
4179 | }; |
4180 | ||
4181 | static const struct mv88e6xxx_ops mv88e6190x_ops = { | |
4b325d8c | 4182 | /* MV88E6XXX_FAMILY_6390 */ |
ea89098e | 4183 | .setup_errata = mv88e6390_setup_errata, |
cd8da8bb | 4184 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
4185 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4186 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
4187 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4188 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
4189 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
4190 | .port_set_link = mv88e6xxx_port_set_link, | |
4efe7662 | 4191 | .port_sync_link = mv88e6xxx_port_sync_link, |
1a3b39ec | 4192 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
f365c6f7 | 4193 | .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, |
7cbbee05 | 4194 | .port_max_speed_mode = mv88e6390x_port_max_speed_mode, |
ef0a7318 | 4195 | .port_tag_remap = mv88e6390_port_tag_remap, |
f3a2cd32 | 4196 | .port_set_policy = mv88e6352_port_set_policy, |
56995cbc | 4197 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4198 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4199 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4200 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
e8b34c67 | 4201 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
0898432c | 4202 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 4203 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4204 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4205 | .port_get_cmode = mv88e6352_port_get_cmode, |
fdc71eea | 4206 | .port_set_cmode = mv88e6390x_port_set_cmode, |
121b8fe2 | 4207 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
79523473 | 4208 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 4209 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
4210 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4211 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 4212 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
4213 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4214 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 4215 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 4216 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 4217 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4218 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 4219 | .rmu_disable = mv88e6390_g1_rmu_disable, |
23e8b470 AL |
4220 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4221 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
931d1822 VD |
4222 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
4223 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
d3cf7d8f | 4224 | .serdes_power = mv88e6390_serdes_power, |
17deaf5c | 4225 | .serdes_get_lane = mv88e6390x_serdes_get_lane, |
a5a6858b RK |
4226 | /* Check status register pause & lpa register */ |
4227 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, | |
4228 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, | |
4229 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, | |
4230 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, | |
4241ef52 | 4231 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
61a46b41 | 4232 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
907b9b9f | 4233 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
4262c38d AL |
4234 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
4235 | .serdes_get_stats = mv88e6390_serdes_get_stats, | |
bf3504ce AL |
4236 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4237 | .serdes_get_regs = mv88e6390_serdes_get_regs, | |
a73ccd61 | 4238 | .gpio_ops = &mv88e6352_gpio_ops, |
6c422e34 | 4239 | .phylink_validate = mv88e6390x_phylink_validate, |
1a3b39ec AL |
4240 | }; |
4241 | ||
4242 | static const struct mv88e6xxx_ops mv88e6191_ops = { | |
4b325d8c | 4243 | /* MV88E6XXX_FAMILY_6390 */ |
ea89098e | 4244 | .setup_errata = mv88e6390_setup_errata, |
cd8da8bb | 4245 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
4246 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4247 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
4248 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4249 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
4250 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
4251 | .port_set_link = mv88e6xxx_port_set_link, | |
4efe7662 | 4252 | .port_sync_link = mv88e6xxx_port_sync_link, |
1a3b39ec | 4253 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
f365c6f7 | 4254 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
7cbbee05 | 4255 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
ef0a7318 | 4256 | .port_tag_remap = mv88e6390_port_tag_remap, |
56995cbc | 4257 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4258 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4259 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4260 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
0898432c | 4261 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 4262 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4263 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4264 | .port_get_cmode = mv88e6352_port_get_cmode, |
fdc71eea | 4265 | .port_set_cmode = mv88e6390_port_set_cmode, |
121b8fe2 | 4266 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
79523473 | 4267 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 4268 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
4269 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4270 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 4271 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
4272 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4273 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 4274 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 4275 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 4276 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4277 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 4278 | .rmu_disable = mv88e6390_g1_rmu_disable, |
23e8b470 AL |
4279 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4280 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
931d1822 VD |
4281 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
4282 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 4283 | .serdes_power = mv88e6390_serdes_power, |
17deaf5c | 4284 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
a5a6858b RK |
4285 | /* Check status register pause & lpa register */ |
4286 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, | |
4287 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, | |
4288 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, | |
4289 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, | |
4241ef52 | 4290 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
61a46b41 | 4291 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
907b9b9f | 4292 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
4262c38d AL |
4293 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
4294 | .serdes_get_stats = mv88e6390_serdes_get_stats, | |
bf3504ce AL |
4295 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4296 | .serdes_get_regs = mv88e6390_serdes_get_regs, | |
6d2ac8ee AL |
4297 | .avb_ops = &mv88e6390_avb_ops, |
4298 | .ptp_ops = &mv88e6352_ptp_ops, | |
6c422e34 | 4299 | .phylink_validate = mv88e6390_phylink_validate, |
1a3b39ec AL |
4300 | }; |
4301 | ||
b3469dd8 | 4302 | static const struct mv88e6xxx_ops mv88e6240_ops = { |
4b325d8c | 4303 | /* MV88E6XXX_FAMILY_6352 */ |
93e18d61 VD |
4304 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4305 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 4306 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
4307 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
4308 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 4309 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
4310 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
4311 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 4312 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 4313 | .port_sync_link = mv88e6xxx_port_sync_link, |
a0a0f622 | 4314 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
f365c6f7 | 4315 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
ef0a7318 | 4316 | .port_tag_remap = mv88e6095_port_tag_remap, |
f3a2cd32 | 4317 | .port_set_policy = mv88e6352_port_set_policy, |
56995cbc | 4318 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4319 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4320 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4321 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 4322 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 4323 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 4324 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 4325 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4326 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4327 | .port_get_cmode = mv88e6352_port_get_cmode, |
121b8fe2 | 4328 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 4329 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 4330 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
4331 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4332 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 4333 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
4334 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4335 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 4336 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 4337 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 4338 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4339 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 4340 | .rmu_disable = mv88e6352_g1_rmu_disable, |
23e8b470 AL |
4341 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4342 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 4343 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 4344 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
9db4a725 | 4345 | .serdes_get_lane = mv88e6352_serdes_get_lane, |
a5a6858b RK |
4346 | .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, |
4347 | .serdes_pcs_config = mv88e6352_serdes_pcs_config, | |
4348 | .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, | |
4349 | .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, | |
6d91782f | 4350 | .serdes_power = mv88e6352_serdes_power, |
4241ef52 | 4351 | .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, |
61a46b41 | 4352 | .serdes_irq_enable = mv88e6352_serdes_irq_enable, |
907b9b9f | 4353 | .serdes_irq_status = mv88e6352_serdes_irq_status, |
d3f88a24 AL |
4354 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
4355 | .serdes_get_regs = mv88e6352_serdes_get_regs, | |
a73ccd61 | 4356 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 4357 | .avb_ops = &mv88e6352_avb_ops, |
6d2ac8ee | 4358 | .ptp_ops = &mv88e6352_ptp_ops, |
6c422e34 | 4359 | .phylink_validate = mv88e6352_phylink_validate, |
b3469dd8 VD |
4360 | }; |
4361 | ||
1f71836f RV |
4362 | static const struct mv88e6xxx_ops mv88e6250_ops = { |
4363 | /* MV88E6XXX_FAMILY_6250 */ | |
4364 | .ieee_pri_map = mv88e6250_g1_ieee_pri_map, | |
4365 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
4366 | .irl_init_all = mv88e6352_g2_irl_init_all, | |
4367 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, | |
4368 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
4369 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | |
4370 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
4371 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
4372 | .port_set_link = mv88e6xxx_port_set_link, | |
4efe7662 | 4373 | .port_sync_link = mv88e6xxx_port_sync_link, |
1f71836f | 4374 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
f365c6f7 | 4375 | .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, |
1f71836f RV |
4376 | .port_tag_remap = mv88e6095_port_tag_remap, |
4377 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, | |
a8b659e7 VO |
4378 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4379 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
1f71836f RV |
4380 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4381 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, | |
4382 | .port_pause_limit = mv88e6097_port_pause_limit, | |
4383 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, | |
1f71836f RV |
4384 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
4385 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, | |
4386 | .stats_get_sset_count = mv88e6250_stats_get_sset_count, | |
4387 | .stats_get_strings = mv88e6250_stats_get_strings, | |
4388 | .stats_get_stats = mv88e6250_stats_get_stats, | |
4389 | .set_cpu_port = mv88e6095_g1_set_cpu_port, | |
4390 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
4391 | .watchdog_ops = &mv88e6250_watchdog_ops, | |
4392 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, | |
4393 | .pot_clear = mv88e6xxx_g2_pot_clear, | |
4394 | .reset = mv88e6250_g1_reset, | |
67c9ed1c | 4395 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
b28f3f3c | 4396 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
71509614 HF |
4397 | .avb_ops = &mv88e6352_avb_ops, |
4398 | .ptp_ops = &mv88e6250_ptp_ops, | |
1f71836f RV |
4399 | .phylink_validate = mv88e6065_phylink_validate, |
4400 | }; | |
4401 | ||
1a3b39ec | 4402 | static const struct mv88e6xxx_ops mv88e6290_ops = { |
4b325d8c | 4403 | /* MV88E6XXX_FAMILY_6390 */ |
ea89098e | 4404 | .setup_errata = mv88e6390_setup_errata, |
cd8da8bb | 4405 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
4406 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4407 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
4408 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4409 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
4410 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
4411 | .port_set_link = mv88e6xxx_port_set_link, | |
4efe7662 | 4412 | .port_sync_link = mv88e6xxx_port_sync_link, |
1a3b39ec | 4413 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
f365c6f7 | 4414 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
7cbbee05 | 4415 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
ef0a7318 | 4416 | .port_tag_remap = mv88e6390_port_tag_remap, |
f3a2cd32 | 4417 | .port_set_policy = mv88e6352_port_set_policy, |
56995cbc | 4418 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4419 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4420 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4421 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
0898432c | 4422 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 4423 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4424 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4425 | .port_get_cmode = mv88e6352_port_get_cmode, |
fdc71eea | 4426 | .port_set_cmode = mv88e6390_port_set_cmode, |
121b8fe2 | 4427 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
79523473 | 4428 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 4429 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
4430 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4431 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 4432 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
4433 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4434 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 4435 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 4436 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 4437 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4438 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 4439 | .rmu_disable = mv88e6390_g1_rmu_disable, |
23e8b470 AL |
4440 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4441 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
931d1822 VD |
4442 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
4443 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 4444 | .serdes_power = mv88e6390_serdes_power, |
17deaf5c | 4445 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
a5a6858b RK |
4446 | /* Check status register pause & lpa register */ |
4447 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, | |
4448 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, | |
4449 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, | |
4450 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, | |
4241ef52 | 4451 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
61a46b41 | 4452 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
907b9b9f | 4453 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
4262c38d AL |
4454 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
4455 | .serdes_get_stats = mv88e6390_serdes_get_stats, | |
bf3504ce AL |
4456 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4457 | .serdes_get_regs = mv88e6390_serdes_get_regs, | |
a73ccd61 | 4458 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 4459 | .avb_ops = &mv88e6390_avb_ops, |
6d2ac8ee | 4460 | .ptp_ops = &mv88e6352_ptp_ops, |
6c422e34 | 4461 | .phylink_validate = mv88e6390_phylink_validate, |
1a3b39ec AL |
4462 | }; |
4463 | ||
b3469dd8 | 4464 | static const struct mv88e6xxx_ops mv88e6320_ops = { |
4b325d8c | 4465 | /* MV88E6XXX_FAMILY_6320 */ |
93e18d61 VD |
4466 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4467 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 4468 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
4469 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
4470 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 4471 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
4472 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
4473 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 4474 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 4475 | .port_sync_link = mv88e6xxx_port_sync_link, |
f365c6f7 | 4476 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
ef0a7318 | 4477 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 4478 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4479 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4480 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4481 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 4482 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 4483 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 4484 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 4485 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4486 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4487 | .port_get_cmode = mv88e6352_port_get_cmode, |
121b8fe2 | 4488 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 4489 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 4490 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
4491 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4492 | .stats_get_strings = mv88e6320_stats_get_strings, | |
052f947f | 4493 | .stats_get_stats = mv88e6320_stats_get_stats, |
fa8d1179 VD |
4494 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4495 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
9c7f37e5 | 4496 | .watchdog_ops = &mv88e6390_watchdog_ops, |
51c901a7 | 4497 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 4498 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4499 | .reset = mv88e6352_g1_reset, |
f1394b78 | 4500 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 4501 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
a73ccd61 | 4502 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 4503 | .avb_ops = &mv88e6352_avb_ops, |
6d2ac8ee | 4504 | .ptp_ops = &mv88e6352_ptp_ops, |
6c422e34 | 4505 | .phylink_validate = mv88e6185_phylink_validate, |
b3469dd8 VD |
4506 | }; |
4507 | ||
4508 | static const struct mv88e6xxx_ops mv88e6321_ops = { | |
bd807204 | 4509 | /* MV88E6XXX_FAMILY_6320 */ |
93e18d61 VD |
4510 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4511 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 4512 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
4513 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
4514 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 4515 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
4516 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
4517 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 4518 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 4519 | .port_sync_link = mv88e6xxx_port_sync_link, |
f365c6f7 | 4520 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
ef0a7318 | 4521 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 4522 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4523 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4524 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4525 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 4526 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 4527 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 4528 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 4529 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4530 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4531 | .port_get_cmode = mv88e6352_port_get_cmode, |
121b8fe2 | 4532 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 4533 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 4534 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
4535 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4536 | .stats_get_strings = mv88e6320_stats_get_strings, | |
052f947f | 4537 | .stats_get_stats = mv88e6320_stats_get_stats, |
fa8d1179 VD |
4538 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4539 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
9c7f37e5 | 4540 | .watchdog_ops = &mv88e6390_watchdog_ops, |
17e708ba | 4541 | .reset = mv88e6352_g1_reset, |
f1394b78 | 4542 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
0ad5daf6 | 4543 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
a73ccd61 | 4544 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 4545 | .avb_ops = &mv88e6352_avb_ops, |
6d2ac8ee | 4546 | .ptp_ops = &mv88e6352_ptp_ops, |
6c422e34 | 4547 | .phylink_validate = mv88e6185_phylink_validate, |
b3469dd8 VD |
4548 | }; |
4549 | ||
16e329ae VD |
4550 | static const struct mv88e6xxx_ops mv88e6341_ops = { |
4551 | /* MV88E6XXX_FAMILY_6341 */ | |
93e18d61 VD |
4552 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4553 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 4554 | .irl_init_all = mv88e6352_g2_irl_init_all, |
16e329ae VD |
4555 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4556 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
4557 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | |
4558 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
4559 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
4560 | .port_set_link = mv88e6xxx_port_set_link, | |
4efe7662 | 4561 | .port_sync_link = mv88e6xxx_port_sync_link, |
16e329ae | 4562 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
f365c6f7 | 4563 | .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, |
7cbbee05 | 4564 | .port_max_speed_mode = mv88e6341_port_max_speed_mode, |
16e329ae | 4565 | .port_tag_remap = mv88e6095_port_tag_remap, |
7da467d8 | 4566 | .port_set_policy = mv88e6352_port_set_policy, |
16e329ae | 4567 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4568 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4569 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
16e329ae | 4570 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 4571 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
16e329ae | 4572 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 4573 | .port_pause_limit = mv88e6097_port_pause_limit, |
16e329ae VD |
4574 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4575 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, | |
2d2e1dd2 | 4576 | .port_get_cmode = mv88e6352_port_get_cmode, |
7a3007d2 | 4577 | .port_set_cmode = mv88e6341_port_set_cmode, |
121b8fe2 | 4578 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
16e329ae | 4579 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
11527f3c | 4580 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
16e329ae VD |
4581 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4582 | .stats_get_strings = mv88e6320_stats_get_strings, | |
4583 | .stats_get_stats = mv88e6390_stats_get_stats, | |
fa8d1179 VD |
4584 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4585 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
16e329ae VD |
4586 | .watchdog_ops = &mv88e6390_watchdog_ops, |
4587 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, | |
9e907d73 | 4588 | .pot_clear = mv88e6xxx_g2_pot_clear, |
16e329ae | 4589 | .reset = mv88e6352_g1_reset, |
37094887 | 4590 | .rmu_disable = mv88e6390_g1_rmu_disable, |
c07fff34 MB |
4591 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4592 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 4593 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 4594 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
d3cf7d8f MB |
4595 | .serdes_power = mv88e6390_serdes_power, |
4596 | .serdes_get_lane = mv88e6341_serdes_get_lane, | |
a5a6858b RK |
4597 | /* Check status register pause & lpa register */ |
4598 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, | |
4599 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, | |
4600 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, | |
4601 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, | |
4241ef52 | 4602 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
61a46b41 | 4603 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
907b9b9f | 4604 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
a73ccd61 | 4605 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 4606 | .avb_ops = &mv88e6390_avb_ops, |
6d2ac8ee | 4607 | .ptp_ops = &mv88e6352_ptp_ops, |
a03b98d6 MB |
4608 | .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, |
4609 | .serdes_get_strings = mv88e6390_serdes_get_strings, | |
4610 | .serdes_get_stats = mv88e6390_serdes_get_stats, | |
953b0dcb MB |
4611 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4612 | .serdes_get_regs = mv88e6390_serdes_get_regs, | |
e3af71a3 | 4613 | .phylink_validate = mv88e6341_phylink_validate, |
16e329ae VD |
4614 | }; |
4615 | ||
b3469dd8 | 4616 | static const struct mv88e6xxx_ops mv88e6350_ops = { |
4b325d8c | 4617 | /* MV88E6XXX_FAMILY_6351 */ |
93e18d61 VD |
4618 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4619 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 4620 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 4621 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
4622 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
4623 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 4624 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 4625 | .port_sync_link = mv88e6xxx_port_sync_link, |
94d66ae6 | 4626 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
f365c6f7 | 4627 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
ef0a7318 | 4628 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 4629 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4630 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4631 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4632 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 4633 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 4634 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 4635 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 4636 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4637 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4638 | .port_get_cmode = mv88e6352_port_get_cmode, |
121b8fe2 | 4639 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 4640 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 4641 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
4642 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4643 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 4644 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
4645 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4646 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 4647 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 4648 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 4649 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4650 | .reset = mv88e6352_g1_reset, |
23e8b470 AL |
4651 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4652 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 4653 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 4654 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
6c422e34 | 4655 | .phylink_validate = mv88e6185_phylink_validate, |
b3469dd8 VD |
4656 | }; |
4657 | ||
4658 | static const struct mv88e6xxx_ops mv88e6351_ops = { | |
4b325d8c | 4659 | /* MV88E6XXX_FAMILY_6351 */ |
93e18d61 VD |
4660 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4661 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 4662 | .irl_init_all = mv88e6352_g2_irl_init_all, |
b073d4e2 | 4663 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
4664 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
4665 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 4666 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 4667 | .port_sync_link = mv88e6xxx_port_sync_link, |
94d66ae6 | 4668 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
f365c6f7 | 4669 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
ef0a7318 | 4670 | .port_tag_remap = mv88e6095_port_tag_remap, |
56995cbc | 4671 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4672 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4673 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4674 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 4675 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 4676 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 4677 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 4678 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4679 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4680 | .port_get_cmode = mv88e6352_port_get_cmode, |
121b8fe2 | 4681 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 4682 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 4683 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
4684 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4685 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 4686 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
4687 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4688 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 4689 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 4690 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 4691 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4692 | .reset = mv88e6352_g1_reset, |
23e8b470 AL |
4693 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4694 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 4695 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 4696 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
0d632c3d | 4697 | .avb_ops = &mv88e6352_avb_ops, |
6d2ac8ee | 4698 | .ptp_ops = &mv88e6352_ptp_ops, |
6c422e34 | 4699 | .phylink_validate = mv88e6185_phylink_validate, |
b3469dd8 VD |
4700 | }; |
4701 | ||
4702 | static const struct mv88e6xxx_ops mv88e6352_ops = { | |
4b325d8c | 4703 | /* MV88E6XXX_FAMILY_6352 */ |
93e18d61 VD |
4704 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4705 | .ip_pri_map = mv88e6085_g1_ip_pri_map, | |
cd8da8bb | 4706 | .irl_init_all = mv88e6352_g2_irl_init_all, |
ee4dc2e7 VD |
4707 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
4708 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, | |
b073d4e2 | 4709 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
b3469dd8 VD |
4710 | .phy_read = mv88e6xxx_g2_smi_phy_read, |
4711 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
08ef7f10 | 4712 | .port_set_link = mv88e6xxx_port_set_link, |
4efe7662 | 4713 | .port_sync_link = mv88e6xxx_port_sync_link, |
a0a0f622 | 4714 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
f365c6f7 | 4715 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
ef0a7318 | 4716 | .port_tag_remap = mv88e6095_port_tag_remap, |
f3a2cd32 | 4717 | .port_set_policy = mv88e6352_port_set_policy, |
56995cbc | 4718 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4719 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4720 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4721 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 4722 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 4723 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 4724 | .port_pause_limit = mv88e6097_port_pause_limit, |
c8c94891 | 4725 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4726 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4727 | .port_get_cmode = mv88e6352_port_get_cmode, |
121b8fe2 | 4728 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
a605a0fe | 4729 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
40cff8fc | 4730 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
dfafe449 AL |
4731 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4732 | .stats_get_strings = mv88e6095_stats_get_strings, | |
052f947f | 4733 | .stats_get_stats = mv88e6095_stats_get_stats, |
fa8d1179 VD |
4734 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4735 | .set_egress_port = mv88e6095_g1_set_egress_port, | |
fcd25166 | 4736 | .watchdog_ops = &mv88e6097_watchdog_ops, |
51c901a7 | 4737 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
9e907d73 | 4738 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4739 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 4740 | .rmu_disable = mv88e6352_g1_rmu_disable, |
23e8b470 AL |
4741 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4742 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
f1394b78 | 4743 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
0ad5daf6 | 4744 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
9db4a725 | 4745 | .serdes_get_lane = mv88e6352_serdes_get_lane, |
a5a6858b RK |
4746 | .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, |
4747 | .serdes_pcs_config = mv88e6352_serdes_pcs_config, | |
4748 | .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, | |
4749 | .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, | |
6d91782f | 4750 | .serdes_power = mv88e6352_serdes_power, |
4241ef52 | 4751 | .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, |
61a46b41 | 4752 | .serdes_irq_enable = mv88e6352_serdes_irq_enable, |
907b9b9f | 4753 | .serdes_irq_status = mv88e6352_serdes_irq_status, |
a73ccd61 | 4754 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 4755 | .avb_ops = &mv88e6352_avb_ops, |
6d2ac8ee | 4756 | .ptp_ops = &mv88e6352_ptp_ops, |
cda9f4aa AL |
4757 | .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, |
4758 | .serdes_get_strings = mv88e6352_serdes_get_strings, | |
4759 | .serdes_get_stats = mv88e6352_serdes_get_stats, | |
d3f88a24 AL |
4760 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
4761 | .serdes_get_regs = mv88e6352_serdes_get_regs, | |
6c422e34 | 4762 | .phylink_validate = mv88e6352_phylink_validate, |
b3469dd8 VD |
4763 | }; |
4764 | ||
1a3b39ec | 4765 | static const struct mv88e6xxx_ops mv88e6390_ops = { |
4b325d8c | 4766 | /* MV88E6XXX_FAMILY_6390 */ |
ea89098e | 4767 | .setup_errata = mv88e6390_setup_errata, |
cd8da8bb | 4768 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
4769 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4770 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
4771 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4772 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
4773 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
4774 | .port_set_link = mv88e6xxx_port_set_link, | |
4efe7662 | 4775 | .port_sync_link = mv88e6xxx_port_sync_link, |
1a3b39ec | 4776 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
f365c6f7 | 4777 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
7cbbee05 | 4778 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
ef0a7318 | 4779 | .port_tag_remap = mv88e6390_port_tag_remap, |
f3a2cd32 | 4780 | .port_set_policy = mv88e6352_port_set_policy, |
56995cbc | 4781 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4782 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4783 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4784 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 4785 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 4786 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 4787 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 4788 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4789 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4790 | .port_get_cmode = mv88e6352_port_get_cmode, |
fdc71eea | 4791 | .port_set_cmode = mv88e6390_port_set_cmode, |
121b8fe2 | 4792 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
79523473 | 4793 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 4794 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
4795 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4796 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 4797 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
4798 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4799 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 4800 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 4801 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 4802 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4803 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 4804 | .rmu_disable = mv88e6390_g1_rmu_disable, |
23e8b470 AL |
4805 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4806 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
931d1822 VD |
4807 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
4808 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
6335e9f2 | 4809 | .serdes_power = mv88e6390_serdes_power, |
17deaf5c | 4810 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
a5a6858b RK |
4811 | /* Check status register pause & lpa register */ |
4812 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, | |
4813 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, | |
4814 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, | |
4815 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, | |
4241ef52 | 4816 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
61a46b41 | 4817 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
907b9b9f | 4818 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
a73ccd61 | 4819 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 4820 | .avb_ops = &mv88e6390_avb_ops, |
6d2ac8ee | 4821 | .ptp_ops = &mv88e6352_ptp_ops, |
0df95287 NY |
4822 | .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, |
4823 | .serdes_get_strings = mv88e6390_serdes_get_strings, | |
4824 | .serdes_get_stats = mv88e6390_serdes_get_stats, | |
bf3504ce AL |
4825 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4826 | .serdes_get_regs = mv88e6390_serdes_get_regs, | |
6c422e34 | 4827 | .phylink_validate = mv88e6390_phylink_validate, |
1a3b39ec AL |
4828 | }; |
4829 | ||
4830 | static const struct mv88e6xxx_ops mv88e6390x_ops = { | |
4b325d8c | 4831 | /* MV88E6XXX_FAMILY_6390 */ |
ea89098e | 4832 | .setup_errata = mv88e6390_setup_errata, |
cd8da8bb | 4833 | .irl_init_all = mv88e6390_g2_irl_init_all, |
98fc3c6f VD |
4834 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4835 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
1a3b39ec AL |
4836 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4837 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
4838 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
4839 | .port_set_link = mv88e6xxx_port_set_link, | |
4efe7662 | 4840 | .port_sync_link = mv88e6xxx_port_sync_link, |
1a3b39ec | 4841 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
f365c6f7 | 4842 | .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, |
7cbbee05 | 4843 | .port_max_speed_mode = mv88e6390x_port_max_speed_mode, |
ef0a7318 | 4844 | .port_tag_remap = mv88e6390_port_tag_remap, |
f3a2cd32 | 4845 | .port_set_policy = mv88e6352_port_set_policy, |
56995cbc | 4846 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
a8b659e7 VO |
4847 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4848 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
56995cbc | 4849 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
cd782656 | 4850 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
ef70b111 | 4851 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
0898432c | 4852 | .port_pause_limit = mv88e6390_port_pause_limit, |
c8c94891 | 4853 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
9dbfb4e1 | 4854 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
2d2e1dd2 | 4855 | .port_get_cmode = mv88e6352_port_get_cmode, |
b3dce4da | 4856 | .port_set_cmode = mv88e6390x_port_set_cmode, |
121b8fe2 | 4857 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
79523473 | 4858 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
de227387 | 4859 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
dfafe449 AL |
4860 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4861 | .stats_get_strings = mv88e6320_stats_get_strings, | |
e0d8b615 | 4862 | .stats_get_stats = mv88e6390_stats_get_stats, |
fa8d1179 VD |
4863 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4864 | .set_egress_port = mv88e6390_g1_set_egress_port, | |
61303736 | 4865 | .watchdog_ops = &mv88e6390_watchdog_ops, |
6e55f698 | 4866 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
9e907d73 | 4867 | .pot_clear = mv88e6xxx_g2_pot_clear, |
17e708ba | 4868 | .reset = mv88e6352_g1_reset, |
9e5baf9b | 4869 | .rmu_disable = mv88e6390_g1_rmu_disable, |
23e8b470 AL |
4870 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4871 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
931d1822 VD |
4872 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
4873 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
d3cf7d8f | 4874 | .serdes_power = mv88e6390_serdes_power, |
17deaf5c | 4875 | .serdes_get_lane = mv88e6390x_serdes_get_lane, |
a5a6858b RK |
4876 | .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, |
4877 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, | |
4878 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, | |
4879 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, | |
4241ef52 | 4880 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
61a46b41 | 4881 | .serdes_irq_enable = mv88e6390_serdes_irq_enable, |
907b9b9f | 4882 | .serdes_irq_status = mv88e6390_serdes_irq_status, |
4262c38d AL |
4883 | .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, |
4884 | .serdes_get_strings = mv88e6390_serdes_get_strings, | |
4885 | .serdes_get_stats = mv88e6390_serdes_get_stats, | |
bf3504ce AL |
4886 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4887 | .serdes_get_regs = mv88e6390_serdes_get_regs, | |
a73ccd61 | 4888 | .gpio_ops = &mv88e6352_gpio_ops, |
0d632c3d | 4889 | .avb_ops = &mv88e6390_avb_ops, |
6d2ac8ee | 4890 | .ptp_ops = &mv88e6352_ptp_ops, |
6c422e34 | 4891 | .phylink_validate = mv88e6390x_phylink_validate, |
1a3b39ec AL |
4892 | }; |
4893 | ||
de776d0d PS |
4894 | static const struct mv88e6xxx_ops mv88e6393x_ops = { |
4895 | /* MV88E6XXX_FAMILY_6393 */ | |
4896 | .setup_errata = mv88e6393x_serdes_setup_errata, | |
4897 | .irl_init_all = mv88e6390_g2_irl_init_all, | |
4898 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, | |
4899 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, | |
4900 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, | |
4901 | .phy_read = mv88e6xxx_g2_smi_phy_read, | |
4902 | .phy_write = mv88e6xxx_g2_smi_phy_write, | |
4903 | .port_set_link = mv88e6xxx_port_set_link, | |
4904 | .port_sync_link = mv88e6xxx_port_sync_link, | |
4905 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, | |
4906 | .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, | |
4907 | .port_max_speed_mode = mv88e6393x_port_max_speed_mode, | |
4908 | .port_tag_remap = mv88e6390_port_tag_remap, | |
6584b260 | 4909 | .port_set_policy = mv88e6393x_port_set_policy, |
de776d0d PS |
4910 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4911 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, | |
4912 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, | |
4913 | .port_set_ether_type = mv88e6393x_port_set_ether_type, | |
4914 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, | |
4915 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, | |
4916 | .port_pause_limit = mv88e6390_port_pause_limit, | |
4917 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, | |
4918 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, | |
4919 | .port_get_cmode = mv88e6352_port_get_cmode, | |
4920 | .port_set_cmode = mv88e6393x_port_set_cmode, | |
4921 | .port_setup_message_port = mv88e6xxx_setup_message_port, | |
4922 | .port_set_upstream_port = mv88e6393x_port_set_upstream_port, | |
4923 | .stats_snapshot = mv88e6390_g1_stats_snapshot, | |
4924 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, | |
4925 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, | |
4926 | .stats_get_strings = mv88e6320_stats_get_strings, | |
4927 | .stats_get_stats = mv88e6390_stats_get_stats, | |
4928 | /* .set_cpu_port is missing because this family does not support a global | |
4929 | * CPU port, only per port CPU port which is set via | |
4930 | * .port_set_upstream_port method. | |
4931 | */ | |
4932 | .set_egress_port = mv88e6393x_set_egress_port, | |
4933 | .watchdog_ops = &mv88e6390_watchdog_ops, | |
4934 | .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, | |
4935 | .pot_clear = mv88e6xxx_g2_pot_clear, | |
4936 | .reset = mv88e6352_g1_reset, | |
4937 | .rmu_disable = mv88e6390_g1_rmu_disable, | |
4938 | .atu_get_hash = mv88e6165_g1_atu_get_hash, | |
4939 | .atu_set_hash = mv88e6165_g1_atu_set_hash, | |
4940 | .vtu_getnext = mv88e6390_g1_vtu_getnext, | |
4941 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, | |
4942 | .serdes_power = mv88e6393x_serdes_power, | |
4943 | .serdes_get_lane = mv88e6393x_serdes_get_lane, | |
4944 | .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, | |
4945 | .serdes_pcs_config = mv88e6390_serdes_pcs_config, | |
4946 | .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, | |
4947 | .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, | |
4948 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, | |
4949 | .serdes_irq_enable = mv88e6393x_serdes_irq_enable, | |
4950 | .serdes_irq_status = mv88e6393x_serdes_irq_status, | |
4951 | /* TODO: serdes stats */ | |
4952 | .gpio_ops = &mv88e6352_gpio_ops, | |
4953 | .avb_ops = &mv88e6390_avb_ops, | |
4954 | .ptp_ops = &mv88e6352_ptp_ops, | |
4955 | .phylink_validate = mv88e6393x_phylink_validate, | |
4956 | }; | |
4957 | ||
f81ec90f VD |
4958 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
4959 | [MV88E6085] = { | |
107fcc10 | 4960 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, |
f81ec90f VD |
4961 | .family = MV88E6XXX_FAMILY_6097, |
4962 | .name = "Marvell 88E6085", | |
4963 | .num_databases = 4096, | |
d9ea5620 | 4964 | .num_macs = 8192, |
f81ec90f | 4965 | .num_ports = 10, |
bc393155 | 4966 | .num_internal_phys = 5, |
3cf3c846 | 4967 | .max_vid = 4095, |
9dddd478 | 4968 | .port_base_addr = 0x10, |
9255bacd | 4969 | .phy_base_addr = 0x0, |
a935c052 | 4970 | .global1_addr = 0x1b, |
9069c13a | 4971 | .global2_addr = 0x1c, |
acddbd21 | 4972 | .age_time_coeff = 15000, |
dc30c35b | 4973 | .g1_irqs = 8, |
d6c5e6af | 4974 | .g2_irqs = 10, |
e606ca36 | 4975 | .atu_move_port_mask = 0xf, |
f3645652 | 4976 | .pvt = true, |
b3e05aa1 | 4977 | .multi_chip = true, |
b3469dd8 | 4978 | .ops = &mv88e6085_ops, |
f81ec90f VD |
4979 | }, |
4980 | ||
4981 | [MV88E6095] = { | |
107fcc10 | 4982 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, |
f81ec90f VD |
4983 | .family = MV88E6XXX_FAMILY_6095, |
4984 | .name = "Marvell 88E6095/88E6095F", | |
4985 | .num_databases = 256, | |
d9ea5620 | 4986 | .num_macs = 8192, |
f81ec90f | 4987 | .num_ports = 11, |
bc393155 | 4988 | .num_internal_phys = 0, |
3cf3c846 | 4989 | .max_vid = 4095, |
9dddd478 | 4990 | .port_base_addr = 0x10, |
9255bacd | 4991 | .phy_base_addr = 0x0, |
a935c052 | 4992 | .global1_addr = 0x1b, |
9069c13a | 4993 | .global2_addr = 0x1c, |
acddbd21 | 4994 | .age_time_coeff = 15000, |
dc30c35b | 4995 | .g1_irqs = 8, |
e606ca36 | 4996 | .atu_move_port_mask = 0xf, |
b3e05aa1 | 4997 | .multi_chip = true, |
b3469dd8 | 4998 | .ops = &mv88e6095_ops, |
f81ec90f VD |
4999 | }, |
5000 | ||
7d381a02 | 5001 | [MV88E6097] = { |
107fcc10 | 5002 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, |
7d381a02 SE |
5003 | .family = MV88E6XXX_FAMILY_6097, |
5004 | .name = "Marvell 88E6097/88E6097F", | |
5005 | .num_databases = 4096, | |
d9ea5620 | 5006 | .num_macs = 8192, |
7d381a02 | 5007 | .num_ports = 11, |
bc393155 | 5008 | .num_internal_phys = 8, |
3cf3c846 | 5009 | .max_vid = 4095, |
7d381a02 | 5010 | .port_base_addr = 0x10, |
9255bacd | 5011 | .phy_base_addr = 0x0, |
7d381a02 | 5012 | .global1_addr = 0x1b, |
9069c13a | 5013 | .global2_addr = 0x1c, |
7d381a02 | 5014 | .age_time_coeff = 15000, |
c534178b | 5015 | .g1_irqs = 8, |
d6c5e6af | 5016 | .g2_irqs = 10, |
e606ca36 | 5017 | .atu_move_port_mask = 0xf, |
f3645652 | 5018 | .pvt = true, |
b3e05aa1 | 5019 | .multi_chip = true, |
670bb80f | 5020 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
7d381a02 SE |
5021 | .ops = &mv88e6097_ops, |
5022 | }, | |
5023 | ||
f81ec90f | 5024 | [MV88E6123] = { |
107fcc10 | 5025 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, |
f81ec90f VD |
5026 | .family = MV88E6XXX_FAMILY_6165, |
5027 | .name = "Marvell 88E6123", | |
5028 | .num_databases = 4096, | |
d9ea5620 | 5029 | .num_macs = 1024, |
f81ec90f | 5030 | .num_ports = 3, |
bc393155 | 5031 | .num_internal_phys = 5, |
3cf3c846 | 5032 | .max_vid = 4095, |
9dddd478 | 5033 | .port_base_addr = 0x10, |
9255bacd | 5034 | .phy_base_addr = 0x0, |
a935c052 | 5035 | .global1_addr = 0x1b, |
9069c13a | 5036 | .global2_addr = 0x1c, |
acddbd21 | 5037 | .age_time_coeff = 15000, |
dc30c35b | 5038 | .g1_irqs = 9, |
d6c5e6af | 5039 | .g2_irqs = 10, |
e606ca36 | 5040 | .atu_move_port_mask = 0xf, |
f3645652 | 5041 | .pvt = true, |
b3e05aa1 | 5042 | .multi_chip = true, |
670bb80f | 5043 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
b3469dd8 | 5044 | .ops = &mv88e6123_ops, |
f81ec90f VD |
5045 | }, |
5046 | ||
5047 | [MV88E6131] = { | |
107fcc10 | 5048 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, |
f81ec90f VD |
5049 | .family = MV88E6XXX_FAMILY_6185, |
5050 | .name = "Marvell 88E6131", | |
5051 | .num_databases = 256, | |
d9ea5620 | 5052 | .num_macs = 8192, |
f81ec90f | 5053 | .num_ports = 8, |
bc393155 | 5054 | .num_internal_phys = 0, |
3cf3c846 | 5055 | .max_vid = 4095, |
9dddd478 | 5056 | .port_base_addr = 0x10, |
9255bacd | 5057 | .phy_base_addr = 0x0, |
a935c052 | 5058 | .global1_addr = 0x1b, |
9069c13a | 5059 | .global2_addr = 0x1c, |
acddbd21 | 5060 | .age_time_coeff = 15000, |
dc30c35b | 5061 | .g1_irqs = 9, |
e606ca36 | 5062 | .atu_move_port_mask = 0xf, |
b3e05aa1 | 5063 | .multi_chip = true, |
b3469dd8 | 5064 | .ops = &mv88e6131_ops, |
f81ec90f VD |
5065 | }, |
5066 | ||
990e27b0 | 5067 | [MV88E6141] = { |
107fcc10 | 5068 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, |
990e27b0 | 5069 | .family = MV88E6XXX_FAMILY_6341, |
79a68b26 | 5070 | .name = "Marvell 88E6141", |
990e27b0 | 5071 | .num_databases = 4096, |
d9ea5620 | 5072 | .num_macs = 2048, |
990e27b0 | 5073 | .num_ports = 6, |
bc393155 | 5074 | .num_internal_phys = 5, |
a73ccd61 | 5075 | .num_gpio = 11, |
3cf3c846 | 5076 | .max_vid = 4095, |
990e27b0 | 5077 | .port_base_addr = 0x10, |
9255bacd | 5078 | .phy_base_addr = 0x10, |
990e27b0 | 5079 | .global1_addr = 0x1b, |
9069c13a | 5080 | .global2_addr = 0x1c, |
990e27b0 VD |
5081 | .age_time_coeff = 3750, |
5082 | .atu_move_port_mask = 0x1f, | |
adfccf11 | 5083 | .g1_irqs = 9, |
d6c5e6af | 5084 | .g2_irqs = 10, |
f3645652 | 5085 | .pvt = true, |
b3e05aa1 | 5086 | .multi_chip = true, |
670bb80f | 5087 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
990e27b0 VD |
5088 | .ops = &mv88e6141_ops, |
5089 | }, | |
5090 | ||
f81ec90f | 5091 | [MV88E6161] = { |
107fcc10 | 5092 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, |
f81ec90f VD |
5093 | .family = MV88E6XXX_FAMILY_6165, |
5094 | .name = "Marvell 88E6161", | |
5095 | .num_databases = 4096, | |
d9ea5620 | 5096 | .num_macs = 1024, |
f81ec90f | 5097 | .num_ports = 6, |
bc393155 | 5098 | .num_internal_phys = 5, |
3cf3c846 | 5099 | .max_vid = 4095, |
9dddd478 | 5100 | .port_base_addr = 0x10, |
9255bacd | 5101 | .phy_base_addr = 0x0, |
a935c052 | 5102 | .global1_addr = 0x1b, |
9069c13a | 5103 | .global2_addr = 0x1c, |
acddbd21 | 5104 | .age_time_coeff = 15000, |
dc30c35b | 5105 | .g1_irqs = 9, |
d6c5e6af | 5106 | .g2_irqs = 10, |
e606ca36 | 5107 | .atu_move_port_mask = 0xf, |
f3645652 | 5108 | .pvt = true, |
b3e05aa1 | 5109 | .multi_chip = true, |
670bb80f | 5110 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
dfa54348 | 5111 | .ptp_support = true, |
b3469dd8 | 5112 | .ops = &mv88e6161_ops, |
f81ec90f VD |
5113 | }, |
5114 | ||
5115 | [MV88E6165] = { | |
107fcc10 | 5116 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, |
f81ec90f VD |
5117 | .family = MV88E6XXX_FAMILY_6165, |
5118 | .name = "Marvell 88E6165", | |
5119 | .num_databases = 4096, | |
d9ea5620 | 5120 | .num_macs = 8192, |
f81ec90f | 5121 | .num_ports = 6, |
bc393155 | 5122 | .num_internal_phys = 0, |
3cf3c846 | 5123 | .max_vid = 4095, |
9dddd478 | 5124 | .port_base_addr = 0x10, |
9255bacd | 5125 | .phy_base_addr = 0x0, |
a935c052 | 5126 | .global1_addr = 0x1b, |
9069c13a | 5127 | .global2_addr = 0x1c, |
acddbd21 | 5128 | .age_time_coeff = 15000, |
dc30c35b | 5129 | .g1_irqs = 9, |
d6c5e6af | 5130 | .g2_irqs = 10, |
e606ca36 | 5131 | .atu_move_port_mask = 0xf, |
f3645652 | 5132 | .pvt = true, |
b3e05aa1 | 5133 | .multi_chip = true, |
dfa54348 | 5134 | .ptp_support = true, |
b3469dd8 | 5135 | .ops = &mv88e6165_ops, |
f81ec90f VD |
5136 | }, |
5137 | ||
5138 | [MV88E6171] = { | |
107fcc10 | 5139 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, |
f81ec90f VD |
5140 | .family = MV88E6XXX_FAMILY_6351, |
5141 | .name = "Marvell 88E6171", | |
5142 | .num_databases = 4096, | |
d9ea5620 | 5143 | .num_macs = 8192, |
f81ec90f | 5144 | .num_ports = 7, |
bc393155 | 5145 | .num_internal_phys = 5, |
3cf3c846 | 5146 | .max_vid = 4095, |
9dddd478 | 5147 | .port_base_addr = 0x10, |
9255bacd | 5148 | .phy_base_addr = 0x0, |
a935c052 | 5149 | .global1_addr = 0x1b, |
9069c13a | 5150 | .global2_addr = 0x1c, |
acddbd21 | 5151 | .age_time_coeff = 15000, |
dc30c35b | 5152 | .g1_irqs = 9, |
d6c5e6af | 5153 | .g2_irqs = 10, |
e606ca36 | 5154 | .atu_move_port_mask = 0xf, |
f3645652 | 5155 | .pvt = true, |
b3e05aa1 | 5156 | .multi_chip = true, |
670bb80f | 5157 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
b3469dd8 | 5158 | .ops = &mv88e6171_ops, |
f81ec90f VD |
5159 | }, |
5160 | ||
5161 | [MV88E6172] = { | |
107fcc10 | 5162 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, |
f81ec90f VD |
5163 | .family = MV88E6XXX_FAMILY_6352, |
5164 | .name = "Marvell 88E6172", | |
5165 | .num_databases = 4096, | |
d9ea5620 | 5166 | .num_macs = 8192, |
f81ec90f | 5167 | .num_ports = 7, |
bc393155 | 5168 | .num_internal_phys = 5, |
a73ccd61 | 5169 | .num_gpio = 15, |
3cf3c846 | 5170 | .max_vid = 4095, |
9dddd478 | 5171 | .port_base_addr = 0x10, |
9255bacd | 5172 | .phy_base_addr = 0x0, |
a935c052 | 5173 | .global1_addr = 0x1b, |
9069c13a | 5174 | .global2_addr = 0x1c, |
acddbd21 | 5175 | .age_time_coeff = 15000, |
dc30c35b | 5176 | .g1_irqs = 9, |
d6c5e6af | 5177 | .g2_irqs = 10, |
e606ca36 | 5178 | .atu_move_port_mask = 0xf, |
f3645652 | 5179 | .pvt = true, |
b3e05aa1 | 5180 | .multi_chip = true, |
670bb80f | 5181 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
b3469dd8 | 5182 | .ops = &mv88e6172_ops, |
f81ec90f VD |
5183 | }, |
5184 | ||
5185 | [MV88E6175] = { | |
107fcc10 | 5186 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, |
f81ec90f VD |
5187 | .family = MV88E6XXX_FAMILY_6351, |
5188 | .name = "Marvell 88E6175", | |
5189 | .num_databases = 4096, | |
d9ea5620 | 5190 | .num_macs = 8192, |
f81ec90f | 5191 | .num_ports = 7, |
bc393155 | 5192 | .num_internal_phys = 5, |
3cf3c846 | 5193 | .max_vid = 4095, |
9dddd478 | 5194 | .port_base_addr = 0x10, |
9255bacd | 5195 | .phy_base_addr = 0x0, |
a935c052 | 5196 | .global1_addr = 0x1b, |
9069c13a | 5197 | .global2_addr = 0x1c, |
acddbd21 | 5198 | .age_time_coeff = 15000, |
dc30c35b | 5199 | .g1_irqs = 9, |
d6c5e6af | 5200 | .g2_irqs = 10, |
e606ca36 | 5201 | .atu_move_port_mask = 0xf, |
f3645652 | 5202 | .pvt = true, |
b3e05aa1 | 5203 | .multi_chip = true, |
670bb80f | 5204 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
b3469dd8 | 5205 | .ops = &mv88e6175_ops, |
f81ec90f VD |
5206 | }, |
5207 | ||
5208 | [MV88E6176] = { | |
107fcc10 | 5209 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, |
f81ec90f VD |
5210 | .family = MV88E6XXX_FAMILY_6352, |
5211 | .name = "Marvell 88E6176", | |
5212 | .num_databases = 4096, | |
d9ea5620 | 5213 | .num_macs = 8192, |
f81ec90f | 5214 | .num_ports = 7, |
bc393155 | 5215 | .num_internal_phys = 5, |
a73ccd61 | 5216 | .num_gpio = 15, |
3cf3c846 | 5217 | .max_vid = 4095, |
9dddd478 | 5218 | .port_base_addr = 0x10, |
9255bacd | 5219 | .phy_base_addr = 0x0, |
a935c052 | 5220 | .global1_addr = 0x1b, |
9069c13a | 5221 | .global2_addr = 0x1c, |
acddbd21 | 5222 | .age_time_coeff = 15000, |
dc30c35b | 5223 | .g1_irqs = 9, |
d6c5e6af | 5224 | .g2_irqs = 10, |
e606ca36 | 5225 | .atu_move_port_mask = 0xf, |
f3645652 | 5226 | .pvt = true, |
b3e05aa1 | 5227 | .multi_chip = true, |
670bb80f | 5228 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
b3469dd8 | 5229 | .ops = &mv88e6176_ops, |
f81ec90f VD |
5230 | }, |
5231 | ||
5232 | [MV88E6185] = { | |
107fcc10 | 5233 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, |
f81ec90f VD |
5234 | .family = MV88E6XXX_FAMILY_6185, |
5235 | .name = "Marvell 88E6185", | |
5236 | .num_databases = 256, | |
d9ea5620 | 5237 | .num_macs = 8192, |
f81ec90f | 5238 | .num_ports = 10, |
bc393155 | 5239 | .num_internal_phys = 0, |
3cf3c846 | 5240 | .max_vid = 4095, |
9dddd478 | 5241 | .port_base_addr = 0x10, |
9255bacd | 5242 | .phy_base_addr = 0x0, |
a935c052 | 5243 | .global1_addr = 0x1b, |
9069c13a | 5244 | .global2_addr = 0x1c, |
acddbd21 | 5245 | .age_time_coeff = 15000, |
dc30c35b | 5246 | .g1_irqs = 8, |
e606ca36 | 5247 | .atu_move_port_mask = 0xf, |
b3e05aa1 | 5248 | .multi_chip = true, |
670bb80f | 5249 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
b3469dd8 | 5250 | .ops = &mv88e6185_ops, |
f81ec90f VD |
5251 | }, |
5252 | ||
1a3b39ec | 5253 | [MV88E6190] = { |
107fcc10 | 5254 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, |
1a3b39ec AL |
5255 | .family = MV88E6XXX_FAMILY_6390, |
5256 | .name = "Marvell 88E6190", | |
5257 | .num_databases = 4096, | |
d9ea5620 | 5258 | .num_macs = 16384, |
1a3b39ec | 5259 | .num_ports = 11, /* 10 + Z80 */ |
95150f29 | 5260 | .num_internal_phys = 9, |
a73ccd61 | 5261 | .num_gpio = 16, |
931d1822 | 5262 | .max_vid = 8191, |
1a3b39ec | 5263 | .port_base_addr = 0x0, |
9255bacd | 5264 | .phy_base_addr = 0x0, |
1a3b39ec | 5265 | .global1_addr = 0x1b, |
9069c13a | 5266 | .global2_addr = 0x1c, |
b91e055c | 5267 | .age_time_coeff = 3750, |
1a3b39ec | 5268 | .g1_irqs = 9, |
d6c5e6af | 5269 | .g2_irqs = 14, |
f3645652 | 5270 | .pvt = true, |
b3e05aa1 | 5271 | .multi_chip = true, |
e606ca36 | 5272 | .atu_move_port_mask = 0x1f, |
1a3b39ec AL |
5273 | .ops = &mv88e6190_ops, |
5274 | }, | |
5275 | ||
5276 | [MV88E6190X] = { | |
107fcc10 | 5277 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, |
1a3b39ec AL |
5278 | .family = MV88E6XXX_FAMILY_6390, |
5279 | .name = "Marvell 88E6190X", | |
5280 | .num_databases = 4096, | |
d9ea5620 | 5281 | .num_macs = 16384, |
1a3b39ec | 5282 | .num_ports = 11, /* 10 + Z80 */ |
95150f29 | 5283 | .num_internal_phys = 9, |
a73ccd61 | 5284 | .num_gpio = 16, |
931d1822 | 5285 | .max_vid = 8191, |
1a3b39ec | 5286 | .port_base_addr = 0x0, |
9255bacd | 5287 | .phy_base_addr = 0x0, |
1a3b39ec | 5288 | .global1_addr = 0x1b, |
9069c13a | 5289 | .global2_addr = 0x1c, |
b91e055c | 5290 | .age_time_coeff = 3750, |
1a3b39ec | 5291 | .g1_irqs = 9, |
d6c5e6af | 5292 | .g2_irqs = 14, |
e606ca36 | 5293 | .atu_move_port_mask = 0x1f, |
f3645652 | 5294 | .pvt = true, |
b3e05aa1 | 5295 | .multi_chip = true, |
1a3b39ec AL |
5296 | .ops = &mv88e6190x_ops, |
5297 | }, | |
5298 | ||
5299 | [MV88E6191] = { | |
107fcc10 | 5300 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, |
1a3b39ec AL |
5301 | .family = MV88E6XXX_FAMILY_6390, |
5302 | .name = "Marvell 88E6191", | |
5303 | .num_databases = 4096, | |
d9ea5620 | 5304 | .num_macs = 16384, |
1a3b39ec | 5305 | .num_ports = 11, /* 10 + Z80 */ |
95150f29 | 5306 | .num_internal_phys = 9, |
931d1822 | 5307 | .max_vid = 8191, |
1a3b39ec | 5308 | .port_base_addr = 0x0, |
9255bacd | 5309 | .phy_base_addr = 0x0, |
1a3b39ec | 5310 | .global1_addr = 0x1b, |
9069c13a | 5311 | .global2_addr = 0x1c, |
b91e055c | 5312 | .age_time_coeff = 3750, |
443d5a1b | 5313 | .g1_irqs = 9, |
d6c5e6af | 5314 | .g2_irqs = 14, |
e606ca36 | 5315 | .atu_move_port_mask = 0x1f, |
f3645652 | 5316 | .pvt = true, |
b3e05aa1 | 5317 | .multi_chip = true, |
2fa8d3af | 5318 | .ptp_support = true, |
2cf4cefb | 5319 | .ops = &mv88e6191_ops, |
1a3b39ec AL |
5320 | }, |
5321 | ||
de776d0d PS |
5322 | [MV88E6191X] = { |
5323 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, | |
5324 | .family = MV88E6XXX_FAMILY_6393, | |
5325 | .name = "Marvell 88E6191X", | |
5326 | .num_databases = 4096, | |
5327 | .num_ports = 11, /* 10 + Z80 */ | |
5328 | .num_internal_phys = 9, | |
5329 | .max_vid = 8191, | |
5330 | .port_base_addr = 0x0, | |
5331 | .phy_base_addr = 0x0, | |
5332 | .global1_addr = 0x1b, | |
5333 | .global2_addr = 0x1c, | |
5334 | .age_time_coeff = 3750, | |
5335 | .g1_irqs = 10, | |
5336 | .g2_irqs = 14, | |
5337 | .atu_move_port_mask = 0x1f, | |
5338 | .pvt = true, | |
5339 | .multi_chip = true, | |
de776d0d PS |
5340 | .ptp_support = true, |
5341 | .ops = &mv88e6393x_ops, | |
5342 | }, | |
5343 | ||
5344 | [MV88E6193X] = { | |
5345 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, | |
5346 | .family = MV88E6XXX_FAMILY_6393, | |
5347 | .name = "Marvell 88E6193X", | |
5348 | .num_databases = 4096, | |
5349 | .num_ports = 11, /* 10 + Z80 */ | |
5350 | .num_internal_phys = 9, | |
5351 | .max_vid = 8191, | |
5352 | .port_base_addr = 0x0, | |
5353 | .phy_base_addr = 0x0, | |
5354 | .global1_addr = 0x1b, | |
5355 | .global2_addr = 0x1c, | |
5356 | .age_time_coeff = 3750, | |
5357 | .g1_irqs = 10, | |
5358 | .g2_irqs = 14, | |
5359 | .atu_move_port_mask = 0x1f, | |
5360 | .pvt = true, | |
5361 | .multi_chip = true, | |
de776d0d PS |
5362 | .ptp_support = true, |
5363 | .ops = &mv88e6393x_ops, | |
5364 | }, | |
5365 | ||
49022647 HF |
5366 | [MV88E6220] = { |
5367 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, | |
5368 | .family = MV88E6XXX_FAMILY_6250, | |
5369 | .name = "Marvell 88E6220", | |
5370 | .num_databases = 64, | |
5371 | ||
5372 | /* Ports 2-4 are not routed to pins | |
5373 | * => usable ports 0, 1, 5, 6 | |
5374 | */ | |
5375 | .num_ports = 7, | |
5376 | .num_internal_phys = 2, | |
c857486a | 5377 | .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), |
49022647 HF |
5378 | .max_vid = 4095, |
5379 | .port_base_addr = 0x08, | |
5380 | .phy_base_addr = 0x00, | |
5381 | .global1_addr = 0x0f, | |
5382 | .global2_addr = 0x07, | |
5383 | .age_time_coeff = 15000, | |
5384 | .g1_irqs = 9, | |
5385 | .g2_irqs = 10, | |
5386 | .atu_move_port_mask = 0xf, | |
5387 | .dual_chip = true, | |
71509614 | 5388 | .ptp_support = true, |
49022647 HF |
5389 | .ops = &mv88e6250_ops, |
5390 | }, | |
5391 | ||
f81ec90f | 5392 | [MV88E6240] = { |
107fcc10 | 5393 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, |
f81ec90f VD |
5394 | .family = MV88E6XXX_FAMILY_6352, |
5395 | .name = "Marvell 88E6240", | |
5396 | .num_databases = 4096, | |
d9ea5620 | 5397 | .num_macs = 8192, |
f81ec90f | 5398 | .num_ports = 7, |
bc393155 | 5399 | .num_internal_phys = 5, |
a73ccd61 | 5400 | .num_gpio = 15, |
3cf3c846 | 5401 | .max_vid = 4095, |
9dddd478 | 5402 | .port_base_addr = 0x10, |
9255bacd | 5403 | .phy_base_addr = 0x0, |
a935c052 | 5404 | .global1_addr = 0x1b, |
9069c13a | 5405 | .global2_addr = 0x1c, |
acddbd21 | 5406 | .age_time_coeff = 15000, |
dc30c35b | 5407 | .g1_irqs = 9, |
d6c5e6af | 5408 | .g2_irqs = 10, |
e606ca36 | 5409 | .atu_move_port_mask = 0xf, |
f3645652 | 5410 | .pvt = true, |
b3e05aa1 | 5411 | .multi_chip = true, |
670bb80f | 5412 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
2fa8d3af | 5413 | .ptp_support = true, |
b3469dd8 | 5414 | .ops = &mv88e6240_ops, |
f81ec90f VD |
5415 | }, |
5416 | ||
1f71836f RV |
5417 | [MV88E6250] = { |
5418 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, | |
5419 | .family = MV88E6XXX_FAMILY_6250, | |
5420 | .name = "Marvell 88E6250", | |
5421 | .num_databases = 64, | |
5422 | .num_ports = 7, | |
5423 | .num_internal_phys = 5, | |
5424 | .max_vid = 4095, | |
5425 | .port_base_addr = 0x08, | |
5426 | .phy_base_addr = 0x00, | |
5427 | .global1_addr = 0x0f, | |
5428 | .global2_addr = 0x07, | |
5429 | .age_time_coeff = 15000, | |
5430 | .g1_irqs = 9, | |
5431 | .g2_irqs = 10, | |
5432 | .atu_move_port_mask = 0xf, | |
5433 | .dual_chip = true, | |
71509614 | 5434 | .ptp_support = true, |
1f71836f RV |
5435 | .ops = &mv88e6250_ops, |
5436 | }, | |
5437 | ||
1a3b39ec | 5438 | [MV88E6290] = { |
107fcc10 | 5439 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, |
1a3b39ec AL |
5440 | .family = MV88E6XXX_FAMILY_6390, |
5441 | .name = "Marvell 88E6290", | |
5442 | .num_databases = 4096, | |
5443 | .num_ports = 11, /* 10 + Z80 */ | |
95150f29 | 5444 | .num_internal_phys = 9, |
a73ccd61 | 5445 | .num_gpio = 16, |
931d1822 | 5446 | .max_vid = 8191, |
1a3b39ec | 5447 | .port_base_addr = 0x0, |
9255bacd | 5448 | .phy_base_addr = 0x0, |
1a3b39ec | 5449 | .global1_addr = 0x1b, |
9069c13a | 5450 | .global2_addr = 0x1c, |
b91e055c | 5451 | .age_time_coeff = 3750, |
1a3b39ec | 5452 | .g1_irqs = 9, |
d6c5e6af | 5453 | .g2_irqs = 14, |
e606ca36 | 5454 | .atu_move_port_mask = 0x1f, |
f3645652 | 5455 | .pvt = true, |
b3e05aa1 | 5456 | .multi_chip = true, |
2fa8d3af | 5457 | .ptp_support = true, |
1a3b39ec AL |
5458 | .ops = &mv88e6290_ops, |
5459 | }, | |
5460 | ||
f81ec90f | 5461 | [MV88E6320] = { |
107fcc10 | 5462 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, |
f81ec90f VD |
5463 | .family = MV88E6XXX_FAMILY_6320, |
5464 | .name = "Marvell 88E6320", | |
5465 | .num_databases = 4096, | |
d9ea5620 | 5466 | .num_macs = 8192, |
f81ec90f | 5467 | .num_ports = 7, |
bc393155 | 5468 | .num_internal_phys = 5, |
a73ccd61 | 5469 | .num_gpio = 15, |
3cf3c846 | 5470 | .max_vid = 4095, |
9dddd478 | 5471 | .port_base_addr = 0x10, |
9255bacd | 5472 | .phy_base_addr = 0x0, |
a935c052 | 5473 | .global1_addr = 0x1b, |
9069c13a | 5474 | .global2_addr = 0x1c, |
acddbd21 | 5475 | .age_time_coeff = 15000, |
dc30c35b | 5476 | .g1_irqs = 8, |
bc393155 | 5477 | .g2_irqs = 10, |
e606ca36 | 5478 | .atu_move_port_mask = 0xf, |
f3645652 | 5479 | .pvt = true, |
b3e05aa1 | 5480 | .multi_chip = true, |
670bb80f | 5481 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
2fa8d3af | 5482 | .ptp_support = true, |
b3469dd8 | 5483 | .ops = &mv88e6320_ops, |
f81ec90f VD |
5484 | }, |
5485 | ||
5486 | [MV88E6321] = { | |
107fcc10 | 5487 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, |
f81ec90f VD |
5488 | .family = MV88E6XXX_FAMILY_6320, |
5489 | .name = "Marvell 88E6321", | |
5490 | .num_databases = 4096, | |
d9ea5620 | 5491 | .num_macs = 8192, |
f81ec90f | 5492 | .num_ports = 7, |
bc393155 | 5493 | .num_internal_phys = 5, |
a73ccd61 | 5494 | .num_gpio = 15, |
3cf3c846 | 5495 | .max_vid = 4095, |
9dddd478 | 5496 | .port_base_addr = 0x10, |
9255bacd | 5497 | .phy_base_addr = 0x0, |
a935c052 | 5498 | .global1_addr = 0x1b, |
9069c13a | 5499 | .global2_addr = 0x1c, |
acddbd21 | 5500 | .age_time_coeff = 15000, |
dc30c35b | 5501 | .g1_irqs = 8, |
bc393155 | 5502 | .g2_irqs = 10, |
e606ca36 | 5503 | .atu_move_port_mask = 0xf, |
b3e05aa1 | 5504 | .multi_chip = true, |
670bb80f | 5505 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
2fa8d3af | 5506 | .ptp_support = true, |
b3469dd8 | 5507 | .ops = &mv88e6321_ops, |
f81ec90f VD |
5508 | }, |
5509 | ||
a75961d0 | 5510 | [MV88E6341] = { |
107fcc10 | 5511 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, |
a75961d0 GC |
5512 | .family = MV88E6XXX_FAMILY_6341, |
5513 | .name = "Marvell 88E6341", | |
5514 | .num_databases = 4096, | |
d9ea5620 | 5515 | .num_macs = 2048, |
bc393155 | 5516 | .num_internal_phys = 5, |
a75961d0 | 5517 | .num_ports = 6, |
a73ccd61 | 5518 | .num_gpio = 11, |
3cf3c846 | 5519 | .max_vid = 4095, |
a75961d0 | 5520 | .port_base_addr = 0x10, |
9255bacd | 5521 | .phy_base_addr = 0x10, |
a75961d0 | 5522 | .global1_addr = 0x1b, |
9069c13a | 5523 | .global2_addr = 0x1c, |
a75961d0 | 5524 | .age_time_coeff = 3750, |
e606ca36 | 5525 | .atu_move_port_mask = 0x1f, |
adfccf11 | 5526 | .g1_irqs = 9, |
d6c5e6af | 5527 | .g2_irqs = 10, |
f3645652 | 5528 | .pvt = true, |
b3e05aa1 | 5529 | .multi_chip = true, |
670bb80f | 5530 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
2fa8d3af | 5531 | .ptp_support = true, |
a75961d0 GC |
5532 | .ops = &mv88e6341_ops, |
5533 | }, | |
5534 | ||
f81ec90f | 5535 | [MV88E6350] = { |
107fcc10 | 5536 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, |
f81ec90f VD |
5537 | .family = MV88E6XXX_FAMILY_6351, |
5538 | .name = "Marvell 88E6350", | |
5539 | .num_databases = 4096, | |
d9ea5620 | 5540 | .num_macs = 8192, |
f81ec90f | 5541 | .num_ports = 7, |
bc393155 | 5542 | .num_internal_phys = 5, |
3cf3c846 | 5543 | .max_vid = 4095, |
9dddd478 | 5544 | .port_base_addr = 0x10, |
9255bacd | 5545 | .phy_base_addr = 0x0, |
a935c052 | 5546 | .global1_addr = 0x1b, |
9069c13a | 5547 | .global2_addr = 0x1c, |
acddbd21 | 5548 | .age_time_coeff = 15000, |
dc30c35b | 5549 | .g1_irqs = 9, |
d6c5e6af | 5550 | .g2_irqs = 10, |
e606ca36 | 5551 | .atu_move_port_mask = 0xf, |
f3645652 | 5552 | .pvt = true, |
b3e05aa1 | 5553 | .multi_chip = true, |
670bb80f | 5554 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
b3469dd8 | 5555 | .ops = &mv88e6350_ops, |
f81ec90f VD |
5556 | }, |
5557 | ||
5558 | [MV88E6351] = { | |
107fcc10 | 5559 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, |
f81ec90f VD |
5560 | .family = MV88E6XXX_FAMILY_6351, |
5561 | .name = "Marvell 88E6351", | |
5562 | .num_databases = 4096, | |
d9ea5620 | 5563 | .num_macs = 8192, |
f81ec90f | 5564 | .num_ports = 7, |
bc393155 | 5565 | .num_internal_phys = 5, |
3cf3c846 | 5566 | .max_vid = 4095, |
9dddd478 | 5567 | .port_base_addr = 0x10, |
9255bacd | 5568 | .phy_base_addr = 0x0, |
a935c052 | 5569 | .global1_addr = 0x1b, |
9069c13a | 5570 | .global2_addr = 0x1c, |
acddbd21 | 5571 | .age_time_coeff = 15000, |
dc30c35b | 5572 | .g1_irqs = 9, |
d6c5e6af | 5573 | .g2_irqs = 10, |
e606ca36 | 5574 | .atu_move_port_mask = 0xf, |
f3645652 | 5575 | .pvt = true, |
b3e05aa1 | 5576 | .multi_chip = true, |
670bb80f | 5577 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
b3469dd8 | 5578 | .ops = &mv88e6351_ops, |
f81ec90f VD |
5579 | }, |
5580 | ||
5581 | [MV88E6352] = { | |
107fcc10 | 5582 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, |
f81ec90f VD |
5583 | .family = MV88E6XXX_FAMILY_6352, |
5584 | .name = "Marvell 88E6352", | |
5585 | .num_databases = 4096, | |
d9ea5620 | 5586 | .num_macs = 8192, |
f81ec90f | 5587 | .num_ports = 7, |
bc393155 | 5588 | .num_internal_phys = 5, |
a73ccd61 | 5589 | .num_gpio = 15, |
3cf3c846 | 5590 | .max_vid = 4095, |
9dddd478 | 5591 | .port_base_addr = 0x10, |
9255bacd | 5592 | .phy_base_addr = 0x0, |
a935c052 | 5593 | .global1_addr = 0x1b, |
9069c13a | 5594 | .global2_addr = 0x1c, |
acddbd21 | 5595 | .age_time_coeff = 15000, |
dc30c35b | 5596 | .g1_irqs = 9, |
d6c5e6af | 5597 | .g2_irqs = 10, |
e606ca36 | 5598 | .atu_move_port_mask = 0xf, |
f3645652 | 5599 | .pvt = true, |
b3e05aa1 | 5600 | .multi_chip = true, |
670bb80f | 5601 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
2fa8d3af | 5602 | .ptp_support = true, |
b3469dd8 | 5603 | .ops = &mv88e6352_ops, |
f81ec90f | 5604 | }, |
1a3b39ec | 5605 | [MV88E6390] = { |
107fcc10 | 5606 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, |
1a3b39ec AL |
5607 | .family = MV88E6XXX_FAMILY_6390, |
5608 | .name = "Marvell 88E6390", | |
5609 | .num_databases = 4096, | |
d9ea5620 | 5610 | .num_macs = 16384, |
1a3b39ec | 5611 | .num_ports = 11, /* 10 + Z80 */ |
95150f29 | 5612 | .num_internal_phys = 9, |
a73ccd61 | 5613 | .num_gpio = 16, |
931d1822 | 5614 | .max_vid = 8191, |
1a3b39ec | 5615 | .port_base_addr = 0x0, |
9255bacd | 5616 | .phy_base_addr = 0x0, |
1a3b39ec | 5617 | .global1_addr = 0x1b, |
9069c13a | 5618 | .global2_addr = 0x1c, |
b91e055c | 5619 | .age_time_coeff = 3750, |
1a3b39ec | 5620 | .g1_irqs = 9, |
d6c5e6af | 5621 | .g2_irqs = 14, |
e606ca36 | 5622 | .atu_move_port_mask = 0x1f, |
f3645652 | 5623 | .pvt = true, |
b3e05aa1 | 5624 | .multi_chip = true, |
670bb80f | 5625 | .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, |
2fa8d3af | 5626 | .ptp_support = true, |
1a3b39ec AL |
5627 | .ops = &mv88e6390_ops, |
5628 | }, | |
5629 | [MV88E6390X] = { | |
107fcc10 | 5630 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, |
1a3b39ec AL |
5631 | .family = MV88E6XXX_FAMILY_6390, |
5632 | .name = "Marvell 88E6390X", | |
5633 | .num_databases = 4096, | |
d9ea5620 | 5634 | .num_macs = 16384, |
1a3b39ec | 5635 | .num_ports = 11, /* 10 + Z80 */ |
95150f29 | 5636 | .num_internal_phys = 9, |
a73ccd61 | 5637 | .num_gpio = 16, |
931d1822 | 5638 | .max_vid = 8191, |
1a3b39ec | 5639 | .port_base_addr = 0x0, |
9255bacd | 5640 | .phy_base_addr = 0x0, |
1a3b39ec | 5641 | .global1_addr = 0x1b, |
9069c13a | 5642 | .global2_addr = 0x1c, |
b91e055c | 5643 | .age_time_coeff = 3750, |
1a3b39ec | 5644 | .g1_irqs = 9, |
d6c5e6af | 5645 | .g2_irqs = 14, |
e606ca36 | 5646 | .atu_move_port_mask = 0x1f, |
f3645652 | 5647 | .pvt = true, |
b3e05aa1 | 5648 | .multi_chip = true, |
670bb80f | 5649 | .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, |
2fa8d3af | 5650 | .ptp_support = true, |
1a3b39ec AL |
5651 | .ops = &mv88e6390x_ops, |
5652 | }, | |
de776d0d PS |
5653 | |
5654 | [MV88E6393X] = { | |
5655 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, | |
5656 | .family = MV88E6XXX_FAMILY_6393, | |
5657 | .name = "Marvell 88E6393X", | |
5658 | .num_databases = 4096, | |
5659 | .num_ports = 11, /* 10 + Z80 */ | |
5660 | .num_internal_phys = 9, | |
5661 | .max_vid = 8191, | |
5662 | .port_base_addr = 0x0, | |
5663 | .phy_base_addr = 0x0, | |
5664 | .global1_addr = 0x1b, | |
5665 | .global2_addr = 0x1c, | |
5666 | .age_time_coeff = 3750, | |
5667 | .g1_irqs = 10, | |
5668 | .g2_irqs = 14, | |
5669 | .atu_move_port_mask = 0x1f, | |
5670 | .pvt = true, | |
5671 | .multi_chip = true, | |
de776d0d PS |
5672 | .ptp_support = true, |
5673 | .ops = &mv88e6393x_ops, | |
5674 | }, | |
f81ec90f VD |
5675 | }; |
5676 | ||
5f7c0367 | 5677 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
b9b37713 | 5678 | { |
a439c061 | 5679 | int i; |
b9b37713 | 5680 | |
5f7c0367 VD |
5681 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
5682 | if (mv88e6xxx_table[i].prod_num == prod_num) | |
5683 | return &mv88e6xxx_table[i]; | |
b9b37713 | 5684 | |
b9b37713 VD |
5685 | return NULL; |
5686 | } | |
5687 | ||
fad09c73 | 5688 | static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) |
bc46a3d5 VD |
5689 | { |
5690 | const struct mv88e6xxx_info *info; | |
8f6345b2 VD |
5691 | unsigned int prod_num, rev; |
5692 | u16 id; | |
5693 | int err; | |
bc46a3d5 | 5694 | |
c9acece0 | 5695 | mv88e6xxx_reg_lock(chip); |
107fcc10 | 5696 | err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); |
c9acece0 | 5697 | mv88e6xxx_reg_unlock(chip); |
8f6345b2 VD |
5698 | if (err) |
5699 | return err; | |
bc46a3d5 | 5700 | |
107fcc10 VD |
5701 | prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; |
5702 | rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; | |
bc46a3d5 VD |
5703 | |
5704 | info = mv88e6xxx_lookup_info(prod_num); | |
5705 | if (!info) | |
5706 | return -ENODEV; | |
5707 | ||
caac8545 | 5708 | /* Update the compatible info with the probed one */ |
fad09c73 | 5709 | chip->info = info; |
bc46a3d5 | 5710 | |
fad09c73 VD |
5711 | dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", |
5712 | chip->info->prod_num, chip->info->name, rev); | |
bc46a3d5 VD |
5713 | |
5714 | return 0; | |
5715 | } | |
5716 | ||
fad09c73 | 5717 | static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) |
469d729f | 5718 | { |
fad09c73 | 5719 | struct mv88e6xxx_chip *chip; |
469d729f | 5720 | |
fad09c73 VD |
5721 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
5722 | if (!chip) | |
469d729f VD |
5723 | return NULL; |
5724 | ||
fad09c73 | 5725 | chip->dev = dev; |
469d729f | 5726 | |
fad09c73 | 5727 | mutex_init(&chip->reg_lock); |
a3c53be5 | 5728 | INIT_LIST_HEAD(&chip->mdios); |
da7dc875 | 5729 | idr_init(&chip->policies); |
469d729f | 5730 | |
fad09c73 | 5731 | return chip; |
469d729f VD |
5732 | } |
5733 | ||
5ed4e3eb | 5734 | static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, |
4d776482 FF |
5735 | int port, |
5736 | enum dsa_tag_protocol m) | |
7b314362 | 5737 | { |
04bed143 | 5738 | struct mv88e6xxx_chip *chip = ds->priv; |
2bbb33be | 5739 | |
670bb80f | 5740 | return chip->tag_protocol; |
7b314362 AL |
5741 | } |
5742 | ||
9a99bef5 TW |
5743 | static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, |
5744 | enum dsa_tag_protocol proto) | |
5745 | { | |
5746 | struct mv88e6xxx_chip *chip = ds->priv; | |
5747 | enum dsa_tag_protocol old_protocol; | |
5748 | int err; | |
5749 | ||
5750 | switch (proto) { | |
5751 | case DSA_TAG_PROTO_EDSA: | |
5752 | switch (chip->info->edsa_support) { | |
5753 | case MV88E6XXX_EDSA_UNSUPPORTED: | |
5754 | return -EPROTONOSUPPORT; | |
5755 | case MV88E6XXX_EDSA_UNDOCUMENTED: | |
5756 | dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); | |
5757 | fallthrough; | |
5758 | case MV88E6XXX_EDSA_SUPPORTED: | |
5759 | break; | |
5760 | } | |
5761 | break; | |
5762 | case DSA_TAG_PROTO_DSA: | |
5763 | break; | |
5764 | default: | |
5765 | return -EPROTONOSUPPORT; | |
5766 | } | |
5767 | ||
5768 | old_protocol = chip->tag_protocol; | |
5769 | chip->tag_protocol = proto; | |
5770 | ||
5771 | mv88e6xxx_reg_lock(chip); | |
5772 | err = mv88e6xxx_setup_port_mode(chip, port); | |
5773 | mv88e6xxx_reg_unlock(chip); | |
5774 | ||
5775 | if (err) | |
5776 | chip->tag_protocol = old_protocol; | |
5777 | ||
5778 | return err; | |
5779 | } | |
5780 | ||
a52b2da7 VO |
5781 | static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, |
5782 | const struct switchdev_obj_port_mdb *mdb) | |
7df8fbdd | 5783 | { |
04bed143 | 5784 | struct mv88e6xxx_chip *chip = ds->priv; |
a52b2da7 | 5785 | int err; |
7df8fbdd | 5786 | |
c9acece0 | 5787 | mv88e6xxx_reg_lock(chip); |
a52b2da7 VO |
5788 | err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, |
5789 | MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); | |
c9acece0 | 5790 | mv88e6xxx_reg_unlock(chip); |
a52b2da7 VO |
5791 | |
5792 | return err; | |
7df8fbdd VD |
5793 | } |
5794 | ||
5795 | static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, | |
5796 | const struct switchdev_obj_port_mdb *mdb) | |
5797 | { | |
04bed143 | 5798 | struct mv88e6xxx_chip *chip = ds->priv; |
7df8fbdd VD |
5799 | int err; |
5800 | ||
c9acece0 | 5801 | mv88e6xxx_reg_lock(chip); |
d8291a95 | 5802 | err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); |
c9acece0 | 5803 | mv88e6xxx_reg_unlock(chip); |
7df8fbdd VD |
5804 | |
5805 | return err; | |
5806 | } | |
5807 | ||
f0942e00 IT |
5808 | static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, |
5809 | struct dsa_mall_mirror_tc_entry *mirror, | |
5810 | bool ingress) | |
5811 | { | |
5812 | enum mv88e6xxx_egress_direction direction = ingress ? | |
5813 | MV88E6XXX_EGRESS_DIR_INGRESS : | |
5814 | MV88E6XXX_EGRESS_DIR_EGRESS; | |
5815 | struct mv88e6xxx_chip *chip = ds->priv; | |
5816 | bool other_mirrors = false; | |
5817 | int i; | |
5818 | int err; | |
5819 | ||
f0942e00 IT |
5820 | mutex_lock(&chip->reg_lock); |
5821 | if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != | |
5822 | mirror->to_local_port) { | |
5823 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) | |
5824 | other_mirrors |= ingress ? | |
5825 | chip->ports[i].mirror_ingress : | |
5826 | chip->ports[i].mirror_egress; | |
5827 | ||
5828 | /* Can't change egress port when other mirror is active */ | |
5829 | if (other_mirrors) { | |
5830 | err = -EBUSY; | |
5831 | goto out; | |
5832 | } | |
5833 | ||
2fda45f0 MB |
5834 | err = mv88e6xxx_set_egress_port(chip, direction, |
5835 | mirror->to_local_port); | |
f0942e00 IT |
5836 | if (err) |
5837 | goto out; | |
5838 | } | |
5839 | ||
5840 | err = mv88e6xxx_port_set_mirror(chip, port, direction, true); | |
5841 | out: | |
5842 | mutex_unlock(&chip->reg_lock); | |
5843 | ||
5844 | return err; | |
5845 | } | |
5846 | ||
5847 | static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, | |
5848 | struct dsa_mall_mirror_tc_entry *mirror) | |
5849 | { | |
5850 | enum mv88e6xxx_egress_direction direction = mirror->ingress ? | |
5851 | MV88E6XXX_EGRESS_DIR_INGRESS : | |
5852 | MV88E6XXX_EGRESS_DIR_EGRESS; | |
5853 | struct mv88e6xxx_chip *chip = ds->priv; | |
5854 | bool other_mirrors = false; | |
5855 | int i; | |
5856 | ||
5857 | mutex_lock(&chip->reg_lock); | |
5858 | if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) | |
5859 | dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); | |
5860 | ||
5861 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) | |
5862 | other_mirrors |= mirror->ingress ? | |
5863 | chip->ports[i].mirror_ingress : | |
5864 | chip->ports[i].mirror_egress; | |
5865 | ||
5866 | /* Reset egress port when no other mirror is active */ | |
5867 | if (!other_mirrors) { | |
2fda45f0 MB |
5868 | if (mv88e6xxx_set_egress_port(chip, direction, |
5869 | dsa_upstream_port(ds, port))) | |
f0942e00 IT |
5870 | dev_err(ds->dev, "failed to set egress port\n"); |
5871 | } | |
5872 | ||
5873 | mutex_unlock(&chip->reg_lock); | |
5874 | } | |
5875 | ||
a8b659e7 VO |
5876 | static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, |
5877 | struct switchdev_brport_flags flags, | |
5878 | struct netlink_ext_ack *extack) | |
5879 | { | |
5880 | struct mv88e6xxx_chip *chip = ds->priv; | |
5881 | const struct mv88e6xxx_ops *ops; | |
5882 | ||
8d1d8298 TW |
5883 | if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | |
5884 | BR_BCAST_FLOOD)) | |
a8b659e7 VO |
5885 | return -EINVAL; |
5886 | ||
5887 | ops = chip->info->ops; | |
5888 | ||
5889 | if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) | |
5890 | return -EINVAL; | |
5891 | ||
5892 | if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) | |
5893 | return -EINVAL; | |
5894 | ||
5895 | return 0; | |
5896 | } | |
5897 | ||
5898 | static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, | |
5899 | struct switchdev_brport_flags flags, | |
5900 | struct netlink_ext_ack *extack) | |
4f85901f RK |
5901 | { |
5902 | struct mv88e6xxx_chip *chip = ds->priv; | |
5903 | int err = -EOPNOTSUPP; | |
5904 | ||
c9acece0 | 5905 | mv88e6xxx_reg_lock(chip); |
a8b659e7 | 5906 | |
041bd545 TW |
5907 | if (flags.mask & BR_LEARNING) { |
5908 | bool learning = !!(flags.val & BR_LEARNING); | |
5909 | u16 pav = learning ? (1 << port) : 0; | |
5910 | ||
5911 | err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); | |
5912 | if (err) | |
5913 | goto out; | |
041bd545 TW |
5914 | } |
5915 | ||
a8b659e7 VO |
5916 | if (flags.mask & BR_FLOOD) { |
5917 | bool unicast = !!(flags.val & BR_FLOOD); | |
5918 | ||
5919 | err = chip->info->ops->port_set_ucast_flood(chip, port, | |
5920 | unicast); | |
5921 | if (err) | |
5922 | goto out; | |
5923 | } | |
5924 | ||
5925 | if (flags.mask & BR_MCAST_FLOOD) { | |
5926 | bool multicast = !!(flags.val & BR_MCAST_FLOOD); | |
5927 | ||
5928 | err = chip->info->ops->port_set_mcast_flood(chip, port, | |
5929 | multicast); | |
5930 | if (err) | |
5931 | goto out; | |
5932 | } | |
5933 | ||
8d1d8298 TW |
5934 | if (flags.mask & BR_BCAST_FLOOD) { |
5935 | bool broadcast = !!(flags.val & BR_BCAST_FLOOD); | |
5936 | ||
5937 | err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); | |
5938 | if (err) | |
5939 | goto out; | |
5940 | } | |
5941 | ||
a8b659e7 VO |
5942 | out: |
5943 | mv88e6xxx_reg_unlock(chip); | |
5944 | ||
5945 | return err; | |
5946 | } | |
5947 | ||
57e661aa TW |
5948 | static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, |
5949 | struct net_device *lag, | |
5950 | struct netdev_lag_upper_info *info) | |
5951 | { | |
b80dc51b | 5952 | struct mv88e6xxx_chip *chip = ds->priv; |
57e661aa TW |
5953 | struct dsa_port *dp; |
5954 | int id, members = 0; | |
5955 | ||
b80dc51b TW |
5956 | if (!mv88e6xxx_has_lag(chip)) |
5957 | return false; | |
5958 | ||
57e661aa TW |
5959 | id = dsa_lag_id(ds->dst, lag); |
5960 | if (id < 0 || id >= ds->num_lag_ids) | |
5961 | return false; | |
5962 | ||
5963 | dsa_lag_foreach_port(dp, ds->dst, lag) | |
5964 | /* Includes the port joining the LAG */ | |
5965 | members++; | |
5966 | ||
5967 | if (members > 8) | |
5968 | return false; | |
5969 | ||
5970 | /* We could potentially relax this to include active | |
5971 | * backup in the future. | |
5972 | */ | |
5973 | if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) | |
5974 | return false; | |
5975 | ||
5976 | /* Ideally we would also validate that the hash type matches | |
5977 | * the hardware. Alas, this is always set to unknown on team | |
5978 | * interfaces. | |
5979 | */ | |
5980 | return true; | |
5981 | } | |
5982 | ||
5983 | static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) | |
5984 | { | |
5985 | struct mv88e6xxx_chip *chip = ds->priv; | |
5986 | struct dsa_port *dp; | |
5987 | u16 map = 0; | |
5988 | int id; | |
5989 | ||
5990 | id = dsa_lag_id(ds->dst, lag); | |
5991 | ||
5992 | /* Build the map of all ports to distribute flows destined for | |
5993 | * this LAG. This can be either a local user port, or a DSA | |
5994 | * port if the LAG port is on a remote chip. | |
5995 | */ | |
5996 | dsa_lag_foreach_port(dp, ds->dst, lag) | |
5997 | map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); | |
5998 | ||
5999 | return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); | |
6000 | } | |
6001 | ||
6002 | static const u8 mv88e6xxx_lag_mask_table[8][8] = { | |
6003 | /* Row number corresponds to the number of active members in a | |
6004 | * LAG. Each column states which of the eight hash buckets are | |
6005 | * mapped to the column:th port in the LAG. | |
6006 | * | |
6007 | * Example: In a LAG with three active ports, the second port | |
6008 | * ([2][1]) would be selected for traffic mapped to buckets | |
6009 | * 3,4,5 (0x38). | |
6010 | */ | |
6011 | { 0xff, 0, 0, 0, 0, 0, 0, 0 }, | |
6012 | { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, | |
6013 | { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, | |
6014 | { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, | |
6015 | { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, | |
6016 | { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, | |
6017 | { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, | |
6018 | { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, | |
6019 | }; | |
6020 | ||
6021 | static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, | |
6022 | int num_tx, int nth) | |
6023 | { | |
6024 | u8 active = 0; | |
6025 | int i; | |
6026 | ||
6027 | num_tx = num_tx <= 8 ? num_tx : 8; | |
6028 | if (nth < num_tx) | |
6029 | active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; | |
6030 | ||
6031 | for (i = 0; i < 8; i++) { | |
6032 | if (BIT(i) & active) | |
6033 | mask[i] |= BIT(port); | |
6034 | } | |
6035 | } | |
6036 | ||
6037 | static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) | |
6038 | { | |
6039 | struct mv88e6xxx_chip *chip = ds->priv; | |
6040 | unsigned int id, num_tx; | |
6041 | struct net_device *lag; | |
6042 | struct dsa_port *dp; | |
6043 | int i, err, nth; | |
6044 | u16 mask[8]; | |
6045 | u16 ivec; | |
6046 | ||
6047 | /* Assume no port is a member of any LAG. */ | |
6048 | ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; | |
6049 | ||
6050 | /* Disable all masks for ports that _are_ members of a LAG. */ | |
6051 | list_for_each_entry(dp, &ds->dst->ports, list) { | |
6052 | if (!dp->lag_dev || dp->ds != ds) | |
6053 | continue; | |
6054 | ||
6055 | ivec &= ~BIT(dp->index); | |
6056 | } | |
6057 | ||
6058 | for (i = 0; i < 8; i++) | |
6059 | mask[i] = ivec; | |
6060 | ||
6061 | /* Enable the correct subset of masks for all LAG ports that | |
6062 | * are in the Tx set. | |
6063 | */ | |
6064 | dsa_lags_foreach_id(id, ds->dst) { | |
6065 | lag = dsa_lag_dev(ds->dst, id); | |
6066 | if (!lag) | |
6067 | continue; | |
6068 | ||
6069 | num_tx = 0; | |
6070 | dsa_lag_foreach_port(dp, ds->dst, lag) { | |
6071 | if (dp->lag_tx_enabled) | |
6072 | num_tx++; | |
6073 | } | |
6074 | ||
6075 | if (!num_tx) | |
6076 | continue; | |
6077 | ||
6078 | nth = 0; | |
6079 | dsa_lag_foreach_port(dp, ds->dst, lag) { | |
6080 | if (!dp->lag_tx_enabled) | |
6081 | continue; | |
6082 | ||
6083 | if (dp->ds == ds) | |
6084 | mv88e6xxx_lag_set_port_mask(mask, dp->index, | |
6085 | num_tx, nth); | |
6086 | ||
6087 | nth++; | |
6088 | } | |
6089 | } | |
6090 | ||
6091 | for (i = 0; i < 8; i++) { | |
6092 | err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); | |
6093 | if (err) | |
6094 | return err; | |
6095 | } | |
6096 | ||
6097 | return 0; | |
6098 | } | |
6099 | ||
6100 | static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, | |
6101 | struct net_device *lag) | |
6102 | { | |
6103 | int err; | |
6104 | ||
6105 | err = mv88e6xxx_lag_sync_masks(ds); | |
6106 | ||
6107 | if (!err) | |
6108 | err = mv88e6xxx_lag_sync_map(ds, lag); | |
6109 | ||
6110 | return err; | |
6111 | } | |
6112 | ||
6113 | static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) | |
6114 | { | |
6115 | struct mv88e6xxx_chip *chip = ds->priv; | |
6116 | int err; | |
6117 | ||
6118 | mv88e6xxx_reg_lock(chip); | |
6119 | err = mv88e6xxx_lag_sync_masks(ds); | |
6120 | mv88e6xxx_reg_unlock(chip); | |
6121 | return err; | |
6122 | } | |
6123 | ||
6124 | static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, | |
6125 | struct net_device *lag, | |
6126 | struct netdev_lag_upper_info *info) | |
6127 | { | |
6128 | struct mv88e6xxx_chip *chip = ds->priv; | |
6129 | int err, id; | |
6130 | ||
6131 | if (!mv88e6xxx_lag_can_offload(ds, lag, info)) | |
6132 | return -EOPNOTSUPP; | |
6133 | ||
6134 | id = dsa_lag_id(ds->dst, lag); | |
6135 | ||
6136 | mv88e6xxx_reg_lock(chip); | |
6137 | ||
6138 | err = mv88e6xxx_port_set_trunk(chip, port, true, id); | |
6139 | if (err) | |
6140 | goto err_unlock; | |
6141 | ||
6142 | err = mv88e6xxx_lag_sync_masks_map(ds, lag); | |
6143 | if (err) | |
6144 | goto err_clear_trunk; | |
6145 | ||
6146 | mv88e6xxx_reg_unlock(chip); | |
6147 | return 0; | |
6148 | ||
6149 | err_clear_trunk: | |
6150 | mv88e6xxx_port_set_trunk(chip, port, false, 0); | |
6151 | err_unlock: | |
6152 | mv88e6xxx_reg_unlock(chip); | |
6153 | return err; | |
6154 | } | |
6155 | ||
6156 | static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, | |
6157 | struct net_device *lag) | |
6158 | { | |
6159 | struct mv88e6xxx_chip *chip = ds->priv; | |
6160 | int err_sync, err_trunk; | |
6161 | ||
6162 | mv88e6xxx_reg_lock(chip); | |
6163 | err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); | |
6164 | err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); | |
6165 | mv88e6xxx_reg_unlock(chip); | |
6166 | return err_sync ? : err_trunk; | |
6167 | } | |
6168 | ||
6169 | static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, | |
6170 | int port) | |
6171 | { | |
6172 | struct mv88e6xxx_chip *chip = ds->priv; | |
6173 | int err; | |
6174 | ||
6175 | mv88e6xxx_reg_lock(chip); | |
6176 | err = mv88e6xxx_lag_sync_masks(ds); | |
6177 | mv88e6xxx_reg_unlock(chip); | |
6178 | return err; | |
6179 | } | |
6180 | ||
6181 | static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, | |
6182 | int port, struct net_device *lag, | |
6183 | struct netdev_lag_upper_info *info) | |
6184 | { | |
6185 | struct mv88e6xxx_chip *chip = ds->priv; | |
6186 | int err; | |
6187 | ||
6188 | if (!mv88e6xxx_lag_can_offload(ds, lag, info)) | |
6189 | return -EOPNOTSUPP; | |
6190 | ||
6191 | mv88e6xxx_reg_lock(chip); | |
6192 | ||
6193 | err = mv88e6xxx_lag_sync_masks_map(ds, lag); | |
6194 | if (err) | |
6195 | goto unlock; | |
6196 | ||
6197 | err = mv88e6xxx_pvt_map(chip, sw_index, port); | |
6198 | ||
6199 | unlock: | |
6200 | mv88e6xxx_reg_unlock(chip); | |
6201 | return err; | |
6202 | } | |
6203 | ||
6204 | static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, | |
6205 | int port, struct net_device *lag) | |
6206 | { | |
6207 | struct mv88e6xxx_chip *chip = ds->priv; | |
6208 | int err_sync, err_pvt; | |
6209 | ||
6210 | mv88e6xxx_reg_lock(chip); | |
6211 | err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); | |
6212 | err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); | |
6213 | mv88e6xxx_reg_unlock(chip); | |
6214 | return err_sync ? : err_pvt; | |
6215 | } | |
6216 | ||
a82f67af | 6217 | static const struct dsa_switch_ops mv88e6xxx_switch_ops = { |
7b314362 | 6218 | .get_tag_protocol = mv88e6xxx_get_tag_protocol, |
9a99bef5 | 6219 | .change_tag_protocol = mv88e6xxx_change_tag_protocol, |
f81ec90f | 6220 | .setup = mv88e6xxx_setup, |
23e8b470 | 6221 | .teardown = mv88e6xxx_teardown, |
fd292c18 VO |
6222 | .port_setup = mv88e6xxx_port_setup, |
6223 | .port_teardown = mv88e6xxx_port_teardown, | |
c9a2356f | 6224 | .phylink_validate = mv88e6xxx_validate, |
a5a6858b | 6225 | .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, |
c9a2356f | 6226 | .phylink_mac_config = mv88e6xxx_mac_config, |
a5a6858b | 6227 | .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, |
c9a2356f RK |
6228 | .phylink_mac_link_down = mv88e6xxx_mac_link_down, |
6229 | .phylink_mac_link_up = mv88e6xxx_mac_link_up, | |
f81ec90f VD |
6230 | .get_strings = mv88e6xxx_get_strings, |
6231 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, | |
6232 | .get_sset_count = mv88e6xxx_get_sset_count, | |
04aca993 AL |
6233 | .port_enable = mv88e6xxx_port_enable, |
6234 | .port_disable = mv88e6xxx_port_disable, | |
2a550aec AL |
6235 | .port_max_mtu = mv88e6xxx_get_max_mtu, |
6236 | .port_change_mtu = mv88e6xxx_change_mtu, | |
08f50061 VD |
6237 | .get_mac_eee = mv88e6xxx_get_mac_eee, |
6238 | .set_mac_eee = mv88e6xxx_set_mac_eee, | |
f8cd8753 | 6239 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
f81ec90f VD |
6240 | .get_eeprom = mv88e6xxx_get_eeprom, |
6241 | .set_eeprom = mv88e6xxx_set_eeprom, | |
6242 | .get_regs_len = mv88e6xxx_get_regs_len, | |
6243 | .get_regs = mv88e6xxx_get_regs, | |
da7dc875 VD |
6244 | .get_rxnfc = mv88e6xxx_get_rxnfc, |
6245 | .set_rxnfc = mv88e6xxx_set_rxnfc, | |
2cfcd964 | 6246 | .set_ageing_time = mv88e6xxx_set_ageing_time, |
f81ec90f VD |
6247 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
6248 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, | |
a8b659e7 VO |
6249 | .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, |
6250 | .port_bridge_flags = mv88e6xxx_port_bridge_flags, | |
f81ec90f | 6251 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, |
749efcb8 | 6252 | .port_fast_age = mv88e6xxx_port_fast_age, |
f81ec90f | 6253 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, |
f81ec90f VD |
6254 | .port_vlan_add = mv88e6xxx_port_vlan_add, |
6255 | .port_vlan_del = mv88e6xxx_port_vlan_del, | |
f81ec90f VD |
6256 | .port_fdb_add = mv88e6xxx_port_fdb_add, |
6257 | .port_fdb_del = mv88e6xxx_port_fdb_del, | |
6258 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, | |
7df8fbdd VD |
6259 | .port_mdb_add = mv88e6xxx_port_mdb_add, |
6260 | .port_mdb_del = mv88e6xxx_port_mdb_del, | |
f0942e00 IT |
6261 | .port_mirror_add = mv88e6xxx_port_mirror_add, |
6262 | .port_mirror_del = mv88e6xxx_port_mirror_del, | |
aec5ac88 VD |
6263 | .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, |
6264 | .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, | |
c6fe0ad2 BS |
6265 | .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, |
6266 | .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, | |
6267 | .port_txtstamp = mv88e6xxx_port_txtstamp, | |
6268 | .port_rxtstamp = mv88e6xxx_port_rxtstamp, | |
6269 | .get_ts_info = mv88e6xxx_get_ts_info, | |
23e8b470 AL |
6270 | .devlink_param_get = mv88e6xxx_devlink_param_get, |
6271 | .devlink_param_set = mv88e6xxx_devlink_param_set, | |
93157307 | 6272 | .devlink_info_get = mv88e6xxx_devlink_info_get, |
57e661aa TW |
6273 | .port_lag_change = mv88e6xxx_port_lag_change, |
6274 | .port_lag_join = mv88e6xxx_port_lag_join, | |
6275 | .port_lag_leave = mv88e6xxx_port_lag_leave, | |
6276 | .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, | |
6277 | .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, | |
6278 | .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, | |
ce5df689 VO |
6279 | .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload, |
6280 | .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload, | |
f81ec90f VD |
6281 | }; |
6282 | ||
55ed0ce0 | 6283 | static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) |
b7e66a5f | 6284 | { |
fad09c73 | 6285 | struct device *dev = chip->dev; |
b7e66a5f VD |
6286 | struct dsa_switch *ds; |
6287 | ||
7e99e347 | 6288 | ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); |
b7e66a5f VD |
6289 | if (!ds) |
6290 | return -ENOMEM; | |
6291 | ||
7e99e347 VD |
6292 | ds->dev = dev; |
6293 | ds->num_ports = mv88e6xxx_num_ports(chip); | |
fad09c73 | 6294 | ds->priv = chip; |
877b7cb0 | 6295 | ds->dev = dev; |
9d490b4e | 6296 | ds->ops = &mv88e6xxx_switch_ops; |
9ff74f24 VD |
6297 | ds->ageing_time_min = chip->info->age_time_coeff; |
6298 | ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; | |
b7e66a5f | 6299 | |
57e661aa TW |
6300 | /* Some chips support up to 32, but that requires enabling the |
6301 | * 5-bit port mode, which we do not support. 640k^W16 ought to | |
6302 | * be enough for anyone. | |
6303 | */ | |
b80dc51b | 6304 | ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; |
57e661aa | 6305 | |
b7e66a5f VD |
6306 | dev_set_drvdata(dev, ds); |
6307 | ||
23c9ee49 | 6308 | return dsa_register_switch(ds); |
b7e66a5f VD |
6309 | } |
6310 | ||
fad09c73 | 6311 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) |
b7e66a5f | 6312 | { |
fad09c73 | 6313 | dsa_unregister_switch(chip->ds); |
b7e66a5f VD |
6314 | } |
6315 | ||
877b7cb0 AL |
6316 | static const void *pdata_device_get_match_data(struct device *dev) |
6317 | { | |
6318 | const struct of_device_id *matches = dev->driver->of_match_table; | |
6319 | const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; | |
6320 | ||
6321 | for (; matches->name[0] || matches->type[0] || matches->compatible[0]; | |
6322 | matches++) { | |
6323 | if (!strcmp(pdata->compatible, matches->compatible)) | |
6324 | return matches->data; | |
6325 | } | |
6326 | return NULL; | |
6327 | } | |
6328 | ||
bcd3d9d9 MR |
6329 | /* There is no suspend to RAM support at DSA level yet, the switch configuration |
6330 | * would be lost after a power cycle so prevent it to be suspended. | |
6331 | */ | |
6332 | static int __maybe_unused mv88e6xxx_suspend(struct device *dev) | |
6333 | { | |
6334 | return -EOPNOTSUPP; | |
6335 | } | |
6336 | ||
6337 | static int __maybe_unused mv88e6xxx_resume(struct device *dev) | |
6338 | { | |
6339 | return 0; | |
6340 | } | |
6341 | ||
6342 | static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); | |
6343 | ||
57d32310 | 6344 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
98e67308 | 6345 | { |
877b7cb0 | 6346 | struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; |
7ddae24f | 6347 | const struct mv88e6xxx_info *compat_info = NULL; |
14c7b3c3 | 6348 | struct device *dev = &mdiodev->dev; |
f8cd8753 | 6349 | struct device_node *np = dev->of_node; |
fad09c73 | 6350 | struct mv88e6xxx_chip *chip; |
877b7cb0 | 6351 | int port; |
52638f71 | 6352 | int err; |
14c7b3c3 | 6353 | |
7bb8c996 AL |
6354 | if (!np && !pdata) |
6355 | return -EINVAL; | |
6356 | ||
877b7cb0 AL |
6357 | if (np) |
6358 | compat_info = of_device_get_match_data(dev); | |
6359 | ||
6360 | if (pdata) { | |
6361 | compat_info = pdata_device_get_match_data(dev); | |
6362 | ||
6363 | if (!pdata->netdev) | |
6364 | return -EINVAL; | |
6365 | ||
6366 | for (port = 0; port < DSA_MAX_PORTS; port++) { | |
6367 | if (!(pdata->enabled_ports & (1 << port))) | |
6368 | continue; | |
6369 | if (strcmp(pdata->cd.port_names[port], "cpu")) | |
6370 | continue; | |
6371 | pdata->cd.netdev[port] = &pdata->netdev->dev; | |
6372 | break; | |
6373 | } | |
6374 | } | |
6375 | ||
caac8545 VD |
6376 | if (!compat_info) |
6377 | return -EINVAL; | |
6378 | ||
fad09c73 | 6379 | chip = mv88e6xxx_alloc_chip(dev); |
877b7cb0 AL |
6380 | if (!chip) { |
6381 | err = -ENOMEM; | |
6382 | goto out; | |
6383 | } | |
14c7b3c3 | 6384 | |
fad09c73 | 6385 | chip->info = compat_info; |
caac8545 | 6386 | |
fad09c73 | 6387 | err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); |
4a70c4ab | 6388 | if (err) |
877b7cb0 | 6389 | goto out; |
14c7b3c3 | 6390 | |
b4308f04 | 6391 | chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); |
877b7cb0 AL |
6392 | if (IS_ERR(chip->reset)) { |
6393 | err = PTR_ERR(chip->reset); | |
6394 | goto out; | |
6395 | } | |
7b75e49d BS |
6396 | if (chip->reset) |
6397 | usleep_range(1000, 2000); | |
b4308f04 | 6398 | |
fad09c73 | 6399 | err = mv88e6xxx_detect(chip); |
bc46a3d5 | 6400 | if (err) |
877b7cb0 | 6401 | goto out; |
14c7b3c3 | 6402 | |
670bb80f TW |
6403 | if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) |
6404 | chip->tag_protocol = DSA_TAG_PROTO_EDSA; | |
6405 | else | |
6406 | chip->tag_protocol = DSA_TAG_PROTO_DSA; | |
6407 | ||
e57e5e77 VD |
6408 | mv88e6xxx_phy_init(chip); |
6409 | ||
00baabe5 AL |
6410 | if (chip->info->ops->get_eeprom) { |
6411 | if (np) | |
6412 | of_property_read_u32(np, "eeprom-length", | |
6413 | &chip->eeprom_len); | |
6414 | else | |
6415 | chip->eeprom_len = pdata->eeprom_len; | |
6416 | } | |
f8cd8753 | 6417 | |
c9acece0 | 6418 | mv88e6xxx_reg_lock(chip); |
dc30c35b | 6419 | err = mv88e6xxx_switch_reset(chip); |
c9acece0 | 6420 | mv88e6xxx_reg_unlock(chip); |
dc30c35b AL |
6421 | if (err) |
6422 | goto out; | |
6423 | ||
a27415de AL |
6424 | if (np) { |
6425 | chip->irq = of_irq_get(np, 0); | |
6426 | if (chip->irq == -EPROBE_DEFER) { | |
6427 | err = chip->irq; | |
6428 | goto out; | |
6429 | } | |
dc30c35b AL |
6430 | } |
6431 | ||
a27415de AL |
6432 | if (pdata) |
6433 | chip->irq = pdata->irq; | |
6434 | ||
294d711e | 6435 | /* Has to be performed before the MDIO bus is created, because |
a708767e | 6436 | * the PHYs will link their interrupts to these interrupt |
294d711e AL |
6437 | * controllers |
6438 | */ | |
c9acece0 | 6439 | mv88e6xxx_reg_lock(chip); |
294d711e | 6440 | if (chip->irq > 0) |
dc30c35b | 6441 | err = mv88e6xxx_g1_irq_setup(chip); |
294d711e AL |
6442 | else |
6443 | err = mv88e6xxx_irq_poll_setup(chip); | |
c9acece0 | 6444 | mv88e6xxx_reg_unlock(chip); |
0977644c | 6445 | |
294d711e AL |
6446 | if (err) |
6447 | goto out; | |
62eb1162 | 6448 | |
294d711e AL |
6449 | if (chip->info->g2_irqs > 0) { |
6450 | err = mv88e6xxx_g2_irq_setup(chip); | |
62eb1162 | 6451 | if (err) |
294d711e | 6452 | goto out_g1_irq; |
dc30c35b AL |
6453 | } |
6454 | ||
294d711e AL |
6455 | err = mv88e6xxx_g1_atu_prob_irq_setup(chip); |
6456 | if (err) | |
6457 | goto out_g2_irq; | |
6458 | ||
6459 | err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); | |
6460 | if (err) | |
6461 | goto out_g1_atu_prob_irq; | |
6462 | ||
a3c53be5 | 6463 | err = mv88e6xxx_mdios_register(chip, np); |
b516d453 | 6464 | if (err) |
62eb1162 | 6465 | goto out_g1_vtu_prob_irq; |
b516d453 | 6466 | |
55ed0ce0 | 6467 | err = mv88e6xxx_register_switch(chip); |
dc30c35b AL |
6468 | if (err) |
6469 | goto out_mdio; | |
83c0afae | 6470 | |
98e67308 | 6471 | return 0; |
dc30c35b AL |
6472 | |
6473 | out_mdio: | |
a3c53be5 | 6474 | mv88e6xxx_mdios_unregister(chip); |
62eb1162 | 6475 | out_g1_vtu_prob_irq: |
294d711e | 6476 | mv88e6xxx_g1_vtu_prob_irq_free(chip); |
0977644c | 6477 | out_g1_atu_prob_irq: |
294d711e | 6478 | mv88e6xxx_g1_atu_prob_irq_free(chip); |
dc30c35b | 6479 | out_g2_irq: |
294d711e | 6480 | if (chip->info->g2_irqs > 0) |
dc30c35b AL |
6481 | mv88e6xxx_g2_irq_free(chip); |
6482 | out_g1_irq: | |
294d711e | 6483 | if (chip->irq > 0) |
46712644 | 6484 | mv88e6xxx_g1_irq_free(chip); |
294d711e AL |
6485 | else |
6486 | mv88e6xxx_irq_poll_free(chip); | |
dc30c35b | 6487 | out: |
877b7cb0 AL |
6488 | if (pdata) |
6489 | dev_put(pdata->netdev); | |
6490 | ||
dc30c35b | 6491 | return err; |
98e67308 | 6492 | } |
14c7b3c3 AL |
6493 | |
6494 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) | |
6495 | { | |
6496 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); | |
0650bf52 VO |
6497 | struct mv88e6xxx_chip *chip; |
6498 | ||
6499 | if (!ds) | |
6500 | return; | |
6501 | ||
6502 | chip = ds->priv; | |
14c7b3c3 | 6503 | |
c6fe0ad2 BS |
6504 | if (chip->info->ptp_support) { |
6505 | mv88e6xxx_hwtstamp_free(chip); | |
2fa8d3af | 6506 | mv88e6xxx_ptp_free(chip); |
c6fe0ad2 | 6507 | } |
2fa8d3af | 6508 | |
930188ce | 6509 | mv88e6xxx_phy_destroy(chip); |
fad09c73 | 6510 | mv88e6xxx_unregister_switch(chip); |
a3c53be5 | 6511 | mv88e6xxx_mdios_unregister(chip); |
dc30c35b | 6512 | |
76f38f1f AL |
6513 | mv88e6xxx_g1_vtu_prob_irq_free(chip); |
6514 | mv88e6xxx_g1_atu_prob_irq_free(chip); | |
6515 | ||
6516 | if (chip->info->g2_irqs > 0) | |
6517 | mv88e6xxx_g2_irq_free(chip); | |
6518 | ||
76f38f1f | 6519 | if (chip->irq > 0) |
46712644 | 6520 | mv88e6xxx_g1_irq_free(chip); |
76f38f1f AL |
6521 | else |
6522 | mv88e6xxx_irq_poll_free(chip); | |
0650bf52 VO |
6523 | |
6524 | dev_set_drvdata(&mdiodev->dev, NULL); | |
6525 | } | |
6526 | ||
6527 | static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) | |
6528 | { | |
6529 | struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); | |
6530 | ||
6531 | if (!ds) | |
6532 | return; | |
6533 | ||
6534 | dsa_switch_shutdown(ds); | |
6535 | ||
6536 | dev_set_drvdata(&mdiodev->dev, NULL); | |
14c7b3c3 AL |
6537 | } |
6538 | ||
6539 | static const struct of_device_id mv88e6xxx_of_match[] = { | |
caac8545 VD |
6540 | { |
6541 | .compatible = "marvell,mv88e6085", | |
6542 | .data = &mv88e6xxx_table[MV88E6085], | |
6543 | }, | |
1a3b39ec AL |
6544 | { |
6545 | .compatible = "marvell,mv88e6190", | |
6546 | .data = &mv88e6xxx_table[MV88E6190], | |
6547 | }, | |
1f71836f RV |
6548 | { |
6549 | .compatible = "marvell,mv88e6250", | |
6550 | .data = &mv88e6xxx_table[MV88E6250], | |
6551 | }, | |
14c7b3c3 AL |
6552 | { /* sentinel */ }, |
6553 | }; | |
6554 | ||
6555 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); | |
6556 | ||
6557 | static struct mdio_driver mv88e6xxx_driver = { | |
6558 | .probe = mv88e6xxx_probe, | |
6559 | .remove = mv88e6xxx_remove, | |
0650bf52 | 6560 | .shutdown = mv88e6xxx_shutdown, |
14c7b3c3 AL |
6561 | .mdiodrv.driver = { |
6562 | .name = "mv88e6085", | |
6563 | .of_match_table = mv88e6xxx_of_match, | |
bcd3d9d9 | 6564 | .pm = &mv88e6xxx_pm_ops, |
14c7b3c3 AL |
6565 | }, |
6566 | }; | |
6567 | ||
7324d50e | 6568 | mdio_module_driver(mv88e6xxx_driver); |
3d825ede BH |
6569 | |
6570 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
6571 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
6572 | MODULE_LICENSE("GPL"); |