[linux-2.6-block.git] / drivers / net / dsa / mv88e6131.c

/*
 * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/list.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6xxx.h"

/*
 * Switch product IDs
 */
#define ID_6085		0x04a0
#define ID_6095		0x0950
#define ID_6131		0x1060

static char *mv88e6131_probe(struct mii_bus *bus, int sw_addr)
{
	int ret;

	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
	if (ret >= 0) {
		ret &= 0xfff0;
		if (ret == ID_6085)
			return "Marvell 88E6085";
		if (ret == ID_6095)
			return "Marvell 88E6095/88E6095F";
		if (ret == ID_6131)
			return "Marvell 88E6131";
	}

	return NULL;
}

static int mv88e6131_switch_reset(struct dsa_switch *ds)
{
	int i;
	int ret;

	/*
	 * Set all ports to the disabled state.
	 */
	for (i = 0; i < 11; i++) {
		ret = REG_READ(REG_PORT(i), 0x04);
		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	}

	/*
	 * Wait for transmit queues to drain.
	 */
	msleep(2);

	/*
	 * Reset the switch.
	 */
	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);

	/*
	 * Wait up to one second for reset to complete.
	 */
	for (i = 0; i < 1000; i++) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		if ((ret & 0xc800) == 0xc800)
			break;

		msleep(1);
	}
	if (i == 1000)
		return -ETIMEDOUT;

	return 0;
}

static int mv88e6131_setup_global(struct dsa_switch *ds)
{
	int ret;
	int i;

	/*
	 * Enable the PHY polling unit, don't discard packets with
	 * excessive collisions, use a weighted fair queueing scheme
	 * to arbitrate between packet queues, set the maximum frame
	 * size to 1632, and mask all interrupt sources.
	 */
	REG_WRITE(REG_GLOBAL, 0x04, 0x4400);

	/*
	 * Set the default address aging time to 5 minutes, and
	 * enable address learn messages to be sent to all message
	 * ports.
	 */
	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);

	/*
	 * Configure the priority mapping registers.
	 */
	ret = mv88e6xxx_config_prio(ds);
	if (ret < 0)
		return ret;

	/*
	 * Set the VLAN ethertype to 0x8100.
	 */
	REG_WRITE(REG_GLOBAL, 0x19, 0x8100);

	/*
	 * Disable ARP mirroring, and configure the upstream port as
	 * the port to which ingress and egress monitor frames are to
	 * be sent.
	 */
	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);

	/*
	 * Disable cascade port functionality unless this device
	 * is used in a cascade configuration, and set the switch's
	 * DSA device number.
	 */
	if (ds->dst->pd->nr_chips > 1)
		REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f));
	else
		REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));

	/*
	 * Send all frames with destination addresses matching
	 * 01:80:c2:00:00:0x to the CPU port.
	 */
	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);

	/*
	 * Ignore removed tag data on doubly tagged packets, disable
	 * flow control messages, force flow control priority to the
	 * highest, and send all special multicast frames to the CPU
	 * port at the highest priority.
	 */
	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);

	/*
	 * Program the DSA routing table.
	 */
	for (i = 0; i < 32; i++) {
		int nexthop;

		nexthop = 0x1f;
		if (i != ds->index && i < ds->dst->pd->nr_chips)
			nexthop = ds->pd->rtable[i] & 0x1f;

		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
	}

	/*
	 * Clear all trunk masks.
	 */
	for (i = 0; i < 8; i++)
		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);

	/*
	 * Clear all trunk mappings.
	 */
	for (i = 0; i < 16; i++)
		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));

	/*
	 * Force the priority of IGMP/MLD snoop frames and ARP frames
	 * to the highest setting.
	 */
	REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);

	return 0;
}

static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
{
	struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
	int addr = REG_PORT(p);
	u16 val;

	/*
	 * MAC Forcing register: don't force link, speed, duplex
	 * or flow control state to any particular values on physical
	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
	 * (100 Mb/s on 6085) full duplex.
	 */
	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
		if (ps->id == ID_6085)
			REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
		else
			REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
	else
		REG_WRITE(addr, 0x01, 0x0003);

	/*
	 * Port Control: disable Core Tag, disable Drop-on-Lock,
	 * transmit frames unmodified, disable Header mode,
	 * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and
	 * IP priority fields (IP prio has precedence), and set STP
	 * state to Forwarding.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts, and enable DSA tagging
	 * mode.
	 *
	 * If this is the link to another switch, use DSA tagging
	 * mode, but do not enable forwarding of unknown unicasts.
	 */
	val = 0x0433;
	if (p == dsa_upstream_port(ds)) {
		val |= 0x0104;
		/*
		 * On 6085, unknown multicast forward is controlled
		 * here rather than in Port Control 2 register.
		 */
		if (ps->id == ID_6085)
			val |= 0x0008;
	}
	if (ds->dsa_port_mask & (1 << p))
		val |= 0x0100;
	REG_WRITE(addr, 0x04, val);

	/*
	 * Port Control 1: disable trunking.  Also, if this is the
	 * CPU port, enable learn messages to be sent to this port.
	 */
	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);

	/*
	 * Port based VLAN map: give each port its own address
	 * database, allow the CPU port to talk to each of the 'real'
	 * ports, and allow each of the 'real' ports to only talk to
	 * the upstream port.
	 */
	val = (p & 0xf) << 12;
	if (dsa_is_cpu_port(ds, p))
		val |= ds->phys_port_mask;
	else
		val |= 1 << dsa_upstream_port(ds);
	REG_WRITE(addr, 0x06, val);

	/*
	 * Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
	REG_WRITE(addr, 0x07, 0x0000);

	/*
	 * Port Control 2: don't force a good FCS, don't use
	 * VLAN-based, source address-based or destination
	 * address-based priority overrides, don't let the switch
	 * add or strip 802.1q tags, don't discard tagged or
	 * untagged frames on this port, do a destination address
	 * lookup on received packets as usual, don't send a copy
	 * of all transmitted/received frames on this port to the
	 * CPU, and configure the upstream port number.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown multicast addresses.
	 */
	if (ps->id == ID_6085)
		/*
		 * on 6085, bits 3:0 are reserved, bit 6 control ARP
		 * mirroring, and multicast forward is handled in
		 * Port Control register.
		 */
		REG_WRITE(addr, 0x08, 0x0080);
	else {
		val = 0x0080 | dsa_upstream_port(ds);
		if (p == dsa_upstream_port(ds))
			val |= 0x0040;
		REG_WRITE(addr, 0x08, val);
	}

	/*
	 * Rate Control: disable ingress rate limiting.
	 */
	REG_WRITE(addr, 0x09, 0x0000);

	/*
	 * Rate Control 2: disable egress rate limiting.
	 */
	REG_WRITE(addr, 0x0a, 0x0000);

	/*
	 * Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
	REG_WRITE(addr, 0x0b, 1 << p);

	/*
	 * Tag Remap: use an identity 802.1p prio -> switch prio
	 * mapping.
	 */
	REG_WRITE(addr, 0x18, 0x3210);

	/*
	 * Tag Remap 2: use an identity 802.1p prio -> switch prio
	 * mapping.
	 */
	REG_WRITE(addr, 0x19, 0x7654);

	return 0;
}

static int mv88e6131_setup(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
	int i;
	int ret;

	mutex_init(&ps->smi_mutex);
	mv88e6xxx_ppu_state_init(ds);
	mutex_init(&ps->stats_mutex);

	ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;

	ret = mv88e6131_switch_reset(ds);
	if (ret < 0)
		return ret;

	/* @@@ initialise vtu and atu */

	ret = mv88e6131_setup_global(ds);
	if (ret < 0)
		return ret;

	for (i = 0; i < 11; i++) {
		ret = mv88e6131_setup_port(ds, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int mv88e6131_port_to_phy_addr(int port)
{
	if (port >= 0 && port <= 11)
		return port;
	return -1;
}

static int
mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
{
	int addr = mv88e6131_port_to_phy_addr(port);
	return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
}

static int
mv88e6131_phy_write(struct dsa_switch *ds,
			      int port, int regnum, u16 val)
{
	int addr = mv88e6131_port_to_phy_addr(port);
	return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
}

static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
	{ "in_good_octets", 8, 0x00, },
	{ "in_bad_octets", 4, 0x02, },
	{ "in_unicast", 4, 0x04, },
	{ "in_broadcasts", 4, 0x06, },
	{ "in_multicasts", 4, 0x07, },
	{ "in_pause", 4, 0x16, },
	{ "in_undersize", 4, 0x18, },
	{ "in_fragments", 4, 0x19, },
	{ "in_oversize", 4, 0x1a, },
	{ "in_jabber", 4, 0x1b, },
	{ "in_rx_error", 4, 0x1c, },
	{ "in_fcs_error", 4, 0x1d, },
	{ "out_octets", 8, 0x0e, },
	{ "out_unicast", 4, 0x10, },
	{ "out_broadcasts", 4, 0x13, },
	{ "out_multicasts", 4, 0x12, },
	{ "out_pause", 4, 0x15, },
	{ "excessive", 4, 0x11, },
	{ "collisions", 4, 0x1e, },
	{ "deferred", 4, 0x05, },
	{ "single", 4, 0x14, },
	{ "multiple", 4, 0x17, },
	{ "out_fcs_error", 4, 0x03, },
	{ "late", 4, 0x1f, },
	{ "hist_64bytes", 4, 0x08, },
	{ "hist_65_127bytes", 4, 0x09, },
	{ "hist_128_255bytes", 4, 0x0a, },
	{ "hist_256_511bytes", 4, 0x0b, },
	{ "hist_512_1023bytes", 4, 0x0c, },
	{ "hist_1024_max_bytes", 4, 0x0d, },
};

static void
mv88e6131_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
{
	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
			      mv88e6131_hw_stats, port, data);
}

static void
mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
				  int port, uint64_t *data)
{
	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
				    mv88e6131_hw_stats, port, data);
}

static int mv88e6131_get_sset_count(struct dsa_switch *ds)
{
	return ARRAY_SIZE(mv88e6131_hw_stats);
}

struct dsa_switch_driver mv88e6131_switch_driver = {
	.tag_protocol		= cpu_to_be16(ETH_P_DSA),
	.priv_size		= sizeof(struct mv88e6xxx_priv_state),
	.probe			= mv88e6131_probe,
	.setup			= mv88e6131_setup,
	.set_addr		= mv88e6xxx_set_addr_direct,
	.phy_read		= mv88e6131_phy_read,
	.phy_write		= mv88e6131_phy_write,
	.poll_link		= mv88e6xxx_poll_link,
	.get_strings		= mv88e6131_get_strings,
	.get_ethtool_stats	= mv88e6131_get_ethtool_stats,
	.get_sset_count		= mv88e6131_get_sset_count,
};

MODULE_ALIAS("platform:mv88e6085");
MODULE_ALIAS("platform:mv88e6095");
MODULE_ALIAS("platform:mv88e6095f");
MODULE_ALIAS("platform:mv88e6131");
Commit	Line	Data
2e5f0320	1	/*
076d3e10 LB	2	* net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
076d3e10 LB	3	* Copyright (c) 2008-2009 Marvell Semiconductor
2e5f0320 LB	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
	11	#include <linux/list.h>
	12	#include <linux/netdevice.h>
	13	#include <linux/phy.h>
c8f0b869	14	#include <net/dsa.h>
2e5f0320 LB	15	#include "mv88e6xxx.h"
2e5f0320 LB	16
ec80bfcb PK	17	/*
	18	* Switch product IDs
	19	*/
	20	#define ID_6085 0x04a0
	21	#define ID_6095 0x0950
	22	#define ID_6131 0x1060
	23
2e5f0320 LB	24	static char mv88e6131_probe(struct mii_bus bus, int sw_addr)
	25	{
	26	int ret;
	27
	28	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
	29	if (ret >= 0) {
	30	ret &= 0xfff0;
ec80bfcb PK	31	if (ret == ID_6085)
	32	return "Marvell 88E6085";
	33	if (ret == ID_6095)
076d3e10	34	return "Marvell 88E6095/88E6095F";
ec80bfcb	35	if (ret == ID_6131)
2e5f0320 LB	36	return "Marvell 88E6131";
	37	}
	38
	39	return NULL;
	40	}
	41
	42	static int mv88e6131_switch_reset(struct dsa_switch *ds)
	43	{
	44	int i;
	45	int ret;
	46
	47	/*
	48	* Set all ports to the disabled state.
	49	*/
076d3e10	50	for (i = 0; i < 11; i++) {
2e5f0320 LB	51	ret = REG_READ(REG_PORT(i), 0x04);
	52	REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	53	}
	54
	55	/*
	56	* Wait for transmit queues to drain.
	57	*/
	58	msleep(2);
	59
	60	/*
	61	* Reset the switch.
	62	*/
	63	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
	64
	65	/*
	66	* Wait up to one second for reset to complete.
	67	*/
	68	for (i = 0; i < 1000; i++) {
	69	ret = REG_READ(REG_GLOBAL, 0x00);
	70	if ((ret & 0xc800) == 0xc800)
	71	break;
	72
	73	msleep(1);
	74	}
	75	if (i == 1000)
	76	return -ETIMEDOUT;
	77
	78	return 0;
	79	}
	80
	81	static int mv88e6131_setup_global(struct dsa_switch *ds)
	82	{
	83	int ret;
	84	int i;
	85
	86	/*
	87	* Enable the PHY polling unit, don't discard packets with
	88	* excessive collisions, use a weighted fair queueing scheme
	89	* to arbitrate between packet queues, set the maximum frame
	90	* size to 1632, and mask all interrupt sources.
	91	*/
	92	REG_WRITE(REG_GLOBAL, 0x04, 0x4400);
	93
	94	/*
	95	* Set the default address aging time to 5 minutes, and
	96	* enable address learn messages to be sent to all message
	97	* ports.
	98	*/
	99	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
	100
	101	/*
	102	* Configure the priority mapping registers.
	103	*/
	104	ret = mv88e6xxx_config_prio(ds);
	105	if (ret < 0)
	106	return ret;
	107
	108	/*
	109	* Set the VLAN ethertype to 0x8100.
	110	*/
	111	REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
	112
	113	/*
e84665c9 LB	114	* Disable ARP mirroring, and configure the upstream port as
	115	* the port to which ingress and egress monitor frames are to
	116	* be sent.
2e5f0320	117	*/
e84665c9	118	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) \| 0x00f0);
2e5f0320 LB	119
2e5f0320 LB	120	/*
81399ec6 BG	121	* Disable cascade port functionality unless this device
81399ec6 BG	122	* is used in a cascade configuration, and set the switch's
e84665c9	123	* DSA device number.
2e5f0320	124	*/
81399ec6 BG	125	if (ds->dst->pd->nr_chips > 1)
	126	REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 \| (ds->index & 0x1f));
	127	else
	128	REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 \| (ds->index & 0x1f));
2e5f0320 LB	129
	130	/*
	131	* Send all frames with destination addresses matching
	132	* 01:80:c2:00:00:0x to the CPU port.
	133	*/
	134	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
	135
	136	/*
	137	* Ignore removed tag data on doubly tagged packets, disable
	138	* flow control messages, force flow control priority to the
	139	* highest, and send all special multicast frames to the CPU
25985edc	140	* port at the highest priority.
2e5f0320 LB	141	*/
	142	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
	143
	144	/*
e84665c9	145	* Program the DSA routing table.
2e5f0320	146	*/
e84665c9 LB	147	for (i = 0; i < 32; i++) {
	148	int nexthop;
	149
	150	nexthop = 0x1f;
	151	if (i != ds->index && i < ds->dst->pd->nr_chips)
	152	nexthop = ds->pd->rtable[i] & 0x1f;
	153
	154	REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 \| (i << 8) \| nexthop);
	155	}
2e5f0320 LB	156
	157	/*
	158	* Clear all trunk masks.
	159	*/
	160	for (i = 0; i < 8; i++)
076d3e10	161	REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 \| (i << 12) \| 0x7ff);
2e5f0320 LB	162
	163	/*
	164	* Clear all trunk mappings.
	165	*/
	166	for (i = 0; i < 16; i++)
	167	REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 \| (i << 11));
	168
	169	/*
	170	* Force the priority of IGMP/MLD snoop frames and ARP frames
	171	* to the highest setting.
	172	*/
	173	REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);
	174
	175	return 0;
	176	}
	177
	178	static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
	179	{
ec80bfcb	180	struct mv88e6xxx_priv_state ps = (void )(ds + 1);
2e5f0320	181	int addr = REG_PORT(p);
e84665c9	182	u16 val;
2e5f0320 LB	183
	184	/*
	185	* MAC Forcing register: don't force link, speed, duplex
076d3e10	186	* or flow control state to any particular values on physical
e84665c9	187	* ports, but force the CPU port and all DSA ports to 1000 Mb/s
ec80bfcb	188	* (100 Mb/s on 6085) full duplex.
2e5f0320	189	*/
e84665c9	190	if (dsa_is_cpu_port(ds, p) \|\| ds->dsa_port_mask & (1 << p))
ec80bfcb PK	191	if (ps->id == ID_6085)
	192	REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
	193	else
	194	REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
076d3e10 LB	195	else
076d3e10 LB	196	REG_WRITE(addr, 0x01, 0x0003);
2e5f0320 LB	197
	198	/*
	199	* Port Control: disable Core Tag, disable Drop-on-Lock,
	200	* transmit frames unmodified, disable Header mode,
	201	* enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
	202	* tunneling, determine priority by looking at 802.1p and
	203	* IP priority fields (IP prio has precedence), and set STP
e84665c9 LB	204	* state to Forwarding.
	205	*
	206	* If this is the upstream port for this switch, enable
	207	* forwarding of unknown unicasts, and enable DSA tagging
	208	* mode.
	209	*
	210	* If this is the link to another switch, use DSA tagging
	211	* mode, but do not enable forwarding of unknown unicasts.
2e5f0320	212	*/
e84665c9	213	val = 0x0433;
b3b27005	214	if (p == dsa_upstream_port(ds)) {
e84665c9	215	val \|= 0x0104;
b3b27005 PK	216	/*
	217	* On 6085, unknown multicast forward is controlled
	218	* here rather than in Port Control 2 register.
	219	*/
	220	if (ps->id == ID_6085)
	221	val \|= 0x0008;
	222	}
e84665c9 LB	223	if (ds->dsa_port_mask & (1 << p))
	224	val \|= 0x0100;
	225	REG_WRITE(addr, 0x04, val);
2e5f0320 LB	226
	227	/*
	228	* Port Control 1: disable trunking. Also, if this is the
	229	* CPU port, enable learn messages to be sent to this port.
	230	*/
e84665c9	231	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
2e5f0320 LB	232
	233	/*
	234	* Port based VLAN map: give each port its own address
	235	* database, allow the CPU port to talk to each of the 'real'
	236	* ports, and allow each of the 'real' ports to only talk to
e84665c9	237	* the upstream port.
2e5f0320	238	*/
e84665c9 LB	239	val = (p & 0xf) << 12;
	240	if (dsa_is_cpu_port(ds, p))
	241	val \|= ds->phys_port_mask;
	242	else
	243	val \|= 1 << dsa_upstream_port(ds);
	244	REG_WRITE(addr, 0x06, val);
2e5f0320 LB	245
	246	/*
	247	* Default VLAN ID and priority: don't set a default VLAN
	248	* ID, and set the default packet priority to zero.
	249	*/
	250	REG_WRITE(addr, 0x07, 0x0000);
	251
	252	/*
	253	* Port Control 2: don't force a good FCS, don't use
	254	* VLAN-based, source address-based or destination
	255	* address-based priority overrides, don't let the switch
	256	* add or strip 802.1q tags, don't discard tagged or
	257	* untagged frames on this port, do a destination address
	258	* lookup on received packets as usual, don't send a copy
	259	* of all transmitted/received frames on this port to the
e84665c9 LB	260	* CPU, and configure the upstream port number.
	261	*
	262	* If this is the upstream port for this switch, enable
	263	* forwarding of unknown multicast addresses.
2e5f0320	264	*/
b3b27005 PK	265	if (ps->id == ID_6085)
	266	/*
	267	* on 6085, bits 3:0 are reserved, bit 6 control ARP
	268	* mirroring, and multicast forward is handled in
	269	* Port Control register.
	270	*/
	271	REG_WRITE(addr, 0x08, 0x0080);
	272	else {
	273	val = 0x0080 \| dsa_upstream_port(ds);
	274	if (p == dsa_upstream_port(ds))
	275	val \|= 0x0040;
	276	REG_WRITE(addr, 0x08, val);
	277	}
2e5f0320 LB	278
	279	/*
	280	* Rate Control: disable ingress rate limiting.
	281	*/
	282	REG_WRITE(addr, 0x09, 0x0000);
	283
	284	/*
	285	* Rate Control 2: disable egress rate limiting.
	286	*/
	287	REG_WRITE(addr, 0x0a, 0x0000);
	288
	289	/*
	290	* Port Association Vector: when learning source addresses
	291	* of packets, add the address to the address database using
	292	* a port bitmap that has only the bit for this port set and
	293	* the other bits clear.
	294	*/
	295	REG_WRITE(addr, 0x0b, 1 << p);
	296
	297	/*
	298	* Tag Remap: use an identity 802.1p prio -> switch prio
	299	* mapping.
	300	*/
	301	REG_WRITE(addr, 0x18, 0x3210);
	302
	303	/*
	304	* Tag Remap 2: use an identity 802.1p prio -> switch prio
	305	* mapping.
	306	*/
	307	REG_WRITE(addr, 0x19, 0x7654);
	308
	309	return 0;
	310	}
	311
	312	static int mv88e6131_setup(struct dsa_switch *ds)
	313	{
	314	struct mv88e6xxx_priv_state ps = (void )(ds + 1);
	315	int i;
	316	int ret;
	317
	318	mutex_init(&ps->smi_mutex);
	319	mv88e6xxx_ppu_state_init(ds);
	320	mutex_init(&ps->stats_mutex);
	321
ec80bfcb PK	322	ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
ec80bfcb PK	323
2e5f0320 LB	324	ret = mv88e6131_switch_reset(ds);
	325	if (ret < 0)
	326	return ret;
	327
	328	/* @@@ initialise vtu and atu */
	329
	330	ret = mv88e6131_setup_global(ds);
	331	if (ret < 0)
	332	return ret;
	333
076d3e10	334	for (i = 0; i < 11; i++) {
2e5f0320 LB	335	ret = mv88e6131_setup_port(ds, i);
	336	if (ret < 0)
	337	return ret;
	338	}
	339
	340	return 0;
	341	}
	342
	343	static int mv88e6131_port_to_phy_addr(int port)
	344	{
076d3e10	345	if (port >= 0 && port <= 11)
2e5f0320 LB	346	return port;
	347	return -1;
	348	}
	349
	350	static int
	351	mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
	352	{
	353	int addr = mv88e6131_port_to_phy_addr(port);
	354	return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
	355	}
	356
	357	static int
	358	mv88e6131_phy_write(struct dsa_switch *ds,
	359	int port, int regnum, u16 val)
	360	{
	361	int addr = mv88e6131_port_to_phy_addr(port);
	362	return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
	363	}
	364
	365	static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
	366	{ "in_good_octets", 8, 0x00, },
	367	{ "in_bad_octets", 4, 0x02, },
	368	{ "in_unicast", 4, 0x04, },
	369	{ "in_broadcasts", 4, 0x06, },
	370	{ "in_multicasts", 4, 0x07, },
	371	{ "in_pause", 4, 0x16, },
	372	{ "in_undersize", 4, 0x18, },
	373	{ "in_fragments", 4, 0x19, },
	374	{ "in_oversize", 4, 0x1a, },
	375	{ "in_jabber", 4, 0x1b, },
	376	{ "in_rx_error", 4, 0x1c, },
	377	{ "in_fcs_error", 4, 0x1d, },
	378	{ "out_octets", 8, 0x0e, },
	379	{ "out_unicast", 4, 0x10, },
	380	{ "out_broadcasts", 4, 0x13, },
	381	{ "out_multicasts", 4, 0x12, },
	382	{ "out_pause", 4, 0x15, },
	383	{ "excessive", 4, 0x11, },
	384	{ "collisions", 4, 0x1e, },
	385	{ "deferred", 4, 0x05, },
	386	{ "single", 4, 0x14, },
	387	{ "multiple", 4, 0x17, },
	388	{ "out_fcs_error", 4, 0x03, },
	389	{ "late", 4, 0x1f, },
	390	{ "hist_64bytes", 4, 0x08, },
	391	{ "hist_65_127bytes", 4, 0x09, },
	392	{ "hist_128_255bytes", 4, 0x0a, },
	393	{ "hist_256_511bytes", 4, 0x0b, },
	394	{ "hist_512_1023bytes", 4, 0x0c, },
	395	{ "hist_1024_max_bytes", 4, 0x0d, },
	396	};
	397
	398	static void
	399	mv88e6131_get_strings(struct dsa_switch ds, int port, uint8_t data)
	400	{
	401	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
	402	mv88e6131_hw_stats, port, data);
	403	}
	404
	405	static void
	406	mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
	407	int port, uint64_t *data)
	408	{
	409	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
410	mv88e6131_hw_stats, port, data);
411	}
412
413	static int mv88e6131_get_sset_count(struct dsa_switch *ds)
414	{
415	return ARRAY_SIZE(mv88e6131_hw_stats);
416	}
417
98e67308	418	struct dsa_switch_driver mv88e6131_switch_driver = {
09640e63	419	.tag_protocol = cpu_to_be16(ETH_P_DSA),
2e5f0320 LB	420	.priv_size = sizeof(struct mv88e6xxx_priv_state),
	421	.probe = mv88e6131_probe,
	422	.setup = mv88e6131_setup,
	423	.set_addr = mv88e6xxx_set_addr_direct,
	424	.phy_read = mv88e6131_phy_read,
	425	.phy_write = mv88e6131_phy_write,
	426	.poll_link = mv88e6xxx_poll_link,
	427	.get_strings = mv88e6131_get_strings,
	428	.get_ethtool_stats = mv88e6131_get_ethtool_stats,
	429	.get_sset_count = mv88e6131_get_sset_count,
	430	};
3d825ede BH	431
	432	MODULE_ALIAS("platform:mv88e6085");
	433	MODULE_ALIAS("platform:mv88e6095");
	434	MODULE_ALIAS("platform:mv88e6095f");
	435	MODULE_ALIAS("platform:mv88e6131");