[linux-2.6-block.git] / drivers / net / dsa / mv88e6131.c

/*
 * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
 * Copyright (c) 2008-2009 Marvell Semiconductor
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/list.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/phy.h>
#include <net/dsa.h>
#include "mv88e6xxx.h"

/* Switch product IDs */
#define ID_6085		0x04a0
#define ID_6095		0x0950
#define ID_6131		0x1060

static char *mv88e6131_probe(struct mii_bus *bus, int sw_addr)
{
	int ret;

	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
	if (ret >= 0) {
		ret &= 0xfff0;
		if (ret == ID_6085)
			return "Marvell 88E6085";
		if (ret == ID_6095)
			return "Marvell 88E6095/88E6095F";
		if (ret == ID_6131)
			return "Marvell 88E6131";
	}

	return NULL;
}

static int mv88e6131_switch_reset(struct dsa_switch *ds)
{
	int i;
	int ret;

	/* Set all ports to the disabled state. */
	for (i = 0; i < 11; i++) {
		ret = REG_READ(REG_PORT(i), 0x04);
		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	}

	/* Wait for transmit queues to drain. */
	msleep(2);

	/* Reset the switch. */
	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);

	/* Wait up to one second for reset to complete. */
	for (i = 0; i < 1000; i++) {
		ret = REG_READ(REG_GLOBAL, 0x00);
		if ((ret & 0xc800) == 0xc800)
			break;

		msleep(1);
	}
	if (i == 1000)
		return -ETIMEDOUT;

	return 0;
}

static int mv88e6131_setup_global(struct dsa_switch *ds)
{
	int ret;
	int i;

	/* Enable the PHY polling unit, don't discard packets with
	 * excessive collisions, use a weighted fair queueing scheme
	 * to arbitrate between packet queues, set the maximum frame
	 * size to 1632, and mask all interrupt sources.
	 */
	REG_WRITE(REG_GLOBAL, 0x04, 0x4400);

	/* Set the default address aging time to 5 minutes, and
	 * enable address learn messages to be sent to all message
	 * ports.
	 */
	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);

	/* Configure the priority mapping registers. */
	ret = mv88e6xxx_config_prio(ds);
	if (ret < 0)
		return ret;

	/* Set the VLAN ethertype to 0x8100. */
	REG_WRITE(REG_GLOBAL, 0x19, 0x8100);

	/* Disable ARP mirroring, and configure the upstream port as
	 * the port to which ingress and egress monitor frames are to
	 * be sent.
	 */
	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);

	/* Disable cascade port functionality unless this device
	 * is used in a cascade configuration, and set the switch's
	 * DSA device number.
	 */
	if (ds->dst->pd->nr_chips > 1)
		REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f));
	else
		REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));

	/* Send all frames with destination addresses matching
	 * 01:80:c2:00:00:0x to the CPU port.
	 */
	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);

	/* Ignore removed tag data on doubly tagged packets, disable
	 * flow control messages, force flow control priority to the
	 * highest, and send all special multicast frames to the CPU
	 * port at the highest priority.
	 */
	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);

	/* Program the DSA routing table. */
	for (i = 0; i < 32; i++) {
		int nexthop;

		nexthop = 0x1f;
		if (i != ds->index && i < ds->dst->pd->nr_chips)
			nexthop = ds->pd->rtable[i] & 0x1f;

		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
	}

	/* Clear all trunk masks. */
	for (i = 0; i < 8; i++)
		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);

	/* Clear all trunk mappings. */
	for (i = 0; i < 16; i++)
		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));

	/* Force the priority of IGMP/MLD snoop frames and ARP frames
	 * to the highest setting.
	 */
	REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);

	return 0;
}

static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
{
	struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
	int addr = REG_PORT(p);
	u16 val;

	/* MAC Forcing register: don't force link, speed, duplex
	 * or flow control state to any particular values on physical
	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
	 * (100 Mb/s on 6085) full duplex.
	 */
	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
		if (ps->id == ID_6085)
			REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
		else
			REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
	else
		REG_WRITE(addr, 0x01, 0x0003);

	/* Port Control: disable Core Tag, disable Drop-on-Lock,
	 * transmit frames unmodified, disable Header mode,
	 * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
	 * tunneling, determine priority by looking at 802.1p and
	 * IP priority fields (IP prio has precedence), and set STP
	 * state to Forwarding.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown unicasts, and enable DSA tagging
	 * mode.
	 *
	 * If this is the link to another switch, use DSA tagging
	 * mode, but do not enable forwarding of unknown unicasts.
	 */
	val = 0x0433;
	if (p == dsa_upstream_port(ds)) {
		val |= 0x0104;
		/* On 6085, unknown multicast forward is controlled
		 * here rather than in Port Control 2 register.
		 */
		if (ps->id == ID_6085)
			val |= 0x0008;
	}
	if (ds->dsa_port_mask & (1 << p))
		val |= 0x0100;
	REG_WRITE(addr, 0x04, val);

	/* Port Control 1: disable trunking.  Also, if this is the
	 * CPU port, enable learn messages to be sent to this port.
	 */
	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);

	/* Port based VLAN map: give each port its own address
	 * database, allow the CPU port to talk to each of the 'real'
	 * ports, and allow each of the 'real' ports to only talk to
	 * the upstream port.
	 */
	val = (p & 0xf) << 12;
	if (dsa_is_cpu_port(ds, p))
		val |= ds->phys_port_mask;
	else
		val |= 1 << dsa_upstream_port(ds);
	REG_WRITE(addr, 0x06, val);

	/* Default VLAN ID and priority: don't set a default VLAN
	 * ID, and set the default packet priority to zero.
	 */
	REG_WRITE(addr, 0x07, 0x0000);

	/* Port Control 2: don't force a good FCS, don't use
	 * VLAN-based, source address-based or destination
	 * address-based priority overrides, don't let the switch
	 * add or strip 802.1q tags, don't discard tagged or
	 * untagged frames on this port, do a destination address
	 * lookup on received packets as usual, don't send a copy
	 * of all transmitted/received frames on this port to the
	 * CPU, and configure the upstream port number.
	 *
	 * If this is the upstream port for this switch, enable
	 * forwarding of unknown multicast addresses.
	 */
	if (ps->id == ID_6085)
		/* on 6085, bits 3:0 are reserved, bit 6 control ARP
		 * mirroring, and multicast forward is handled in
		 * Port Control register.
		 */
		REG_WRITE(addr, 0x08, 0x0080);
	else {
		val = 0x0080 | dsa_upstream_port(ds);
		if (p == dsa_upstream_port(ds))
			val |= 0x0040;
		REG_WRITE(addr, 0x08, val);
	}

	/* Rate Control: disable ingress rate limiting. */
	REG_WRITE(addr, 0x09, 0x0000);

	/* Rate Control 2: disable egress rate limiting. */
	REG_WRITE(addr, 0x0a, 0x0000);

	/* Port Association Vector: when learning source addresses
	 * of packets, add the address to the address database using
	 * a port bitmap that has only the bit for this port set and
	 * the other bits clear.
	 */
	REG_WRITE(addr, 0x0b, 1 << p);

	/* Tag Remap: use an identity 802.1p prio -> switch prio
	 * mapping.
	 */
	REG_WRITE(addr, 0x18, 0x3210);

	/* Tag Remap 2: use an identity 802.1p prio -> switch prio
	 * mapping.
	 */
	REG_WRITE(addr, 0x19, 0x7654);

	return 0;
}

static int mv88e6131_setup(struct dsa_switch *ds)
{
	struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
	int i;
	int ret;

	mutex_init(&ps->smi_mutex);
	mv88e6xxx_ppu_state_init(ds);
	mutex_init(&ps->stats_mutex);

	ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;

	ret = mv88e6131_switch_reset(ds);
	if (ret < 0)
		return ret;

	/* @@@ initialise vtu and atu */

	ret = mv88e6131_setup_global(ds);
	if (ret < 0)
		return ret;

	for (i = 0; i < 11; i++) {
		ret = mv88e6131_setup_port(ds, i);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int mv88e6131_port_to_phy_addr(int port)
{
	if (port >= 0 && port <= 11)
		return port;
	return -1;
}

static int
mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
{
	int addr = mv88e6131_port_to_phy_addr(port);
	return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
}

static int
mv88e6131_phy_write(struct dsa_switch *ds,
			      int port, int regnum, u16 val)
{
	int addr = mv88e6131_port_to_phy_addr(port);
	return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
}

static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
	{ "in_good_octets", 8, 0x00, },
	{ "in_bad_octets", 4, 0x02, },
	{ "in_unicast", 4, 0x04, },
	{ "in_broadcasts", 4, 0x06, },
	{ "in_multicasts", 4, 0x07, },
	{ "in_pause", 4, 0x16, },
	{ "in_undersize", 4, 0x18, },
	{ "in_fragments", 4, 0x19, },
	{ "in_oversize", 4, 0x1a, },
	{ "in_jabber", 4, 0x1b, },
	{ "in_rx_error", 4, 0x1c, },
	{ "in_fcs_error", 4, 0x1d, },
	{ "out_octets", 8, 0x0e, },
	{ "out_unicast", 4, 0x10, },
	{ "out_broadcasts", 4, 0x13, },
	{ "out_multicasts", 4, 0x12, },
	{ "out_pause", 4, 0x15, },
	{ "excessive", 4, 0x11, },
	{ "collisions", 4, 0x1e, },
	{ "deferred", 4, 0x05, },
	{ "single", 4, 0x14, },
	{ "multiple", 4, 0x17, },
	{ "out_fcs_error", 4, 0x03, },
	{ "late", 4, 0x1f, },
	{ "hist_64bytes", 4, 0x08, },
	{ "hist_65_127bytes", 4, 0x09, },
	{ "hist_128_255bytes", 4, 0x0a, },
	{ "hist_256_511bytes", 4, 0x0b, },
	{ "hist_512_1023bytes", 4, 0x0c, },
	{ "hist_1024_max_bytes", 4, 0x0d, },
};

static void
mv88e6131_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
{
	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
			      mv88e6131_hw_stats, port, data);
}

static void
mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
				  int port, uint64_t *data)
{
	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
				    mv88e6131_hw_stats, port, data);
}

static int mv88e6131_get_sset_count(struct dsa_switch *ds)
{
	return ARRAY_SIZE(mv88e6131_hw_stats);
}

struct dsa_switch_driver mv88e6131_switch_driver = {
	.tag_protocol		= cpu_to_be16(ETH_P_DSA),
	.priv_size		= sizeof(struct mv88e6xxx_priv_state),
	.probe			= mv88e6131_probe,
	.setup			= mv88e6131_setup,
	.set_addr		= mv88e6xxx_set_addr_direct,
	.phy_read		= mv88e6131_phy_read,
	.phy_write		= mv88e6131_phy_write,
	.poll_link		= mv88e6xxx_poll_link,
	.get_strings		= mv88e6131_get_strings,
	.get_ethtool_stats	= mv88e6131_get_ethtool_stats,
	.get_sset_count		= mv88e6131_get_sset_count,
};

MODULE_ALIAS("platform:mv88e6085");
MODULE_ALIAS("platform:mv88e6095");
MODULE_ALIAS("platform:mv88e6095f");
MODULE_ALIAS("platform:mv88e6131");
Commit	Line	Data
2e5f0320	1	/*
076d3e10 LB	2	* net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
076d3e10 LB	3	* Copyright (c) 2008-2009 Marvell Semiconductor
2e5f0320 LB	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*/
	10
	11	#include <linux/list.h>
2bbba277	12	#include <linux/module.h>
2e5f0320 LB	13	#include <linux/netdevice.h>
2e5f0320 LB	14	#include <linux/phy.h>
c8f0b869	15	#include <net/dsa.h>
2e5f0320 LB	16	#include "mv88e6xxx.h"
2e5f0320 LB	17
3675c8d7	18	/* Switch product IDs */
ec80bfcb PK	19	#define ID_6085 0x04a0
	20	#define ID_6095 0x0950
	21	#define ID_6131 0x1060
	22
2e5f0320 LB	23	static char mv88e6131_probe(struct mii_bus bus, int sw_addr)
	24	{
	25	int ret;
	26
	27	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
	28	if (ret >= 0) {
	29	ret &= 0xfff0;
ec80bfcb PK	30	if (ret == ID_6085)
	31	return "Marvell 88E6085";
	32	if (ret == ID_6095)
076d3e10	33	return "Marvell 88E6095/88E6095F";
ec80bfcb	34	if (ret == ID_6131)
2e5f0320 LB	35	return "Marvell 88E6131";
	36	}
	37
	38	return NULL;
	39	}
	40
	41	static int mv88e6131_switch_reset(struct dsa_switch *ds)
	42	{
	43	int i;
	44	int ret;
	45
3675c8d7	46	/* Set all ports to the disabled state. */
076d3e10	47	for (i = 0; i < 11; i++) {
2e5f0320 LB	48	ret = REG_READ(REG_PORT(i), 0x04);
	49	REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
	50	}
	51
3675c8d7	52	/* Wait for transmit queues to drain. */
2e5f0320 LB	53	msleep(2);
2e5f0320 LB	54
3675c8d7	55	/* Reset the switch. */
2e5f0320 LB	56	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2e5f0320 LB	57
3675c8d7	58	/* Wait up to one second for reset to complete. */
2e5f0320 LB	59	for (i = 0; i < 1000; i++) {
	60	ret = REG_READ(REG_GLOBAL, 0x00);
	61	if ((ret & 0xc800) == 0xc800)
	62	break;
	63
	64	msleep(1);
	65	}
	66	if (i == 1000)
	67	return -ETIMEDOUT;
	68
	69	return 0;
	70	}
	71
	72	static int mv88e6131_setup_global(struct dsa_switch *ds)
	73	{
	74	int ret;
	75	int i;
	76
3675c8d7	77	/* Enable the PHY polling unit, don't discard packets with
2e5f0320 LB	78	* excessive collisions, use a weighted fair queueing scheme
	79	* to arbitrate between packet queues, set the maximum frame
	80	* size to 1632, and mask all interrupt sources.
	81	*/
	82	REG_WRITE(REG_GLOBAL, 0x04, 0x4400);
	83
3675c8d7	84	/* Set the default address aging time to 5 minutes, and
2e5f0320 LB	85	* enable address learn messages to be sent to all message
	86	* ports.
	87	*/
	88	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
	89
3675c8d7	90	/* Configure the priority mapping registers. */
2e5f0320 LB	91	ret = mv88e6xxx_config_prio(ds);
	92	if (ret < 0)
	93	return ret;
	94
3675c8d7	95	/* Set the VLAN ethertype to 0x8100. */
2e5f0320 LB	96	REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
2e5f0320 LB	97
3675c8d7	98	/* Disable ARP mirroring, and configure the upstream port as
e84665c9 LB	99	* the port to which ingress and egress monitor frames are to
e84665c9 LB	100	* be sent.
2e5f0320	101	*/
e84665c9	102	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) \| 0x00f0);
2e5f0320	103
3675c8d7	104	/* Disable cascade port functionality unless this device
81399ec6	105	* is used in a cascade configuration, and set the switch's
e84665c9	106	* DSA device number.
2e5f0320	107	*/
81399ec6 BG	108	if (ds->dst->pd->nr_chips > 1)
	109	REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 \| (ds->index & 0x1f));
	110	else
	111	REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 \| (ds->index & 0x1f));
2e5f0320	112
3675c8d7	113	/* Send all frames with destination addresses matching
2e5f0320 LB	114	* 01:80:c2:00:00:0x to the CPU port.
	115	*/
	116	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
	117
3675c8d7	118	/* Ignore removed tag data on doubly tagged packets, disable
2e5f0320 LB	119	* flow control messages, force flow control priority to the
2e5f0320 LB	120	* highest, and send all special multicast frames to the CPU
25985edc	121	* port at the highest priority.
2e5f0320 LB	122	*/
	123	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
	124
3675c8d7	125	/* Program the DSA routing table. */
e84665c9 LB	126	for (i = 0; i < 32; i++) {
	127	int nexthop;
	128
	129	nexthop = 0x1f;
	130	if (i != ds->index && i < ds->dst->pd->nr_chips)
	131	nexthop = ds->pd->rtable[i] & 0x1f;
	132
	133	REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 \| (i << 8) \| nexthop);
	134	}
2e5f0320	135
3675c8d7	136	/* Clear all trunk masks. */
2e5f0320	137	for (i = 0; i < 8; i++)
076d3e10	138	REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 \| (i << 12) \| 0x7ff);
2e5f0320	139
3675c8d7	140	/* Clear all trunk mappings. */
2e5f0320 LB	141	for (i = 0; i < 16; i++)
	142	REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 \| (i << 11));
	143
3675c8d7	144	/* Force the priority of IGMP/MLD snoop frames and ARP frames
2e5f0320 LB	145	* to the highest setting.
	146	*/
	147	REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);
	148
	149	return 0;
	150	}
	151
	152	static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
	153	{
ec80bfcb	154	struct mv88e6xxx_priv_state ps = (void )(ds + 1);
2e5f0320	155	int addr = REG_PORT(p);
e84665c9	156	u16 val;
2e5f0320	157
3675c8d7	158	/* MAC Forcing register: don't force link, speed, duplex
076d3e10	159	* or flow control state to any particular values on physical
e84665c9	160	* ports, but force the CPU port and all DSA ports to 1000 Mb/s
ec80bfcb	161	* (100 Mb/s on 6085) full duplex.
2e5f0320	162	*/
e84665c9	163	if (dsa_is_cpu_port(ds, p) \|\| ds->dsa_port_mask & (1 << p))
ec80bfcb PK	164	if (ps->id == ID_6085)
	165	REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
	166	else
	167	REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
076d3e10 LB	168	else
076d3e10 LB	169	REG_WRITE(addr, 0x01, 0x0003);
2e5f0320	170
3675c8d7	171	/* Port Control: disable Core Tag, disable Drop-on-Lock,
2e5f0320 LB	172	* transmit frames unmodified, disable Header mode,
	173	* enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
	174	* tunneling, determine priority by looking at 802.1p and
	175	* IP priority fields (IP prio has precedence), and set STP
e84665c9 LB	176	* state to Forwarding.
	177	*
	178	* If this is the upstream port for this switch, enable
	179	* forwarding of unknown unicasts, and enable DSA tagging
	180	* mode.
	181	*
	182	* If this is the link to another switch, use DSA tagging
	183	* mode, but do not enable forwarding of unknown unicasts.
2e5f0320	184	*/
e84665c9	185	val = 0x0433;
b3b27005	186	if (p == dsa_upstream_port(ds)) {
e84665c9	187	val \|= 0x0104;
3675c8d7	188	/* On 6085, unknown multicast forward is controlled
b3b27005 PK	189	* here rather than in Port Control 2 register.
	190	*/
	191	if (ps->id == ID_6085)
	192	val \|= 0x0008;
	193	}
e84665c9 LB	194	if (ds->dsa_port_mask & (1 << p))
	195	val \|= 0x0100;
	196	REG_WRITE(addr, 0x04, val);
2e5f0320	197
3675c8d7	198	/* Port Control 1: disable trunking. Also, if this is the
2e5f0320 LB	199	* CPU port, enable learn messages to be sent to this port.
2e5f0320 LB	200	*/
e84665c9	201	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
2e5f0320	202
3675c8d7	203	/* Port based VLAN map: give each port its own address
2e5f0320 LB	204	* database, allow the CPU port to talk to each of the 'real'
2e5f0320 LB	205	* ports, and allow each of the 'real' ports to only talk to
e84665c9	206	* the upstream port.
2e5f0320	207	*/
e84665c9 LB	208	val = (p & 0xf) << 12;
	209	if (dsa_is_cpu_port(ds, p))
	210	val \|= ds->phys_port_mask;
	211	else
	212	val \|= 1 << dsa_upstream_port(ds);
	213	REG_WRITE(addr, 0x06, val);
2e5f0320	214
3675c8d7	215	/* Default VLAN ID and priority: don't set a default VLAN
2e5f0320 LB	216	* ID, and set the default packet priority to zero.
	217	*/
	218	REG_WRITE(addr, 0x07, 0x0000);
	219
3675c8d7	220	/* Port Control 2: don't force a good FCS, don't use
2e5f0320 LB	221	* VLAN-based, source address-based or destination
	222	* address-based priority overrides, don't let the switch
	223	* add or strip 802.1q tags, don't discard tagged or
	224	* untagged frames on this port, do a destination address
	225	* lookup on received packets as usual, don't send a copy
	226	* of all transmitted/received frames on this port to the
e84665c9 LB	227	* CPU, and configure the upstream port number.
	228	*
	229	* If this is the upstream port for this switch, enable
	230	* forwarding of unknown multicast addresses.
2e5f0320	231	*/
b3b27005	232	if (ps->id == ID_6085)
3675c8d7	233	/* on 6085, bits 3:0 are reserved, bit 6 control ARP
b3b27005 PK	234	* mirroring, and multicast forward is handled in
	235	* Port Control register.
	236	*/
	237	REG_WRITE(addr, 0x08, 0x0080);
	238	else {
	239	val = 0x0080 \| dsa_upstream_port(ds);
	240	if (p == dsa_upstream_port(ds))
	241	val \|= 0x0040;
	242	REG_WRITE(addr, 0x08, val);
	243	}
2e5f0320	244
3675c8d7	245	/* Rate Control: disable ingress rate limiting. */
2e5f0320 LB	246	REG_WRITE(addr, 0x09, 0x0000);
2e5f0320 LB	247
3675c8d7	248	/* Rate Control 2: disable egress rate limiting. */
2e5f0320 LB	249	REG_WRITE(addr, 0x0a, 0x0000);
2e5f0320 LB	250
3675c8d7	251	/* Port Association Vector: when learning source addresses
2e5f0320 LB	252	* of packets, add the address to the address database using
	253	* a port bitmap that has only the bit for this port set and
	254	* the other bits clear.
	255	*/
	256	REG_WRITE(addr, 0x0b, 1 << p);
	257
3675c8d7	258	/* Tag Remap: use an identity 802.1p prio -> switch prio
2e5f0320 LB	259	* mapping.
	260	*/
	261	REG_WRITE(addr, 0x18, 0x3210);
	262
3675c8d7	263	/* Tag Remap 2: use an identity 802.1p prio -> switch prio
2e5f0320 LB	264	* mapping.
	265	*/
	266	REG_WRITE(addr, 0x19, 0x7654);
	267
	268	return 0;
	269	}
	270
	271	static int mv88e6131_setup(struct dsa_switch *ds)
	272	{
	273	struct mv88e6xxx_priv_state ps = (void )(ds + 1);
	274	int i;
	275	int ret;
	276
	277	mutex_init(&ps->smi_mutex);
	278	mv88e6xxx_ppu_state_init(ds);
	279	mutex_init(&ps->stats_mutex);
	280
ec80bfcb PK	281	ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
ec80bfcb PK	282
2e5f0320 LB	283	ret = mv88e6131_switch_reset(ds);
	284	if (ret < 0)
	285	return ret;
	286
	287	/* @@@ initialise vtu and atu */
	288
	289	ret = mv88e6131_setup_global(ds);
	290	if (ret < 0)
	291	return ret;
	292
076d3e10	293	for (i = 0; i < 11; i++) {
2e5f0320 LB	294	ret = mv88e6131_setup_port(ds, i);
	295	if (ret < 0)
	296	return ret;
	297	}
	298
	299	return 0;
	300	}
	301
	302	static int mv88e6131_port_to_phy_addr(int port)
	303	{
076d3e10	304	if (port >= 0 && port <= 11)
2e5f0320 LB	305	return port;
	306	return -1;
	307	}
	308
	309	static int
	310	mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
	311	{
	312	int addr = mv88e6131_port_to_phy_addr(port);
	313	return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
	314	}
	315
	316	static int
	317	mv88e6131_phy_write(struct dsa_switch *ds,
	318	int port, int regnum, u16 val)
	319	{
	320	int addr = mv88e6131_port_to_phy_addr(port);
	321	return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
	322	}
	323
	324	static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
	325	{ "in_good_octets", 8, 0x00, },
	326	{ "in_bad_octets", 4, 0x02, },
	327	{ "in_unicast", 4, 0x04, },
	328	{ "in_broadcasts", 4, 0x06, },
	329	{ "in_multicasts", 4, 0x07, },
	330	{ "in_pause", 4, 0x16, },
	331	{ "in_undersize", 4, 0x18, },
	332	{ "in_fragments", 4, 0x19, },
	333	{ "in_oversize", 4, 0x1a, },
	334	{ "in_jabber", 4, 0x1b, },
	335	{ "in_rx_error", 4, 0x1c, },
	336	{ "in_fcs_error", 4, 0x1d, },
	337	{ "out_octets", 8, 0x0e, },
	338	{ "out_unicast", 4, 0x10, },
	339	{ "out_broadcasts", 4, 0x13, },
	340	{ "out_multicasts", 4, 0x12, },
	341	{ "out_pause", 4, 0x15, },
	342	{ "excessive", 4, 0x11, },
	343	{ "collisions", 4, 0x1e, },
	344	{ "deferred", 4, 0x05, },
	345	{ "single", 4, 0x14, },
	346	{ "multiple", 4, 0x17, },
	347	{ "out_fcs_error", 4, 0x03, },
	348	{ "late", 4, 0x1f, },
	349	{ "hist_64bytes", 4, 0x08, },
	350	{ "hist_65_127bytes", 4, 0x09, },
	351	{ "hist_128_255bytes", 4, 0x0a, },
	352	{ "hist_256_511bytes", 4, 0x0b, },
	353	{ "hist_512_1023bytes", 4, 0x0c, },
	354	{ "hist_1024_max_bytes", 4, 0x0d, },
	355	};
	356
	357	static void
	358	mv88e6131_get_strings(struct dsa_switch ds, int port, uint8_t data)
	359	{
	360	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
	361	mv88e6131_hw_stats, port, data);
	362	}
	363
	364	static void
	365	mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
	366	int port, uint64_t *data)
	367	{
	368	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
369	mv88e6131_hw_stats, port, data);
370	}
371
372	static int mv88e6131_get_sset_count(struct dsa_switch *ds)
373	{
374	return ARRAY_SIZE(mv88e6131_hw_stats);
375	}
376
98e67308	377	struct dsa_switch_driver mv88e6131_switch_driver = {
09640e63	378	.tag_protocol = cpu_to_be16(ETH_P_DSA),
2e5f0320 LB	379	.priv_size = sizeof(struct mv88e6xxx_priv_state),
	380	.probe = mv88e6131_probe,
	381	.setup = mv88e6131_setup,
	382	.set_addr = mv88e6xxx_set_addr_direct,
	383	.phy_read = mv88e6131_phy_read,
	384	.phy_write = mv88e6131_phy_write,
	385	.poll_link = mv88e6xxx_poll_link,
	386	.get_strings = mv88e6131_get_strings,
	387	.get_ethtool_stats = mv88e6131_get_ethtool_stats,
	388	.get_sset_count = mv88e6131_get_sset_count,
	389	};
3d825ede BH	390
	391	MODULE_ALIAS("platform:mv88e6085");
	392	MODULE_ALIAS("platform:mv88e6095");
	393	MODULE_ALIAS("platform:mv88e6095f");
	394	MODULE_ALIAS("platform:mv88e6131");