Commit | Line | Data |
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2e16a77e LB |
1 | /* |
2 | * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips | |
e84665c9 | 3 | * Copyright (c) 2008-2009 Marvell Semiconductor |
2e16a77e LB |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e | 11 | #include <linux/delay.h> |
56c3ff9b | 12 | #include <linux/etherdevice.h> |
19b2f97e | 13 | #include <linux/jiffies.h> |
2e16a77e | 14 | #include <linux/list.h> |
2bbba277 | 15 | #include <linux/module.h> |
2e16a77e LB |
16 | #include <linux/netdevice.h> |
17 | #include <linux/phy.h> | |
c8f0b869 | 18 | #include <net/dsa.h> |
6a4b2980 | 19 | #include "mv88e6060.h" |
2e16a77e LB |
20 | |
21 | static int reg_read(struct dsa_switch *ds, int addr, int reg) | |
22 | { | |
04bed143 | 23 | struct mv88e6060_priv *priv = ds->priv; |
b184e497 | 24 | |
a77d43f1 | 25 | return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg); |
2e16a77e LB |
26 | } |
27 | ||
28 | #define REG_READ(addr, reg) \ | |
29 | ({ \ | |
30 | int __ret; \ | |
31 | \ | |
32 | __ret = reg_read(ds, addr, reg); \ | |
33 | if (__ret < 0) \ | |
34 | return __ret; \ | |
35 | __ret; \ | |
36 | }) | |
37 | ||
38 | ||
39 | static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) | |
40 | { | |
04bed143 | 41 | struct mv88e6060_priv *priv = ds->priv; |
b184e497 | 42 | |
a77d43f1 | 43 | return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val); |
2e16a77e LB |
44 | } |
45 | ||
46 | #define REG_WRITE(addr, reg, val) \ | |
47 | ({ \ | |
48 | int __ret; \ | |
49 | \ | |
50 | __ret = reg_write(ds, addr, reg, val); \ | |
51 | if (__ret < 0) \ | |
52 | return __ret; \ | |
53 | }) | |
54 | ||
0209d144 | 55 | static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr) |
2e16a77e LB |
56 | { |
57 | int ret; | |
58 | ||
6a4b2980 | 59 | ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID); |
2e16a77e | 60 | if (ret >= 0) { |
6a4b2980 | 61 | if (ret == PORT_SWITCH_ID_6060) |
3de6aa4c | 62 | return "Marvell 88E6060 (A0)"; |
6a4b2980 NA |
63 | if (ret == PORT_SWITCH_ID_6060_R1 || |
64 | ret == PORT_SWITCH_ID_6060_R2) | |
3de6aa4c | 65 | return "Marvell 88E6060 (B0)"; |
6a4b2980 | 66 | if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060) |
2e16a77e LB |
67 | return "Marvell 88E6060"; |
68 | } | |
69 | ||
70 | return NULL; | |
71 | } | |
72 | ||
5ed4e3eb FF |
73 | static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds, |
74 | int port) | |
7b314362 AL |
75 | { |
76 | return DSA_TAG_PROTO_TRAILER; | |
77 | } | |
78 | ||
0209d144 VD |
79 | static const char *mv88e6060_drv_probe(struct device *dsa_dev, |
80 | struct device *host_dev, int sw_addr, | |
81 | void **_priv) | |
a77d43f1 AL |
82 | { |
83 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); | |
84 | struct mv88e6060_priv *priv; | |
0209d144 | 85 | const char *name; |
a77d43f1 AL |
86 | |
87 | name = mv88e6060_get_name(bus, sw_addr); | |
88 | if (name) { | |
89 | priv = devm_kzalloc(dsa_dev, sizeof(*priv), GFP_KERNEL); | |
90 | if (!priv) | |
91 | return NULL; | |
92 | *_priv = priv; | |
93 | priv->bus = bus; | |
94 | priv->sw_addr = sw_addr; | |
95 | } | |
96 | ||
97 | return name; | |
98 | } | |
99 | ||
2e16a77e LB |
100 | static int mv88e6060_switch_reset(struct dsa_switch *ds) |
101 | { | |
102 | int i; | |
103 | int ret; | |
19b2f97e | 104 | unsigned long timeout; |
2e16a77e | 105 | |
3675c8d7 | 106 | /* Set all ports to the disabled state. */ |
6a4b2980 NA |
107 | for (i = 0; i < MV88E6060_PORTS; i++) { |
108 | ret = REG_READ(REG_PORT(i), PORT_CONTROL); | |
109 | REG_WRITE(REG_PORT(i), PORT_CONTROL, | |
110 | ret & ~PORT_CONTROL_STATE_MASK); | |
2e16a77e LB |
111 | } |
112 | ||
3675c8d7 | 113 | /* Wait for transmit queues to drain. */ |
19b2f97e | 114 | usleep_range(2000, 4000); |
2e16a77e | 115 | |
3675c8d7 | 116 | /* Reset the switch. */ |
6a4b2980 NA |
117 | REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, |
118 | GLOBAL_ATU_CONTROL_SWRESET | | |
119 | GLOBAL_ATU_CONTROL_ATUSIZE_1024 | | |
120 | GLOBAL_ATU_CONTROL_ATE_AGE_5MIN); | |
2e16a77e | 121 | |
3675c8d7 | 122 | /* Wait up to one second for reset to complete. */ |
19b2f97e BG |
123 | timeout = jiffies + 1 * HZ; |
124 | while (time_before(jiffies, timeout)) { | |
6a4b2980 NA |
125 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
126 | if (ret & GLOBAL_STATUS_INIT_READY) | |
2e16a77e LB |
127 | break; |
128 | ||
19b2f97e | 129 | usleep_range(1000, 2000); |
2e16a77e | 130 | } |
19b2f97e | 131 | if (time_after(jiffies, timeout)) |
2e16a77e LB |
132 | return -ETIMEDOUT; |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
137 | static int mv88e6060_setup_global(struct dsa_switch *ds) | |
138 | { | |
3675c8d7 | 139 | /* Disable discarding of frames with excessive collisions, |
2e16a77e LB |
140 | * set the maximum frame size to 1536 bytes, and mask all |
141 | * interrupt sources. | |
142 | */ | |
6a4b2980 | 143 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536); |
2e16a77e | 144 | |
3675c8d7 | 145 | /* Enable automatic address learning, set the address |
2e16a77e LB |
146 | * database size to 1024 entries, and set the default aging |
147 | * time to 5 minutes. | |
148 | */ | |
6a4b2980 NA |
149 | REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, |
150 | GLOBAL_ATU_CONTROL_ATUSIZE_1024 | | |
151 | GLOBAL_ATU_CONTROL_ATE_AGE_5MIN); | |
2e16a77e LB |
152 | |
153 | return 0; | |
154 | } | |
155 | ||
156 | static int mv88e6060_setup_port(struct dsa_switch *ds, int p) | |
157 | { | |
158 | int addr = REG_PORT(p); | |
159 | ||
3675c8d7 | 160 | /* Do not force flow control, disable Ingress and Egress |
2e16a77e LB |
161 | * Header tagging, disable VLAN tunneling, and set the port |
162 | * state to Forwarding. Additionally, if this is the CPU | |
163 | * port, enable Ingress and Egress Trailer tagging mode. | |
164 | */ | |
6a4b2980 NA |
165 | REG_WRITE(addr, PORT_CONTROL, |
166 | dsa_is_cpu_port(ds, p) ? | |
167 | PORT_CONTROL_TRAILER | | |
168 | PORT_CONTROL_INGRESS_MODE | | |
169 | PORT_CONTROL_STATE_FORWARDING : | |
170 | PORT_CONTROL_STATE_FORWARDING); | |
2e16a77e | 171 | |
3675c8d7 | 172 | /* Port based VLAN map: give each port its own address |
2e16a77e LB |
173 | * database, allow the CPU port to talk to each of the 'real' |
174 | * ports, and allow each of the 'real' ports to only talk to | |
175 | * the CPU port. | |
176 | */ | |
6a4b2980 NA |
177 | REG_WRITE(addr, PORT_VLAN_MAP, |
178 | ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) | | |
02bc6e54 VD |
179 | (dsa_is_cpu_port(ds, p) ? dsa_user_ports(ds) : |
180 | BIT(dsa_to_port(ds, p)->cpu_dp->index))); | |
2e16a77e | 181 | |
3675c8d7 | 182 | /* Port Association Vector: when learning source addresses |
2e16a77e LB |
183 | * of packets, add the address to the address database using |
184 | * a port bitmap that has only the bit for this port set and | |
185 | * the other bits clear. | |
186 | */ | |
6a4b2980 | 187 | REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p)); |
2e16a77e LB |
188 | |
189 | return 0; | |
190 | } | |
191 | ||
56c3ff9b VD |
192 | static int mv88e6060_setup_addr(struct dsa_switch *ds) |
193 | { | |
194 | u8 addr[ETH_ALEN]; | |
195 | u16 val; | |
196 | ||
197 | eth_random_addr(addr); | |
198 | ||
199 | val = addr[0] << 8 | addr[1]; | |
200 | ||
201 | /* The multicast bit is always transmitted as a zero, so the switch uses | |
202 | * bit 8 for "DiffAddr", where 0 means all ports transmit the same SA. | |
203 | */ | |
204 | val &= 0xfeff; | |
205 | ||
206 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, val); | |
207 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); | |
208 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); | |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
2e16a77e LB |
213 | static int mv88e6060_setup(struct dsa_switch *ds) |
214 | { | |
2e16a77e | 215 | int ret; |
a77d43f1 | 216 | int i; |
2e16a77e LB |
217 | |
218 | ret = mv88e6060_switch_reset(ds); | |
219 | if (ret < 0) | |
220 | return ret; | |
221 | ||
222 | /* @@@ initialise atu */ | |
223 | ||
224 | ret = mv88e6060_setup_global(ds); | |
225 | if (ret < 0) | |
226 | return ret; | |
227 | ||
56c3ff9b VD |
228 | ret = mv88e6060_setup_addr(ds); |
229 | if (ret < 0) | |
230 | return ret; | |
231 | ||
6a4b2980 | 232 | for (i = 0; i < MV88E6060_PORTS; i++) { |
2e16a77e LB |
233 | ret = mv88e6060_setup_port(ds, i); |
234 | if (ret < 0) | |
235 | return ret; | |
236 | } | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
2e16a77e LB |
241 | static int mv88e6060_port_to_phy_addr(int port) |
242 | { | |
6a4b2980 | 243 | if (port >= 0 && port < MV88E6060_PORTS) |
2e16a77e LB |
244 | return port; |
245 | return -1; | |
246 | } | |
247 | ||
248 | static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum) | |
249 | { | |
250 | int addr; | |
251 | ||
252 | addr = mv88e6060_port_to_phy_addr(port); | |
253 | if (addr == -1) | |
254 | return 0xffff; | |
255 | ||
256 | return reg_read(ds, addr, regnum); | |
257 | } | |
258 | ||
259 | static int | |
260 | mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
261 | { | |
262 | int addr; | |
263 | ||
264 | addr = mv88e6060_port_to_phy_addr(port); | |
265 | if (addr == -1) | |
266 | return 0xffff; | |
267 | ||
268 | return reg_write(ds, addr, regnum, val); | |
269 | } | |
270 | ||
a82f67af | 271 | static const struct dsa_switch_ops mv88e6060_switch_ops = { |
7b314362 | 272 | .get_tag_protocol = mv88e6060_get_tag_protocol, |
e49bad31 | 273 | .probe = mv88e6060_drv_probe, |
2e16a77e | 274 | .setup = mv88e6060_setup, |
2e16a77e LB |
275 | .phy_read = mv88e6060_phy_read, |
276 | .phy_write = mv88e6060_phy_write, | |
2e16a77e LB |
277 | }; |
278 | ||
ab3d408d FF |
279 | static struct dsa_switch_driver mv88e6060_switch_drv = { |
280 | .ops = &mv88e6060_switch_ops, | |
281 | }; | |
282 | ||
5eaa65b2 | 283 | static int __init mv88e6060_init(void) |
2e16a77e | 284 | { |
ab3d408d | 285 | register_switch_driver(&mv88e6060_switch_drv); |
2e16a77e LB |
286 | return 0; |
287 | } | |
288 | module_init(mv88e6060_init); | |
289 | ||
5eaa65b2 | 290 | static void __exit mv88e6060_cleanup(void) |
2e16a77e | 291 | { |
ab3d408d | 292 | unregister_switch_driver(&mv88e6060_switch_drv); |
2e16a77e LB |
293 | } |
294 | module_exit(mv88e6060_cleanup); | |
3d825ede BH |
295 | |
296 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
297 | MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip"); | |
298 | MODULE_LICENSE("GPL"); | |
299 | MODULE_ALIAS("platform:mv88e6060"); |