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1802d0be | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
b8f126a8 SW |
2 | /* |
3 | * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> | |
b8f126a8 SW |
4 | */ |
5 | ||
6 | #ifndef __MT7530_H | |
7 | #define __MT7530_H | |
8 | ||
9 | #define MT7530_NUM_PORTS 7 | |
ba751e28 | 10 | #define MT7530_NUM_PHYS 5 |
b8f126a8 SW |
11 | #define MT7530_CPU_PORT 6 |
12 | #define MT7530_NUM_FDB_RECORDS 2048 | |
83163f7d | 13 | #define MT7530_ALL_MEMBERS 0xff |
b8f126a8 | 14 | |
9470174e DQ |
15 | #define MTK_HDR_LEN 4 |
16 | #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) | |
17 | ||
88bdef8b | 18 | enum mt753x_id { |
ddda1ac1 GU |
19 | ID_MT7530 = 0, |
20 | ID_MT7621 = 1, | |
c288575f | 21 | ID_MT7531 = 2, |
ddda1ac1 GU |
22 | }; |
23 | ||
b8f126a8 SW |
24 | #define NUM_TRGMII_CTRL 5 |
25 | ||
26 | #define TRGMII_BASE(x) (0x10000 + (x)) | |
27 | ||
28 | /* Registers to ethsys access */ | |
29 | #define ETHSYS_CLKCFG0 0x2c | |
30 | #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) | |
31 | ||
32 | #define SYSC_REG_RSTCTRL 0x34 | |
33 | #define RESET_MCM BIT(2) | |
34 | ||
35 | /* Registers to mac forward control for unknown frames */ | |
36 | #define MT7530_MFC 0x10 | |
37 | #define BC_FFP(x) (((x) & 0xff) << 24) | |
5a30833b | 38 | #define BC_FFP_MASK BC_FFP(~0) |
b8f126a8 | 39 | #define UNM_FFP(x) (((x) & 0xff) << 16) |
5e5502e0 | 40 | #define UNM_FFP_MASK UNM_FFP(~0) |
b8f126a8 SW |
41 | #define UNU_FFP(x) (((x) & 0xff) << 8) |
42 | #define UNU_FFP_MASK UNU_FFP(~0) | |
ddda1ac1 GU |
43 | #define CPU_EN BIT(7) |
44 | #define CPU_PORT(x) ((x) << 4) | |
45 | #define CPU_MASK (0xf << 4) | |
37feab60 | 46 | #define MIRROR_EN BIT(3) |
13e787ca | 47 | #define MIRROR_PORT(x) ((x) & 0x7) |
37feab60 | 48 | #define MIRROR_MASK 0x7 |
b8f126a8 | 49 | |
c288575f LC |
50 | /* Registers for CPU forward control */ |
51 | #define MT7531_CFC 0x4 | |
52 | #define MT7531_MIRROR_EN BIT(19) | |
53 | #define MT7531_MIRROR_MASK (MIRROR_MASK << 16) | |
54 | #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) | |
55 | #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) | |
56 | #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) | |
57 | ||
58 | #define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \ | |
59 | MT7531_CFC : MT7530_MFC) | |
60 | #define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \ | |
61 | MT7531_MIRROR_EN : MIRROR_EN) | |
62 | #define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \ | |
63 | MT7531_MIRROR_MASK : MIRROR_MASK) | |
64 | ||
65 | /* Registers for BPDU and PAE frame control*/ | |
66 | #define MT753X_BPC 0x24 | |
67 | #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) | |
68 | ||
69 | enum mt753x_bpdu_port_fw { | |
70 | MT753X_BPDU_FOLLOW_MFC, | |
71 | MT753X_BPDU_CPU_EXCLUDE = 4, | |
72 | MT753X_BPDU_CPU_INCLUDE = 5, | |
73 | MT753X_BPDU_CPU_ONLY = 6, | |
74 | MT753X_BPDU_DROP = 7, | |
75 | }; | |
76 | ||
b8f126a8 SW |
77 | /* Registers for address table access */ |
78 | #define MT7530_ATA1 0x74 | |
79 | #define STATIC_EMP 0 | |
80 | #define STATIC_ENT 3 | |
81 | #define MT7530_ATA2 0x78 | |
11d8d98c | 82 | #define ATA2_IVL BIT(15) |
73c447ca | 83 | #define ATA2_FID(x) (((x) & 0x7) << 12) |
b8f126a8 SW |
84 | |
85 | /* Register for address table write data */ | |
86 | #define MT7530_ATWD 0x7c | |
87 | ||
88 | /* Register for address table control */ | |
89 | #define MT7530_ATC 0x80 | |
90 | #define ATC_HASH (((x) & 0xfff) << 16) | |
91 | #define ATC_BUSY BIT(15) | |
92 | #define ATC_SRCH_END BIT(14) | |
93 | #define ATC_SRCH_HIT BIT(13) | |
94 | #define ATC_INVALID BIT(12) | |
95 | #define ATC_MAT(x) (((x) & 0xf) << 8) | |
96 | #define ATC_MAT_MACTAB ATC_MAT(0) | |
97 | ||
98 | enum mt7530_fdb_cmd { | |
99 | MT7530_FDB_READ = 0, | |
100 | MT7530_FDB_WRITE = 1, | |
101 | MT7530_FDB_FLUSH = 2, | |
102 | MT7530_FDB_START = 4, | |
103 | MT7530_FDB_NEXT = 5, | |
104 | }; | |
105 | ||
106 | /* Registers for table search read address */ | |
107 | #define MT7530_TSRA1 0x84 | |
108 | #define MAC_BYTE_0 24 | |
109 | #define MAC_BYTE_1 16 | |
110 | #define MAC_BYTE_2 8 | |
111 | #define MAC_BYTE_3 0 | |
112 | #define MAC_BYTE_MASK 0xff | |
113 | ||
114 | #define MT7530_TSRA2 0x88 | |
115 | #define MAC_BYTE_4 24 | |
116 | #define MAC_BYTE_5 16 | |
117 | #define CVID 0 | |
118 | #define CVID_MASK 0xfff | |
119 | ||
120 | #define MT7530_ATRD 0x8C | |
121 | #define AGE_TIMER 24 | |
122 | #define AGE_TIMER_MASK 0xff | |
123 | #define PORT_MAP 4 | |
124 | #define PORT_MAP_MASK 0xff | |
125 | #define ENT_STATUS 2 | |
126 | #define ENT_STATUS_MASK 0x3 | |
127 | ||
128 | /* Register for vlan table control */ | |
129 | #define MT7530_VTCR 0x90 | |
130 | #define VTCR_BUSY BIT(31) | |
83163f7d SW |
131 | #define VTCR_INVALID BIT(16) |
132 | #define VTCR_FUNC(x) (((x) & 0xf) << 12) | |
b8f126a8 SW |
133 | #define VTCR_VID ((x) & 0xfff) |
134 | ||
83163f7d SW |
135 | enum mt7530_vlan_cmd { |
136 | /* Read/Write the specified VID entry from VAWD register based | |
137 | * on VID. | |
138 | */ | |
139 | MT7530_VTCR_RD_VID = 0, | |
140 | MT7530_VTCR_WR_VID = 1, | |
141 | }; | |
142 | ||
b8f126a8 SW |
143 | /* Register for setup vlan and acl write data */ |
144 | #define MT7530_VAWD1 0x94 | |
145 | #define PORT_STAG BIT(31) | |
83163f7d | 146 | /* Independent VLAN Learning */ |
b8f126a8 | 147 | #define IVL_MAC BIT(30) |
1ca8a193 DQ |
148 | /* Egress Tag Consistent */ |
149 | #define EG_CON BIT(29) | |
83163f7d SW |
150 | /* Per VLAN Egress Tag Control */ |
151 | #define VTAG_EN BIT(28) | |
152 | /* VLAN Member Control */ | |
b8f126a8 | 153 | #define PORT_MEM(x) (((x) & 0xff) << 16) |
6087175b DQ |
154 | /* Filter ID */ |
155 | #define FID(x) (((x) & 0x7) << 1) | |
83163f7d SW |
156 | /* VLAN Entry Valid */ |
157 | #define VLAN_VALID BIT(0) | |
158 | #define PORT_MEM_SHFT 16 | |
159 | #define PORT_MEM_MASK 0xff | |
b8f126a8 | 160 | |
6087175b DQ |
161 | enum mt7530_fid { |
162 | FID_STANDALONE = 0, | |
163 | FID_BRIDGED = 1, | |
164 | }; | |
165 | ||
b8f126a8 | 166 | #define MT7530_VAWD2 0x98 |
83163f7d SW |
167 | /* Egress Tag Control */ |
168 | #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) | |
169 | #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) | |
170 | ||
171 | enum mt7530_vlan_egress_attr { | |
172 | MT7530_VLAN_EGRESS_UNTAG = 0, | |
173 | MT7530_VLAN_EGRESS_TAG = 2, | |
174 | MT7530_VLAN_EGRESS_STACK = 3, | |
175 | }; | |
b8f126a8 | 176 | |
ea6d5c92 DQ |
177 | /* Register for address age control */ |
178 | #define MT7530_AAC 0xa0 | |
179 | /* Disable ageing */ | |
180 | #define AGE_DIS BIT(20) | |
181 | /* Age count */ | |
182 | #define AGE_CNT_MASK GENMASK(19, 12) | |
183 | #define AGE_CNT_MAX 0xff | |
184 | #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) | |
185 | /* Age unit */ | |
186 | #define AGE_UNIT_MASK GENMASK(11, 0) | |
187 | #define AGE_UNIT_MAX 0xfff | |
188 | #define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) | |
189 | ||
b8f126a8 SW |
190 | /* Register for port STP state control */ |
191 | #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) | |
a9e3f62d DQ |
192 | #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) |
193 | #define FID_PST_MASK(fid) FID_PST(fid, 0x3) | |
b8f126a8 SW |
194 | |
195 | enum mt7530_stp_state { | |
196 | MT7530_STP_DISABLED = 0, | |
197 | MT7530_STP_BLOCKING = 1, | |
198 | MT7530_STP_LISTENING = 1, | |
199 | MT7530_STP_LEARNING = 2, | |
200 | MT7530_STP_FORWARDING = 3 | |
201 | }; | |
202 | ||
203 | /* Register for port control */ | |
204 | #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) | |
37feab60 DQ |
205 | #define PORT_TX_MIR BIT(9) |
206 | #define PORT_RX_MIR BIT(8) | |
b8f126a8 | 207 | #define PORT_VLAN(x) ((x) & 0x3) |
83163f7d SW |
208 | |
209 | enum mt7530_port_mode { | |
210 | /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ | |
211 | MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), | |
212 | ||
38152ea3 DQ |
213 | /* Fallback Mode: Forward received frames with ingress ports that do |
214 | * not belong to the VLAN member. Frames whose VID is not listed on | |
215 | * the VLAN table are forwarded by the PCR_MATRIX members. | |
216 | */ | |
217 | MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), | |
218 | ||
83163f7d SW |
219 | /* Security Mode: Discard any frame due to ingress membership |
220 | * violation or VID missed on the VLAN table. | |
221 | */ | |
222 | MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), | |
223 | }; | |
224 | ||
b8f126a8 SW |
225 | #define PCR_MATRIX(x) (((x) & 0xff) << 16) |
226 | #define PORT_PRI(x) (((x) & 0x7) << 24) | |
227 | #define EG_TAG(x) (((x) & 0x3) << 28) | |
228 | #define PCR_MATRIX_MASK PCR_MATRIX(0xff) | |
229 | #define PCR_MATRIX_CLR PCR_MATRIX(0) | |
83163f7d | 230 | #define PCR_PORT_VLAN_MASK PORT_VLAN(3) |
b8f126a8 SW |
231 | |
232 | /* Register for port security control */ | |
233 | #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) | |
234 | #define SA_DIS BIT(4) | |
235 | ||
236 | /* Register for port vlan control */ | |
237 | #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) | |
238 | #define PORT_SPEC_TAG BIT(5) | |
e045124e DQ |
239 | #define PVC_EG_TAG(x) (((x) & 0x7) << 8) |
240 | #define PVC_EG_TAG_MASK PVC_EG_TAG(7) | |
b8f126a8 | 241 | #define VLAN_ATTR(x) (((x) & 0x3) << 6) |
83163f7d | 242 | #define VLAN_ATTR_MASK VLAN_ATTR(3) |
8fbebef8 | 243 | #define ACC_FRM_MASK GENMASK(1, 0) |
83163f7d | 244 | |
e045124e DQ |
245 | enum mt7530_vlan_port_eg_tag { |
246 | MT7530_VLAN_EG_DISABLED = 0, | |
247 | MT7530_VLAN_EG_CONSISTENT = 1, | |
248 | }; | |
249 | ||
83163f7d SW |
250 | enum mt7530_vlan_port_attr { |
251 | MT7530_VLAN_USER = 0, | |
252 | MT7530_VLAN_TRANSPARENT = 3, | |
253 | }; | |
254 | ||
8fbebef8 DQ |
255 | enum mt7530_vlan_port_acc_frm { |
256 | MT7530_VLAN_ACC_ALL = 0, | |
257 | MT7530_VLAN_ACC_TAGGED = 1, | |
258 | MT7530_VLAN_ACC_UNTAGGED = 2, | |
259 | }; | |
260 | ||
b8f126a8 SW |
261 | #define STAG_VPID (((x) & 0xffff) << 16) |
262 | ||
263 | /* Register for port port-and-protocol based vlan 1 control */ | |
264 | #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) | |
83163f7d SW |
265 | #define G0_PORT_VID(x) (((x) & 0xfff) << 0) |
266 | #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) | |
6087175b | 267 | #define G0_PORT_VID_DEF G0_PORT_VID(0) |
b8f126a8 SW |
268 | |
269 | /* Register for port MAC control register */ | |
270 | #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) | |
271 | #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) | |
38f790a8 | 272 | #define PMCR_EXT_PHY BIT(17) |
b8f126a8 SW |
273 | #define PMCR_MAC_MODE BIT(16) |
274 | #define PMCR_FORCE_MODE BIT(15) | |
275 | #define PMCR_TX_EN BIT(14) | |
276 | #define PMCR_RX_EN BIT(13) | |
277 | #define PMCR_BACKOFF_EN BIT(9) | |
278 | #define PMCR_BACKPR_EN BIT(8) | |
40b5d2f1 RD |
279 | #define PMCR_FORCE_EEE1G BIT(7) |
280 | #define PMCR_FORCE_EEE100 BIT(6) | |
b8f126a8 SW |
281 | #define PMCR_TX_FC_EN BIT(5) |
282 | #define PMCR_RX_FC_EN BIT(4) | |
283 | #define PMCR_FORCE_SPEED_1000 BIT(3) | |
8e6f1521 | 284 | #define PMCR_FORCE_SPEED_100 BIT(2) |
b8f126a8 SW |
285 | #define PMCR_FORCE_FDX BIT(1) |
286 | #define PMCR_FORCE_LNK BIT(0) | |
ca366d6c RD |
287 | #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ |
288 | PMCR_FORCE_SPEED_1000) | |
c288575f LC |
289 | #define MT7531_FORCE_LNK BIT(31) |
290 | #define MT7531_FORCE_SPD BIT(30) | |
291 | #define MT7531_FORCE_DPX BIT(29) | |
292 | #define MT7531_FORCE_RX_FC BIT(28) | |
293 | #define MT7531_FORCE_TX_FC BIT(27) | |
294 | #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ | |
295 | MT7531_FORCE_SPD | \ | |
296 | MT7531_FORCE_DPX | \ | |
297 | MT7531_FORCE_RX_FC | \ | |
298 | MT7531_FORCE_TX_FC) | |
299 | #define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \ | |
300 | MT7531_FORCE_MODE : \ | |
301 | PMCR_FORCE_MODE) | |
1d01145f RD |
302 | #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ |
303 | PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ | |
304 | PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ | |
40b5d2f1 RD |
305 | PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ |
306 | PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) | |
c288575f LC |
307 | #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \ |
308 | PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ | |
309 | PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \ | |
310 | PMCR_TX_EN | PMCR_RX_EN | \ | |
311 | PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ | |
312 | PMCR_FORCE_SPEED_1000 | \ | |
313 | PMCR_FORCE_FDX | PMCR_FORCE_LNK) | |
b8f126a8 | 314 | |
40b5d2f1 RD |
315 | #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) |
316 | #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) | |
317 | #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16) | |
318 | #define LPI_THRESH_MASK GENMASK(15, 4) | |
319 | #define LPI_THRESH_SHT 4 | |
320 | #define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK) | |
321 | #define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT) | |
322 | #define LPI_MODE_EN BIT(0) | |
323 | ||
b8f126a8 | 324 | #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) |
ca366d6c RD |
325 | #define PMSR_EEE1G BIT(7) |
326 | #define PMSR_EEE100M BIT(6) | |
327 | #define PMSR_RX_FC BIT(5) | |
328 | #define PMSR_TX_FC BIT(4) | |
329 | #define PMSR_SPEED_1000 BIT(3) | |
330 | #define PMSR_SPEED_100 BIT(2) | |
331 | #define PMSR_SPEED_10 0x00 | |
332 | #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) | |
333 | #define PMSR_DPX BIT(1) | |
334 | #define PMSR_LINK BIT(0) | |
b8f126a8 | 335 | |
c288575f LC |
336 | /* Register for port debug count */ |
337 | #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) | |
338 | #define MT7531_DIS_CLR BIT(31) | |
339 | ||
9470174e DQ |
340 | #define MT7530_GMACCR 0x30e0 |
341 | #define MAX_RX_JUMBO(x) ((x) << 2) | |
342 | #define MAX_RX_JUMBO_MASK GENMASK(5, 2) | |
343 | #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) | |
344 | #define MAX_RX_PKT_LEN_1522 0x0 | |
345 | #define MAX_RX_PKT_LEN_1536 0x1 | |
346 | #define MAX_RX_PKT_LEN_1552 0x2 | |
347 | #define MAX_RX_PKT_LEN_JUMBO 0x3 | |
348 | ||
b8f126a8 SW |
349 | /* Register for MIB */ |
350 | #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) | |
351 | #define MT7530_MIB_CCR 0x4fe0 | |
352 | #define CCR_MIB_ENABLE BIT(31) | |
353 | #define CCR_RX_OCT_CNT_GOOD BIT(7) | |
354 | #define CCR_RX_OCT_CNT_BAD BIT(6) | |
355 | #define CCR_TX_OCT_CNT_GOOD BIT(5) | |
356 | #define CCR_TX_OCT_CNT_BAD BIT(4) | |
357 | #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ | |
358 | CCR_RX_OCT_CNT_BAD | \ | |
359 | CCR_TX_OCT_CNT_GOOD | \ | |
360 | CCR_TX_OCT_CNT_BAD) | |
361 | #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ | |
362 | CCR_RX_OCT_CNT_GOOD | \ | |
363 | CCR_RX_OCT_CNT_BAD | \ | |
364 | CCR_TX_OCT_CNT_GOOD | \ | |
365 | CCR_TX_OCT_CNT_BAD) | |
c288575f LC |
366 | |
367 | /* MT7531 SGMII register group */ | |
368 | #define MT7531_SGMII_REG_BASE 0x5000 | |
369 | #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ | |
370 | ((p) - 5) * 0x1000 + (r)) | |
371 | ||
372 | /* Register forSGMII PCS_CONTROL_1 */ | |
373 | #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00) | |
374 | #define MT7531_SGMII_LINK_STATUS BIT(18) | |
375 | #define MT7531_SGMII_AN_ENABLE BIT(12) | |
376 | #define MT7531_SGMII_AN_RESTART BIT(9) | |
377 | ||
378 | /* Register for SGMII PCS_SPPED_ABILITY */ | |
379 | #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08) | |
380 | #define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0) | |
381 | #define MT7531_SGMII_TX_CONFIG BIT(0) | |
382 | ||
383 | /* Register for SGMII_MODE */ | |
384 | #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20) | |
385 | #define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8) | |
386 | #define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1) | |
387 | #define MT7531_SGMII_FORCE_DUPLEX BIT(4) | |
388 | #define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2) | |
389 | #define MT7531_SGMII_FORCE_SPEED_1000 BIT(3) | |
390 | #define MT7531_SGMII_FORCE_SPEED_100 BIT(2) | |
391 | #define MT7531_SGMII_FORCE_SPEED_10 0 | |
392 | #define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1) | |
393 | ||
394 | enum mt7531_sgmii_force_duplex { | |
395 | MT7531_SGMII_FORCE_FULL_DUPLEX = 0, | |
396 | MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10, | |
397 | }; | |
398 | ||
399 | /* Fields of QPHY_PWR_STATE_CTRL */ | |
400 | #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8) | |
401 | #define MT7531_SGMII_PHYA_PWD BIT(4) | |
402 | ||
403 | /* Values of SGMII SPEED */ | |
404 | #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128) | |
405 | #define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3)) | |
406 | #define MT7531_RG_TPHY_SPEED_1_25G 0x0 | |
407 | #define MT7531_RG_TPHY_SPEED_3_125G BIT(2) | |
408 | ||
b8f126a8 SW |
409 | /* Register for system reset */ |
410 | #define MT7530_SYS_CTRL 0x7000 | |
411 | #define SYS_CTRL_PHY_RST BIT(2) | |
412 | #define SYS_CTRL_SW_RST BIT(1) | |
413 | #define SYS_CTRL_REG_RST BIT(0) | |
414 | ||
ba751e28 DQ |
415 | /* Register for system interrupt */ |
416 | #define MT7530_SYS_INT_EN 0x7008 | |
417 | ||
418 | /* Register for system interrupt status */ | |
419 | #define MT7530_SYS_INT_STS 0x700c | |
420 | ||
c288575f LC |
421 | /* Register for PHY Indirect Access Control */ |
422 | #define MT7531_PHY_IAC 0x701C | |
423 | #define MT7531_PHY_ACS_ST BIT(31) | |
424 | #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25) | |
425 | #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20) | |
426 | #define MT7531_MDIO_CMD_MASK (0x3 << 18) | |
427 | #define MT7531_MDIO_ST_MASK (0x3 << 16) | |
428 | #define MT7531_MDIO_RW_DATA_MASK (0xffff) | |
429 | #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) | |
430 | #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) | |
431 | #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) | |
432 | #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) | |
433 | #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) | |
434 | ||
435 | enum mt7531_phy_iac_cmd { | |
436 | MT7531_MDIO_ADDR = 0, | |
437 | MT7531_MDIO_WRITE = 1, | |
438 | MT7531_MDIO_READ = 2, | |
439 | MT7531_MDIO_READ_CL45 = 3, | |
440 | }; | |
441 | ||
442 | /* MDIO_ST: MDIO start field */ | |
443 | enum mt7531_mdio_st { | |
444 | MT7531_MDIO_ST_CL45 = 0, | |
445 | MT7531_MDIO_ST_CL22 = 1, | |
446 | }; | |
447 | ||
448 | #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ | |
449 | MT7531_MDIO_CMD(MT7531_MDIO_READ)) | |
450 | #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ | |
451 | MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) | |
452 | #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ | |
453 | MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) | |
454 | #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ | |
455 | MT7531_MDIO_CMD(MT7531_MDIO_READ)) | |
456 | #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ | |
457 | MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) | |
458 | ||
459 | /* Register for RGMII clock phase */ | |
460 | #define MT7531_CLKGEN_CTRL 0x7500 | |
461 | #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) | |
462 | #define CLK_SKEW_OUT_MASK GENMASK(9, 8) | |
463 | #define CLK_SKEW_IN(x) (((x) & 0x3) << 6) | |
464 | #define CLK_SKEW_IN_MASK GENMASK(7, 6) | |
465 | #define RXCLK_NO_DELAY BIT(5) | |
466 | #define TXCLK_NO_REVERSE BIT(4) | |
467 | #define GP_MODE(x) (((x) & 0x3) << 1) | |
468 | #define GP_MODE_MASK GENMASK(2, 1) | |
469 | #define GP_CLK_EN BIT(0) | |
470 | ||
471 | enum mt7531_gp_mode { | |
472 | MT7531_GP_MODE_RGMII = 0, | |
473 | MT7531_GP_MODE_MII = 1, | |
474 | MT7531_GP_MODE_REV_MII = 2 | |
475 | }; | |
476 | ||
477 | enum mt7531_clk_skew { | |
478 | MT7531_CLK_SKEW_NO_CHG = 0, | |
479 | MT7531_CLK_SKEW_DLY_100PPS = 1, | |
480 | MT7531_CLK_SKEW_DLY_200PPS = 2, | |
481 | MT7531_CLK_SKEW_REVERSE = 3, | |
482 | }; | |
483 | ||
b8f126a8 SW |
484 | /* Register for hw trap status */ |
485 | #define MT7530_HWTRAP 0x7800 | |
7ef6f6f8 RD |
486 | #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) |
487 | #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) | |
488 | #define HWTRAP_XTAL_40MHZ (BIT(10)) | |
489 | #define HWTRAP_XTAL_20MHZ (BIT(9)) | |
b8f126a8 | 490 | |
c288575f LC |
491 | #define MT7531_HWTRAP 0x7800 |
492 | #define HWTRAP_XTAL_FSEL_MASK BIT(7) | |
493 | #define HWTRAP_XTAL_FSEL_25MHZ BIT(7) | |
494 | #define HWTRAP_XTAL_FSEL_40MHZ 0 | |
495 | /* Unique fields of (M)HWSTRAP for MT7531 */ | |
496 | #define XTAL_FSEL_S 7 | |
497 | #define XTAL_FSEL_M BIT(7) | |
498 | #define PHY_EN BIT(6) | |
499 | #define CHG_STRAP BIT(8) | |
500 | ||
b8f126a8 SW |
501 | /* Register for hw trap modification */ |
502 | #define MT7530_MHWTRAP 0x7804 | |
38f790a8 | 503 | #define MHWTRAP_PHY0_SEL BIT(20) |
b8f126a8 SW |
504 | #define MHWTRAP_MANUAL BIT(16) |
505 | #define MHWTRAP_P5_MAC_SEL BIT(13) | |
506 | #define MHWTRAP_P6_DIS BIT(8) | |
507 | #define MHWTRAP_P5_RGMII_MODE BIT(7) | |
508 | #define MHWTRAP_P5_DIS BIT(6) | |
509 | #define MHWTRAP_PHY_ACCESS BIT(5) | |
510 | ||
511 | /* Register for TOP signal control */ | |
512 | #define MT7530_TOP_SIG_CTRL 0x7808 | |
513 | #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) | |
514 | ||
c288575f LC |
515 | #define MT7531_TOP_SIG_SR 0x780c |
516 | #define PAD_DUAL_SGMII_EN BIT(1) | |
517 | #define PAD_MCM_SMI_EN BIT(0) | |
518 | ||
b8f126a8 SW |
519 | #define MT7530_IO_DRV_CR 0x7810 |
520 | #define P5_IO_CLK_DRV(x) ((x) & 0x3) | |
521 | #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) | |
522 | ||
c288575f LC |
523 | #define MT7531_CHIP_REV 0x781C |
524 | ||
525 | #define MT7531_PLLGP_EN 0x7820 | |
526 | #define EN_COREPLL BIT(2) | |
527 | #define SW_CLKSW BIT(1) | |
528 | #define SW_PLLGP BIT(0) | |
529 | ||
b8f126a8 SW |
530 | #define MT7530_P6ECR 0x7830 |
531 | #define P6_INTF_MODE_MASK 0x3 | |
532 | #define P6_INTF_MODE(x) ((x) & 0x3) | |
533 | ||
c288575f LC |
534 | #define MT7531_PLLGP_CR0 0x78a8 |
535 | #define RG_COREPLL_EN BIT(22) | |
536 | #define RG_COREPLL_POSDIV_S 23 | |
537 | #define RG_COREPLL_POSDIV_M 0x3800000 | |
538 | #define RG_COREPLL_SDM_PCW_S 1 | |
539 | #define RG_COREPLL_SDM_PCW_M 0x3ffffe | |
540 | #define RG_COREPLL_SDM_PCW_CHG BIT(0) | |
541 | ||
542 | /* Registers for RGMII and SGMII PLL clock */ | |
543 | #define MT7531_ANA_PLLGP_CR2 0x78b0 | |
544 | #define MT7531_ANA_PLLGP_CR5 0x78bc | |
545 | ||
b8f126a8 SW |
546 | /* Registers for TRGMII on the both side */ |
547 | #define MT7530_TRGMII_RCK_CTRL 0x7a00 | |
b8f126a8 SW |
548 | #define RX_RST BIT(31) |
549 | #define RXC_DQSISEL BIT(30) | |
550 | #define DQSI1_TAP_MASK (0x7f << 8) | |
551 | #define DQSI0_TAP_MASK 0x7f | |
552 | #define DQSI1_TAP(x) (((x) & 0x7f) << 8) | |
553 | #define DQSI0_TAP(x) ((x) & 0x7f) | |
554 | ||
555 | #define MT7530_TRGMII_RCK_RTT 0x7a04 | |
b8f126a8 SW |
556 | #define DQS1_GATE BIT(31) |
557 | #define DQS0_GATE BIT(30) | |
558 | ||
559 | #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) | |
b8f126a8 SW |
560 | #define BSLIP_EN BIT(31) |
561 | #define EDGE_CHK BIT(30) | |
562 | #define RD_TAP_MASK 0x7f | |
563 | #define RD_TAP(x) ((x) & 0x7f) | |
564 | ||
b8f126a8 SW |
565 | #define MT7530_TRGMII_TXCTRL 0x7a40 |
566 | #define TRAIN_TXEN BIT(31) | |
567 | #define TXC_INV BIT(30) | |
568 | #define TX_RST BIT(28) | |
569 | ||
570 | #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) | |
b8f126a8 SW |
571 | #define TD_DM_DRVP(x) ((x) & 0xf) |
572 | #define TD_DM_DRVN(x) (((x) & 0xf) << 4) | |
573 | ||
b8f126a8 SW |
574 | #define MT7530_TRGMII_TCK_CTRL 0x7a78 |
575 | #define TCK_TAP(x) (((x) & 0xf) << 8) | |
576 | ||
577 | #define MT7530_P5RGMIIRXCR 0x7b00 | |
578 | #define CSR_RGMII_EDGE_ALIGN BIT(8) | |
579 | #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) | |
580 | ||
581 | #define MT7530_P5RGMIITXCR 0x7b04 | |
582 | #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) | |
583 | ||
c288575f LC |
584 | /* Registers for GPIO mode */ |
585 | #define MT7531_GPIO_MODE0 0x7c0c | |
586 | #define MT7531_GPIO0_MASK GENMASK(3, 0) | |
587 | #define MT7531_GPIO0_INTERRUPT 1 | |
588 | ||
589 | #define MT7531_GPIO_MODE1 0x7c10 | |
590 | #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) | |
591 | #define MT7531_EXT_P_MDC_11 (2 << 12) | |
592 | #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) | |
593 | #define MT7531_EXT_P_MDIO_12 (2 << 16) | |
594 | ||
429a0ede DQ |
595 | /* Registers for LED GPIO control (MT7530 only) |
596 | * All registers follow this pattern: | |
597 | * [ 2: 0] port 0 | |
598 | * [ 6: 4] port 1 | |
599 | * [10: 8] port 2 | |
600 | * [14:12] port 3 | |
601 | * [18:16] port 4 | |
602 | */ | |
603 | ||
604 | /* LED enable, 0: Disable, 1: Enable (Default) */ | |
605 | #define MT7530_LED_EN 0x7d00 | |
606 | /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ | |
607 | #define MT7530_LED_IO_MODE 0x7d04 | |
608 | /* GPIO direction, 0: Input, 1: Output */ | |
609 | #define MT7530_LED_GPIO_DIR 0x7d10 | |
610 | /* GPIO output enable, 0: Disable, 1: Enable */ | |
611 | #define MT7530_LED_GPIO_OE 0x7d14 | |
612 | /* GPIO value, 0: Low, 1: High */ | |
613 | #define MT7530_LED_GPIO_DATA 0x7d18 | |
614 | ||
b8f126a8 SW |
615 | #define MT7530_CREV 0x7ffc |
616 | #define CHIP_NAME_SHIFT 16 | |
617 | #define MT7530_ID 0x7530 | |
618 | ||
c288575f LC |
619 | #define MT7531_CREV 0x781C |
620 | #define CHIP_REV_M 0x0f | |
621 | #define MT7531_ID 0x7531 | |
622 | ||
b8f126a8 SW |
623 | /* Registers for core PLL access through mmd indirect */ |
624 | #define CORE_PLL_GROUP2 0x401 | |
625 | #define RG_SYSPLL_EN_NORMAL BIT(15) | |
626 | #define RG_SYSPLL_VODEN BIT(14) | |
627 | #define RG_SYSPLL_LF BIT(13) | |
628 | #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) | |
629 | #define RG_SYSPLL_LVROD_EN BIT(10) | |
630 | #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) | |
631 | #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) | |
632 | #define RG_SYSPLL_FBKSEL BIT(4) | |
633 | #define RT_SYSPLL_EN_AFE_OLT BIT(0) | |
634 | ||
635 | #define CORE_PLL_GROUP4 0x403 | |
636 | #define RG_SYSPLL_DDSFBK_EN BIT(12) | |
637 | #define RG_SYSPLL_BIAS_EN BIT(11) | |
638 | #define RG_SYSPLL_BIAS_LPF_EN BIT(10) | |
c288575f LC |
639 | #define MT7531_PHY_PLL_OFF BIT(5) |
640 | #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) | |
641 | ||
642 | #define MT753X_CTRL_PHY_ADDR 0 | |
b8f126a8 SW |
643 | |
644 | #define CORE_PLL_GROUP5 0x404 | |
645 | #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) | |
646 | ||
647 | #define CORE_PLL_GROUP6 0x405 | |
648 | #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) | |
649 | ||
650 | #define CORE_PLL_GROUP7 0x406 | |
651 | #define RG_LCDDS_PWDB BIT(15) | |
652 | #define RG_LCDDS_ISO_EN BIT(13) | |
653 | #define RG_LCCDS_C(x) (((x) & 0x7) << 4) | |
654 | #define RG_LCDDS_PCW_NCPO_CHG BIT(3) | |
655 | ||
656 | #define CORE_PLL_GROUP10 0x409 | |
657 | #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) | |
658 | ||
659 | #define CORE_PLL_GROUP11 0x40a | |
660 | #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) | |
661 | ||
662 | #define CORE_GSWPLL_GRP1 0x40d | |
663 | #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) | |
664 | #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) | |
665 | #define RG_GSWPLL_EN_PRE BIT(11) | |
666 | #define RG_GSWPLL_FBKSEL BIT(10) | |
667 | #define RG_GSWPLL_BP BIT(9) | |
668 | #define RG_GSWPLL_BR BIT(8) | |
669 | #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) | |
670 | ||
671 | #define CORE_GSWPLL_GRP2 0x40e | |
672 | #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) | |
673 | #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) | |
674 | ||
675 | #define CORE_TRGMII_GSW_CLK_CG 0x410 | |
676 | #define REG_GSWCK_EN BIT(0) | |
677 | #define REG_TRGMIICK_EN BIT(1) | |
678 | ||
679 | #define MIB_DESC(_s, _o, _n) \ | |
680 | { \ | |
681 | .size = (_s), \ | |
682 | .offset = (_o), \ | |
683 | .name = (_n), \ | |
684 | } | |
685 | ||
686 | struct mt7530_mib_desc { | |
687 | unsigned int size; | |
688 | unsigned int offset; | |
689 | const char *name; | |
690 | }; | |
691 | ||
692 | struct mt7530_fdb { | |
693 | u16 vid; | |
694 | u8 port_mask; | |
695 | u8 aging; | |
696 | u8 mac[6]; | |
697 | bool noarp; | |
698 | }; | |
699 | ||
83163f7d SW |
700 | /* struct mt7530_port - This is the main data structure for holding the state |
701 | * of the port. | |
702 | * @enable: The status used for show port is enabled or not. | |
703 | * @pm: The matrix used to show all connections with the port. | |
704 | * @pvid: The VLAN specified is to be considered a PVID at ingress. Any | |
705 | * untagged frames will be assigned to the related VLAN. | |
706 | * @vlan_filtering: The flags indicating whether the port that can recognize | |
707 | * VLAN-tagged frames. | |
708 | */ | |
b8f126a8 SW |
709 | struct mt7530_port { |
710 | bool enable; | |
711 | u32 pm; | |
83163f7d | 712 | u16 pvid; |
b8f126a8 SW |
713 | }; |
714 | ||
38f790a8 RD |
715 | /* Port 5 interface select definitions */ |
716 | enum p5_interface_select { | |
717 | P5_DISABLED = 0, | |
718 | P5_INTF_SEL_PHY_P0, | |
719 | P5_INTF_SEL_PHY_P4, | |
720 | P5_INTF_SEL_GMAC5, | |
c288575f | 721 | P5_INTF_SEL_GMAC5_SGMII, |
38f790a8 RD |
722 | }; |
723 | ||
724 | static const char *p5_intf_modes(unsigned int p5_interface) | |
725 | { | |
726 | switch (p5_interface) { | |
727 | case P5_DISABLED: | |
728 | return "DISABLED"; | |
729 | case P5_INTF_SEL_PHY_P0: | |
730 | return "PHY P0"; | |
731 | case P5_INTF_SEL_PHY_P4: | |
732 | return "PHY P4"; | |
733 | case P5_INTF_SEL_GMAC5: | |
734 | return "GMAC5"; | |
c288575f LC |
735 | case P5_INTF_SEL_GMAC5_SGMII: |
736 | return "GMAC5_SGMII"; | |
38f790a8 RD |
737 | default: |
738 | return "unknown"; | |
739 | } | |
740 | } | |
741 | ||
ba751e28 DQ |
742 | struct mt7530_priv; |
743 | ||
88bdef8b LC |
744 | /* struct mt753x_info - This is the main data structure for holding the specific |
745 | * part for each supported device | |
746 | * @sw_setup: Holding the handler to a device initialization | |
747 | * @phy_read: Holding the way reading PHY port | |
748 | * @phy_write: Holding the way writing PHY port | |
749 | * @pad_setup: Holding the way setting up the bus pad for a certain | |
750 | * MAC port | |
751 | * @phy_mode_supported: Check if the PHY type is being supported on a certain | |
752 | * port | |
753 | * @mac_port_validate: Holding the way to set addition validate type for a | |
754 | * certan MAC port | |
755 | * @mac_port_get_state: Holding the way getting the MAC/PCS state for a certain | |
756 | * MAC port | |
757 | * @mac_port_config: Holding the way setting up the PHY attribute to a | |
758 | * certain MAC port | |
c288575f LC |
759 | * @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a |
760 | * certain MAC port | |
761 | * @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs | |
762 | * of the certain MAC port | |
88bdef8b LC |
763 | */ |
764 | struct mt753x_info { | |
765 | enum mt753x_id id; | |
766 | ||
767 | int (*sw_setup)(struct dsa_switch *ds); | |
ba751e28 DQ |
768 | int (*phy_read)(struct mt7530_priv *priv, int port, int regnum); |
769 | int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); | |
88bdef8b | 770 | int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); |
c288575f | 771 | int (*cpu_port_config)(struct dsa_switch *ds, int port); |
59c2215f RKO |
772 | void (*mac_port_get_caps)(struct dsa_switch *ds, int port, |
773 | struct phylink_config *config); | |
88bdef8b | 774 | void (*mac_port_validate)(struct dsa_switch *ds, int port, |
7c04c848 | 775 | phy_interface_t interface, |
88bdef8b LC |
776 | unsigned long *supported); |
777 | int (*mac_port_get_state)(struct dsa_switch *ds, int port, | |
778 | struct phylink_link_state *state); | |
779 | int (*mac_port_config)(struct dsa_switch *ds, int port, | |
780 | unsigned int mode, | |
781 | phy_interface_t interface); | |
c288575f LC |
782 | void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port); |
783 | void (*mac_pcs_link_up)(struct dsa_switch *ds, int port, | |
784 | unsigned int mode, phy_interface_t interface, | |
785 | int speed, int duplex); | |
88bdef8b LC |
786 | }; |
787 | ||
b8f126a8 SW |
788 | /* struct mt7530_priv - This is the main data structure for holding the state |
789 | * of the driver | |
790 | * @dev: The device pointer | |
791 | * @ds: The pointer to the dsa core structure | |
792 | * @bus: The bus used for the device and built-in PHY | |
793 | * @rstc: The pointer to reset control used by MCM | |
b8f126a8 SW |
794 | * @core_pwr: The power supplied into the core |
795 | * @io_pwr: The power supplied into the I/O | |
796 | * @reset: The descriptor for GPIO line tied to its reset pin | |
797 | * @mcm: Flag for distinguishing if standalone IC or module | |
798 | * coupling | |
799 | * @ports: Holding the state among ports | |
800 | * @reg_mutex: The lock for protecting among process accessing | |
801 | * registers | |
ca366d6c | 802 | * @p6_interface Holding the current port 6 interface |
38f790a8 | 803 | * @p5_intf_sel: Holding the current port 5 interface select |
ba751e28 DQ |
804 | * |
805 | * @irq: IRQ number of the switch | |
806 | * @irq_domain: IRQ domain of the switch irq_chip | |
807 | * @irq_enable: IRQ enable bits, synced to SYS_INT_EN | |
b8f126a8 SW |
808 | */ |
809 | struct mt7530_priv { | |
810 | struct device *dev; | |
811 | struct dsa_switch *ds; | |
812 | struct mii_bus *bus; | |
813 | struct reset_control *rstc; | |
b8f126a8 SW |
814 | struct regulator *core_pwr; |
815 | struct regulator *io_pwr; | |
816 | struct gpio_desc *reset; | |
88bdef8b | 817 | const struct mt753x_info *info; |
ddda1ac1 | 818 | unsigned int id; |
b8f126a8 | 819 | bool mcm; |
ca366d6c | 820 | phy_interface_t p6_interface; |
38f790a8 RD |
821 | phy_interface_t p5_interface; |
822 | unsigned int p5_intf_sel; | |
37feab60 DQ |
823 | u8 mirror_rx; |
824 | u8 mirror_tx; | |
b8f126a8 SW |
825 | |
826 | struct mt7530_port ports[MT7530_NUM_PORTS]; | |
827 | /* protect among processes for registers access*/ | |
828 | struct mutex reg_mutex; | |
ba751e28 DQ |
829 | int irq; |
830 | struct irq_domain *irq_domain; | |
831 | u32 irq_enable; | |
b8f126a8 SW |
832 | }; |
833 | ||
83163f7d SW |
834 | struct mt7530_hw_vlan_entry { |
835 | int port; | |
836 | u8 old_members; | |
837 | bool untagged; | |
838 | }; | |
839 | ||
840 | static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, | |
841 | int port, bool untagged) | |
842 | { | |
843 | e->port = port; | |
844 | e->untagged = untagged; | |
845 | } | |
846 | ||
847 | typedef void (*mt7530_vlan_op)(struct mt7530_priv *, | |
848 | struct mt7530_hw_vlan_entry *); | |
849 | ||
b8f126a8 SW |
850 | struct mt7530_hw_stats { |
851 | const char *string; | |
852 | u16 reg; | |
853 | u8 sizeof_stat; | |
854 | }; | |
855 | ||
856 | struct mt7530_dummy_poll { | |
857 | struct mt7530_priv *priv; | |
858 | u32 reg; | |
859 | }; | |
860 | ||
861 | static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, | |
862 | struct mt7530_priv *priv, u32 reg) | |
863 | { | |
864 | p->priv = priv; | |
865 | p->reg = reg; | |
866 | } | |
867 | ||
868 | #endif /* __MT7530_H */ |