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net: phy: add MediaTek Gigabit Ethernet PHY driver
[linux-block.git] / drivers / net / dsa / mt7530.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
b8f126a8
SW		 2/*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
b8f126a8
SW		 5 */
6#include <linux/etherdevice.h>
7#include <linux/if_bridge.h>
8#include <linux/iopoll.h>
9#include <linux/mdio.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
b8f126a8
SW		 13#include <linux/of_mdio.h>
14#include <linux/of_net.h>
15#include <linux/of_platform.h>
ca366d6c 16#include <linux/phylink.h>
b8f126a8
SW		 17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19#include <linux/reset.h>
eb976a55 20#include <linux/gpio/consumer.h>
429a0ede 21#include <linux/gpio/driver.h>
b8f126a8 22#include <net/dsa.h>
b8f126a8
SW		 23
24#include "mt7530.h"
25
26/* String, offset, and register size in bytes if different from 4 bytes */
27static const struct mt7530_mib_desc mt7530_mib[] = {
28 MIB_DESC(1, 0x00, "TxDrop"),
29 MIB_DESC(1, 0x04, "TxCrcErr"),
30 MIB_DESC(1, 0x08, "TxUnicast"),
31 MIB_DESC(1, 0x0c, "TxMulticast"),
32 MIB_DESC(1, 0x10, "TxBroadcast"),
33 MIB_DESC(1, 0x14, "TxCollision"),
34 MIB_DESC(1, 0x18, "TxSingleCollision"),
35 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
36 MIB_DESC(1, 0x20, "TxDeferred"),
37 MIB_DESC(1, 0x24, "TxLateCollision"),
38 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
39 MIB_DESC(1, 0x2c, "TxPause"),
40 MIB_DESC(1, 0x30, "TxPktSz64"),
41 MIB_DESC(1, 0x34, "TxPktSz65To127"),
42 MIB_DESC(1, 0x38, "TxPktSz128To255"),
43 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
44 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
45 MIB_DESC(1, 0x44, "Tx1024ToMax"),
46 MIB_DESC(2, 0x48, "TxBytes"),
47 MIB_DESC(1, 0x60, "RxDrop"),
48 MIB_DESC(1, 0x64, "RxFiltering"),
49 MIB_DESC(1, 0x6c, "RxMulticast"),
50 MIB_DESC(1, 0x70, "RxBroadcast"),
51 MIB_DESC(1, 0x74, "RxAlignErr"),
52 MIB_DESC(1, 0x78, "RxCrcErr"),
53 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
54 MIB_DESC(1, 0x80, "RxFragErr"),
55 MIB_DESC(1, 0x84, "RxOverSzErr"),
56 MIB_DESC(1, 0x88, "RxJabberErr"),
57 MIB_DESC(1, 0x8c, "RxPause"),
58 MIB_DESC(1, 0x90, "RxPktSz64"),
59 MIB_DESC(1, 0x94, "RxPktSz65To127"),
60 MIB_DESC(1, 0x98, "RxPktSz128To255"),
61 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
62 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
63 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
64 MIB_DESC(2, 0xa8, "RxBytes"),
65 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
66 MIB_DESC(1, 0xb4, "RxIngressDrop"),
67 MIB_DESC(1, 0xb8, "RxArlDrop"),
68};
69
4732315c
IL		 70/* Since phy_device has not yet been created and
71 * phy_{read,write}_mmd_indirect is not available, we provide our own
72 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
73 * to complete this function.
74 */
b8f126a8
SW		 75static int
76core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
77{
78 struct mii_bus *bus = priv->bus;
79 int value, ret;
80
81 /* Write the desired MMD Devad */
82 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
83 if (ret < 0)
84 goto err;
85
86 /* Write the desired MMD register address */
87 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
88 if (ret < 0)
89 goto err;
90
91 /* Select the Function : DATA with no post increment */
92 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
93 if (ret < 0)
94 goto err;
95
96 /* Read the content of the MMD's selected register */
97 value = bus->read(bus, 0, MII_MMD_DATA);
98
99 return value;
100err:
101 dev_err(&bus->dev, "failed to read mmd register\n");
102
103 return ret;
104}
105
106static int
107core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
108 int devad, u32 data)
109{
110 struct mii_bus *bus = priv->bus;
111 int ret;
112
113 /* Write the desired MMD Devad */
114 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
115 if (ret < 0)
116 goto err;
117
118 /* Write the desired MMD register address */
119 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
120 if (ret < 0)
121 goto err;
122
123 /* Select the Function : DATA with no post increment */
124 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
125 if (ret < 0)
126 goto err;
127
128 /* Write the data into MMD's selected register */
129 ret = bus->write(bus, 0, MII_MMD_DATA, data);
130err:
131 if (ret < 0)
132 dev_err(&bus->dev,
133 "failed to write mmd register\n");
134 return ret;
135}
136
137static void
138core_write(struct mt7530_priv *priv, u32 reg, u32 val)
139{
140 struct mii_bus *bus = priv->bus;
141
142 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
143
144 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
145
146 mutex_unlock(&bus->mdio_lock);
147}
148
149static void
150core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
151{
152 struct mii_bus *bus = priv->bus;
153 u32 val;
154
155 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
156
157 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
158 val &= ~mask;
159 val |= set;
160 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
161
162 mutex_unlock(&bus->mdio_lock);
163}
164
165static void
166core_set(struct mt7530_priv *priv, u32 reg, u32 val)
167{
168 core_rmw(priv, reg, 0, val);
169}
170
171static void
172core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
173{
174 core_rmw(priv, reg, val, 0);
175}
176
177static int
178mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
179{
180 struct mii_bus *bus = priv->bus;
181 u16 page, r, lo, hi;
182 int ret;
183
184 page = (reg >> 6) & 0x3ff;
185 r = (reg >> 2) & 0xf;
186 lo = val & 0xffff;
187 hi = val >> 16;
188
189 /* MT7530 uses 31 as the pseudo port */
190 ret = bus->write(bus, 0x1f, 0x1f, page);
191 if (ret < 0)
192 goto err;
193
194 ret = bus->write(bus, 0x1f, r, lo);
195 if (ret < 0)
196 goto err;
197
198 ret = bus->write(bus, 0x1f, 0x10, hi);
199err:
200 if (ret < 0)
201 dev_err(&bus->dev,
202 "failed to write mt7530 register\n");
203 return ret;
204}
205
206static u32
207mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
208{
209 struct mii_bus *bus = priv->bus;
210 u16 page, r, lo, hi;
211 int ret;
212
213 page = (reg >> 6) & 0x3ff;
214 r = (reg >> 2) & 0xf;
215
216 /* MT7530 uses 31 as the pseudo port */
217 ret = bus->write(bus, 0x1f, 0x1f, page);
218 if (ret < 0) {
219 dev_err(&bus->dev,
220 "failed to read mt7530 register\n");
221 return ret;
222 }
223
224 lo = bus->read(bus, 0x1f, r);
225 hi = bus->read(bus, 0x1f, 0x10);
226
227 return (hi << 16) | (lo & 0xffff);
228}
229
230static void
231mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
232{
233 struct mii_bus *bus = priv->bus;
234
235 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
236
237 mt7530_mii_write(priv, reg, val);
238
239 mutex_unlock(&bus->mdio_lock);
240}
241
c288575f
LC		 242static u32
243_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
244{
245 return mt7530_mii_read(p->priv, p->reg);
246}
247
b8f126a8
SW		 248static u32
249_mt7530_read(struct mt7530_dummy_poll *p)
250{
251 struct mii_bus *bus = p->priv->bus;
252 u32 val;
253
254 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
255
256 val = mt7530_mii_read(p->priv, p->reg);
257
258 mutex_unlock(&bus->mdio_lock);
259
260 return val;
261}
262
263static u32
264mt7530_read(struct mt7530_priv *priv, u32 reg)
265{
266 struct mt7530_dummy_poll p;
267
268 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
269 return _mt7530_read(&p);
270}
271
272static void
273mt7530_rmw(struct mt7530_priv *priv, u32 reg,
274 u32 mask, u32 set)
275{
276 struct mii_bus *bus = priv->bus;
277 u32 val;
278
279 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
280
281 val = mt7530_mii_read(priv, reg);
282 val &= ~mask;
283 val |= set;
284 mt7530_mii_write(priv, reg, val);
285
286 mutex_unlock(&bus->mdio_lock);
287}
288
289static void
290mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
291{
292 mt7530_rmw(priv, reg, 0, val);
293}
294
295static void
296mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
297{
298 mt7530_rmw(priv, reg, val, 0);
299}
300
301static int
302mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
303{
304 u32 val;
305 int ret;
306 struct mt7530_dummy_poll p;
307
308 /* Set the command operating upon the MAC address entries */
309 val = ATC_BUSY | ATC_MAT(0) | cmd;
310 mt7530_write(priv, MT7530_ATC, val);
311
312 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
313 ret = readx_poll_timeout(_mt7530_read, &p, val,
314 !(val & ATC_BUSY), 20, 20000);
315 if (ret < 0) {
316 dev_err(priv->dev, "reset timeout\n");
317 return ret;
318 }
319
320 /* Additional sanity for read command if the specified
321 * entry is invalid
322 */
323 val = mt7530_read(priv, MT7530_ATC);
324 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
325 return -EINVAL;
326
327 if (rsp)
328 *rsp = val;
329
330 return 0;
331}
332
333static void
334mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
335{
336 u32 reg[3];
337 int i;
338
339 /* Read from ARL table into an array */
340 for (i = 0; i < 3; i++) {
341 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
342
343 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
344 __func__, __LINE__, i, reg[i]);
345 }
346
347 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
348 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
349 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
350 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
351 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
352 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
353 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
354 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
355 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
356 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
357}
358
359static void
360mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
361 u8 port_mask, const u8 *mac,
362 u8 aging, u8 type)
363{
364 u32 reg[3] = { 0 };
365 int i;
366
367 reg[1] |= vid & CVID_MASK;
368 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
369 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
370 /* STATIC_ENT indicate that entry is static wouldn't
371 * be aged out and STATIC_EMP specified as erasing an
372 * entry
373 */
374 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
375 reg[1] |= mac[5] << MAC_BYTE_5;
376 reg[1] |= mac[4] << MAC_BYTE_4;
377 reg[0] |= mac[3] << MAC_BYTE_3;
378 reg[0] |= mac[2] << MAC_BYTE_2;
379 reg[0] |= mac[1] << MAC_BYTE_1;
380 reg[0] |= mac[0] << MAC_BYTE_0;
381
382 /* Write array into the ARL table */
383 for (i = 0; i < 3; i++)
384 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
385}
386
88bdef8b 387/* Setup TX circuit including relevant PAD and driving */
b8f126a8 388static int
88bdef8b 389mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
b8f126a8
SW		 390{
391 struct mt7530_priv *priv = ds->priv;
7ef6f6f8
RD		 392 u32 ncpo1, ssc_delta, trgint, i, xtal;
393
394 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
395
396 if (xtal == HWTRAP_XTAL_20MHZ) {
397 dev_err(priv->dev,
398 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
399 __func__);
400 return -EINVAL;
401 }
b8f126a8 402
88bdef8b 403 switch (interface) {
b8f126a8
SW		 404 case PHY_INTERFACE_MODE_RGMII:
405 trgint = 0;
7ef6f6f8 406 /* PLL frequency: 125MHz */
b8f126a8 407 ncpo1 = 0x0c80;
b8f126a8
SW		 408 break;
409 case PHY_INTERFACE_MODE_TRGMII:
410 trgint = 1;
7ef6f6f8
RD		 411 if (priv->id == ID_MT7621) {
412 /* PLL frequency: 150MHz: 1.2GBit */
413 if (xtal == HWTRAP_XTAL_40MHZ)
414 ncpo1 = 0x0780;
415 if (xtal == HWTRAP_XTAL_25MHZ)
416 ncpo1 = 0x0a00;
417 } else { /* PLL frequency: 250MHz: 2.0Gbit */
418 if (xtal == HWTRAP_XTAL_40MHZ)
419 ncpo1 = 0x0c80;
420 if (xtal == HWTRAP_XTAL_25MHZ)
421 ncpo1 = 0x1400;
422 }
b8f126a8
SW		 423 break;
424 default:
88bdef8b
LC		 425 dev_err(priv->dev, "xMII interface %d not supported\n",
426 interface);
b8f126a8
SW		 427 return -EINVAL;
428 }
429
7ef6f6f8
RD		 430 if (xtal == HWTRAP_XTAL_25MHZ)
431 ssc_delta = 0x57;
432 else
433 ssc_delta = 0x87;
434
b8f126a8
SW		 435 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
436 P6_INTF_MODE(trgint));
437
438 /* Lower Tx Driving for TRGMII path */
439 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
440 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
441 TD_DM_DRVP(8) | TD_DM_DRVN(8));
442
4732315c
IL		 443 /* Disable MT7530 core and TRGMII Tx clocks */
444 core_clear(priv, CORE_TRGMII_GSW_CLK_CG,
445 REG_GSWCK_EN | REG_TRGMIICK_EN);
c3b8e079 446
4732315c
IL		 447 /* Setup core clock for MT7530 */
448 /* Disable PLL */
449 core_write(priv, CORE_GSWPLL_GRP1, 0);
c3b8e079
IL		 450
451 /* Set core clock into 500Mhz */
452 core_write(priv, CORE_GSWPLL_GRP2,
453 RG_GSWPLL_POSDIV_500M(1) |
454 RG_GSWPLL_FBKDIV_500M(25));
455
456 /* Enable PLL */
457 core_write(priv, CORE_GSWPLL_GRP1,
458 RG_GSWPLL_EN_PRE |
459 RG_GSWPLL_POSDIV_200M(2) |
460 RG_GSWPLL_FBKDIV_200M(32));
461
b8f126a8 462 /* Setup the MT7530 TRGMII Tx Clock */
b8f126a8
SW		 463 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
464 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
465 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
466 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
467 core_write(priv, CORE_PLL_GROUP4,
468 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
469 RG_SYSPLL_BIAS_LPF_EN);
470 core_write(priv, CORE_PLL_GROUP2,
471 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
472 RG_SYSPLL_POSDIV(1));
473 core_write(priv, CORE_PLL_GROUP7,
474 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
475 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
4732315c
IL		 476
477 /* Enable MT7530 core and TRGMII Tx clocks */
b8f126a8
SW		 478 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
479 REG_GSWCK_EN | REG_TRGMIICK_EN);
480
481 if (!trgint)
482 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
483 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
484 RD_TAP_MASK, RD_TAP(16));
b8f126a8
SW		 485 return 0;
486}
487
c288575f
LC		 488static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
489{
490 u32 val;
491
492 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
493
494 return (val & PAD_DUAL_SGMII_EN) != 0;
495}
496
497static int
498mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
499{
500 struct mt7530_priv *priv = ds->priv;
501 u32 top_sig;
502 u32 hwstrap;
503 u32 xtal;
504 u32 val;
505
506 if (mt7531_dual_sgmii_supported(priv))
507 return 0;
508
509 val = mt7530_read(priv, MT7531_CREV);
510 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
511 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
512 if ((val & CHIP_REV_M) > 0)
513 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
514 HWTRAP_XTAL_FSEL_25MHZ;
515 else
516 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
517
518 /* Step 1 : Disable MT7531 COREPLL */
519 val = mt7530_read(priv, MT7531_PLLGP_EN);
520 val &= ~EN_COREPLL;
521 mt7530_write(priv, MT7531_PLLGP_EN, val);
522
523 /* Step 2: switch to XTAL output */
524 val = mt7530_read(priv, MT7531_PLLGP_EN);
525 val |= SW_CLKSW;
526 mt7530_write(priv, MT7531_PLLGP_EN, val);
527
528 val = mt7530_read(priv, MT7531_PLLGP_CR0);
529 val &= ~RG_COREPLL_EN;
530 mt7530_write(priv, MT7531_PLLGP_CR0, val);
531
532 /* Step 3: disable PLLGP and enable program PLLGP */
533 val = mt7530_read(priv, MT7531_PLLGP_EN);
534 val |= SW_PLLGP;
535 mt7530_write(priv, MT7531_PLLGP_EN, val);
536
537 /* Step 4: program COREPLL output frequency to 500MHz */
538 val = mt7530_read(priv, MT7531_PLLGP_CR0);
539 val &= ~RG_COREPLL_POSDIV_M;
540 val |= 2 << RG_COREPLL_POSDIV_S;
541 mt7530_write(priv, MT7531_PLLGP_CR0, val);
542 usleep_range(25, 35);
543
544 switch (xtal) {
545 case HWTRAP_XTAL_FSEL_25MHZ:
546 val = mt7530_read(priv, MT7531_PLLGP_CR0);
547 val &= ~RG_COREPLL_SDM_PCW_M;
548 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
549 mt7530_write(priv, MT7531_PLLGP_CR0, val);
550 break;
551 case HWTRAP_XTAL_FSEL_40MHZ:
552 val = mt7530_read(priv, MT7531_PLLGP_CR0);
553 val &= ~RG_COREPLL_SDM_PCW_M;
554 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
555 mt7530_write(priv, MT7531_PLLGP_CR0, val);
556 break;
0e8c266c 557 }
c288575f
LC		 558
559 /* Set feedback divide ratio update signal to high */
560 val = mt7530_read(priv, MT7531_PLLGP_CR0);
561 val |= RG_COREPLL_SDM_PCW_CHG;
562 mt7530_write(priv, MT7531_PLLGP_CR0, val);
563 /* Wait for at least 16 XTAL clocks */
564 usleep_range(10, 20);
565
566 /* Step 5: set feedback divide ratio update signal to low */
567 val = mt7530_read(priv, MT7531_PLLGP_CR0);
568 val &= ~RG_COREPLL_SDM_PCW_CHG;
569 mt7530_write(priv, MT7531_PLLGP_CR0, val);
570
571 /* Enable 325M clock for SGMII */
572 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
573
574 /* Enable 250SSC clock for RGMII */
575 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
576
577 /* Step 6: Enable MT7531 PLL */
578 val = mt7530_read(priv, MT7531_PLLGP_CR0);
579 val |= RG_COREPLL_EN;
580 mt7530_write(priv, MT7531_PLLGP_CR0, val);
581
582 val = mt7530_read(priv, MT7531_PLLGP_EN);
583 val |= EN_COREPLL;
584 mt7530_write(priv, MT7531_PLLGP_EN, val);
585 usleep_range(25, 35);
586
587 return 0;
588}
589
b8f126a8
SW		 590static void
591mt7530_mib_reset(struct dsa_switch *ds)
592{
593 struct mt7530_priv *priv = ds->priv;
594
595 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
596 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
597}
598
b8f126a8
SW		 599static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
600{
601 struct mt7530_priv *priv = ds->priv;
602
603 return mdiobus_read_nested(priv->bus, port, regnum);
604}
605
360cc342
CIK		 606static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
607 u16 val)
b8f126a8
SW		 608{
609 struct mt7530_priv *priv = ds->priv;
610
611 return mdiobus_write_nested(priv->bus, port, regnum, val);
612}
613
c288575f
LC		 614static int
615mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
616 int regnum)
617{
618 struct mii_bus *bus = priv->bus;
619 struct mt7530_dummy_poll p;
620 u32 reg, val;
621 int ret;
622
623 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
624
625 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
626
627 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
628 !(val & MT7531_PHY_ACS_ST), 20, 100000);
629 if (ret < 0) {
630 dev_err(priv->dev, "poll timeout\n");
631 goto out;
632 }
633
634 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
635 MT7531_MDIO_DEV_ADDR(devad) | regnum;
636 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
637
638 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
639 !(val & MT7531_PHY_ACS_ST), 20, 100000);
640 if (ret < 0) {
641 dev_err(priv->dev, "poll timeout\n");
642 goto out;
643 }
644
645 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
646 MT7531_MDIO_DEV_ADDR(devad);
647 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
648
649 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
650 !(val & MT7531_PHY_ACS_ST), 20, 100000);
651 if (ret < 0) {
652 dev_err(priv->dev, "poll timeout\n");
653 goto out;
654 }
655
656 ret = val & MT7531_MDIO_RW_DATA_MASK;
657out:
658 mutex_unlock(&bus->mdio_lock);
659
660 return ret;
661}
662
663static int
664mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
665 int regnum, u32 data)
666{
667 struct mii_bus *bus = priv->bus;
668 struct mt7530_dummy_poll p;
669 u32 val, reg;
670 int ret;
671
672 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
673
674 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
675
676 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
677 !(val & MT7531_PHY_ACS_ST), 20, 100000);
678 if (ret < 0) {
679 dev_err(priv->dev, "poll timeout\n");
680 goto out;
681 }
682
683 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
684 MT7531_MDIO_DEV_ADDR(devad) | regnum;
685 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
686
687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
688 !(val & MT7531_PHY_ACS_ST), 20, 100000);
689 if (ret < 0) {
690 dev_err(priv->dev, "poll timeout\n");
691 goto out;
692 }
693
694 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
695 MT7531_MDIO_DEV_ADDR(devad) | data;
696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
697
698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
699 !(val & MT7531_PHY_ACS_ST), 20, 100000);
700 if (ret < 0) {
701 dev_err(priv->dev, "poll timeout\n");
702 goto out;
703 }
704
705out:
706 mutex_unlock(&bus->mdio_lock);
707
708 return ret;
709}
710
711static int
712mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
713{
714 struct mii_bus *bus = priv->bus;
715 struct mt7530_dummy_poll p;
716 int ret;
717 u32 val;
718
719 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
720
721 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
722
723 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
724 !(val & MT7531_PHY_ACS_ST), 20, 100000);
725 if (ret < 0) {
726 dev_err(priv->dev, "poll timeout\n");
727 goto out;
728 }
729
730 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
731 MT7531_MDIO_REG_ADDR(regnum);
732
733 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
734
735 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
736 !(val & MT7531_PHY_ACS_ST), 20, 100000);
737 if (ret < 0) {
738 dev_err(priv->dev, "poll timeout\n");
739 goto out;
740 }
741
742 ret = val & MT7531_MDIO_RW_DATA_MASK;
743out:
744 mutex_unlock(&bus->mdio_lock);
745
746 return ret;
747}
748
749static int
750mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
751 u16 data)
752{
753 struct mii_bus *bus = priv->bus;
754 struct mt7530_dummy_poll p;
755 int ret;
756 u32 reg;
757
758 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
759
760 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
761
762 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
763 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
764 if (ret < 0) {
765 dev_err(priv->dev, "poll timeout\n");
766 goto out;
767 }
768
769 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
770 MT7531_MDIO_REG_ADDR(regnum) | data;
771
772 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
773
774 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
775 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
776 if (ret < 0) {
777 dev_err(priv->dev, "poll timeout\n");
778 goto out;
779 }
780
781out:
782 mutex_unlock(&bus->mdio_lock);
783
784 return ret;
785}
786
787static int
788mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
789{
790 struct mt7530_priv *priv = ds->priv;
791 int devad;
792 int ret;
793
794 if (regnum & MII_ADDR_C45) {
795 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
796 ret = mt7531_ind_c45_phy_read(priv, port, devad,
797 regnum & MII_REGADDR_C45_MASK);
798 } else {
799 ret = mt7531_ind_c22_phy_read(priv, port, regnum);
800 }
801
802 return ret;
803}
804
805static int
806mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
807 u16 data)
808{
809 struct mt7530_priv *priv = ds->priv;
810 int devad;
811 int ret;
812
813 if (regnum & MII_ADDR_C45) {
814 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
815 ret = mt7531_ind_c45_phy_write(priv, port, devad,
816 regnum & MII_REGADDR_C45_MASK,
817 data);
818 } else {
819 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
820 }
821
822 return ret;
823}
824
b8f126a8 825static void
89f09048
FF		 826mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
827 uint8_t *data)
b8f126a8
SW		 828{
829 int i;
830
89f09048
FF		 831 if (stringset != ETH_SS_STATS)
832 return;
833
b8f126a8
SW		 834 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
835 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
836 ETH_GSTRING_LEN);
837}
838
839static void
840mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
841 uint64_t *data)
842{
843 struct mt7530_priv *priv = ds->priv;
844 const struct mt7530_mib_desc *mib;
845 u32 reg, i;
846 u64 hi;
847
848 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
849 mib = &mt7530_mib[i];
850 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
851
852 data[i] = mt7530_read(priv, reg);
853 if (mib->size == 2) {
854 hi = mt7530_read(priv, reg + 4);
855 data[i] |= hi << 32;
856 }
857 }
858}
859
860static int
89f09048 861mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
b8f126a8 862{
89f09048
FF		 863 if (sset != ETH_SS_STATS)
864 return 0;
865
b8f126a8
SW		 866 return ARRAY_SIZE(mt7530_mib);
867}
868
ea6d5c92
DQ		 869static int
870mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
871{
872 struct mt7530_priv *priv = ds->priv;
873 unsigned int secs = msecs / 1000;
874 unsigned int tmp_age_count;
875 unsigned int error = -1;
876 unsigned int age_count;
877 unsigned int age_unit;
878
879 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
880 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
881 return -ERANGE;
882
883 /* iterate through all possible age_count to find the closest pair */
884 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
885 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
886
887 if (tmp_age_unit <= AGE_UNIT_MAX) {
888 unsigned int tmp_error = secs -
889 (tmp_age_count + 1) * (tmp_age_unit + 1);
890
891 /* found a closer pair */
892 if (error > tmp_error) {
893 error = tmp_error;
894 age_count = tmp_age_count;
895 age_unit = tmp_age_unit;
896 }
897
898 /* found the exact match, so break the loop */
899 if (!error)
900 break;
901 }
902 }
903
904 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
905
906 return 0;
907}
908
38f790a8
RD		 909static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
910{
911 struct mt7530_priv *priv = ds->priv;
912 u8 tx_delay = 0;
913 int val;
914
915 mutex_lock(&priv->reg_mutex);
916
917 val = mt7530_read(priv, MT7530_MHWTRAP);
918
919 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
920 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
921
922 switch (priv->p5_intf_sel) {
923 case P5_INTF_SEL_PHY_P0:
924 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
925 val |= MHWTRAP_PHY0_SEL;
df561f66 926 fallthrough;
38f790a8
RD		 927 case P5_INTF_SEL_PHY_P4:
928 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
929 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
930
931 /* Setup the MAC by default for the cpu port */
932 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
933 break;
934 case P5_INTF_SEL_GMAC5:
935 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
936 val &= ~MHWTRAP_P5_DIS;
937 break;
938 case P5_DISABLED:
939 interface = PHY_INTERFACE_MODE_NA;
940 break;
941 default:
942 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
943 priv->p5_intf_sel);
944 goto unlock_exit;
945 }
946
947 /* Setup RGMII settings */
948 if (phy_interface_mode_is_rgmii(interface)) {
949 val |= MHWTRAP_P5_RGMII_MODE;
950
951 /* P5 RGMII RX Clock Control: delay setting for 1000M */
952 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
953
954 /* Don't set delay in DSA mode */
955 if (!dsa_is_dsa_port(priv->ds, 5) &&
956 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
957 interface == PHY_INTERFACE_MODE_RGMII_ID))
958 tx_delay = 4; /* n * 0.5 ns */
959
960 /* P5 RGMII TX Clock Control: delay x */
961 mt7530_write(priv, MT7530_P5RGMIITXCR,
962 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
963
964 /* reduce P5 RGMII Tx driving, 8mA */
965 mt7530_write(priv, MT7530_IO_DRV_CR,
966 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
967 }
968
969 mt7530_write(priv, MT7530_MHWTRAP, val);
970
971 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
972 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
973
974 priv->p5_interface = interface;
975
976unlock_exit:
977 mutex_unlock(&priv->reg_mutex);
978}
979
b8f126a8 980static int
c288575f 981mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
b8f126a8 982{
c288575f 983 struct mt7530_priv *priv = ds->priv;
0ce0c3cd 984 int ret;
c288575f
LC		 985
986 /* Setup max capability of CPU port at first */
0ce0c3cd
AD		 987 if (priv->info->cpu_port_config) {
988 ret = priv->info->cpu_port_config(ds, port);
989 if (ret)
990 return ret;
991 }
c288575f 992
b8f126a8
SW		 993 /* Enable Mediatek header mode on the cpu port */
994 mt7530_write(priv, MT7530_PVC_P(port),
995 PORT_SPEC_TAG);
996
5a30833b
DQ		 997 /* Disable flooding by default */
998 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK,
999 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port)));
b8f126a8 1000
ddda1ac1
GU		 1001 /* Set CPU port number */
1002 if (priv->id == ID_MT7621)
1003 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1004
b8f126a8 1005 /* CPU port gets connected to all user ports of
c288575f 1006 * the switch.
b8f126a8
SW		 1007 */
1008 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 1009 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8
SW		 1010
1011 return 0;
1012}
1013
1014static int
1015mt7530_port_enable(struct dsa_switch *ds, int port,
1016 struct phy_device *phy)
1017{
1018 struct mt7530_priv *priv = ds->priv;
1019
74be4bab
VD		 1020 if (!dsa_is_user_port(ds, port))
1021 return 0;
1022
b8f126a8
SW		 1023 mutex_lock(&priv->reg_mutex);
1024
b8f126a8
SW		 1025 /* Allow the user port gets connected to the cpu port and also
1026 * restore the port matrix if the port is the member of a certain
1027 * bridge.
1028 */
1029 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
1030 priv->ports[port].enable = true;
1031 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1032 priv->ports[port].pm);
1d01145f 1033 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1034
1035 mutex_unlock(&priv->reg_mutex);
1036
1037 return 0;
1038}
1039
1040static void
75104db0 1041mt7530_port_disable(struct dsa_switch *ds, int port)
b8f126a8
SW		 1042{
1043 struct mt7530_priv *priv = ds->priv;
1044
74be4bab
VD		 1045 if (!dsa_is_user_port(ds, port))
1046 return;
1047
b8f126a8
SW		 1048 mutex_lock(&priv->reg_mutex);
1049
1050 /* Clear up all port matrix which could be restored in the next
1051 * enablement for the port.
1052 */
1053 priv->ports[port].enable = false;
1054 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1055 PCR_MATRIX_CLR);
1d01145f 1056 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1057
1058 mutex_unlock(&priv->reg_mutex);
1059}
1060
9470174e
DQ		 1061static int
1062mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1063{
1064 struct mt7530_priv *priv = ds->priv;
1065 struct mii_bus *bus = priv->bus;
1066 int length;
1067 u32 val;
1068
1069 /* When a new MTU is set, DSA always set the CPU port's MTU to the
1070 * largest MTU of the slave ports. Because the switch only has a global
1071 * RX length register, only allowing CPU port here is enough.
1072 */
1073 if (!dsa_is_cpu_port(ds, port))
1074 return 0;
1075
1076 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1077
1078 val = mt7530_mii_read(priv, MT7530_GMACCR);
1079 val &= ~MAX_RX_PKT_LEN_MASK;
1080
1081 /* RX length also includes Ethernet header, MTK tag, and FCS length */
1082 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1083 if (length <= 1522) {
1084 val |= MAX_RX_PKT_LEN_1522;
1085 } else if (length <= 1536) {
1086 val |= MAX_RX_PKT_LEN_1536;
1087 } else if (length <= 1552) {
1088 val |= MAX_RX_PKT_LEN_1552;
1089 } else {
1090 val &= ~MAX_RX_JUMBO_MASK;
1091 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1092 val |= MAX_RX_PKT_LEN_JUMBO;
1093 }
1094
1095 mt7530_mii_write(priv, MT7530_GMACCR, val);
1096
1097 mutex_unlock(&bus->mdio_lock);
1098
1099 return 0;
1100}
1101
1102static int
1103mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1104{
1105 return MT7530_MAX_MTU;
1106}
1107
b8f126a8
SW		 1108static void
1109mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1110{
1111 struct mt7530_priv *priv = ds->priv;
1112 u32 stp_state;
1113
1114 switch (state) {
1115 case BR_STATE_DISABLED:
1116 stp_state = MT7530_STP_DISABLED;
1117 break;
1118 case BR_STATE_BLOCKING:
1119 stp_state = MT7530_STP_BLOCKING;
1120 break;
1121 case BR_STATE_LISTENING:
1122 stp_state = MT7530_STP_LISTENING;
1123 break;
1124 case BR_STATE_LEARNING:
1125 stp_state = MT7530_STP_LEARNING;
1126 break;
1127 case BR_STATE_FORWARDING:
1128 default:
1129 stp_state = MT7530_STP_FORWARDING;
1130 break;
1131 }
1132
1133 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
1134}
1135
5a30833b
DQ		 1136static int
1137mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1138 struct switchdev_brport_flags flags,
1139 struct netlink_ext_ack *extack)
1140{
1141 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1142 BR_BCAST_FLOOD))
1143 return -EINVAL;
1144
1145 return 0;
1146}
1147
1148static int
1149mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
1150 struct switchdev_brport_flags flags,
1151 struct netlink_ext_ack *extack)
1152{
1153 struct mt7530_priv *priv = ds->priv;
1154
1155 if (flags.mask & BR_LEARNING)
1156 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
1157 flags.val & BR_LEARNING ? 0 : SA_DIS);
1158
1159 if (flags.mask & BR_FLOOD)
1160 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
1161 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1162
1163 if (flags.mask & BR_MCAST_FLOOD)
1164 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1165 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1166
1167 if (flags.mask & BR_BCAST_FLOOD)
1168 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
1169 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1170
1171 return 0;
1172}
1173
1174static int
1175mt7530_port_set_mrouter(struct dsa_switch *ds, int port, bool mrouter,
1176 struct netlink_ext_ack *extack)
1177{
1178 struct mt7530_priv *priv = ds->priv;
1179
1180 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1181 mrouter ? UNM_FFP(BIT(port)) : 0);
1182
1183 return 0;
1184}
1185
b8f126a8
SW		 1186static int
1187mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1188 struct net_device *bridge)
1189{
1190 struct mt7530_priv *priv = ds->priv;
1191 u32 port_bitmap = BIT(MT7530_CPU_PORT);
1192 int i;
1193
1194 mutex_lock(&priv->reg_mutex);
1195
1196 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1197 /* Add this port to the port matrix of the other ports in the
1198 * same bridge. If the port is disabled, port matrix is kept
1199 * and not being setup until the port becomes enabled.
1200 */
4a5b85ff 1201 if (dsa_is_user_port(ds, i) && i != port) {
c8652c83 1202 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 1203 continue;
1204 if (priv->ports[i].enable)
1205 mt7530_set(priv, MT7530_PCR_P(i),
1206 PCR_MATRIX(BIT(port)));
1207 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
1208
1209 port_bitmap |= BIT(i);
1210 }
1211 }
1212
1213 /* Add the all other ports to this port matrix. */
1214 if (priv->ports[port].enable)
1215 mt7530_rmw(priv, MT7530_PCR_P(port),
1216 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1217 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1218
1219 mutex_unlock(&priv->reg_mutex);
1220
1221 return 0;
1222}
1223
83163f7d
SW		 1224static void
1225mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1226{
1227 struct mt7530_priv *priv = ds->priv;
1228 bool all_user_ports_removed = true;
1229 int i;
1230
1231 /* When a port is removed from the bridge, the port would be set up
1232 * back to the default as is at initial boot which is a VLAN-unaware
1233 * port.
1234 */
1235 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1236 MT7530_PORT_MATRIX_MODE);
e045124e
DQ		 1237 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1238 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
1239 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d 1240
83163f7d
SW		 1241 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1242 if (dsa_is_user_port(ds, i) &&
68bb8ea8 1243 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
83163f7d
SW		 1244 all_user_ports_removed = false;
1245 break;
1246 }
1247 }
1248
1249 /* CPU port also does the same thing until all user ports belonging to
1250 * the CPU port get out of VLAN filtering mode.
1251 */
1252 if (all_user_ports_removed) {
1253 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
1254 PCR_MATRIX(dsa_user_ports(priv->ds)));
e045124e
DQ		 1255 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
1256 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d
SW		 1257 }
1258}
1259
1260static void
1261mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1262{
1263 struct mt7530_priv *priv = ds->priv;
1264
1265 /* The real fabric path would be decided on the membership in the
1266 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
1267 * means potential VLAN can be consisting of certain subset of all
1268 * ports.
1269 */
1270 mt7530_rmw(priv, MT7530_PCR_P(port),
1271 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
1272
1273 /* Trapped into security mode allows packet forwarding through VLAN
38152ea3
DQ		 1274 * table lookup. CPU port is set to fallback mode to let untagged
1275 * frames pass through.
83163f7d 1276 */
38152ea3
DQ		 1277 if (dsa_is_cpu_port(ds, port))
1278 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1279 MT7530_PORT_FALLBACK_MODE);
1280 else
1281 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1282 MT7530_PORT_SECURITY_MODE);
83163f7d
SW		 1283
1284 /* Set the port as a user port which is to be able to recognize VID
1285 * from incoming packets before fetching entry within the VLAN table.
1286 */
e045124e
DQ		 1287 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1288 VLAN_ATTR(MT7530_VLAN_USER) |
1289 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
83163f7d
SW		 1290}
1291
b8f126a8
SW		 1292static void
1293mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1294 struct net_device *bridge)
1295{
1296 struct mt7530_priv *priv = ds->priv;
1297 int i;
1298
1299 mutex_lock(&priv->reg_mutex);
1300
1301 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1302 /* Remove this port from the port matrix of the other ports
1303 * in the same bridge. If the port is disabled, port matrix
1304 * is kept and not being setup until the port becomes enabled.
83163f7d
SW		 1305 * And the other port's port matrix cannot be broken when the
1306 * other port is still a VLAN-aware port.
b8f126a8 1307 */
2a130551 1308 if (dsa_is_user_port(ds, i) && i != port &&
68bb8ea8 1309 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
c8652c83 1310 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 1311 continue;
1312 if (priv->ports[i].enable)
1313 mt7530_clear(priv, MT7530_PCR_P(i),
1314 PCR_MATRIX(BIT(port)));
1315 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
1316 }
1317 }
1318
1319 /* Set the cpu port to be the only one in the port matrix of
1320 * this port.
1321 */
1322 if (priv->ports[port].enable)
1323 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1324 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
1325 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
1326
1327 mutex_unlock(&priv->reg_mutex);
1328}
1329
1330static int
b8f126a8 1331mt7530_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 1332 const unsigned char *addr, u16 vid)
b8f126a8
SW		 1333{
1334 struct mt7530_priv *priv = ds->priv;
1b6dd556 1335 int ret;
b8f126a8
SW		 1336 u8 port_mask = BIT(port);
1337
1338 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1339 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 1340 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 1341 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 1342
1343 return ret;
b8f126a8
SW		 1344}
1345
1346static int
1347mt7530_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1348 const unsigned char *addr, u16 vid)
b8f126a8
SW		 1349{
1350 struct mt7530_priv *priv = ds->priv;
1351 int ret;
1352 u8 port_mask = BIT(port);
1353
1354 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1355 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 1356 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 1357 mutex_unlock(&priv->reg_mutex);
1358
1359 return ret;
1360}
1361
1362static int
1363mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1364 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 1365{
1366 struct mt7530_priv *priv = ds->priv;
1367 struct mt7530_fdb _fdb = { 0 };
1368 int cnt = MT7530_NUM_FDB_RECORDS;
1369 int ret = 0;
1370 u32 rsp = 0;
1371
1372 mutex_lock(&priv->reg_mutex);
1373
1374 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1375 if (ret < 0)
1376 goto err;
1377
1378 do {
1379 if (rsp & ATC_SRCH_HIT) {
1380 mt7530_fdb_read(priv, &_fdb);
1381 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 1382 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1383 data);
b8f126a8
SW		 1384 if (ret < 0)
1385 break;
1386 }
1387 }
1388 } while (--cnt &&
1389 !(rsp & ATC_SRCH_END) &&
1390 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1391err:
1392 mutex_unlock(&priv->reg_mutex);
1393
1394 return 0;
1395}
1396
5a30833b
DQ		 1397static int
1398mt7530_port_mdb_add(struct dsa_switch *ds, int port,
1399 const struct switchdev_obj_port_mdb *mdb)
1400{
1401 struct mt7530_priv *priv = ds->priv;
1402 const u8 *addr = mdb->addr;
1403 u16 vid = mdb->vid;
1404 u8 port_mask = 0;
1405 int ret;
1406
1407 mutex_lock(&priv->reg_mutex);
1408
1409 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1410 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1411 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1412 & PORT_MAP_MASK;
1413
1414 port_mask |= BIT(port);
1415 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1416 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1417
1418 mutex_unlock(&priv->reg_mutex);
1419
1420 return ret;
1421}
1422
1423static int
1424mt7530_port_mdb_del(struct dsa_switch *ds, int port,
1425 const struct switchdev_obj_port_mdb *mdb)
1426{
1427 struct mt7530_priv *priv = ds->priv;
1428 const u8 *addr = mdb->addr;
1429 u16 vid = mdb->vid;
1430 u8 port_mask = 0;
1431 int ret;
1432
1433 mutex_lock(&priv->reg_mutex);
1434
1435 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1436 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1437 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1438 & PORT_MAP_MASK;
1439
1440 port_mask &= ~BIT(port);
1441 mt7530_fdb_write(priv, vid, port_mask, addr, -1,
1442 port_mask ? STATIC_ENT : STATIC_EMP);
1443 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1444
1445 mutex_unlock(&priv->reg_mutex);
1446
1447 return ret;
1448}
1449
83163f7d
SW		 1450static int
1451mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1452{
1453 struct mt7530_dummy_poll p;
1454 u32 val;
1455 int ret;
1456
1457 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1458 mt7530_write(priv, MT7530_VTCR, val);
1459
1460 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1461 ret = readx_poll_timeout(_mt7530_read, &p, val,
1462 !(val & VTCR_BUSY), 20, 20000);
1463 if (ret < 0) {
1464 dev_err(priv->dev, "poll timeout\n");
1465 return ret;
1466 }
1467
1468 val = mt7530_read(priv, MT7530_VTCR);
1469 if (val & VTCR_INVALID) {
1470 dev_err(priv->dev, "read VTCR invalid\n");
1471 return -EINVAL;
1472 }
1473
1474 return 0;
1475}
1476
1477static int
89153ed6
VO		 1478mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1479 struct netlink_ext_ack *extack)
83163f7d 1480{
83163f7d
SW		 1481 if (vlan_filtering) {
1482 /* The port is being kept as VLAN-unaware port when bridge is
1483 * set up with vlan_filtering not being set, Otherwise, the
1484 * port and the corresponding CPU port is required the setup
1485 * for becoming a VLAN-aware port.
1486 */
1487 mt7530_port_set_vlan_aware(ds, port);
1488 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
e3ee07d1
VO		 1489 } else {
1490 mt7530_port_set_vlan_unaware(ds, port);
83163f7d
SW		 1491 }
1492
1493 return 0;
1494}
1495
83163f7d
SW		 1496static void
1497mt7530_hw_vlan_add(struct mt7530_priv *priv,
1498 struct mt7530_hw_vlan_entry *entry)
1499{
1500 u8 new_members;
1501 u32 val;
1502
1503 new_members = entry->old_members | BIT(entry->port) |
1504 BIT(MT7530_CPU_PORT);
1505
1506 /* Validate the entry with independent learning, create egress tag per
1507 * VLAN and joining the port as one of the port members.
1508 */
1509 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1510 mt7530_write(priv, MT7530_VAWD1, val);
1511
1512 /* Decide whether adding tag or not for those outgoing packets from the
1513 * port inside the VLAN.
1514 */
1515 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1516 MT7530_VLAN_EGRESS_TAG;
1517 mt7530_rmw(priv, MT7530_VAWD2,
1518 ETAG_CTRL_P_MASK(entry->port),
1519 ETAG_CTRL_P(entry->port, val));
1520
1521 /* CPU port is always taken as a tagged port for serving more than one
1522 * VLANs across and also being applied with egress type stack mode for
1523 * that VLAN tags would be appended after hardware special tag used as
1524 * DSA tag.
1525 */
1526 mt7530_rmw(priv, MT7530_VAWD2,
1527 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1528 ETAG_CTRL_P(MT7530_CPU_PORT,
1529 MT7530_VLAN_EGRESS_STACK));
1530}
1531
1532static void
1533mt7530_hw_vlan_del(struct mt7530_priv *priv,
1534 struct mt7530_hw_vlan_entry *entry)
1535{
1536 u8 new_members;
1537 u32 val;
1538
1539 new_members = entry->old_members & ~BIT(entry->port);
1540
1541 val = mt7530_read(priv, MT7530_VAWD1);
1542 if (!(val & VLAN_VALID)) {
1543 dev_err(priv->dev,
1544 "Cannot be deleted due to invalid entry\n");
1545 return;
1546 }
1547
1548 /* If certain member apart from CPU port is still alive in the VLAN,
1549 * the entry would be kept valid. Otherwise, the entry is got to be
1550 * disabled.
1551 */
1552 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1553 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1554 VLAN_VALID;
1555 mt7530_write(priv, MT7530_VAWD1, val);
1556 } else {
1557 mt7530_write(priv, MT7530_VAWD1, 0);
1558 mt7530_write(priv, MT7530_VAWD2, 0);
1559 }
1560}
1561
1562static void
1563mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1564 struct mt7530_hw_vlan_entry *entry,
1565 mt7530_vlan_op vlan_op)
1566{
1567 u32 val;
1568
1569 /* Fetch entry */
1570 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1571
1572 val = mt7530_read(priv, MT7530_VAWD1);
1573
1574 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1575
1576 /* Manipulate entry */
1577 vlan_op(priv, entry);
1578
1579 /* Flush result to hardware */
1580 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1581}
1582
1958d581 1583static int
83163f7d 1584mt7530_port_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 1585 const struct switchdev_obj_port_vlan *vlan,
1586 struct netlink_ext_ack *extack)
83163f7d
SW		 1587{
1588 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1589 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1590 struct mt7530_hw_vlan_entry new_entry;
1591 struct mt7530_priv *priv = ds->priv;
83163f7d 1592
83163f7d
SW		 1593 mutex_lock(&priv->reg_mutex);
1594
b7a9e0da
VO		 1595 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1596 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
83163f7d
SW		 1597
1598 if (pvid) {
1599 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
b7a9e0da
VO		 1600 G0_PORT_VID(vlan->vid));
1601 priv->ports[port].pvid = vlan->vid;
83163f7d
SW		 1602 }
1603
1604 mutex_unlock(&priv->reg_mutex);
1958d581
VO		 1605
1606 return 0;
83163f7d
SW		 1607}
1608
1609static int
1610mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1611 const struct switchdev_obj_port_vlan *vlan)
1612{
1613 struct mt7530_hw_vlan_entry target_entry;
1614 struct mt7530_priv *priv = ds->priv;
b7a9e0da 1615 u16 pvid;
83163f7d 1616
83163f7d
SW		 1617 mutex_lock(&priv->reg_mutex);
1618
1619 pvid = priv->ports[port].pvid;
b7a9e0da
VO		 1620 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1621 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1622 mt7530_hw_vlan_del);
83163f7d 1623
b7a9e0da
VO		 1624 /* PVID is being restored to the default whenever the PVID port
1625 * is being removed from the VLAN.
1626 */
1627 if (pvid == vlan->vid)
1628 pvid = G0_PORT_VID_DEF;
83163f7d
SW		 1629
1630 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1631 priv->ports[port].pvid = pvid;
1632
1633 mutex_unlock(&priv->reg_mutex);
1634
1635 return 0;
1636}
1637
c288575f
LC		 1638static int mt753x_mirror_port_get(unsigned int id, u32 val)
1639{
1640 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1641 MIRROR_PORT(val);
1642}
1643
1644static int mt753x_mirror_port_set(unsigned int id, u32 val)
1645{
1646 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1647 MIRROR_PORT(val);
1648}
1649
1650static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
37feab60
DQ		 1651 struct dsa_mall_mirror_tc_entry *mirror,
1652 bool ingress)
1653{
1654 struct mt7530_priv *priv = ds->priv;
c288575f 1655 int monitor_port;
37feab60
DQ		 1656 u32 val;
1657
1658 /* Check for existent entry */
1659 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1660 return -EEXIST;
1661
c288575f 1662 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
37feab60
DQ		 1663
1664 /* MT7530 only supports one monitor port */
c288575f
LC		 1665 monitor_port = mt753x_mirror_port_get(priv->id, val);
1666 if (val & MT753X_MIRROR_EN(priv->id) &&
1667 monitor_port != mirror->to_local_port)
37feab60
DQ		 1668 return -EEXIST;
1669
c288575f
LC		 1670 val |= MT753X_MIRROR_EN(priv->id);
1671 val &= ~MT753X_MIRROR_MASK(priv->id);
1672 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1673 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1674
1675 val = mt7530_read(priv, MT7530_PCR_P(port));
1676 if (ingress) {
1677 val |= PORT_RX_MIR;
1678 priv->mirror_rx |= BIT(port);
1679 } else {
1680 val |= PORT_TX_MIR;
1681 priv->mirror_tx |= BIT(port);
1682 }
1683 mt7530_write(priv, MT7530_PCR_P(port), val);
1684
1685 return 0;
1686}
1687
c288575f 1688static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
37feab60
DQ		 1689 struct dsa_mall_mirror_tc_entry *mirror)
1690{
1691 struct mt7530_priv *priv = ds->priv;
1692 u32 val;
1693
1694 val = mt7530_read(priv, MT7530_PCR_P(port));
1695 if (mirror->ingress) {
1696 val &= ~PORT_RX_MIR;
1697 priv->mirror_rx &= ~BIT(port);
1698 } else {
1699 val &= ~PORT_TX_MIR;
1700 priv->mirror_tx &= ~BIT(port);
1701 }
1702 mt7530_write(priv, MT7530_PCR_P(port), val);
1703
1704 if (!priv->mirror_rx && !priv->mirror_tx) {
c288575f
LC		 1705 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1706 val &= ~MT753X_MIRROR_EN(priv->id);
1707 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1708 }
1709}
1710
b8f126a8 1711static enum dsa_tag_protocol
4d776482
FF		 1712mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1713 enum dsa_tag_protocol mp)
b8f126a8
SW		 1714{
1715 struct mt7530_priv *priv = ds->priv;
1716
5ed4e3eb 1717 if (port != MT7530_CPU_PORT) {
b8f126a8
SW		 1718 dev_warn(priv->dev,
1719 "port not matched with tagging CPU port\n");
1720 return DSA_TAG_PROTO_NONE;
1721 } else {
1722 return DSA_TAG_PROTO_MTK;
1723 }
1724}
1725
63c75c05 1726#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 1727static inline u32
1728mt7530_gpio_to_bit(unsigned int offset)
1729{
1730 /* Map GPIO offset to register bit
1731 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2
1732 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5
1733 * [10: 8] port 2 LED 0..2 as GPIO 6..8
1734 * [14:12] port 3 LED 0..2 as GPIO 9..11
1735 * [18:16] port 4 LED 0..2 as GPIO 12..14
1736 */
1737 return BIT(offset + offset / 3);
1738}
1739
1740static int
1741mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1742{
1743 struct mt7530_priv *priv = gpiochip_get_data(gc);
1744 u32 bit = mt7530_gpio_to_bit(offset);
1745
1746 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1747}
1748
1749static void
1750mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1751{
1752 struct mt7530_priv *priv = gpiochip_get_data(gc);
1753 u32 bit = mt7530_gpio_to_bit(offset);
1754
1755 if (value)
1756 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1757 else
1758 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1759}
1760
1761static int
1762mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1763{
1764 struct mt7530_priv *priv = gpiochip_get_data(gc);
1765 u32 bit = mt7530_gpio_to_bit(offset);
1766
1767 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1768 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1769}
1770
1771static int
1772mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1773{
1774 struct mt7530_priv *priv = gpiochip_get_data(gc);
1775 u32 bit = mt7530_gpio_to_bit(offset);
1776
1777 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1778 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1779
1780 return 0;
1781}
1782
1783static int
1784mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1785{
1786 struct mt7530_priv *priv = gpiochip_get_data(gc);
1787 u32 bit = mt7530_gpio_to_bit(offset);
1788
1789 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1790
1791 if (value)
1792 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1793 else
1794 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1795
1796 mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1797
1798 return 0;
1799}
1800
1801static int
1802mt7530_setup_gpio(struct mt7530_priv *priv)
1803{
1804 struct device *dev = priv->dev;
1805 struct gpio_chip *gc;
1806
1807 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1808 if (!gc)
1809 return -ENOMEM;
1810
1811 mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1812 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1813 mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1814
1815 gc->label = "mt7530";
1816 gc->parent = dev;
1817 gc->owner = THIS_MODULE;
1818 gc->get_direction = mt7530_gpio_get_direction;
1819 gc->direction_input = mt7530_gpio_direction_input;
1820 gc->direction_output = mt7530_gpio_direction_output;
1821 gc->get = mt7530_gpio_get;
1822 gc->set = mt7530_gpio_set;
1823 gc->base = -1;
1824 gc->ngpio = 15;
1825 gc->can_sleep = true;
1826
1827 return devm_gpiochip_add_data(dev, gc, priv);
1828}
63c75c05 1829#endif /* CONFIG_GPIOLIB */
429a0ede 1830
b8f126a8
SW		 1831static int
1832mt7530_setup(struct dsa_switch *ds)
1833{
1834 struct mt7530_priv *priv = ds->priv;
38f790a8
RD		 1835 struct device_node *phy_node;
1836 struct device_node *mac_np;
b8f126a8 1837 struct mt7530_dummy_poll p;
38f790a8 1838 phy_interface_t interface;
ca366d6c
RD		 1839 struct device_node *dn;
1840 u32 id, val;
1841 int ret, i;
b8f126a8 1842
0abfd494 1843 /* The parent node of master netdev which holds the common system
b8f126a8
SW		 1844 * controller also is the container for two GMACs nodes representing
1845 * as two netdev instances.
1846 */
68bb8ea8 1847 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
771c8901 1848 ds->mtu_enforcement_ingress = true;
b8f126a8 1849
ddda1ac1 1850 if (priv->id == ID_MT7530) {
ddda1ac1
GU		 1851 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1852 ret = regulator_enable(priv->core_pwr);
1853 if (ret < 0) {
1854 dev_err(priv->dev,
1855 "Failed to enable core power: %d\n", ret);
1856 return ret;
1857 }
b8f126a8 1858
ddda1ac1
GU		 1859 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1860 ret = regulator_enable(priv->io_pwr);
1861 if (ret < 0) {
1862 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1863 ret);
1864 return ret;
1865 }
b8f126a8
SW		 1866 }
1867
1868 /* Reset whole chip through gpio pin or memory-mapped registers for
1869 * different type of hardware
1870 */
1871 if (priv->mcm) {
1872 reset_control_assert(priv->rstc);
1873 usleep_range(1000, 1100);
1874 reset_control_deassert(priv->rstc);
1875 } else {
1876 gpiod_set_value_cansleep(priv->reset, 0);
1877 usleep_range(1000, 1100);
1878 gpiod_set_value_cansleep(priv->reset, 1);
1879 }
1880
1881 /* Waiting for MT7530 got to stable */
1882 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1883 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1884 20, 1000000);
1885 if (ret < 0) {
1886 dev_err(priv->dev, "reset timeout\n");
1887 return ret;
1888 }
1889
1890 id = mt7530_read(priv, MT7530_CREV);
1891 id >>= CHIP_NAME_SHIFT;
1892 if (id != MT7530_ID) {
1893 dev_err(priv->dev, "chip %x can't be supported\n", id);
1894 return -ENODEV;
1895 }
1896
1897 /* Reset the switch through internal reset */
1898 mt7530_write(priv, MT7530_SYS_CTRL,
1899 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1900 SYS_CTRL_REG_RST);
1901
1902 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1903 val = mt7530_read(priv, MT7530_MHWTRAP);
1904 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1905 val |= MHWTRAP_MANUAL;
1906 mt7530_write(priv, MT7530_MHWTRAP, val);
1907
ca366d6c
RD		 1908 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1909
b8f126a8
SW		 1910 /* Enable and reset MIB counters */
1911 mt7530_mib_reset(ds);
1912
b8f126a8
SW		 1913 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1914 /* Disable forwarding by default on all ports */
1915 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1916 PCR_MATRIX_CLR);
1917
0ce0c3cd
AD		 1918 if (dsa_is_cpu_port(ds, i)) {
1919 ret = mt753x_cpu_port_enable(ds, i);
1920 if (ret)
1921 return ret;
5a30833b 1922 } else {
75104db0 1923 mt7530_port_disable(ds, i);
e045124e 1924
5a30833b
DQ		 1925 /* Disable learning by default on all user ports */
1926 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
1927 }
e045124e
DQ		 1928 /* Enable consistent egress tag */
1929 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1930 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
b8f126a8
SW		 1931 }
1932
38f790a8
RD		 1933 /* Setup port 5 */
1934 priv->p5_intf_sel = P5_DISABLED;
1935 interface = PHY_INTERFACE_MODE_NA;
1936
1937 if (!dsa_is_unused_port(ds, 5)) {
1938 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
0c65b2b9
AL		 1939 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
1940 if (ret && ret != -ENODEV)
1941 return ret;
38f790a8
RD		 1942 } else {
1943 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1944 for_each_child_of_node(dn, mac_np) {
1945 if (!of_device_is_compatible(mac_np,
1946 "mediatek,eth-mac"))
1947 continue;
1948
1949 ret = of_property_read_u32(mac_np, "reg", &id);
1950 if (ret < 0 || id != 1)
1951 continue;
1952
1953 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
0452800f
CG		 1954 if (!phy_node)
1955 continue;
1956
38f790a8 1957 if (phy_node->parent == priv->dev->of_node->parent) {
0c65b2b9 1958 ret = of_get_phy_mode(mac_np, &interface);
8e4efd47
SP		 1959 if (ret && ret != -ENODEV) {
1960 of_node_put(mac_np);
0c65b2b9 1961 return ret;
8e4efd47 1962 }
38f790a8
RD		 1963 id = of_mdio_parse_addr(ds->dev, phy_node);
1964 if (id == 0)
1965 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1966 if (id == 4)
1967 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1968 }
8e4efd47 1969 of_node_put(mac_np);
38f790a8
RD		 1970 of_node_put(phy_node);
1971 break;
1972 }
1973 }
1974
63c75c05 1975#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 1976 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
1977 ret = mt7530_setup_gpio(priv);
1978 if (ret)
1979 return ret;
1980 }
63c75c05 1981#endif /* CONFIG_GPIOLIB */
429a0ede 1982
38f790a8
RD		 1983 mt7530_setup_port5(ds, interface);
1984
b8f126a8 1985 /* Flush the FDB table */
18bd5949 1986 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 1987 if (ret < 0)
1988 return ret;
1989
1990 return 0;
1991}
1992
c288575f
LC		 1993static int
1994mt7531_setup(struct dsa_switch *ds)
1995{
1996 struct mt7530_priv *priv = ds->priv;
1997 struct mt7530_dummy_poll p;
1998 u32 val, id;
1999 int ret, i;
2000
2001 /* Reset whole chip through gpio pin or memory-mapped registers for
2002 * different type of hardware
2003 */
2004 if (priv->mcm) {
2005 reset_control_assert(priv->rstc);
2006 usleep_range(1000, 1100);
2007 reset_control_deassert(priv->rstc);
2008 } else {
2009 gpiod_set_value_cansleep(priv->reset, 0);
2010 usleep_range(1000, 1100);
2011 gpiod_set_value_cansleep(priv->reset, 1);
2012 }
2013
2014 /* Waiting for MT7530 got to stable */
2015 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2016 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2017 20, 1000000);
2018 if (ret < 0) {
2019 dev_err(priv->dev, "reset timeout\n");
2020 return ret;
2021 }
2022
2023 id = mt7530_read(priv, MT7531_CREV);
2024 id >>= CHIP_NAME_SHIFT;
2025
2026 if (id != MT7531_ID) {
2027 dev_err(priv->dev, "chip %x can't be supported\n", id);
2028 return -ENODEV;
2029 }
2030
2031 /* Reset the switch through internal reset */
2032 mt7530_write(priv, MT7530_SYS_CTRL,
2033 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2034 SYS_CTRL_REG_RST);
2035
2036 if (mt7531_dual_sgmii_supported(priv)) {
2037 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
2038
2039 /* Let ds->slave_mii_bus be able to access external phy. */
2040 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
2041 MT7531_EXT_P_MDC_11);
2042 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
2043 MT7531_EXT_P_MDIO_12);
2044 } else {
2045 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2046 }
2047 dev_dbg(ds->dev, "P5 support %s interface\n",
2048 p5_intf_modes(priv->p5_intf_sel));
2049
2050 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
2051 MT7531_GPIO0_INTERRUPT);
2052
2053 /* Let phylink decide the interface later. */
2054 priv->p5_interface = PHY_INTERFACE_MODE_NA;
2055 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2056
2057 /* Enable PHY core PLL, since phy_device has not yet been created
2058 * provided for phy_[read,write]_mmd_indirect is called, we provide
2059 * our own mt7531_ind_mmd_phy_[read,write] to complete this
2060 * function.
2061 */
2062 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
2063 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2064 val |= MT7531_PHY_PLL_BYPASS_MODE;
2065 val &= ~MT7531_PHY_PLL_OFF;
2066 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
2067 CORE_PLL_GROUP4, val);
2068
2069 /* BPDU to CPU port */
2070 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
2071 BIT(MT7530_CPU_PORT));
2072 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
2073 MT753X_BPDU_CPU_ONLY);
2074
2075 /* Enable and reset MIB counters */
2076 mt7530_mib_reset(ds);
2077
2078 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2079 /* Disable forwarding by default on all ports */
2080 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2081 PCR_MATRIX_CLR);
2082
2083 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
2084
0ce0c3cd
AD		 2085 if (dsa_is_cpu_port(ds, i)) {
2086 ret = mt753x_cpu_port_enable(ds, i);
2087 if (ret)
2088 return ret;
5a30833b 2089 } else {
c288575f
LC		 2090 mt7530_port_disable(ds, i);
2091
5a30833b
DQ		 2092 /* Disable learning by default on all user ports */
2093 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2094 }
2095
c288575f
LC		 2096 /* Enable consistent egress tag */
2097 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2098 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2099 }
2100
771c8901 2101 ds->mtu_enforcement_ingress = true;
c288575f
LC		 2102
2103 /* Flush the FDB table */
2104 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2105 if (ret < 0)
2106 return ret;
2107
2108 return 0;
2109}
2110
88bdef8b
LC		 2111static bool
2112mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
2113 const struct phylink_link_state *state)
ca366d6c
RD		 2114{
2115 struct mt7530_priv *priv = ds->priv;
ca366d6c
RD		 2116
2117 switch (port) {
88bdef8b 2118 case 0 ... 4: /* Internal phy */
ca366d6c 2119 if (state->interface != PHY_INTERFACE_MODE_GMII)
88bdef8b 2120 return false;
ca366d6c 2121 break;
38f790a8 2122 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
38f790a8
RD		 2123 if (!phy_interface_mode_is_rgmii(state->interface) &&
2124 state->interface != PHY_INTERFACE_MODE_MII &&
2125 state->interface != PHY_INTERFACE_MODE_GMII)
88bdef8b
LC		 2126 return false;
2127 break;
2128 case 6: /* 1st cpu port */
2129 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
2130 state->interface != PHY_INTERFACE_MODE_TRGMII)
2131 return false;
2132 break;
2133 default:
2134 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2135 port);
2136 return false;
2137 }
2138
2139 return true;
2140}
2141
c288575f
LC		 2142static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
2143{
2144 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
2145}
2146
2147static bool
2148mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
2149 const struct phylink_link_state *state)
2150{
2151 struct mt7530_priv *priv = ds->priv;
2152
2153 switch (port) {
2154 case 0 ... 4: /* Internal phy */
2155 if (state->interface != PHY_INTERFACE_MODE_GMII)
2156 return false;
2157 break;
2158 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
2159 if (mt7531_is_rgmii_port(priv, port))
2160 return phy_interface_mode_is_rgmii(state->interface);
2161 fallthrough;
2162 case 6: /* 1st cpu port supports sgmii/8023z only */
2163 if (state->interface != PHY_INTERFACE_MODE_SGMII &&
2164 !phy_interface_mode_is_8023z(state->interface))
2165 return false;
2166 break;
2167 default:
2168 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2169 port);
2170 return false;
2171 }
2172
2173 return true;
2174}
2175
88bdef8b
LC		 2176static bool
2177mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
2178 const struct phylink_link_state *state)
2179{
2180 struct mt7530_priv *priv = ds->priv;
2181
2182 return priv->info->phy_mode_supported(ds, port, state);
2183}
2184
2185static int
2186mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2187{
2188 struct mt7530_priv *priv = ds->priv;
2189
2190 return priv->info->pad_setup(ds, state->interface);
2191}
2192
2193static int
2194mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2195 phy_interface_t interface)
2196{
2197 struct mt7530_priv *priv = ds->priv;
2198
2199 /* Only need to setup port5. */
2200 if (port != 5)
2201 return 0;
2202
2203 mt7530_setup_port5(priv->ds, interface);
2204
2205 return 0;
2206}
2207
c288575f
LC		 2208static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2209 phy_interface_t interface,
2210 struct phy_device *phydev)
2211{
2212 u32 val;
2213
2214 if (!mt7531_is_rgmii_port(priv, port)) {
2215 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2216 port);
2217 return -EINVAL;
2218 }
2219
2220 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2221 val |= GP_CLK_EN;
2222 val &= ~GP_MODE_MASK;
2223 val |= GP_MODE(MT7531_GP_MODE_RGMII);
2224 val &= ~CLK_SKEW_IN_MASK;
2225 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2226 val &= ~CLK_SKEW_OUT_MASK;
2227 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2228 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2229
2230 /* Do not adjust rgmii delay when vendor phy driver presents. */
2231 if (!phydev || phy_driver_is_genphy(phydev)) {
2232 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2233 switch (interface) {
2234 case PHY_INTERFACE_MODE_RGMII:
2235 val |= TXCLK_NO_REVERSE;
2236 val |= RXCLK_NO_DELAY;
2237 break;
2238 case PHY_INTERFACE_MODE_RGMII_RXID:
2239 val |= TXCLK_NO_REVERSE;
2240 break;
2241 case PHY_INTERFACE_MODE_RGMII_TXID:
2242 val |= RXCLK_NO_DELAY;
2243 break;
2244 case PHY_INTERFACE_MODE_RGMII_ID:
2245 break;
2246 default:
2247 return -EINVAL;
2248 }
2249 }
2250 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2251
2252 return 0;
2253}
2254
2255static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
2256 unsigned long *supported)
2257{
2258 /* Port5 supports ethier RGMII or SGMII.
2259 * Port6 supports SGMII only.
2260 */
2261 switch (port) {
2262 case 5:
2263 if (mt7531_is_rgmii_port(priv, port))
2264 break;
2265 fallthrough;
2266 case 6:
2267 phylink_set(supported, 1000baseX_Full);
2268 phylink_set(supported, 2500baseX_Full);
2269 phylink_set(supported, 2500baseT_Full);
2270 }
2271}
2272
2273static void
2274mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
2275 unsigned int mode, phy_interface_t interface,
2276 int speed, int duplex)
2277{
2278 struct mt7530_priv *priv = ds->priv;
2279 unsigned int val;
2280
2281 /* For adjusting speed and duplex of SGMII force mode. */
2282 if (interface != PHY_INTERFACE_MODE_SGMII ||
2283 phylink_autoneg_inband(mode))
2284 return;
2285
2286 /* SGMII force mode setting */
2287 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
2288 val &= ~MT7531_SGMII_IF_MODE_MASK;
2289
2290 switch (speed) {
2291 case SPEED_10:
2292 val |= MT7531_SGMII_FORCE_SPEED_10;
2293 break;
2294 case SPEED_100:
2295 val |= MT7531_SGMII_FORCE_SPEED_100;
2296 break;
2297 case SPEED_1000:
2298 val |= MT7531_SGMII_FORCE_SPEED_1000;
2299 break;
2300 }
2301
2302 /* MT7531 SGMII 1G force mode can only work in full duplex mode,
2303 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2304 */
2305 if ((speed == SPEED_10 || speed == SPEED_100) &&
2306 duplex != DUPLEX_FULL)
2307 val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2308
2309 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2310}
2311
2312static bool mt753x_is_mac_port(u32 port)
2313{
2314 return (port == 5 || port == 6);
2315}
2316
2317static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2318 phy_interface_t interface)
2319{
2320 u32 val;
2321
2322 if (!mt753x_is_mac_port(port))
2323 return -EINVAL;
2324
2325 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2326 MT7531_SGMII_PHYA_PWD);
2327
2328 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2329 val &= ~MT7531_RG_TPHY_SPEED_MASK;
2330 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2331 * encoding.
2332 */
2333 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2334 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2335 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2336
2337 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2338
2339 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2340 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2341 */
2342 mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2343 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2344 MT7531_SGMII_FORCE_SPEED_1000);
2345
2346 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2347
2348 return 0;
2349}
2350
2351static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2352 phy_interface_t interface)
2353{
2354 if (!mt753x_is_mac_port(port))
2355 return -EINVAL;
2356
2357 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2358 MT7531_SGMII_PHYA_PWD);
2359
2360 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2361 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2362
2363 mt7530_set(priv, MT7531_SGMII_MODE(port),
2364 MT7531_SGMII_REMOTE_FAULT_DIS |
2365 MT7531_SGMII_SPEED_DUPLEX_AN);
2366
2367 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2368 MT7531_SGMII_TX_CONFIG_MASK, 1);
2369
2370 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2371
2372 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2373
2374 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2375
2376 return 0;
2377}
2378
2379static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
2380{
2381 struct mt7530_priv *priv = ds->priv;
2382 u32 val;
2383
2384 /* Only restart AN when AN is enabled */
2385 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2386 if (val & MT7531_SGMII_AN_ENABLE) {
2387 val |= MT7531_SGMII_AN_RESTART;
2388 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2389 }
2390}
2391
2392static int
2393mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2394 phy_interface_t interface)
2395{
2396 struct mt7530_priv *priv = ds->priv;
2397 struct phy_device *phydev;
2398 struct dsa_port *dp;
2399
2400 if (!mt753x_is_mac_port(port)) {
2401 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2402 return -EINVAL;
2403 }
2404
2405 switch (interface) {
2406 case PHY_INTERFACE_MODE_RGMII:
2407 case PHY_INTERFACE_MODE_RGMII_ID:
2408 case PHY_INTERFACE_MODE_RGMII_RXID:
2409 case PHY_INTERFACE_MODE_RGMII_TXID:
2410 dp = dsa_to_port(ds, port);
2411 phydev = dp->slave->phydev;
2412 return mt7531_rgmii_setup(priv, port, interface, phydev);
2413 case PHY_INTERFACE_MODE_SGMII:
2414 return mt7531_sgmii_setup_mode_an(priv, port, interface);
2415 case PHY_INTERFACE_MODE_NA:
2416 case PHY_INTERFACE_MODE_1000BASEX:
2417 case PHY_INTERFACE_MODE_2500BASEX:
2418 if (phylink_autoneg_inband(mode))
2419 return -EINVAL;
2420
2421 return mt7531_sgmii_setup_mode_force(priv, port, interface);
2422 default:
2423 return -EINVAL;
2424 }
2425
2426 return -EINVAL;
2427}
2428
88bdef8b
LC		 2429static int
2430mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2431 const struct phylink_link_state *state)
2432{
2433 struct mt7530_priv *priv = ds->priv;
2434
2435 return priv->info->mac_port_config(ds, port, mode, state->interface);
2436}
2437
2438static void
2439mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2440 const struct phylink_link_state *state)
2441{
2442 struct mt7530_priv *priv = ds->priv;
2443 u32 mcr_cur, mcr_new;
2444
2445 if (!mt753x_phy_mode_supported(ds, port, state))
2446 goto unsupported;
2447
2448 switch (port) {
2449 case 0 ... 4: /* Internal phy */
2450 if (state->interface != PHY_INTERFACE_MODE_GMII)
2451 goto unsupported;
2452 break;
2453 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2454 if (priv->p5_interface == state->interface)
2455 break;
2456
2457 if (mt753x_mac_config(ds, port, mode, state) < 0)
2458 goto unsupported;
38f790a8 2459
c288575f
LC		 2460 if (priv->p5_intf_sel != P5_DISABLED)
2461 priv->p5_interface = state->interface;
38f790a8 2462 break;
ca366d6c
RD		 2463 case 6: /* 1st cpu port */
2464 if (priv->p6_interface == state->interface)
2465 break;
2466
88bdef8b 2467 mt753x_pad_setup(ds, state);
ca366d6c 2468
88bdef8b
LC		 2469 if (mt753x_mac_config(ds, port, mode, state) < 0)
2470 goto unsupported;
ca366d6c 2471
ca366d6c
RD		 2472 priv->p6_interface = state->interface;
2473 break;
2474 default:
88bdef8b
LC		 2475unsupported:
2476 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2477 __func__, phy_modes(state->interface), port);
ca366d6c
RD		 2478 return;
2479 }
2480
c288575f
LC		 2481 if (phylink_autoneg_inband(mode) &&
2482 state->interface != PHY_INTERFACE_MODE_SGMII) {
ca366d6c
RD		 2483 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
2484 __func__);
2485 return;
2486 }
2487
2488 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2489 mcr_new = mcr_cur;
1d01145f 2490 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
ca366d6c 2491 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
c288575f 2492 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
ca366d6c 2493
38f790a8
RD		 2494 /* Are we connected to external phy */
2495 if (port == 5 && dsa_is_user_port(ds, 5))
2496 mcr_new |= PMCR_EXT_PHY;
2497
ca366d6c
RD		 2498 if (mcr_new != mcr_cur)
2499 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2500}
2501
c288575f
LC		 2502static void
2503mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
2504{
2505 struct mt7530_priv *priv = ds->priv;
2506
2507 if (!priv->info->mac_pcs_an_restart)
2508 return;
2509
2510 priv->info->mac_pcs_an_restart(ds, port);
2511}
2512
2513static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
ca366d6c
RD		 2514 unsigned int mode,
2515 phy_interface_t interface)
2516{
2517 struct mt7530_priv *priv = ds->priv;
2518
1d01145f 2519 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
ca366d6c
RD		 2520}
2521
c288575f
LC		 2522static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
2523 unsigned int mode, phy_interface_t interface,
2524 int speed, int duplex)
2525{
2526 struct mt7530_priv *priv = ds->priv;
2527
2528 if (!priv->info->mac_pcs_link_up)
2529 return;
2530
2531 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2532}
2533
2534static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
ca366d6c
RD		 2535 unsigned int mode,
2536 phy_interface_t interface,
5b502a7b
RK		 2537 struct phy_device *phydev,
2538 int speed, int duplex,
2539 bool tx_pause, bool rx_pause)
ca366d6c
RD		 2540{
2541 struct mt7530_priv *priv = ds->priv;
1d01145f
RD		 2542 u32 mcr;
2543
c288575f
LC		 2544 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2545
1d01145f
RD		 2546 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2547
c288575f
LC		 2548 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2549 * variants.
2550 */
2551 if (interface == PHY_INTERFACE_MODE_TRGMII ||
2552 (phy_interface_mode_is_8023z(interface))) {
2553 speed = SPEED_1000;
2554 duplex = DUPLEX_FULL;
2555 }
2556
1d01145f
RD		 2557 switch (speed) {
2558 case SPEED_1000:
2559 mcr |= PMCR_FORCE_SPEED_1000;
2560 break;
2561 case SPEED_100:
2562 mcr |= PMCR_FORCE_SPEED_100;
2563 break;
2564 }
2565 if (duplex == DUPLEX_FULL) {
2566 mcr |= PMCR_FORCE_FDX;
2567 if (tx_pause)
2568 mcr |= PMCR_TX_FC_EN;
2569 if (rx_pause)
2570 mcr |= PMCR_RX_FC_EN;
2571 }
ca366d6c 2572
40b5d2f1
RD		 2573 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) {
2574 switch (speed) {
2575 case SPEED_1000:
2576 mcr |= PMCR_FORCE_EEE1G;
2577 break;
2578 case SPEED_100:
2579 mcr |= PMCR_FORCE_EEE100;
2580 break;
2581 }
2582 }
2583
1d01145f 2584 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
ca366d6c
RD		 2585}
2586
c288575f
LC		 2587static int
2588mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2589{
2590 struct mt7530_priv *priv = ds->priv;
2591 phy_interface_t interface;
2592 int speed;
0ce0c3cd 2593 int ret;
c288575f
LC		 2594
2595 switch (port) {
2596 case 5:
2597 if (mt7531_is_rgmii_port(priv, port))
2598 interface = PHY_INTERFACE_MODE_RGMII;
2599 else
2600 interface = PHY_INTERFACE_MODE_2500BASEX;
2601
2602 priv->p5_interface = interface;
2603 break;
2604 case 6:
2605 interface = PHY_INTERFACE_MODE_2500BASEX;
2606
2607 mt7531_pad_setup(ds, interface);
2608
2609 priv->p6_interface = interface;
2610 break;
0ce0c3cd
AD		 2611 default:
2612 return -EINVAL;
c288575f
LC		 2613 }
2614
2615 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2616 speed = SPEED_2500;
2617 else
2618 speed = SPEED_1000;
2619
0ce0c3cd
AD		 2620 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2621 if (ret)
2622 return ret;
c288575f
LC		 2623 mt7530_write(priv, MT7530_PMCR_P(port),
2624 PMCR_CPU_PORT_SETTING(priv->id));
2625 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2626 speed, DUPLEX_FULL, true, true);
2627
2628 return 0;
2629}
2630
88bdef8b
LC		 2631static void
2632mt7530_mac_port_validate(struct dsa_switch *ds, int port,
2633 unsigned long *supported)
2634{
2635 if (port == 5)
2636 phylink_set(supported, 1000baseX_Full);
2637}
2638
c288575f
LC		 2639static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
2640 unsigned long *supported)
2641{
2642 struct mt7530_priv *priv = ds->priv;
2643
2644 mt7531_sgmii_validate(priv, port, supported);
2645}
2646
88bdef8b
LC		 2647static void
2648mt753x_phylink_validate(struct dsa_switch *ds, int port,
2649 unsigned long *supported,
2650 struct phylink_link_state *state)
ca366d6c
RD		 2651{
2652 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
88bdef8b 2653 struct mt7530_priv *priv = ds->priv;
ca366d6c 2654
88bdef8b
LC		 2655 if (state->interface != PHY_INTERFACE_MODE_NA &&
2656 !mt753x_phy_mode_supported(ds, port, state)) {
ca366d6c
RD		 2657 linkmode_zero(supported);
2658 return;
2659 }
2660
2661 phylink_set_port_modes(mask);
ca366d6c 2662
c288575f
LC		 2663 if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
2664 !phy_interface_mode_is_8023z(state->interface)) {
ca366d6c
RD		 2665 phylink_set(mask, 10baseT_Half);
2666 phylink_set(mask, 10baseT_Full);
2667 phylink_set(mask, 100baseT_Half);
2668 phylink_set(mask, 100baseT_Full);
88bdef8b 2669 phylink_set(mask, Autoneg);
38f790a8 2670 }
ca366d6c 2671
88bdef8b
LC		 2672 /* This switch only supports 1G full-duplex. */
2673 if (state->interface != PHY_INTERFACE_MODE_MII)
2674 phylink_set(mask, 1000baseT_Full);
2675
2676 priv->info->mac_port_validate(ds, port, mask);
2677
ca366d6c
RD		 2678 phylink_set(mask, Pause);
2679 phylink_set(mask, Asym_Pause);
2680
2681 linkmode_and(supported, supported, mask);
2682 linkmode_and(state->advertising, state->advertising, mask);
c288575f
LC		 2683
2684 /* We can only operate at 2500BaseX or 1000BaseX. If requested
2685 * to advertise both, only report advertising at 2500BaseX.
2686 */
2687 phylink_helper_basex_speed(state);
ca366d6c
RD		 2688}
2689
2690static int
2691mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
2692 struct phylink_link_state *state)
2693{
2694 struct mt7530_priv *priv = ds->priv;
2695 u32 pmsr;
2696
2697 if (port < 0 || port >= MT7530_NUM_PORTS)
2698 return -EINVAL;
2699
2700 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2701
2702 state->link = (pmsr & PMSR_LINK);
2703 state->an_complete = state->link;
2704 state->duplex = !!(pmsr & PMSR_DPX);
2705
2706 switch (pmsr & PMSR_SPEED_MASK) {
2707 case PMSR_SPEED_10:
2708 state->speed = SPEED_10;
2709 break;
2710 case PMSR_SPEED_100:
2711 state->speed = SPEED_100;
2712 break;
2713 case PMSR_SPEED_1000:
2714 state->speed = SPEED_1000;
2715 break;
2716 default:
2717 state->speed = SPEED_UNKNOWN;
2718 break;
2719 }
2720
2721 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2722 if (pmsr & PMSR_RX_FC)
2723 state->pause |= MLO_PAUSE_RX;
2724 if (pmsr & PMSR_TX_FC)
2725 state->pause |= MLO_PAUSE_TX;
2726
2727 return 1;
2728}
2729
c288575f
LC		 2730static int
2731mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
2732 struct phylink_link_state *state)
2733{
2734 u32 status, val;
2735 u16 config_reg;
2736
2737 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2738 state->link = !!(status & MT7531_SGMII_LINK_STATUS);
2739 if (state->interface == PHY_INTERFACE_MODE_SGMII &&
2740 (status & MT7531_SGMII_AN_ENABLE)) {
2741 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
2742 config_reg = val >> 16;
2743
2744 switch (config_reg & LPA_SGMII_SPD_MASK) {
2745 case LPA_SGMII_1000:
2746 state->speed = SPEED_1000;
2747 break;
2748 case LPA_SGMII_100:
2749 state->speed = SPEED_100;
2750 break;
2751 case LPA_SGMII_10:
2752 state->speed = SPEED_10;
2753 break;
2754 default:
2755 dev_err(priv->dev, "invalid sgmii PHY speed\n");
2756 state->link = false;
2757 return -EINVAL;
2758 }
2759
2760 if (config_reg & LPA_SGMII_FULL_DUPLEX)
2761 state->duplex = DUPLEX_FULL;
2762 else
2763 state->duplex = DUPLEX_HALF;
2764 }
2765
2766 return 0;
2767}
2768
2769static int
2770mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
2771 struct phylink_link_state *state)
2772{
2773 struct mt7530_priv *priv = ds->priv;
2774
2775 if (state->interface == PHY_INTERFACE_MODE_SGMII)
2776 return mt7531_sgmii_pcs_get_state_an(priv, port, state);
2777
2778 return -EOPNOTSUPP;
2779}
2780
88bdef8b
LC		 2781static int
2782mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
2783 struct phylink_link_state *state)
2784{
2785 struct mt7530_priv *priv = ds->priv;
2786
2787 return priv->info->mac_port_get_state(ds, port, state);
2788}
2789
2790static int
2791mt753x_setup(struct dsa_switch *ds)
2792{
2793 struct mt7530_priv *priv = ds->priv;
2794
2795 return priv->info->sw_setup(ds);
2796}
2797
2798static int
2799mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)
2800{
2801 struct mt7530_priv *priv = ds->priv;
2802
2803 return priv->info->phy_read(ds, port, regnum);
2804}
2805
2806static int
2807mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2808{
2809 struct mt7530_priv *priv = ds->priv;
2810
2811 return priv->info->phy_write(ds, port, regnum, val);
2812}
2813
40b5d2f1
RD		 2814static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,
2815 struct ethtool_eee *e)
2816{
2817 struct mt7530_priv *priv = ds->priv;
2818 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
2819
2820 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
2821 e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
2822
2823 return 0;
2824}
2825
2826static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
2827 struct ethtool_eee *e)
2828{
2829 struct mt7530_priv *priv = ds->priv;
2830 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;
2831
2832 if (e->tx_lpi_timer > 0xFFF)
2833 return -EINVAL;
2834
2835 set = SET_LPI_THRESH(e->tx_lpi_timer);
2836 if (!e->tx_lpi_enabled)
2837 /* Force LPI Mode without a delay */
2838 set |= LPI_MODE_EN;
2839 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
2840
2841 return 0;
2842}
2843
d78d6776 2844static const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8 2845 .get_tag_protocol = mtk_get_tag_protocol,
88bdef8b 2846 .setup = mt753x_setup,
b8f126a8 2847 .get_strings = mt7530_get_strings,
88bdef8b
LC		 2848 .phy_read = mt753x_phy_read,
2849 .phy_write = mt753x_phy_write,
b8f126a8
SW		 2850 .get_ethtool_stats = mt7530_get_ethtool_stats,
2851 .get_sset_count = mt7530_get_sset_count,
ea6d5c92 2852 .set_ageing_time = mt7530_set_ageing_time,
b8f126a8
SW		 2853 .port_enable = mt7530_port_enable,
2854 .port_disable = mt7530_port_disable,
9470174e
DQ		 2855 .port_change_mtu = mt7530_port_change_mtu,
2856 .port_max_mtu = mt7530_port_max_mtu,
b8f126a8 2857 .port_stp_state_set = mt7530_stp_state_set,
5a30833b
DQ		 2858 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags,
2859 .port_bridge_flags = mt7530_port_bridge_flags,
2860 .port_set_mrouter = mt7530_port_set_mrouter,
b8f126a8
SW		 2861 .port_bridge_join = mt7530_port_bridge_join,
2862 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 2863 .port_fdb_add = mt7530_port_fdb_add,
2864 .port_fdb_del = mt7530_port_fdb_del,
2865 .port_fdb_dump = mt7530_port_fdb_dump,
5a30833b
DQ		 2866 .port_mdb_add = mt7530_port_mdb_add,
2867 .port_mdb_del = mt7530_port_mdb_del,
83163f7d 2868 .port_vlan_filtering = mt7530_port_vlan_filtering,
83163f7d
SW		 2869 .port_vlan_add = mt7530_port_vlan_add,
2870 .port_vlan_del = mt7530_port_vlan_del,
c288575f
LC		 2871 .port_mirror_add = mt753x_port_mirror_add,
2872 .port_mirror_del = mt753x_port_mirror_del,
88bdef8b
LC		 2873 .phylink_validate = mt753x_phylink_validate,
2874 .phylink_mac_link_state = mt753x_phylink_mac_link_state,
2875 .phylink_mac_config = mt753x_phylink_mac_config,
c288575f
LC		 2876 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
2877 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
2878 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
40b5d2f1
RD		 2879 .get_mac_eee = mt753x_get_mac_eee,
2880 .set_mac_eee = mt753x_set_mac_eee,
b8f126a8
SW		 2881};
2882
88bdef8b
LC		 2883static const struct mt753x_info mt753x_table[] = {
2884 [ID_MT7621] = {
2885 .id = ID_MT7621,
2886 .sw_setup = mt7530_setup,
2887 .phy_read = mt7530_phy_read,
2888 .phy_write = mt7530_phy_write,
2889 .pad_setup = mt7530_pad_clk_setup,
2890 .phy_mode_supported = mt7530_phy_mode_supported,
2891 .mac_port_validate = mt7530_mac_port_validate,
2892 .mac_port_get_state = mt7530_phylink_mac_link_state,
2893 .mac_port_config = mt7530_mac_config,
2894 },
2895 [ID_MT7530] = {
2896 .id = ID_MT7530,
2897 .sw_setup = mt7530_setup,
2898 .phy_read = mt7530_phy_read,
2899 .phy_write = mt7530_phy_write,
2900 .pad_setup = mt7530_pad_clk_setup,
2901 .phy_mode_supported = mt7530_phy_mode_supported,
2902 .mac_port_validate = mt7530_mac_port_validate,
2903 .mac_port_get_state = mt7530_phylink_mac_link_state,
2904 .mac_port_config = mt7530_mac_config,
2905 },
c288575f
LC		 2906 [ID_MT7531] = {
2907 .id = ID_MT7531,
2908 .sw_setup = mt7531_setup,
2909 .phy_read = mt7531_ind_phy_read,
2910 .phy_write = mt7531_ind_phy_write,
2911 .pad_setup = mt7531_pad_setup,
2912 .cpu_port_config = mt7531_cpu_port_config,
2913 .phy_mode_supported = mt7531_phy_mode_supported,
2914 .mac_port_validate = mt7531_mac_port_validate,
2915 .mac_port_get_state = mt7531_phylink_mac_link_state,
2916 .mac_port_config = mt7531_mac_config,
2917 .mac_pcs_an_restart = mt7531_sgmii_restart_an,
2918 .mac_pcs_link_up = mt7531_sgmii_link_up_force,
2919 },
88bdef8b
LC		 2920};
2921
ddda1ac1 2922static const struct of_device_id mt7530_of_match[] = {
88bdef8b
LC		 2923 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
2924 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
c288575f 2925 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
ddda1ac1
GU		 2926 { /* sentinel */ },
2927};
2928MODULE_DEVICE_TABLE(of, mt7530_of_match);
2929
b8f126a8
SW		 2930static int
2931mt7530_probe(struct mdio_device *mdiodev)
2932{
2933 struct mt7530_priv *priv;
2934 struct device_node *dn;
2935
2936 dn = mdiodev->dev.of_node;
2937
2938 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2939 if (!priv)
2940 return -ENOMEM;
2941
7e99e347 2942 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
b8f126a8
SW		 2943 if (!priv->ds)
2944 return -ENOMEM;
2945
7e99e347
VD		 2946 priv->ds->dev = &mdiodev->dev;
2947 priv->ds->num_ports = DSA_MAX_PORTS;
2948
b8f126a8
SW		 2949 /* Use medatek,mcm property to distinguish hardware type that would
2950 * casues a little bit differences on power-on sequence.
2951 */
2952 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
2953 if (priv->mcm) {
2954 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
2955
2956 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
2957 if (IS_ERR(priv->rstc)) {
2958 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
2959 return PTR_ERR(priv->rstc);
2960 }
2961 }
2962
ddda1ac1
GU		 2963 /* Get the hardware identifier from the devicetree node.
2964 * We will need it for some of the clock and regulator setup.
2965 */
88bdef8b
LC		 2966 priv->info = of_device_get_match_data(&mdiodev->dev);
2967 if (!priv->info)
2968 return -EINVAL;
2969
2970 /* Sanity check if these required device operations are filled
2971 * properly.
2972 */
2973 if (!priv->info->sw_setup || !priv->info->pad_setup ||
2974 !priv->info->phy_read || !priv->info->phy_write ||
2975 !priv->info->phy_mode_supported ||
2976 !priv->info->mac_port_validate ||
2977 !priv->info->mac_port_get_state || !priv->info->mac_port_config)
2978 return -EINVAL;
2979
2980 priv->id = priv->info->id;
b8f126a8 2981
ddda1ac1
GU		 2982 if (priv->id == ID_MT7530) {
2983 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
2984 if (IS_ERR(priv->core_pwr))
2985 return PTR_ERR(priv->core_pwr);
2986
2987 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
2988 if (IS_ERR(priv->io_pwr))
2989 return PTR_ERR(priv->io_pwr);
2990 }
b8f126a8
SW		 2991
2992 /* Not MCM that indicates switch works as the remote standalone
2993 * integrated circuit so the GPIO pin would be used to complete
2994 * the reset, otherwise memory-mapped register accessing used
2995 * through syscon provides in the case of MCM.
2996 */
2997 if (!priv->mcm) {
2998 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
2999 GPIOD_OUT_LOW);
3000 if (IS_ERR(priv->reset)) {
3001 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3002 return PTR_ERR(priv->reset);
3003 }
3004 }
3005
3006 priv->bus = mdiodev->bus;
3007 priv->dev = &mdiodev->dev;
3008 priv->ds->priv = priv;
3009 priv->ds->ops = &mt7530_switch_ops;
3010 mutex_init(&priv->reg_mutex);
3011 dev_set_drvdata(&mdiodev->dev, priv);
3012
23c9ee49 3013 return dsa_register_switch(priv->ds);
b8f126a8
SW		 3014}
3015
3016static void
3017mt7530_remove(struct mdio_device *mdiodev)
3018{
3019 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3020 int ret = 0;
3021
3022 ret = regulator_disable(priv->core_pwr);
3023 if (ret < 0)
3024 dev_err(priv->dev,
3025 "Failed to disable core power: %d\n", ret);
3026
3027 ret = regulator_disable(priv->io_pwr);
3028 if (ret < 0)
3029 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
3030 ret);
3031
3032 dsa_unregister_switch(priv->ds);
3033 mutex_destroy(&priv->reg_mutex);
3034}
3035
b8f126a8
SW		 3036static struct mdio_driver mt7530_mdio_driver = {
3037 .probe = mt7530_probe,
3038 .remove = mt7530_remove,
3039 .mdiodrv.driver = {
3040 .name = "mt7530",
3041 .of_match_table = mt7530_of_match,
3042 },
3043};
3044
3045mdio_module_driver(mt7530_mdio_driver);
3046
3047MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
3048MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
3049MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)