projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx4_core : remove unneeded semicolon
[linux-block.git] / drivers / net / dsa / mt7530.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
b8f126a8
SW		 2/*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
b8f126a8
SW		 5 */
6#include <linux/etherdevice.h>
7#include <linux/if_bridge.h>
8#include <linux/iopoll.h>
9#include <linux/mdio.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
b8f126a8
SW		 13#include <linux/of_mdio.h>
14#include <linux/of_net.h>
15#include <linux/of_platform.h>
ca366d6c 16#include <linux/phylink.h>
b8f126a8
SW		 17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19#include <linux/reset.h>
eb976a55 20#include <linux/gpio/consumer.h>
b8f126a8 21#include <net/dsa.h>
b8f126a8
SW		 22
23#include "mt7530.h"
24
25/* String, offset, and register size in bytes if different from 4 bytes */
26static const struct mt7530_mib_desc mt7530_mib[] = {
27 MIB_DESC(1, 0x00, "TxDrop"),
28 MIB_DESC(1, 0x04, "TxCrcErr"),
29 MIB_DESC(1, 0x08, "TxUnicast"),
30 MIB_DESC(1, 0x0c, "TxMulticast"),
31 MIB_DESC(1, 0x10, "TxBroadcast"),
32 MIB_DESC(1, 0x14, "TxCollision"),
33 MIB_DESC(1, 0x18, "TxSingleCollision"),
34 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
35 MIB_DESC(1, 0x20, "TxDeferred"),
36 MIB_DESC(1, 0x24, "TxLateCollision"),
37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
38 MIB_DESC(1, 0x2c, "TxPause"),
39 MIB_DESC(1, 0x30, "TxPktSz64"),
40 MIB_DESC(1, 0x34, "TxPktSz65To127"),
41 MIB_DESC(1, 0x38, "TxPktSz128To255"),
42 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
43 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
44 MIB_DESC(1, 0x44, "Tx1024ToMax"),
45 MIB_DESC(2, 0x48, "TxBytes"),
46 MIB_DESC(1, 0x60, "RxDrop"),
47 MIB_DESC(1, 0x64, "RxFiltering"),
48 MIB_DESC(1, 0x6c, "RxMulticast"),
49 MIB_DESC(1, 0x70, "RxBroadcast"),
50 MIB_DESC(1, 0x74, "RxAlignErr"),
51 MIB_DESC(1, 0x78, "RxCrcErr"),
52 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
53 MIB_DESC(1, 0x80, "RxFragErr"),
54 MIB_DESC(1, 0x84, "RxOverSzErr"),
55 MIB_DESC(1, 0x88, "RxJabberErr"),
56 MIB_DESC(1, 0x8c, "RxPause"),
57 MIB_DESC(1, 0x90, "RxPktSz64"),
58 MIB_DESC(1, 0x94, "RxPktSz65To127"),
59 MIB_DESC(1, 0x98, "RxPktSz128To255"),
60 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
61 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
62 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
63 MIB_DESC(2, 0xa8, "RxBytes"),
64 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
65 MIB_DESC(1, 0xb4, "RxIngressDrop"),
66 MIB_DESC(1, 0xb8, "RxArlDrop"),
67};
68
b8f126a8
SW		 69static int
70core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
71{
72 struct mii_bus *bus = priv->bus;
73 int value, ret;
74
75 /* Write the desired MMD Devad */
76 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
77 if (ret < 0)
78 goto err;
79
80 /* Write the desired MMD register address */
81 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
82 if (ret < 0)
83 goto err;
84
85 /* Select the Function : DATA with no post increment */
86 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
87 if (ret < 0)
88 goto err;
89
90 /* Read the content of the MMD's selected register */
91 value = bus->read(bus, 0, MII_MMD_DATA);
92
93 return value;
94err:
95 dev_err(&bus->dev, "failed to read mmd register\n");
96
97 return ret;
98}
99
100static int
101core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
102 int devad, u32 data)
103{
104 struct mii_bus *bus = priv->bus;
105 int ret;
106
107 /* Write the desired MMD Devad */
108 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
109 if (ret < 0)
110 goto err;
111
112 /* Write the desired MMD register address */
113 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
114 if (ret < 0)
115 goto err;
116
117 /* Select the Function : DATA with no post increment */
118 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
119 if (ret < 0)
120 goto err;
121
122 /* Write the data into MMD's selected register */
123 ret = bus->write(bus, 0, MII_MMD_DATA, data);
124err:
125 if (ret < 0)
126 dev_err(&bus->dev,
127 "failed to write mmd register\n");
128 return ret;
129}
130
131static void
132core_write(struct mt7530_priv *priv, u32 reg, u32 val)
133{
134 struct mii_bus *bus = priv->bus;
135
136 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
137
138 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
139
140 mutex_unlock(&bus->mdio_lock);
141}
142
143static void
144core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
145{
146 struct mii_bus *bus = priv->bus;
147 u32 val;
148
149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
150
151 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
152 val &= ~mask;
153 val |= set;
154 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
155
156 mutex_unlock(&bus->mdio_lock);
157}
158
159static void
160core_set(struct mt7530_priv *priv, u32 reg, u32 val)
161{
162 core_rmw(priv, reg, 0, val);
163}
164
165static void
166core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
167{
168 core_rmw(priv, reg, val, 0);
169}
170
171static int
172mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
173{
174 struct mii_bus *bus = priv->bus;
175 u16 page, r, lo, hi;
176 int ret;
177
178 page = (reg >> 6) & 0x3ff;
179 r = (reg >> 2) & 0xf;
180 lo = val & 0xffff;
181 hi = val >> 16;
182
183 /* MT7530 uses 31 as the pseudo port */
184 ret = bus->write(bus, 0x1f, 0x1f, page);
185 if (ret < 0)
186 goto err;
187
188 ret = bus->write(bus, 0x1f, r, lo);
189 if (ret < 0)
190 goto err;
191
192 ret = bus->write(bus, 0x1f, 0x10, hi);
193err:
194 if (ret < 0)
195 dev_err(&bus->dev,
196 "failed to write mt7530 register\n");
197 return ret;
198}
199
200static u32
201mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
202{
203 struct mii_bus *bus = priv->bus;
204 u16 page, r, lo, hi;
205 int ret;
206
207 page = (reg >> 6) & 0x3ff;
208 r = (reg >> 2) & 0xf;
209
210 /* MT7530 uses 31 as the pseudo port */
211 ret = bus->write(bus, 0x1f, 0x1f, page);
212 if (ret < 0) {
213 dev_err(&bus->dev,
214 "failed to read mt7530 register\n");
215 return ret;
216 }
217
218 lo = bus->read(bus, 0x1f, r);
219 hi = bus->read(bus, 0x1f, 0x10);
220
221 return (hi << 16) | (lo & 0xffff);
222}
223
224static void
225mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
226{
227 struct mii_bus *bus = priv->bus;
228
229 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
230
231 mt7530_mii_write(priv, reg, val);
232
233 mutex_unlock(&bus->mdio_lock);
234}
235
c288575f
LC		 236static u32
237_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
238{
239 return mt7530_mii_read(p->priv, p->reg);
240}
241
b8f126a8
SW		 242static u32
243_mt7530_read(struct mt7530_dummy_poll *p)
244{
245 struct mii_bus *bus = p->priv->bus;
246 u32 val;
247
248 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
249
250 val = mt7530_mii_read(p->priv, p->reg);
251
252 mutex_unlock(&bus->mdio_lock);
253
254 return val;
255}
256
257static u32
258mt7530_read(struct mt7530_priv *priv, u32 reg)
259{
260 struct mt7530_dummy_poll p;
261
262 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
263 return _mt7530_read(&p);
264}
265
266static void
267mt7530_rmw(struct mt7530_priv *priv, u32 reg,
268 u32 mask, u32 set)
269{
270 struct mii_bus *bus = priv->bus;
271 u32 val;
272
273 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
274
275 val = mt7530_mii_read(priv, reg);
276 val &= ~mask;
277 val |= set;
278 mt7530_mii_write(priv, reg, val);
279
280 mutex_unlock(&bus->mdio_lock);
281}
282
283static void
284mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
285{
286 mt7530_rmw(priv, reg, 0, val);
287}
288
289static void
290mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
291{
292 mt7530_rmw(priv, reg, val, 0);
293}
294
295static int
296mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
297{
298 u32 val;
299 int ret;
300 struct mt7530_dummy_poll p;
301
302 /* Set the command operating upon the MAC address entries */
303 val = ATC_BUSY | ATC_MAT(0) | cmd;
304 mt7530_write(priv, MT7530_ATC, val);
305
306 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
307 ret = readx_poll_timeout(_mt7530_read, &p, val,
308 !(val & ATC_BUSY), 20, 20000);
309 if (ret < 0) {
310 dev_err(priv->dev, "reset timeout\n");
311 return ret;
312 }
313
314 /* Additional sanity for read command if the specified
315 * entry is invalid
316 */
317 val = mt7530_read(priv, MT7530_ATC);
318 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
319 return -EINVAL;
320
321 if (rsp)
322 *rsp = val;
323
324 return 0;
325}
326
327static void
328mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
329{
330 u32 reg[3];
331 int i;
332
333 /* Read from ARL table into an array */
334 for (i = 0; i < 3; i++) {
335 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
336
337 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
338 __func__, __LINE__, i, reg[i]);
339 }
340
341 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
342 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
343 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
344 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
345 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
346 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
347 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
348 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
349 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
350 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
351}
352
353static void
354mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
355 u8 port_mask, const u8 *mac,
356 u8 aging, u8 type)
357{
358 u32 reg[3] = { 0 };
359 int i;
360
361 reg[1] |= vid & CVID_MASK;
362 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
363 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
364 /* STATIC_ENT indicate that entry is static wouldn't
365 * be aged out and STATIC_EMP specified as erasing an
366 * entry
367 */
368 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
369 reg[1] |= mac[5] << MAC_BYTE_5;
370 reg[1] |= mac[4] << MAC_BYTE_4;
371 reg[0] |= mac[3] << MAC_BYTE_3;
372 reg[0] |= mac[2] << MAC_BYTE_2;
373 reg[0] |= mac[1] << MAC_BYTE_1;
374 reg[0] |= mac[0] << MAC_BYTE_0;
375
376 /* Write array into the ARL table */
377 for (i = 0; i < 3; i++)
378 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
379}
380
88bdef8b 381/* Setup TX circuit including relevant PAD and driving */
b8f126a8 382static int
88bdef8b 383mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
b8f126a8
SW		 384{
385 struct mt7530_priv *priv = ds->priv;
7ef6f6f8
RD		 386 u32 ncpo1, ssc_delta, trgint, i, xtal;
387
388 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
389
390 if (xtal == HWTRAP_XTAL_20MHZ) {
391 dev_err(priv->dev,
392 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
393 __func__);
394 return -EINVAL;
395 }
b8f126a8 396
88bdef8b 397 switch (interface) {
b8f126a8
SW		 398 case PHY_INTERFACE_MODE_RGMII:
399 trgint = 0;
7ef6f6f8 400 /* PLL frequency: 125MHz */
b8f126a8 401 ncpo1 = 0x0c80;
b8f126a8
SW		 402 break;
403 case PHY_INTERFACE_MODE_TRGMII:
404 trgint = 1;
7ef6f6f8
RD		 405 if (priv->id == ID_MT7621) {
406 /* PLL frequency: 150MHz: 1.2GBit */
407 if (xtal == HWTRAP_XTAL_40MHZ)
408 ncpo1 = 0x0780;
409 if (xtal == HWTRAP_XTAL_25MHZ)
410 ncpo1 = 0x0a00;
411 } else { /* PLL frequency: 250MHz: 2.0Gbit */
412 if (xtal == HWTRAP_XTAL_40MHZ)
413 ncpo1 = 0x0c80;
414 if (xtal == HWTRAP_XTAL_25MHZ)
415 ncpo1 = 0x1400;
416 }
b8f126a8
SW		 417 break;
418 default:
88bdef8b
LC		 419 dev_err(priv->dev, "xMII interface %d not supported\n",
420 interface);
b8f126a8
SW		 421 return -EINVAL;
422 }
423
7ef6f6f8
RD		 424 if (xtal == HWTRAP_XTAL_25MHZ)
425 ssc_delta = 0x57;
426 else
427 ssc_delta = 0x87;
428
b8f126a8
SW		 429 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
430 P6_INTF_MODE(trgint));
431
432 /* Lower Tx Driving for TRGMII path */
433 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
434 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
435 TD_DM_DRVP(8) | TD_DM_DRVN(8));
436
437 /* Setup core clock for MT7530 */
438 if (!trgint) {
439 /* Disable MT7530 core clock */
440 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
441
442 /* Disable PLL, since phy_device has not yet been created
443 * provided for phy_[read,write]_mmd_indirect is called, we
444 * provide our own core_write_mmd_indirect to complete this
445 * function.
446 */
447 core_write_mmd_indirect(priv,
448 CORE_GSWPLL_GRP1,
449 MDIO_MMD_VEND2,
450 0);
451
452 /* Set core clock into 500Mhz */
453 core_write(priv, CORE_GSWPLL_GRP2,
454 RG_GSWPLL_POSDIV_500M(1) |
455 RG_GSWPLL_FBKDIV_500M(25));
456
457 /* Enable PLL */
458 core_write(priv, CORE_GSWPLL_GRP1,
459 RG_GSWPLL_EN_PRE |
460 RG_GSWPLL_POSDIV_200M(2) |
461 RG_GSWPLL_FBKDIV_200M(32));
462
463 /* Enable MT7530 core clock */
464 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
465 }
466
467 /* Setup the MT7530 TRGMII Tx Clock */
468 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
469 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
470 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
471 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
472 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
473 core_write(priv, CORE_PLL_GROUP4,
474 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
475 RG_SYSPLL_BIAS_LPF_EN);
476 core_write(priv, CORE_PLL_GROUP2,
477 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
478 RG_SYSPLL_POSDIV(1));
479 core_write(priv, CORE_PLL_GROUP7,
480 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
481 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
482 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
483 REG_GSWCK_EN | REG_TRGMIICK_EN);
484
485 if (!trgint)
486 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
487 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
488 RD_TAP_MASK, RD_TAP(16));
b8f126a8
SW		 489 return 0;
490}
491
c288575f
LC		 492static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
493{
494 u32 val;
495
496 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
497
498 return (val & PAD_DUAL_SGMII_EN) != 0;
499}
500
501static int
502mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
503{
504 struct mt7530_priv *priv = ds->priv;
505 u32 top_sig;
506 u32 hwstrap;
507 u32 xtal;
508 u32 val;
509
510 if (mt7531_dual_sgmii_supported(priv))
511 return 0;
512
513 val = mt7530_read(priv, MT7531_CREV);
514 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
515 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
516 if ((val & CHIP_REV_M) > 0)
517 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
518 HWTRAP_XTAL_FSEL_25MHZ;
519 else
520 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
521
522 /* Step 1 : Disable MT7531 COREPLL */
523 val = mt7530_read(priv, MT7531_PLLGP_EN);
524 val &= ~EN_COREPLL;
525 mt7530_write(priv, MT7531_PLLGP_EN, val);
526
527 /* Step 2: switch to XTAL output */
528 val = mt7530_read(priv, MT7531_PLLGP_EN);
529 val |= SW_CLKSW;
530 mt7530_write(priv, MT7531_PLLGP_EN, val);
531
532 val = mt7530_read(priv, MT7531_PLLGP_CR0);
533 val &= ~RG_COREPLL_EN;
534 mt7530_write(priv, MT7531_PLLGP_CR0, val);
535
536 /* Step 3: disable PLLGP and enable program PLLGP */
537 val = mt7530_read(priv, MT7531_PLLGP_EN);
538 val |= SW_PLLGP;
539 mt7530_write(priv, MT7531_PLLGP_EN, val);
540
541 /* Step 4: program COREPLL output frequency to 500MHz */
542 val = mt7530_read(priv, MT7531_PLLGP_CR0);
543 val &= ~RG_COREPLL_POSDIV_M;
544 val |= 2 << RG_COREPLL_POSDIV_S;
545 mt7530_write(priv, MT7531_PLLGP_CR0, val);
546 usleep_range(25, 35);
547
548 switch (xtal) {
549 case HWTRAP_XTAL_FSEL_25MHZ:
550 val = mt7530_read(priv, MT7531_PLLGP_CR0);
551 val &= ~RG_COREPLL_SDM_PCW_M;
552 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
553 mt7530_write(priv, MT7531_PLLGP_CR0, val);
554 break;
555 case HWTRAP_XTAL_FSEL_40MHZ:
556 val = mt7530_read(priv, MT7531_PLLGP_CR0);
557 val &= ~RG_COREPLL_SDM_PCW_M;
558 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
559 mt7530_write(priv, MT7531_PLLGP_CR0, val);
560 break;
561 };
562
563 /* Set feedback divide ratio update signal to high */
564 val = mt7530_read(priv, MT7531_PLLGP_CR0);
565 val |= RG_COREPLL_SDM_PCW_CHG;
566 mt7530_write(priv, MT7531_PLLGP_CR0, val);
567 /* Wait for at least 16 XTAL clocks */
568 usleep_range(10, 20);
569
570 /* Step 5: set feedback divide ratio update signal to low */
571 val = mt7530_read(priv, MT7531_PLLGP_CR0);
572 val &= ~RG_COREPLL_SDM_PCW_CHG;
573 mt7530_write(priv, MT7531_PLLGP_CR0, val);
574
575 /* Enable 325M clock for SGMII */
576 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
577
578 /* Enable 250SSC clock for RGMII */
579 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
580
581 /* Step 6: Enable MT7531 PLL */
582 val = mt7530_read(priv, MT7531_PLLGP_CR0);
583 val |= RG_COREPLL_EN;
584 mt7530_write(priv, MT7531_PLLGP_CR0, val);
585
586 val = mt7530_read(priv, MT7531_PLLGP_EN);
587 val |= EN_COREPLL;
588 mt7530_write(priv, MT7531_PLLGP_EN, val);
589 usleep_range(25, 35);
590
591 return 0;
592}
593
b8f126a8
SW		 594static void
595mt7530_mib_reset(struct dsa_switch *ds)
596{
597 struct mt7530_priv *priv = ds->priv;
598
599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
601}
602
b8f126a8
SW		 603static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
604{
605 struct mt7530_priv *priv = ds->priv;
606
607 return mdiobus_read_nested(priv->bus, port, regnum);
608}
609
360cc342
CIK		 610static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
611 u16 val)
b8f126a8
SW		 612{
613 struct mt7530_priv *priv = ds->priv;
614
615 return mdiobus_write_nested(priv->bus, port, regnum, val);
616}
617
c288575f
LC		 618static int
619mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
620 int regnum)
621{
622 struct mii_bus *bus = priv->bus;
623 struct mt7530_dummy_poll p;
624 u32 reg, val;
625 int ret;
626
627 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
628
629 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
630
631 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
632 !(val & MT7531_PHY_ACS_ST), 20, 100000);
633 if (ret < 0) {
634 dev_err(priv->dev, "poll timeout\n");
635 goto out;
636 }
637
638 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
639 MT7531_MDIO_DEV_ADDR(devad) | regnum;
640 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
641
642 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
643 !(val & MT7531_PHY_ACS_ST), 20, 100000);
644 if (ret < 0) {
645 dev_err(priv->dev, "poll timeout\n");
646 goto out;
647 }
648
649 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
650 MT7531_MDIO_DEV_ADDR(devad);
651 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
652
653 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
654 !(val & MT7531_PHY_ACS_ST), 20, 100000);
655 if (ret < 0) {
656 dev_err(priv->dev, "poll timeout\n");
657 goto out;
658 }
659
660 ret = val & MT7531_MDIO_RW_DATA_MASK;
661out:
662 mutex_unlock(&bus->mdio_lock);
663
664 return ret;
665}
666
667static int
668mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
669 int regnum, u32 data)
670{
671 struct mii_bus *bus = priv->bus;
672 struct mt7530_dummy_poll p;
673 u32 val, reg;
674 int ret;
675
676 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
677
678 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
679
680 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
681 !(val & MT7531_PHY_ACS_ST), 20, 100000);
682 if (ret < 0) {
683 dev_err(priv->dev, "poll timeout\n");
684 goto out;
685 }
686
687 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
688 MT7531_MDIO_DEV_ADDR(devad) | regnum;
689 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
690
691 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
692 !(val & MT7531_PHY_ACS_ST), 20, 100000);
693 if (ret < 0) {
694 dev_err(priv->dev, "poll timeout\n");
695 goto out;
696 }
697
698 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
699 MT7531_MDIO_DEV_ADDR(devad) | data;
700 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
701
702 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
703 !(val & MT7531_PHY_ACS_ST), 20, 100000);
704 if (ret < 0) {
705 dev_err(priv->dev, "poll timeout\n");
706 goto out;
707 }
708
709out:
710 mutex_unlock(&bus->mdio_lock);
711
712 return ret;
713}
714
715static int
716mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
717{
718 struct mii_bus *bus = priv->bus;
719 struct mt7530_dummy_poll p;
720 int ret;
721 u32 val;
722
723 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
724
725 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
726
727 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
728 !(val & MT7531_PHY_ACS_ST), 20, 100000);
729 if (ret < 0) {
730 dev_err(priv->dev, "poll timeout\n");
731 goto out;
732 }
733
734 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
735 MT7531_MDIO_REG_ADDR(regnum);
736
737 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
738
739 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
740 !(val & MT7531_PHY_ACS_ST), 20, 100000);
741 if (ret < 0) {
742 dev_err(priv->dev, "poll timeout\n");
743 goto out;
744 }
745
746 ret = val & MT7531_MDIO_RW_DATA_MASK;
747out:
748 mutex_unlock(&bus->mdio_lock);
749
750 return ret;
751}
752
753static int
754mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
755 u16 data)
756{
757 struct mii_bus *bus = priv->bus;
758 struct mt7530_dummy_poll p;
759 int ret;
760 u32 reg;
761
762 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
763
764 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
765
766 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
767 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
768 if (ret < 0) {
769 dev_err(priv->dev, "poll timeout\n");
770 goto out;
771 }
772
773 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
774 MT7531_MDIO_REG_ADDR(regnum) | data;
775
776 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
777
778 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
779 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
780 if (ret < 0) {
781 dev_err(priv->dev, "poll timeout\n");
782 goto out;
783 }
784
785out:
786 mutex_unlock(&bus->mdio_lock);
787
788 return ret;
789}
790
791static int
792mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
793{
794 struct mt7530_priv *priv = ds->priv;
795 int devad;
796 int ret;
797
798 if (regnum & MII_ADDR_C45) {
799 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
800 ret = mt7531_ind_c45_phy_read(priv, port, devad,
801 regnum & MII_REGADDR_C45_MASK);
802 } else {
803 ret = mt7531_ind_c22_phy_read(priv, port, regnum);
804 }
805
806 return ret;
807}
808
809static int
810mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
811 u16 data)
812{
813 struct mt7530_priv *priv = ds->priv;
814 int devad;
815 int ret;
816
817 if (regnum & MII_ADDR_C45) {
818 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
819 ret = mt7531_ind_c45_phy_write(priv, port, devad,
820 regnum & MII_REGADDR_C45_MASK,
821 data);
822 } else {
823 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
824 }
825
826 return ret;
827}
828
b8f126a8 829static void
89f09048
FF		 830mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
831 uint8_t *data)
b8f126a8
SW		 832{
833 int i;
834
89f09048
FF		 835 if (stringset != ETH_SS_STATS)
836 return;
837
b8f126a8
SW		 838 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
839 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
840 ETH_GSTRING_LEN);
841}
842
843static void
844mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
845 uint64_t *data)
846{
847 struct mt7530_priv *priv = ds->priv;
848 const struct mt7530_mib_desc *mib;
849 u32 reg, i;
850 u64 hi;
851
852 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
853 mib = &mt7530_mib[i];
854 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
855
856 data[i] = mt7530_read(priv, reg);
857 if (mib->size == 2) {
858 hi = mt7530_read(priv, reg + 4);
859 data[i] |= hi << 32;
860 }
861 }
862}
863
864static int
89f09048 865mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
b8f126a8 866{
89f09048
FF		 867 if (sset != ETH_SS_STATS)
868 return 0;
869
b8f126a8
SW		 870 return ARRAY_SIZE(mt7530_mib);
871}
872
38f790a8
RD		 873static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
874{
875 struct mt7530_priv *priv = ds->priv;
876 u8 tx_delay = 0;
877 int val;
878
879 mutex_lock(&priv->reg_mutex);
880
881 val = mt7530_read(priv, MT7530_MHWTRAP);
882
883 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
884 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
885
886 switch (priv->p5_intf_sel) {
887 case P5_INTF_SEL_PHY_P0:
888 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
889 val |= MHWTRAP_PHY0_SEL;
df561f66 890 fallthrough;
38f790a8
RD		 891 case P5_INTF_SEL_PHY_P4:
892 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
893 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
894
895 /* Setup the MAC by default for the cpu port */
896 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
897 break;
898 case P5_INTF_SEL_GMAC5:
899 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
900 val &= ~MHWTRAP_P5_DIS;
901 break;
902 case P5_DISABLED:
903 interface = PHY_INTERFACE_MODE_NA;
904 break;
905 default:
906 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
907 priv->p5_intf_sel);
908 goto unlock_exit;
909 }
910
911 /* Setup RGMII settings */
912 if (phy_interface_mode_is_rgmii(interface)) {
913 val |= MHWTRAP_P5_RGMII_MODE;
914
915 /* P5 RGMII RX Clock Control: delay setting for 1000M */
916 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
917
918 /* Don't set delay in DSA mode */
919 if (!dsa_is_dsa_port(priv->ds, 5) &&
920 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
921 interface == PHY_INTERFACE_MODE_RGMII_ID))
922 tx_delay = 4; /* n * 0.5 ns */
923
924 /* P5 RGMII TX Clock Control: delay x */
925 mt7530_write(priv, MT7530_P5RGMIITXCR,
926 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
927
928 /* reduce P5 RGMII Tx driving, 8mA */
929 mt7530_write(priv, MT7530_IO_DRV_CR,
930 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
931 }
932
933 mt7530_write(priv, MT7530_MHWTRAP, val);
934
935 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
936 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
937
938 priv->p5_interface = interface;
939
940unlock_exit:
941 mutex_unlock(&priv->reg_mutex);
942}
943
b8f126a8 944static int
c288575f 945mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
b8f126a8 946{
c288575f 947 struct mt7530_priv *priv = ds->priv;
0ce0c3cd 948 int ret;
c288575f
LC		 949
950 /* Setup max capability of CPU port at first */
0ce0c3cd
AD		 951 if (priv->info->cpu_port_config) {
952 ret = priv->info->cpu_port_config(ds, port);
953 if (ret)
954 return ret;
955 }
c288575f 956
b8f126a8
SW		 957 /* Enable Mediatek header mode on the cpu port */
958 mt7530_write(priv, MT7530_PVC_P(port),
959 PORT_SPEC_TAG);
960
5e5502e0
DQ		 961 /* Unknown multicast frame forwarding to the cpu port */
962 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
b8f126a8 963
ddda1ac1
GU		 964 /* Set CPU port number */
965 if (priv->id == ID_MT7621)
966 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
967
b8f126a8 968 /* CPU port gets connected to all user ports of
c288575f 969 * the switch.
b8f126a8
SW		 970 */
971 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 972 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8
SW		 973
974 return 0;
975}
976
977static int
978mt7530_port_enable(struct dsa_switch *ds, int port,
979 struct phy_device *phy)
980{
981 struct mt7530_priv *priv = ds->priv;
982
74be4bab
VD		 983 if (!dsa_is_user_port(ds, port))
984 return 0;
985
b8f126a8
SW		 986 mutex_lock(&priv->reg_mutex);
987
b8f126a8
SW		 988 /* Allow the user port gets connected to the cpu port and also
989 * restore the port matrix if the port is the member of a certain
990 * bridge.
991 */
992 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
993 priv->ports[port].enable = true;
994 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
995 priv->ports[port].pm);
1d01145f 996 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 997
998 mutex_unlock(&priv->reg_mutex);
999
1000 return 0;
1001}
1002
1003static void
75104db0 1004mt7530_port_disable(struct dsa_switch *ds, int port)
b8f126a8
SW		 1005{
1006 struct mt7530_priv *priv = ds->priv;
1007
74be4bab
VD		 1008 if (!dsa_is_user_port(ds, port))
1009 return;
1010
b8f126a8
SW		 1011 mutex_lock(&priv->reg_mutex);
1012
1013 /* Clear up all port matrix which could be restored in the next
1014 * enablement for the port.
1015 */
1016 priv->ports[port].enable = false;
1017 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1018 PCR_MATRIX_CLR);
1d01145f 1019 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1020
1021 mutex_unlock(&priv->reg_mutex);
1022}
1023
1024static void
1025mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1026{
1027 struct mt7530_priv *priv = ds->priv;
1028 u32 stp_state;
1029
1030 switch (state) {
1031 case BR_STATE_DISABLED:
1032 stp_state = MT7530_STP_DISABLED;
1033 break;
1034 case BR_STATE_BLOCKING:
1035 stp_state = MT7530_STP_BLOCKING;
1036 break;
1037 case BR_STATE_LISTENING:
1038 stp_state = MT7530_STP_LISTENING;
1039 break;
1040 case BR_STATE_LEARNING:
1041 stp_state = MT7530_STP_LEARNING;
1042 break;
1043 case BR_STATE_FORWARDING:
1044 default:
1045 stp_state = MT7530_STP_FORWARDING;
1046 break;
1047 }
1048
1049 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
1050}
1051
1052static int
1053mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1054 struct net_device *bridge)
1055{
1056 struct mt7530_priv *priv = ds->priv;
1057 u32 port_bitmap = BIT(MT7530_CPU_PORT);
1058 int i;
1059
1060 mutex_lock(&priv->reg_mutex);
1061
1062 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1063 /* Add this port to the port matrix of the other ports in the
1064 * same bridge. If the port is disabled, port matrix is kept
1065 * and not being setup until the port becomes enabled.
1066 */
4a5b85ff 1067 if (dsa_is_user_port(ds, i) && i != port) {
c8652c83 1068 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 1069 continue;
1070 if (priv->ports[i].enable)
1071 mt7530_set(priv, MT7530_PCR_P(i),
1072 PCR_MATRIX(BIT(port)));
1073 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
1074
1075 port_bitmap |= BIT(i);
1076 }
1077 }
1078
1079 /* Add the all other ports to this port matrix. */
1080 if (priv->ports[port].enable)
1081 mt7530_rmw(priv, MT7530_PCR_P(port),
1082 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1083 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1084
1085 mutex_unlock(&priv->reg_mutex);
1086
1087 return 0;
1088}
1089
83163f7d
SW		 1090static void
1091mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1092{
1093 struct mt7530_priv *priv = ds->priv;
1094 bool all_user_ports_removed = true;
1095 int i;
1096
1097 /* When a port is removed from the bridge, the port would be set up
1098 * back to the default as is at initial boot which is a VLAN-unaware
1099 * port.
1100 */
1101 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1102 MT7530_PORT_MATRIX_MODE);
e045124e
DQ		 1103 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1104 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
1105 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d 1106
83163f7d
SW		 1107 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1108 if (dsa_is_user_port(ds, i) &&
68bb8ea8 1109 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
83163f7d
SW		 1110 all_user_ports_removed = false;
1111 break;
1112 }
1113 }
1114
1115 /* CPU port also does the same thing until all user ports belonging to
1116 * the CPU port get out of VLAN filtering mode.
1117 */
1118 if (all_user_ports_removed) {
1119 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
1120 PCR_MATRIX(dsa_user_ports(priv->ds)));
e045124e
DQ		 1121 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
1122 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d
SW		 1123 }
1124}
1125
1126static void
1127mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1128{
1129 struct mt7530_priv *priv = ds->priv;
1130
1131 /* The real fabric path would be decided on the membership in the
1132 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
1133 * means potential VLAN can be consisting of certain subset of all
1134 * ports.
1135 */
1136 mt7530_rmw(priv, MT7530_PCR_P(port),
1137 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
1138
1139 /* Trapped into security mode allows packet forwarding through VLAN
38152ea3
DQ		 1140 * table lookup. CPU port is set to fallback mode to let untagged
1141 * frames pass through.
83163f7d 1142 */
38152ea3
DQ		 1143 if (dsa_is_cpu_port(ds, port))
1144 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1145 MT7530_PORT_FALLBACK_MODE);
1146 else
1147 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1148 MT7530_PORT_SECURITY_MODE);
83163f7d
SW		 1149
1150 /* Set the port as a user port which is to be able to recognize VID
1151 * from incoming packets before fetching entry within the VLAN table.
1152 */
e045124e
DQ		 1153 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1154 VLAN_ATTR(MT7530_VLAN_USER) |
1155 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
83163f7d
SW		 1156}
1157
b8f126a8
SW		 1158static void
1159mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1160 struct net_device *bridge)
1161{
1162 struct mt7530_priv *priv = ds->priv;
1163 int i;
1164
1165 mutex_lock(&priv->reg_mutex);
1166
1167 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1168 /* Remove this port from the port matrix of the other ports
1169 * in the same bridge. If the port is disabled, port matrix
1170 * is kept and not being setup until the port becomes enabled.
83163f7d
SW		 1171 * And the other port's port matrix cannot be broken when the
1172 * other port is still a VLAN-aware port.
b8f126a8 1173 */
2a130551 1174 if (dsa_is_user_port(ds, i) && i != port &&
68bb8ea8 1175 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
c8652c83 1176 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 1177 continue;
1178 if (priv->ports[i].enable)
1179 mt7530_clear(priv, MT7530_PCR_P(i),
1180 PCR_MATRIX(BIT(port)));
1181 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
1182 }
1183 }
1184
1185 /* Set the cpu port to be the only one in the port matrix of
1186 * this port.
1187 */
1188 if (priv->ports[port].enable)
1189 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1190 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
1191 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
1192
1193 mutex_unlock(&priv->reg_mutex);
1194}
1195
1196static int
b8f126a8 1197mt7530_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 1198 const unsigned char *addr, u16 vid)
b8f126a8
SW		 1199{
1200 struct mt7530_priv *priv = ds->priv;
1b6dd556 1201 int ret;
b8f126a8
SW		 1202 u8 port_mask = BIT(port);
1203
1204 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1205 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 1206 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 1207 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 1208
1209 return ret;
b8f126a8
SW		 1210}
1211
1212static int
1213mt7530_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1214 const unsigned char *addr, u16 vid)
b8f126a8
SW		 1215{
1216 struct mt7530_priv *priv = ds->priv;
1217 int ret;
1218 u8 port_mask = BIT(port);
1219
1220 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1221 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 1222 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 1223 mutex_unlock(&priv->reg_mutex);
1224
1225 return ret;
1226}
1227
1228static int
1229mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1230 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 1231{
1232 struct mt7530_priv *priv = ds->priv;
1233 struct mt7530_fdb _fdb = { 0 };
1234 int cnt = MT7530_NUM_FDB_RECORDS;
1235 int ret = 0;
1236 u32 rsp = 0;
1237
1238 mutex_lock(&priv->reg_mutex);
1239
1240 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1241 if (ret < 0)
1242 goto err;
1243
1244 do {
1245 if (rsp & ATC_SRCH_HIT) {
1246 mt7530_fdb_read(priv, &_fdb);
1247 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 1248 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1249 data);
b8f126a8
SW		 1250 if (ret < 0)
1251 break;
1252 }
1253 }
1254 } while (--cnt &&
1255 !(rsp & ATC_SRCH_END) &&
1256 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1257err:
1258 mutex_unlock(&priv->reg_mutex);
1259
1260 return 0;
1261}
1262
83163f7d
SW		 1263static int
1264mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1265{
1266 struct mt7530_dummy_poll p;
1267 u32 val;
1268 int ret;
1269
1270 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1271 mt7530_write(priv, MT7530_VTCR, val);
1272
1273 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1274 ret = readx_poll_timeout(_mt7530_read, &p, val,
1275 !(val & VTCR_BUSY), 20, 20000);
1276 if (ret < 0) {
1277 dev_err(priv->dev, "poll timeout\n");
1278 return ret;
1279 }
1280
1281 val = mt7530_read(priv, MT7530_VTCR);
1282 if (val & VTCR_INVALID) {
1283 dev_err(priv->dev, "read VTCR invalid\n");
1284 return -EINVAL;
1285 }
1286
1287 return 0;
1288}
1289
1290static int
1291mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
2e554a7a
VO		 1292 bool vlan_filtering,
1293 struct switchdev_trans *trans)
83163f7d 1294{
2e554a7a
VO		 1295 if (switchdev_trans_ph_prepare(trans))
1296 return 0;
1297
83163f7d
SW		 1298 if (vlan_filtering) {
1299 /* The port is being kept as VLAN-unaware port when bridge is
1300 * set up with vlan_filtering not being set, Otherwise, the
1301 * port and the corresponding CPU port is required the setup
1302 * for becoming a VLAN-aware port.
1303 */
1304 mt7530_port_set_vlan_aware(ds, port);
1305 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
e3ee07d1
VO		 1306 } else {
1307 mt7530_port_set_vlan_unaware(ds, port);
83163f7d
SW		 1308 }
1309
1310 return 0;
1311}
1312
1313static int
1314mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
1315 const struct switchdev_obj_port_vlan *vlan)
1316{
1317 /* nothing needed */
1318
1319 return 0;
1320}
1321
1322static void
1323mt7530_hw_vlan_add(struct mt7530_priv *priv,
1324 struct mt7530_hw_vlan_entry *entry)
1325{
1326 u8 new_members;
1327 u32 val;
1328
1329 new_members = entry->old_members | BIT(entry->port) |
1330 BIT(MT7530_CPU_PORT);
1331
1332 /* Validate the entry with independent learning, create egress tag per
1333 * VLAN and joining the port as one of the port members.
1334 */
1335 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1336 mt7530_write(priv, MT7530_VAWD1, val);
1337
1338 /* Decide whether adding tag or not for those outgoing packets from the
1339 * port inside the VLAN.
1340 */
1341 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1342 MT7530_VLAN_EGRESS_TAG;
1343 mt7530_rmw(priv, MT7530_VAWD2,
1344 ETAG_CTRL_P_MASK(entry->port),
1345 ETAG_CTRL_P(entry->port, val));
1346
1347 /* CPU port is always taken as a tagged port for serving more than one
1348 * VLANs across and also being applied with egress type stack mode for
1349 * that VLAN tags would be appended after hardware special tag used as
1350 * DSA tag.
1351 */
1352 mt7530_rmw(priv, MT7530_VAWD2,
1353 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1354 ETAG_CTRL_P(MT7530_CPU_PORT,
1355 MT7530_VLAN_EGRESS_STACK));
1356}
1357
1358static void
1359mt7530_hw_vlan_del(struct mt7530_priv *priv,
1360 struct mt7530_hw_vlan_entry *entry)
1361{
1362 u8 new_members;
1363 u32 val;
1364
1365 new_members = entry->old_members & ~BIT(entry->port);
1366
1367 val = mt7530_read(priv, MT7530_VAWD1);
1368 if (!(val & VLAN_VALID)) {
1369 dev_err(priv->dev,
1370 "Cannot be deleted due to invalid entry\n");
1371 return;
1372 }
1373
1374 /* If certain member apart from CPU port is still alive in the VLAN,
1375 * the entry would be kept valid. Otherwise, the entry is got to be
1376 * disabled.
1377 */
1378 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1379 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1380 VLAN_VALID;
1381 mt7530_write(priv, MT7530_VAWD1, val);
1382 } else {
1383 mt7530_write(priv, MT7530_VAWD1, 0);
1384 mt7530_write(priv, MT7530_VAWD2, 0);
1385 }
1386}
1387
1388static void
1389mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1390 struct mt7530_hw_vlan_entry *entry,
1391 mt7530_vlan_op vlan_op)
1392{
1393 u32 val;
1394
1395 /* Fetch entry */
1396 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1397
1398 val = mt7530_read(priv, MT7530_VAWD1);
1399
1400 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1401
1402 /* Manipulate entry */
1403 vlan_op(priv, entry);
1404
1405 /* Flush result to hardware */
1406 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1407}
1408
1409static void
1410mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1411 const struct switchdev_obj_port_vlan *vlan)
1412{
1413 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1414 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1415 struct mt7530_hw_vlan_entry new_entry;
1416 struct mt7530_priv *priv = ds->priv;
1417 u16 vid;
1418
83163f7d
SW		 1419 mutex_lock(&priv->reg_mutex);
1420
1421 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1422 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1423 mt7530_hw_vlan_update(priv, vid, &new_entry,
1424 mt7530_hw_vlan_add);
1425 }
1426
1427 if (pvid) {
1428 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1429 G0_PORT_VID(vlan->vid_end));
1430 priv->ports[port].pvid = vlan->vid_end;
1431 }
1432
1433 mutex_unlock(&priv->reg_mutex);
1434}
1435
1436static int
1437mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1438 const struct switchdev_obj_port_vlan *vlan)
1439{
1440 struct mt7530_hw_vlan_entry target_entry;
1441 struct mt7530_priv *priv = ds->priv;
1442 u16 vid, pvid;
1443
83163f7d
SW		 1444 mutex_lock(&priv->reg_mutex);
1445
1446 pvid = priv->ports[port].pvid;
1447 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1448 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1449 mt7530_hw_vlan_update(priv, vid, &target_entry,
1450 mt7530_hw_vlan_del);
1451
1452 /* PVID is being restored to the default whenever the PVID port
1453 * is being removed from the VLAN.
1454 */
1455 if (pvid == vid)
1456 pvid = G0_PORT_VID_DEF;
1457 }
1458
1459 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1460 priv->ports[port].pvid = pvid;
1461
1462 mutex_unlock(&priv->reg_mutex);
1463
1464 return 0;
1465}
1466
c288575f
LC		 1467static int mt753x_mirror_port_get(unsigned int id, u32 val)
1468{
1469 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1470 MIRROR_PORT(val);
1471}
1472
1473static int mt753x_mirror_port_set(unsigned int id, u32 val)
1474{
1475 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1476 MIRROR_PORT(val);
1477}
1478
1479static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
37feab60
DQ		 1480 struct dsa_mall_mirror_tc_entry *mirror,
1481 bool ingress)
1482{
1483 struct mt7530_priv *priv = ds->priv;
c288575f 1484 int monitor_port;
37feab60
DQ		 1485 u32 val;
1486
1487 /* Check for existent entry */
1488 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1489 return -EEXIST;
1490
c288575f 1491 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
37feab60
DQ		 1492
1493 /* MT7530 only supports one monitor port */
c288575f
LC		 1494 monitor_port = mt753x_mirror_port_get(priv->id, val);
1495 if (val & MT753X_MIRROR_EN(priv->id) &&
1496 monitor_port != mirror->to_local_port)
37feab60
DQ		 1497 return -EEXIST;
1498
c288575f
LC		 1499 val |= MT753X_MIRROR_EN(priv->id);
1500 val &= ~MT753X_MIRROR_MASK(priv->id);
1501 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1502 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1503
1504 val = mt7530_read(priv, MT7530_PCR_P(port));
1505 if (ingress) {
1506 val |= PORT_RX_MIR;
1507 priv->mirror_rx |= BIT(port);
1508 } else {
1509 val |= PORT_TX_MIR;
1510 priv->mirror_tx |= BIT(port);
1511 }
1512 mt7530_write(priv, MT7530_PCR_P(port), val);
1513
1514 return 0;
1515}
1516
c288575f 1517static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
37feab60
DQ		 1518 struct dsa_mall_mirror_tc_entry *mirror)
1519{
1520 struct mt7530_priv *priv = ds->priv;
1521 u32 val;
1522
1523 val = mt7530_read(priv, MT7530_PCR_P(port));
1524 if (mirror->ingress) {
1525 val &= ~PORT_RX_MIR;
1526 priv->mirror_rx &= ~BIT(port);
1527 } else {
1528 val &= ~PORT_TX_MIR;
1529 priv->mirror_tx &= ~BIT(port);
1530 }
1531 mt7530_write(priv, MT7530_PCR_P(port), val);
1532
1533 if (!priv->mirror_rx && !priv->mirror_tx) {
c288575f
LC		 1534 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1535 val &= ~MT753X_MIRROR_EN(priv->id);
1536 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1537 }
1538}
1539
b8f126a8 1540static enum dsa_tag_protocol
4d776482
FF		 1541mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1542 enum dsa_tag_protocol mp)
b8f126a8
SW		 1543{
1544 struct mt7530_priv *priv = ds->priv;
1545
5ed4e3eb 1546 if (port != MT7530_CPU_PORT) {
b8f126a8
SW		 1547 dev_warn(priv->dev,
1548 "port not matched with tagging CPU port\n");
1549 return DSA_TAG_PROTO_NONE;
1550 } else {
1551 return DSA_TAG_PROTO_MTK;
1552 }
1553}
1554
1555static int
1556mt7530_setup(struct dsa_switch *ds)
1557{
1558 struct mt7530_priv *priv = ds->priv;
38f790a8
RD		 1559 struct device_node *phy_node;
1560 struct device_node *mac_np;
b8f126a8 1561 struct mt7530_dummy_poll p;
38f790a8 1562 phy_interface_t interface;
ca366d6c
RD		 1563 struct device_node *dn;
1564 u32 id, val;
1565 int ret, i;
b8f126a8 1566
0abfd494 1567 /* The parent node of master netdev which holds the common system
b8f126a8
SW		 1568 * controller also is the container for two GMACs nodes representing
1569 * as two netdev instances.
1570 */
68bb8ea8 1571 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
0141792f 1572 ds->configure_vlan_while_not_filtering = true;
b8f126a8 1573
ddda1ac1 1574 if (priv->id == ID_MT7530) {
ddda1ac1
GU		 1575 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1576 ret = regulator_enable(priv->core_pwr);
1577 if (ret < 0) {
1578 dev_err(priv->dev,
1579 "Failed to enable core power: %d\n", ret);
1580 return ret;
1581 }
b8f126a8 1582
ddda1ac1
GU		 1583 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1584 ret = regulator_enable(priv->io_pwr);
1585 if (ret < 0) {
1586 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1587 ret);
1588 return ret;
1589 }
b8f126a8
SW		 1590 }
1591
1592 /* Reset whole chip through gpio pin or memory-mapped registers for
1593 * different type of hardware
1594 */
1595 if (priv->mcm) {
1596 reset_control_assert(priv->rstc);
1597 usleep_range(1000, 1100);
1598 reset_control_deassert(priv->rstc);
1599 } else {
1600 gpiod_set_value_cansleep(priv->reset, 0);
1601 usleep_range(1000, 1100);
1602 gpiod_set_value_cansleep(priv->reset, 1);
1603 }
1604
1605 /* Waiting for MT7530 got to stable */
1606 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1607 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1608 20, 1000000);
1609 if (ret < 0) {
1610 dev_err(priv->dev, "reset timeout\n");
1611 return ret;
1612 }
1613
1614 id = mt7530_read(priv, MT7530_CREV);
1615 id >>= CHIP_NAME_SHIFT;
1616 if (id != MT7530_ID) {
1617 dev_err(priv->dev, "chip %x can't be supported\n", id);
1618 return -ENODEV;
1619 }
1620
1621 /* Reset the switch through internal reset */
1622 mt7530_write(priv, MT7530_SYS_CTRL,
1623 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1624 SYS_CTRL_REG_RST);
1625
1626 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1627 val = mt7530_read(priv, MT7530_MHWTRAP);
1628 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1629 val |= MHWTRAP_MANUAL;
1630 mt7530_write(priv, MT7530_MHWTRAP, val);
1631
ca366d6c
RD		 1632 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1633
b8f126a8
SW		 1634 /* Enable and reset MIB counters */
1635 mt7530_mib_reset(ds);
1636
b8f126a8
SW		 1637 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1638 /* Disable forwarding by default on all ports */
1639 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1640 PCR_MATRIX_CLR);
1641
0ce0c3cd
AD		 1642 if (dsa_is_cpu_port(ds, i)) {
1643 ret = mt753x_cpu_port_enable(ds, i);
1644 if (ret)
1645 return ret;
1646 } else
75104db0 1647 mt7530_port_disable(ds, i);
e045124e
DQ		 1648
1649 /* Enable consistent egress tag */
1650 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1651 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
b8f126a8
SW		 1652 }
1653
38f790a8
RD		 1654 /* Setup port 5 */
1655 priv->p5_intf_sel = P5_DISABLED;
1656 interface = PHY_INTERFACE_MODE_NA;
1657
1658 if (!dsa_is_unused_port(ds, 5)) {
1659 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
0c65b2b9
AL		 1660 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
1661 if (ret && ret != -ENODEV)
1662 return ret;
38f790a8
RD		 1663 } else {
1664 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1665 for_each_child_of_node(dn, mac_np) {
1666 if (!of_device_is_compatible(mac_np,
1667 "mediatek,eth-mac"))
1668 continue;
1669
1670 ret = of_property_read_u32(mac_np, "reg", &id);
1671 if (ret < 0 || id != 1)
1672 continue;
1673
1674 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
0452800f
CG		 1675 if (!phy_node)
1676 continue;
1677
38f790a8 1678 if (phy_node->parent == priv->dev->of_node->parent) {
0c65b2b9 1679 ret = of_get_phy_mode(mac_np, &interface);
8e4efd47
SP		 1680 if (ret && ret != -ENODEV) {
1681 of_node_put(mac_np);
0c65b2b9 1682 return ret;
8e4efd47 1683 }
38f790a8
RD		 1684 id = of_mdio_parse_addr(ds->dev, phy_node);
1685 if (id == 0)
1686 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1687 if (id == 4)
1688 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1689 }
8e4efd47 1690 of_node_put(mac_np);
38f790a8
RD		 1691 of_node_put(phy_node);
1692 break;
1693 }
1694 }
1695
1696 mt7530_setup_port5(ds, interface);
1697
b8f126a8 1698 /* Flush the FDB table */
18bd5949 1699 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 1700 if (ret < 0)
1701 return ret;
1702
1703 return 0;
1704}
1705
c288575f
LC		 1706static int
1707mt7531_setup(struct dsa_switch *ds)
1708{
1709 struct mt7530_priv *priv = ds->priv;
1710 struct mt7530_dummy_poll p;
1711 u32 val, id;
1712 int ret, i;
1713
1714 /* Reset whole chip through gpio pin or memory-mapped registers for
1715 * different type of hardware
1716 */
1717 if (priv->mcm) {
1718 reset_control_assert(priv->rstc);
1719 usleep_range(1000, 1100);
1720 reset_control_deassert(priv->rstc);
1721 } else {
1722 gpiod_set_value_cansleep(priv->reset, 0);
1723 usleep_range(1000, 1100);
1724 gpiod_set_value_cansleep(priv->reset, 1);
1725 }
1726
1727 /* Waiting for MT7530 got to stable */
1728 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1729 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1730 20, 1000000);
1731 if (ret < 0) {
1732 dev_err(priv->dev, "reset timeout\n");
1733 return ret;
1734 }
1735
1736 id = mt7530_read(priv, MT7531_CREV);
1737 id >>= CHIP_NAME_SHIFT;
1738
1739 if (id != MT7531_ID) {
1740 dev_err(priv->dev, "chip %x can't be supported\n", id);
1741 return -ENODEV;
1742 }
1743
1744 /* Reset the switch through internal reset */
1745 mt7530_write(priv, MT7530_SYS_CTRL,
1746 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1747 SYS_CTRL_REG_RST);
1748
1749 if (mt7531_dual_sgmii_supported(priv)) {
1750 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
1751
1752 /* Let ds->slave_mii_bus be able to access external phy. */
1753 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
1754 MT7531_EXT_P_MDC_11);
1755 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
1756 MT7531_EXT_P_MDIO_12);
1757 } else {
1758 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1759 }
1760 dev_dbg(ds->dev, "P5 support %s interface\n",
1761 p5_intf_modes(priv->p5_intf_sel));
1762
1763 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
1764 MT7531_GPIO0_INTERRUPT);
1765
1766 /* Let phylink decide the interface later. */
1767 priv->p5_interface = PHY_INTERFACE_MODE_NA;
1768 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1769
1770 /* Enable PHY core PLL, since phy_device has not yet been created
1771 * provided for phy_[read,write]_mmd_indirect is called, we provide
1772 * our own mt7531_ind_mmd_phy_[read,write] to complete this
1773 * function.
1774 */
1775 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
1776 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
1777 val |= MT7531_PHY_PLL_BYPASS_MODE;
1778 val &= ~MT7531_PHY_PLL_OFF;
1779 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
1780 CORE_PLL_GROUP4, val);
1781
1782 /* BPDU to CPU port */
1783 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
1784 BIT(MT7530_CPU_PORT));
1785 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
1786 MT753X_BPDU_CPU_ONLY);
1787
1788 /* Enable and reset MIB counters */
1789 mt7530_mib_reset(ds);
1790
1791 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1792 /* Disable forwarding by default on all ports */
1793 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1794 PCR_MATRIX_CLR);
1795
1796 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
1797
0ce0c3cd
AD		 1798 if (dsa_is_cpu_port(ds, i)) {
1799 ret = mt753x_cpu_port_enable(ds, i);
1800 if (ret)
1801 return ret;
1802 } else
c288575f
LC		 1803 mt7530_port_disable(ds, i);
1804
1805 /* Enable consistent egress tag */
1806 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1807 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1808 }
1809
1810 ds->configure_vlan_while_not_filtering = true;
1811
1812 /* Flush the FDB table */
1813 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1814 if (ret < 0)
1815 return ret;
1816
1817 return 0;
1818}
1819
88bdef8b
LC		 1820static bool
1821mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
1822 const struct phylink_link_state *state)
ca366d6c
RD		 1823{
1824 struct mt7530_priv *priv = ds->priv;
ca366d6c
RD		 1825
1826 switch (port) {
88bdef8b 1827 case 0 ... 4: /* Internal phy */
ca366d6c 1828 if (state->interface != PHY_INTERFACE_MODE_GMII)
88bdef8b 1829 return false;
ca366d6c 1830 break;
38f790a8 1831 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
38f790a8
RD		 1832 if (!phy_interface_mode_is_rgmii(state->interface) &&
1833 state->interface != PHY_INTERFACE_MODE_MII &&
1834 state->interface != PHY_INTERFACE_MODE_GMII)
88bdef8b
LC		 1835 return false;
1836 break;
1837 case 6: /* 1st cpu port */
1838 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1839 state->interface != PHY_INTERFACE_MODE_TRGMII)
1840 return false;
1841 break;
1842 default:
1843 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
1844 port);
1845 return false;
1846 }
1847
1848 return true;
1849}
1850
c288575f
LC		 1851static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
1852{
1853 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
1854}
1855
1856static bool
1857mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
1858 const struct phylink_link_state *state)
1859{
1860 struct mt7530_priv *priv = ds->priv;
1861
1862 switch (port) {
1863 case 0 ... 4: /* Internal phy */
1864 if (state->interface != PHY_INTERFACE_MODE_GMII)
1865 return false;
1866 break;
1867 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
1868 if (mt7531_is_rgmii_port(priv, port))
1869 return phy_interface_mode_is_rgmii(state->interface);
1870 fallthrough;
1871 case 6: /* 1st cpu port supports sgmii/8023z only */
1872 if (state->interface != PHY_INTERFACE_MODE_SGMII &&
1873 !phy_interface_mode_is_8023z(state->interface))
1874 return false;
1875 break;
1876 default:
1877 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
1878 port);
1879 return false;
1880 }
1881
1882 return true;
1883}
1884
88bdef8b
LC		 1885static bool
1886mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
1887 const struct phylink_link_state *state)
1888{
1889 struct mt7530_priv *priv = ds->priv;
1890
1891 return priv->info->phy_mode_supported(ds, port, state);
1892}
1893
1894static int
1895mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
1896{
1897 struct mt7530_priv *priv = ds->priv;
1898
1899 return priv->info->pad_setup(ds, state->interface);
1900}
1901
1902static int
1903mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1904 phy_interface_t interface)
1905{
1906 struct mt7530_priv *priv = ds->priv;
1907
1908 /* Only need to setup port5. */
1909 if (port != 5)
1910 return 0;
1911
1912 mt7530_setup_port5(priv->ds, interface);
1913
1914 return 0;
1915}
1916
c288575f
LC		 1917static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
1918 phy_interface_t interface,
1919 struct phy_device *phydev)
1920{
1921 u32 val;
1922
1923 if (!mt7531_is_rgmii_port(priv, port)) {
1924 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
1925 port);
1926 return -EINVAL;
1927 }
1928
1929 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
1930 val |= GP_CLK_EN;
1931 val &= ~GP_MODE_MASK;
1932 val |= GP_MODE(MT7531_GP_MODE_RGMII);
1933 val &= ~CLK_SKEW_IN_MASK;
1934 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
1935 val &= ~CLK_SKEW_OUT_MASK;
1936 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
1937 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
1938
1939 /* Do not adjust rgmii delay when vendor phy driver presents. */
1940 if (!phydev || phy_driver_is_genphy(phydev)) {
1941 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
1942 switch (interface) {
1943 case PHY_INTERFACE_MODE_RGMII:
1944 val |= TXCLK_NO_REVERSE;
1945 val |= RXCLK_NO_DELAY;
1946 break;
1947 case PHY_INTERFACE_MODE_RGMII_RXID:
1948 val |= TXCLK_NO_REVERSE;
1949 break;
1950 case PHY_INTERFACE_MODE_RGMII_TXID:
1951 val |= RXCLK_NO_DELAY;
1952 break;
1953 case PHY_INTERFACE_MODE_RGMII_ID:
1954 break;
1955 default:
1956 return -EINVAL;
1957 }
1958 }
1959 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
1960
1961 return 0;
1962}
1963
1964static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
1965 unsigned long *supported)
1966{
1967 /* Port5 supports ethier RGMII or SGMII.
1968 * Port6 supports SGMII only.
1969 */
1970 switch (port) {
1971 case 5:
1972 if (mt7531_is_rgmii_port(priv, port))
1973 break;
1974 fallthrough;
1975 case 6:
1976 phylink_set(supported, 1000baseX_Full);
1977 phylink_set(supported, 2500baseX_Full);
1978 phylink_set(supported, 2500baseT_Full);
1979 }
1980}
1981
1982static void
1983mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
1984 unsigned int mode, phy_interface_t interface,
1985 int speed, int duplex)
1986{
1987 struct mt7530_priv *priv = ds->priv;
1988 unsigned int val;
1989
1990 /* For adjusting speed and duplex of SGMII force mode. */
1991 if (interface != PHY_INTERFACE_MODE_SGMII ||
1992 phylink_autoneg_inband(mode))
1993 return;
1994
1995 /* SGMII force mode setting */
1996 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
1997 val &= ~MT7531_SGMII_IF_MODE_MASK;
1998
1999 switch (speed) {
2000 case SPEED_10:
2001 val |= MT7531_SGMII_FORCE_SPEED_10;
2002 break;
2003 case SPEED_100:
2004 val |= MT7531_SGMII_FORCE_SPEED_100;
2005 break;
2006 case SPEED_1000:
2007 val |= MT7531_SGMII_FORCE_SPEED_1000;
2008 break;
2009 }
2010
2011 /* MT7531 SGMII 1G force mode can only work in full duplex mode,
2012 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2013 */
2014 if ((speed == SPEED_10 || speed == SPEED_100) &&
2015 duplex != DUPLEX_FULL)
2016 val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2017
2018 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2019}
2020
2021static bool mt753x_is_mac_port(u32 port)
2022{
2023 return (port == 5 || port == 6);
2024}
2025
2026static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2027 phy_interface_t interface)
2028{
2029 u32 val;
2030
2031 if (!mt753x_is_mac_port(port))
2032 return -EINVAL;
2033
2034 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2035 MT7531_SGMII_PHYA_PWD);
2036
2037 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2038 val &= ~MT7531_RG_TPHY_SPEED_MASK;
2039 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2040 * encoding.
2041 */
2042 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2043 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2044 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2045
2046 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2047
2048 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2049 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2050 */
2051 mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2052 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2053 MT7531_SGMII_FORCE_SPEED_1000);
2054
2055 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2056
2057 return 0;
2058}
2059
2060static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2061 phy_interface_t interface)
2062{
2063 if (!mt753x_is_mac_port(port))
2064 return -EINVAL;
2065
2066 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2067 MT7531_SGMII_PHYA_PWD);
2068
2069 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2070 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2071
2072 mt7530_set(priv, MT7531_SGMII_MODE(port),
2073 MT7531_SGMII_REMOTE_FAULT_DIS |
2074 MT7531_SGMII_SPEED_DUPLEX_AN);
2075
2076 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2077 MT7531_SGMII_TX_CONFIG_MASK, 1);
2078
2079 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2080
2081 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2082
2083 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2084
2085 return 0;
2086}
2087
2088static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
2089{
2090 struct mt7530_priv *priv = ds->priv;
2091 u32 val;
2092
2093 /* Only restart AN when AN is enabled */
2094 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2095 if (val & MT7531_SGMII_AN_ENABLE) {
2096 val |= MT7531_SGMII_AN_RESTART;
2097 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2098 }
2099}
2100
2101static int
2102mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2103 phy_interface_t interface)
2104{
2105 struct mt7530_priv *priv = ds->priv;
2106 struct phy_device *phydev;
2107 struct dsa_port *dp;
2108
2109 if (!mt753x_is_mac_port(port)) {
2110 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2111 return -EINVAL;
2112 }
2113
2114 switch (interface) {
2115 case PHY_INTERFACE_MODE_RGMII:
2116 case PHY_INTERFACE_MODE_RGMII_ID:
2117 case PHY_INTERFACE_MODE_RGMII_RXID:
2118 case PHY_INTERFACE_MODE_RGMII_TXID:
2119 dp = dsa_to_port(ds, port);
2120 phydev = dp->slave->phydev;
2121 return mt7531_rgmii_setup(priv, port, interface, phydev);
2122 case PHY_INTERFACE_MODE_SGMII:
2123 return mt7531_sgmii_setup_mode_an(priv, port, interface);
2124 case PHY_INTERFACE_MODE_NA:
2125 case PHY_INTERFACE_MODE_1000BASEX:
2126 case PHY_INTERFACE_MODE_2500BASEX:
2127 if (phylink_autoneg_inband(mode))
2128 return -EINVAL;
2129
2130 return mt7531_sgmii_setup_mode_force(priv, port, interface);
2131 default:
2132 return -EINVAL;
2133 }
2134
2135 return -EINVAL;
2136}
2137
88bdef8b
LC		 2138static int
2139mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2140 const struct phylink_link_state *state)
2141{
2142 struct mt7530_priv *priv = ds->priv;
2143
2144 return priv->info->mac_port_config(ds, port, mode, state->interface);
2145}
2146
2147static void
2148mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2149 const struct phylink_link_state *state)
2150{
2151 struct mt7530_priv *priv = ds->priv;
2152 u32 mcr_cur, mcr_new;
2153
2154 if (!mt753x_phy_mode_supported(ds, port, state))
2155 goto unsupported;
2156
2157 switch (port) {
2158 case 0 ... 4: /* Internal phy */
2159 if (state->interface != PHY_INTERFACE_MODE_GMII)
2160 goto unsupported;
2161 break;
2162 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2163 if (priv->p5_interface == state->interface)
2164 break;
2165
2166 if (mt753x_mac_config(ds, port, mode, state) < 0)
2167 goto unsupported;
38f790a8 2168
c288575f
LC		 2169 if (priv->p5_intf_sel != P5_DISABLED)
2170 priv->p5_interface = state->interface;
38f790a8 2171 break;
ca366d6c
RD		 2172 case 6: /* 1st cpu port */
2173 if (priv->p6_interface == state->interface)
2174 break;
2175
88bdef8b 2176 mt753x_pad_setup(ds, state);
ca366d6c 2177
88bdef8b
LC		 2178 if (mt753x_mac_config(ds, port, mode, state) < 0)
2179 goto unsupported;
ca366d6c 2180
ca366d6c
RD		 2181 priv->p6_interface = state->interface;
2182 break;
2183 default:
88bdef8b
LC		 2184unsupported:
2185 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2186 __func__, phy_modes(state->interface), port);
ca366d6c
RD		 2187 return;
2188 }
2189
c288575f
LC		 2190 if (phylink_autoneg_inband(mode) &&
2191 state->interface != PHY_INTERFACE_MODE_SGMII) {
ca366d6c
RD		 2192 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
2193 __func__);
2194 return;
2195 }
2196
2197 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2198 mcr_new = mcr_cur;
1d01145f 2199 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
ca366d6c 2200 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
c288575f 2201 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
ca366d6c 2202
38f790a8
RD		 2203 /* Are we connected to external phy */
2204 if (port == 5 && dsa_is_user_port(ds, 5))
2205 mcr_new |= PMCR_EXT_PHY;
2206
ca366d6c
RD		 2207 if (mcr_new != mcr_cur)
2208 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2209}
2210
c288575f
LC		 2211static void
2212mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
2213{
2214 struct mt7530_priv *priv = ds->priv;
2215
2216 if (!priv->info->mac_pcs_an_restart)
2217 return;
2218
2219 priv->info->mac_pcs_an_restart(ds, port);
2220}
2221
2222static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
ca366d6c
RD		 2223 unsigned int mode,
2224 phy_interface_t interface)
2225{
2226 struct mt7530_priv *priv = ds->priv;
2227
1d01145f 2228 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
ca366d6c
RD		 2229}
2230
c288575f
LC		 2231static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
2232 unsigned int mode, phy_interface_t interface,
2233 int speed, int duplex)
2234{
2235 struct mt7530_priv *priv = ds->priv;
2236
2237 if (!priv->info->mac_pcs_link_up)
2238 return;
2239
2240 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2241}
2242
2243static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
ca366d6c
RD		 2244 unsigned int mode,
2245 phy_interface_t interface,
5b502a7b
RK		 2246 struct phy_device *phydev,
2247 int speed, int duplex,
2248 bool tx_pause, bool rx_pause)
ca366d6c
RD		 2249{
2250 struct mt7530_priv *priv = ds->priv;
1d01145f
RD		 2251 u32 mcr;
2252
c288575f
LC		 2253 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2254
1d01145f
RD		 2255 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2256
c288575f
LC		 2257 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2258 * variants.
2259 */
2260 if (interface == PHY_INTERFACE_MODE_TRGMII ||
2261 (phy_interface_mode_is_8023z(interface))) {
2262 speed = SPEED_1000;
2263 duplex = DUPLEX_FULL;
2264 }
2265
1d01145f
RD		 2266 switch (speed) {
2267 case SPEED_1000:
2268 mcr |= PMCR_FORCE_SPEED_1000;
2269 break;
2270 case SPEED_100:
2271 mcr |= PMCR_FORCE_SPEED_100;
2272 break;
2273 }
2274 if (duplex == DUPLEX_FULL) {
2275 mcr |= PMCR_FORCE_FDX;
2276 if (tx_pause)
2277 mcr |= PMCR_TX_FC_EN;
2278 if (rx_pause)
2279 mcr |= PMCR_RX_FC_EN;
2280 }
ca366d6c 2281
1d01145f 2282 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
ca366d6c
RD		 2283}
2284
c288575f
LC		 2285static int
2286mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2287{
2288 struct mt7530_priv *priv = ds->priv;
2289 phy_interface_t interface;
2290 int speed;
0ce0c3cd 2291 int ret;
c288575f
LC		 2292
2293 switch (port) {
2294 case 5:
2295 if (mt7531_is_rgmii_port(priv, port))
2296 interface = PHY_INTERFACE_MODE_RGMII;
2297 else
2298 interface = PHY_INTERFACE_MODE_2500BASEX;
2299
2300 priv->p5_interface = interface;
2301 break;
2302 case 6:
2303 interface = PHY_INTERFACE_MODE_2500BASEX;
2304
2305 mt7531_pad_setup(ds, interface);
2306
2307 priv->p6_interface = interface;
2308 break;
0ce0c3cd
AD		 2309 default:
2310 return -EINVAL;
c288575f
LC		 2311 }
2312
2313 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2314 speed = SPEED_2500;
2315 else
2316 speed = SPEED_1000;
2317
0ce0c3cd
AD		 2318 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2319 if (ret)
2320 return ret;
c288575f
LC		 2321 mt7530_write(priv, MT7530_PMCR_P(port),
2322 PMCR_CPU_PORT_SETTING(priv->id));
2323 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2324 speed, DUPLEX_FULL, true, true);
2325
2326 return 0;
2327}
2328
88bdef8b
LC		 2329static void
2330mt7530_mac_port_validate(struct dsa_switch *ds, int port,
2331 unsigned long *supported)
2332{
2333 if (port == 5)
2334 phylink_set(supported, 1000baseX_Full);
2335}
2336
c288575f
LC		 2337static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
2338 unsigned long *supported)
2339{
2340 struct mt7530_priv *priv = ds->priv;
2341
2342 mt7531_sgmii_validate(priv, port, supported);
2343}
2344
88bdef8b
LC		 2345static void
2346mt753x_phylink_validate(struct dsa_switch *ds, int port,
2347 unsigned long *supported,
2348 struct phylink_link_state *state)
ca366d6c
RD		 2349{
2350 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
88bdef8b 2351 struct mt7530_priv *priv = ds->priv;
ca366d6c 2352
88bdef8b
LC		 2353 if (state->interface != PHY_INTERFACE_MODE_NA &&
2354 !mt753x_phy_mode_supported(ds, port, state)) {
ca366d6c
RD		 2355 linkmode_zero(supported);
2356 return;
2357 }
2358
2359 phylink_set_port_modes(mask);
ca366d6c 2360
c288575f
LC		 2361 if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
2362 !phy_interface_mode_is_8023z(state->interface)) {
ca366d6c
RD		 2363 phylink_set(mask, 10baseT_Half);
2364 phylink_set(mask, 10baseT_Full);
2365 phylink_set(mask, 100baseT_Half);
2366 phylink_set(mask, 100baseT_Full);
88bdef8b 2367 phylink_set(mask, Autoneg);
38f790a8 2368 }
ca366d6c 2369
88bdef8b
LC		 2370 /* This switch only supports 1G full-duplex. */
2371 if (state->interface != PHY_INTERFACE_MODE_MII)
2372 phylink_set(mask, 1000baseT_Full);
2373
2374 priv->info->mac_port_validate(ds, port, mask);
2375
ca366d6c
RD		 2376 phylink_set(mask, Pause);
2377 phylink_set(mask, Asym_Pause);
2378
2379 linkmode_and(supported, supported, mask);
2380 linkmode_and(state->advertising, state->advertising, mask);
c288575f
LC		 2381
2382 /* We can only operate at 2500BaseX or 1000BaseX. If requested
2383 * to advertise both, only report advertising at 2500BaseX.
2384 */
2385 phylink_helper_basex_speed(state);
ca366d6c
RD		 2386}
2387
2388static int
2389mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
2390 struct phylink_link_state *state)
2391{
2392 struct mt7530_priv *priv = ds->priv;
2393 u32 pmsr;
2394
2395 if (port < 0 || port >= MT7530_NUM_PORTS)
2396 return -EINVAL;
2397
2398 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2399
2400 state->link = (pmsr & PMSR_LINK);
2401 state->an_complete = state->link;
2402 state->duplex = !!(pmsr & PMSR_DPX);
2403
2404 switch (pmsr & PMSR_SPEED_MASK) {
2405 case PMSR_SPEED_10:
2406 state->speed = SPEED_10;
2407 break;
2408 case PMSR_SPEED_100:
2409 state->speed = SPEED_100;
2410 break;
2411 case PMSR_SPEED_1000:
2412 state->speed = SPEED_1000;
2413 break;
2414 default:
2415 state->speed = SPEED_UNKNOWN;
2416 break;
2417 }
2418
2419 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2420 if (pmsr & PMSR_RX_FC)
2421 state->pause |= MLO_PAUSE_RX;
2422 if (pmsr & PMSR_TX_FC)
2423 state->pause |= MLO_PAUSE_TX;
2424
2425 return 1;
2426}
2427
c288575f
LC		 2428static int
2429mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
2430 struct phylink_link_state *state)
2431{
2432 u32 status, val;
2433 u16 config_reg;
2434
2435 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2436 state->link = !!(status & MT7531_SGMII_LINK_STATUS);
2437 if (state->interface == PHY_INTERFACE_MODE_SGMII &&
2438 (status & MT7531_SGMII_AN_ENABLE)) {
2439 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
2440 config_reg = val >> 16;
2441
2442 switch (config_reg & LPA_SGMII_SPD_MASK) {
2443 case LPA_SGMII_1000:
2444 state->speed = SPEED_1000;
2445 break;
2446 case LPA_SGMII_100:
2447 state->speed = SPEED_100;
2448 break;
2449 case LPA_SGMII_10:
2450 state->speed = SPEED_10;
2451 break;
2452 default:
2453 dev_err(priv->dev, "invalid sgmii PHY speed\n");
2454 state->link = false;
2455 return -EINVAL;
2456 }
2457
2458 if (config_reg & LPA_SGMII_FULL_DUPLEX)
2459 state->duplex = DUPLEX_FULL;
2460 else
2461 state->duplex = DUPLEX_HALF;
2462 }
2463
2464 return 0;
2465}
2466
2467static int
2468mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
2469 struct phylink_link_state *state)
2470{
2471 struct mt7530_priv *priv = ds->priv;
2472
2473 if (state->interface == PHY_INTERFACE_MODE_SGMII)
2474 return mt7531_sgmii_pcs_get_state_an(priv, port, state);
2475
2476 return -EOPNOTSUPP;
2477}
2478
88bdef8b
LC		 2479static int
2480mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
2481 struct phylink_link_state *state)
2482{
2483 struct mt7530_priv *priv = ds->priv;
2484
2485 return priv->info->mac_port_get_state(ds, port, state);
2486}
2487
2488static int
2489mt753x_setup(struct dsa_switch *ds)
2490{
2491 struct mt7530_priv *priv = ds->priv;
2492
2493 return priv->info->sw_setup(ds);
2494}
2495
2496static int
2497mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)
2498{
2499 struct mt7530_priv *priv = ds->priv;
2500
2501 return priv->info->phy_read(ds, port, regnum);
2502}
2503
2504static int
2505mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2506{
2507 struct mt7530_priv *priv = ds->priv;
2508
2509 return priv->info->phy_write(ds, port, regnum, val);
2510}
2511
d78d6776 2512static const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8 2513 .get_tag_protocol = mtk_get_tag_protocol,
88bdef8b 2514 .setup = mt753x_setup,
b8f126a8 2515 .get_strings = mt7530_get_strings,
88bdef8b
LC		 2516 .phy_read = mt753x_phy_read,
2517 .phy_write = mt753x_phy_write,
b8f126a8
SW		 2518 .get_ethtool_stats = mt7530_get_ethtool_stats,
2519 .get_sset_count = mt7530_get_sset_count,
b8f126a8
SW		 2520 .port_enable = mt7530_port_enable,
2521 .port_disable = mt7530_port_disable,
2522 .port_stp_state_set = mt7530_stp_state_set,
2523 .port_bridge_join = mt7530_port_bridge_join,
2524 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 2525 .port_fdb_add = mt7530_port_fdb_add,
2526 .port_fdb_del = mt7530_port_fdb_del,
2527 .port_fdb_dump = mt7530_port_fdb_dump,
83163f7d
SW		 2528 .port_vlan_filtering = mt7530_port_vlan_filtering,
2529 .port_vlan_prepare = mt7530_port_vlan_prepare,
2530 .port_vlan_add = mt7530_port_vlan_add,
2531 .port_vlan_del = mt7530_port_vlan_del,
c288575f
LC		 2532 .port_mirror_add = mt753x_port_mirror_add,
2533 .port_mirror_del = mt753x_port_mirror_del,
88bdef8b
LC		 2534 .phylink_validate = mt753x_phylink_validate,
2535 .phylink_mac_link_state = mt753x_phylink_mac_link_state,
2536 .phylink_mac_config = mt753x_phylink_mac_config,
c288575f
LC		 2537 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
2538 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
2539 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
b8f126a8
SW		 2540};
2541
88bdef8b
LC		 2542static const struct mt753x_info mt753x_table[] = {
2543 [ID_MT7621] = {
2544 .id = ID_MT7621,
2545 .sw_setup = mt7530_setup,
2546 .phy_read = mt7530_phy_read,
2547 .phy_write = mt7530_phy_write,
2548 .pad_setup = mt7530_pad_clk_setup,
2549 .phy_mode_supported = mt7530_phy_mode_supported,
2550 .mac_port_validate = mt7530_mac_port_validate,
2551 .mac_port_get_state = mt7530_phylink_mac_link_state,
2552 .mac_port_config = mt7530_mac_config,
2553 },
2554 [ID_MT7530] = {
2555 .id = ID_MT7530,
2556 .sw_setup = mt7530_setup,
2557 .phy_read = mt7530_phy_read,
2558 .phy_write = mt7530_phy_write,
2559 .pad_setup = mt7530_pad_clk_setup,
2560 .phy_mode_supported = mt7530_phy_mode_supported,
2561 .mac_port_validate = mt7530_mac_port_validate,
2562 .mac_port_get_state = mt7530_phylink_mac_link_state,
2563 .mac_port_config = mt7530_mac_config,
2564 },
c288575f
LC		 2565 [ID_MT7531] = {
2566 .id = ID_MT7531,
2567 .sw_setup = mt7531_setup,
2568 .phy_read = mt7531_ind_phy_read,
2569 .phy_write = mt7531_ind_phy_write,
2570 .pad_setup = mt7531_pad_setup,
2571 .cpu_port_config = mt7531_cpu_port_config,
2572 .phy_mode_supported = mt7531_phy_mode_supported,
2573 .mac_port_validate = mt7531_mac_port_validate,
2574 .mac_port_get_state = mt7531_phylink_mac_link_state,
2575 .mac_port_config = mt7531_mac_config,
2576 .mac_pcs_an_restart = mt7531_sgmii_restart_an,
2577 .mac_pcs_link_up = mt7531_sgmii_link_up_force,
2578 },
88bdef8b
LC		 2579};
2580
ddda1ac1 2581static const struct of_device_id mt7530_of_match[] = {
88bdef8b
LC		 2582 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
2583 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
c288575f 2584 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
ddda1ac1
GU		 2585 { /* sentinel */ },
2586};
2587MODULE_DEVICE_TABLE(of, mt7530_of_match);
2588
b8f126a8
SW		 2589static int
2590mt7530_probe(struct mdio_device *mdiodev)
2591{
2592 struct mt7530_priv *priv;
2593 struct device_node *dn;
2594
2595 dn = mdiodev->dev.of_node;
2596
2597 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2598 if (!priv)
2599 return -ENOMEM;
2600
7e99e347 2601 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
b8f126a8
SW		 2602 if (!priv->ds)
2603 return -ENOMEM;
2604
7e99e347
VD		 2605 priv->ds->dev = &mdiodev->dev;
2606 priv->ds->num_ports = DSA_MAX_PORTS;
2607
b8f126a8
SW		 2608 /* Use medatek,mcm property to distinguish hardware type that would
2609 * casues a little bit differences on power-on sequence.
2610 */
2611 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
2612 if (priv->mcm) {
2613 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
2614
2615 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
2616 if (IS_ERR(priv->rstc)) {
2617 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
2618 return PTR_ERR(priv->rstc);
2619 }
2620 }
2621
ddda1ac1
GU		 2622 /* Get the hardware identifier from the devicetree node.
2623 * We will need it for some of the clock and regulator setup.
2624 */
88bdef8b
LC		 2625 priv->info = of_device_get_match_data(&mdiodev->dev);
2626 if (!priv->info)
2627 return -EINVAL;
2628
2629 /* Sanity check if these required device operations are filled
2630 * properly.
2631 */
2632 if (!priv->info->sw_setup || !priv->info->pad_setup ||
2633 !priv->info->phy_read || !priv->info->phy_write ||
2634 !priv->info->phy_mode_supported ||
2635 !priv->info->mac_port_validate ||
2636 !priv->info->mac_port_get_state || !priv->info->mac_port_config)
2637 return -EINVAL;
2638
2639 priv->id = priv->info->id;
b8f126a8 2640
ddda1ac1
GU		 2641 if (priv->id == ID_MT7530) {
2642 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
2643 if (IS_ERR(priv->core_pwr))
2644 return PTR_ERR(priv->core_pwr);
2645
2646 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
2647 if (IS_ERR(priv->io_pwr))
2648 return PTR_ERR(priv->io_pwr);
2649 }
b8f126a8
SW		 2650
2651 /* Not MCM that indicates switch works as the remote standalone
2652 * integrated circuit so the GPIO pin would be used to complete
2653 * the reset, otherwise memory-mapped register accessing used
2654 * through syscon provides in the case of MCM.
2655 */
2656 if (!priv->mcm) {
2657 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
2658 GPIOD_OUT_LOW);
2659 if (IS_ERR(priv->reset)) {
2660 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
2661 return PTR_ERR(priv->reset);
2662 }
2663 }
2664
2665 priv->bus = mdiodev->bus;
2666 priv->dev = &mdiodev->dev;
2667 priv->ds->priv = priv;
2668 priv->ds->ops = &mt7530_switch_ops;
2669 mutex_init(&priv->reg_mutex);
2670 dev_set_drvdata(&mdiodev->dev, priv);
2671
23c9ee49 2672 return dsa_register_switch(priv->ds);
b8f126a8
SW		 2673}
2674
2675static void
2676mt7530_remove(struct mdio_device *mdiodev)
2677{
2678 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
2679 int ret = 0;
2680
2681 ret = regulator_disable(priv->core_pwr);
2682 if (ret < 0)
2683 dev_err(priv->dev,
2684 "Failed to disable core power: %d\n", ret);
2685
2686 ret = regulator_disable(priv->io_pwr);
2687 if (ret < 0)
2688 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
2689 ret);
2690
2691 dsa_unregister_switch(priv->ds);
2692 mutex_destroy(&priv->reg_mutex);
2693}
2694
b8f126a8
SW		 2695static struct mdio_driver mt7530_mdio_driver = {
2696 .probe = mt7530_probe,
2697 .remove = mt7530_remove,
2698 .mdiodrv.driver = {
2699 .name = "mt7530",
2700 .of_match_table = mt7530_of_match,
2701 },
2702};
2703
2704mdio_module_driver(mt7530_mdio_driver);
2705
2706MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
2707MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
2708MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)