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Merge branch 'octeon-drr-config'
[linux-block.git] / drivers / net / dsa / mt7530.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
b8f126a8
SW		 2/*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
b8f126a8
SW		 5 */
6#include <linux/etherdevice.h>
7#include <linux/if_bridge.h>
8#include <linux/iopoll.h>
9#include <linux/mdio.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
ba751e28 13#include <linux/of_irq.h>
b8f126a8
SW		 14#include <linux/of_mdio.h>
15#include <linux/of_net.h>
16#include <linux/of_platform.h>
ca366d6c 17#include <linux/phylink.h>
b8f126a8
SW		 18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
eb976a55 21#include <linux/gpio/consumer.h>
429a0ede 22#include <linux/gpio/driver.h>
b8f126a8 23#include <net/dsa.h>
b8f126a8
SW		 24
25#include "mt7530.h"
26
27/* String, offset, and register size in bytes if different from 4 bytes */
28static const struct mt7530_mib_desc mt7530_mib[] = {
29 MIB_DESC(1, 0x00, "TxDrop"),
30 MIB_DESC(1, 0x04, "TxCrcErr"),
31 MIB_DESC(1, 0x08, "TxUnicast"),
32 MIB_DESC(1, 0x0c, "TxMulticast"),
33 MIB_DESC(1, 0x10, "TxBroadcast"),
34 MIB_DESC(1, 0x14, "TxCollision"),
35 MIB_DESC(1, 0x18, "TxSingleCollision"),
36 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
37 MIB_DESC(1, 0x20, "TxDeferred"),
38 MIB_DESC(1, 0x24, "TxLateCollision"),
39 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
40 MIB_DESC(1, 0x2c, "TxPause"),
41 MIB_DESC(1, 0x30, "TxPktSz64"),
42 MIB_DESC(1, 0x34, "TxPktSz65To127"),
43 MIB_DESC(1, 0x38, "TxPktSz128To255"),
44 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
45 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
46 MIB_DESC(1, 0x44, "Tx1024ToMax"),
47 MIB_DESC(2, 0x48, "TxBytes"),
48 MIB_DESC(1, 0x60, "RxDrop"),
49 MIB_DESC(1, 0x64, "RxFiltering"),
50 MIB_DESC(1, 0x6c, "RxMulticast"),
51 MIB_DESC(1, 0x70, "RxBroadcast"),
52 MIB_DESC(1, 0x74, "RxAlignErr"),
53 MIB_DESC(1, 0x78, "RxCrcErr"),
54 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
55 MIB_DESC(1, 0x80, "RxFragErr"),
56 MIB_DESC(1, 0x84, "RxOverSzErr"),
57 MIB_DESC(1, 0x88, "RxJabberErr"),
58 MIB_DESC(1, 0x8c, "RxPause"),
59 MIB_DESC(1, 0x90, "RxPktSz64"),
60 MIB_DESC(1, 0x94, "RxPktSz65To127"),
61 MIB_DESC(1, 0x98, "RxPktSz128To255"),
62 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
63 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
64 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
65 MIB_DESC(2, 0xa8, "RxBytes"),
66 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
67 MIB_DESC(1, 0xb4, "RxIngressDrop"),
68 MIB_DESC(1, 0xb8, "RxArlDrop"),
69};
70
4732315c
IL		 71/* Since phy_device has not yet been created and
72 * phy_{read,write}_mmd_indirect is not available, we provide our own
73 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
74 * to complete this function.
75 */
b8f126a8
SW		 76static int
77core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
78{
79 struct mii_bus *bus = priv->bus;
80 int value, ret;
81
82 /* Write the desired MMD Devad */
83 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
84 if (ret < 0)
85 goto err;
86
87 /* Write the desired MMD register address */
88 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
89 if (ret < 0)
90 goto err;
91
92 /* Select the Function : DATA with no post increment */
93 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
94 if (ret < 0)
95 goto err;
96
97 /* Read the content of the MMD's selected register */
98 value = bus->read(bus, 0, MII_MMD_DATA);
99
100 return value;
101err:
102 dev_err(&bus->dev, "failed to read mmd register\n");
103
104 return ret;
105}
106
107static int
108core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
109 int devad, u32 data)
110{
111 struct mii_bus *bus = priv->bus;
112 int ret;
113
114 /* Write the desired MMD Devad */
115 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
116 if (ret < 0)
117 goto err;
118
119 /* Write the desired MMD register address */
120 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
121 if (ret < 0)
122 goto err;
123
124 /* Select the Function : DATA with no post increment */
125 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
126 if (ret < 0)
127 goto err;
128
129 /* Write the data into MMD's selected register */
130 ret = bus->write(bus, 0, MII_MMD_DATA, data);
131err:
132 if (ret < 0)
133 dev_err(&bus->dev,
134 "failed to write mmd register\n");
135 return ret;
136}
137
138static void
139core_write(struct mt7530_priv *priv, u32 reg, u32 val)
140{
141 struct mii_bus *bus = priv->bus;
142
143 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
144
145 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
146
147 mutex_unlock(&bus->mdio_lock);
148}
149
150static void
151core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
152{
153 struct mii_bus *bus = priv->bus;
154 u32 val;
155
156 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
157
158 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
159 val &= ~mask;
160 val |= set;
161 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
162
163 mutex_unlock(&bus->mdio_lock);
164}
165
166static void
167core_set(struct mt7530_priv *priv, u32 reg, u32 val)
168{
169 core_rmw(priv, reg, 0, val);
170}
171
172static void
173core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
174{
175 core_rmw(priv, reg, val, 0);
176}
177
178static int
179mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
180{
181 struct mii_bus *bus = priv->bus;
182 u16 page, r, lo, hi;
183 int ret;
184
185 page = (reg >> 6) & 0x3ff;
186 r = (reg >> 2) & 0xf;
187 lo = val & 0xffff;
188 hi = val >> 16;
189
190 /* MT7530 uses 31 as the pseudo port */
191 ret = bus->write(bus, 0x1f, 0x1f, page);
192 if (ret < 0)
193 goto err;
194
195 ret = bus->write(bus, 0x1f, r, lo);
196 if (ret < 0)
197 goto err;
198
199 ret = bus->write(bus, 0x1f, 0x10, hi);
200err:
201 if (ret < 0)
202 dev_err(&bus->dev,
203 "failed to write mt7530 register\n");
204 return ret;
205}
206
207static u32
208mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
209{
210 struct mii_bus *bus = priv->bus;
211 u16 page, r, lo, hi;
212 int ret;
213
214 page = (reg >> 6) & 0x3ff;
215 r = (reg >> 2) & 0xf;
216
217 /* MT7530 uses 31 as the pseudo port */
218 ret = bus->write(bus, 0x1f, 0x1f, page);
219 if (ret < 0) {
220 dev_err(&bus->dev,
221 "failed to read mt7530 register\n");
222 return ret;
223 }
224
225 lo = bus->read(bus, 0x1f, r);
226 hi = bus->read(bus, 0x1f, 0x10);
227
228 return (hi << 16) | (lo & 0xffff);
229}
230
231static void
232mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
233{
234 struct mii_bus *bus = priv->bus;
235
236 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
237
238 mt7530_mii_write(priv, reg, val);
239
240 mutex_unlock(&bus->mdio_lock);
241}
242
c288575f
LC		 243static u32
244_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
245{
246 return mt7530_mii_read(p->priv, p->reg);
247}
248
b8f126a8
SW		 249static u32
250_mt7530_read(struct mt7530_dummy_poll *p)
251{
252 struct mii_bus *bus = p->priv->bus;
253 u32 val;
254
255 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
256
257 val = mt7530_mii_read(p->priv, p->reg);
258
259 mutex_unlock(&bus->mdio_lock);
260
261 return val;
262}
263
264static u32
265mt7530_read(struct mt7530_priv *priv, u32 reg)
266{
267 struct mt7530_dummy_poll p;
268
269 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
270 return _mt7530_read(&p);
271}
272
273static void
274mt7530_rmw(struct mt7530_priv *priv, u32 reg,
275 u32 mask, u32 set)
276{
277 struct mii_bus *bus = priv->bus;
278 u32 val;
279
280 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
281
282 val = mt7530_mii_read(priv, reg);
283 val &= ~mask;
284 val |= set;
285 mt7530_mii_write(priv, reg, val);
286
287 mutex_unlock(&bus->mdio_lock);
288}
289
290static void
291mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
292{
293 mt7530_rmw(priv, reg, 0, val);
294}
295
296static void
297mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
298{
299 mt7530_rmw(priv, reg, val, 0);
300}
301
302static int
303mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
304{
305 u32 val;
306 int ret;
307 struct mt7530_dummy_poll p;
308
309 /* Set the command operating upon the MAC address entries */
310 val = ATC_BUSY | ATC_MAT(0) | cmd;
311 mt7530_write(priv, MT7530_ATC, val);
312
313 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
314 ret = readx_poll_timeout(_mt7530_read, &p, val,
315 !(val & ATC_BUSY), 20, 20000);
316 if (ret < 0) {
317 dev_err(priv->dev, "reset timeout\n");
318 return ret;
319 }
320
321 /* Additional sanity for read command if the specified
322 * entry is invalid
323 */
324 val = mt7530_read(priv, MT7530_ATC);
325 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
326 return -EINVAL;
327
328 if (rsp)
329 *rsp = val;
330
331 return 0;
332}
333
334static void
335mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
336{
337 u32 reg[3];
338 int i;
339
340 /* Read from ARL table into an array */
341 for (i = 0; i < 3; i++) {
342 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
343
344 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
345 __func__, __LINE__, i, reg[i]);
346 }
347
348 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
349 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
350 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
351 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
352 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
353 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
354 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
355 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
356 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
357 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
358}
359
360static void
361mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
362 u8 port_mask, const u8 *mac,
363 u8 aging, u8 type)
364{
365 u32 reg[3] = { 0 };
366 int i;
367
368 reg[1] |= vid & CVID_MASK;
7e777021
EW		 369 if (vid > 1)
370 reg[1] |= ATA2_IVL;
b8f126a8
SW		 371 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
372 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
373 /* STATIC_ENT indicate that entry is static wouldn't
374 * be aged out and STATIC_EMP specified as erasing an
375 * entry
376 */
377 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
378 reg[1] |= mac[5] << MAC_BYTE_5;
379 reg[1] |= mac[4] << MAC_BYTE_4;
380 reg[0] |= mac[3] << MAC_BYTE_3;
381 reg[0] |= mac[2] << MAC_BYTE_2;
382 reg[0] |= mac[1] << MAC_BYTE_1;
383 reg[0] |= mac[0] << MAC_BYTE_0;
384
385 /* Write array into the ARL table */
386 for (i = 0; i < 3; i++)
387 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
388}
389
88bdef8b 390/* Setup TX circuit including relevant PAD and driving */
b8f126a8 391static int
88bdef8b 392mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
b8f126a8
SW		 393{
394 struct mt7530_priv *priv = ds->priv;
7ef6f6f8
RD		 395 u32 ncpo1, ssc_delta, trgint, i, xtal;
396
397 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
398
399 if (xtal == HWTRAP_XTAL_20MHZ) {
400 dev_err(priv->dev,
401 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
402 __func__);
403 return -EINVAL;
404 }
b8f126a8 405
88bdef8b 406 switch (interface) {
b8f126a8
SW		 407 case PHY_INTERFACE_MODE_RGMII:
408 trgint = 0;
7ef6f6f8 409 /* PLL frequency: 125MHz */
b8f126a8 410 ncpo1 = 0x0c80;
b8f126a8
SW		 411 break;
412 case PHY_INTERFACE_MODE_TRGMII:
413 trgint = 1;
7ef6f6f8
RD		 414 if (priv->id == ID_MT7621) {
415 /* PLL frequency: 150MHz: 1.2GBit */
416 if (xtal == HWTRAP_XTAL_40MHZ)
417 ncpo1 = 0x0780;
418 if (xtal == HWTRAP_XTAL_25MHZ)
419 ncpo1 = 0x0a00;
420 } else { /* PLL frequency: 250MHz: 2.0Gbit */
421 if (xtal == HWTRAP_XTAL_40MHZ)
422 ncpo1 = 0x0c80;
423 if (xtal == HWTRAP_XTAL_25MHZ)
424 ncpo1 = 0x1400;
425 }
b8f126a8
SW		 426 break;
427 default:
88bdef8b
LC		 428 dev_err(priv->dev, "xMII interface %d not supported\n",
429 interface);
b8f126a8
SW		 430 return -EINVAL;
431 }
432
7ef6f6f8
RD		 433 if (xtal == HWTRAP_XTAL_25MHZ)
434 ssc_delta = 0x57;
435 else
436 ssc_delta = 0x87;
437
b8f126a8
SW		 438 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
439 P6_INTF_MODE(trgint));
440
441 /* Lower Tx Driving for TRGMII path */
442 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
443 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
444 TD_DM_DRVP(8) | TD_DM_DRVN(8));
445
4732315c
IL		 446 /* Disable MT7530 core and TRGMII Tx clocks */
447 core_clear(priv, CORE_TRGMII_GSW_CLK_CG,
448 REG_GSWCK_EN | REG_TRGMIICK_EN);
c3b8e079 449
4732315c
IL		 450 /* Setup core clock for MT7530 */
451 /* Disable PLL */
452 core_write(priv, CORE_GSWPLL_GRP1, 0);
c3b8e079
IL		 453
454 /* Set core clock into 500Mhz */
455 core_write(priv, CORE_GSWPLL_GRP2,
456 RG_GSWPLL_POSDIV_500M(1) |
457 RG_GSWPLL_FBKDIV_500M(25));
458
459 /* Enable PLL */
460 core_write(priv, CORE_GSWPLL_GRP1,
461 RG_GSWPLL_EN_PRE |
462 RG_GSWPLL_POSDIV_200M(2) |
463 RG_GSWPLL_FBKDIV_200M(32));
464
b8f126a8 465 /* Setup the MT7530 TRGMII Tx Clock */
b8f126a8
SW		 466 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
467 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
468 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
469 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
470 core_write(priv, CORE_PLL_GROUP4,
471 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
472 RG_SYSPLL_BIAS_LPF_EN);
473 core_write(priv, CORE_PLL_GROUP2,
474 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
475 RG_SYSPLL_POSDIV(1));
476 core_write(priv, CORE_PLL_GROUP7,
477 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
478 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
4732315c
IL		 479
480 /* Enable MT7530 core and TRGMII Tx clocks */
b8f126a8
SW		 481 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
482 REG_GSWCK_EN | REG_TRGMIICK_EN);
483
484 if (!trgint)
485 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
486 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
487 RD_TAP_MASK, RD_TAP(16));
b8f126a8
SW		 488 return 0;
489}
490
c288575f
LC		 491static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
492{
493 u32 val;
494
495 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
496
497 return (val & PAD_DUAL_SGMII_EN) != 0;
498}
499
500static int
501mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
502{
503 struct mt7530_priv *priv = ds->priv;
504 u32 top_sig;
505 u32 hwstrap;
506 u32 xtal;
507 u32 val;
508
509 if (mt7531_dual_sgmii_supported(priv))
510 return 0;
511
512 val = mt7530_read(priv, MT7531_CREV);
513 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
514 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
515 if ((val & CHIP_REV_M) > 0)
516 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
517 HWTRAP_XTAL_FSEL_25MHZ;
518 else
519 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
520
521 /* Step 1 : Disable MT7531 COREPLL */
522 val = mt7530_read(priv, MT7531_PLLGP_EN);
523 val &= ~EN_COREPLL;
524 mt7530_write(priv, MT7531_PLLGP_EN, val);
525
526 /* Step 2: switch to XTAL output */
527 val = mt7530_read(priv, MT7531_PLLGP_EN);
528 val |= SW_CLKSW;
529 mt7530_write(priv, MT7531_PLLGP_EN, val);
530
531 val = mt7530_read(priv, MT7531_PLLGP_CR0);
532 val &= ~RG_COREPLL_EN;
533 mt7530_write(priv, MT7531_PLLGP_CR0, val);
534
535 /* Step 3: disable PLLGP and enable program PLLGP */
536 val = mt7530_read(priv, MT7531_PLLGP_EN);
537 val |= SW_PLLGP;
538 mt7530_write(priv, MT7531_PLLGP_EN, val);
539
540 /* Step 4: program COREPLL output frequency to 500MHz */
541 val = mt7530_read(priv, MT7531_PLLGP_CR0);
542 val &= ~RG_COREPLL_POSDIV_M;
543 val |= 2 << RG_COREPLL_POSDIV_S;
544 mt7530_write(priv, MT7531_PLLGP_CR0, val);
545 usleep_range(25, 35);
546
547 switch (xtal) {
548 case HWTRAP_XTAL_FSEL_25MHZ:
549 val = mt7530_read(priv, MT7531_PLLGP_CR0);
550 val &= ~RG_COREPLL_SDM_PCW_M;
551 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
552 mt7530_write(priv, MT7531_PLLGP_CR0, val);
553 break;
554 case HWTRAP_XTAL_FSEL_40MHZ:
555 val = mt7530_read(priv, MT7531_PLLGP_CR0);
556 val &= ~RG_COREPLL_SDM_PCW_M;
557 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
558 mt7530_write(priv, MT7531_PLLGP_CR0, val);
559 break;
0e8c266c 560 }
c288575f
LC		 561
562 /* Set feedback divide ratio update signal to high */
563 val = mt7530_read(priv, MT7531_PLLGP_CR0);
564 val |= RG_COREPLL_SDM_PCW_CHG;
565 mt7530_write(priv, MT7531_PLLGP_CR0, val);
566 /* Wait for at least 16 XTAL clocks */
567 usleep_range(10, 20);
568
569 /* Step 5: set feedback divide ratio update signal to low */
570 val = mt7530_read(priv, MT7531_PLLGP_CR0);
571 val &= ~RG_COREPLL_SDM_PCW_CHG;
572 mt7530_write(priv, MT7531_PLLGP_CR0, val);
573
574 /* Enable 325M clock for SGMII */
575 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
576
577 /* Enable 250SSC clock for RGMII */
578 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
579
580 /* Step 6: Enable MT7531 PLL */
581 val = mt7530_read(priv, MT7531_PLLGP_CR0);
582 val |= RG_COREPLL_EN;
583 mt7530_write(priv, MT7531_PLLGP_CR0, val);
584
585 val = mt7530_read(priv, MT7531_PLLGP_EN);
586 val |= EN_COREPLL;
587 mt7530_write(priv, MT7531_PLLGP_EN, val);
588 usleep_range(25, 35);
589
590 return 0;
591}
592
b8f126a8
SW		 593static void
594mt7530_mib_reset(struct dsa_switch *ds)
595{
596 struct mt7530_priv *priv = ds->priv;
597
598 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
600}
601
ba751e28 602static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum)
b8f126a8 603{
b8f126a8
SW		 604 return mdiobus_read_nested(priv->bus, port, regnum);
605}
606
ba751e28 607static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum,
360cc342 608 u16 val)
b8f126a8 609{
b8f126a8
SW		 610 return mdiobus_write_nested(priv->bus, port, regnum, val);
611}
612
c288575f
LC		 613static int
614mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
615 int regnum)
616{
617 struct mii_bus *bus = priv->bus;
618 struct mt7530_dummy_poll p;
619 u32 reg, val;
620 int ret;
621
622 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
623
624 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
625
626 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
627 !(val & MT7531_PHY_ACS_ST), 20, 100000);
628 if (ret < 0) {
629 dev_err(priv->dev, "poll timeout\n");
630 goto out;
631 }
632
633 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
634 MT7531_MDIO_DEV_ADDR(devad) | regnum;
635 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
636
637 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
638 !(val & MT7531_PHY_ACS_ST), 20, 100000);
639 if (ret < 0) {
640 dev_err(priv->dev, "poll timeout\n");
641 goto out;
642 }
643
644 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
645 MT7531_MDIO_DEV_ADDR(devad);
646 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
647
648 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
649 !(val & MT7531_PHY_ACS_ST), 20, 100000);
650 if (ret < 0) {
651 dev_err(priv->dev, "poll timeout\n");
652 goto out;
653 }
654
655 ret = val & MT7531_MDIO_RW_DATA_MASK;
656out:
657 mutex_unlock(&bus->mdio_lock);
658
659 return ret;
660}
661
662static int
663mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
664 int regnum, u32 data)
665{
666 struct mii_bus *bus = priv->bus;
667 struct mt7530_dummy_poll p;
668 u32 val, reg;
669 int ret;
670
671 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
672
673 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
674
675 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
676 !(val & MT7531_PHY_ACS_ST), 20, 100000);
677 if (ret < 0) {
678 dev_err(priv->dev, "poll timeout\n");
679 goto out;
680 }
681
682 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
683 MT7531_MDIO_DEV_ADDR(devad) | regnum;
684 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
685
686 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
687 !(val & MT7531_PHY_ACS_ST), 20, 100000);
688 if (ret < 0) {
689 dev_err(priv->dev, "poll timeout\n");
690 goto out;
691 }
692
693 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
694 MT7531_MDIO_DEV_ADDR(devad) | data;
695 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
696
697 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
698 !(val & MT7531_PHY_ACS_ST), 20, 100000);
699 if (ret < 0) {
700 dev_err(priv->dev, "poll timeout\n");
701 goto out;
702 }
703
704out:
705 mutex_unlock(&bus->mdio_lock);
706
707 return ret;
708}
709
710static int
711mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
712{
713 struct mii_bus *bus = priv->bus;
714 struct mt7530_dummy_poll p;
715 int ret;
716 u32 val;
717
718 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
719
720 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
721
722 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
723 !(val & MT7531_PHY_ACS_ST), 20, 100000);
724 if (ret < 0) {
725 dev_err(priv->dev, "poll timeout\n");
726 goto out;
727 }
728
729 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
730 MT7531_MDIO_REG_ADDR(regnum);
731
732 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
733
734 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
735 !(val & MT7531_PHY_ACS_ST), 20, 100000);
736 if (ret < 0) {
737 dev_err(priv->dev, "poll timeout\n");
738 goto out;
739 }
740
741 ret = val & MT7531_MDIO_RW_DATA_MASK;
742out:
743 mutex_unlock(&bus->mdio_lock);
744
745 return ret;
746}
747
748static int
749mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
750 u16 data)
751{
752 struct mii_bus *bus = priv->bus;
753 struct mt7530_dummy_poll p;
754 int ret;
755 u32 reg;
756
757 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
758
759 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
760
761 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
762 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
763 if (ret < 0) {
764 dev_err(priv->dev, "poll timeout\n");
765 goto out;
766 }
767
768 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
769 MT7531_MDIO_REG_ADDR(regnum) | data;
770
771 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
772
773 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
774 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
775 if (ret < 0) {
776 dev_err(priv->dev, "poll timeout\n");
777 goto out;
778 }
779
780out:
781 mutex_unlock(&bus->mdio_lock);
782
783 return ret;
784}
785
786static int
ba751e28 787mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum)
c288575f 788{
c288575f
LC		 789 int devad;
790 int ret;
791
792 if (regnum & MII_ADDR_C45) {
793 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
794 ret = mt7531_ind_c45_phy_read(priv, port, devad,
795 regnum & MII_REGADDR_C45_MASK);
796 } else {
797 ret = mt7531_ind_c22_phy_read(priv, port, regnum);
798 }
799
800 return ret;
801}
802
803static int
ba751e28 804mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum,
c288575f
LC		 805 u16 data)
806{
c288575f
LC		 807 int devad;
808 int ret;
809
810 if (regnum & MII_ADDR_C45) {
811 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
812 ret = mt7531_ind_c45_phy_write(priv, port, devad,
813 regnum & MII_REGADDR_C45_MASK,
814 data);
815 } else {
816 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
817 }
818
819 return ret;
820}
821
ba751e28
DQ		 822static int
823mt753x_phy_read(struct mii_bus *bus, int port, int regnum)
824{
825 struct mt7530_priv *priv = bus->priv;
826
827 return priv->info->phy_read(priv, port, regnum);
828}
829
830static int
831mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val)
832{
833 struct mt7530_priv *priv = bus->priv;
834
835 return priv->info->phy_write(priv, port, regnum, val);
836}
837
b8f126a8 838static void
89f09048
FF		 839mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
840 uint8_t *data)
b8f126a8
SW		 841{
842 int i;
843
89f09048
FF		 844 if (stringset != ETH_SS_STATS)
845 return;
846
b8f126a8
SW		 847 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
848 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
849 ETH_GSTRING_LEN);
850}
851
852static void
853mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
854 uint64_t *data)
855{
856 struct mt7530_priv *priv = ds->priv;
857 const struct mt7530_mib_desc *mib;
858 u32 reg, i;
859 u64 hi;
860
861 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
862 mib = &mt7530_mib[i];
863 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
864
865 data[i] = mt7530_read(priv, reg);
866 if (mib->size == 2) {
867 hi = mt7530_read(priv, reg + 4);
868 data[i] |= hi << 32;
869 }
870 }
871}
872
873static int
89f09048 874mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
b8f126a8 875{
89f09048
FF		 876 if (sset != ETH_SS_STATS)
877 return 0;
878
b8f126a8
SW		 879 return ARRAY_SIZE(mt7530_mib);
880}
881
ea6d5c92
DQ		 882static int
883mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
884{
885 struct mt7530_priv *priv = ds->priv;
886 unsigned int secs = msecs / 1000;
887 unsigned int tmp_age_count;
888 unsigned int error = -1;
889 unsigned int age_count;
890 unsigned int age_unit;
891
892 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
893 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
894 return -ERANGE;
895
896 /* iterate through all possible age_count to find the closest pair */
897 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
898 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
899
900 if (tmp_age_unit <= AGE_UNIT_MAX) {
901 unsigned int tmp_error = secs -
902 (tmp_age_count + 1) * (tmp_age_unit + 1);
903
904 /* found a closer pair */
905 if (error > tmp_error) {
906 error = tmp_error;
907 age_count = tmp_age_count;
908 age_unit = tmp_age_unit;
909 }
910
911 /* found the exact match, so break the loop */
912 if (!error)
913 break;
914 }
915 }
916
917 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
918
919 return 0;
920}
921
38f790a8
RD		 922static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
923{
924 struct mt7530_priv *priv = ds->priv;
925 u8 tx_delay = 0;
926 int val;
927
928 mutex_lock(&priv->reg_mutex);
929
930 val = mt7530_read(priv, MT7530_MHWTRAP);
931
932 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
933 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
934
935 switch (priv->p5_intf_sel) {
936 case P5_INTF_SEL_PHY_P0:
937 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
938 val |= MHWTRAP_PHY0_SEL;
df561f66 939 fallthrough;
38f790a8
RD		 940 case P5_INTF_SEL_PHY_P4:
941 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
942 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
943
944 /* Setup the MAC by default for the cpu port */
945 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
946 break;
947 case P5_INTF_SEL_GMAC5:
948 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
949 val &= ~MHWTRAP_P5_DIS;
950 break;
951 case P5_DISABLED:
952 interface = PHY_INTERFACE_MODE_NA;
953 break;
954 default:
955 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
956 priv->p5_intf_sel);
957 goto unlock_exit;
958 }
959
960 /* Setup RGMII settings */
961 if (phy_interface_mode_is_rgmii(interface)) {
962 val |= MHWTRAP_P5_RGMII_MODE;
963
964 /* P5 RGMII RX Clock Control: delay setting for 1000M */
965 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
966
967 /* Don't set delay in DSA mode */
968 if (!dsa_is_dsa_port(priv->ds, 5) &&
969 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
970 interface == PHY_INTERFACE_MODE_RGMII_ID))
971 tx_delay = 4; /* n * 0.5 ns */
972
973 /* P5 RGMII TX Clock Control: delay x */
974 mt7530_write(priv, MT7530_P5RGMIITXCR,
975 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
976
977 /* reduce P5 RGMII Tx driving, 8mA */
978 mt7530_write(priv, MT7530_IO_DRV_CR,
979 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
980 }
981
982 mt7530_write(priv, MT7530_MHWTRAP, val);
983
984 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
985 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
986
987 priv->p5_interface = interface;
988
989unlock_exit:
990 mutex_unlock(&priv->reg_mutex);
991}
992
b8f126a8 993static int
c288575f 994mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
b8f126a8 995{
c288575f 996 struct mt7530_priv *priv = ds->priv;
0ce0c3cd 997 int ret;
c288575f
LC		 998
999 /* Setup max capability of CPU port at first */
0ce0c3cd
AD		 1000 if (priv->info->cpu_port_config) {
1001 ret = priv->info->cpu_port_config(ds, port);
1002 if (ret)
1003 return ret;
1004 }
c288575f 1005
b8f126a8
SW		 1006 /* Enable Mediatek header mode on the cpu port */
1007 mt7530_write(priv, MT7530_PVC_P(port),
1008 PORT_SPEC_TAG);
1009
5a30833b
DQ		 1010 /* Disable flooding by default */
1011 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK,
1012 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port)));
b8f126a8 1013
ddda1ac1
GU		 1014 /* Set CPU port number */
1015 if (priv->id == ID_MT7621)
1016 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1017
b8f126a8 1018 /* CPU port gets connected to all user ports of
c288575f 1019 * the switch.
b8f126a8
SW		 1020 */
1021 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 1022 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8
SW		 1023
1024 return 0;
1025}
1026
1027static int
1028mt7530_port_enable(struct dsa_switch *ds, int port,
1029 struct phy_device *phy)
1030{
1031 struct mt7530_priv *priv = ds->priv;
1032
74be4bab
VD		 1033 if (!dsa_is_user_port(ds, port))
1034 return 0;
1035
b8f126a8
SW		 1036 mutex_lock(&priv->reg_mutex);
1037
b8f126a8
SW		 1038 /* Allow the user port gets connected to the cpu port and also
1039 * restore the port matrix if the port is the member of a certain
1040 * bridge.
1041 */
1042 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
1043 priv->ports[port].enable = true;
1044 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1045 priv->ports[port].pm);
1d01145f 1046 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1047
1048 mutex_unlock(&priv->reg_mutex);
1049
1050 return 0;
1051}
1052
1053static void
75104db0 1054mt7530_port_disable(struct dsa_switch *ds, int port)
b8f126a8
SW		 1055{
1056 struct mt7530_priv *priv = ds->priv;
1057
74be4bab
VD		 1058 if (!dsa_is_user_port(ds, port))
1059 return;
1060
b8f126a8
SW		 1061 mutex_lock(&priv->reg_mutex);
1062
1063 /* Clear up all port matrix which could be restored in the next
1064 * enablement for the port.
1065 */
1066 priv->ports[port].enable = false;
1067 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1068 PCR_MATRIX_CLR);
1d01145f 1069 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1070
1071 mutex_unlock(&priv->reg_mutex);
1072}
1073
9470174e
DQ		 1074static int
1075mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1076{
1077 struct mt7530_priv *priv = ds->priv;
1078 struct mii_bus *bus = priv->bus;
1079 int length;
1080 u32 val;
1081
1082 /* When a new MTU is set, DSA always set the CPU port's MTU to the
1083 * largest MTU of the slave ports. Because the switch only has a global
1084 * RX length register, only allowing CPU port here is enough.
1085 */
1086 if (!dsa_is_cpu_port(ds, port))
1087 return 0;
1088
1089 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1090
1091 val = mt7530_mii_read(priv, MT7530_GMACCR);
1092 val &= ~MAX_RX_PKT_LEN_MASK;
1093
1094 /* RX length also includes Ethernet header, MTK tag, and FCS length */
1095 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1096 if (length <= 1522) {
1097 val |= MAX_RX_PKT_LEN_1522;
1098 } else if (length <= 1536) {
1099 val |= MAX_RX_PKT_LEN_1536;
1100 } else if (length <= 1552) {
1101 val |= MAX_RX_PKT_LEN_1552;
1102 } else {
1103 val &= ~MAX_RX_JUMBO_MASK;
1104 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1105 val |= MAX_RX_PKT_LEN_JUMBO;
1106 }
1107
1108 mt7530_mii_write(priv, MT7530_GMACCR, val);
1109
1110 mutex_unlock(&bus->mdio_lock);
1111
1112 return 0;
1113}
1114
1115static int
1116mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1117{
1118 return MT7530_MAX_MTU;
1119}
1120
b8f126a8
SW		 1121static void
1122mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1123{
1124 struct mt7530_priv *priv = ds->priv;
1125 u32 stp_state;
1126
1127 switch (state) {
1128 case BR_STATE_DISABLED:
1129 stp_state = MT7530_STP_DISABLED;
1130 break;
1131 case BR_STATE_BLOCKING:
1132 stp_state = MT7530_STP_BLOCKING;
1133 break;
1134 case BR_STATE_LISTENING:
1135 stp_state = MT7530_STP_LISTENING;
1136 break;
1137 case BR_STATE_LEARNING:
1138 stp_state = MT7530_STP_LEARNING;
1139 break;
1140 case BR_STATE_FORWARDING:
1141 default:
1142 stp_state = MT7530_STP_FORWARDING;
1143 break;
1144 }
1145
1146 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
1147}
1148
5a30833b
DQ		 1149static int
1150mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1151 struct switchdev_brport_flags flags,
1152 struct netlink_ext_ack *extack)
1153{
1154 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1155 BR_BCAST_FLOOD))
1156 return -EINVAL;
1157
1158 return 0;
1159}
1160
1161static int
1162mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
1163 struct switchdev_brport_flags flags,
1164 struct netlink_ext_ack *extack)
1165{
1166 struct mt7530_priv *priv = ds->priv;
1167
1168 if (flags.mask & BR_LEARNING)
1169 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
1170 flags.val & BR_LEARNING ? 0 : SA_DIS);
1171
1172 if (flags.mask & BR_FLOOD)
1173 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
1174 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1175
1176 if (flags.mask & BR_MCAST_FLOOD)
1177 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1178 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1179
1180 if (flags.mask & BR_BCAST_FLOOD)
1181 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
1182 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1183
1184 return 0;
1185}
1186
1187static int
1188mt7530_port_set_mrouter(struct dsa_switch *ds, int port, bool mrouter,
1189 struct netlink_ext_ack *extack)
1190{
1191 struct mt7530_priv *priv = ds->priv;
1192
1193 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1194 mrouter ? UNM_FFP(BIT(port)) : 0);
1195
1196 return 0;
1197}
1198
b8f126a8
SW		 1199static int
1200mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1201 struct net_device *bridge)
1202{
1203 struct mt7530_priv *priv = ds->priv;
1204 u32 port_bitmap = BIT(MT7530_CPU_PORT);
1205 int i;
1206
1207 mutex_lock(&priv->reg_mutex);
1208
1209 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1210 /* Add this port to the port matrix of the other ports in the
1211 * same bridge. If the port is disabled, port matrix is kept
1212 * and not being setup until the port becomes enabled.
1213 */
4a5b85ff 1214 if (dsa_is_user_port(ds, i) && i != port) {
c8652c83 1215 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 1216 continue;
1217 if (priv->ports[i].enable)
1218 mt7530_set(priv, MT7530_PCR_P(i),
1219 PCR_MATRIX(BIT(port)));
1220 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
1221
1222 port_bitmap |= BIT(i);
1223 }
1224 }
1225
1226 /* Add the all other ports to this port matrix. */
1227 if (priv->ports[port].enable)
1228 mt7530_rmw(priv, MT7530_PCR_P(port),
1229 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1230 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1231
1232 mutex_unlock(&priv->reg_mutex);
1233
1234 return 0;
1235}
1236
83163f7d
SW		 1237static void
1238mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1239{
1240 struct mt7530_priv *priv = ds->priv;
1241 bool all_user_ports_removed = true;
1242 int i;
1243
1244 /* When a port is removed from the bridge, the port would be set up
1245 * back to the default as is at initial boot which is a VLAN-unaware
1246 * port.
1247 */
1248 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1249 MT7530_PORT_MATRIX_MODE);
e045124e
DQ		 1250 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1251 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
1252 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d 1253
83163f7d
SW		 1254 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1255 if (dsa_is_user_port(ds, i) &&
68bb8ea8 1256 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
83163f7d
SW		 1257 all_user_ports_removed = false;
1258 break;
1259 }
1260 }
1261
1262 /* CPU port also does the same thing until all user ports belonging to
1263 * the CPU port get out of VLAN filtering mode.
1264 */
1265 if (all_user_ports_removed) {
1266 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
1267 PCR_MATRIX(dsa_user_ports(priv->ds)));
e045124e
DQ		 1268 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
1269 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d
SW		 1270 }
1271}
1272
1273static void
1274mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1275{
1276 struct mt7530_priv *priv = ds->priv;
1277
83163f7d 1278 /* Trapped into security mode allows packet forwarding through VLAN
38152ea3
DQ		 1279 * table lookup. CPU port is set to fallback mode to let untagged
1280 * frames pass through.
83163f7d 1281 */
38152ea3
DQ		 1282 if (dsa_is_cpu_port(ds, port))
1283 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1284 MT7530_PORT_FALLBACK_MODE);
1285 else
1286 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1287 MT7530_PORT_SECURITY_MODE);
83163f7d
SW		 1288
1289 /* Set the port as a user port which is to be able to recognize VID
1290 * from incoming packets before fetching entry within the VLAN table.
1291 */
e045124e
DQ		 1292 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1293 VLAN_ATTR(MT7530_VLAN_USER) |
1294 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
83163f7d
SW		 1295}
1296
b8f126a8
SW		 1297static void
1298mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1299 struct net_device *bridge)
1300{
1301 struct mt7530_priv *priv = ds->priv;
1302 int i;
1303
1304 mutex_lock(&priv->reg_mutex);
1305
1306 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1307 /* Remove this port from the port matrix of the other ports
1308 * in the same bridge. If the port is disabled, port matrix
1309 * is kept and not being setup until the port becomes enabled.
83163f7d
SW		 1310 * And the other port's port matrix cannot be broken when the
1311 * other port is still a VLAN-aware port.
b8f126a8 1312 */
2a130551 1313 if (dsa_is_user_port(ds, i) && i != port &&
68bb8ea8 1314 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
c8652c83 1315 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 1316 continue;
1317 if (priv->ports[i].enable)
1318 mt7530_clear(priv, MT7530_PCR_P(i),
1319 PCR_MATRIX(BIT(port)));
1320 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
1321 }
1322 }
1323
1324 /* Set the cpu port to be the only one in the port matrix of
1325 * this port.
1326 */
1327 if (priv->ports[port].enable)
1328 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1329 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
1330 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
1331
1332 mutex_unlock(&priv->reg_mutex);
1333}
1334
1335static int
b8f126a8 1336mt7530_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 1337 const unsigned char *addr, u16 vid)
b8f126a8
SW		 1338{
1339 struct mt7530_priv *priv = ds->priv;
1b6dd556 1340 int ret;
b8f126a8
SW		 1341 u8 port_mask = BIT(port);
1342
1343 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1344 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 1345 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 1346 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 1347
1348 return ret;
b8f126a8
SW		 1349}
1350
1351static int
1352mt7530_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1353 const unsigned char *addr, u16 vid)
b8f126a8
SW		 1354{
1355 struct mt7530_priv *priv = ds->priv;
1356 int ret;
1357 u8 port_mask = BIT(port);
1358
1359 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1360 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 1361 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 1362 mutex_unlock(&priv->reg_mutex);
1363
1364 return ret;
1365}
1366
1367static int
1368mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1369 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 1370{
1371 struct mt7530_priv *priv = ds->priv;
1372 struct mt7530_fdb _fdb = { 0 };
1373 int cnt = MT7530_NUM_FDB_RECORDS;
1374 int ret = 0;
1375 u32 rsp = 0;
1376
1377 mutex_lock(&priv->reg_mutex);
1378
1379 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1380 if (ret < 0)
1381 goto err;
1382
1383 do {
1384 if (rsp & ATC_SRCH_HIT) {
1385 mt7530_fdb_read(priv, &_fdb);
1386 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 1387 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1388 data);
b8f126a8
SW		 1389 if (ret < 0)
1390 break;
1391 }
1392 }
1393 } while (--cnt &&
1394 !(rsp & ATC_SRCH_END) &&
1395 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1396err:
1397 mutex_unlock(&priv->reg_mutex);
1398
1399 return 0;
1400}
1401
5a30833b
DQ		 1402static int
1403mt7530_port_mdb_add(struct dsa_switch *ds, int port,
1404 const struct switchdev_obj_port_mdb *mdb)
1405{
1406 struct mt7530_priv *priv = ds->priv;
1407 const u8 *addr = mdb->addr;
1408 u16 vid = mdb->vid;
1409 u8 port_mask = 0;
1410 int ret;
1411
1412 mutex_lock(&priv->reg_mutex);
1413
1414 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1415 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1416 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1417 & PORT_MAP_MASK;
1418
1419 port_mask |= BIT(port);
1420 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1421 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1422
1423 mutex_unlock(&priv->reg_mutex);
1424
1425 return ret;
1426}
1427
1428static int
1429mt7530_port_mdb_del(struct dsa_switch *ds, int port,
1430 const struct switchdev_obj_port_mdb *mdb)
1431{
1432 struct mt7530_priv *priv = ds->priv;
1433 const u8 *addr = mdb->addr;
1434 u16 vid = mdb->vid;
1435 u8 port_mask = 0;
1436 int ret;
1437
1438 mutex_lock(&priv->reg_mutex);
1439
1440 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1441 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1442 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1443 & PORT_MAP_MASK;
1444
1445 port_mask &= ~BIT(port);
1446 mt7530_fdb_write(priv, vid, port_mask, addr, -1,
1447 port_mask ? STATIC_ENT : STATIC_EMP);
1448 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1449
1450 mutex_unlock(&priv->reg_mutex);
1451
1452 return ret;
1453}
1454
83163f7d
SW		 1455static int
1456mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1457{
1458 struct mt7530_dummy_poll p;
1459 u32 val;
1460 int ret;
1461
1462 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1463 mt7530_write(priv, MT7530_VTCR, val);
1464
1465 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1466 ret = readx_poll_timeout(_mt7530_read, &p, val,
1467 !(val & VTCR_BUSY), 20, 20000);
1468 if (ret < 0) {
1469 dev_err(priv->dev, "poll timeout\n");
1470 return ret;
1471 }
1472
1473 val = mt7530_read(priv, MT7530_VTCR);
1474 if (val & VTCR_INVALID) {
1475 dev_err(priv->dev, "read VTCR invalid\n");
1476 return -EINVAL;
1477 }
1478
1479 return 0;
1480}
1481
1482static int
89153ed6
VO		 1483mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1484 struct netlink_ext_ack *extack)
83163f7d 1485{
83163f7d
SW		 1486 if (vlan_filtering) {
1487 /* The port is being kept as VLAN-unaware port when bridge is
1488 * set up with vlan_filtering not being set, Otherwise, the
1489 * port and the corresponding CPU port is required the setup
1490 * for becoming a VLAN-aware port.
1491 */
1492 mt7530_port_set_vlan_aware(ds, port);
1493 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
e3ee07d1
VO		 1494 } else {
1495 mt7530_port_set_vlan_unaware(ds, port);
83163f7d
SW		 1496 }
1497
1498 return 0;
1499}
1500
83163f7d
SW		 1501static void
1502mt7530_hw_vlan_add(struct mt7530_priv *priv,
1503 struct mt7530_hw_vlan_entry *entry)
1504{
1505 u8 new_members;
1506 u32 val;
1507
1508 new_members = entry->old_members | BIT(entry->port) |
1509 BIT(MT7530_CPU_PORT);
1510
1511 /* Validate the entry with independent learning, create egress tag per
1512 * VLAN and joining the port as one of the port members.
1513 */
1514 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1515 mt7530_write(priv, MT7530_VAWD1, val);
1516
1517 /* Decide whether adding tag or not for those outgoing packets from the
1518 * port inside the VLAN.
1519 */
1520 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1521 MT7530_VLAN_EGRESS_TAG;
1522 mt7530_rmw(priv, MT7530_VAWD2,
1523 ETAG_CTRL_P_MASK(entry->port),
1524 ETAG_CTRL_P(entry->port, val));
1525
1526 /* CPU port is always taken as a tagged port for serving more than one
1527 * VLANs across and also being applied with egress type stack mode for
1528 * that VLAN tags would be appended after hardware special tag used as
1529 * DSA tag.
1530 */
1531 mt7530_rmw(priv, MT7530_VAWD2,
1532 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1533 ETAG_CTRL_P(MT7530_CPU_PORT,
1534 MT7530_VLAN_EGRESS_STACK));
1535}
1536
1537static void
1538mt7530_hw_vlan_del(struct mt7530_priv *priv,
1539 struct mt7530_hw_vlan_entry *entry)
1540{
1541 u8 new_members;
1542 u32 val;
1543
1544 new_members = entry->old_members & ~BIT(entry->port);
1545
1546 val = mt7530_read(priv, MT7530_VAWD1);
1547 if (!(val & VLAN_VALID)) {
1548 dev_err(priv->dev,
1549 "Cannot be deleted due to invalid entry\n");
1550 return;
1551 }
1552
1553 /* If certain member apart from CPU port is still alive in the VLAN,
1554 * the entry would be kept valid. Otherwise, the entry is got to be
1555 * disabled.
1556 */
1557 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1558 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1559 VLAN_VALID;
1560 mt7530_write(priv, MT7530_VAWD1, val);
1561 } else {
1562 mt7530_write(priv, MT7530_VAWD1, 0);
1563 mt7530_write(priv, MT7530_VAWD2, 0);
1564 }
1565}
1566
1567static void
1568mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1569 struct mt7530_hw_vlan_entry *entry,
1570 mt7530_vlan_op vlan_op)
1571{
1572 u32 val;
1573
1574 /* Fetch entry */
1575 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1576
1577 val = mt7530_read(priv, MT7530_VAWD1);
1578
1579 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1580
1581 /* Manipulate entry */
1582 vlan_op(priv, entry);
1583
1584 /* Flush result to hardware */
1585 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1586}
1587
1958d581 1588static int
83163f7d 1589mt7530_port_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 1590 const struct switchdev_obj_port_vlan *vlan,
1591 struct netlink_ext_ack *extack)
83163f7d
SW		 1592{
1593 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1594 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1595 struct mt7530_hw_vlan_entry new_entry;
1596 struct mt7530_priv *priv = ds->priv;
83163f7d 1597
83163f7d
SW		 1598 mutex_lock(&priv->reg_mutex);
1599
b7a9e0da
VO		 1600 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1601 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
83163f7d
SW		 1602
1603 if (pvid) {
1604 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
b7a9e0da
VO		 1605 G0_PORT_VID(vlan->vid));
1606 priv->ports[port].pvid = vlan->vid;
83163f7d
SW		 1607 }
1608
1609 mutex_unlock(&priv->reg_mutex);
1958d581
VO		 1610
1611 return 0;
83163f7d
SW		 1612}
1613
1614static int
1615mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1616 const struct switchdev_obj_port_vlan *vlan)
1617{
1618 struct mt7530_hw_vlan_entry target_entry;
1619 struct mt7530_priv *priv = ds->priv;
b7a9e0da 1620 u16 pvid;
83163f7d 1621
83163f7d
SW		 1622 mutex_lock(&priv->reg_mutex);
1623
1624 pvid = priv->ports[port].pvid;
b7a9e0da
VO		 1625 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1626 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1627 mt7530_hw_vlan_del);
83163f7d 1628
b7a9e0da
VO		 1629 /* PVID is being restored to the default whenever the PVID port
1630 * is being removed from the VLAN.
1631 */
1632 if (pvid == vlan->vid)
1633 pvid = G0_PORT_VID_DEF;
83163f7d
SW		 1634
1635 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1636 priv->ports[port].pvid = pvid;
1637
1638 mutex_unlock(&priv->reg_mutex);
1639
1640 return 0;
1641}
1642
c288575f
LC		 1643static int mt753x_mirror_port_get(unsigned int id, u32 val)
1644{
1645 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1646 MIRROR_PORT(val);
1647}
1648
1649static int mt753x_mirror_port_set(unsigned int id, u32 val)
1650{
1651 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1652 MIRROR_PORT(val);
1653}
1654
1655static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
37feab60
DQ		 1656 struct dsa_mall_mirror_tc_entry *mirror,
1657 bool ingress)
1658{
1659 struct mt7530_priv *priv = ds->priv;
c288575f 1660 int monitor_port;
37feab60
DQ		 1661 u32 val;
1662
1663 /* Check for existent entry */
1664 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1665 return -EEXIST;
1666
c288575f 1667 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
37feab60
DQ		 1668
1669 /* MT7530 only supports one monitor port */
c288575f
LC		 1670 monitor_port = mt753x_mirror_port_get(priv->id, val);
1671 if (val & MT753X_MIRROR_EN(priv->id) &&
1672 monitor_port != mirror->to_local_port)
37feab60
DQ		 1673 return -EEXIST;
1674
c288575f
LC		 1675 val |= MT753X_MIRROR_EN(priv->id);
1676 val &= ~MT753X_MIRROR_MASK(priv->id);
1677 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1678 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1679
1680 val = mt7530_read(priv, MT7530_PCR_P(port));
1681 if (ingress) {
1682 val |= PORT_RX_MIR;
1683 priv->mirror_rx |= BIT(port);
1684 } else {
1685 val |= PORT_TX_MIR;
1686 priv->mirror_tx |= BIT(port);
1687 }
1688 mt7530_write(priv, MT7530_PCR_P(port), val);
1689
1690 return 0;
1691}
1692
c288575f 1693static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
37feab60
DQ		 1694 struct dsa_mall_mirror_tc_entry *mirror)
1695{
1696 struct mt7530_priv *priv = ds->priv;
1697 u32 val;
1698
1699 val = mt7530_read(priv, MT7530_PCR_P(port));
1700 if (mirror->ingress) {
1701 val &= ~PORT_RX_MIR;
1702 priv->mirror_rx &= ~BIT(port);
1703 } else {
1704 val &= ~PORT_TX_MIR;
1705 priv->mirror_tx &= ~BIT(port);
1706 }
1707 mt7530_write(priv, MT7530_PCR_P(port), val);
1708
1709 if (!priv->mirror_rx && !priv->mirror_tx) {
c288575f
LC		 1710 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1711 val &= ~MT753X_MIRROR_EN(priv->id);
1712 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1713 }
1714}
1715
b8f126a8 1716static enum dsa_tag_protocol
4d776482
FF		 1717mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1718 enum dsa_tag_protocol mp)
b8f126a8
SW		 1719{
1720 struct mt7530_priv *priv = ds->priv;
1721
5ed4e3eb 1722 if (port != MT7530_CPU_PORT) {
b8f126a8
SW		 1723 dev_warn(priv->dev,
1724 "port not matched with tagging CPU port\n");
1725 return DSA_TAG_PROTO_NONE;
1726 } else {
1727 return DSA_TAG_PROTO_MTK;
1728 }
1729}
1730
63c75c05 1731#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 1732static inline u32
1733mt7530_gpio_to_bit(unsigned int offset)
1734{
1735 /* Map GPIO offset to register bit
1736 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2
1737 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5
1738 * [10: 8] port 2 LED 0..2 as GPIO 6..8
1739 * [14:12] port 3 LED 0..2 as GPIO 9..11
1740 * [18:16] port 4 LED 0..2 as GPIO 12..14
1741 */
1742 return BIT(offset + offset / 3);
1743}
1744
1745static int
1746mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1747{
1748 struct mt7530_priv *priv = gpiochip_get_data(gc);
1749 u32 bit = mt7530_gpio_to_bit(offset);
1750
1751 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1752}
1753
1754static void
1755mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1756{
1757 struct mt7530_priv *priv = gpiochip_get_data(gc);
1758 u32 bit = mt7530_gpio_to_bit(offset);
1759
1760 if (value)
1761 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1762 else
1763 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1764}
1765
1766static int
1767mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1768{
1769 struct mt7530_priv *priv = gpiochip_get_data(gc);
1770 u32 bit = mt7530_gpio_to_bit(offset);
1771
1772 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1773 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1774}
1775
1776static int
1777mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1778{
1779 struct mt7530_priv *priv = gpiochip_get_data(gc);
1780 u32 bit = mt7530_gpio_to_bit(offset);
1781
1782 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1783 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1784
1785 return 0;
1786}
1787
1788static int
1789mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1790{
1791 struct mt7530_priv *priv = gpiochip_get_data(gc);
1792 u32 bit = mt7530_gpio_to_bit(offset);
1793
1794 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1795
1796 if (value)
1797 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1798 else
1799 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1800
1801 mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1802
1803 return 0;
1804}
1805
1806static int
1807mt7530_setup_gpio(struct mt7530_priv *priv)
1808{
1809 struct device *dev = priv->dev;
1810 struct gpio_chip *gc;
1811
1812 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1813 if (!gc)
1814 return -ENOMEM;
1815
1816 mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1817 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1818 mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1819
1820 gc->label = "mt7530";
1821 gc->parent = dev;
1822 gc->owner = THIS_MODULE;
1823 gc->get_direction = mt7530_gpio_get_direction;
1824 gc->direction_input = mt7530_gpio_direction_input;
1825 gc->direction_output = mt7530_gpio_direction_output;
1826 gc->get = mt7530_gpio_get;
1827 gc->set = mt7530_gpio_set;
1828 gc->base = -1;
1829 gc->ngpio = 15;
1830 gc->can_sleep = true;
1831
1832 return devm_gpiochip_add_data(dev, gc, priv);
1833}
63c75c05 1834#endif /* CONFIG_GPIOLIB */
429a0ede 1835
ba751e28
DQ		 1836static irqreturn_t
1837mt7530_irq_thread_fn(int irq, void *dev_id)
1838{
1839 struct mt7530_priv *priv = dev_id;
1840 bool handled = false;
1841 u32 val;
1842 int p;
1843
1844 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1845 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
1846 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
1847 mutex_unlock(&priv->bus->mdio_lock);
1848
1849 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1850 if (BIT(p) & val) {
1851 unsigned int irq;
1852
1853 irq = irq_find_mapping(priv->irq_domain, p);
1854 handle_nested_irq(irq);
1855 handled = true;
1856 }
1857 }
1858
1859 return IRQ_RETVAL(handled);
1860}
1861
1862static void
1863mt7530_irq_mask(struct irq_data *d)
1864{
1865 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1866
1867 priv->irq_enable &= ~BIT(d->hwirq);
1868}
1869
1870static void
1871mt7530_irq_unmask(struct irq_data *d)
1872{
1873 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1874
1875 priv->irq_enable |= BIT(d->hwirq);
1876}
1877
1878static void
1879mt7530_irq_bus_lock(struct irq_data *d)
1880{
1881 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1882
1883 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1884}
1885
1886static void
1887mt7530_irq_bus_sync_unlock(struct irq_data *d)
1888{
1889 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1890
1891 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1892 mutex_unlock(&priv->bus->mdio_lock);
1893}
1894
1895static struct irq_chip mt7530_irq_chip = {
1896 .name = KBUILD_MODNAME,
1897 .irq_mask = mt7530_irq_mask,
1898 .irq_unmask = mt7530_irq_unmask,
1899 .irq_bus_lock = mt7530_irq_bus_lock,
1900 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock,
1901};
1902
1903static int
1904mt7530_irq_map(struct irq_domain *domain, unsigned int irq,
1905 irq_hw_number_t hwirq)
1906{
1907 irq_set_chip_data(irq, domain->host_data);
1908 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq);
1909 irq_set_nested_thread(irq, true);
1910 irq_set_noprobe(irq);
1911
1912 return 0;
1913}
1914
1915static const struct irq_domain_ops mt7530_irq_domain_ops = {
1916 .map = mt7530_irq_map,
1917 .xlate = irq_domain_xlate_onecell,
1918};
1919
1920static void
1921mt7530_setup_mdio_irq(struct mt7530_priv *priv)
1922{
1923 struct dsa_switch *ds = priv->ds;
1924 int p;
1925
1926 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1927 if (BIT(p) & ds->phys_mii_mask) {
1928 unsigned int irq;
1929
1930 irq = irq_create_mapping(priv->irq_domain, p);
1931 ds->slave_mii_bus->irq[p] = irq;
1932 }
1933 }
1934}
1935
1936static int
1937mt7530_setup_irq(struct mt7530_priv *priv)
1938{
1939 struct device *dev = priv->dev;
1940 struct device_node *np = dev->of_node;
1941 int ret;
1942
1943 if (!of_property_read_bool(np, "interrupt-controller")) {
1944 dev_info(dev, "no interrupt support\n");
1945 return 0;
1946 }
1947
1948 priv->irq = of_irq_get(np, 0);
1949 if (priv->irq <= 0) {
1950 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq);
1951 return priv->irq ? : -EINVAL;
1952 }
1953
1954 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
1955 &mt7530_irq_domain_ops, priv);
1956 if (!priv->irq_domain) {
1957 dev_err(dev, "failed to create IRQ domain\n");
1958 return -ENOMEM;
1959 }
1960
1961 /* This register must be set for MT7530 to properly fire interrupts */
1962 if (priv->id != ID_MT7531)
1963 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
1964
1965 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
1966 IRQF_ONESHOT, KBUILD_MODNAME, priv);
1967 if (ret) {
1968 irq_domain_remove(priv->irq_domain);
1969 dev_err(dev, "failed to request IRQ: %d\n", ret);
1970 return ret;
1971 }
1972
1973 return 0;
1974}
1975
1976static void
1977mt7530_free_mdio_irq(struct mt7530_priv *priv)
1978{
1979 int p;
1980
1981 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1982 if (BIT(p) & priv->ds->phys_mii_mask) {
1983 unsigned int irq;
1984
1985 irq = irq_find_mapping(priv->irq_domain, p);
1986 irq_dispose_mapping(irq);
1987 }
1988 }
1989}
1990
1991static void
1992mt7530_free_irq_common(struct mt7530_priv *priv)
1993{
1994 free_irq(priv->irq, priv);
1995 irq_domain_remove(priv->irq_domain);
1996}
1997
1998static void
1999mt7530_free_irq(struct mt7530_priv *priv)
2000{
2001 mt7530_free_mdio_irq(priv);
2002 mt7530_free_irq_common(priv);
2003}
2004
2005static int
2006mt7530_setup_mdio(struct mt7530_priv *priv)
2007{
2008 struct dsa_switch *ds = priv->ds;
2009 struct device *dev = priv->dev;
2010 struct mii_bus *bus;
2011 static int idx;
2012 int ret;
2013
2014 bus = devm_mdiobus_alloc(dev);
2015 if (!bus)
2016 return -ENOMEM;
2017
2018 ds->slave_mii_bus = bus;
2019 bus->priv = priv;
2020 bus->name = KBUILD_MODNAME "-mii";
2021 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
2022 bus->read = mt753x_phy_read;
2023 bus->write = mt753x_phy_write;
2024 bus->parent = dev;
2025 bus->phy_mask = ~ds->phys_mii_mask;
2026
2027 if (priv->irq)
2028 mt7530_setup_mdio_irq(priv);
2029
2030 ret = mdiobus_register(bus);
2031 if (ret) {
2032 dev_err(dev, "failed to register MDIO bus: %d\n", ret);
2033 if (priv->irq)
2034 mt7530_free_mdio_irq(priv);
2035 }
2036
2037 return ret;
2038}
2039
b8f126a8
SW		 2040static int
2041mt7530_setup(struct dsa_switch *ds)
2042{
2043 struct mt7530_priv *priv = ds->priv;
38f790a8
RD		 2044 struct device_node *phy_node;
2045 struct device_node *mac_np;
b8f126a8 2046 struct mt7530_dummy_poll p;
38f790a8 2047 phy_interface_t interface;
ca366d6c
RD		 2048 struct device_node *dn;
2049 u32 id, val;
2050 int ret, i;
b8f126a8 2051
0abfd494 2052 /* The parent node of master netdev which holds the common system
b8f126a8
SW		 2053 * controller also is the container for two GMACs nodes representing
2054 * as two netdev instances.
2055 */
68bb8ea8 2056 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
771c8901 2057 ds->mtu_enforcement_ingress = true;
b8f126a8 2058
ddda1ac1 2059 if (priv->id == ID_MT7530) {
ddda1ac1
GU		 2060 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
2061 ret = regulator_enable(priv->core_pwr);
2062 if (ret < 0) {
2063 dev_err(priv->dev,
2064 "Failed to enable core power: %d\n", ret);
2065 return ret;
2066 }
b8f126a8 2067
ddda1ac1
GU		 2068 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
2069 ret = regulator_enable(priv->io_pwr);
2070 if (ret < 0) {
2071 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
2072 ret);
2073 return ret;
2074 }
b8f126a8
SW		 2075 }
2076
2077 /* Reset whole chip through gpio pin or memory-mapped registers for
2078 * different type of hardware
2079 */
2080 if (priv->mcm) {
2081 reset_control_assert(priv->rstc);
2082 usleep_range(1000, 1100);
2083 reset_control_deassert(priv->rstc);
2084 } else {
2085 gpiod_set_value_cansleep(priv->reset, 0);
2086 usleep_range(1000, 1100);
2087 gpiod_set_value_cansleep(priv->reset, 1);
2088 }
2089
2090 /* Waiting for MT7530 got to stable */
2091 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2092 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2093 20, 1000000);
2094 if (ret < 0) {
2095 dev_err(priv->dev, "reset timeout\n");
2096 return ret;
2097 }
2098
2099 id = mt7530_read(priv, MT7530_CREV);
2100 id >>= CHIP_NAME_SHIFT;
2101 if (id != MT7530_ID) {
2102 dev_err(priv->dev, "chip %x can't be supported\n", id);
2103 return -ENODEV;
2104 }
2105
2106 /* Reset the switch through internal reset */
2107 mt7530_write(priv, MT7530_SYS_CTRL,
2108 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2109 SYS_CTRL_REG_RST);
2110
2111 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
2112 val = mt7530_read(priv, MT7530_MHWTRAP);
2113 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
2114 val |= MHWTRAP_MANUAL;
2115 mt7530_write(priv, MT7530_MHWTRAP, val);
2116
ca366d6c
RD		 2117 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2118
b8f126a8
SW		 2119 /* Enable and reset MIB counters */
2120 mt7530_mib_reset(ds);
2121
b8f126a8
SW		 2122 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2123 /* Disable forwarding by default on all ports */
2124 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2125 PCR_MATRIX_CLR);
2126
0ce0c3cd
AD		 2127 if (dsa_is_cpu_port(ds, i)) {
2128 ret = mt753x_cpu_port_enable(ds, i);
2129 if (ret)
2130 return ret;
5a30833b 2131 } else {
75104db0 2132 mt7530_port_disable(ds, i);
e045124e 2133
5a30833b
DQ		 2134 /* Disable learning by default on all user ports */
2135 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2136 }
e045124e
DQ		 2137 /* Enable consistent egress tag */
2138 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2139 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
b8f126a8
SW		 2140 }
2141
38f790a8
RD		 2142 /* Setup port 5 */
2143 priv->p5_intf_sel = P5_DISABLED;
2144 interface = PHY_INTERFACE_MODE_NA;
2145
2146 if (!dsa_is_unused_port(ds, 5)) {
2147 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
0c65b2b9
AL		 2148 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
2149 if (ret && ret != -ENODEV)
2150 return ret;
38f790a8
RD		 2151 } else {
2152 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
2153 for_each_child_of_node(dn, mac_np) {
2154 if (!of_device_is_compatible(mac_np,
2155 "mediatek,eth-mac"))
2156 continue;
2157
2158 ret = of_property_read_u32(mac_np, "reg", &id);
2159 if (ret < 0 || id != 1)
2160 continue;
2161
2162 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
0452800f
CG		 2163 if (!phy_node)
2164 continue;
2165
38f790a8 2166 if (phy_node->parent == priv->dev->of_node->parent) {
0c65b2b9 2167 ret = of_get_phy_mode(mac_np, &interface);
8e4efd47
SP		 2168 if (ret && ret != -ENODEV) {
2169 of_node_put(mac_np);
0c65b2b9 2170 return ret;
8e4efd47 2171 }
38f790a8
RD		 2172 id = of_mdio_parse_addr(ds->dev, phy_node);
2173 if (id == 0)
2174 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
2175 if (id == 4)
2176 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
2177 }
8e4efd47 2178 of_node_put(mac_np);
38f790a8
RD		 2179 of_node_put(phy_node);
2180 break;
2181 }
2182 }
2183
63c75c05 2184#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 2185 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
2186 ret = mt7530_setup_gpio(priv);
2187 if (ret)
2188 return ret;
2189 }
63c75c05 2190#endif /* CONFIG_GPIOLIB */
429a0ede 2191
38f790a8
RD		 2192 mt7530_setup_port5(ds, interface);
2193
b8f126a8 2194 /* Flush the FDB table */
18bd5949 2195 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 2196 if (ret < 0)
2197 return ret;
2198
2199 return 0;
2200}
2201
c288575f
LC		 2202static int
2203mt7531_setup(struct dsa_switch *ds)
2204{
2205 struct mt7530_priv *priv = ds->priv;
2206 struct mt7530_dummy_poll p;
2207 u32 val, id;
2208 int ret, i;
2209
2210 /* Reset whole chip through gpio pin or memory-mapped registers for
2211 * different type of hardware
2212 */
2213 if (priv->mcm) {
2214 reset_control_assert(priv->rstc);
2215 usleep_range(1000, 1100);
2216 reset_control_deassert(priv->rstc);
2217 } else {
2218 gpiod_set_value_cansleep(priv->reset, 0);
2219 usleep_range(1000, 1100);
2220 gpiod_set_value_cansleep(priv->reset, 1);
2221 }
2222
2223 /* Waiting for MT7530 got to stable */
2224 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2225 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2226 20, 1000000);
2227 if (ret < 0) {
2228 dev_err(priv->dev, "reset timeout\n");
2229 return ret;
2230 }
2231
2232 id = mt7530_read(priv, MT7531_CREV);
2233 id >>= CHIP_NAME_SHIFT;
2234
2235 if (id != MT7531_ID) {
2236 dev_err(priv->dev, "chip %x can't be supported\n", id);
2237 return -ENODEV;
2238 }
2239
2240 /* Reset the switch through internal reset */
2241 mt7530_write(priv, MT7530_SYS_CTRL,
2242 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2243 SYS_CTRL_REG_RST);
2244
2245 if (mt7531_dual_sgmii_supported(priv)) {
2246 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
2247
2248 /* Let ds->slave_mii_bus be able to access external phy. */
2249 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
2250 MT7531_EXT_P_MDC_11);
2251 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
2252 MT7531_EXT_P_MDIO_12);
2253 } else {
2254 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2255 }
2256 dev_dbg(ds->dev, "P5 support %s interface\n",
2257 p5_intf_modes(priv->p5_intf_sel));
2258
2259 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
2260 MT7531_GPIO0_INTERRUPT);
2261
2262 /* Let phylink decide the interface later. */
2263 priv->p5_interface = PHY_INTERFACE_MODE_NA;
2264 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2265
2266 /* Enable PHY core PLL, since phy_device has not yet been created
2267 * provided for phy_[read,write]_mmd_indirect is called, we provide
2268 * our own mt7531_ind_mmd_phy_[read,write] to complete this
2269 * function.
2270 */
2271 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
2272 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2273 val |= MT7531_PHY_PLL_BYPASS_MODE;
2274 val &= ~MT7531_PHY_PLL_OFF;
2275 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
2276 CORE_PLL_GROUP4, val);
2277
2278 /* BPDU to CPU port */
2279 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
2280 BIT(MT7530_CPU_PORT));
2281 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
2282 MT753X_BPDU_CPU_ONLY);
2283
2284 /* Enable and reset MIB counters */
2285 mt7530_mib_reset(ds);
2286
2287 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2288 /* Disable forwarding by default on all ports */
2289 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2290 PCR_MATRIX_CLR);
2291
2292 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
2293
0ce0c3cd
AD		 2294 if (dsa_is_cpu_port(ds, i)) {
2295 ret = mt753x_cpu_port_enable(ds, i);
2296 if (ret)
2297 return ret;
5a30833b 2298 } else {
c288575f
LC		 2299 mt7530_port_disable(ds, i);
2300
5a30833b
DQ		 2301 /* Disable learning by default on all user ports */
2302 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2303 }
2304
c288575f
LC		 2305 /* Enable consistent egress tag */
2306 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2307 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2308 }
2309
771c8901 2310 ds->mtu_enforcement_ingress = true;
c288575f
LC		 2311
2312 /* Flush the FDB table */
2313 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2314 if (ret < 0)
2315 return ret;
2316
2317 return 0;
2318}
2319
88bdef8b
LC		 2320static bool
2321mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
2322 const struct phylink_link_state *state)
ca366d6c
RD		 2323{
2324 struct mt7530_priv *priv = ds->priv;
ca366d6c
RD		 2325
2326 switch (port) {
88bdef8b 2327 case 0 ... 4: /* Internal phy */
ca366d6c 2328 if (state->interface != PHY_INTERFACE_MODE_GMII)
88bdef8b 2329 return false;
ca366d6c 2330 break;
38f790a8 2331 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
38f790a8
RD		 2332 if (!phy_interface_mode_is_rgmii(state->interface) &&
2333 state->interface != PHY_INTERFACE_MODE_MII &&
2334 state->interface != PHY_INTERFACE_MODE_GMII)
88bdef8b
LC		 2335 return false;
2336 break;
2337 case 6: /* 1st cpu port */
2338 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
2339 state->interface != PHY_INTERFACE_MODE_TRGMII)
2340 return false;
2341 break;
2342 default:
2343 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2344 port);
2345 return false;
2346 }
2347
2348 return true;
2349}
2350
c288575f
LC		 2351static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
2352{
2353 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
2354}
2355
2356static bool
2357mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
2358 const struct phylink_link_state *state)
2359{
2360 struct mt7530_priv *priv = ds->priv;
2361
2362 switch (port) {
2363 case 0 ... 4: /* Internal phy */
2364 if (state->interface != PHY_INTERFACE_MODE_GMII)
2365 return false;
2366 break;
2367 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
2368 if (mt7531_is_rgmii_port(priv, port))
2369 return phy_interface_mode_is_rgmii(state->interface);
2370 fallthrough;
2371 case 6: /* 1st cpu port supports sgmii/8023z only */
2372 if (state->interface != PHY_INTERFACE_MODE_SGMII &&
2373 !phy_interface_mode_is_8023z(state->interface))
2374 return false;
2375 break;
2376 default:
2377 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2378 port);
2379 return false;
2380 }
2381
2382 return true;
2383}
2384
88bdef8b
LC		 2385static bool
2386mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
2387 const struct phylink_link_state *state)
2388{
2389 struct mt7530_priv *priv = ds->priv;
2390
2391 return priv->info->phy_mode_supported(ds, port, state);
2392}
2393
2394static int
2395mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2396{
2397 struct mt7530_priv *priv = ds->priv;
2398
2399 return priv->info->pad_setup(ds, state->interface);
2400}
2401
2402static int
2403mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2404 phy_interface_t interface)
2405{
2406 struct mt7530_priv *priv = ds->priv;
2407
2408 /* Only need to setup port5. */
2409 if (port != 5)
2410 return 0;
2411
2412 mt7530_setup_port5(priv->ds, interface);
2413
2414 return 0;
2415}
2416
c288575f
LC		 2417static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2418 phy_interface_t interface,
2419 struct phy_device *phydev)
2420{
2421 u32 val;
2422
2423 if (!mt7531_is_rgmii_port(priv, port)) {
2424 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2425 port);
2426 return -EINVAL;
2427 }
2428
2429 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2430 val |= GP_CLK_EN;
2431 val &= ~GP_MODE_MASK;
2432 val |= GP_MODE(MT7531_GP_MODE_RGMII);
2433 val &= ~CLK_SKEW_IN_MASK;
2434 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2435 val &= ~CLK_SKEW_OUT_MASK;
2436 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2437 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2438
2439 /* Do not adjust rgmii delay when vendor phy driver presents. */
2440 if (!phydev || phy_driver_is_genphy(phydev)) {
2441 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2442 switch (interface) {
2443 case PHY_INTERFACE_MODE_RGMII:
2444 val |= TXCLK_NO_REVERSE;
2445 val |= RXCLK_NO_DELAY;
2446 break;
2447 case PHY_INTERFACE_MODE_RGMII_RXID:
2448 val |= TXCLK_NO_REVERSE;
2449 break;
2450 case PHY_INTERFACE_MODE_RGMII_TXID:
2451 val |= RXCLK_NO_DELAY;
2452 break;
2453 case PHY_INTERFACE_MODE_RGMII_ID:
2454 break;
2455 default:
2456 return -EINVAL;
2457 }
2458 }
2459 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2460
2461 return 0;
2462}
2463
2464static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
2465 unsigned long *supported)
2466{
2467 /* Port5 supports ethier RGMII or SGMII.
2468 * Port6 supports SGMII only.
2469 */
2470 switch (port) {
2471 case 5:
2472 if (mt7531_is_rgmii_port(priv, port))
2473 break;
2474 fallthrough;
2475 case 6:
2476 phylink_set(supported, 1000baseX_Full);
2477 phylink_set(supported, 2500baseX_Full);
2478 phylink_set(supported, 2500baseT_Full);
2479 }
2480}
2481
2482static void
2483mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
2484 unsigned int mode, phy_interface_t interface,
2485 int speed, int duplex)
2486{
2487 struct mt7530_priv *priv = ds->priv;
2488 unsigned int val;
2489
2490 /* For adjusting speed and duplex of SGMII force mode. */
2491 if (interface != PHY_INTERFACE_MODE_SGMII ||
2492 phylink_autoneg_inband(mode))
2493 return;
2494
2495 /* SGMII force mode setting */
2496 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
2497 val &= ~MT7531_SGMII_IF_MODE_MASK;
2498
2499 switch (speed) {
2500 case SPEED_10:
2501 val |= MT7531_SGMII_FORCE_SPEED_10;
2502 break;
2503 case SPEED_100:
2504 val |= MT7531_SGMII_FORCE_SPEED_100;
2505 break;
2506 case SPEED_1000:
2507 val |= MT7531_SGMII_FORCE_SPEED_1000;
2508 break;
2509 }
2510
2511 /* MT7531 SGMII 1G force mode can only work in full duplex mode,
2512 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2513 */
2514 if ((speed == SPEED_10 || speed == SPEED_100) &&
2515 duplex != DUPLEX_FULL)
2516 val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2517
2518 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2519}
2520
2521static bool mt753x_is_mac_port(u32 port)
2522{
2523 return (port == 5 || port == 6);
2524}
2525
2526static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2527 phy_interface_t interface)
2528{
2529 u32 val;
2530
2531 if (!mt753x_is_mac_port(port))
2532 return -EINVAL;
2533
2534 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2535 MT7531_SGMII_PHYA_PWD);
2536
2537 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2538 val &= ~MT7531_RG_TPHY_SPEED_MASK;
2539 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2540 * encoding.
2541 */
2542 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2543 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2544 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2545
2546 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2547
2548 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2549 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2550 */
2551 mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2552 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2553 MT7531_SGMII_FORCE_SPEED_1000);
2554
2555 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2556
2557 return 0;
2558}
2559
2560static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2561 phy_interface_t interface)
2562{
2563 if (!mt753x_is_mac_port(port))
2564 return -EINVAL;
2565
2566 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2567 MT7531_SGMII_PHYA_PWD);
2568
2569 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2570 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2571
2572 mt7530_set(priv, MT7531_SGMII_MODE(port),
2573 MT7531_SGMII_REMOTE_FAULT_DIS |
2574 MT7531_SGMII_SPEED_DUPLEX_AN);
2575
2576 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2577 MT7531_SGMII_TX_CONFIG_MASK, 1);
2578
2579 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2580
2581 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2582
2583 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2584
2585 return 0;
2586}
2587
2588static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
2589{
2590 struct mt7530_priv *priv = ds->priv;
2591 u32 val;
2592
2593 /* Only restart AN when AN is enabled */
2594 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2595 if (val & MT7531_SGMII_AN_ENABLE) {
2596 val |= MT7531_SGMII_AN_RESTART;
2597 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2598 }
2599}
2600
2601static int
2602mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2603 phy_interface_t interface)
2604{
2605 struct mt7530_priv *priv = ds->priv;
2606 struct phy_device *phydev;
2607 struct dsa_port *dp;
2608
2609 if (!mt753x_is_mac_port(port)) {
2610 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2611 return -EINVAL;
2612 }
2613
2614 switch (interface) {
2615 case PHY_INTERFACE_MODE_RGMII:
2616 case PHY_INTERFACE_MODE_RGMII_ID:
2617 case PHY_INTERFACE_MODE_RGMII_RXID:
2618 case PHY_INTERFACE_MODE_RGMII_TXID:
2619 dp = dsa_to_port(ds, port);
2620 phydev = dp->slave->phydev;
2621 return mt7531_rgmii_setup(priv, port, interface, phydev);
2622 case PHY_INTERFACE_MODE_SGMII:
2623 return mt7531_sgmii_setup_mode_an(priv, port, interface);
2624 case PHY_INTERFACE_MODE_NA:
2625 case PHY_INTERFACE_MODE_1000BASEX:
2626 case PHY_INTERFACE_MODE_2500BASEX:
2627 if (phylink_autoneg_inband(mode))
2628 return -EINVAL;
2629
2630 return mt7531_sgmii_setup_mode_force(priv, port, interface);
2631 default:
2632 return -EINVAL;
2633 }
2634
2635 return -EINVAL;
2636}
2637
88bdef8b
LC		 2638static int
2639mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2640 const struct phylink_link_state *state)
2641{
2642 struct mt7530_priv *priv = ds->priv;
2643
2644 return priv->info->mac_port_config(ds, port, mode, state->interface);
2645}
2646
2647static void
2648mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2649 const struct phylink_link_state *state)
2650{
2651 struct mt7530_priv *priv = ds->priv;
2652 u32 mcr_cur, mcr_new;
2653
2654 if (!mt753x_phy_mode_supported(ds, port, state))
2655 goto unsupported;
2656
2657 switch (port) {
2658 case 0 ... 4: /* Internal phy */
2659 if (state->interface != PHY_INTERFACE_MODE_GMII)
2660 goto unsupported;
2661 break;
2662 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2663 if (priv->p5_interface == state->interface)
2664 break;
2665
2666 if (mt753x_mac_config(ds, port, mode, state) < 0)
2667 goto unsupported;
38f790a8 2668
c288575f
LC		 2669 if (priv->p5_intf_sel != P5_DISABLED)
2670 priv->p5_interface = state->interface;
38f790a8 2671 break;
ca366d6c
RD		 2672 case 6: /* 1st cpu port */
2673 if (priv->p6_interface == state->interface)
2674 break;
2675
88bdef8b 2676 mt753x_pad_setup(ds, state);
ca366d6c 2677
88bdef8b
LC		 2678 if (mt753x_mac_config(ds, port, mode, state) < 0)
2679 goto unsupported;
ca366d6c 2680
ca366d6c
RD		 2681 priv->p6_interface = state->interface;
2682 break;
2683 default:
88bdef8b
LC		 2684unsupported:
2685 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2686 __func__, phy_modes(state->interface), port);
ca366d6c
RD		 2687 return;
2688 }
2689
c288575f
LC		 2690 if (phylink_autoneg_inband(mode) &&
2691 state->interface != PHY_INTERFACE_MODE_SGMII) {
ca366d6c
RD		 2692 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
2693 __func__);
2694 return;
2695 }
2696
2697 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2698 mcr_new = mcr_cur;
1d01145f 2699 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
ca366d6c 2700 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
c288575f 2701 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
ca366d6c 2702
38f790a8
RD		 2703 /* Are we connected to external phy */
2704 if (port == 5 && dsa_is_user_port(ds, 5))
2705 mcr_new |= PMCR_EXT_PHY;
2706
ca366d6c
RD		 2707 if (mcr_new != mcr_cur)
2708 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2709}
2710
c288575f
LC		 2711static void
2712mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
2713{
2714 struct mt7530_priv *priv = ds->priv;
2715
2716 if (!priv->info->mac_pcs_an_restart)
2717 return;
2718
2719 priv->info->mac_pcs_an_restart(ds, port);
2720}
2721
2722static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
ca366d6c
RD		 2723 unsigned int mode,
2724 phy_interface_t interface)
2725{
2726 struct mt7530_priv *priv = ds->priv;
2727
1d01145f 2728 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
ca366d6c
RD		 2729}
2730
c288575f
LC		 2731static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
2732 unsigned int mode, phy_interface_t interface,
2733 int speed, int duplex)
2734{
2735 struct mt7530_priv *priv = ds->priv;
2736
2737 if (!priv->info->mac_pcs_link_up)
2738 return;
2739
2740 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2741}
2742
2743static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
ca366d6c
RD		 2744 unsigned int mode,
2745 phy_interface_t interface,
5b502a7b
RK		 2746 struct phy_device *phydev,
2747 int speed, int duplex,
2748 bool tx_pause, bool rx_pause)
ca366d6c
RD		 2749{
2750 struct mt7530_priv *priv = ds->priv;
1d01145f
RD		 2751 u32 mcr;
2752
c288575f
LC		 2753 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2754
1d01145f
RD		 2755 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2756
c288575f
LC		 2757 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2758 * variants.
2759 */
2760 if (interface == PHY_INTERFACE_MODE_TRGMII ||
2761 (phy_interface_mode_is_8023z(interface))) {
2762 speed = SPEED_1000;
2763 duplex = DUPLEX_FULL;
2764 }
2765
1d01145f
RD		 2766 switch (speed) {
2767 case SPEED_1000:
2768 mcr |= PMCR_FORCE_SPEED_1000;
2769 break;
2770 case SPEED_100:
2771 mcr |= PMCR_FORCE_SPEED_100;
2772 break;
2773 }
2774 if (duplex == DUPLEX_FULL) {
2775 mcr |= PMCR_FORCE_FDX;
2776 if (tx_pause)
2777 mcr |= PMCR_TX_FC_EN;
2778 if (rx_pause)
2779 mcr |= PMCR_RX_FC_EN;
2780 }
ca366d6c 2781
40b5d2f1
RD		 2782 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) {
2783 switch (speed) {
2784 case SPEED_1000:
2785 mcr |= PMCR_FORCE_EEE1G;
2786 break;
2787 case SPEED_100:
2788 mcr |= PMCR_FORCE_EEE100;
2789 break;
2790 }
2791 }
2792
1d01145f 2793 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
ca366d6c
RD		 2794}
2795
c288575f
LC		 2796static int
2797mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2798{
2799 struct mt7530_priv *priv = ds->priv;
2800 phy_interface_t interface;
2801 int speed;
0ce0c3cd 2802 int ret;
c288575f
LC		 2803
2804 switch (port) {
2805 case 5:
2806 if (mt7531_is_rgmii_port(priv, port))
2807 interface = PHY_INTERFACE_MODE_RGMII;
2808 else
2809 interface = PHY_INTERFACE_MODE_2500BASEX;
2810
2811 priv->p5_interface = interface;
2812 break;
2813 case 6:
2814 interface = PHY_INTERFACE_MODE_2500BASEX;
2815
2816 mt7531_pad_setup(ds, interface);
2817
2818 priv->p6_interface = interface;
2819 break;
0ce0c3cd
AD		 2820 default:
2821 return -EINVAL;
c288575f
LC		 2822 }
2823
2824 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2825 speed = SPEED_2500;
2826 else
2827 speed = SPEED_1000;
2828
0ce0c3cd
AD		 2829 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2830 if (ret)
2831 return ret;
c288575f
LC		 2832 mt7530_write(priv, MT7530_PMCR_P(port),
2833 PMCR_CPU_PORT_SETTING(priv->id));
2834 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2835 speed, DUPLEX_FULL, true, true);
2836
2837 return 0;
2838}
2839
88bdef8b
LC		 2840static void
2841mt7530_mac_port_validate(struct dsa_switch *ds, int port,
2842 unsigned long *supported)
2843{
2844 if (port == 5)
2845 phylink_set(supported, 1000baseX_Full);
2846}
2847
c288575f
LC		 2848static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
2849 unsigned long *supported)
2850{
2851 struct mt7530_priv *priv = ds->priv;
2852
2853 mt7531_sgmii_validate(priv, port, supported);
2854}
2855
88bdef8b
LC		 2856static void
2857mt753x_phylink_validate(struct dsa_switch *ds, int port,
2858 unsigned long *supported,
2859 struct phylink_link_state *state)
ca366d6c
RD		 2860{
2861 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
88bdef8b 2862 struct mt7530_priv *priv = ds->priv;
ca366d6c 2863
88bdef8b
LC		 2864 if (state->interface != PHY_INTERFACE_MODE_NA &&
2865 !mt753x_phy_mode_supported(ds, port, state)) {
ca366d6c
RD		 2866 linkmode_zero(supported);
2867 return;
2868 }
2869
2870 phylink_set_port_modes(mask);
ca366d6c 2871
c288575f
LC		 2872 if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
2873 !phy_interface_mode_is_8023z(state->interface)) {
ca366d6c
RD		 2874 phylink_set(mask, 10baseT_Half);
2875 phylink_set(mask, 10baseT_Full);
2876 phylink_set(mask, 100baseT_Half);
2877 phylink_set(mask, 100baseT_Full);
88bdef8b 2878 phylink_set(mask, Autoneg);
38f790a8 2879 }
ca366d6c 2880
88bdef8b
LC		 2881 /* This switch only supports 1G full-duplex. */
2882 if (state->interface != PHY_INTERFACE_MODE_MII)
2883 phylink_set(mask, 1000baseT_Full);
2884
2885 priv->info->mac_port_validate(ds, port, mask);
2886
ca366d6c
RD		 2887 phylink_set(mask, Pause);
2888 phylink_set(mask, Asym_Pause);
2889
2890 linkmode_and(supported, supported, mask);
2891 linkmode_and(state->advertising, state->advertising, mask);
c288575f
LC		 2892
2893 /* We can only operate at 2500BaseX or 1000BaseX. If requested
2894 * to advertise both, only report advertising at 2500BaseX.
2895 */
2896 phylink_helper_basex_speed(state);
ca366d6c
RD		 2897}
2898
2899static int
2900mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
2901 struct phylink_link_state *state)
2902{
2903 struct mt7530_priv *priv = ds->priv;
2904 u32 pmsr;
2905
2906 if (port < 0 || port >= MT7530_NUM_PORTS)
2907 return -EINVAL;
2908
2909 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2910
2911 state->link = (pmsr & PMSR_LINK);
2912 state->an_complete = state->link;
2913 state->duplex = !!(pmsr & PMSR_DPX);
2914
2915 switch (pmsr & PMSR_SPEED_MASK) {
2916 case PMSR_SPEED_10:
2917 state->speed = SPEED_10;
2918 break;
2919 case PMSR_SPEED_100:
2920 state->speed = SPEED_100;
2921 break;
2922 case PMSR_SPEED_1000:
2923 state->speed = SPEED_1000;
2924 break;
2925 default:
2926 state->speed = SPEED_UNKNOWN;
2927 break;
2928 }
2929
2930 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2931 if (pmsr & PMSR_RX_FC)
2932 state->pause |= MLO_PAUSE_RX;
2933 if (pmsr & PMSR_TX_FC)
2934 state->pause |= MLO_PAUSE_TX;
2935
2936 return 1;
2937}
2938
c288575f
LC		 2939static int
2940mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
2941 struct phylink_link_state *state)
2942{
2943 u32 status, val;
2944 u16 config_reg;
2945
2946 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2947 state->link = !!(status & MT7531_SGMII_LINK_STATUS);
2948 if (state->interface == PHY_INTERFACE_MODE_SGMII &&
2949 (status & MT7531_SGMII_AN_ENABLE)) {
2950 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
2951 config_reg = val >> 16;
2952
2953 switch (config_reg & LPA_SGMII_SPD_MASK) {
2954 case LPA_SGMII_1000:
2955 state->speed = SPEED_1000;
2956 break;
2957 case LPA_SGMII_100:
2958 state->speed = SPEED_100;
2959 break;
2960 case LPA_SGMII_10:
2961 state->speed = SPEED_10;
2962 break;
2963 default:
2964 dev_err(priv->dev, "invalid sgmii PHY speed\n");
2965 state->link = false;
2966 return -EINVAL;
2967 }
2968
2969 if (config_reg & LPA_SGMII_FULL_DUPLEX)
2970 state->duplex = DUPLEX_FULL;
2971 else
2972 state->duplex = DUPLEX_HALF;
2973 }
2974
2975 return 0;
2976}
2977
2978static int
2979mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
2980 struct phylink_link_state *state)
2981{
2982 struct mt7530_priv *priv = ds->priv;
2983
2984 if (state->interface == PHY_INTERFACE_MODE_SGMII)
2985 return mt7531_sgmii_pcs_get_state_an(priv, port, state);
2986
2987 return -EOPNOTSUPP;
2988}
2989
88bdef8b
LC		 2990static int
2991mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
2992 struct phylink_link_state *state)
2993{
2994 struct mt7530_priv *priv = ds->priv;
2995
2996 return priv->info->mac_port_get_state(ds, port, state);
2997}
2998
2999static int
3000mt753x_setup(struct dsa_switch *ds)
3001{
3002 struct mt7530_priv *priv = ds->priv;
ba751e28 3003 int ret = priv->info->sw_setup(ds);
88bdef8b 3004
ba751e28
DQ		 3005 if (ret)
3006 return ret;
88bdef8b 3007
ba751e28
DQ		 3008 ret = mt7530_setup_irq(priv);
3009 if (ret)
3010 return ret;
88bdef8b 3011
ba751e28
DQ		 3012 ret = mt7530_setup_mdio(priv);
3013 if (ret && priv->irq)
3014 mt7530_free_irq_common(priv);
88bdef8b 3015
ba751e28 3016 return ret;
88bdef8b
LC		 3017}
3018
40b5d2f1
RD		 3019static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,
3020 struct ethtool_eee *e)
3021{
3022 struct mt7530_priv *priv = ds->priv;
3023 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
3024
3025 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
3026 e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
3027
3028 return 0;
3029}
3030
3031static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
3032 struct ethtool_eee *e)
3033{
3034 struct mt7530_priv *priv = ds->priv;
3035 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;
3036
3037 if (e->tx_lpi_timer > 0xFFF)
3038 return -EINVAL;
3039
3040 set = SET_LPI_THRESH(e->tx_lpi_timer);
3041 if (!e->tx_lpi_enabled)
3042 /* Force LPI Mode without a delay */
3043 set |= LPI_MODE_EN;
3044 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
3045
3046 return 0;
3047}
3048
d78d6776 3049static const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8 3050 .get_tag_protocol = mtk_get_tag_protocol,
88bdef8b 3051 .setup = mt753x_setup,
b8f126a8 3052 .get_strings = mt7530_get_strings,
b8f126a8
SW		 3053 .get_ethtool_stats = mt7530_get_ethtool_stats,
3054 .get_sset_count = mt7530_get_sset_count,
ea6d5c92 3055 .set_ageing_time = mt7530_set_ageing_time,
b8f126a8
SW		 3056 .port_enable = mt7530_port_enable,
3057 .port_disable = mt7530_port_disable,
9470174e
DQ		 3058 .port_change_mtu = mt7530_port_change_mtu,
3059 .port_max_mtu = mt7530_port_max_mtu,
b8f126a8 3060 .port_stp_state_set = mt7530_stp_state_set,
5a30833b
DQ		 3061 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags,
3062 .port_bridge_flags = mt7530_port_bridge_flags,
3063 .port_set_mrouter = mt7530_port_set_mrouter,
b8f126a8
SW		 3064 .port_bridge_join = mt7530_port_bridge_join,
3065 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 3066 .port_fdb_add = mt7530_port_fdb_add,
3067 .port_fdb_del = mt7530_port_fdb_del,
3068 .port_fdb_dump = mt7530_port_fdb_dump,
5a30833b
DQ		 3069 .port_mdb_add = mt7530_port_mdb_add,
3070 .port_mdb_del = mt7530_port_mdb_del,
83163f7d 3071 .port_vlan_filtering = mt7530_port_vlan_filtering,
83163f7d
SW		 3072 .port_vlan_add = mt7530_port_vlan_add,
3073 .port_vlan_del = mt7530_port_vlan_del,
c288575f
LC		 3074 .port_mirror_add = mt753x_port_mirror_add,
3075 .port_mirror_del = mt753x_port_mirror_del,
88bdef8b
LC		 3076 .phylink_validate = mt753x_phylink_validate,
3077 .phylink_mac_link_state = mt753x_phylink_mac_link_state,
3078 .phylink_mac_config = mt753x_phylink_mac_config,
c288575f
LC		 3079 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
3080 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
3081 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
40b5d2f1
RD		 3082 .get_mac_eee = mt753x_get_mac_eee,
3083 .set_mac_eee = mt753x_set_mac_eee,
b8f126a8
SW		 3084};
3085
88bdef8b
LC		 3086static const struct mt753x_info mt753x_table[] = {
3087 [ID_MT7621] = {
3088 .id = ID_MT7621,
3089 .sw_setup = mt7530_setup,
3090 .phy_read = mt7530_phy_read,
3091 .phy_write = mt7530_phy_write,
3092 .pad_setup = mt7530_pad_clk_setup,
3093 .phy_mode_supported = mt7530_phy_mode_supported,
3094 .mac_port_validate = mt7530_mac_port_validate,
3095 .mac_port_get_state = mt7530_phylink_mac_link_state,
3096 .mac_port_config = mt7530_mac_config,
3097 },
3098 [ID_MT7530] = {
3099 .id = ID_MT7530,
3100 .sw_setup = mt7530_setup,
3101 .phy_read = mt7530_phy_read,
3102 .phy_write = mt7530_phy_write,
3103 .pad_setup = mt7530_pad_clk_setup,
3104 .phy_mode_supported = mt7530_phy_mode_supported,
3105 .mac_port_validate = mt7530_mac_port_validate,
3106 .mac_port_get_state = mt7530_phylink_mac_link_state,
3107 .mac_port_config = mt7530_mac_config,
3108 },
c288575f
LC		 3109 [ID_MT7531] = {
3110 .id = ID_MT7531,
3111 .sw_setup = mt7531_setup,
3112 .phy_read = mt7531_ind_phy_read,
3113 .phy_write = mt7531_ind_phy_write,
3114 .pad_setup = mt7531_pad_setup,
3115 .cpu_port_config = mt7531_cpu_port_config,
3116 .phy_mode_supported = mt7531_phy_mode_supported,
3117 .mac_port_validate = mt7531_mac_port_validate,
3118 .mac_port_get_state = mt7531_phylink_mac_link_state,
3119 .mac_port_config = mt7531_mac_config,
3120 .mac_pcs_an_restart = mt7531_sgmii_restart_an,
3121 .mac_pcs_link_up = mt7531_sgmii_link_up_force,
3122 },
88bdef8b
LC		 3123};
3124
ddda1ac1 3125static const struct of_device_id mt7530_of_match[] = {
88bdef8b
LC		 3126 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
3127 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
c288575f 3128 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
ddda1ac1
GU		 3129 { /* sentinel */ },
3130};
3131MODULE_DEVICE_TABLE(of, mt7530_of_match);
3132
b8f126a8
SW		 3133static int
3134mt7530_probe(struct mdio_device *mdiodev)
3135{
3136 struct mt7530_priv *priv;
3137 struct device_node *dn;
3138
3139 dn = mdiodev->dev.of_node;
3140
3141 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
3142 if (!priv)
3143 return -ENOMEM;
3144
7e99e347 3145 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
b8f126a8
SW		 3146 if (!priv->ds)
3147 return -ENOMEM;
3148
7e99e347
VD		 3149 priv->ds->dev = &mdiodev->dev;
3150 priv->ds->num_ports = DSA_MAX_PORTS;
3151
b8f126a8
SW		 3152 /* Use medatek,mcm property to distinguish hardware type that would
3153 * casues a little bit differences on power-on sequence.
3154 */
3155 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
3156 if (priv->mcm) {
3157 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
3158
3159 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
3160 if (IS_ERR(priv->rstc)) {
3161 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3162 return PTR_ERR(priv->rstc);
3163 }
3164 }
3165
ddda1ac1
GU		 3166 /* Get the hardware identifier from the devicetree node.
3167 * We will need it for some of the clock and regulator setup.
3168 */
88bdef8b
LC		 3169 priv->info = of_device_get_match_data(&mdiodev->dev);
3170 if (!priv->info)
3171 return -EINVAL;
3172
3173 /* Sanity check if these required device operations are filled
3174 * properly.
3175 */
3176 if (!priv->info->sw_setup || !priv->info->pad_setup ||
3177 !priv->info->phy_read || !priv->info->phy_write ||
3178 !priv->info->phy_mode_supported ||
3179 !priv->info->mac_port_validate ||
3180 !priv->info->mac_port_get_state || !priv->info->mac_port_config)
3181 return -EINVAL;
3182
3183 priv->id = priv->info->id;
b8f126a8 3184
ddda1ac1
GU		 3185 if (priv->id == ID_MT7530) {
3186 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
3187 if (IS_ERR(priv->core_pwr))
3188 return PTR_ERR(priv->core_pwr);
3189
3190 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
3191 if (IS_ERR(priv->io_pwr))
3192 return PTR_ERR(priv->io_pwr);
3193 }
b8f126a8
SW		 3194
3195 /* Not MCM that indicates switch works as the remote standalone
3196 * integrated circuit so the GPIO pin would be used to complete
3197 * the reset, otherwise memory-mapped register accessing used
3198 * through syscon provides in the case of MCM.
3199 */
3200 if (!priv->mcm) {
3201 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
3202 GPIOD_OUT_LOW);
3203 if (IS_ERR(priv->reset)) {
3204 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3205 return PTR_ERR(priv->reset);
3206 }
3207 }
3208
3209 priv->bus = mdiodev->bus;
3210 priv->dev = &mdiodev->dev;
3211 priv->ds->priv = priv;
3212 priv->ds->ops = &mt7530_switch_ops;
3213 mutex_init(&priv->reg_mutex);
3214 dev_set_drvdata(&mdiodev->dev, priv);
3215
23c9ee49 3216 return dsa_register_switch(priv->ds);
b8f126a8
SW		 3217}
3218
3219static void
3220mt7530_remove(struct mdio_device *mdiodev)
3221{
3222 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3223 int ret = 0;
3224
3225 ret = regulator_disable(priv->core_pwr);
3226 if (ret < 0)
3227 dev_err(priv->dev,
3228 "Failed to disable core power: %d\n", ret);
3229
3230 ret = regulator_disable(priv->io_pwr);
3231 if (ret < 0)
3232 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
3233 ret);
3234
ba751e28
DQ		 3235 if (priv->irq)
3236 mt7530_free_irq(priv);
3237
b8f126a8
SW		 3238 dsa_unregister_switch(priv->ds);
3239 mutex_destroy(&priv->reg_mutex);
3240}
3241
b8f126a8
SW		 3242static struct mdio_driver mt7530_mdio_driver = {
3243 .probe = mt7530_probe,
3244 .remove = mt7530_remove,
3245 .mdiodrv.driver = {
3246 .name = "mt7530",
3247 .of_match_table = mt7530_of_match,
3248 },
3249};
3250
3251mdio_module_driver(mt7530_mdio_driver);
3252
3253MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
3254MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
3255MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)