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net: dsa: mt7530: fix handling of LLDP frames
[linux-block.git] / drivers / net / dsa / mt7530.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
b8f126a8
SW		 2/*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
b8f126a8
SW		 5 */
6#include <linux/etherdevice.h>
7#include <linux/if_bridge.h>
8#include <linux/iopoll.h>
9#include <linux/mdio.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
ba751e28 13#include <linux/of_irq.h>
b8f126a8
SW		 14#include <linux/of_mdio.h>
15#include <linux/of_net.h>
16#include <linux/of_platform.h>
ca366d6c 17#include <linux/phylink.h>
b8f126a8
SW		 18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
eb976a55 21#include <linux/gpio/consumer.h>
429a0ede 22#include <linux/gpio/driver.h>
b8f126a8 23#include <net/dsa.h>
b8f126a8
SW		 24
25#include "mt7530.h"
26
cbd1f243
RKO		 27static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
28{
29 return container_of(pcs, struct mt753x_pcs, pcs);
30}
31
b8f126a8
SW		 32/* String, offset, and register size in bytes if different from 4 bytes */
33static const struct mt7530_mib_desc mt7530_mib[] = {
34 MIB_DESC(1, 0x00, "TxDrop"),
35 MIB_DESC(1, 0x04, "TxCrcErr"),
36 MIB_DESC(1, 0x08, "TxUnicast"),
37 MIB_DESC(1, 0x0c, "TxMulticast"),
38 MIB_DESC(1, 0x10, "TxBroadcast"),
39 MIB_DESC(1, 0x14, "TxCollision"),
40 MIB_DESC(1, 0x18, "TxSingleCollision"),
41 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
42 MIB_DESC(1, 0x20, "TxDeferred"),
43 MIB_DESC(1, 0x24, "TxLateCollision"),
44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
45 MIB_DESC(1, 0x2c, "TxPause"),
46 MIB_DESC(1, 0x30, "TxPktSz64"),
47 MIB_DESC(1, 0x34, "TxPktSz65To127"),
48 MIB_DESC(1, 0x38, "TxPktSz128To255"),
49 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
50 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
51 MIB_DESC(1, 0x44, "Tx1024ToMax"),
52 MIB_DESC(2, 0x48, "TxBytes"),
53 MIB_DESC(1, 0x60, "RxDrop"),
54 MIB_DESC(1, 0x64, "RxFiltering"),
aff51c5d 55 MIB_DESC(1, 0x68, "RxUnicast"),
b8f126a8
SW		 56 MIB_DESC(1, 0x6c, "RxMulticast"),
57 MIB_DESC(1, 0x70, "RxBroadcast"),
58 MIB_DESC(1, 0x74, "RxAlignErr"),
59 MIB_DESC(1, 0x78, "RxCrcErr"),
60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
61 MIB_DESC(1, 0x80, "RxFragErr"),
62 MIB_DESC(1, 0x84, "RxOverSzErr"),
63 MIB_DESC(1, 0x88, "RxJabberErr"),
64 MIB_DESC(1, 0x8c, "RxPause"),
65 MIB_DESC(1, 0x90, "RxPktSz64"),
66 MIB_DESC(1, 0x94, "RxPktSz65To127"),
67 MIB_DESC(1, 0x98, "RxPktSz128To255"),
68 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
71 MIB_DESC(2, 0xa8, "RxBytes"),
72 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
73 MIB_DESC(1, 0xb4, "RxIngressDrop"),
74 MIB_DESC(1, 0xb8, "RxArlDrop"),
75};
76
4732315c
IL		 77/* Since phy_device has not yet been created and
78 * phy_{read,write}_mmd_indirect is not available, we provide our own
79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
80 * to complete this function.
81 */
b8f126a8
SW		 82static int
83core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
84{
85 struct mii_bus *bus = priv->bus;
86 int value, ret;
87
88 /* Write the desired MMD Devad */
89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
90 if (ret < 0)
91 goto err;
92
93 /* Write the desired MMD register address */
94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
95 if (ret < 0)
96 goto err;
97
98 /* Select the Function : DATA with no post increment */
99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
100 if (ret < 0)
101 goto err;
102
103 /* Read the content of the MMD's selected register */
104 value = bus->read(bus, 0, MII_MMD_DATA);
105
106 return value;
107err:
108 dev_err(&bus->dev, "failed to read mmd register\n");
109
110 return ret;
111}
112
113static int
114core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
115 int devad, u32 data)
116{
117 struct mii_bus *bus = priv->bus;
118 int ret;
119
120 /* Write the desired MMD Devad */
121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
122 if (ret < 0)
123 goto err;
124
125 /* Write the desired MMD register address */
126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
127 if (ret < 0)
128 goto err;
129
130 /* Select the Function : DATA with no post increment */
131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
132 if (ret < 0)
133 goto err;
134
135 /* Write the data into MMD's selected register */
136 ret = bus->write(bus, 0, MII_MMD_DATA, data);
137err:
138 if (ret < 0)
139 dev_err(&bus->dev,
140 "failed to write mmd register\n");
141 return ret;
142}
143
144static void
1557c679 145mt7530_mutex_lock(struct mt7530_priv *priv)
b8f126a8 146{
54d4147a
DG		 147 if (priv->bus)
148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1557c679 149}
b8f126a8 150
1557c679
DG		 151static void
152mt7530_mutex_unlock(struct mt7530_priv *priv)
153{
54d4147a
DG		 154 if (priv->bus)
155 mutex_unlock(&priv->bus->mdio_lock);
1557c679
DG		 156}
157
158static void
159core_write(struct mt7530_priv *priv, u32 reg, u32 val)
160{
161 mt7530_mutex_lock(priv);
b8f126a8
SW		 162
163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
164
1557c679 165 mt7530_mutex_unlock(priv);
b8f126a8
SW		 166}
167
168static void
169core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
170{
b8f126a8
SW		 171 u32 val;
172
1557c679 173 mt7530_mutex_lock(priv);
b8f126a8
SW		 174
175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
176 val &= ~mask;
177 val |= set;
178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
179
1557c679 180 mt7530_mutex_unlock(priv);
b8f126a8
SW		 181}
182
183static void
184core_set(struct mt7530_priv *priv, u32 reg, u32 val)
185{
186 core_rmw(priv, reg, 0, val);
187}
188
189static void
190core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
191{
192 core_rmw(priv, reg, val, 0);
193}
194
a08c0455
DG		 195static int
196mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
197{
198 int ret;
199
200 ret = regmap_write(priv->regmap, reg, val);
201
b8f126a8 202 if (ret < 0)
a08c0455 203 dev_err(priv->dev,
b8f126a8 204 "failed to write mt7530 register\n");
a08c0455 205
b8f126a8
SW		 206 return ret;
207}
208
a08c0455
DG		 209static u32
210mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
211{
212 int ret;
213 u32 val;
214
215 ret = regmap_read(priv->regmap, reg, &val);
216 if (ret) {
b6f56cdd 217 WARN_ON_ONCE(1);
a08c0455 218 dev_err(priv->dev,
b8f126a8 219 "failed to read mt7530 register\n");
b6f56cdd 220 return 0;
b8f126a8
SW		 221 }
222
a08c0455 223 return val;
b8f126a8
SW		 224}
225
226static void
227mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
228{
1557c679 229 mt7530_mutex_lock(priv);
b8f126a8
SW		 230
231 mt7530_mii_write(priv, reg, val);
232
1557c679 233 mt7530_mutex_unlock(priv);
b8f126a8
SW		 234}
235
c288575f
LC		 236static u32
237_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
238{
239 return mt7530_mii_read(p->priv, p->reg);
240}
241
b8f126a8
SW		 242static u32
243_mt7530_read(struct mt7530_dummy_poll *p)
244{
b8f126a8
SW		 245 u32 val;
246
1557c679 247 mt7530_mutex_lock(p->priv);
b8f126a8
SW		 248
249 val = mt7530_mii_read(p->priv, p->reg);
250
1557c679 251 mt7530_mutex_unlock(p->priv);
b8f126a8
SW		 252
253 return val;
254}
255
256static u32
257mt7530_read(struct mt7530_priv *priv, u32 reg)
258{
259 struct mt7530_dummy_poll p;
260
261 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
262 return _mt7530_read(&p);
263}
264
265static void
266mt7530_rmw(struct mt7530_priv *priv, u32 reg,
267 u32 mask, u32 set)
268{
1557c679 269 mt7530_mutex_lock(priv);
b8f126a8 270
a08c0455 271 regmap_update_bits(priv->regmap, reg, mask, set);
b8f126a8 272
1557c679 273 mt7530_mutex_unlock(priv);
b8f126a8
SW		 274}
275
276static void
277mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
278{
a08c0455 279 mt7530_rmw(priv, reg, val, val);
b8f126a8
SW		 280}
281
282static void
283mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
284{
285 mt7530_rmw(priv, reg, val, 0);
286}
287
288static int
289mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
290{
291 u32 val;
292 int ret;
293 struct mt7530_dummy_poll p;
294
295 /* Set the command operating upon the MAC address entries */
296 val = ATC_BUSY | ATC_MAT(0) | cmd;
297 mt7530_write(priv, MT7530_ATC, val);
298
299 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
300 ret = readx_poll_timeout(_mt7530_read, &p, val,
301 !(val & ATC_BUSY), 20, 20000);
302 if (ret < 0) {
303 dev_err(priv->dev, "reset timeout\n");
304 return ret;
305 }
306
307 /* Additional sanity for read command if the specified
308 * entry is invalid
309 */
310 val = mt7530_read(priv, MT7530_ATC);
311 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
312 return -EINVAL;
313
314 if (rsp)
315 *rsp = val;
316
317 return 0;
318}
319
320static void
321mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
322{
323 u32 reg[3];
324 int i;
325
326 /* Read from ARL table into an array */
327 for (i = 0; i < 3; i++) {
328 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
329
330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
331 __func__, __LINE__, i, reg[i]);
332 }
333
334 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
344}
345
346static void
347mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
348 u8 port_mask, const u8 *mac,
349 u8 aging, u8 type)
350{
351 u32 reg[3] = { 0 };
352 int i;
353
354 reg[1] |= vid & CVID_MASK;
73c447ca
DQ		 355 reg[1] |= ATA2_IVL;
356 reg[1] |= ATA2_FID(FID_BRIDGED);
b8f126a8
SW		 357 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
358 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
359 /* STATIC_ENT indicate that entry is static wouldn't
360 * be aged out and STATIC_EMP specified as erasing an
361 * entry
362 */
363 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
364 reg[1] |= mac[5] << MAC_BYTE_5;
365 reg[1] |= mac[4] << MAC_BYTE_4;
366 reg[0] |= mac[3] << MAC_BYTE_3;
367 reg[0] |= mac[2] << MAC_BYTE_2;
368 reg[0] |= mac[1] << MAC_BYTE_1;
369 reg[0] |= mac[0] << MAC_BYTE_0;
370
371 /* Write array into the ARL table */
372 for (i = 0; i < 3; i++)
373 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
374}
375
c8b8a3c6
VO		 376/* Set up switch core clock for MT7530 */
377static void mt7530_pll_setup(struct mt7530_priv *priv)
378{
8f058a6e
AÜ		 379 /* Disable core clock */
380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
381
c8b8a3c6
VO		 382 /* Disable PLL */
383 core_write(priv, CORE_GSWPLL_GRP1, 0);
384
385 /* Set core clock into 500Mhz */
386 core_write(priv, CORE_GSWPLL_GRP2,
387 RG_GSWPLL_POSDIV_500M(1) |
388 RG_GSWPLL_FBKDIV_500M(25));
389
390 /* Enable PLL */
391 core_write(priv, CORE_GSWPLL_GRP1,
392 RG_GSWPLL_EN_PRE |
393 RG_GSWPLL_POSDIV_200M(2) |
394 RG_GSWPLL_FBKDIV_200M(32));
8f058a6e
AÜ		 395
396 udelay(20);
397
398 /* Enable core clock */
399 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
c8b8a3c6
VO		 400}
401
fdcc8ccd 402/* Setup port 6 interface mode and TRGMII TX circuit */
b8f126a8 403static int
88bdef8b 404mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
b8f126a8
SW		 405{
406 struct mt7530_priv *priv = ds->priv;
fdcc8ccd 407 u32 ncpo1, ssc_delta, trgint, xtal;
7ef6f6f8
RD		 408
409 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
410
411 if (xtal == HWTRAP_XTAL_20MHZ) {
412 dev_err(priv->dev,
413 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
414 __func__);
415 return -EINVAL;
416 }
b8f126a8 417
88bdef8b 418 switch (interface) {
b8f126a8
SW		 419 case PHY_INTERFACE_MODE_RGMII:
420 trgint = 0;
b8f126a8
SW		 421 break;
422 case PHY_INTERFACE_MODE_TRGMII:
423 trgint = 1;
407b508b
AÜ		 424 if (xtal == HWTRAP_XTAL_25MHZ)
425 ssc_delta = 0x57;
426 else
427 ssc_delta = 0x87;
7ef6f6f8 428 if (priv->id == ID_MT7621) {
37c218d8 429 /* PLL frequency: 125MHz: 1.0GBit */
7ef6f6f8 430 if (xtal == HWTRAP_XTAL_40MHZ)
37c218d8 431 ncpo1 = 0x0640;
7ef6f6f8
RD		 432 if (xtal == HWTRAP_XTAL_25MHZ)
433 ncpo1 = 0x0a00;
434 } else { /* PLL frequency: 250MHz: 2.0Gbit */
435 if (xtal == HWTRAP_XTAL_40MHZ)
436 ncpo1 = 0x0c80;
437 if (xtal == HWTRAP_XTAL_25MHZ)
438 ncpo1 = 0x1400;
439 }
b8f126a8
SW		 440 break;
441 default:
88bdef8b
LC		 442 dev_err(priv->dev, "xMII interface %d not supported\n",
443 interface);
b8f126a8
SW		 444 return -EINVAL;
445 }
446
447 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
448 P6_INTF_MODE(trgint));
449
0b086d76 450 if (trgint) {
8f058a6e
AÜ		 451 /* Disable the MT7530 TRGMII clocks */
452 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
0b086d76
AÜ		 453
454 /* Setup the MT7530 TRGMII Tx Clock */
455 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
456 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
457 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
458 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
459 core_write(priv, CORE_PLL_GROUP4,
460 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
461 RG_SYSPLL_BIAS_LPF_EN);
462 core_write(priv, CORE_PLL_GROUP2,
463 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
464 RG_SYSPLL_POSDIV(1));
465 core_write(priv, CORE_PLL_GROUP7,
466 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
467 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
468
8f058a6e
AÜ		 469 /* Enable the MT7530 TRGMII clocks */
470 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
0b086d76
AÜ		 471 }
472
b8f126a8
SW		 473 return 0;
474}
475
c288575f
LC		 476static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
477{
478 u32 val;
479
480 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
481
482 return (val & PAD_DUAL_SGMII_EN) != 0;
483}
484
485static int
486mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
487{
42bc4faf
AC		 488 return 0;
489}
490
491static void
492mt7531_pll_setup(struct mt7530_priv *priv)
493{
c288575f
LC		 494 u32 top_sig;
495 u32 hwstrap;
496 u32 xtal;
497 u32 val;
498
499 if (mt7531_dual_sgmii_supported(priv))
42bc4faf 500 return;
c288575f
LC		 501
502 val = mt7530_read(priv, MT7531_CREV);
503 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
504 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
505 if ((val & CHIP_REV_M) > 0)
506 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
507 HWTRAP_XTAL_FSEL_25MHZ;
508 else
509 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
510
511 /* Step 1 : Disable MT7531 COREPLL */
512 val = mt7530_read(priv, MT7531_PLLGP_EN);
513 val &= ~EN_COREPLL;
514 mt7530_write(priv, MT7531_PLLGP_EN, val);
515
516 /* Step 2: switch to XTAL output */
517 val = mt7530_read(priv, MT7531_PLLGP_EN);
518 val |= SW_CLKSW;
519 mt7530_write(priv, MT7531_PLLGP_EN, val);
520
521 val = mt7530_read(priv, MT7531_PLLGP_CR0);
522 val &= ~RG_COREPLL_EN;
523 mt7530_write(priv, MT7531_PLLGP_CR0, val);
524
525 /* Step 3: disable PLLGP and enable program PLLGP */
526 val = mt7530_read(priv, MT7531_PLLGP_EN);
527 val |= SW_PLLGP;
528 mt7530_write(priv, MT7531_PLLGP_EN, val);
529
530 /* Step 4: program COREPLL output frequency to 500MHz */
531 val = mt7530_read(priv, MT7531_PLLGP_CR0);
532 val &= ~RG_COREPLL_POSDIV_M;
533 val |= 2 << RG_COREPLL_POSDIV_S;
534 mt7530_write(priv, MT7531_PLLGP_CR0, val);
535 usleep_range(25, 35);
536
537 switch (xtal) {
538 case HWTRAP_XTAL_FSEL_25MHZ:
539 val = mt7530_read(priv, MT7531_PLLGP_CR0);
540 val &= ~RG_COREPLL_SDM_PCW_M;
541 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
542 mt7530_write(priv, MT7531_PLLGP_CR0, val);
543 break;
544 case HWTRAP_XTAL_FSEL_40MHZ:
545 val = mt7530_read(priv, MT7531_PLLGP_CR0);
546 val &= ~RG_COREPLL_SDM_PCW_M;
547 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
548 mt7530_write(priv, MT7531_PLLGP_CR0, val);
549 break;
0e8c266c 550 }
c288575f
LC		 551
552 /* Set feedback divide ratio update signal to high */
553 val = mt7530_read(priv, MT7531_PLLGP_CR0);
554 val |= RG_COREPLL_SDM_PCW_CHG;
555 mt7530_write(priv, MT7531_PLLGP_CR0, val);
556 /* Wait for at least 16 XTAL clocks */
557 usleep_range(10, 20);
558
559 /* Step 5: set feedback divide ratio update signal to low */
560 val = mt7530_read(priv, MT7531_PLLGP_CR0);
561 val &= ~RG_COREPLL_SDM_PCW_CHG;
562 mt7530_write(priv, MT7531_PLLGP_CR0, val);
563
564 /* Enable 325M clock for SGMII */
565 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
566
567 /* Enable 250SSC clock for RGMII */
568 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
569
570 /* Step 6: Enable MT7531 PLL */
571 val = mt7530_read(priv, MT7531_PLLGP_CR0);
572 val |= RG_COREPLL_EN;
573 mt7530_write(priv, MT7531_PLLGP_CR0, val);
574
575 val = mt7530_read(priv, MT7531_PLLGP_EN);
576 val |= EN_COREPLL;
577 mt7530_write(priv, MT7531_PLLGP_EN, val);
578 usleep_range(25, 35);
c288575f
LC		 579}
580
b8f126a8
SW		 581static void
582mt7530_mib_reset(struct dsa_switch *ds)
583{
584 struct mt7530_priv *priv = ds->priv;
585
586 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
587 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
588}
589
defa2e54 590static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)
b8f126a8 591{
b8f126a8
SW		 592 return mdiobus_read_nested(priv->bus, port, regnum);
593}
594
defa2e54
AL		 595static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum,
596 u16 val)
b8f126a8 597{
b8f126a8
SW		 598 return mdiobus_write_nested(priv->bus, port, regnum, val);
599}
600
defa2e54
AL		 601static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port,
602 int devad, int regnum)
603{
604 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum);
605}
606
607static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad,
608 int regnum, u16 val)
609{
610 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val);
611}
612
c288575f
LC		 613static int
614mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
615 int regnum)
616{
c288575f
LC		 617 struct mt7530_dummy_poll p;
618 u32 reg, val;
619 int ret;
620
621 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
622
1557c679 623 mt7530_mutex_lock(priv);
c288575f
LC		 624
625 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
626 !(val & MT7531_PHY_ACS_ST), 20, 100000);
627 if (ret < 0) {
628 dev_err(priv->dev, "poll timeout\n");
629 goto out;
630 }
631
632 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
633 MT7531_MDIO_DEV_ADDR(devad) | regnum;
634 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
635
636 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
637 !(val & MT7531_PHY_ACS_ST), 20, 100000);
638 if (ret < 0) {
639 dev_err(priv->dev, "poll timeout\n");
640 goto out;
641 }
642
643 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
644 MT7531_MDIO_DEV_ADDR(devad);
645 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
646
647 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
648 !(val & MT7531_PHY_ACS_ST), 20, 100000);
649 if (ret < 0) {
650 dev_err(priv->dev, "poll timeout\n");
651 goto out;
652 }
653
654 ret = val & MT7531_MDIO_RW_DATA_MASK;
655out:
1557c679 656 mt7530_mutex_unlock(priv);
c288575f
LC		 657
658 return ret;
659}
660
661static int
662mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
defa2e54 663 int regnum, u16 data)
c288575f 664{
c288575f
LC		 665 struct mt7530_dummy_poll p;
666 u32 val, reg;
667 int ret;
668
669 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
670
1557c679 671 mt7530_mutex_lock(priv);
c288575f
LC		 672
673 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
674 !(val & MT7531_PHY_ACS_ST), 20, 100000);
675 if (ret < 0) {
676 dev_err(priv->dev, "poll timeout\n");
677 goto out;
678 }
679
680 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
681 MT7531_MDIO_DEV_ADDR(devad) | regnum;
682 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
683
684 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
685 !(val & MT7531_PHY_ACS_ST), 20, 100000);
686 if (ret < 0) {
687 dev_err(priv->dev, "poll timeout\n");
688 goto out;
689 }
690
691 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
692 MT7531_MDIO_DEV_ADDR(devad) | data;
693 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
694
695 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
696 !(val & MT7531_PHY_ACS_ST), 20, 100000);
697 if (ret < 0) {
698 dev_err(priv->dev, "poll timeout\n");
699 goto out;
700 }
701
702out:
1557c679 703 mt7530_mutex_unlock(priv);
c288575f
LC		 704
705 return ret;
706}
707
708static int
709mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
710{
c288575f
LC		 711 struct mt7530_dummy_poll p;
712 int ret;
713 u32 val;
714
715 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
716
1557c679 717 mt7530_mutex_lock(priv);
c288575f
LC		 718
719 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
720 !(val & MT7531_PHY_ACS_ST), 20, 100000);
721 if (ret < 0) {
722 dev_err(priv->dev, "poll timeout\n");
723 goto out;
724 }
725
726 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
727 MT7531_MDIO_REG_ADDR(regnum);
728
729 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
730
731 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
732 !(val & MT7531_PHY_ACS_ST), 20, 100000);
733 if (ret < 0) {
734 dev_err(priv->dev, "poll timeout\n");
735 goto out;
736 }
737
738 ret = val & MT7531_MDIO_RW_DATA_MASK;
739out:
1557c679 740 mt7530_mutex_unlock(priv);
c288575f
LC		 741
742 return ret;
743}
744
745static int
746mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
747 u16 data)
748{
c288575f
LC		 749 struct mt7530_dummy_poll p;
750 int ret;
751 u32 reg;
752
753 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
754
1557c679 755 mt7530_mutex_lock(priv);
c288575f
LC		 756
757 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
758 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
759 if (ret < 0) {
760 dev_err(priv->dev, "poll timeout\n");
761 goto out;
762 }
763
764 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
765 MT7531_MDIO_REG_ADDR(regnum) | data;
766
767 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
768
769 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
770 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
771 if (ret < 0) {
772 dev_err(priv->dev, "poll timeout\n");
773 goto out;
774 }
775
776out:
1557c679 777 mt7530_mutex_unlock(priv);
c288575f
LC		 778
779 return ret;
780}
781
782static int
defa2e54 783mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum)
c288575f 784{
defa2e54 785 struct mt7530_priv *priv = bus->priv;
c288575f 786
defa2e54 787 return priv->info->phy_read_c22(priv, port, regnum);
c288575f
LC		 788}
789
790static int
defa2e54 791mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum)
c288575f 792{
defa2e54 793 struct mt7530_priv *priv = bus->priv;
c288575f 794
defa2e54 795 return priv->info->phy_read_c45(priv, port, devad, regnum);
c288575f
LC		 796}
797
ba751e28 798static int
defa2e54 799mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val)
ba751e28
DQ		 800{
801 struct mt7530_priv *priv = bus->priv;
802
defa2e54 803 return priv->info->phy_write_c22(priv, port, regnum, val);
ba751e28
DQ		 804}
805
806static int
defa2e54
AL		 807mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum,
808 u16 val)
ba751e28
DQ		 809{
810 struct mt7530_priv *priv = bus->priv;
811
defa2e54 812 return priv->info->phy_write_c45(priv, port, devad, regnum, val);
ba751e28
DQ		 813}
814
b8f126a8 815static void
89f09048
FF		 816mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
817 uint8_t *data)
b8f126a8
SW		 818{
819 int i;
820
89f09048
FF		 821 if (stringset != ETH_SS_STATS)
822 return;
823
b8f126a8
SW		 824 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
825 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
826 ETH_GSTRING_LEN);
827}
828
829static void
830mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
831 uint64_t *data)
832{
833 struct mt7530_priv *priv = ds->priv;
834 const struct mt7530_mib_desc *mib;
835 u32 reg, i;
836 u64 hi;
837
838 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
839 mib = &mt7530_mib[i];
840 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
841
842 data[i] = mt7530_read(priv, reg);
843 if (mib->size == 2) {
844 hi = mt7530_read(priv, reg + 4);
845 data[i] |= hi << 32;
846 }
847 }
848}
849
850static int
89f09048 851mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
b8f126a8 852{
89f09048
FF		 853 if (sset != ETH_SS_STATS)
854 return 0;
855
b8f126a8
SW		 856 return ARRAY_SIZE(mt7530_mib);
857}
858
ea6d5c92
DQ		 859static int
860mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
861{
862 struct mt7530_priv *priv = ds->priv;
863 unsigned int secs = msecs / 1000;
864 unsigned int tmp_age_count;
865 unsigned int error = -1;
866 unsigned int age_count;
867 unsigned int age_unit;
868
869 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
870 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
871 return -ERANGE;
872
873 /* iterate through all possible age_count to find the closest pair */
874 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
875 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
876
877 if (tmp_age_unit <= AGE_UNIT_MAX) {
878 unsigned int tmp_error = secs -
879 (tmp_age_count + 1) * (tmp_age_unit + 1);
880
881 /* found a closer pair */
882 if (error > tmp_error) {
883 error = tmp_error;
884 age_count = tmp_age_count;
885 age_unit = tmp_age_unit;
886 }
887
888 /* found the exact match, so break the loop */
889 if (!error)
890 break;
891 }
892 }
893
894 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
895
896 return 0;
897}
898
25d15dee
DG		 899static const char *p5_intf_modes(unsigned int p5_interface)
900{
901 switch (p5_interface) {
902 case P5_DISABLED:
903 return "DISABLED";
904 case P5_INTF_SEL_PHY_P0:
905 return "PHY P0";
906 case P5_INTF_SEL_PHY_P4:
907 return "PHY P4";
908 case P5_INTF_SEL_GMAC5:
909 return "GMAC5";
910 case P5_INTF_SEL_GMAC5_SGMII:
911 return "GMAC5_SGMII";
912 default:
913 return "unknown";
914 }
915}
916
38f790a8
RD		 917static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
918{
919 struct mt7530_priv *priv = ds->priv;
920 u8 tx_delay = 0;
921 int val;
922
923 mutex_lock(&priv->reg_mutex);
924
925 val = mt7530_read(priv, MT7530_MHWTRAP);
926
927 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
928 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
929
930 switch (priv->p5_intf_sel) {
931 case P5_INTF_SEL_PHY_P0:
932 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
933 val |= MHWTRAP_PHY0_SEL;
df561f66 934 fallthrough;
38f790a8
RD		 935 case P5_INTF_SEL_PHY_P4:
936 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
937 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
938
939 /* Setup the MAC by default for the cpu port */
940 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
941 break;
942 case P5_INTF_SEL_GMAC5:
943 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
944 val &= ~MHWTRAP_P5_DIS;
945 break;
946 case P5_DISABLED:
947 interface = PHY_INTERFACE_MODE_NA;
948 break;
949 default:
950 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
951 priv->p5_intf_sel);
952 goto unlock_exit;
953 }
954
955 /* Setup RGMII settings */
956 if (phy_interface_mode_is_rgmii(interface)) {
957 val |= MHWTRAP_P5_RGMII_MODE;
958
959 /* P5 RGMII RX Clock Control: delay setting for 1000M */
960 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
961
962 /* Don't set delay in DSA mode */
963 if (!dsa_is_dsa_port(priv->ds, 5) &&
964 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
965 interface == PHY_INTERFACE_MODE_RGMII_ID))
966 tx_delay = 4; /* n * 0.5 ns */
967
968 /* P5 RGMII TX Clock Control: delay x */
969 mt7530_write(priv, MT7530_P5RGMIITXCR,
970 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
971
972 /* reduce P5 RGMII Tx driving, 8mA */
973 mt7530_write(priv, MT7530_IO_DRV_CR,
974 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
975 }
976
977 mt7530_write(priv, MT7530_MHWTRAP, val);
978
979 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
980 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
981
982 priv->p5_interface = interface;
983
984unlock_exit:
985 mutex_unlock(&priv->reg_mutex);
986}
987
d7c66073
AÜ		 988static void
989mt753x_trap_frames(struct mt7530_priv *priv)
990{
991 /* Trap BPDUs to the CPU port(s) */
992 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
993 MT753X_BPDU_CPU_ONLY);
8332cf6f
AÜ		 994
995 /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */
996 mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK,
997 MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY));
d7c66073
AÜ		 998}
999
b8f126a8 1000static int
c288575f 1001mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
b8f126a8 1002{
c288575f 1003 struct mt7530_priv *priv = ds->priv;
0ce0c3cd 1004 int ret;
c288575f
LC		 1005
1006 /* Setup max capability of CPU port at first */
0ce0c3cd
AD		 1007 if (priv->info->cpu_port_config) {
1008 ret = priv->info->cpu_port_config(ds, port);
1009 if (ret)
1010 return ret;
1011 }
c288575f 1012
b8f126a8
SW		 1013 /* Enable Mediatek header mode on the cpu port */
1014 mt7530_write(priv, MT7530_PVC_P(port),
1015 PORT_SPEC_TAG);
1016
120a56b0
AÜ		 1017 /* Enable flooding on the CPU port */
1018 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
1019 UNU_FFP(BIT(port)));
b8f126a8 1020
ddda1ac1 1021 /* Set CPU port number */
4ae90f90 1022 if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
ddda1ac1
GU		 1023 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1024
ff221029
AÜ		 1025 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
1026 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
1027 * is affine to the inbound user port.
1028 */
1029 if (priv->id == ID_MT7531 || priv->id == ID_MT7988)
1030 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port)));
1031
b8f126a8 1032 /* CPU port gets connected to all user ports of
c288575f 1033 * the switch.
b8f126a8
SW		 1034 */
1035 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 1036 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8 1037
6087175b
DQ		 1038 /* Set to fallback mode for independent VLAN learning */
1039 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1040 MT7530_PORT_FALLBACK_MODE);
1041
b8f126a8
SW		 1042 return 0;
1043}
1044
1045static int
1046mt7530_port_enable(struct dsa_switch *ds, int port,
1047 struct phy_device *phy)
1048{
1f9a6abe 1049 struct dsa_port *dp = dsa_to_port(ds, port);
b8f126a8
SW		 1050 struct mt7530_priv *priv = ds->priv;
1051
1052 mutex_lock(&priv->reg_mutex);
1053
b8f126a8
SW		 1054 /* Allow the user port gets connected to the cpu port and also
1055 * restore the port matrix if the port is the member of a certain
1056 * bridge.
1057 */
1f9a6abe
FW		 1058 if (dsa_port_is_user(dp)) {
1059 struct dsa_port *cpu_dp = dp->cpu_dp;
1060
1061 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index));
1062 }
b8f126a8
SW		 1063 priv->ports[port].enable = true;
1064 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1065 priv->ports[port].pm);
1d01145f 1066 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1067
1068 mutex_unlock(&priv->reg_mutex);
1069
1070 return 0;
1071}
1072
1073static void
75104db0 1074mt7530_port_disable(struct dsa_switch *ds, int port)
b8f126a8
SW		 1075{
1076 struct mt7530_priv *priv = ds->priv;
1077
1078 mutex_lock(&priv->reg_mutex);
1079
1080 /* Clear up all port matrix which could be restored in the next
1081 * enablement for the port.
1082 */
1083 priv->ports[port].enable = false;
1084 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1085 PCR_MATRIX_CLR);
1d01145f 1086 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1087
1088 mutex_unlock(&priv->reg_mutex);
1089}
1090
9470174e
DQ		 1091static int
1092mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1093{
1094 struct mt7530_priv *priv = ds->priv;
9470174e
DQ		 1095 int length;
1096 u32 val;
1097
1098 /* When a new MTU is set, DSA always set the CPU port's MTU to the
1099 * largest MTU of the slave ports. Because the switch only has a global
1100 * RX length register, only allowing CPU port here is enough.
1101 */
1102 if (!dsa_is_cpu_port(ds, port))
1103 return 0;
1104
1557c679 1105 mt7530_mutex_lock(priv);
9470174e
DQ		 1106
1107 val = mt7530_mii_read(priv, MT7530_GMACCR);
1108 val &= ~MAX_RX_PKT_LEN_MASK;
1109
1110 /* RX length also includes Ethernet header, MTK tag, and FCS length */
1111 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1112 if (length <= 1522) {
1113 val |= MAX_RX_PKT_LEN_1522;
1114 } else if (length <= 1536) {
1115 val |= MAX_RX_PKT_LEN_1536;
1116 } else if (length <= 1552) {
1117 val |= MAX_RX_PKT_LEN_1552;
1118 } else {
1119 val &= ~MAX_RX_JUMBO_MASK;
1120 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1121 val |= MAX_RX_PKT_LEN_JUMBO;
1122 }
1123
1124 mt7530_mii_write(priv, MT7530_GMACCR, val);
1125
1557c679 1126 mt7530_mutex_unlock(priv);
9470174e
DQ		 1127
1128 return 0;
1129}
1130
1131static int
1132mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1133{
1134 return MT7530_MAX_MTU;
1135}
1136
b8f126a8
SW		 1137static void
1138mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1139{
1140 struct mt7530_priv *priv = ds->priv;
1141 u32 stp_state;
1142
1143 switch (state) {
1144 case BR_STATE_DISABLED:
1145 stp_state = MT7530_STP_DISABLED;
1146 break;
1147 case BR_STATE_BLOCKING:
1148 stp_state = MT7530_STP_BLOCKING;
1149 break;
1150 case BR_STATE_LISTENING:
1151 stp_state = MT7530_STP_LISTENING;
1152 break;
1153 case BR_STATE_LEARNING:
1154 stp_state = MT7530_STP_LEARNING;
1155 break;
1156 case BR_STATE_FORWARDING:
1157 default:
1158 stp_state = MT7530_STP_FORWARDING;
1159 break;
1160 }
1161
a9e3f62d
DQ		 1162 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED),
1163 FID_PST(FID_BRIDGED, stp_state));
b8f126a8
SW		 1164}
1165
5a30833b
DQ		 1166static int
1167mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1168 struct switchdev_brport_flags flags,
1169 struct netlink_ext_ack *extack)
1170{
1171 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1172 BR_BCAST_FLOOD))
1173 return -EINVAL;
1174
1175 return 0;
1176}
1177
1178static int
1179mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
1180 struct switchdev_brport_flags flags,
1181 struct netlink_ext_ack *extack)
1182{
1183 struct mt7530_priv *priv = ds->priv;
1184
1185 if (flags.mask & BR_LEARNING)
1186 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
1187 flags.val & BR_LEARNING ? 0 : SA_DIS);
1188
1189 if (flags.mask & BR_FLOOD)
1190 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
1191 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1192
1193 if (flags.mask & BR_MCAST_FLOOD)
1194 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1195 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1196
1197 if (flags.mask & BR_BCAST_FLOOD)
1198 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
1199 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1200
1201 return 0;
1202}
1203
b8f126a8
SW		 1204static int
1205mt7530_port_bridge_join(struct dsa_switch *ds, int port,
06b9cce4
VO		 1206 struct dsa_bridge bridge, bool *tx_fwd_offload,
1207 struct netlink_ext_ack *extack)
b8f126a8 1208{
872bb81d 1209 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1f9a6abe
FW		 1210 struct dsa_port *cpu_dp = dp->cpu_dp;
1211 u32 port_bitmap = BIT(cpu_dp->index);
872bb81d 1212 struct mt7530_priv *priv = ds->priv;
b8f126a8
SW		 1213
1214 mutex_lock(&priv->reg_mutex);
1215
872bb81d
VO		 1216 dsa_switch_for_each_user_port(other_dp, ds) {
1217 int other_port = other_dp->index;
1218
1219 if (dp == other_dp)
1220 continue;
1221
b8f126a8
SW		 1222 /* Add this port to the port matrix of the other ports in the
1223 * same bridge. If the port is disabled, port matrix is kept
1224 * and not being setup until the port becomes enabled.
1225 */
d3eed0e5 1226 if (!dsa_port_offloads_bridge(other_dp, &bridge))
872bb81d
VO		 1227 continue;
1228
1229 if (priv->ports[other_port].enable)
1230 mt7530_set(priv, MT7530_PCR_P(other_port),
1231 PCR_MATRIX(BIT(port)));
1232 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port));
1233
1234 port_bitmap |= BIT(other_port);
b8f126a8
SW		 1235 }
1236
1237 /* Add the all other ports to this port matrix. */
1238 if (priv->ports[port].enable)
1239 mt7530_rmw(priv, MT7530_PCR_P(port),
1240 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1241 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1242
6087175b
DQ		 1243 /* Set to fallback mode for independent VLAN learning */
1244 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1245 MT7530_PORT_FALLBACK_MODE);
1246
b8f126a8
SW		 1247 mutex_unlock(&priv->reg_mutex);
1248
1249 return 0;
1250}
1251
83163f7d
SW		 1252static void
1253mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1254{
1255 struct mt7530_priv *priv = ds->priv;
1256 bool all_user_ports_removed = true;
1257 int i;
1258
6087175b
DQ		 1259 /* This is called after .port_bridge_leave when leaving a VLAN-aware
1260 * bridge. Don't set standalone ports to fallback mode.
83163f7d 1261 */
41fb0cf1 1262 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
6087175b
DQ		 1263 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1264 MT7530_PORT_FALLBACK_MODE);
1265
8fbebef8
DQ		 1266 mt7530_rmw(priv, MT7530_PVC_P(port),
1267 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
e045124e 1268 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
8fbebef8
DQ		 1269 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
1270 MT7530_VLAN_ACC_ALL);
83163f7d 1271
6087175b
DQ		 1272 /* Set PVID to 0 */
1273 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1274 G0_PORT_VID_DEF);
1275
83163f7d
SW		 1276 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1277 if (dsa_is_user_port(ds, i) &&
68bb8ea8 1278 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
83163f7d
SW		 1279 all_user_ports_removed = false;
1280 break;
1281 }
1282 }
1283
1284 /* CPU port also does the same thing until all user ports belonging to
1285 * the CPU port get out of VLAN filtering mode.
1286 */
1287 if (all_user_ports_removed) {
1f9a6abe
FW		 1288 struct dsa_port *dp = dsa_to_port(ds, port);
1289 struct dsa_port *cpu_dp = dp->cpu_dp;
1290
1291 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index),
83163f7d 1292 PCR_MATRIX(dsa_user_ports(priv->ds)));
1f9a6abe 1293 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG
e045124e 1294 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d
SW		 1295 }
1296}
1297
1298static void
1299mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1300{
1301 struct mt7530_priv *priv = ds->priv;
1302
83163f7d 1303 /* Trapped into security mode allows packet forwarding through VLAN
6087175b 1304 * table lookup.
83163f7d 1305 */
6087175b 1306 if (dsa_is_user_port(ds, port)) {
38152ea3
DQ		 1307 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1308 MT7530_PORT_SECURITY_MODE);
6087175b
DQ		 1309 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1310 G0_PORT_VID(priv->ports[port].pvid));
8fbebef8
DQ		 1311
1312 /* Only accept tagged frames if PVID is not set */
1313 if (!priv->ports[port].pvid)
1314 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1315 MT7530_VLAN_ACC_TAGGED);
83163f7d 1316
0b6d6425
VO		 1317 /* Set the port as a user port which is to be able to recognize
1318 * VID from incoming packets before fetching entry within the
1319 * VLAN table.
1320 */
1321 mt7530_rmw(priv, MT7530_PVC_P(port),
1322 VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1323 VLAN_ATTR(MT7530_VLAN_USER) |
1324 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
1325 } else {
1326 /* Also set CPU ports to the "user" VLAN port attribute, to
1327 * allow VLAN classification, but keep the EG_TAG attribute as
1328 * "consistent" (i.o.w. don't change its value) for packets
1329 * received by the switch from the CPU, so that tagged packets
1330 * are forwarded to user ports as tagged, and untagged as
1331 * untagged.
1332 */
1333 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
1334 VLAN_ATTR(MT7530_VLAN_USER));
1335 }
83163f7d
SW		 1336}
1337
b8f126a8
SW		 1338static void
1339mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
d3eed0e5 1340 struct dsa_bridge bridge)
b8f126a8 1341{
872bb81d 1342 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1f9a6abe 1343 struct dsa_port *cpu_dp = dp->cpu_dp;
b8f126a8 1344 struct mt7530_priv *priv = ds->priv;
b8f126a8
SW		 1345
1346 mutex_lock(&priv->reg_mutex);
1347
872bb81d
VO		 1348 dsa_switch_for_each_user_port(other_dp, ds) {
1349 int other_port = other_dp->index;
1350
1351 if (dp == other_dp)
1352 continue;
1353
b8f126a8
SW		 1354 /* Remove this port from the port matrix of the other ports
1355 * in the same bridge. If the port is disabled, port matrix
1356 * is kept and not being setup until the port becomes enabled.
1357 */
d3eed0e5 1358 if (!dsa_port_offloads_bridge(other_dp, &bridge))
872bb81d
VO		 1359 continue;
1360
1361 if (priv->ports[other_port].enable)
1362 mt7530_clear(priv, MT7530_PCR_P(other_port),
1363 PCR_MATRIX(BIT(port)));
1364 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port));
b8f126a8
SW		 1365 }
1366
1367 /* Set the cpu port to be the only one in the port matrix of
1368 * this port.
1369 */
1370 if (priv->ports[port].enable)
1371 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1f9a6abe
FW		 1372 PCR_MATRIX(BIT(cpu_dp->index)));
1373 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index));
b8f126a8 1374
6087175b
DQ		 1375 /* When a port is removed from the bridge, the port would be set up
1376 * back to the default as is at initial boot which is a VLAN-unaware
1377 * port.
1378 */
1379 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1380 MT7530_PORT_MATRIX_MODE);
1381
b8f126a8
SW		 1382 mutex_unlock(&priv->reg_mutex);
1383}
1384
1385static int
b8f126a8 1386mt7530_port_fdb_add(struct dsa_switch *ds, int port,
c2693363
VO		 1387 const unsigned char *addr, u16 vid,
1388 struct dsa_db db)
b8f126a8
SW		 1389{
1390 struct mt7530_priv *priv = ds->priv;
1b6dd556 1391 int ret;
b8f126a8
SW		 1392 u8 port_mask = BIT(port);
1393
1394 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1395 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 1396 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 1397 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 1398
1399 return ret;
b8f126a8
SW		 1400}
1401
1402static int
1403mt7530_port_fdb_del(struct dsa_switch *ds, int port,
c2693363
VO		 1404 const unsigned char *addr, u16 vid,
1405 struct dsa_db db)
b8f126a8
SW		 1406{
1407 struct mt7530_priv *priv = ds->priv;
1408 int ret;
1409 u8 port_mask = BIT(port);
1410
1411 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1412 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 1413 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 1414 mutex_unlock(&priv->reg_mutex);
1415
1416 return ret;
1417}
1418
1419static int
1420mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1421 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 1422{
1423 struct mt7530_priv *priv = ds->priv;
1424 struct mt7530_fdb _fdb = { 0 };
1425 int cnt = MT7530_NUM_FDB_RECORDS;
1426 int ret = 0;
1427 u32 rsp = 0;
1428
1429 mutex_lock(&priv->reg_mutex);
1430
1431 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1432 if (ret < 0)
1433 goto err;
1434
1435 do {
1436 if (rsp & ATC_SRCH_HIT) {
1437 mt7530_fdb_read(priv, &_fdb);
1438 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 1439 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1440 data);
b8f126a8
SW		 1441 if (ret < 0)
1442 break;
1443 }
1444 }
1445 } while (--cnt &&
1446 !(rsp & ATC_SRCH_END) &&
1447 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1448err:
1449 mutex_unlock(&priv->reg_mutex);
1450
1451 return 0;
1452}
1453
5a30833b
DQ		 1454static int
1455mt7530_port_mdb_add(struct dsa_switch *ds, int port,
c2693363
VO		 1456 const struct switchdev_obj_port_mdb *mdb,
1457 struct dsa_db db)
5a30833b
DQ		 1458{
1459 struct mt7530_priv *priv = ds->priv;
1460 const u8 *addr = mdb->addr;
1461 u16 vid = mdb->vid;
1462 u8 port_mask = 0;
1463 int ret;
1464
1465 mutex_lock(&priv->reg_mutex);
1466
1467 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1468 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1469 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1470 & PORT_MAP_MASK;
1471
1472 port_mask |= BIT(port);
1473 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1474 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1475
1476 mutex_unlock(&priv->reg_mutex);
1477
1478 return ret;
1479}
1480
1481static int
1482mt7530_port_mdb_del(struct dsa_switch *ds, int port,
c2693363
VO		 1483 const struct switchdev_obj_port_mdb *mdb,
1484 struct dsa_db db)
5a30833b
DQ		 1485{
1486 struct mt7530_priv *priv = ds->priv;
1487 const u8 *addr = mdb->addr;
1488 u16 vid = mdb->vid;
1489 u8 port_mask = 0;
1490 int ret;
1491
1492 mutex_lock(&priv->reg_mutex);
1493
1494 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1495 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1496 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1497 & PORT_MAP_MASK;
1498
1499 port_mask &= ~BIT(port);
1500 mt7530_fdb_write(priv, vid, port_mask, addr, -1,
1501 port_mask ? STATIC_ENT : STATIC_EMP);
1502 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1503
1504 mutex_unlock(&priv->reg_mutex);
1505
1506 return ret;
1507}
1508
83163f7d
SW		 1509static int
1510mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1511{
1512 struct mt7530_dummy_poll p;
1513 u32 val;
1514 int ret;
1515
1516 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1517 mt7530_write(priv, MT7530_VTCR, val);
1518
1519 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1520 ret = readx_poll_timeout(_mt7530_read, &p, val,
1521 !(val & VTCR_BUSY), 20, 20000);
1522 if (ret < 0) {
1523 dev_err(priv->dev, "poll timeout\n");
1524 return ret;
1525 }
1526
1527 val = mt7530_read(priv, MT7530_VTCR);
1528 if (val & VTCR_INVALID) {
1529 dev_err(priv->dev, "read VTCR invalid\n");
1530 return -EINVAL;
1531 }
1532
1533 return 0;
1534}
1535
1536static int
89153ed6
VO		 1537mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1538 struct netlink_ext_ack *extack)
83163f7d 1539{
1f9a6abe
FW		 1540 struct dsa_port *dp = dsa_to_port(ds, port);
1541 struct dsa_port *cpu_dp = dp->cpu_dp;
1542
83163f7d
SW		 1543 if (vlan_filtering) {
1544 /* The port is being kept as VLAN-unaware port when bridge is
1545 * set up with vlan_filtering not being set, Otherwise, the
1546 * port and the corresponding CPU port is required the setup
1547 * for becoming a VLAN-aware port.
1548 */
1549 mt7530_port_set_vlan_aware(ds, port);
1f9a6abe 1550 mt7530_port_set_vlan_aware(ds, cpu_dp->index);
e3ee07d1
VO		 1551 } else {
1552 mt7530_port_set_vlan_unaware(ds, port);
83163f7d
SW		 1553 }
1554
1555 return 0;
1556}
1557
83163f7d
SW		 1558static void
1559mt7530_hw_vlan_add(struct mt7530_priv *priv,
1560 struct mt7530_hw_vlan_entry *entry)
1561{
a9c31741 1562 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
83163f7d
SW		 1563 u8 new_members;
1564 u32 val;
1565
a9c31741 1566 new_members = entry->old_members | BIT(entry->port);
83163f7d
SW		 1567
1568 /* Validate the entry with independent learning, create egress tag per
1569 * VLAN and joining the port as one of the port members.
1570 */
6087175b
DQ		 1571 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
1572 VLAN_VALID;
83163f7d
SW		 1573 mt7530_write(priv, MT7530_VAWD1, val);
1574
1575 /* Decide whether adding tag or not for those outgoing packets from the
1576 * port inside the VLAN.
a9c31741 1577 * CPU port is always taken as a tagged port for serving more than one
83163f7d
SW		 1578 * VLANs across and also being applied with egress type stack mode for
1579 * that VLAN tags would be appended after hardware special tag used as
1580 * DSA tag.
1581 */
a9c31741
FW		 1582 if (dsa_port_is_cpu(dp))
1583 val = MT7530_VLAN_EGRESS_STACK;
1584 else if (entry->untagged)
1585 val = MT7530_VLAN_EGRESS_UNTAG;
1586 else
1587 val = MT7530_VLAN_EGRESS_TAG;
83163f7d 1588 mt7530_rmw(priv, MT7530_VAWD2,
a9c31741
FW		 1589 ETAG_CTRL_P_MASK(entry->port),
1590 ETAG_CTRL_P(entry->port, val));
83163f7d
SW		 1591}
1592
1593static void
1594mt7530_hw_vlan_del(struct mt7530_priv *priv,
1595 struct mt7530_hw_vlan_entry *entry)
1596{
1597 u8 new_members;
1598 u32 val;
1599
1600 new_members = entry->old_members & ~BIT(entry->port);
1601
1602 val = mt7530_read(priv, MT7530_VAWD1);
1603 if (!(val & VLAN_VALID)) {
1604 dev_err(priv->dev,
1605 "Cannot be deleted due to invalid entry\n");
1606 return;
1607 }
1608
a9c31741 1609 if (new_members) {
83163f7d
SW		 1610 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1611 VLAN_VALID;
1612 mt7530_write(priv, MT7530_VAWD1, val);
1613 } else {
1614 mt7530_write(priv, MT7530_VAWD1, 0);
1615 mt7530_write(priv, MT7530_VAWD2, 0);
1616 }
1617}
1618
1619static void
1620mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1621 struct mt7530_hw_vlan_entry *entry,
1622 mt7530_vlan_op vlan_op)
1623{
1624 u32 val;
1625
1626 /* Fetch entry */
1627 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1628
1629 val = mt7530_read(priv, MT7530_VAWD1);
1630
1631 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1632
1633 /* Manipulate entry */
1634 vlan_op(priv, entry);
1635
1636 /* Flush result to hardware */
1637 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1638}
1639
1ca8a193
DQ		 1640static int
1641mt7530_setup_vlan0(struct mt7530_priv *priv)
1642{
1643 u32 val;
1644
1645 /* Validate the entry with independent learning, keep the original
1646 * ingress tag attribute.
1647 */
1648 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
1649 VLAN_VALID;
1650 mt7530_write(priv, MT7530_VAWD1, val);
1651
1652 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
1653}
1654
1958d581 1655static int
83163f7d 1656mt7530_port_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 1657 const struct switchdev_obj_port_vlan *vlan,
1658 struct netlink_ext_ack *extack)
83163f7d
SW		 1659{
1660 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1661 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1662 struct mt7530_hw_vlan_entry new_entry;
1663 struct mt7530_priv *priv = ds->priv;
83163f7d 1664
83163f7d
SW		 1665 mutex_lock(&priv->reg_mutex);
1666
b7a9e0da
VO		 1667 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1668 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
83163f7d
SW		 1669
1670 if (pvid) {
b7a9e0da 1671 priv->ports[port].pvid = vlan->vid;
6087175b 1672
8fbebef8
DQ		 1673 /* Accept all frames if PVID is set */
1674 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1675 MT7530_VLAN_ACC_ALL);
1676
6087175b
DQ		 1677 /* Only configure PVID if VLAN filtering is enabled */
1678 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1679 mt7530_rmw(priv, MT7530_PPBV1_P(port),
1680 G0_PORT_VID_MASK,
1681 G0_PORT_VID(vlan->vid));
8fbebef8
DQ		 1682 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
1683 /* This VLAN is overwritten without PVID, so unset it */
1684 priv->ports[port].pvid = G0_PORT_VID_DEF;
1685
1686 /* Only accept tagged frames if the port is VLAN-aware */
1687 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1688 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1689 MT7530_VLAN_ACC_TAGGED);
1690
1691 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1692 G0_PORT_VID_DEF);
83163f7d
SW		 1693 }
1694
1695 mutex_unlock(&priv->reg_mutex);
1958d581
VO		 1696
1697 return 0;
83163f7d
SW		 1698}
1699
1700static int
1701mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1702 const struct switchdev_obj_port_vlan *vlan)
1703{
1704 struct mt7530_hw_vlan_entry target_entry;
1705 struct mt7530_priv *priv = ds->priv;
83163f7d 1706
83163f7d
SW		 1707 mutex_lock(&priv->reg_mutex);
1708
b7a9e0da
VO		 1709 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1710 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1711 mt7530_hw_vlan_del);
83163f7d 1712
b7a9e0da
VO		 1713 /* PVID is being restored to the default whenever the PVID port
1714 * is being removed from the VLAN.
1715 */
6087175b
DQ		 1716 if (priv->ports[port].pvid == vlan->vid) {
1717 priv->ports[port].pvid = G0_PORT_VID_DEF;
8fbebef8
DQ		 1718
1719 /* Only accept tagged frames if the port is VLAN-aware */
1720 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1721 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1722 MT7530_VLAN_ACC_TAGGED);
1723
6087175b
DQ		 1724 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1725 G0_PORT_VID_DEF);
1726 }
83163f7d 1727
83163f7d
SW		 1728
1729 mutex_unlock(&priv->reg_mutex);
1730
1731 return 0;
1732}
1733
c288575f
LC		 1734static int mt753x_mirror_port_get(unsigned int id, u32 val)
1735{
1736 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1737 MIRROR_PORT(val);
1738}
1739
1740static int mt753x_mirror_port_set(unsigned int id, u32 val)
1741{
1742 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1743 MIRROR_PORT(val);
1744}
1745
1746static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
37feab60 1747 struct dsa_mall_mirror_tc_entry *mirror,
0148bb50 1748 bool ingress, struct netlink_ext_ack *extack)
37feab60
DQ		 1749{
1750 struct mt7530_priv *priv = ds->priv;
c288575f 1751 int monitor_port;
37feab60
DQ		 1752 u32 val;
1753
1754 /* Check for existent entry */
1755 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1756 return -EEXIST;
1757
c288575f 1758 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
37feab60
DQ		 1759
1760 /* MT7530 only supports one monitor port */
c288575f
LC		 1761 monitor_port = mt753x_mirror_port_get(priv->id, val);
1762 if (val & MT753X_MIRROR_EN(priv->id) &&
1763 monitor_port != mirror->to_local_port)
37feab60
DQ		 1764 return -EEXIST;
1765
c288575f
LC		 1766 val |= MT753X_MIRROR_EN(priv->id);
1767 val &= ~MT753X_MIRROR_MASK(priv->id);
1768 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1769 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1770
1771 val = mt7530_read(priv, MT7530_PCR_P(port));
1772 if (ingress) {
1773 val |= PORT_RX_MIR;
1774 priv->mirror_rx |= BIT(port);
1775 } else {
1776 val |= PORT_TX_MIR;
1777 priv->mirror_tx |= BIT(port);
1778 }
1779 mt7530_write(priv, MT7530_PCR_P(port), val);
1780
1781 return 0;
1782}
1783
c288575f 1784static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
37feab60
DQ		 1785 struct dsa_mall_mirror_tc_entry *mirror)
1786{
1787 struct mt7530_priv *priv = ds->priv;
1788 u32 val;
1789
1790 val = mt7530_read(priv, MT7530_PCR_P(port));
1791 if (mirror->ingress) {
1792 val &= ~PORT_RX_MIR;
1793 priv->mirror_rx &= ~BIT(port);
1794 } else {
1795 val &= ~PORT_TX_MIR;
1796 priv->mirror_tx &= ~BIT(port);
1797 }
1798 mt7530_write(priv, MT7530_PCR_P(port), val);
1799
1800 if (!priv->mirror_rx && !priv->mirror_tx) {
c288575f
LC		 1801 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1802 val &= ~MT753X_MIRROR_EN(priv->id);
1803 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1804 }
1805}
1806
b8f126a8 1807static enum dsa_tag_protocol
4d776482
FF		 1808mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1809 enum dsa_tag_protocol mp)
b8f126a8 1810{
244f8a80 1811 return DSA_TAG_PROTO_MTK;
b8f126a8
SW		 1812}
1813
63c75c05 1814#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 1815static inline u32
1816mt7530_gpio_to_bit(unsigned int offset)
1817{
1818 /* Map GPIO offset to register bit
1819 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2
1820 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5
1821 * [10: 8] port 2 LED 0..2 as GPIO 6..8
1822 * [14:12] port 3 LED 0..2 as GPIO 9..11
1823 * [18:16] port 4 LED 0..2 as GPIO 12..14
1824 */
1825 return BIT(offset + offset / 3);
1826}
1827
1828static int
1829mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1830{
1831 struct mt7530_priv *priv = gpiochip_get_data(gc);
1832 u32 bit = mt7530_gpio_to_bit(offset);
1833
1834 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1835}
1836
1837static void
1838mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1839{
1840 struct mt7530_priv *priv = gpiochip_get_data(gc);
1841 u32 bit = mt7530_gpio_to_bit(offset);
1842
1843 if (value)
1844 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1845 else
1846 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1847}
1848
1849static int
1850mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1851{
1852 struct mt7530_priv *priv = gpiochip_get_data(gc);
1853 u32 bit = mt7530_gpio_to_bit(offset);
1854
1855 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1856 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1857}
1858
1859static int
1860mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1861{
1862 struct mt7530_priv *priv = gpiochip_get_data(gc);
1863 u32 bit = mt7530_gpio_to_bit(offset);
1864
1865 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1866 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1867
1868 return 0;
1869}
1870
1871static int
1872mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1873{
1874 struct mt7530_priv *priv = gpiochip_get_data(gc);
1875 u32 bit = mt7530_gpio_to_bit(offset);
1876
1877 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1878
1879 if (value)
1880 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1881 else
1882 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1883
1884 mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1885
1886 return 0;
1887}
1888
1889static int
1890mt7530_setup_gpio(struct mt7530_priv *priv)
1891{
1892 struct device *dev = priv->dev;
1893 struct gpio_chip *gc;
1894
1895 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1896 if (!gc)
1897 return -ENOMEM;
1898
1899 mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1900 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1901 mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1902
1903 gc->label = "mt7530";
1904 gc->parent = dev;
1905 gc->owner = THIS_MODULE;
1906 gc->get_direction = mt7530_gpio_get_direction;
1907 gc->direction_input = mt7530_gpio_direction_input;
1908 gc->direction_output = mt7530_gpio_direction_output;
1909 gc->get = mt7530_gpio_get;
1910 gc->set = mt7530_gpio_set;
1911 gc->base = -1;
1912 gc->ngpio = 15;
1913 gc->can_sleep = true;
1914
1915 return devm_gpiochip_add_data(dev, gc, priv);
1916}
63c75c05 1917#endif /* CONFIG_GPIOLIB */
429a0ede 1918
ba751e28
DQ		 1919static irqreturn_t
1920mt7530_irq_thread_fn(int irq, void *dev_id)
1921{
1922 struct mt7530_priv *priv = dev_id;
1923 bool handled = false;
1924 u32 val;
1925 int p;
1926
1557c679 1927 mt7530_mutex_lock(priv);
ba751e28
DQ		 1928 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
1929 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
1557c679 1930 mt7530_mutex_unlock(priv);
ba751e28
DQ		 1931
1932 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1933 if (BIT(p) & val) {
1934 unsigned int irq;
1935
1936 irq = irq_find_mapping(priv->irq_domain, p);
1937 handle_nested_irq(irq);
1938 handled = true;
1939 }
1940 }
1941
1942 return IRQ_RETVAL(handled);
1943}
1944
1945static void
1946mt7530_irq_mask(struct irq_data *d)
1947{
1948 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1949
1950 priv->irq_enable &= ~BIT(d->hwirq);
1951}
1952
1953static void
1954mt7530_irq_unmask(struct irq_data *d)
1955{
1956 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1957
1958 priv->irq_enable |= BIT(d->hwirq);
1959}
1960
1961static void
1962mt7530_irq_bus_lock(struct irq_data *d)
1963{
1964 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1965
1557c679 1966 mt7530_mutex_lock(priv);
ba751e28
DQ		 1967}
1968
1969static void
1970mt7530_irq_bus_sync_unlock(struct irq_data *d)
1971{
1972 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1973
1974 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1557c679 1975 mt7530_mutex_unlock(priv);
ba751e28
DQ		 1976}
1977
1978static struct irq_chip mt7530_irq_chip = {
1979 .name = KBUILD_MODNAME,
1980 .irq_mask = mt7530_irq_mask,
1981 .irq_unmask = mt7530_irq_unmask,
1982 .irq_bus_lock = mt7530_irq_bus_lock,
1983 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock,
1984};
1985
1986static int
1987mt7530_irq_map(struct irq_domain *domain, unsigned int irq,
1988 irq_hw_number_t hwirq)
1989{
1990 irq_set_chip_data(irq, domain->host_data);
1991 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq);
1992 irq_set_nested_thread(irq, true);
1993 irq_set_noprobe(irq);
1994
1995 return 0;
1996}
1997
1998static const struct irq_domain_ops mt7530_irq_domain_ops = {
1999 .map = mt7530_irq_map,
2000 .xlate = irq_domain_xlate_onecell,
2001};
2002
110c18bf
DG		 2003static void
2004mt7988_irq_mask(struct irq_data *d)
2005{
2006 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
2007
2008 priv->irq_enable &= ~BIT(d->hwirq);
2009 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
2010}
2011
2012static void
2013mt7988_irq_unmask(struct irq_data *d)
2014{
2015 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
2016
2017 priv->irq_enable |= BIT(d->hwirq);
2018 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
2019}
2020
2021static struct irq_chip mt7988_irq_chip = {
2022 .name = KBUILD_MODNAME,
2023 .irq_mask = mt7988_irq_mask,
2024 .irq_unmask = mt7988_irq_unmask,
2025};
2026
2027static int
2028mt7988_irq_map(struct irq_domain *domain, unsigned int irq,
2029 irq_hw_number_t hwirq)
2030{
2031 irq_set_chip_data(irq, domain->host_data);
2032 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq);
2033 irq_set_nested_thread(irq, true);
2034 irq_set_noprobe(irq);
2035
2036 return 0;
2037}
2038
2039static const struct irq_domain_ops mt7988_irq_domain_ops = {
2040 .map = mt7988_irq_map,
2041 .xlate = irq_domain_xlate_onecell,
2042};
2043
ba751e28
DQ		 2044static void
2045mt7530_setup_mdio_irq(struct mt7530_priv *priv)
2046{
2047 struct dsa_switch *ds = priv->ds;
2048 int p;
2049
2050 for (p = 0; p < MT7530_NUM_PHYS; p++) {
2051 if (BIT(p) & ds->phys_mii_mask) {
2052 unsigned int irq;
2053
2054 irq = irq_create_mapping(priv->irq_domain, p);
2055 ds->slave_mii_bus->irq[p] = irq;
2056 }
2057 }
2058}
2059
2060static int
2061mt7530_setup_irq(struct mt7530_priv *priv)
2062{
2063 struct device *dev = priv->dev;
2064 struct device_node *np = dev->of_node;
2065 int ret;
2066
2067 if (!of_property_read_bool(np, "interrupt-controller")) {
2068 dev_info(dev, "no interrupt support\n");
2069 return 0;
2070 }
2071
2072 priv->irq = of_irq_get(np, 0);
2073 if (priv->irq <= 0) {
2074 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq);
2075 return priv->irq ? : -EINVAL;
2076 }
2077
110c18bf
DG		 2078 if (priv->id == ID_MT7988)
2079 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
2080 &mt7988_irq_domain_ops,
2081 priv);
2082 else
2083 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
2084 &mt7530_irq_domain_ops,
2085 priv);
2086
ba751e28
DQ		 2087 if (!priv->irq_domain) {
2088 dev_err(dev, "failed to create IRQ domain\n");
2089 return -ENOMEM;
2090 }
2091
2092 /* This register must be set for MT7530 to properly fire interrupts */
2093 if (priv->id != ID_MT7531)
2094 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
2095
2096 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
2097 IRQF_ONESHOT, KBUILD_MODNAME, priv);
2098 if (ret) {
2099 irq_domain_remove(priv->irq_domain);
2100 dev_err(dev, "failed to request IRQ: %d\n", ret);
2101 return ret;
2102 }
2103
2104 return 0;
2105}
2106
2107static void
2108mt7530_free_mdio_irq(struct mt7530_priv *priv)
2109{
2110 int p;
2111
2112 for (p = 0; p < MT7530_NUM_PHYS; p++) {
2113 if (BIT(p) & priv->ds->phys_mii_mask) {
2114 unsigned int irq;
2115
2116 irq = irq_find_mapping(priv->irq_domain, p);
2117 irq_dispose_mapping(irq);
2118 }
2119 }
2120}
2121
2122static void
2123mt7530_free_irq_common(struct mt7530_priv *priv)
2124{
2125 free_irq(priv->irq, priv);
2126 irq_domain_remove(priv->irq_domain);
2127}
2128
2129static void
2130mt7530_free_irq(struct mt7530_priv *priv)
2131{
2132 mt7530_free_mdio_irq(priv);
2133 mt7530_free_irq_common(priv);
2134}
2135
2136static int
2137mt7530_setup_mdio(struct mt7530_priv *priv)
2138{
2139 struct dsa_switch *ds = priv->ds;
2140 struct device *dev = priv->dev;
2141 struct mii_bus *bus;
2142 static int idx;
2143 int ret;
2144
2145 bus = devm_mdiobus_alloc(dev);
2146 if (!bus)
2147 return -ENOMEM;
2148
2149 ds->slave_mii_bus = bus;
2150 bus->priv = priv;
2151 bus->name = KBUILD_MODNAME "-mii";
2152 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
defa2e54
AL		 2153 bus->read = mt753x_phy_read_c22;
2154 bus->write = mt753x_phy_write_c22;
2155 bus->read_c45 = mt753x_phy_read_c45;
2156 bus->write_c45 = mt753x_phy_write_c45;
ba751e28
DQ		 2157 bus->parent = dev;
2158 bus->phy_mask = ~ds->phys_mii_mask;
2159
2160 if (priv->irq)
2161 mt7530_setup_mdio_irq(priv);
2162
9ffe3d09 2163 ret = devm_mdiobus_register(dev, bus);
ba751e28
DQ		 2164 if (ret) {
2165 dev_err(dev, "failed to register MDIO bus: %d\n", ret);
2166 if (priv->irq)
2167 mt7530_free_mdio_irq(priv);
2168 }
2169
2170 return ret;
2171}
2172
b8f126a8
SW		 2173static int
2174mt7530_setup(struct dsa_switch *ds)
2175{
2176 struct mt7530_priv *priv = ds->priv;
6e19bc26 2177 struct device_node *dn = NULL;
38f790a8
RD		 2178 struct device_node *phy_node;
2179 struct device_node *mac_np;
b8f126a8 2180 struct mt7530_dummy_poll p;
38f790a8 2181 phy_interface_t interface;
6e19bc26 2182 struct dsa_port *cpu_dp;
ca366d6c
RD		 2183 u32 id, val;
2184 int ret, i;
b8f126a8 2185
0abfd494 2186 /* The parent node of master netdev which holds the common system
b8f126a8
SW		 2187 * controller also is the container for two GMACs nodes representing
2188 * as two netdev instances.
2189 */
6e19bc26
FW		 2190 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
2191 dn = cpu_dp->master->dev.of_node->parent;
2192 /* It doesn't matter which CPU port is found first,
2193 * their masters should share the same parent OF node
2194 */
2195 break;
2196 }
2197
2198 if (!dn) {
2199 dev_err(ds->dev, "parent OF node of DSA master not found");
2200 return -EINVAL;
2201 }
2202
0b69c54c 2203 ds->assisted_learning_on_cpu_port = true;
771c8901 2204 ds->mtu_enforcement_ingress = true;
b8f126a8 2205
ddda1ac1 2206 if (priv->id == ID_MT7530) {
ddda1ac1
GU		 2207 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
2208 ret = regulator_enable(priv->core_pwr);
2209 if (ret < 0) {
2210 dev_err(priv->dev,
2211 "Failed to enable core power: %d\n", ret);
2212 return ret;
2213 }
b8f126a8 2214
ddda1ac1
GU		 2215 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
2216 ret = regulator_enable(priv->io_pwr);
2217 if (ret < 0) {
2218 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
2219 ret);
2220 return ret;
2221 }
b8f126a8
SW		 2222 }
2223
2224 /* Reset whole chip through gpio pin or memory-mapped registers for
2225 * different type of hardware
2226 */
2227 if (priv->mcm) {
2228 reset_control_assert(priv->rstc);
2229 usleep_range(1000, 1100);
2230 reset_control_deassert(priv->rstc);
2231 } else {
2232 gpiod_set_value_cansleep(priv->reset, 0);
2233 usleep_range(1000, 1100);
2234 gpiod_set_value_cansleep(priv->reset, 1);
2235 }
2236
2237 /* Waiting for MT7530 got to stable */
2238 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2239 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2240 20, 1000000);
2241 if (ret < 0) {
2242 dev_err(priv->dev, "reset timeout\n");
2243 return ret;
2244 }
2245
2246 id = mt7530_read(priv, MT7530_CREV);
2247 id >>= CHIP_NAME_SHIFT;
2248 if (id != MT7530_ID) {
2249 dev_err(priv->dev, "chip %x can't be supported\n", id);
2250 return -ENODEV;
2251 }
2252
2253 /* Reset the switch through internal reset */
2254 mt7530_write(priv, MT7530_SYS_CTRL,
2255 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2256 SYS_CTRL_REG_RST);
2257
c8b8a3c6
VO		 2258 mt7530_pll_setup(priv);
2259
fdcc8ccd
AÜ		 2260 /* Lower Tx driving for TRGMII path */
2261 for (i = 0; i < NUM_TRGMII_CTRL; i++)
2262 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
2263 TD_DM_DRVP(8) | TD_DM_DRVN(8));
2264
2265 for (i = 0; i < NUM_TRGMII_CTRL; i++)
2266 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
2267 RD_TAP_MASK, RD_TAP(16));
2268
feb03fd1 2269 /* Enable port 6 */
b8f126a8
SW		 2270 val = mt7530_read(priv, MT7530_MHWTRAP);
2271 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
2272 val |= MHWTRAP_MANUAL;
2273 mt7530_write(priv, MT7530_MHWTRAP, val);
2274
ca366d6c
RD		 2275 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2276
d7c66073
AÜ		 2277 mt753x_trap_frames(priv);
2278
b8f126a8
SW		 2279 /* Enable and reset MIB counters */
2280 mt7530_mib_reset(ds);
2281
b8f126a8
SW		 2282 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2283 /* Disable forwarding by default on all ports */
2284 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2285 PCR_MATRIX_CLR);
2286
0b69c54c
DQ		 2287 /* Disable learning by default on all ports */
2288 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2289
0ce0c3cd
AD		 2290 if (dsa_is_cpu_port(ds, i)) {
2291 ret = mt753x_cpu_port_enable(ds, i);
2292 if (ret)
2293 return ret;
5a30833b 2294 } else {
75104db0 2295 mt7530_port_disable(ds, i);
6087175b
DQ		 2296
2297 /* Set default PVID to 0 on all user ports */
2298 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2299 G0_PORT_VID_DEF);
5a30833b 2300 }
e045124e
DQ		 2301 /* Enable consistent egress tag */
2302 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2303 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
b8f126a8
SW		 2304 }
2305
1ca8a193
DQ		 2306 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2307 ret = mt7530_setup_vlan0(priv);
2308 if (ret)
2309 return ret;
2310
38f790a8
RD		 2311 /* Setup port 5 */
2312 priv->p5_intf_sel = P5_DISABLED;
2313 interface = PHY_INTERFACE_MODE_NA;
2314
2315 if (!dsa_is_unused_port(ds, 5)) {
2316 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
0c65b2b9
AL		 2317 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
2318 if (ret && ret != -ENODEV)
2319 return ret;
38f790a8
RD		 2320 } else {
2321 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
2322 for_each_child_of_node(dn, mac_np) {
2323 if (!of_device_is_compatible(mac_np,
2324 "mediatek,eth-mac"))
2325 continue;
2326
2327 ret = of_property_read_u32(mac_np, "reg", &id);
2328 if (ret < 0 || id != 1)
2329 continue;
2330
2331 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
0452800f
CG		 2332 if (!phy_node)
2333 continue;
2334
38f790a8 2335 if (phy_node->parent == priv->dev->of_node->parent) {
0c65b2b9 2336 ret = of_get_phy_mode(mac_np, &interface);
8e4efd47
SP		 2337 if (ret && ret != -ENODEV) {
2338 of_node_put(mac_np);
a9e9b091 2339 of_node_put(phy_node);
0c65b2b9 2340 return ret;
8e4efd47 2341 }
38f790a8
RD		 2342 id = of_mdio_parse_addr(ds->dev, phy_node);
2343 if (id == 0)
2344 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
2345 if (id == 4)
2346 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
2347 }
8e4efd47 2348 of_node_put(mac_np);
38f790a8
RD		 2349 of_node_put(phy_node);
2350 break;
2351 }
2352 }
2353
63c75c05 2354#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 2355 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
2356 ret = mt7530_setup_gpio(priv);
2357 if (ret)
2358 return ret;
2359 }
63c75c05 2360#endif /* CONFIG_GPIOLIB */
429a0ede 2361
38f790a8
RD		 2362 mt7530_setup_port5(ds, interface);
2363
b8f126a8 2364 /* Flush the FDB table */
18bd5949 2365 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 2366 if (ret < 0)
2367 return ret;
2368
2369 return 0;
2370}
2371
7f54cc97
DG		 2372static int
2373mt7531_setup_common(struct dsa_switch *ds)
2374{
2375 struct mt7530_priv *priv = ds->priv;
7f54cc97
DG		 2376 int ret, i;
2377
d7c66073 2378 mt753x_trap_frames(priv);
7f54cc97
DG		 2379
2380 /* Enable and reset MIB counters */
2381 mt7530_mib_reset(ds);
2382
120a56b0
AÜ		 2383 /* Disable flooding on all ports */
2384 mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
2385 UNU_FFP_MASK);
2386
7f54cc97
DG		 2387 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2388 /* Disable forwarding by default on all ports */
2389 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2390 PCR_MATRIX_CLR);
2391
2392 /* Disable learning by default on all ports */
2393 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2394
2395 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
2396
2397 if (dsa_is_cpu_port(ds, i)) {
2398 ret = mt753x_cpu_port_enable(ds, i);
2399 if (ret)
2400 return ret;
2401 } else {
2402 mt7530_port_disable(ds, i);
2403
2404 /* Set default PVID to 0 on all user ports */
2405 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2406 G0_PORT_VID_DEF);
2407 }
2408
2409 /* Enable consistent egress tag */
2410 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2411 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2412 }
2413
2414 /* Flush the FDB table */
2415 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2416 if (ret < 0)
2417 return ret;
2418
2419 return 0;
2420}
2421
c288575f
LC		 2422static int
2423mt7531_setup(struct dsa_switch *ds)
2424{
2425 struct mt7530_priv *priv = ds->priv;
2426 struct mt7530_dummy_poll p;
2427 u32 val, id;
2428 int ret, i;
2429
2430 /* Reset whole chip through gpio pin or memory-mapped registers for
2431 * different type of hardware
2432 */
2433 if (priv->mcm) {
2434 reset_control_assert(priv->rstc);
2435 usleep_range(1000, 1100);
2436 reset_control_deassert(priv->rstc);
2437 } else {
2438 gpiod_set_value_cansleep(priv->reset, 0);
2439 usleep_range(1000, 1100);
2440 gpiod_set_value_cansleep(priv->reset, 1);
2441 }
2442
2443 /* Waiting for MT7530 got to stable */
2444 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2445 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2446 20, 1000000);
2447 if (ret < 0) {
2448 dev_err(priv->dev, "reset timeout\n");
2449 return ret;
2450 }
2451
2452 id = mt7530_read(priv, MT7531_CREV);
2453 id >>= CHIP_NAME_SHIFT;
2454
2455 if (id != MT7531_ID) {
2456 dev_err(priv->dev, "chip %x can't be supported\n", id);
2457 return -ENODEV;
2458 }
2459
728c2af6
AC		 2460 /* all MACs must be forced link-down before sw reset */
2461 for (i = 0; i < MT7530_NUM_PORTS; i++)
2462 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
2463
c288575f
LC		 2464 /* Reset the switch through internal reset */
2465 mt7530_write(priv, MT7530_SYS_CTRL,
2466 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2467 SYS_CTRL_REG_RST);
2468
42bc4faf
AC		 2469 mt7531_pll_setup(priv);
2470
c288575f
LC		 2471 if (mt7531_dual_sgmii_supported(priv)) {
2472 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
2473
2474 /* Let ds->slave_mii_bus be able to access external phy. */
2475 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
2476 MT7531_EXT_P_MDC_11);
2477 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
2478 MT7531_EXT_P_MDIO_12);
2479 } else {
2480 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2481 }
2482 dev_dbg(ds->dev, "P5 support %s interface\n",
2483 p5_intf_modes(priv->p5_intf_sel));
2484
2485 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
2486 MT7531_GPIO0_INTERRUPT);
2487
2488 /* Let phylink decide the interface later. */
2489 priv->p5_interface = PHY_INTERFACE_MODE_NA;
2490 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2491
2492 /* Enable PHY core PLL, since phy_device has not yet been created
2493 * provided for phy_[read,write]_mmd_indirect is called, we provide
2494 * our own mt7531_ind_mmd_phy_[read,write] to complete this
2495 * function.
2496 */
2497 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
2498 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2499 val |= MT7531_PHY_PLL_BYPASS_MODE;
2500 val &= ~MT7531_PHY_PLL_OFF;
2501 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
2502 CORE_PLL_GROUP4, val);
2503
7f54cc97 2504 mt7531_setup_common(ds);
c288575f 2505
1ca8a193
DQ		 2506 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2507 ret = mt7530_setup_vlan0(priv);
2508 if (ret)
2509 return ret;
2510
0b69c54c 2511 ds->assisted_learning_on_cpu_port = true;
771c8901 2512 ds->mtu_enforcement_ingress = true;
c288575f 2513
c288575f
LC		 2514 return 0;
2515}
2516
59c2215f
RKO		 2517static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
2518 struct phylink_config *config)
2519{
2520 switch (port) {
2521 case 0 ... 4: /* Internal phy */
2522 __set_bit(PHY_INTERFACE_MODE_GMII,
2523 config->supported_interfaces);
2524 break;
2525
2526 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2527 phy_interface_set_rgmii(config->supported_interfaces);
2528 __set_bit(PHY_INTERFACE_MODE_MII,
2529 config->supported_interfaces);
2530 __set_bit(PHY_INTERFACE_MODE_GMII,
2531 config->supported_interfaces);
2532 break;
2533
2534 case 6: /* 1st cpu port */
2535 __set_bit(PHY_INTERFACE_MODE_RGMII,
2536 config->supported_interfaces);
2537 __set_bit(PHY_INTERFACE_MODE_TRGMII,
2538 config->supported_interfaces);
2539 break;
2540 }
2541}
2542
c288575f
LC		 2543static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
2544{
2545 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
2546}
2547
59c2215f
RKO		 2548static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
2549 struct phylink_config *config)
2550{
2551 struct mt7530_priv *priv = ds->priv;
2552
2553 switch (port) {
2554 case 0 ... 4: /* Internal phy */
2555 __set_bit(PHY_INTERFACE_MODE_GMII,
2556 config->supported_interfaces);
2557 break;
2558
2559 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
2560 if (mt7531_is_rgmii_port(priv, port)) {
2561 phy_interface_set_rgmii(config->supported_interfaces);
2562 break;
2563 }
2564 fallthrough;
2565
2566 case 6: /* 1st cpu port supports sgmii/8023z only */
2567 __set_bit(PHY_INTERFACE_MODE_SGMII,
2568 config->supported_interfaces);
2569 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
2570 config->supported_interfaces);
2571 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
2572 config->supported_interfaces);
2573
2574 config->mac_capabilities |= MAC_2500FD;
2575 break;
2576 }
2577}
2578
110c18bf
DG		 2579static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
2580 struct phylink_config *config)
2581{
2582 phy_interface_zero(config->supported_interfaces);
2583
2584 switch (port) {
2585 case 0 ... 4: /* Internal phy */
2586 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
2587 config->supported_interfaces);
2588 break;
2589
2590 case 6:
2591 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
2592 config->supported_interfaces);
2593 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
2594 MAC_10000FD;
2595 }
2596}
2597
88bdef8b
LC		 2598static int
2599mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2600{
2601 struct mt7530_priv *priv = ds->priv;
2602
2603 return priv->info->pad_setup(ds, state->interface);
2604}
2605
2606static int
2607mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2608 phy_interface_t interface)
2609{
2610 struct mt7530_priv *priv = ds->priv;
2611
2612 /* Only need to setup port5. */
2613 if (port != 5)
2614 return 0;
2615
2616 mt7530_setup_port5(priv->ds, interface);
2617
2618 return 0;
2619}
2620
c288575f
LC		 2621static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2622 phy_interface_t interface,
2623 struct phy_device *phydev)
2624{
2625 u32 val;
2626
2627 if (!mt7531_is_rgmii_port(priv, port)) {
2628 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2629 port);
2630 return -EINVAL;
2631 }
2632
2633 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2634 val |= GP_CLK_EN;
2635 val &= ~GP_MODE_MASK;
2636 val |= GP_MODE(MT7531_GP_MODE_RGMII);
2637 val &= ~CLK_SKEW_IN_MASK;
2638 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2639 val &= ~CLK_SKEW_OUT_MASK;
2640 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2641 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2642
2643 /* Do not adjust rgmii delay when vendor phy driver presents. */
2644 if (!phydev || phy_driver_is_genphy(phydev)) {
2645 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2646 switch (interface) {
2647 case PHY_INTERFACE_MODE_RGMII:
2648 val |= TXCLK_NO_REVERSE;
2649 val |= RXCLK_NO_DELAY;
2650 break;
2651 case PHY_INTERFACE_MODE_RGMII_RXID:
2652 val |= TXCLK_NO_REVERSE;
2653 break;
2654 case PHY_INTERFACE_MODE_RGMII_TXID:
2655 val |= RXCLK_NO_DELAY;
2656 break;
2657 case PHY_INTERFACE_MODE_RGMII_ID:
2658 break;
2659 default:
2660 return -EINVAL;
2661 }
2662 }
2663 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2664
2665 return 0;
2666}
2667
c288575f
LC		 2668static bool mt753x_is_mac_port(u32 port)
2669{
2670 return (port == 5 || port == 6);
2671}
2672
110c18bf
DG		 2673static int
2674mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2675 phy_interface_t interface)
2676{
2677 if (dsa_is_cpu_port(ds, port) &&
2678 interface == PHY_INTERFACE_MODE_INTERNAL)
2679 return 0;
2680
2681 return -EINVAL;
2682}
2683
c288575f
LC		 2684static int
2685mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2686 phy_interface_t interface)
2687{
2688 struct mt7530_priv *priv = ds->priv;
2689 struct phy_device *phydev;
2690 struct dsa_port *dp;
2691
2692 if (!mt753x_is_mac_port(port)) {
2693 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2694 return -EINVAL;
2695 }
2696
2697 switch (interface) {
2698 case PHY_INTERFACE_MODE_RGMII:
2699 case PHY_INTERFACE_MODE_RGMII_ID:
2700 case PHY_INTERFACE_MODE_RGMII_RXID:
2701 case PHY_INTERFACE_MODE_RGMII_TXID:
2702 dp = dsa_to_port(ds, port);
2703 phydev = dp->slave->phydev;
2704 return mt7531_rgmii_setup(priv, port, interface, phydev);
2705 case PHY_INTERFACE_MODE_SGMII:
c288575f
LC		 2706 case PHY_INTERFACE_MODE_NA:
2707 case PHY_INTERFACE_MODE_1000BASEX:
2708 case PHY_INTERFACE_MODE_2500BASEX:
5b89aeae
DG		 2709 /* handled in SGMII PCS driver */
2710 return 0;
c288575f
LC		 2711 default:
2712 return -EINVAL;
2713 }
2714
2715 return -EINVAL;
2716}
2717
88bdef8b
LC		 2718static int
2719mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2720 const struct phylink_link_state *state)
2721{
2722 struct mt7530_priv *priv = ds->priv;
2723
2724 return priv->info->mac_port_config(ds, port, mode, state->interface);
2725}
2726
cbd1f243
RKO		 2727static struct phylink_pcs *
2728mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
2729 phy_interface_t interface)
2730{
2731 struct mt7530_priv *priv = ds->priv;
2732
2733 switch (interface) {
2734 case PHY_INTERFACE_MODE_TRGMII:
5b89aeae 2735 return &priv->pcs[port].pcs;
cbd1f243
RKO		 2736 case PHY_INTERFACE_MODE_SGMII:
2737 case PHY_INTERFACE_MODE_1000BASEX:
2738 case PHY_INTERFACE_MODE_2500BASEX:
5b89aeae 2739 return priv->ports[port].sgmii_pcs;
cbd1f243
RKO		 2740 default:
2741 return NULL;
2742 }
2743}
2744
88bdef8b
LC		 2745static void
2746mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2747 const struct phylink_link_state *state)
2748{
2749 struct mt7530_priv *priv = ds->priv;
2750 u32 mcr_cur, mcr_new;
2751
88bdef8b
LC		 2752 switch (port) {
2753 case 0 ... 4: /* Internal phy */
110c18bf
DG		 2754 if (state->interface != PHY_INTERFACE_MODE_GMII &&
2755 state->interface != PHY_INTERFACE_MODE_INTERNAL)
88bdef8b
LC		 2756 goto unsupported;
2757 break;
2758 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2759 if (priv->p5_interface == state->interface)
2760 break;
2761
2762 if (mt753x_mac_config(ds, port, mode, state) < 0)
2763 goto unsupported;
38f790a8 2764
c288575f
LC		 2765 if (priv->p5_intf_sel != P5_DISABLED)
2766 priv->p5_interface = state->interface;
38f790a8 2767 break;
ca366d6c
RD		 2768 case 6: /* 1st cpu port */
2769 if (priv->p6_interface == state->interface)
2770 break;
2771
88bdef8b 2772 mt753x_pad_setup(ds, state);
ca366d6c 2773
88bdef8b
LC		 2774 if (mt753x_mac_config(ds, port, mode, state) < 0)
2775 goto unsupported;
ca366d6c 2776
ca366d6c
RD		 2777 priv->p6_interface = state->interface;
2778 break;
2779 default:
88bdef8b
LC		 2780unsupported:
2781 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2782 __func__, phy_modes(state->interface), port);
ca366d6c
RD		 2783 return;
2784 }
2785
ca366d6c
RD		 2786 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2787 mcr_new = mcr_cur;
1d01145f 2788 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
ca366d6c 2789 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
c288575f 2790 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
ca366d6c 2791
38f790a8
RD		 2792 /* Are we connected to external phy */
2793 if (port == 5 && dsa_is_user_port(ds, 5))
2794 mcr_new |= PMCR_EXT_PHY;
2795
ca366d6c
RD		 2796 if (mcr_new != mcr_cur)
2797 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2798}
2799
c288575f 2800static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
ca366d6c
RD		 2801 unsigned int mode,
2802 phy_interface_t interface)
2803{
2804 struct mt7530_priv *priv = ds->priv;
2805
1d01145f 2806 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
ca366d6c
RD		 2807}
2808
cbd1f243
RKO		 2809static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs,
2810 unsigned int mode,
2811 phy_interface_t interface,
2812 int speed, int duplex)
c288575f 2813{
cbd1f243
RKO		 2814 if (pcs->ops->pcs_link_up)
2815 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
c288575f
LC		 2816}
2817
2818static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
ca366d6c
RD		 2819 unsigned int mode,
2820 phy_interface_t interface,
5b502a7b
RK		 2821 struct phy_device *phydev,
2822 int speed, int duplex,
2823 bool tx_pause, bool rx_pause)
ca366d6c
RD		 2824{
2825 struct mt7530_priv *priv = ds->priv;
1d01145f
RD		 2826 u32 mcr;
2827
2828 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2829
c288575f
LC		 2830 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2831 * variants.
2832 */
110c18bf
DG		 2833 if (interface == PHY_INTERFACE_MODE_INTERNAL ||
2834 interface == PHY_INTERFACE_MODE_TRGMII ||
c288575f
LC		 2835 (phy_interface_mode_is_8023z(interface))) {
2836 speed = SPEED_1000;
2837 duplex = DUPLEX_FULL;
2838 }
2839
1d01145f
RD		 2840 switch (speed) {
2841 case SPEED_1000:
2842 mcr |= PMCR_FORCE_SPEED_1000;
2843 break;
2844 case SPEED_100:
2845 mcr |= PMCR_FORCE_SPEED_100;
2846 break;
2847 }
2848 if (duplex == DUPLEX_FULL) {
2849 mcr |= PMCR_FORCE_FDX;
2850 if (tx_pause)
2851 mcr |= PMCR_TX_FC_EN;
2852 if (rx_pause)
2853 mcr |= PMCR_RX_FC_EN;
2854 }
ca366d6c 2855
53243d41 2856 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
40b5d2f1
RD		 2857 switch (speed) {
2858 case SPEED_1000:
2859 mcr |= PMCR_FORCE_EEE1G;
2860 break;
2861 case SPEED_100:
2862 mcr |= PMCR_FORCE_EEE100;
2863 break;
2864 }
2865 }
2866
1d01145f 2867 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
ca366d6c
RD		 2868}
2869
c288575f
LC		 2870static int
2871mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2872{
2873 struct mt7530_priv *priv = ds->priv;
2874 phy_interface_t interface;
2875 int speed;
0ce0c3cd 2876 int ret;
c288575f
LC		 2877
2878 switch (port) {
2879 case 5:
2880 if (mt7531_is_rgmii_port(priv, port))
2881 interface = PHY_INTERFACE_MODE_RGMII;
2882 else
2883 interface = PHY_INTERFACE_MODE_2500BASEX;
2884
2885 priv->p5_interface = interface;
2886 break;
2887 case 6:
2888 interface = PHY_INTERFACE_MODE_2500BASEX;
2889
c288575f
LC		 2890 priv->p6_interface = interface;
2891 break;
0ce0c3cd
AD		 2892 default:
2893 return -EINVAL;
c288575f
LC		 2894 }
2895
2896 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2897 speed = SPEED_2500;
2898 else
2899 speed = SPEED_1000;
2900
0ce0c3cd
AD		 2901 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2902 if (ret)
2903 return ret;
c288575f
LC		 2904 mt7530_write(priv, MT7530_PMCR_P(port),
2905 PMCR_CPU_PORT_SETTING(priv->id));
cbd1f243
RKO		 2906 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED,
2907 interface, speed, DUPLEX_FULL);
c288575f
LC		 2908 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2909 speed, DUPLEX_FULL, true, true);
2910
2911 return 0;
2912}
2913
110c18bf
DG		 2914static int
2915mt7988_cpu_port_config(struct dsa_switch *ds, int port)
2916{
2917 struct mt7530_priv *priv = ds->priv;
2918
2919 mt7530_write(priv, MT7530_PMCR_P(port),
2920 PMCR_CPU_PORT_SETTING(priv->id));
2921
2922 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
2923 PHY_INTERFACE_MODE_INTERNAL, NULL,
2924 SPEED_10000, DUPLEX_FULL, true, true);
2925
2926 return 0;
2927}
2928
59c2215f
RKO		 2929static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
2930 struct phylink_config *config)
2931{
2932 struct mt7530_priv *priv = ds->priv;
2933
2934 /* This switch only supports full-duplex at 1Gbps */
2935 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
2936 MAC_10 | MAC_100 | MAC_1000FD;
2937
7b972512
RKO		 2938 /* This driver does not make use of the speed, duplex, pause or the
2939 * advertisement in its mac_config, so it is safe to mark this driver
2940 * as non-legacy.
2941 */
2942 config->legacy_pre_march2020 = false;
2943
59c2215f
RKO		 2944 priv->info->mac_port_get_caps(ds, port, config);
2945}
2946
9d0df207
RKO		 2947static int mt753x_pcs_validate(struct phylink_pcs *pcs,
2948 unsigned long *supported,
2949 const struct phylink_link_state *state)
ca366d6c 2950{
9d0df207
RKO		 2951 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */
2952 if (state->interface == PHY_INTERFACE_MODE_TRGMII ||
2953 phy_interface_mode_is_8023z(state->interface))
2954 phylink_clear(supported, Autoneg);
ca366d6c 2955
9d0df207 2956 return 0;
ca366d6c
RD		 2957}
2958
cbd1f243
RKO		 2959static void mt7530_pcs_get_state(struct phylink_pcs *pcs,
2960 struct phylink_link_state *state)
ca366d6c 2961{
cbd1f243
RKO		 2962 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
2963 int port = pcs_to_mt753x_pcs(pcs)->port;
ca366d6c
RD		 2964 u32 pmsr;
2965
ca366d6c
RD		 2966 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2967
2968 state->link = (pmsr & PMSR_LINK);
2969 state->an_complete = state->link;
2970 state->duplex = !!(pmsr & PMSR_DPX);
2971
2972 switch (pmsr & PMSR_SPEED_MASK) {
2973 case PMSR_SPEED_10:
2974 state->speed = SPEED_10;
2975 break;
2976 case PMSR_SPEED_100:
2977 state->speed = SPEED_100;
2978 break;
2979 case PMSR_SPEED_1000:
2980 state->speed = SPEED_1000;
2981 break;
2982 default:
2983 state->speed = SPEED_UNKNOWN;
2984 break;
2985 }
2986
2987 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2988 if (pmsr & PMSR_RX_FC)
2989 state->pause |= MLO_PAUSE_RX;
2990 if (pmsr & PMSR_TX_FC)
2991 state->pause |= MLO_PAUSE_TX;
ca366d6c
RD		 2992}
2993
cbd1f243
RKO		 2994static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
2995 phy_interface_t interface,
2996 const unsigned long *advertising,
2997 bool permit_pause_to_mac)
88bdef8b 2998{
cbd1f243
RKO		 2999 return 0;
3000}
88bdef8b 3001
cbd1f243
RKO		 3002static void mt7530_pcs_an_restart(struct phylink_pcs *pcs)
3003{
88bdef8b
LC		 3004}
3005
cbd1f243 3006static const struct phylink_pcs_ops mt7530_pcs_ops = {
9d0df207 3007 .pcs_validate = mt753x_pcs_validate,
cbd1f243
RKO		 3008 .pcs_get_state = mt7530_pcs_get_state,
3009 .pcs_config = mt753x_pcs_config,
3010 .pcs_an_restart = mt7530_pcs_an_restart,
3011};
3012
88bdef8b
LC		 3013static int
3014mt753x_setup(struct dsa_switch *ds)
3015{
3016 struct mt7530_priv *priv = ds->priv;
fae46308
RKO		 3017 int i, ret;
3018
3019 /* Initialise the PCS devices */
3020 for (i = 0; i < priv->ds->num_ports; i++) {
3021 priv->pcs[i].pcs.ops = priv->info->pcs_ops;
3022 priv->pcs[i].priv = priv;
3023 priv->pcs[i].port = i;
3024 }
88bdef8b 3025
fae46308 3026 ret = priv->info->sw_setup(ds);
ba751e28
DQ		 3027 if (ret)
3028 return ret;
88bdef8b 3029
ba751e28
DQ		 3030 ret = mt7530_setup_irq(priv);
3031 if (ret)
3032 return ret;
88bdef8b 3033
ba751e28
DQ		 3034 ret = mt7530_setup_mdio(priv);
3035 if (ret && priv->irq)
3036 mt7530_free_irq_common(priv);
88bdef8b 3037
91daa4f6
DG		 3038 if (priv->create_sgmii) {
3039 ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv));
3040 if (ret && priv->irq)
3041 mt7530_free_irq(priv);
3042 }
3043
ba751e28 3044 return ret;
88bdef8b
LC		 3045}
3046
40b5d2f1
RD		 3047static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,
3048 struct ethtool_eee *e)
3049{
3050 struct mt7530_priv *priv = ds->priv;
3051 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
3052
3053 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
3054 e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
3055
3056 return 0;
3057}
3058
3059static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
3060 struct ethtool_eee *e)
3061{
3062 struct mt7530_priv *priv = ds->priv;
3063 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;
3064
3065 if (e->tx_lpi_timer > 0xFFF)
3066 return -EINVAL;
3067
3068 set = SET_LPI_THRESH(e->tx_lpi_timer);
3069 if (!e->tx_lpi_enabled)
3070 /* Force LPI Mode without a delay */
3071 set |= LPI_MODE_EN;
3072 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
3073
3074 return 0;
3075}
3076
110c18bf
DG		 3077static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
3078{
3079 return 0;
3080}
3081
3082static int mt7988_setup(struct dsa_switch *ds)
3083{
3084 struct mt7530_priv *priv = ds->priv;
3085
3086 /* Reset the switch */
3087 reset_control_assert(priv->rstc);
3088 usleep_range(20, 50);
3089 reset_control_deassert(priv->rstc);
3090 usleep_range(20, 50);
3091
3092 /* Reset the switch PHYs */
3093 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
3094
3095 return mt7531_setup_common(ds);
3096}
3097
cb675afc 3098const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8 3099 .get_tag_protocol = mtk_get_tag_protocol,
88bdef8b 3100 .setup = mt753x_setup,
b8f126a8 3101 .get_strings = mt7530_get_strings,
b8f126a8
SW		 3102 .get_ethtool_stats = mt7530_get_ethtool_stats,
3103 .get_sset_count = mt7530_get_sset_count,
ea6d5c92 3104 .set_ageing_time = mt7530_set_ageing_time,
b8f126a8
SW		 3105 .port_enable = mt7530_port_enable,
3106 .port_disable = mt7530_port_disable,
9470174e
DQ		 3107 .port_change_mtu = mt7530_port_change_mtu,
3108 .port_max_mtu = mt7530_port_max_mtu,
b8f126a8 3109 .port_stp_state_set = mt7530_stp_state_set,
5a30833b
DQ		 3110 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags,
3111 .port_bridge_flags = mt7530_port_bridge_flags,
b8f126a8
SW		 3112 .port_bridge_join = mt7530_port_bridge_join,
3113 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 3114 .port_fdb_add = mt7530_port_fdb_add,
3115 .port_fdb_del = mt7530_port_fdb_del,
3116 .port_fdb_dump = mt7530_port_fdb_dump,
5a30833b
DQ		 3117 .port_mdb_add = mt7530_port_mdb_add,
3118 .port_mdb_del = mt7530_port_mdb_del,
83163f7d 3119 .port_vlan_filtering = mt7530_port_vlan_filtering,
83163f7d
SW		 3120 .port_vlan_add = mt7530_port_vlan_add,
3121 .port_vlan_del = mt7530_port_vlan_del,
c288575f
LC		 3122 .port_mirror_add = mt753x_port_mirror_add,
3123 .port_mirror_del = mt753x_port_mirror_del,
59c2215f 3124 .phylink_get_caps = mt753x_phylink_get_caps,
cbd1f243 3125 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs,
88bdef8b 3126 .phylink_mac_config = mt753x_phylink_mac_config,
c288575f
LC		 3127 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
3128 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
40b5d2f1
RD		 3129 .get_mac_eee = mt753x_get_mac_eee,
3130 .set_mac_eee = mt753x_set_mac_eee,
b8f126a8 3131};
cb675afc 3132EXPORT_SYMBOL_GPL(mt7530_switch_ops);
b8f126a8 3133
cb675afc 3134const struct mt753x_info mt753x_table[] = {
88bdef8b
LC		 3135 [ID_MT7621] = {
3136 .id = ID_MT7621,
cbd1f243 3137 .pcs_ops = &mt7530_pcs_ops,
88bdef8b 3138 .sw_setup = mt7530_setup,
defa2e54
AL		 3139 .phy_read_c22 = mt7530_phy_read_c22,
3140 .phy_write_c22 = mt7530_phy_write_c22,
3141 .phy_read_c45 = mt7530_phy_read_c45,
3142 .phy_write_c45 = mt7530_phy_write_c45,
88bdef8b 3143 .pad_setup = mt7530_pad_clk_setup,
59c2215f 3144 .mac_port_get_caps = mt7530_mac_port_get_caps,
88bdef8b
LC		 3145 .mac_port_config = mt7530_mac_config,
3146 },
3147 [ID_MT7530] = {
3148 .id = ID_MT7530,
cbd1f243 3149 .pcs_ops = &mt7530_pcs_ops,
88bdef8b 3150 .sw_setup = mt7530_setup,
defa2e54
AL		 3151 .phy_read_c22 = mt7530_phy_read_c22,
3152 .phy_write_c22 = mt7530_phy_write_c22,
3153 .phy_read_c45 = mt7530_phy_read_c45,
3154 .phy_write_c45 = mt7530_phy_write_c45,
88bdef8b 3155 .pad_setup = mt7530_pad_clk_setup,
59c2215f 3156 .mac_port_get_caps = mt7530_mac_port_get_caps,
88bdef8b
LC		 3157 .mac_port_config = mt7530_mac_config,
3158 },
c288575f
LC		 3159 [ID_MT7531] = {
3160 .id = ID_MT7531,
5b89aeae 3161 .pcs_ops = &mt7530_pcs_ops,
c288575f 3162 .sw_setup = mt7531_setup,
defa2e54
AL		 3163 .phy_read_c22 = mt7531_ind_c22_phy_read,
3164 .phy_write_c22 = mt7531_ind_c22_phy_write,
3165 .phy_read_c45 = mt7531_ind_c45_phy_read,
3166 .phy_write_c45 = mt7531_ind_c45_phy_write,
c288575f
LC		 3167 .pad_setup = mt7531_pad_setup,
3168 .cpu_port_config = mt7531_cpu_port_config,
59c2215f 3169 .mac_port_get_caps = mt7531_mac_port_get_caps,
c288575f 3170 .mac_port_config = mt7531_mac_config,
c288575f 3171 },
110c18bf
DG		 3172 [ID_MT7988] = {
3173 .id = ID_MT7988,
3174 .pcs_ops = &mt7530_pcs_ops,
3175 .sw_setup = mt7988_setup,
3176 .phy_read_c22 = mt7531_ind_c22_phy_read,
3177 .phy_write_c22 = mt7531_ind_c22_phy_write,
3178 .phy_read_c45 = mt7531_ind_c45_phy_read,
3179 .phy_write_c45 = mt7531_ind_c45_phy_write,
3180 .pad_setup = mt7988_pad_setup,
3181 .cpu_port_config = mt7988_cpu_port_config,
3182 .mac_port_get_caps = mt7988_mac_port_get_caps,
3183 .mac_port_config = mt7988_mac_config,
3184 },
88bdef8b 3185};
cb675afc 3186EXPORT_SYMBOL_GPL(mt753x_table);
88bdef8b 3187
cb675afc 3188int
37c9c0d8 3189mt7530_probe_common(struct mt7530_priv *priv)
b8f126a8 3190{
37c9c0d8 3191 struct device *dev = priv->dev;
b8f126a8 3192
37c9c0d8 3193 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
b8f126a8
SW		 3194 if (!priv->ds)
3195 return -ENOMEM;
3196
37c9c0d8 3197 priv->ds->dev = dev;
342afce1 3198 priv->ds->num_ports = MT7530_NUM_PORTS;
7e99e347 3199
ddda1ac1
GU		 3200 /* Get the hardware identifier from the devicetree node.
3201 * We will need it for some of the clock and regulator setup.
3202 */
37c9c0d8 3203 priv->info = of_device_get_match_data(dev);
88bdef8b
LC		 3204 if (!priv->info)
3205 return -EINVAL;
3206
3207 /* Sanity check if these required device operations are filled
3208 * properly.
3209 */
3210 if (!priv->info->sw_setup || !priv->info->pad_setup ||
defa2e54 3211 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 ||
59c2215f 3212 !priv->info->mac_port_get_caps ||
cbd1f243 3213 !priv->info->mac_port_config)
88bdef8b
LC		 3214 return -EINVAL;
3215
3216 priv->id = priv->info->id;
37c9c0d8
DG		 3217 priv->dev = dev;
3218 priv->ds->priv = priv;
3219 priv->ds->ops = &mt7530_switch_ops;
3220 mutex_init(&priv->reg_mutex);
3221 dev_set_drvdata(dev, priv);
b8f126a8 3222
37c9c0d8
DG		 3223 return 0;
3224}
cb675afc 3225EXPORT_SYMBOL_GPL(mt7530_probe_common);
ddda1ac1 3226
cb675afc 3227void
720d7363
DG		 3228mt7530_remove_common(struct mt7530_priv *priv)
3229{
3230 if (priv->irq)
3231 mt7530_free_irq(priv);
3232
3233 dsa_unregister_switch(priv->ds);
3234
3235 mutex_destroy(&priv->reg_mutex);
3236}
cb675afc 3237EXPORT_SYMBOL_GPL(mt7530_remove_common);
b8f126a8
SW		 3238
3239MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
3240MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
3241MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)