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net: fec_ptp: remove redundant initialization of variable val
[linux-block.git] / drivers / net / dsa / mt7530.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
b8f126a8
SW		 2/*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
b8f126a8
SW		 5 */
6#include <linux/etherdevice.h>
7#include <linux/if_bridge.h>
8#include <linux/iopoll.h>
9#include <linux/mdio.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
ba751e28 13#include <linux/of_irq.h>
b8f126a8
SW		 14#include <linux/of_mdio.h>
15#include <linux/of_net.h>
16#include <linux/of_platform.h>
ca366d6c 17#include <linux/phylink.h>
b8f126a8
SW		 18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
eb976a55 21#include <linux/gpio/consumer.h>
429a0ede 22#include <linux/gpio/driver.h>
b8f126a8 23#include <net/dsa.h>
b8f126a8
SW		 24
25#include "mt7530.h"
26
27/* String, offset, and register size in bytes if different from 4 bytes */
28static const struct mt7530_mib_desc mt7530_mib[] = {
29 MIB_DESC(1, 0x00, "TxDrop"),
30 MIB_DESC(1, 0x04, "TxCrcErr"),
31 MIB_DESC(1, 0x08, "TxUnicast"),
32 MIB_DESC(1, 0x0c, "TxMulticast"),
33 MIB_DESC(1, 0x10, "TxBroadcast"),
34 MIB_DESC(1, 0x14, "TxCollision"),
35 MIB_DESC(1, 0x18, "TxSingleCollision"),
36 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
37 MIB_DESC(1, 0x20, "TxDeferred"),
38 MIB_DESC(1, 0x24, "TxLateCollision"),
39 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
40 MIB_DESC(1, 0x2c, "TxPause"),
41 MIB_DESC(1, 0x30, "TxPktSz64"),
42 MIB_DESC(1, 0x34, "TxPktSz65To127"),
43 MIB_DESC(1, 0x38, "TxPktSz128To255"),
44 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
45 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
46 MIB_DESC(1, 0x44, "Tx1024ToMax"),
47 MIB_DESC(2, 0x48, "TxBytes"),
48 MIB_DESC(1, 0x60, "RxDrop"),
49 MIB_DESC(1, 0x64, "RxFiltering"),
aff51c5d 50 MIB_DESC(1, 0x68, "RxUnicast"),
b8f126a8
SW		 51 MIB_DESC(1, 0x6c, "RxMulticast"),
52 MIB_DESC(1, 0x70, "RxBroadcast"),
53 MIB_DESC(1, 0x74, "RxAlignErr"),
54 MIB_DESC(1, 0x78, "RxCrcErr"),
55 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
56 MIB_DESC(1, 0x80, "RxFragErr"),
57 MIB_DESC(1, 0x84, "RxOverSzErr"),
58 MIB_DESC(1, 0x88, "RxJabberErr"),
59 MIB_DESC(1, 0x8c, "RxPause"),
60 MIB_DESC(1, 0x90, "RxPktSz64"),
61 MIB_DESC(1, 0x94, "RxPktSz65To127"),
62 MIB_DESC(1, 0x98, "RxPktSz128To255"),
63 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
64 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
65 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
66 MIB_DESC(2, 0xa8, "RxBytes"),
67 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
68 MIB_DESC(1, 0xb4, "RxIngressDrop"),
69 MIB_DESC(1, 0xb8, "RxArlDrop"),
70};
71
4732315c
IL		 72/* Since phy_device has not yet been created and
73 * phy_{read,write}_mmd_indirect is not available, we provide our own
74 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
75 * to complete this function.
76 */
b8f126a8
SW		 77static int
78core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
79{
80 struct mii_bus *bus = priv->bus;
81 int value, ret;
82
83 /* Write the desired MMD Devad */
84 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
85 if (ret < 0)
86 goto err;
87
88 /* Write the desired MMD register address */
89 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
90 if (ret < 0)
91 goto err;
92
93 /* Select the Function : DATA with no post increment */
94 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
95 if (ret < 0)
96 goto err;
97
98 /* Read the content of the MMD's selected register */
99 value = bus->read(bus, 0, MII_MMD_DATA);
100
101 return value;
102err:
103 dev_err(&bus->dev, "failed to read mmd register\n");
104
105 return ret;
106}
107
108static int
109core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
110 int devad, u32 data)
111{
112 struct mii_bus *bus = priv->bus;
113 int ret;
114
115 /* Write the desired MMD Devad */
116 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
117 if (ret < 0)
118 goto err;
119
120 /* Write the desired MMD register address */
121 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
122 if (ret < 0)
123 goto err;
124
125 /* Select the Function : DATA with no post increment */
126 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
127 if (ret < 0)
128 goto err;
129
130 /* Write the data into MMD's selected register */
131 ret = bus->write(bus, 0, MII_MMD_DATA, data);
132err:
133 if (ret < 0)
134 dev_err(&bus->dev,
135 "failed to write mmd register\n");
136 return ret;
137}
138
139static void
140core_write(struct mt7530_priv *priv, u32 reg, u32 val)
141{
142 struct mii_bus *bus = priv->bus;
143
144 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
145
146 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
147
148 mutex_unlock(&bus->mdio_lock);
149}
150
151static void
152core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
153{
154 struct mii_bus *bus = priv->bus;
155 u32 val;
156
157 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
158
159 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
160 val &= ~mask;
161 val |= set;
162 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
163
164 mutex_unlock(&bus->mdio_lock);
165}
166
167static void
168core_set(struct mt7530_priv *priv, u32 reg, u32 val)
169{
170 core_rmw(priv, reg, 0, val);
171}
172
173static void
174core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
175{
176 core_rmw(priv, reg, val, 0);
177}
178
179static int
180mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
181{
182 struct mii_bus *bus = priv->bus;
183 u16 page, r, lo, hi;
184 int ret;
185
186 page = (reg >> 6) & 0x3ff;
187 r = (reg >> 2) & 0xf;
188 lo = val & 0xffff;
189 hi = val >> 16;
190
191 /* MT7530 uses 31 as the pseudo port */
192 ret = bus->write(bus, 0x1f, 0x1f, page);
193 if (ret < 0)
194 goto err;
195
196 ret = bus->write(bus, 0x1f, r, lo);
197 if (ret < 0)
198 goto err;
199
200 ret = bus->write(bus, 0x1f, 0x10, hi);
201err:
202 if (ret < 0)
203 dev_err(&bus->dev,
204 "failed to write mt7530 register\n");
205 return ret;
206}
207
208static u32
209mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
210{
211 struct mii_bus *bus = priv->bus;
212 u16 page, r, lo, hi;
213 int ret;
214
215 page = (reg >> 6) & 0x3ff;
216 r = (reg >> 2) & 0xf;
217
218 /* MT7530 uses 31 as the pseudo port */
219 ret = bus->write(bus, 0x1f, 0x1f, page);
220 if (ret < 0) {
221 dev_err(&bus->dev,
222 "failed to read mt7530 register\n");
223 return ret;
224 }
225
226 lo = bus->read(bus, 0x1f, r);
227 hi = bus->read(bus, 0x1f, 0x10);
228
229 return (hi << 16) | (lo & 0xffff);
230}
231
232static void
233mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
234{
235 struct mii_bus *bus = priv->bus;
236
237 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
238
239 mt7530_mii_write(priv, reg, val);
240
241 mutex_unlock(&bus->mdio_lock);
242}
243
c288575f
LC		 244static u32
245_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
246{
247 return mt7530_mii_read(p->priv, p->reg);
248}
249
b8f126a8
SW		 250static u32
251_mt7530_read(struct mt7530_dummy_poll *p)
252{
253 struct mii_bus *bus = p->priv->bus;
254 u32 val;
255
256 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
257
258 val = mt7530_mii_read(p->priv, p->reg);
259
260 mutex_unlock(&bus->mdio_lock);
261
262 return val;
263}
264
265static u32
266mt7530_read(struct mt7530_priv *priv, u32 reg)
267{
268 struct mt7530_dummy_poll p;
269
270 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
271 return _mt7530_read(&p);
272}
273
274static void
275mt7530_rmw(struct mt7530_priv *priv, u32 reg,
276 u32 mask, u32 set)
277{
278 struct mii_bus *bus = priv->bus;
279 u32 val;
280
281 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
282
283 val = mt7530_mii_read(priv, reg);
284 val &= ~mask;
285 val |= set;
286 mt7530_mii_write(priv, reg, val);
287
288 mutex_unlock(&bus->mdio_lock);
289}
290
291static void
292mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
293{
294 mt7530_rmw(priv, reg, 0, val);
295}
296
297static void
298mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
299{
300 mt7530_rmw(priv, reg, val, 0);
301}
302
303static int
304mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
305{
306 u32 val;
307 int ret;
308 struct mt7530_dummy_poll p;
309
310 /* Set the command operating upon the MAC address entries */
311 val = ATC_BUSY | ATC_MAT(0) | cmd;
312 mt7530_write(priv, MT7530_ATC, val);
313
314 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
315 ret = readx_poll_timeout(_mt7530_read, &p, val,
316 !(val & ATC_BUSY), 20, 20000);
317 if (ret < 0) {
318 dev_err(priv->dev, "reset timeout\n");
319 return ret;
320 }
321
322 /* Additional sanity for read command if the specified
323 * entry is invalid
324 */
325 val = mt7530_read(priv, MT7530_ATC);
326 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
327 return -EINVAL;
328
329 if (rsp)
330 *rsp = val;
331
332 return 0;
333}
334
335static void
336mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
337{
338 u32 reg[3];
339 int i;
340
341 /* Read from ARL table into an array */
342 for (i = 0; i < 3; i++) {
343 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
344
345 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
346 __func__, __LINE__, i, reg[i]);
347 }
348
349 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
350 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
351 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
352 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
353 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
354 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
355 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
356 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
357 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
358 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
359}
360
361static void
362mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
363 u8 port_mask, const u8 *mac,
364 u8 aging, u8 type)
365{
366 u32 reg[3] = { 0 };
367 int i;
368
369 reg[1] |= vid & CVID_MASK;
73c447ca
DQ		 370 reg[1] |= ATA2_IVL;
371 reg[1] |= ATA2_FID(FID_BRIDGED);
b8f126a8
SW		 372 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
373 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
374 /* STATIC_ENT indicate that entry is static wouldn't
375 * be aged out and STATIC_EMP specified as erasing an
376 * entry
377 */
378 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
379 reg[1] |= mac[5] << MAC_BYTE_5;
380 reg[1] |= mac[4] << MAC_BYTE_4;
381 reg[0] |= mac[3] << MAC_BYTE_3;
382 reg[0] |= mac[2] << MAC_BYTE_2;
383 reg[0] |= mac[1] << MAC_BYTE_1;
384 reg[0] |= mac[0] << MAC_BYTE_0;
385
386 /* Write array into the ARL table */
387 for (i = 0; i < 3; i++)
388 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
389}
390
88bdef8b 391/* Setup TX circuit including relevant PAD and driving */
b8f126a8 392static int
88bdef8b 393mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
b8f126a8
SW		 394{
395 struct mt7530_priv *priv = ds->priv;
7ef6f6f8
RD		 396 u32 ncpo1, ssc_delta, trgint, i, xtal;
397
398 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
399
400 if (xtal == HWTRAP_XTAL_20MHZ) {
401 dev_err(priv->dev,
402 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
403 __func__);
404 return -EINVAL;
405 }
b8f126a8 406
88bdef8b 407 switch (interface) {
b8f126a8
SW		 408 case PHY_INTERFACE_MODE_RGMII:
409 trgint = 0;
7ef6f6f8 410 /* PLL frequency: 125MHz */
b8f126a8 411 ncpo1 = 0x0c80;
b8f126a8
SW		 412 break;
413 case PHY_INTERFACE_MODE_TRGMII:
414 trgint = 1;
7ef6f6f8
RD		 415 if (priv->id == ID_MT7621) {
416 /* PLL frequency: 150MHz: 1.2GBit */
417 if (xtal == HWTRAP_XTAL_40MHZ)
418 ncpo1 = 0x0780;
419 if (xtal == HWTRAP_XTAL_25MHZ)
420 ncpo1 = 0x0a00;
421 } else { /* PLL frequency: 250MHz: 2.0Gbit */
422 if (xtal == HWTRAP_XTAL_40MHZ)
423 ncpo1 = 0x0c80;
424 if (xtal == HWTRAP_XTAL_25MHZ)
425 ncpo1 = 0x1400;
426 }
b8f126a8
SW		 427 break;
428 default:
88bdef8b
LC		 429 dev_err(priv->dev, "xMII interface %d not supported\n",
430 interface);
b8f126a8
SW		 431 return -EINVAL;
432 }
433
7ef6f6f8
RD		 434 if (xtal == HWTRAP_XTAL_25MHZ)
435 ssc_delta = 0x57;
436 else
437 ssc_delta = 0x87;
438
b8f126a8
SW		 439 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
440 P6_INTF_MODE(trgint));
441
442 /* Lower Tx Driving for TRGMII path */
443 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
444 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
445 TD_DM_DRVP(8) | TD_DM_DRVN(8));
446
4732315c
IL		 447 /* Disable MT7530 core and TRGMII Tx clocks */
448 core_clear(priv, CORE_TRGMII_GSW_CLK_CG,
449 REG_GSWCK_EN | REG_TRGMIICK_EN);
c3b8e079 450
4732315c
IL		 451 /* Setup core clock for MT7530 */
452 /* Disable PLL */
453 core_write(priv, CORE_GSWPLL_GRP1, 0);
c3b8e079
IL		 454
455 /* Set core clock into 500Mhz */
456 core_write(priv, CORE_GSWPLL_GRP2,
457 RG_GSWPLL_POSDIV_500M(1) |
458 RG_GSWPLL_FBKDIV_500M(25));
459
460 /* Enable PLL */
461 core_write(priv, CORE_GSWPLL_GRP1,
462 RG_GSWPLL_EN_PRE |
463 RG_GSWPLL_POSDIV_200M(2) |
464 RG_GSWPLL_FBKDIV_200M(32));
465
b8f126a8 466 /* Setup the MT7530 TRGMII Tx Clock */
b8f126a8
SW		 467 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
468 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
469 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
470 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
471 core_write(priv, CORE_PLL_GROUP4,
472 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
473 RG_SYSPLL_BIAS_LPF_EN);
474 core_write(priv, CORE_PLL_GROUP2,
475 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
476 RG_SYSPLL_POSDIV(1));
477 core_write(priv, CORE_PLL_GROUP7,
478 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
479 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
4732315c
IL		 480
481 /* Enable MT7530 core and TRGMII Tx clocks */
b8f126a8
SW		 482 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
483 REG_GSWCK_EN | REG_TRGMIICK_EN);
484
485 if (!trgint)
486 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
487 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
488 RD_TAP_MASK, RD_TAP(16));
b8f126a8
SW		 489 return 0;
490}
491
c288575f
LC		 492static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
493{
494 u32 val;
495
496 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
497
498 return (val & PAD_DUAL_SGMII_EN) != 0;
499}
500
501static int
502mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
503{
504 struct mt7530_priv *priv = ds->priv;
505 u32 top_sig;
506 u32 hwstrap;
507 u32 xtal;
508 u32 val;
509
510 if (mt7531_dual_sgmii_supported(priv))
511 return 0;
512
513 val = mt7530_read(priv, MT7531_CREV);
514 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
515 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
516 if ((val & CHIP_REV_M) > 0)
517 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
518 HWTRAP_XTAL_FSEL_25MHZ;
519 else
520 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
521
522 /* Step 1 : Disable MT7531 COREPLL */
523 val = mt7530_read(priv, MT7531_PLLGP_EN);
524 val &= ~EN_COREPLL;
525 mt7530_write(priv, MT7531_PLLGP_EN, val);
526
527 /* Step 2: switch to XTAL output */
528 val = mt7530_read(priv, MT7531_PLLGP_EN);
529 val |= SW_CLKSW;
530 mt7530_write(priv, MT7531_PLLGP_EN, val);
531
532 val = mt7530_read(priv, MT7531_PLLGP_CR0);
533 val &= ~RG_COREPLL_EN;
534 mt7530_write(priv, MT7531_PLLGP_CR0, val);
535
536 /* Step 3: disable PLLGP and enable program PLLGP */
537 val = mt7530_read(priv, MT7531_PLLGP_EN);
538 val |= SW_PLLGP;
539 mt7530_write(priv, MT7531_PLLGP_EN, val);
540
541 /* Step 4: program COREPLL output frequency to 500MHz */
542 val = mt7530_read(priv, MT7531_PLLGP_CR0);
543 val &= ~RG_COREPLL_POSDIV_M;
544 val |= 2 << RG_COREPLL_POSDIV_S;
545 mt7530_write(priv, MT7531_PLLGP_CR0, val);
546 usleep_range(25, 35);
547
548 switch (xtal) {
549 case HWTRAP_XTAL_FSEL_25MHZ:
550 val = mt7530_read(priv, MT7531_PLLGP_CR0);
551 val &= ~RG_COREPLL_SDM_PCW_M;
552 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
553 mt7530_write(priv, MT7531_PLLGP_CR0, val);
554 break;
555 case HWTRAP_XTAL_FSEL_40MHZ:
556 val = mt7530_read(priv, MT7531_PLLGP_CR0);
557 val &= ~RG_COREPLL_SDM_PCW_M;
558 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
559 mt7530_write(priv, MT7531_PLLGP_CR0, val);
560 break;
0e8c266c 561 }
c288575f
LC		 562
563 /* Set feedback divide ratio update signal to high */
564 val = mt7530_read(priv, MT7531_PLLGP_CR0);
565 val |= RG_COREPLL_SDM_PCW_CHG;
566 mt7530_write(priv, MT7531_PLLGP_CR0, val);
567 /* Wait for at least 16 XTAL clocks */
568 usleep_range(10, 20);
569
570 /* Step 5: set feedback divide ratio update signal to low */
571 val = mt7530_read(priv, MT7531_PLLGP_CR0);
572 val &= ~RG_COREPLL_SDM_PCW_CHG;
573 mt7530_write(priv, MT7531_PLLGP_CR0, val);
574
575 /* Enable 325M clock for SGMII */
576 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
577
578 /* Enable 250SSC clock for RGMII */
579 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
580
581 /* Step 6: Enable MT7531 PLL */
582 val = mt7530_read(priv, MT7531_PLLGP_CR0);
583 val |= RG_COREPLL_EN;
584 mt7530_write(priv, MT7531_PLLGP_CR0, val);
585
586 val = mt7530_read(priv, MT7531_PLLGP_EN);
587 val |= EN_COREPLL;
588 mt7530_write(priv, MT7531_PLLGP_EN, val);
589 usleep_range(25, 35);
590
591 return 0;
592}
593
b8f126a8
SW		 594static void
595mt7530_mib_reset(struct dsa_switch *ds)
596{
597 struct mt7530_priv *priv = ds->priv;
598
599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
601}
602
ba751e28 603static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum)
b8f126a8 604{
b8f126a8
SW		 605 return mdiobus_read_nested(priv->bus, port, regnum);
606}
607
ba751e28 608static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum,
360cc342 609 u16 val)
b8f126a8 610{
b8f126a8
SW		 611 return mdiobus_write_nested(priv->bus, port, regnum, val);
612}
613
c288575f
LC		 614static int
615mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
616 int regnum)
617{
618 struct mii_bus *bus = priv->bus;
619 struct mt7530_dummy_poll p;
620 u32 reg, val;
621 int ret;
622
623 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
624
625 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
626
627 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
628 !(val & MT7531_PHY_ACS_ST), 20, 100000);
629 if (ret < 0) {
630 dev_err(priv->dev, "poll timeout\n");
631 goto out;
632 }
633
634 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
635 MT7531_MDIO_DEV_ADDR(devad) | regnum;
636 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
637
638 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
639 !(val & MT7531_PHY_ACS_ST), 20, 100000);
640 if (ret < 0) {
641 dev_err(priv->dev, "poll timeout\n");
642 goto out;
643 }
644
645 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
646 MT7531_MDIO_DEV_ADDR(devad);
647 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
648
649 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
650 !(val & MT7531_PHY_ACS_ST), 20, 100000);
651 if (ret < 0) {
652 dev_err(priv->dev, "poll timeout\n");
653 goto out;
654 }
655
656 ret = val & MT7531_MDIO_RW_DATA_MASK;
657out:
658 mutex_unlock(&bus->mdio_lock);
659
660 return ret;
661}
662
663static int
664mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
665 int regnum, u32 data)
666{
667 struct mii_bus *bus = priv->bus;
668 struct mt7530_dummy_poll p;
669 u32 val, reg;
670 int ret;
671
672 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
673
674 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
675
676 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
677 !(val & MT7531_PHY_ACS_ST), 20, 100000);
678 if (ret < 0) {
679 dev_err(priv->dev, "poll timeout\n");
680 goto out;
681 }
682
683 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
684 MT7531_MDIO_DEV_ADDR(devad) | regnum;
685 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
686
687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
688 !(val & MT7531_PHY_ACS_ST), 20, 100000);
689 if (ret < 0) {
690 dev_err(priv->dev, "poll timeout\n");
691 goto out;
692 }
693
694 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
695 MT7531_MDIO_DEV_ADDR(devad) | data;
696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
697
698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
699 !(val & MT7531_PHY_ACS_ST), 20, 100000);
700 if (ret < 0) {
701 dev_err(priv->dev, "poll timeout\n");
702 goto out;
703 }
704
705out:
706 mutex_unlock(&bus->mdio_lock);
707
708 return ret;
709}
710
711static int
712mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
713{
714 struct mii_bus *bus = priv->bus;
715 struct mt7530_dummy_poll p;
716 int ret;
717 u32 val;
718
719 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
720
721 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
722
723 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
724 !(val & MT7531_PHY_ACS_ST), 20, 100000);
725 if (ret < 0) {
726 dev_err(priv->dev, "poll timeout\n");
727 goto out;
728 }
729
730 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
731 MT7531_MDIO_REG_ADDR(regnum);
732
733 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
734
735 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
736 !(val & MT7531_PHY_ACS_ST), 20, 100000);
737 if (ret < 0) {
738 dev_err(priv->dev, "poll timeout\n");
739 goto out;
740 }
741
742 ret = val & MT7531_MDIO_RW_DATA_MASK;
743out:
744 mutex_unlock(&bus->mdio_lock);
745
746 return ret;
747}
748
749static int
750mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
751 u16 data)
752{
753 struct mii_bus *bus = priv->bus;
754 struct mt7530_dummy_poll p;
755 int ret;
756 u32 reg;
757
758 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
759
760 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
761
762 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
763 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
764 if (ret < 0) {
765 dev_err(priv->dev, "poll timeout\n");
766 goto out;
767 }
768
769 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
770 MT7531_MDIO_REG_ADDR(regnum) | data;
771
772 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
773
774 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
775 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
776 if (ret < 0) {
777 dev_err(priv->dev, "poll timeout\n");
778 goto out;
779 }
780
781out:
782 mutex_unlock(&bus->mdio_lock);
783
784 return ret;
785}
786
787static int
ba751e28 788mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum)
c288575f 789{
c288575f
LC		 790 int devad;
791 int ret;
792
793 if (regnum & MII_ADDR_C45) {
794 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
795 ret = mt7531_ind_c45_phy_read(priv, port, devad,
796 regnum & MII_REGADDR_C45_MASK);
797 } else {
798 ret = mt7531_ind_c22_phy_read(priv, port, regnum);
799 }
800
801 return ret;
802}
803
804static int
ba751e28 805mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum,
c288575f
LC		 806 u16 data)
807{
c288575f
LC		 808 int devad;
809 int ret;
810
811 if (regnum & MII_ADDR_C45) {
812 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
813 ret = mt7531_ind_c45_phy_write(priv, port, devad,
814 regnum & MII_REGADDR_C45_MASK,
815 data);
816 } else {
817 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
818 }
819
820 return ret;
821}
822
ba751e28
DQ		 823static int
824mt753x_phy_read(struct mii_bus *bus, int port, int regnum)
825{
826 struct mt7530_priv *priv = bus->priv;
827
828 return priv->info->phy_read(priv, port, regnum);
829}
830
831static int
832mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val)
833{
834 struct mt7530_priv *priv = bus->priv;
835
836 return priv->info->phy_write(priv, port, regnum, val);
837}
838
b8f126a8 839static void
89f09048
FF		 840mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
841 uint8_t *data)
b8f126a8
SW		 842{
843 int i;
844
89f09048
FF		 845 if (stringset != ETH_SS_STATS)
846 return;
847
b8f126a8
SW		 848 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
849 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
850 ETH_GSTRING_LEN);
851}
852
853static void
854mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
855 uint64_t *data)
856{
857 struct mt7530_priv *priv = ds->priv;
858 const struct mt7530_mib_desc *mib;
859 u32 reg, i;
860 u64 hi;
861
862 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
863 mib = &mt7530_mib[i];
864 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
865
866 data[i] = mt7530_read(priv, reg);
867 if (mib->size == 2) {
868 hi = mt7530_read(priv, reg + 4);
869 data[i] |= hi << 32;
870 }
871 }
872}
873
874static int
89f09048 875mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
b8f126a8 876{
89f09048
FF		 877 if (sset != ETH_SS_STATS)
878 return 0;
879
b8f126a8
SW		 880 return ARRAY_SIZE(mt7530_mib);
881}
882
ea6d5c92
DQ		 883static int
884mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
885{
886 struct mt7530_priv *priv = ds->priv;
887 unsigned int secs = msecs / 1000;
888 unsigned int tmp_age_count;
889 unsigned int error = -1;
890 unsigned int age_count;
891 unsigned int age_unit;
892
893 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
894 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
895 return -ERANGE;
896
897 /* iterate through all possible age_count to find the closest pair */
898 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
899 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
900
901 if (tmp_age_unit <= AGE_UNIT_MAX) {
902 unsigned int tmp_error = secs -
903 (tmp_age_count + 1) * (tmp_age_unit + 1);
904
905 /* found a closer pair */
906 if (error > tmp_error) {
907 error = tmp_error;
908 age_count = tmp_age_count;
909 age_unit = tmp_age_unit;
910 }
911
912 /* found the exact match, so break the loop */
913 if (!error)
914 break;
915 }
916 }
917
918 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
919
920 return 0;
921}
922
38f790a8
RD		 923static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
924{
925 struct mt7530_priv *priv = ds->priv;
926 u8 tx_delay = 0;
927 int val;
928
929 mutex_lock(&priv->reg_mutex);
930
931 val = mt7530_read(priv, MT7530_MHWTRAP);
932
933 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
934 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
935
936 switch (priv->p5_intf_sel) {
937 case P5_INTF_SEL_PHY_P0:
938 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
939 val |= MHWTRAP_PHY0_SEL;
df561f66 940 fallthrough;
38f790a8
RD		 941 case P5_INTF_SEL_PHY_P4:
942 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
943 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
944
945 /* Setup the MAC by default for the cpu port */
946 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
947 break;
948 case P5_INTF_SEL_GMAC5:
949 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
950 val &= ~MHWTRAP_P5_DIS;
951 break;
952 case P5_DISABLED:
953 interface = PHY_INTERFACE_MODE_NA;
954 break;
955 default:
956 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
957 priv->p5_intf_sel);
958 goto unlock_exit;
959 }
960
961 /* Setup RGMII settings */
962 if (phy_interface_mode_is_rgmii(interface)) {
963 val |= MHWTRAP_P5_RGMII_MODE;
964
965 /* P5 RGMII RX Clock Control: delay setting for 1000M */
966 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
967
968 /* Don't set delay in DSA mode */
969 if (!dsa_is_dsa_port(priv->ds, 5) &&
970 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
971 interface == PHY_INTERFACE_MODE_RGMII_ID))
972 tx_delay = 4; /* n * 0.5 ns */
973
974 /* P5 RGMII TX Clock Control: delay x */
975 mt7530_write(priv, MT7530_P5RGMIITXCR,
976 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
977
978 /* reduce P5 RGMII Tx driving, 8mA */
979 mt7530_write(priv, MT7530_IO_DRV_CR,
980 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
981 }
982
983 mt7530_write(priv, MT7530_MHWTRAP, val);
984
985 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
986 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
987
988 priv->p5_interface = interface;
989
990unlock_exit:
991 mutex_unlock(&priv->reg_mutex);
992}
993
b8f126a8 994static int
c288575f 995mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
b8f126a8 996{
c288575f 997 struct mt7530_priv *priv = ds->priv;
0ce0c3cd 998 int ret;
c288575f
LC		 999
1000 /* Setup max capability of CPU port at first */
0ce0c3cd
AD		 1001 if (priv->info->cpu_port_config) {
1002 ret = priv->info->cpu_port_config(ds, port);
1003 if (ret)
1004 return ret;
1005 }
c288575f 1006
b8f126a8
SW		 1007 /* Enable Mediatek header mode on the cpu port */
1008 mt7530_write(priv, MT7530_PVC_P(port),
1009 PORT_SPEC_TAG);
1010
5a30833b
DQ		 1011 /* Disable flooding by default */
1012 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK,
1013 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port)));
b8f126a8 1014
ddda1ac1
GU		 1015 /* Set CPU port number */
1016 if (priv->id == ID_MT7621)
1017 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1018
b8f126a8 1019 /* CPU port gets connected to all user ports of
c288575f 1020 * the switch.
b8f126a8
SW		 1021 */
1022 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 1023 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8 1024
6087175b
DQ		 1025 /* Set to fallback mode for independent VLAN learning */
1026 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1027 MT7530_PORT_FALLBACK_MODE);
1028
b8f126a8
SW		 1029 return 0;
1030}
1031
1032static int
1033mt7530_port_enable(struct dsa_switch *ds, int port,
1034 struct phy_device *phy)
1035{
1036 struct mt7530_priv *priv = ds->priv;
1037
1038 mutex_lock(&priv->reg_mutex);
1039
b8f126a8
SW		 1040 /* Allow the user port gets connected to the cpu port and also
1041 * restore the port matrix if the port is the member of a certain
1042 * bridge.
1043 */
1044 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
1045 priv->ports[port].enable = true;
1046 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1047 priv->ports[port].pm);
1d01145f 1048 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1049
1050 mutex_unlock(&priv->reg_mutex);
1051
1052 return 0;
1053}
1054
1055static void
75104db0 1056mt7530_port_disable(struct dsa_switch *ds, int port)
b8f126a8
SW		 1057{
1058 struct mt7530_priv *priv = ds->priv;
1059
1060 mutex_lock(&priv->reg_mutex);
1061
1062 /* Clear up all port matrix which could be restored in the next
1063 * enablement for the port.
1064 */
1065 priv->ports[port].enable = false;
1066 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1067 PCR_MATRIX_CLR);
1d01145f 1068 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1069
1070 mutex_unlock(&priv->reg_mutex);
1071}
1072
9470174e
DQ		 1073static int
1074mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1075{
1076 struct mt7530_priv *priv = ds->priv;
1077 struct mii_bus *bus = priv->bus;
1078 int length;
1079 u32 val;
1080
1081 /* When a new MTU is set, DSA always set the CPU port's MTU to the
1082 * largest MTU of the slave ports. Because the switch only has a global
1083 * RX length register, only allowing CPU port here is enough.
1084 */
1085 if (!dsa_is_cpu_port(ds, port))
1086 return 0;
1087
1088 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1089
1090 val = mt7530_mii_read(priv, MT7530_GMACCR);
1091 val &= ~MAX_RX_PKT_LEN_MASK;
1092
1093 /* RX length also includes Ethernet header, MTK tag, and FCS length */
1094 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1095 if (length <= 1522) {
1096 val |= MAX_RX_PKT_LEN_1522;
1097 } else if (length <= 1536) {
1098 val |= MAX_RX_PKT_LEN_1536;
1099 } else if (length <= 1552) {
1100 val |= MAX_RX_PKT_LEN_1552;
1101 } else {
1102 val &= ~MAX_RX_JUMBO_MASK;
1103 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1104 val |= MAX_RX_PKT_LEN_JUMBO;
1105 }
1106
1107 mt7530_mii_write(priv, MT7530_GMACCR, val);
1108
1109 mutex_unlock(&bus->mdio_lock);
1110
1111 return 0;
1112}
1113
1114static int
1115mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1116{
1117 return MT7530_MAX_MTU;
1118}
1119
b8f126a8
SW		 1120static void
1121mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1122{
1123 struct mt7530_priv *priv = ds->priv;
1124 u32 stp_state;
1125
1126 switch (state) {
1127 case BR_STATE_DISABLED:
1128 stp_state = MT7530_STP_DISABLED;
1129 break;
1130 case BR_STATE_BLOCKING:
1131 stp_state = MT7530_STP_BLOCKING;
1132 break;
1133 case BR_STATE_LISTENING:
1134 stp_state = MT7530_STP_LISTENING;
1135 break;
1136 case BR_STATE_LEARNING:
1137 stp_state = MT7530_STP_LEARNING;
1138 break;
1139 case BR_STATE_FORWARDING:
1140 default:
1141 stp_state = MT7530_STP_FORWARDING;
1142 break;
1143 }
1144
a9e3f62d
DQ		 1145 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED),
1146 FID_PST(FID_BRIDGED, stp_state));
b8f126a8
SW		 1147}
1148
5a30833b
DQ		 1149static int
1150mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1151 struct switchdev_brport_flags flags,
1152 struct netlink_ext_ack *extack)
1153{
1154 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1155 BR_BCAST_FLOOD))
1156 return -EINVAL;
1157
1158 return 0;
1159}
1160
1161static int
1162mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
1163 struct switchdev_brport_flags flags,
1164 struct netlink_ext_ack *extack)
1165{
1166 struct mt7530_priv *priv = ds->priv;
1167
1168 if (flags.mask & BR_LEARNING)
1169 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
1170 flags.val & BR_LEARNING ? 0 : SA_DIS);
1171
1172 if (flags.mask & BR_FLOOD)
1173 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
1174 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1175
1176 if (flags.mask & BR_MCAST_FLOOD)
1177 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1178 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1179
1180 if (flags.mask & BR_BCAST_FLOOD)
1181 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
1182 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1183
1184 return 0;
1185}
1186
b8f126a8
SW		 1187static int
1188mt7530_port_bridge_join(struct dsa_switch *ds, int port,
b079922b 1189 struct dsa_bridge bridge, bool *tx_fwd_offload)
b8f126a8 1190{
872bb81d 1191 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
b8f126a8 1192 u32 port_bitmap = BIT(MT7530_CPU_PORT);
872bb81d 1193 struct mt7530_priv *priv = ds->priv;
b8f126a8
SW		 1194
1195 mutex_lock(&priv->reg_mutex);
1196
872bb81d
VO		 1197 dsa_switch_for_each_user_port(other_dp, ds) {
1198 int other_port = other_dp->index;
1199
1200 if (dp == other_dp)
1201 continue;
1202
b8f126a8
SW		 1203 /* Add this port to the port matrix of the other ports in the
1204 * same bridge. If the port is disabled, port matrix is kept
1205 * and not being setup until the port becomes enabled.
1206 */
d3eed0e5 1207 if (!dsa_port_offloads_bridge(other_dp, &bridge))
872bb81d
VO		 1208 continue;
1209
1210 if (priv->ports[other_port].enable)
1211 mt7530_set(priv, MT7530_PCR_P(other_port),
1212 PCR_MATRIX(BIT(port)));
1213 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port));
1214
1215 port_bitmap |= BIT(other_port);
b8f126a8
SW		 1216 }
1217
1218 /* Add the all other ports to this port matrix. */
1219 if (priv->ports[port].enable)
1220 mt7530_rmw(priv, MT7530_PCR_P(port),
1221 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1222 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1223
6087175b
DQ		 1224 /* Set to fallback mode for independent VLAN learning */
1225 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1226 MT7530_PORT_FALLBACK_MODE);
1227
b8f126a8
SW		 1228 mutex_unlock(&priv->reg_mutex);
1229
1230 return 0;
1231}
1232
83163f7d
SW		 1233static void
1234mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1235{
1236 struct mt7530_priv *priv = ds->priv;
1237 bool all_user_ports_removed = true;
1238 int i;
1239
6087175b
DQ		 1240 /* This is called after .port_bridge_leave when leaving a VLAN-aware
1241 * bridge. Don't set standalone ports to fallback mode.
83163f7d 1242 */
41fb0cf1 1243 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
6087175b
DQ		 1244 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1245 MT7530_PORT_FALLBACK_MODE);
1246
8fbebef8
DQ		 1247 mt7530_rmw(priv, MT7530_PVC_P(port),
1248 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
e045124e 1249 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
8fbebef8
DQ		 1250 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
1251 MT7530_VLAN_ACC_ALL);
83163f7d 1252
6087175b
DQ		 1253 /* Set PVID to 0 */
1254 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1255 G0_PORT_VID_DEF);
1256
83163f7d
SW		 1257 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1258 if (dsa_is_user_port(ds, i) &&
68bb8ea8 1259 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
83163f7d
SW		 1260 all_user_ports_removed = false;
1261 break;
1262 }
1263 }
1264
1265 /* CPU port also does the same thing until all user ports belonging to
1266 * the CPU port get out of VLAN filtering mode.
1267 */
1268 if (all_user_ports_removed) {
1269 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
1270 PCR_MATRIX(dsa_user_ports(priv->ds)));
e045124e
DQ		 1271 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
1272 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d
SW		 1273 }
1274}
1275
1276static void
1277mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1278{
1279 struct mt7530_priv *priv = ds->priv;
1280
83163f7d 1281 /* Trapped into security mode allows packet forwarding through VLAN
6087175b 1282 * table lookup.
83163f7d 1283 */
6087175b 1284 if (dsa_is_user_port(ds, port)) {
38152ea3
DQ		 1285 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1286 MT7530_PORT_SECURITY_MODE);
6087175b
DQ		 1287 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1288 G0_PORT_VID(priv->ports[port].pvid));
8fbebef8
DQ		 1289
1290 /* Only accept tagged frames if PVID is not set */
1291 if (!priv->ports[port].pvid)
1292 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1293 MT7530_VLAN_ACC_TAGGED);
6087175b 1294 }
83163f7d
SW		 1295
1296 /* Set the port as a user port which is to be able to recognize VID
1297 * from incoming packets before fetching entry within the VLAN table.
1298 */
e045124e
DQ		 1299 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1300 VLAN_ATTR(MT7530_VLAN_USER) |
1301 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
83163f7d
SW		 1302}
1303
b8f126a8
SW		 1304static void
1305mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
d3eed0e5 1306 struct dsa_bridge bridge)
b8f126a8 1307{
872bb81d 1308 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
b8f126a8 1309 struct mt7530_priv *priv = ds->priv;
b8f126a8
SW		 1310
1311 mutex_lock(&priv->reg_mutex);
1312
872bb81d
VO		 1313 dsa_switch_for_each_user_port(other_dp, ds) {
1314 int other_port = other_dp->index;
1315
1316 if (dp == other_dp)
1317 continue;
1318
b8f126a8
SW		 1319 /* Remove this port from the port matrix of the other ports
1320 * in the same bridge. If the port is disabled, port matrix
1321 * is kept and not being setup until the port becomes enabled.
1322 */
d3eed0e5 1323 if (!dsa_port_offloads_bridge(other_dp, &bridge))
872bb81d
VO		 1324 continue;
1325
1326 if (priv->ports[other_port].enable)
1327 mt7530_clear(priv, MT7530_PCR_P(other_port),
1328 PCR_MATRIX(BIT(port)));
1329 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port));
b8f126a8
SW		 1330 }
1331
1332 /* Set the cpu port to be the only one in the port matrix of
1333 * this port.
1334 */
1335 if (priv->ports[port].enable)
1336 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1337 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
1338 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
1339
6087175b
DQ		 1340 /* When a port is removed from the bridge, the port would be set up
1341 * back to the default as is at initial boot which is a VLAN-unaware
1342 * port.
1343 */
1344 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1345 MT7530_PORT_MATRIX_MODE);
1346
b8f126a8
SW		 1347 mutex_unlock(&priv->reg_mutex);
1348}
1349
1350static int
b8f126a8 1351mt7530_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 1352 const unsigned char *addr, u16 vid)
b8f126a8
SW		 1353{
1354 struct mt7530_priv *priv = ds->priv;
1b6dd556 1355 int ret;
b8f126a8
SW		 1356 u8 port_mask = BIT(port);
1357
1358 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1359 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 1360 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 1361 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 1362
1363 return ret;
b8f126a8
SW		 1364}
1365
1366static int
1367mt7530_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1368 const unsigned char *addr, u16 vid)
b8f126a8
SW		 1369{
1370 struct mt7530_priv *priv = ds->priv;
1371 int ret;
1372 u8 port_mask = BIT(port);
1373
1374 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1375 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 1376 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 1377 mutex_unlock(&priv->reg_mutex);
1378
1379 return ret;
1380}
1381
1382static int
1383mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1384 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 1385{
1386 struct mt7530_priv *priv = ds->priv;
1387 struct mt7530_fdb _fdb = { 0 };
1388 int cnt = MT7530_NUM_FDB_RECORDS;
1389 int ret = 0;
1390 u32 rsp = 0;
1391
1392 mutex_lock(&priv->reg_mutex);
1393
1394 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1395 if (ret < 0)
1396 goto err;
1397
1398 do {
1399 if (rsp & ATC_SRCH_HIT) {
1400 mt7530_fdb_read(priv, &_fdb);
1401 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 1402 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1403 data);
b8f126a8
SW		 1404 if (ret < 0)
1405 break;
1406 }
1407 }
1408 } while (--cnt &&
1409 !(rsp & ATC_SRCH_END) &&
1410 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1411err:
1412 mutex_unlock(&priv->reg_mutex);
1413
1414 return 0;
1415}
1416
5a30833b
DQ		 1417static int
1418mt7530_port_mdb_add(struct dsa_switch *ds, int port,
1419 const struct switchdev_obj_port_mdb *mdb)
1420{
1421 struct mt7530_priv *priv = ds->priv;
1422 const u8 *addr = mdb->addr;
1423 u16 vid = mdb->vid;
1424 u8 port_mask = 0;
1425 int ret;
1426
1427 mutex_lock(&priv->reg_mutex);
1428
1429 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1430 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1431 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1432 & PORT_MAP_MASK;
1433
1434 port_mask |= BIT(port);
1435 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1436 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1437
1438 mutex_unlock(&priv->reg_mutex);
1439
1440 return ret;
1441}
1442
1443static int
1444mt7530_port_mdb_del(struct dsa_switch *ds, int port,
1445 const struct switchdev_obj_port_mdb *mdb)
1446{
1447 struct mt7530_priv *priv = ds->priv;
1448 const u8 *addr = mdb->addr;
1449 u16 vid = mdb->vid;
1450 u8 port_mask = 0;
1451 int ret;
1452
1453 mutex_lock(&priv->reg_mutex);
1454
1455 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1456 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1457 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1458 & PORT_MAP_MASK;
1459
1460 port_mask &= ~BIT(port);
1461 mt7530_fdb_write(priv, vid, port_mask, addr, -1,
1462 port_mask ? STATIC_ENT : STATIC_EMP);
1463 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1464
1465 mutex_unlock(&priv->reg_mutex);
1466
1467 return ret;
1468}
1469
83163f7d
SW		 1470static int
1471mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1472{
1473 struct mt7530_dummy_poll p;
1474 u32 val;
1475 int ret;
1476
1477 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1478 mt7530_write(priv, MT7530_VTCR, val);
1479
1480 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1481 ret = readx_poll_timeout(_mt7530_read, &p, val,
1482 !(val & VTCR_BUSY), 20, 20000);
1483 if (ret < 0) {
1484 dev_err(priv->dev, "poll timeout\n");
1485 return ret;
1486 }
1487
1488 val = mt7530_read(priv, MT7530_VTCR);
1489 if (val & VTCR_INVALID) {
1490 dev_err(priv->dev, "read VTCR invalid\n");
1491 return -EINVAL;
1492 }
1493
1494 return 0;
1495}
1496
1497static int
89153ed6
VO		 1498mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1499 struct netlink_ext_ack *extack)
83163f7d 1500{
83163f7d
SW		 1501 if (vlan_filtering) {
1502 /* The port is being kept as VLAN-unaware port when bridge is
1503 * set up with vlan_filtering not being set, Otherwise, the
1504 * port and the corresponding CPU port is required the setup
1505 * for becoming a VLAN-aware port.
1506 */
1507 mt7530_port_set_vlan_aware(ds, port);
1508 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
e3ee07d1
VO		 1509 } else {
1510 mt7530_port_set_vlan_unaware(ds, port);
83163f7d
SW		 1511 }
1512
1513 return 0;
1514}
1515
83163f7d
SW		 1516static void
1517mt7530_hw_vlan_add(struct mt7530_priv *priv,
1518 struct mt7530_hw_vlan_entry *entry)
1519{
1520 u8 new_members;
1521 u32 val;
1522
1523 new_members = entry->old_members | BIT(entry->port) |
1524 BIT(MT7530_CPU_PORT);
1525
1526 /* Validate the entry with independent learning, create egress tag per
1527 * VLAN and joining the port as one of the port members.
1528 */
6087175b
DQ		 1529 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
1530 VLAN_VALID;
83163f7d
SW		 1531 mt7530_write(priv, MT7530_VAWD1, val);
1532
1533 /* Decide whether adding tag or not for those outgoing packets from the
1534 * port inside the VLAN.
1535 */
1536 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1537 MT7530_VLAN_EGRESS_TAG;
1538 mt7530_rmw(priv, MT7530_VAWD2,
1539 ETAG_CTRL_P_MASK(entry->port),
1540 ETAG_CTRL_P(entry->port, val));
1541
1542 /* CPU port is always taken as a tagged port for serving more than one
1543 * VLANs across and also being applied with egress type stack mode for
1544 * that VLAN tags would be appended after hardware special tag used as
1545 * DSA tag.
1546 */
1547 mt7530_rmw(priv, MT7530_VAWD2,
1548 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1549 ETAG_CTRL_P(MT7530_CPU_PORT,
1550 MT7530_VLAN_EGRESS_STACK));
1551}
1552
1553static void
1554mt7530_hw_vlan_del(struct mt7530_priv *priv,
1555 struct mt7530_hw_vlan_entry *entry)
1556{
1557 u8 new_members;
1558 u32 val;
1559
1560 new_members = entry->old_members & ~BIT(entry->port);
1561
1562 val = mt7530_read(priv, MT7530_VAWD1);
1563 if (!(val & VLAN_VALID)) {
1564 dev_err(priv->dev,
1565 "Cannot be deleted due to invalid entry\n");
1566 return;
1567 }
1568
1569 /* If certain member apart from CPU port is still alive in the VLAN,
1570 * the entry would be kept valid. Otherwise, the entry is got to be
1571 * disabled.
1572 */
1573 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1574 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1575 VLAN_VALID;
1576 mt7530_write(priv, MT7530_VAWD1, val);
1577 } else {
1578 mt7530_write(priv, MT7530_VAWD1, 0);
1579 mt7530_write(priv, MT7530_VAWD2, 0);
1580 }
1581}
1582
1583static void
1584mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1585 struct mt7530_hw_vlan_entry *entry,
1586 mt7530_vlan_op vlan_op)
1587{
1588 u32 val;
1589
1590 /* Fetch entry */
1591 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1592
1593 val = mt7530_read(priv, MT7530_VAWD1);
1594
1595 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1596
1597 /* Manipulate entry */
1598 vlan_op(priv, entry);
1599
1600 /* Flush result to hardware */
1601 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1602}
1603
1ca8a193
DQ		 1604static int
1605mt7530_setup_vlan0(struct mt7530_priv *priv)
1606{
1607 u32 val;
1608
1609 /* Validate the entry with independent learning, keep the original
1610 * ingress tag attribute.
1611 */
1612 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
1613 VLAN_VALID;
1614 mt7530_write(priv, MT7530_VAWD1, val);
1615
1616 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
1617}
1618
1958d581 1619static int
83163f7d 1620mt7530_port_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 1621 const struct switchdev_obj_port_vlan *vlan,
1622 struct netlink_ext_ack *extack)
83163f7d
SW		 1623{
1624 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1625 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1626 struct mt7530_hw_vlan_entry new_entry;
1627 struct mt7530_priv *priv = ds->priv;
83163f7d 1628
83163f7d
SW		 1629 mutex_lock(&priv->reg_mutex);
1630
b7a9e0da
VO		 1631 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1632 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
83163f7d
SW		 1633
1634 if (pvid) {
b7a9e0da 1635 priv->ports[port].pvid = vlan->vid;
6087175b 1636
8fbebef8
DQ		 1637 /* Accept all frames if PVID is set */
1638 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1639 MT7530_VLAN_ACC_ALL);
1640
6087175b
DQ		 1641 /* Only configure PVID if VLAN filtering is enabled */
1642 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1643 mt7530_rmw(priv, MT7530_PPBV1_P(port),
1644 G0_PORT_VID_MASK,
1645 G0_PORT_VID(vlan->vid));
8fbebef8
DQ		 1646 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
1647 /* This VLAN is overwritten without PVID, so unset it */
1648 priv->ports[port].pvid = G0_PORT_VID_DEF;
1649
1650 /* Only accept tagged frames if the port is VLAN-aware */
1651 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1652 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1653 MT7530_VLAN_ACC_TAGGED);
1654
1655 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1656 G0_PORT_VID_DEF);
83163f7d
SW		 1657 }
1658
1659 mutex_unlock(&priv->reg_mutex);
1958d581
VO		 1660
1661 return 0;
83163f7d
SW		 1662}
1663
1664static int
1665mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1666 const struct switchdev_obj_port_vlan *vlan)
1667{
1668 struct mt7530_hw_vlan_entry target_entry;
1669 struct mt7530_priv *priv = ds->priv;
83163f7d 1670
83163f7d
SW		 1671 mutex_lock(&priv->reg_mutex);
1672
b7a9e0da
VO		 1673 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1674 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1675 mt7530_hw_vlan_del);
83163f7d 1676
b7a9e0da
VO		 1677 /* PVID is being restored to the default whenever the PVID port
1678 * is being removed from the VLAN.
1679 */
6087175b
DQ		 1680 if (priv->ports[port].pvid == vlan->vid) {
1681 priv->ports[port].pvid = G0_PORT_VID_DEF;
8fbebef8
DQ		 1682
1683 /* Only accept tagged frames if the port is VLAN-aware */
1684 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1685 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1686 MT7530_VLAN_ACC_TAGGED);
1687
6087175b
DQ		 1688 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1689 G0_PORT_VID_DEF);
1690 }
83163f7d 1691
83163f7d
SW		 1692
1693 mutex_unlock(&priv->reg_mutex);
1694
1695 return 0;
1696}
1697
c288575f
LC		 1698static int mt753x_mirror_port_get(unsigned int id, u32 val)
1699{
1700 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1701 MIRROR_PORT(val);
1702}
1703
1704static int mt753x_mirror_port_set(unsigned int id, u32 val)
1705{
1706 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1707 MIRROR_PORT(val);
1708}
1709
1710static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
37feab60
DQ		 1711 struct dsa_mall_mirror_tc_entry *mirror,
1712 bool ingress)
1713{
1714 struct mt7530_priv *priv = ds->priv;
c288575f 1715 int monitor_port;
37feab60
DQ		 1716 u32 val;
1717
1718 /* Check for existent entry */
1719 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1720 return -EEXIST;
1721
c288575f 1722 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
37feab60
DQ		 1723
1724 /* MT7530 only supports one monitor port */
c288575f
LC		 1725 monitor_port = mt753x_mirror_port_get(priv->id, val);
1726 if (val & MT753X_MIRROR_EN(priv->id) &&
1727 monitor_port != mirror->to_local_port)
37feab60
DQ		 1728 return -EEXIST;
1729
c288575f
LC		 1730 val |= MT753X_MIRROR_EN(priv->id);
1731 val &= ~MT753X_MIRROR_MASK(priv->id);
1732 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1733 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1734
1735 val = mt7530_read(priv, MT7530_PCR_P(port));
1736 if (ingress) {
1737 val |= PORT_RX_MIR;
1738 priv->mirror_rx |= BIT(port);
1739 } else {
1740 val |= PORT_TX_MIR;
1741 priv->mirror_tx |= BIT(port);
1742 }
1743 mt7530_write(priv, MT7530_PCR_P(port), val);
1744
1745 return 0;
1746}
1747
c288575f 1748static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
37feab60
DQ		 1749 struct dsa_mall_mirror_tc_entry *mirror)
1750{
1751 struct mt7530_priv *priv = ds->priv;
1752 u32 val;
1753
1754 val = mt7530_read(priv, MT7530_PCR_P(port));
1755 if (mirror->ingress) {
1756 val &= ~PORT_RX_MIR;
1757 priv->mirror_rx &= ~BIT(port);
1758 } else {
1759 val &= ~PORT_TX_MIR;
1760 priv->mirror_tx &= ~BIT(port);
1761 }
1762 mt7530_write(priv, MT7530_PCR_P(port), val);
1763
1764 if (!priv->mirror_rx && !priv->mirror_tx) {
c288575f
LC		 1765 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1766 val &= ~MT753X_MIRROR_EN(priv->id);
1767 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1768 }
1769}
1770
b8f126a8 1771static enum dsa_tag_protocol
4d776482
FF		 1772mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1773 enum dsa_tag_protocol mp)
b8f126a8 1774{
244f8a80 1775 return DSA_TAG_PROTO_MTK;
b8f126a8
SW		 1776}
1777
63c75c05 1778#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 1779static inline u32
1780mt7530_gpio_to_bit(unsigned int offset)
1781{
1782 /* Map GPIO offset to register bit
1783 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2
1784 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5
1785 * [10: 8] port 2 LED 0..2 as GPIO 6..8
1786 * [14:12] port 3 LED 0..2 as GPIO 9..11
1787 * [18:16] port 4 LED 0..2 as GPIO 12..14
1788 */
1789 return BIT(offset + offset / 3);
1790}
1791
1792static int
1793mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1794{
1795 struct mt7530_priv *priv = gpiochip_get_data(gc);
1796 u32 bit = mt7530_gpio_to_bit(offset);
1797
1798 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1799}
1800
1801static void
1802mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1803{
1804 struct mt7530_priv *priv = gpiochip_get_data(gc);
1805 u32 bit = mt7530_gpio_to_bit(offset);
1806
1807 if (value)
1808 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1809 else
1810 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1811}
1812
1813static int
1814mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1815{
1816 struct mt7530_priv *priv = gpiochip_get_data(gc);
1817 u32 bit = mt7530_gpio_to_bit(offset);
1818
1819 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1820 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1821}
1822
1823static int
1824mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1825{
1826 struct mt7530_priv *priv = gpiochip_get_data(gc);
1827 u32 bit = mt7530_gpio_to_bit(offset);
1828
1829 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1830 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1831
1832 return 0;
1833}
1834
1835static int
1836mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1837{
1838 struct mt7530_priv *priv = gpiochip_get_data(gc);
1839 u32 bit = mt7530_gpio_to_bit(offset);
1840
1841 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1842
1843 if (value)
1844 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1845 else
1846 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1847
1848 mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1849
1850 return 0;
1851}
1852
1853static int
1854mt7530_setup_gpio(struct mt7530_priv *priv)
1855{
1856 struct device *dev = priv->dev;
1857 struct gpio_chip *gc;
1858
1859 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1860 if (!gc)
1861 return -ENOMEM;
1862
1863 mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1864 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1865 mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1866
1867 gc->label = "mt7530";
1868 gc->parent = dev;
1869 gc->owner = THIS_MODULE;
1870 gc->get_direction = mt7530_gpio_get_direction;
1871 gc->direction_input = mt7530_gpio_direction_input;
1872 gc->direction_output = mt7530_gpio_direction_output;
1873 gc->get = mt7530_gpio_get;
1874 gc->set = mt7530_gpio_set;
1875 gc->base = -1;
1876 gc->ngpio = 15;
1877 gc->can_sleep = true;
1878
1879 return devm_gpiochip_add_data(dev, gc, priv);
1880}
63c75c05 1881#endif /* CONFIG_GPIOLIB */
429a0ede 1882
ba751e28
DQ		 1883static irqreturn_t
1884mt7530_irq_thread_fn(int irq, void *dev_id)
1885{
1886 struct mt7530_priv *priv = dev_id;
1887 bool handled = false;
1888 u32 val;
1889 int p;
1890
1891 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1892 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
1893 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
1894 mutex_unlock(&priv->bus->mdio_lock);
1895
1896 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1897 if (BIT(p) & val) {
1898 unsigned int irq;
1899
1900 irq = irq_find_mapping(priv->irq_domain, p);
1901 handle_nested_irq(irq);
1902 handled = true;
1903 }
1904 }
1905
1906 return IRQ_RETVAL(handled);
1907}
1908
1909static void
1910mt7530_irq_mask(struct irq_data *d)
1911{
1912 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1913
1914 priv->irq_enable &= ~BIT(d->hwirq);
1915}
1916
1917static void
1918mt7530_irq_unmask(struct irq_data *d)
1919{
1920 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1921
1922 priv->irq_enable |= BIT(d->hwirq);
1923}
1924
1925static void
1926mt7530_irq_bus_lock(struct irq_data *d)
1927{
1928 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1929
1930 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1931}
1932
1933static void
1934mt7530_irq_bus_sync_unlock(struct irq_data *d)
1935{
1936 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1937
1938 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1939 mutex_unlock(&priv->bus->mdio_lock);
1940}
1941
1942static struct irq_chip mt7530_irq_chip = {
1943 .name = KBUILD_MODNAME,
1944 .irq_mask = mt7530_irq_mask,
1945 .irq_unmask = mt7530_irq_unmask,
1946 .irq_bus_lock = mt7530_irq_bus_lock,
1947 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock,
1948};
1949
1950static int
1951mt7530_irq_map(struct irq_domain *domain, unsigned int irq,
1952 irq_hw_number_t hwirq)
1953{
1954 irq_set_chip_data(irq, domain->host_data);
1955 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq);
1956 irq_set_nested_thread(irq, true);
1957 irq_set_noprobe(irq);
1958
1959 return 0;
1960}
1961
1962static const struct irq_domain_ops mt7530_irq_domain_ops = {
1963 .map = mt7530_irq_map,
1964 .xlate = irq_domain_xlate_onecell,
1965};
1966
1967static void
1968mt7530_setup_mdio_irq(struct mt7530_priv *priv)
1969{
1970 struct dsa_switch *ds = priv->ds;
1971 int p;
1972
1973 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1974 if (BIT(p) & ds->phys_mii_mask) {
1975 unsigned int irq;
1976
1977 irq = irq_create_mapping(priv->irq_domain, p);
1978 ds->slave_mii_bus->irq[p] = irq;
1979 }
1980 }
1981}
1982
1983static int
1984mt7530_setup_irq(struct mt7530_priv *priv)
1985{
1986 struct device *dev = priv->dev;
1987 struct device_node *np = dev->of_node;
1988 int ret;
1989
1990 if (!of_property_read_bool(np, "interrupt-controller")) {
1991 dev_info(dev, "no interrupt support\n");
1992 return 0;
1993 }
1994
1995 priv->irq = of_irq_get(np, 0);
1996 if (priv->irq <= 0) {
1997 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq);
1998 return priv->irq ? : -EINVAL;
1999 }
2000
2001 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
2002 &mt7530_irq_domain_ops, priv);
2003 if (!priv->irq_domain) {
2004 dev_err(dev, "failed to create IRQ domain\n");
2005 return -ENOMEM;
2006 }
2007
2008 /* This register must be set for MT7530 to properly fire interrupts */
2009 if (priv->id != ID_MT7531)
2010 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
2011
2012 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
2013 IRQF_ONESHOT, KBUILD_MODNAME, priv);
2014 if (ret) {
2015 irq_domain_remove(priv->irq_domain);
2016 dev_err(dev, "failed to request IRQ: %d\n", ret);
2017 return ret;
2018 }
2019
2020 return 0;
2021}
2022
2023static void
2024mt7530_free_mdio_irq(struct mt7530_priv *priv)
2025{
2026 int p;
2027
2028 for (p = 0; p < MT7530_NUM_PHYS; p++) {
2029 if (BIT(p) & priv->ds->phys_mii_mask) {
2030 unsigned int irq;
2031
2032 irq = irq_find_mapping(priv->irq_domain, p);
2033 irq_dispose_mapping(irq);
2034 }
2035 }
2036}
2037
2038static void
2039mt7530_free_irq_common(struct mt7530_priv *priv)
2040{
2041 free_irq(priv->irq, priv);
2042 irq_domain_remove(priv->irq_domain);
2043}
2044
2045static void
2046mt7530_free_irq(struct mt7530_priv *priv)
2047{
2048 mt7530_free_mdio_irq(priv);
2049 mt7530_free_irq_common(priv);
2050}
2051
2052static int
2053mt7530_setup_mdio(struct mt7530_priv *priv)
2054{
2055 struct dsa_switch *ds = priv->ds;
2056 struct device *dev = priv->dev;
2057 struct mii_bus *bus;
2058 static int idx;
2059 int ret;
2060
2061 bus = devm_mdiobus_alloc(dev);
2062 if (!bus)
2063 return -ENOMEM;
2064
2065 ds->slave_mii_bus = bus;
2066 bus->priv = priv;
2067 bus->name = KBUILD_MODNAME "-mii";
2068 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
2069 bus->read = mt753x_phy_read;
2070 bus->write = mt753x_phy_write;
2071 bus->parent = dev;
2072 bus->phy_mask = ~ds->phys_mii_mask;
2073
2074 if (priv->irq)
2075 mt7530_setup_mdio_irq(priv);
2076
2077 ret = mdiobus_register(bus);
2078 if (ret) {
2079 dev_err(dev, "failed to register MDIO bus: %d\n", ret);
2080 if (priv->irq)
2081 mt7530_free_mdio_irq(priv);
2082 }
2083
2084 return ret;
2085}
2086
b8f126a8
SW		 2087static int
2088mt7530_setup(struct dsa_switch *ds)
2089{
2090 struct mt7530_priv *priv = ds->priv;
38f790a8
RD		 2091 struct device_node *phy_node;
2092 struct device_node *mac_np;
b8f126a8 2093 struct mt7530_dummy_poll p;
38f790a8 2094 phy_interface_t interface;
ca366d6c
RD		 2095 struct device_node *dn;
2096 u32 id, val;
2097 int ret, i;
b8f126a8 2098
0abfd494 2099 /* The parent node of master netdev which holds the common system
b8f126a8
SW		 2100 * controller also is the container for two GMACs nodes representing
2101 * as two netdev instances.
2102 */
68bb8ea8 2103 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
0b69c54c 2104 ds->assisted_learning_on_cpu_port = true;
771c8901 2105 ds->mtu_enforcement_ingress = true;
b8f126a8 2106
ddda1ac1 2107 if (priv->id == ID_MT7530) {
ddda1ac1
GU		 2108 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
2109 ret = regulator_enable(priv->core_pwr);
2110 if (ret < 0) {
2111 dev_err(priv->dev,
2112 "Failed to enable core power: %d\n", ret);
2113 return ret;
2114 }
b8f126a8 2115
ddda1ac1
GU		 2116 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
2117 ret = regulator_enable(priv->io_pwr);
2118 if (ret < 0) {
2119 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
2120 ret);
2121 return ret;
2122 }
b8f126a8
SW		 2123 }
2124
2125 /* Reset whole chip through gpio pin or memory-mapped registers for
2126 * different type of hardware
2127 */
2128 if (priv->mcm) {
2129 reset_control_assert(priv->rstc);
2130 usleep_range(1000, 1100);
2131 reset_control_deassert(priv->rstc);
2132 } else {
2133 gpiod_set_value_cansleep(priv->reset, 0);
2134 usleep_range(1000, 1100);
2135 gpiod_set_value_cansleep(priv->reset, 1);
2136 }
2137
2138 /* Waiting for MT7530 got to stable */
2139 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2140 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2141 20, 1000000);
2142 if (ret < 0) {
2143 dev_err(priv->dev, "reset timeout\n");
2144 return ret;
2145 }
2146
2147 id = mt7530_read(priv, MT7530_CREV);
2148 id >>= CHIP_NAME_SHIFT;
2149 if (id != MT7530_ID) {
2150 dev_err(priv->dev, "chip %x can't be supported\n", id);
2151 return -ENODEV;
2152 }
2153
2154 /* Reset the switch through internal reset */
2155 mt7530_write(priv, MT7530_SYS_CTRL,
2156 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2157 SYS_CTRL_REG_RST);
2158
2159 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
2160 val = mt7530_read(priv, MT7530_MHWTRAP);
2161 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
2162 val |= MHWTRAP_MANUAL;
2163 mt7530_write(priv, MT7530_MHWTRAP, val);
2164
ca366d6c
RD		 2165 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2166
b8f126a8
SW		 2167 /* Enable and reset MIB counters */
2168 mt7530_mib_reset(ds);
2169
b8f126a8
SW		 2170 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2171 /* Disable forwarding by default on all ports */
2172 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2173 PCR_MATRIX_CLR);
2174
0b69c54c
DQ		 2175 /* Disable learning by default on all ports */
2176 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2177
0ce0c3cd
AD		 2178 if (dsa_is_cpu_port(ds, i)) {
2179 ret = mt753x_cpu_port_enable(ds, i);
2180 if (ret)
2181 return ret;
5a30833b 2182 } else {
75104db0 2183 mt7530_port_disable(ds, i);
6087175b
DQ		 2184
2185 /* Set default PVID to 0 on all user ports */
2186 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2187 G0_PORT_VID_DEF);
5a30833b 2188 }
e045124e
DQ		 2189 /* Enable consistent egress tag */
2190 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2191 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
b8f126a8
SW		 2192 }
2193
1ca8a193
DQ		 2194 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2195 ret = mt7530_setup_vlan0(priv);
2196 if (ret)
2197 return ret;
2198
38f790a8
RD		 2199 /* Setup port 5 */
2200 priv->p5_intf_sel = P5_DISABLED;
2201 interface = PHY_INTERFACE_MODE_NA;
2202
2203 if (!dsa_is_unused_port(ds, 5)) {
2204 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
0c65b2b9
AL		 2205 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
2206 if (ret && ret != -ENODEV)
2207 return ret;
38f790a8
RD		 2208 } else {
2209 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
2210 for_each_child_of_node(dn, mac_np) {
2211 if (!of_device_is_compatible(mac_np,
2212 "mediatek,eth-mac"))
2213 continue;
2214
2215 ret = of_property_read_u32(mac_np, "reg", &id);
2216 if (ret < 0 || id != 1)
2217 continue;
2218
2219 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
0452800f
CG		 2220 if (!phy_node)
2221 continue;
2222
38f790a8 2223 if (phy_node->parent == priv->dev->of_node->parent) {
0c65b2b9 2224 ret = of_get_phy_mode(mac_np, &interface);
8e4efd47
SP		 2225 if (ret && ret != -ENODEV) {
2226 of_node_put(mac_np);
0c65b2b9 2227 return ret;
8e4efd47 2228 }
38f790a8
RD		 2229 id = of_mdio_parse_addr(ds->dev, phy_node);
2230 if (id == 0)
2231 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
2232 if (id == 4)
2233 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
2234 }
8e4efd47 2235 of_node_put(mac_np);
38f790a8
RD		 2236 of_node_put(phy_node);
2237 break;
2238 }
2239 }
2240
63c75c05 2241#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 2242 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
2243 ret = mt7530_setup_gpio(priv);
2244 if (ret)
2245 return ret;
2246 }
63c75c05 2247#endif /* CONFIG_GPIOLIB */
429a0ede 2248
38f790a8
RD		 2249 mt7530_setup_port5(ds, interface);
2250
b8f126a8 2251 /* Flush the FDB table */
18bd5949 2252 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 2253 if (ret < 0)
2254 return ret;
2255
2256 return 0;
2257}
2258
c288575f
LC		 2259static int
2260mt7531_setup(struct dsa_switch *ds)
2261{
2262 struct mt7530_priv *priv = ds->priv;
2263 struct mt7530_dummy_poll p;
2264 u32 val, id;
2265 int ret, i;
2266
2267 /* Reset whole chip through gpio pin or memory-mapped registers for
2268 * different type of hardware
2269 */
2270 if (priv->mcm) {
2271 reset_control_assert(priv->rstc);
2272 usleep_range(1000, 1100);
2273 reset_control_deassert(priv->rstc);
2274 } else {
2275 gpiod_set_value_cansleep(priv->reset, 0);
2276 usleep_range(1000, 1100);
2277 gpiod_set_value_cansleep(priv->reset, 1);
2278 }
2279
2280 /* Waiting for MT7530 got to stable */
2281 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2282 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2283 20, 1000000);
2284 if (ret < 0) {
2285 dev_err(priv->dev, "reset timeout\n");
2286 return ret;
2287 }
2288
2289 id = mt7530_read(priv, MT7531_CREV);
2290 id >>= CHIP_NAME_SHIFT;
2291
2292 if (id != MT7531_ID) {
2293 dev_err(priv->dev, "chip %x can't be supported\n", id);
2294 return -ENODEV;
2295 }
2296
2297 /* Reset the switch through internal reset */
2298 mt7530_write(priv, MT7530_SYS_CTRL,
2299 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2300 SYS_CTRL_REG_RST);
2301
2302 if (mt7531_dual_sgmii_supported(priv)) {
2303 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
2304
2305 /* Let ds->slave_mii_bus be able to access external phy. */
2306 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
2307 MT7531_EXT_P_MDC_11);
2308 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
2309 MT7531_EXT_P_MDIO_12);
2310 } else {
2311 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2312 }
2313 dev_dbg(ds->dev, "P5 support %s interface\n",
2314 p5_intf_modes(priv->p5_intf_sel));
2315
2316 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
2317 MT7531_GPIO0_INTERRUPT);
2318
2319 /* Let phylink decide the interface later. */
2320 priv->p5_interface = PHY_INTERFACE_MODE_NA;
2321 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2322
2323 /* Enable PHY core PLL, since phy_device has not yet been created
2324 * provided for phy_[read,write]_mmd_indirect is called, we provide
2325 * our own mt7531_ind_mmd_phy_[read,write] to complete this
2326 * function.
2327 */
2328 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
2329 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2330 val |= MT7531_PHY_PLL_BYPASS_MODE;
2331 val &= ~MT7531_PHY_PLL_OFF;
2332 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
2333 CORE_PLL_GROUP4, val);
2334
2335 /* BPDU to CPU port */
2336 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
2337 BIT(MT7530_CPU_PORT));
2338 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
2339 MT753X_BPDU_CPU_ONLY);
2340
2341 /* Enable and reset MIB counters */
2342 mt7530_mib_reset(ds);
2343
2344 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2345 /* Disable forwarding by default on all ports */
2346 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2347 PCR_MATRIX_CLR);
2348
0b69c54c
DQ		 2349 /* Disable learning by default on all ports */
2350 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2351
c288575f
LC		 2352 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
2353
0ce0c3cd
AD		 2354 if (dsa_is_cpu_port(ds, i)) {
2355 ret = mt753x_cpu_port_enable(ds, i);
2356 if (ret)
2357 return ret;
5a30833b 2358 } else {
c288575f 2359 mt7530_port_disable(ds, i);
6087175b
DQ		 2360
2361 /* Set default PVID to 0 on all user ports */
2362 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2363 G0_PORT_VID_DEF);
5a30833b
DQ		 2364 }
2365
c288575f
LC		 2366 /* Enable consistent egress tag */
2367 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2368 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2369 }
2370
1ca8a193
DQ		 2371 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2372 ret = mt7530_setup_vlan0(priv);
2373 if (ret)
2374 return ret;
2375
0b69c54c 2376 ds->assisted_learning_on_cpu_port = true;
771c8901 2377 ds->mtu_enforcement_ingress = true;
c288575f
LC		 2378
2379 /* Flush the FDB table */
2380 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2381 if (ret < 0)
2382 return ret;
2383
2384 return 0;
2385}
2386
88bdef8b
LC		 2387static bool
2388mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
2389 const struct phylink_link_state *state)
ca366d6c
RD		 2390{
2391 struct mt7530_priv *priv = ds->priv;
ca366d6c
RD		 2392
2393 switch (port) {
88bdef8b 2394 case 0 ... 4: /* Internal phy */
ca366d6c 2395 if (state->interface != PHY_INTERFACE_MODE_GMII)
88bdef8b 2396 return false;
ca366d6c 2397 break;
38f790a8 2398 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
38f790a8
RD		 2399 if (!phy_interface_mode_is_rgmii(state->interface) &&
2400 state->interface != PHY_INTERFACE_MODE_MII &&
2401 state->interface != PHY_INTERFACE_MODE_GMII)
88bdef8b
LC		 2402 return false;
2403 break;
2404 case 6: /* 1st cpu port */
2405 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
2406 state->interface != PHY_INTERFACE_MODE_TRGMII)
2407 return false;
2408 break;
2409 default:
2410 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2411 port);
2412 return false;
2413 }
2414
2415 return true;
2416}
2417
c288575f
LC		 2418static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
2419{
2420 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
2421}
2422
2423static bool
2424mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
2425 const struct phylink_link_state *state)
2426{
2427 struct mt7530_priv *priv = ds->priv;
2428
2429 switch (port) {
2430 case 0 ... 4: /* Internal phy */
2431 if (state->interface != PHY_INTERFACE_MODE_GMII)
2432 return false;
2433 break;
2434 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
2435 if (mt7531_is_rgmii_port(priv, port))
2436 return phy_interface_mode_is_rgmii(state->interface);
2437 fallthrough;
2438 case 6: /* 1st cpu port supports sgmii/8023z only */
2439 if (state->interface != PHY_INTERFACE_MODE_SGMII &&
2440 !phy_interface_mode_is_8023z(state->interface))
2441 return false;
2442 break;
2443 default:
2444 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2445 port);
2446 return false;
2447 }
2448
2449 return true;
2450}
2451
88bdef8b
LC		 2452static bool
2453mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
2454 const struct phylink_link_state *state)
2455{
2456 struct mt7530_priv *priv = ds->priv;
2457
2458 return priv->info->phy_mode_supported(ds, port, state);
2459}
2460
2461static int
2462mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2463{
2464 struct mt7530_priv *priv = ds->priv;
2465
2466 return priv->info->pad_setup(ds, state->interface);
2467}
2468
2469static int
2470mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2471 phy_interface_t interface)
2472{
2473 struct mt7530_priv *priv = ds->priv;
2474
2475 /* Only need to setup port5. */
2476 if (port != 5)
2477 return 0;
2478
2479 mt7530_setup_port5(priv->ds, interface);
2480
2481 return 0;
2482}
2483
c288575f
LC		 2484static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2485 phy_interface_t interface,
2486 struct phy_device *phydev)
2487{
2488 u32 val;
2489
2490 if (!mt7531_is_rgmii_port(priv, port)) {
2491 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2492 port);
2493 return -EINVAL;
2494 }
2495
2496 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2497 val |= GP_CLK_EN;
2498 val &= ~GP_MODE_MASK;
2499 val |= GP_MODE(MT7531_GP_MODE_RGMII);
2500 val &= ~CLK_SKEW_IN_MASK;
2501 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2502 val &= ~CLK_SKEW_OUT_MASK;
2503 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2504 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2505
2506 /* Do not adjust rgmii delay when vendor phy driver presents. */
2507 if (!phydev || phy_driver_is_genphy(phydev)) {
2508 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2509 switch (interface) {
2510 case PHY_INTERFACE_MODE_RGMII:
2511 val |= TXCLK_NO_REVERSE;
2512 val |= RXCLK_NO_DELAY;
2513 break;
2514 case PHY_INTERFACE_MODE_RGMII_RXID:
2515 val |= TXCLK_NO_REVERSE;
2516 break;
2517 case PHY_INTERFACE_MODE_RGMII_TXID:
2518 val |= RXCLK_NO_DELAY;
2519 break;
2520 case PHY_INTERFACE_MODE_RGMII_ID:
2521 break;
2522 default:
2523 return -EINVAL;
2524 }
2525 }
2526 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2527
2528 return 0;
2529}
2530
2531static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
2532 unsigned long *supported)
2533{
2534 /* Port5 supports ethier RGMII or SGMII.
2535 * Port6 supports SGMII only.
2536 */
2537 switch (port) {
2538 case 5:
2539 if (mt7531_is_rgmii_port(priv, port))
2540 break;
2541 fallthrough;
2542 case 6:
2543 phylink_set(supported, 1000baseX_Full);
2544 phylink_set(supported, 2500baseX_Full);
2545 phylink_set(supported, 2500baseT_Full);
2546 }
2547}
2548
2549static void
2550mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
2551 unsigned int mode, phy_interface_t interface,
2552 int speed, int duplex)
2553{
2554 struct mt7530_priv *priv = ds->priv;
2555 unsigned int val;
2556
2557 /* For adjusting speed and duplex of SGMII force mode. */
2558 if (interface != PHY_INTERFACE_MODE_SGMII ||
2559 phylink_autoneg_inband(mode))
2560 return;
2561
2562 /* SGMII force mode setting */
2563 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
2564 val &= ~MT7531_SGMII_IF_MODE_MASK;
2565
2566 switch (speed) {
2567 case SPEED_10:
2568 val |= MT7531_SGMII_FORCE_SPEED_10;
2569 break;
2570 case SPEED_100:
2571 val |= MT7531_SGMII_FORCE_SPEED_100;
2572 break;
2573 case SPEED_1000:
2574 val |= MT7531_SGMII_FORCE_SPEED_1000;
2575 break;
2576 }
2577
2578 /* MT7531 SGMII 1G force mode can only work in full duplex mode,
2579 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2580 */
2581 if ((speed == SPEED_10 || speed == SPEED_100) &&
2582 duplex != DUPLEX_FULL)
2583 val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2584
2585 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2586}
2587
2588static bool mt753x_is_mac_port(u32 port)
2589{
2590 return (port == 5 || port == 6);
2591}
2592
2593static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2594 phy_interface_t interface)
2595{
2596 u32 val;
2597
2598 if (!mt753x_is_mac_port(port))
2599 return -EINVAL;
2600
2601 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2602 MT7531_SGMII_PHYA_PWD);
2603
2604 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2605 val &= ~MT7531_RG_TPHY_SPEED_MASK;
2606 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2607 * encoding.
2608 */
2609 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2610 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2611 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2612
2613 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2614
2615 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2616 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2617 */
2618 mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2619 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2620 MT7531_SGMII_FORCE_SPEED_1000);
2621
2622 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2623
2624 return 0;
2625}
2626
2627static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2628 phy_interface_t interface)
2629{
2630 if (!mt753x_is_mac_port(port))
2631 return -EINVAL;
2632
2633 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2634 MT7531_SGMII_PHYA_PWD);
2635
2636 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2637 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2638
2639 mt7530_set(priv, MT7531_SGMII_MODE(port),
2640 MT7531_SGMII_REMOTE_FAULT_DIS |
2641 MT7531_SGMII_SPEED_DUPLEX_AN);
2642
2643 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2644 MT7531_SGMII_TX_CONFIG_MASK, 1);
2645
2646 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2647
2648 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2649
2650 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2651
2652 return 0;
2653}
2654
2655static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
2656{
2657 struct mt7530_priv *priv = ds->priv;
2658 u32 val;
2659
2660 /* Only restart AN when AN is enabled */
2661 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2662 if (val & MT7531_SGMII_AN_ENABLE) {
2663 val |= MT7531_SGMII_AN_RESTART;
2664 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2665 }
2666}
2667
2668static int
2669mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2670 phy_interface_t interface)
2671{
2672 struct mt7530_priv *priv = ds->priv;
2673 struct phy_device *phydev;
2674 struct dsa_port *dp;
2675
2676 if (!mt753x_is_mac_port(port)) {
2677 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2678 return -EINVAL;
2679 }
2680
2681 switch (interface) {
2682 case PHY_INTERFACE_MODE_RGMII:
2683 case PHY_INTERFACE_MODE_RGMII_ID:
2684 case PHY_INTERFACE_MODE_RGMII_RXID:
2685 case PHY_INTERFACE_MODE_RGMII_TXID:
2686 dp = dsa_to_port(ds, port);
2687 phydev = dp->slave->phydev;
2688 return mt7531_rgmii_setup(priv, port, interface, phydev);
2689 case PHY_INTERFACE_MODE_SGMII:
2690 return mt7531_sgmii_setup_mode_an(priv, port, interface);
2691 case PHY_INTERFACE_MODE_NA:
2692 case PHY_INTERFACE_MODE_1000BASEX:
2693 case PHY_INTERFACE_MODE_2500BASEX:
2694 if (phylink_autoneg_inband(mode))
2695 return -EINVAL;
2696
2697 return mt7531_sgmii_setup_mode_force(priv, port, interface);
2698 default:
2699 return -EINVAL;
2700 }
2701
2702 return -EINVAL;
2703}
2704
88bdef8b
LC		 2705static int
2706mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2707 const struct phylink_link_state *state)
2708{
2709 struct mt7530_priv *priv = ds->priv;
2710
2711 return priv->info->mac_port_config(ds, port, mode, state->interface);
2712}
2713
2714static void
2715mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2716 const struct phylink_link_state *state)
2717{
2718 struct mt7530_priv *priv = ds->priv;
2719 u32 mcr_cur, mcr_new;
2720
2721 if (!mt753x_phy_mode_supported(ds, port, state))
2722 goto unsupported;
2723
2724 switch (port) {
2725 case 0 ... 4: /* Internal phy */
2726 if (state->interface != PHY_INTERFACE_MODE_GMII)
2727 goto unsupported;
2728 break;
2729 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2730 if (priv->p5_interface == state->interface)
2731 break;
2732
2733 if (mt753x_mac_config(ds, port, mode, state) < 0)
2734 goto unsupported;
38f790a8 2735
c288575f
LC		 2736 if (priv->p5_intf_sel != P5_DISABLED)
2737 priv->p5_interface = state->interface;
38f790a8 2738 break;
ca366d6c
RD		 2739 case 6: /* 1st cpu port */
2740 if (priv->p6_interface == state->interface)
2741 break;
2742
88bdef8b 2743 mt753x_pad_setup(ds, state);
ca366d6c 2744
88bdef8b
LC		 2745 if (mt753x_mac_config(ds, port, mode, state) < 0)
2746 goto unsupported;
ca366d6c 2747
ca366d6c
RD		 2748 priv->p6_interface = state->interface;
2749 break;
2750 default:
88bdef8b
LC		 2751unsupported:
2752 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2753 __func__, phy_modes(state->interface), port);
ca366d6c
RD		 2754 return;
2755 }
2756
c288575f
LC		 2757 if (phylink_autoneg_inband(mode) &&
2758 state->interface != PHY_INTERFACE_MODE_SGMII) {
ca366d6c
RD		 2759 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
2760 __func__);
2761 return;
2762 }
2763
2764 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2765 mcr_new = mcr_cur;
1d01145f 2766 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
ca366d6c 2767 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
c288575f 2768 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
ca366d6c 2769
38f790a8
RD		 2770 /* Are we connected to external phy */
2771 if (port == 5 && dsa_is_user_port(ds, 5))
2772 mcr_new |= PMCR_EXT_PHY;
2773
ca366d6c
RD		 2774 if (mcr_new != mcr_cur)
2775 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2776}
2777
c288575f
LC		 2778static void
2779mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
2780{
2781 struct mt7530_priv *priv = ds->priv;
2782
2783 if (!priv->info->mac_pcs_an_restart)
2784 return;
2785
2786 priv->info->mac_pcs_an_restart(ds, port);
2787}
2788
2789static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
ca366d6c
RD		 2790 unsigned int mode,
2791 phy_interface_t interface)
2792{
2793 struct mt7530_priv *priv = ds->priv;
2794
1d01145f 2795 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
ca366d6c
RD		 2796}
2797
c288575f
LC		 2798static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
2799 unsigned int mode, phy_interface_t interface,
2800 int speed, int duplex)
2801{
2802 struct mt7530_priv *priv = ds->priv;
2803
2804 if (!priv->info->mac_pcs_link_up)
2805 return;
2806
2807 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2808}
2809
2810static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
ca366d6c
RD		 2811 unsigned int mode,
2812 phy_interface_t interface,
5b502a7b
RK		 2813 struct phy_device *phydev,
2814 int speed, int duplex,
2815 bool tx_pause, bool rx_pause)
ca366d6c
RD		 2816{
2817 struct mt7530_priv *priv = ds->priv;
1d01145f
RD		 2818 u32 mcr;
2819
c288575f
LC		 2820 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2821
1d01145f
RD		 2822 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2823
c288575f
LC		 2824 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2825 * variants.
2826 */
2827 if (interface == PHY_INTERFACE_MODE_TRGMII ||
2828 (phy_interface_mode_is_8023z(interface))) {
2829 speed = SPEED_1000;
2830 duplex = DUPLEX_FULL;
2831 }
2832
1d01145f
RD		 2833 switch (speed) {
2834 case SPEED_1000:
2835 mcr |= PMCR_FORCE_SPEED_1000;
2836 break;
2837 case SPEED_100:
2838 mcr |= PMCR_FORCE_SPEED_100;
2839 break;
2840 }
2841 if (duplex == DUPLEX_FULL) {
2842 mcr |= PMCR_FORCE_FDX;
2843 if (tx_pause)
2844 mcr |= PMCR_TX_FC_EN;
2845 if (rx_pause)
2846 mcr |= PMCR_RX_FC_EN;
2847 }
ca366d6c 2848
40b5d2f1
RD		 2849 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) {
2850 switch (speed) {
2851 case SPEED_1000:
2852 mcr |= PMCR_FORCE_EEE1G;
2853 break;
2854 case SPEED_100:
2855 mcr |= PMCR_FORCE_EEE100;
2856 break;
2857 }
2858 }
2859
1d01145f 2860 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
ca366d6c
RD		 2861}
2862
c288575f
LC		 2863static int
2864mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2865{
2866 struct mt7530_priv *priv = ds->priv;
2867 phy_interface_t interface;
2868 int speed;
0ce0c3cd 2869 int ret;
c288575f
LC		 2870
2871 switch (port) {
2872 case 5:
2873 if (mt7531_is_rgmii_port(priv, port))
2874 interface = PHY_INTERFACE_MODE_RGMII;
2875 else
2876 interface = PHY_INTERFACE_MODE_2500BASEX;
2877
2878 priv->p5_interface = interface;
2879 break;
2880 case 6:
2881 interface = PHY_INTERFACE_MODE_2500BASEX;
2882
2883 mt7531_pad_setup(ds, interface);
2884
2885 priv->p6_interface = interface;
2886 break;
0ce0c3cd
AD		 2887 default:
2888 return -EINVAL;
c288575f
LC		 2889 }
2890
2891 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2892 speed = SPEED_2500;
2893 else
2894 speed = SPEED_1000;
2895
0ce0c3cd
AD		 2896 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2897 if (ret)
2898 return ret;
c288575f
LC		 2899 mt7530_write(priv, MT7530_PMCR_P(port),
2900 PMCR_CPU_PORT_SETTING(priv->id));
2901 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2902 speed, DUPLEX_FULL, true, true);
2903
2904 return 0;
2905}
2906
88bdef8b
LC		 2907static void
2908mt7530_mac_port_validate(struct dsa_switch *ds, int port,
2909 unsigned long *supported)
2910{
2911 if (port == 5)
2912 phylink_set(supported, 1000baseX_Full);
2913}
2914
c288575f
LC		 2915static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
2916 unsigned long *supported)
2917{
2918 struct mt7530_priv *priv = ds->priv;
2919
2920 mt7531_sgmii_validate(priv, port, supported);
2921}
2922
88bdef8b
LC		 2923static void
2924mt753x_phylink_validate(struct dsa_switch *ds, int port,
2925 unsigned long *supported,
2926 struct phylink_link_state *state)
ca366d6c
RD		 2927{
2928 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
88bdef8b 2929 struct mt7530_priv *priv = ds->priv;
ca366d6c 2930
88bdef8b
LC		 2931 if (state->interface != PHY_INTERFACE_MODE_NA &&
2932 !mt753x_phy_mode_supported(ds, port, state)) {
ca366d6c
RD		 2933 linkmode_zero(supported);
2934 return;
2935 }
2936
2937 phylink_set_port_modes(mask);
ca366d6c 2938
c288575f
LC		 2939 if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
2940 !phy_interface_mode_is_8023z(state->interface)) {
ca366d6c
RD		 2941 phylink_set(mask, 10baseT_Half);
2942 phylink_set(mask, 10baseT_Full);
2943 phylink_set(mask, 100baseT_Half);
2944 phylink_set(mask, 100baseT_Full);
88bdef8b 2945 phylink_set(mask, Autoneg);
38f790a8 2946 }
ca366d6c 2947
88bdef8b
LC		 2948 /* This switch only supports 1G full-duplex. */
2949 if (state->interface != PHY_INTERFACE_MODE_MII)
2950 phylink_set(mask, 1000baseT_Full);
2951
2952 priv->info->mac_port_validate(ds, port, mask);
2953
ca366d6c
RD		 2954 phylink_set(mask, Pause);
2955 phylink_set(mask, Asym_Pause);
2956
2957 linkmode_and(supported, supported, mask);
2958 linkmode_and(state->advertising, state->advertising, mask);
c288575f
LC		 2959
2960 /* We can only operate at 2500BaseX or 1000BaseX. If requested
2961 * to advertise both, only report advertising at 2500BaseX.
2962 */
2963 phylink_helper_basex_speed(state);
ca366d6c
RD		 2964}
2965
2966static int
2967mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
2968 struct phylink_link_state *state)
2969{
2970 struct mt7530_priv *priv = ds->priv;
2971 u32 pmsr;
2972
2973 if (port < 0 || port >= MT7530_NUM_PORTS)
2974 return -EINVAL;
2975
2976 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2977
2978 state->link = (pmsr & PMSR_LINK);
2979 state->an_complete = state->link;
2980 state->duplex = !!(pmsr & PMSR_DPX);
2981
2982 switch (pmsr & PMSR_SPEED_MASK) {
2983 case PMSR_SPEED_10:
2984 state->speed = SPEED_10;
2985 break;
2986 case PMSR_SPEED_100:
2987 state->speed = SPEED_100;
2988 break;
2989 case PMSR_SPEED_1000:
2990 state->speed = SPEED_1000;
2991 break;
2992 default:
2993 state->speed = SPEED_UNKNOWN;
2994 break;
2995 }
2996
2997 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2998 if (pmsr & PMSR_RX_FC)
2999 state->pause |= MLO_PAUSE_RX;
3000 if (pmsr & PMSR_TX_FC)
3001 state->pause |= MLO_PAUSE_TX;
3002
3003 return 1;
3004}
3005
c288575f
LC		 3006static int
3007mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
3008 struct phylink_link_state *state)
3009{
3010 u32 status, val;
3011 u16 config_reg;
3012
3013 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
3014 state->link = !!(status & MT7531_SGMII_LINK_STATUS);
3015 if (state->interface == PHY_INTERFACE_MODE_SGMII &&
3016 (status & MT7531_SGMII_AN_ENABLE)) {
3017 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
3018 config_reg = val >> 16;
3019
3020 switch (config_reg & LPA_SGMII_SPD_MASK) {
3021 case LPA_SGMII_1000:
3022 state->speed = SPEED_1000;
3023 break;
3024 case LPA_SGMII_100:
3025 state->speed = SPEED_100;
3026 break;
3027 case LPA_SGMII_10:
3028 state->speed = SPEED_10;
3029 break;
3030 default:
3031 dev_err(priv->dev, "invalid sgmii PHY speed\n");
3032 state->link = false;
3033 return -EINVAL;
3034 }
3035
3036 if (config_reg & LPA_SGMII_FULL_DUPLEX)
3037 state->duplex = DUPLEX_FULL;
3038 else
3039 state->duplex = DUPLEX_HALF;
3040 }
3041
3042 return 0;
3043}
3044
3045static int
3046mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
3047 struct phylink_link_state *state)
3048{
3049 struct mt7530_priv *priv = ds->priv;
3050
3051 if (state->interface == PHY_INTERFACE_MODE_SGMII)
3052 return mt7531_sgmii_pcs_get_state_an(priv, port, state);
3053
3054 return -EOPNOTSUPP;
3055}
3056
88bdef8b
LC		 3057static int
3058mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
3059 struct phylink_link_state *state)
3060{
3061 struct mt7530_priv *priv = ds->priv;
3062
3063 return priv->info->mac_port_get_state(ds, port, state);
3064}
3065
3066static int
3067mt753x_setup(struct dsa_switch *ds)
3068{
3069 struct mt7530_priv *priv = ds->priv;
ba751e28 3070 int ret = priv->info->sw_setup(ds);
88bdef8b 3071
ba751e28
DQ		 3072 if (ret)
3073 return ret;
88bdef8b 3074
ba751e28
DQ		 3075 ret = mt7530_setup_irq(priv);
3076 if (ret)
3077 return ret;
88bdef8b 3078
ba751e28
DQ		 3079 ret = mt7530_setup_mdio(priv);
3080 if (ret && priv->irq)
3081 mt7530_free_irq_common(priv);
88bdef8b 3082
ba751e28 3083 return ret;
88bdef8b
LC		 3084}
3085
40b5d2f1
RD		 3086static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,
3087 struct ethtool_eee *e)
3088{
3089 struct mt7530_priv *priv = ds->priv;
3090 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
3091
3092 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
3093 e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
3094
3095 return 0;
3096}
3097
3098static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
3099 struct ethtool_eee *e)
3100{
3101 struct mt7530_priv *priv = ds->priv;
3102 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;
3103
3104 if (e->tx_lpi_timer > 0xFFF)
3105 return -EINVAL;
3106
3107 set = SET_LPI_THRESH(e->tx_lpi_timer);
3108 if (!e->tx_lpi_enabled)
3109 /* Force LPI Mode without a delay */
3110 set |= LPI_MODE_EN;
3111 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
3112
3113 return 0;
3114}
3115
d78d6776 3116static const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8 3117 .get_tag_protocol = mtk_get_tag_protocol,
88bdef8b 3118 .setup = mt753x_setup,
b8f126a8 3119 .get_strings = mt7530_get_strings,
b8f126a8
SW		 3120 .get_ethtool_stats = mt7530_get_ethtool_stats,
3121 .get_sset_count = mt7530_get_sset_count,
ea6d5c92 3122 .set_ageing_time = mt7530_set_ageing_time,
b8f126a8
SW		 3123 .port_enable = mt7530_port_enable,
3124 .port_disable = mt7530_port_disable,
9470174e
DQ		 3125 .port_change_mtu = mt7530_port_change_mtu,
3126 .port_max_mtu = mt7530_port_max_mtu,
b8f126a8 3127 .port_stp_state_set = mt7530_stp_state_set,
5a30833b
DQ		 3128 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags,
3129 .port_bridge_flags = mt7530_port_bridge_flags,
b8f126a8
SW		 3130 .port_bridge_join = mt7530_port_bridge_join,
3131 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 3132 .port_fdb_add = mt7530_port_fdb_add,
3133 .port_fdb_del = mt7530_port_fdb_del,
3134 .port_fdb_dump = mt7530_port_fdb_dump,
5a30833b
DQ		 3135 .port_mdb_add = mt7530_port_mdb_add,
3136 .port_mdb_del = mt7530_port_mdb_del,
83163f7d 3137 .port_vlan_filtering = mt7530_port_vlan_filtering,
83163f7d
SW		 3138 .port_vlan_add = mt7530_port_vlan_add,
3139 .port_vlan_del = mt7530_port_vlan_del,
c288575f
LC		 3140 .port_mirror_add = mt753x_port_mirror_add,
3141 .port_mirror_del = mt753x_port_mirror_del,
88bdef8b
LC		 3142 .phylink_validate = mt753x_phylink_validate,
3143 .phylink_mac_link_state = mt753x_phylink_mac_link_state,
3144 .phylink_mac_config = mt753x_phylink_mac_config,
c288575f
LC		 3145 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
3146 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
3147 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
40b5d2f1
RD		 3148 .get_mac_eee = mt753x_get_mac_eee,
3149 .set_mac_eee = mt753x_set_mac_eee,
b8f126a8
SW		 3150};
3151
88bdef8b
LC		 3152static const struct mt753x_info mt753x_table[] = {
3153 [ID_MT7621] = {
3154 .id = ID_MT7621,
3155 .sw_setup = mt7530_setup,
3156 .phy_read = mt7530_phy_read,
3157 .phy_write = mt7530_phy_write,
3158 .pad_setup = mt7530_pad_clk_setup,
3159 .phy_mode_supported = mt7530_phy_mode_supported,
3160 .mac_port_validate = mt7530_mac_port_validate,
3161 .mac_port_get_state = mt7530_phylink_mac_link_state,
3162 .mac_port_config = mt7530_mac_config,
3163 },
3164 [ID_MT7530] = {
3165 .id = ID_MT7530,
3166 .sw_setup = mt7530_setup,
3167 .phy_read = mt7530_phy_read,
3168 .phy_write = mt7530_phy_write,
3169 .pad_setup = mt7530_pad_clk_setup,
3170 .phy_mode_supported = mt7530_phy_mode_supported,
3171 .mac_port_validate = mt7530_mac_port_validate,
3172 .mac_port_get_state = mt7530_phylink_mac_link_state,
3173 .mac_port_config = mt7530_mac_config,
3174 },
c288575f
LC		 3175 [ID_MT7531] = {
3176 .id = ID_MT7531,
3177 .sw_setup = mt7531_setup,
3178 .phy_read = mt7531_ind_phy_read,
3179 .phy_write = mt7531_ind_phy_write,
3180 .pad_setup = mt7531_pad_setup,
3181 .cpu_port_config = mt7531_cpu_port_config,
3182 .phy_mode_supported = mt7531_phy_mode_supported,
3183 .mac_port_validate = mt7531_mac_port_validate,
3184 .mac_port_get_state = mt7531_phylink_mac_link_state,
3185 .mac_port_config = mt7531_mac_config,
3186 .mac_pcs_an_restart = mt7531_sgmii_restart_an,
3187 .mac_pcs_link_up = mt7531_sgmii_link_up_force,
3188 },
88bdef8b
LC		 3189};
3190
ddda1ac1 3191static const struct of_device_id mt7530_of_match[] = {
88bdef8b
LC		 3192 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
3193 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
c288575f 3194 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
ddda1ac1
GU		 3195 { /* sentinel */ },
3196};
3197MODULE_DEVICE_TABLE(of, mt7530_of_match);
3198
b8f126a8
SW		 3199static int
3200mt7530_probe(struct mdio_device *mdiodev)
3201{
3202 struct mt7530_priv *priv;
3203 struct device_node *dn;
3204
3205 dn = mdiodev->dev.of_node;
3206
3207 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
3208 if (!priv)
3209 return -ENOMEM;
3210
7e99e347 3211 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
b8f126a8
SW		 3212 if (!priv->ds)
3213 return -ENOMEM;
3214
7e99e347 3215 priv->ds->dev = &mdiodev->dev;
342afce1 3216 priv->ds->num_ports = MT7530_NUM_PORTS;
7e99e347 3217
b8f126a8
SW		 3218 /* Use medatek,mcm property to distinguish hardware type that would
3219 * casues a little bit differences on power-on sequence.
3220 */
3221 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
3222 if (priv->mcm) {
3223 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
3224
3225 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
3226 if (IS_ERR(priv->rstc)) {
3227 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3228 return PTR_ERR(priv->rstc);
3229 }
3230 }
3231
ddda1ac1
GU		 3232 /* Get the hardware identifier from the devicetree node.
3233 * We will need it for some of the clock and regulator setup.
3234 */
88bdef8b
LC		 3235 priv->info = of_device_get_match_data(&mdiodev->dev);
3236 if (!priv->info)
3237 return -EINVAL;
3238
3239 /* Sanity check if these required device operations are filled
3240 * properly.
3241 */
3242 if (!priv->info->sw_setup || !priv->info->pad_setup ||
3243 !priv->info->phy_read || !priv->info->phy_write ||
3244 !priv->info->phy_mode_supported ||
3245 !priv->info->mac_port_validate ||
3246 !priv->info->mac_port_get_state || !priv->info->mac_port_config)
3247 return -EINVAL;
3248
3249 priv->id = priv->info->id;
b8f126a8 3250
ddda1ac1
GU		 3251 if (priv->id == ID_MT7530) {
3252 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
3253 if (IS_ERR(priv->core_pwr))
3254 return PTR_ERR(priv->core_pwr);
3255
3256 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
3257 if (IS_ERR(priv->io_pwr))
3258 return PTR_ERR(priv->io_pwr);
3259 }
b8f126a8
SW		 3260
3261 /* Not MCM that indicates switch works as the remote standalone
3262 * integrated circuit so the GPIO pin would be used to complete
3263 * the reset, otherwise memory-mapped register accessing used
3264 * through syscon provides in the case of MCM.
3265 */
3266 if (!priv->mcm) {
3267 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
3268 GPIOD_OUT_LOW);
3269 if (IS_ERR(priv->reset)) {
3270 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3271 return PTR_ERR(priv->reset);
3272 }
3273 }
3274
3275 priv->bus = mdiodev->bus;
3276 priv->dev = &mdiodev->dev;
3277 priv->ds->priv = priv;
3278 priv->ds->ops = &mt7530_switch_ops;
3279 mutex_init(&priv->reg_mutex);
3280 dev_set_drvdata(&mdiodev->dev, priv);
3281
23c9ee49 3282 return dsa_register_switch(priv->ds);
b8f126a8
SW		 3283}
3284
3285static void
3286mt7530_remove(struct mdio_device *mdiodev)
3287{
3288 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3289 int ret = 0;
3290
0650bf52
VO		 3291 if (!priv)
3292 return;
3293
b8f126a8
SW		 3294 ret = regulator_disable(priv->core_pwr);
3295 if (ret < 0)
3296 dev_err(priv->dev,
3297 "Failed to disable core power: %d\n", ret);
3298
3299 ret = regulator_disable(priv->io_pwr);
3300 if (ret < 0)
3301 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
3302 ret);
3303
ba751e28
DQ		 3304 if (priv->irq)
3305 mt7530_free_irq(priv);
3306
b8f126a8
SW		 3307 dsa_unregister_switch(priv->ds);
3308 mutex_destroy(&priv->reg_mutex);
0650bf52
VO		 3309
3310 dev_set_drvdata(&mdiodev->dev, NULL);
3311}
3312
3313static void mt7530_shutdown(struct mdio_device *mdiodev)
3314{
3315 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3316
3317 if (!priv)
3318 return;
3319
3320 dsa_switch_shutdown(priv->ds);
3321
3322 dev_set_drvdata(&mdiodev->dev, NULL);
b8f126a8
SW		 3323}
3324
b8f126a8
SW		 3325static struct mdio_driver mt7530_mdio_driver = {
3326 .probe = mt7530_probe,
3327 .remove = mt7530_remove,
0650bf52 3328 .shutdown = mt7530_shutdown,
b8f126a8
SW		 3329 .mdiodrv.driver = {
3330 .name = "mt7530",
3331 .of_match_table = mt7530_of_match,
3332 },
3333};
3334
3335mdio_module_driver(mt7530_mdio_driver);
3336
3337MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
3338MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
3339MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)