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net: dsa: mt7530: simplify mt7530_pad_clk_setup()
[linux-block.git] / drivers / net / dsa / mt7530.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
b8f126a8
SW		 2/*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
b8f126a8
SW		 5 */
6#include <linux/etherdevice.h>
7#include <linux/if_bridge.h>
8#include <linux/iopoll.h>
9#include <linux/mdio.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
ba751e28 13#include <linux/of_irq.h>
b8f126a8
SW		 14#include <linux/of_mdio.h>
15#include <linux/of_net.h>
16#include <linux/of_platform.h>
ca366d6c 17#include <linux/phylink.h>
b8f126a8
SW		 18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
eb976a55 21#include <linux/gpio/consumer.h>
429a0ede 22#include <linux/gpio/driver.h>
b8f126a8 23#include <net/dsa.h>
b8f126a8
SW		 24
25#include "mt7530.h"
26
cbd1f243
RKO		 27static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
28{
29 return container_of(pcs, struct mt753x_pcs, pcs);
30}
31
b8f126a8
SW		 32/* String, offset, and register size in bytes if different from 4 bytes */
33static const struct mt7530_mib_desc mt7530_mib[] = {
34 MIB_DESC(1, 0x00, "TxDrop"),
35 MIB_DESC(1, 0x04, "TxCrcErr"),
36 MIB_DESC(1, 0x08, "TxUnicast"),
37 MIB_DESC(1, 0x0c, "TxMulticast"),
38 MIB_DESC(1, 0x10, "TxBroadcast"),
39 MIB_DESC(1, 0x14, "TxCollision"),
40 MIB_DESC(1, 0x18, "TxSingleCollision"),
41 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
42 MIB_DESC(1, 0x20, "TxDeferred"),
43 MIB_DESC(1, 0x24, "TxLateCollision"),
44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
45 MIB_DESC(1, 0x2c, "TxPause"),
46 MIB_DESC(1, 0x30, "TxPktSz64"),
47 MIB_DESC(1, 0x34, "TxPktSz65To127"),
48 MIB_DESC(1, 0x38, "TxPktSz128To255"),
49 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
50 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
51 MIB_DESC(1, 0x44, "Tx1024ToMax"),
52 MIB_DESC(2, 0x48, "TxBytes"),
53 MIB_DESC(1, 0x60, "RxDrop"),
54 MIB_DESC(1, 0x64, "RxFiltering"),
aff51c5d 55 MIB_DESC(1, 0x68, "RxUnicast"),
b8f126a8
SW		 56 MIB_DESC(1, 0x6c, "RxMulticast"),
57 MIB_DESC(1, 0x70, "RxBroadcast"),
58 MIB_DESC(1, 0x74, "RxAlignErr"),
59 MIB_DESC(1, 0x78, "RxCrcErr"),
60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
61 MIB_DESC(1, 0x80, "RxFragErr"),
62 MIB_DESC(1, 0x84, "RxOverSzErr"),
63 MIB_DESC(1, 0x88, "RxJabberErr"),
64 MIB_DESC(1, 0x8c, "RxPause"),
65 MIB_DESC(1, 0x90, "RxPktSz64"),
66 MIB_DESC(1, 0x94, "RxPktSz65To127"),
67 MIB_DESC(1, 0x98, "RxPktSz128To255"),
68 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
71 MIB_DESC(2, 0xa8, "RxBytes"),
72 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
73 MIB_DESC(1, 0xb4, "RxIngressDrop"),
74 MIB_DESC(1, 0xb8, "RxArlDrop"),
75};
76
4732315c
IL		 77/* Since phy_device has not yet been created and
78 * phy_{read,write}_mmd_indirect is not available, we provide our own
79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
80 * to complete this function.
81 */
b8f126a8
SW		 82static int
83core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
84{
85 struct mii_bus *bus = priv->bus;
86 int value, ret;
87
88 /* Write the desired MMD Devad */
89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
90 if (ret < 0)
91 goto err;
92
93 /* Write the desired MMD register address */
94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
95 if (ret < 0)
96 goto err;
97
98 /* Select the Function : DATA with no post increment */
99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
100 if (ret < 0)
101 goto err;
102
103 /* Read the content of the MMD's selected register */
104 value = bus->read(bus, 0, MII_MMD_DATA);
105
106 return value;
107err:
108 dev_err(&bus->dev, "failed to read mmd register\n");
109
110 return ret;
111}
112
113static int
114core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
115 int devad, u32 data)
116{
117 struct mii_bus *bus = priv->bus;
118 int ret;
119
120 /* Write the desired MMD Devad */
121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
122 if (ret < 0)
123 goto err;
124
125 /* Write the desired MMD register address */
126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
127 if (ret < 0)
128 goto err;
129
130 /* Select the Function : DATA with no post increment */
131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
132 if (ret < 0)
133 goto err;
134
135 /* Write the data into MMD's selected register */
136 ret = bus->write(bus, 0, MII_MMD_DATA, data);
137err:
138 if (ret < 0)
139 dev_err(&bus->dev,
140 "failed to write mmd register\n");
141 return ret;
142}
143
144static void
1557c679 145mt7530_mutex_lock(struct mt7530_priv *priv)
b8f126a8 146{
54d4147a
DG		 147 if (priv->bus)
148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
1557c679 149}
b8f126a8 150
1557c679
DG		 151static void
152mt7530_mutex_unlock(struct mt7530_priv *priv)
153{
54d4147a
DG		 154 if (priv->bus)
155 mutex_unlock(&priv->bus->mdio_lock);
1557c679
DG		 156}
157
158static void
159core_write(struct mt7530_priv *priv, u32 reg, u32 val)
160{
161 mt7530_mutex_lock(priv);
b8f126a8
SW		 162
163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
164
1557c679 165 mt7530_mutex_unlock(priv);
b8f126a8
SW		 166}
167
168static void
169core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
170{
b8f126a8
SW		 171 u32 val;
172
1557c679 173 mt7530_mutex_lock(priv);
b8f126a8
SW		 174
175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
176 val &= ~mask;
177 val |= set;
178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
179
1557c679 180 mt7530_mutex_unlock(priv);
b8f126a8
SW		 181}
182
183static void
184core_set(struct mt7530_priv *priv, u32 reg, u32 val)
185{
186 core_rmw(priv, reg, 0, val);
187}
188
189static void
190core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
191{
192 core_rmw(priv, reg, val, 0);
193}
194
a08c0455
DG		 195static int
196mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
197{
198 int ret;
199
200 ret = regmap_write(priv->regmap, reg, val);
201
b8f126a8 202 if (ret < 0)
a08c0455 203 dev_err(priv->dev,
b8f126a8 204 "failed to write mt7530 register\n");
a08c0455 205
b8f126a8
SW		 206 return ret;
207}
208
a08c0455
DG		 209static u32
210mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
211{
212 int ret;
213 u32 val;
214
215 ret = regmap_read(priv->regmap, reg, &val);
216 if (ret) {
b6f56cdd 217 WARN_ON_ONCE(1);
a08c0455 218 dev_err(priv->dev,
b8f126a8 219 "failed to read mt7530 register\n");
b6f56cdd 220 return 0;
b8f126a8
SW		 221 }
222
a08c0455 223 return val;
b8f126a8
SW		 224}
225
226static void
227mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
228{
1557c679 229 mt7530_mutex_lock(priv);
b8f126a8
SW		 230
231 mt7530_mii_write(priv, reg, val);
232
1557c679 233 mt7530_mutex_unlock(priv);
b8f126a8
SW		 234}
235
c288575f
LC		 236static u32
237_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
238{
239 return mt7530_mii_read(p->priv, p->reg);
240}
241
b8f126a8
SW		 242static u32
243_mt7530_read(struct mt7530_dummy_poll *p)
244{
b8f126a8
SW		 245 u32 val;
246
1557c679 247 mt7530_mutex_lock(p->priv);
b8f126a8
SW		 248
249 val = mt7530_mii_read(p->priv, p->reg);
250
1557c679 251 mt7530_mutex_unlock(p->priv);
b8f126a8
SW		 252
253 return val;
254}
255
256static u32
257mt7530_read(struct mt7530_priv *priv, u32 reg)
258{
259 struct mt7530_dummy_poll p;
260
261 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
262 return _mt7530_read(&p);
263}
264
265static void
266mt7530_rmw(struct mt7530_priv *priv, u32 reg,
267 u32 mask, u32 set)
268{
1557c679 269 mt7530_mutex_lock(priv);
b8f126a8 270
a08c0455 271 regmap_update_bits(priv->regmap, reg, mask, set);
b8f126a8 272
1557c679 273 mt7530_mutex_unlock(priv);
b8f126a8
SW		 274}
275
276static void
277mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
278{
a08c0455 279 mt7530_rmw(priv, reg, val, val);
b8f126a8
SW		 280}
281
282static void
283mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
284{
285 mt7530_rmw(priv, reg, val, 0);
286}
287
288static int
289mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
290{
291 u32 val;
292 int ret;
293 struct mt7530_dummy_poll p;
294
295 /* Set the command operating upon the MAC address entries */
296 val = ATC_BUSY | ATC_MAT(0) | cmd;
297 mt7530_write(priv, MT7530_ATC, val);
298
299 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
300 ret = readx_poll_timeout(_mt7530_read, &p, val,
301 !(val & ATC_BUSY), 20, 20000);
302 if (ret < 0) {
303 dev_err(priv->dev, "reset timeout\n");
304 return ret;
305 }
306
307 /* Additional sanity for read command if the specified
308 * entry is invalid
309 */
310 val = mt7530_read(priv, MT7530_ATC);
311 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
312 return -EINVAL;
313
314 if (rsp)
315 *rsp = val;
316
317 return 0;
318}
319
320static void
321mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
322{
323 u32 reg[3];
324 int i;
325
326 /* Read from ARL table into an array */
327 for (i = 0; i < 3; i++) {
328 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
329
330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
331 __func__, __LINE__, i, reg[i]);
332 }
333
334 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
344}
345
346static void
347mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
348 u8 port_mask, const u8 *mac,
349 u8 aging, u8 type)
350{
351 u32 reg[3] = { 0 };
352 int i;
353
354 reg[1] |= vid & CVID_MASK;
73c447ca
DQ		 355 reg[1] |= ATA2_IVL;
356 reg[1] |= ATA2_FID(FID_BRIDGED);
b8f126a8
SW		 357 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
358 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
359 /* STATIC_ENT indicate that entry is static wouldn't
360 * be aged out and STATIC_EMP specified as erasing an
361 * entry
362 */
363 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
364 reg[1] |= mac[5] << MAC_BYTE_5;
365 reg[1] |= mac[4] << MAC_BYTE_4;
366 reg[0] |= mac[3] << MAC_BYTE_3;
367 reg[0] |= mac[2] << MAC_BYTE_2;
368 reg[0] |= mac[1] << MAC_BYTE_1;
369 reg[0] |= mac[0] << MAC_BYTE_0;
370
371 /* Write array into the ARL table */
372 for (i = 0; i < 3; i++)
373 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
374}
375
c8b8a3c6
VO		 376/* Set up switch core clock for MT7530 */
377static void mt7530_pll_setup(struct mt7530_priv *priv)
378{
8f058a6e
AÜ		 379 /* Disable core clock */
380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
381
c8b8a3c6
VO		 382 /* Disable PLL */
383 core_write(priv, CORE_GSWPLL_GRP1, 0);
384
385 /* Set core clock into 500Mhz */
386 core_write(priv, CORE_GSWPLL_GRP2,
387 RG_GSWPLL_POSDIV_500M(1) |
388 RG_GSWPLL_FBKDIV_500M(25));
389
390 /* Enable PLL */
391 core_write(priv, CORE_GSWPLL_GRP1,
392 RG_GSWPLL_EN_PRE |
393 RG_GSWPLL_POSDIV_200M(2) |
394 RG_GSWPLL_FBKDIV_200M(32));
8f058a6e
AÜ		 395
396 udelay(20);
397
398 /* Enable core clock */
399 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
c8b8a3c6
VO		 400}
401
b79d7c14
VO		 402/* If port 6 is available as a CPU port, always prefer that as the default,
403 * otherwise don't care.
404 */
405static struct dsa_port *
406mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds)
407{
408 struct dsa_port *cpu_dp = dsa_to_port(ds, 6);
409
410 if (dsa_port_is_cpu(cpu_dp))
411 return cpu_dp;
412
413 return NULL;
414}
415
fdcc8ccd 416/* Setup port 6 interface mode and TRGMII TX circuit */
b8f126a8 417static int
88bdef8b 418mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
b8f126a8
SW		 419{
420 struct mt7530_priv *priv = ds->priv;
4eec447e
AÜ		 421 u32 ncpo1, ssc_delta, xtal;
422
423 /* Disable the MT7530 TRGMII clocks */
424 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
425
426 if (interface == PHY_INTERFACE_MODE_RGMII) {
427 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
428 P6_INTF_MODE(0));
429 return 0;
430 }
431
432 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
7ef6f6f8
RD		 433
434 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
435
4eec447e
AÜ		 436 if (xtal == HWTRAP_XTAL_25MHZ)
437 ssc_delta = 0x57;
438 else
439 ssc_delta = 0x87;
440
441 if (priv->id == ID_MT7621) {
442 /* PLL frequency: 125MHz: 1.0GBit */
443 if (xtal == HWTRAP_XTAL_40MHZ)
444 ncpo1 = 0x0640;
407b508b 445 if (xtal == HWTRAP_XTAL_25MHZ)
4eec447e
AÜ		 446 ncpo1 = 0x0a00;
447 } else { /* PLL frequency: 250MHz: 2.0Gbit */
448 if (xtal == HWTRAP_XTAL_40MHZ)
449 ncpo1 = 0x0c80;
450 if (xtal == HWTRAP_XTAL_25MHZ)
451 ncpo1 = 0x1400;
b8f126a8
SW		 452 }
453
4eec447e
AÜ		 454 /* Setup the MT7530 TRGMII Tx Clock */
455 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
456 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
457 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
458 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
459 core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
460 RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
461 core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL |
462 RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1));
463 core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG |
464 RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
465
466 /* Enable the MT7530 TRGMII clocks */
467 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
0b086d76 468
b8f126a8
SW		 469 return 0;
470}
471
c288575f
LC		 472static int
473mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
474{
42bc4faf
AC		 475 return 0;
476}
477
478static void
479mt7531_pll_setup(struct mt7530_priv *priv)
480{
c288575f
LC		 481 u32 top_sig;
482 u32 hwstrap;
483 u32 xtal;
484 u32 val;
485
c288575f
LC		 486 val = mt7530_read(priv, MT7531_CREV);
487 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
488 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
489 if ((val & CHIP_REV_M) > 0)
490 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
491 HWTRAP_XTAL_FSEL_25MHZ;
492 else
493 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
494
495 /* Step 1 : Disable MT7531 COREPLL */
496 val = mt7530_read(priv, MT7531_PLLGP_EN);
497 val &= ~EN_COREPLL;
498 mt7530_write(priv, MT7531_PLLGP_EN, val);
499
500 /* Step 2: switch to XTAL output */
501 val = mt7530_read(priv, MT7531_PLLGP_EN);
502 val |= SW_CLKSW;
503 mt7530_write(priv, MT7531_PLLGP_EN, val);
504
505 val = mt7530_read(priv, MT7531_PLLGP_CR0);
506 val &= ~RG_COREPLL_EN;
507 mt7530_write(priv, MT7531_PLLGP_CR0, val);
508
509 /* Step 3: disable PLLGP and enable program PLLGP */
510 val = mt7530_read(priv, MT7531_PLLGP_EN);
511 val |= SW_PLLGP;
512 mt7530_write(priv, MT7531_PLLGP_EN, val);
513
514 /* Step 4: program COREPLL output frequency to 500MHz */
515 val = mt7530_read(priv, MT7531_PLLGP_CR0);
516 val &= ~RG_COREPLL_POSDIV_M;
517 val |= 2 << RG_COREPLL_POSDIV_S;
518 mt7530_write(priv, MT7531_PLLGP_CR0, val);
519 usleep_range(25, 35);
520
521 switch (xtal) {
522 case HWTRAP_XTAL_FSEL_25MHZ:
523 val = mt7530_read(priv, MT7531_PLLGP_CR0);
524 val &= ~RG_COREPLL_SDM_PCW_M;
525 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
526 mt7530_write(priv, MT7531_PLLGP_CR0, val);
527 break;
528 case HWTRAP_XTAL_FSEL_40MHZ:
529 val = mt7530_read(priv, MT7531_PLLGP_CR0);
530 val &= ~RG_COREPLL_SDM_PCW_M;
531 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
532 mt7530_write(priv, MT7531_PLLGP_CR0, val);
533 break;
0e8c266c 534 }
c288575f
LC		 535
536 /* Set feedback divide ratio update signal to high */
537 val = mt7530_read(priv, MT7531_PLLGP_CR0);
538 val |= RG_COREPLL_SDM_PCW_CHG;
539 mt7530_write(priv, MT7531_PLLGP_CR0, val);
540 /* Wait for at least 16 XTAL clocks */
541 usleep_range(10, 20);
542
543 /* Step 5: set feedback divide ratio update signal to low */
544 val = mt7530_read(priv, MT7531_PLLGP_CR0);
545 val &= ~RG_COREPLL_SDM_PCW_CHG;
546 mt7530_write(priv, MT7531_PLLGP_CR0, val);
547
548 /* Enable 325M clock for SGMII */
549 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
550
551 /* Enable 250SSC clock for RGMII */
552 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
553
554 /* Step 6: Enable MT7531 PLL */
555 val = mt7530_read(priv, MT7531_PLLGP_CR0);
556 val |= RG_COREPLL_EN;
557 mt7530_write(priv, MT7531_PLLGP_CR0, val);
558
559 val = mt7530_read(priv, MT7531_PLLGP_EN);
560 val |= EN_COREPLL;
561 mt7530_write(priv, MT7531_PLLGP_EN, val);
562 usleep_range(25, 35);
c288575f
LC		 563}
564
b8f126a8
SW		 565static void
566mt7530_mib_reset(struct dsa_switch *ds)
567{
568 struct mt7530_priv *priv = ds->priv;
569
570 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
571 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
572}
573
defa2e54 574static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)
b8f126a8 575{
b8f126a8
SW		 576 return mdiobus_read_nested(priv->bus, port, regnum);
577}
578
defa2e54
AL		 579static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum,
580 u16 val)
b8f126a8 581{
b8f126a8
SW		 582 return mdiobus_write_nested(priv->bus, port, regnum, val);
583}
584
defa2e54
AL		 585static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port,
586 int devad, int regnum)
587{
588 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum);
589}
590
591static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad,
592 int regnum, u16 val)
593{
594 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val);
595}
596
c288575f
LC		 597static int
598mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
599 int regnum)
600{
c288575f
LC		 601 struct mt7530_dummy_poll p;
602 u32 reg, val;
603 int ret;
604
605 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
606
1557c679 607 mt7530_mutex_lock(priv);
c288575f
LC		 608
609 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
610 !(val & MT7531_PHY_ACS_ST), 20, 100000);
611 if (ret < 0) {
612 dev_err(priv->dev, "poll timeout\n");
613 goto out;
614 }
615
616 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
617 MT7531_MDIO_DEV_ADDR(devad) | regnum;
618 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
619
620 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
621 !(val & MT7531_PHY_ACS_ST), 20, 100000);
622 if (ret < 0) {
623 dev_err(priv->dev, "poll timeout\n");
624 goto out;
625 }
626
627 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
628 MT7531_MDIO_DEV_ADDR(devad);
629 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
630
631 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
632 !(val & MT7531_PHY_ACS_ST), 20, 100000);
633 if (ret < 0) {
634 dev_err(priv->dev, "poll timeout\n");
635 goto out;
636 }
637
638 ret = val & MT7531_MDIO_RW_DATA_MASK;
639out:
1557c679 640 mt7530_mutex_unlock(priv);
c288575f
LC		 641
642 return ret;
643}
644
645static int
646mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
defa2e54 647 int regnum, u16 data)
c288575f 648{
c288575f
LC		 649 struct mt7530_dummy_poll p;
650 u32 val, reg;
651 int ret;
652
653 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
654
1557c679 655 mt7530_mutex_lock(priv);
c288575f
LC		 656
657 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
658 !(val & MT7531_PHY_ACS_ST), 20, 100000);
659 if (ret < 0) {
660 dev_err(priv->dev, "poll timeout\n");
661 goto out;
662 }
663
664 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
665 MT7531_MDIO_DEV_ADDR(devad) | regnum;
666 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
667
668 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
669 !(val & MT7531_PHY_ACS_ST), 20, 100000);
670 if (ret < 0) {
671 dev_err(priv->dev, "poll timeout\n");
672 goto out;
673 }
674
675 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
676 MT7531_MDIO_DEV_ADDR(devad) | data;
677 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
678
679 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
680 !(val & MT7531_PHY_ACS_ST), 20, 100000);
681 if (ret < 0) {
682 dev_err(priv->dev, "poll timeout\n");
683 goto out;
684 }
685
686out:
1557c679 687 mt7530_mutex_unlock(priv);
c288575f
LC		 688
689 return ret;
690}
691
692static int
693mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
694{
c288575f
LC		 695 struct mt7530_dummy_poll p;
696 int ret;
697 u32 val;
698
699 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
700
1557c679 701 mt7530_mutex_lock(priv);
c288575f
LC		 702
703 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
704 !(val & MT7531_PHY_ACS_ST), 20, 100000);
705 if (ret < 0) {
706 dev_err(priv->dev, "poll timeout\n");
707 goto out;
708 }
709
710 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
711 MT7531_MDIO_REG_ADDR(regnum);
712
713 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
714
715 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
716 !(val & MT7531_PHY_ACS_ST), 20, 100000);
717 if (ret < 0) {
718 dev_err(priv->dev, "poll timeout\n");
719 goto out;
720 }
721
722 ret = val & MT7531_MDIO_RW_DATA_MASK;
723out:
1557c679 724 mt7530_mutex_unlock(priv);
c288575f
LC		 725
726 return ret;
727}
728
729static int
730mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
731 u16 data)
732{
c288575f
LC		 733 struct mt7530_dummy_poll p;
734 int ret;
735 u32 reg;
736
737 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
738
1557c679 739 mt7530_mutex_lock(priv);
c288575f
LC		 740
741 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
742 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
743 if (ret < 0) {
744 dev_err(priv->dev, "poll timeout\n");
745 goto out;
746 }
747
748 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
749 MT7531_MDIO_REG_ADDR(regnum) | data;
750
751 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
752
753 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
754 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
755 if (ret < 0) {
756 dev_err(priv->dev, "poll timeout\n");
757 goto out;
758 }
759
760out:
1557c679 761 mt7530_mutex_unlock(priv);
c288575f
LC		 762
763 return ret;
764}
765
766static int
defa2e54 767mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum)
c288575f 768{
defa2e54 769 struct mt7530_priv *priv = bus->priv;
c288575f 770
defa2e54 771 return priv->info->phy_read_c22(priv, port, regnum);
c288575f
LC		 772}
773
774static int
defa2e54 775mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum)
c288575f 776{
defa2e54 777 struct mt7530_priv *priv = bus->priv;
c288575f 778
defa2e54 779 return priv->info->phy_read_c45(priv, port, devad, regnum);
c288575f
LC		 780}
781
ba751e28 782static int
defa2e54 783mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val)
ba751e28
DQ		 784{
785 struct mt7530_priv *priv = bus->priv;
786
defa2e54 787 return priv->info->phy_write_c22(priv, port, regnum, val);
ba751e28
DQ		 788}
789
790static int
defa2e54
AL		 791mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum,
792 u16 val)
ba751e28
DQ		 793{
794 struct mt7530_priv *priv = bus->priv;
795
defa2e54 796 return priv->info->phy_write_c45(priv, port, devad, regnum, val);
ba751e28
DQ		 797}
798
b8f126a8 799static void
89f09048
FF		 800mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
801 uint8_t *data)
b8f126a8
SW		 802{
803 int i;
804
89f09048
FF		 805 if (stringset != ETH_SS_STATS)
806 return;
807
b8f126a8 808 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
e403cfff 809 ethtool_puts(&data, mt7530_mib[i].name);
b8f126a8
SW		 810}
811
812static void
813mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
814 uint64_t *data)
815{
816 struct mt7530_priv *priv = ds->priv;
817 const struct mt7530_mib_desc *mib;
818 u32 reg, i;
819 u64 hi;
820
821 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
822 mib = &mt7530_mib[i];
823 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
824
825 data[i] = mt7530_read(priv, reg);
826 if (mib->size == 2) {
827 hi = mt7530_read(priv, reg + 4);
828 data[i] |= hi << 32;
829 }
830 }
831}
832
833static int
89f09048 834mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
b8f126a8 835{
89f09048
FF		 836 if (sset != ETH_SS_STATS)
837 return 0;
838
b8f126a8
SW		 839 return ARRAY_SIZE(mt7530_mib);
840}
841
ea6d5c92
DQ		 842static int
843mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
844{
845 struct mt7530_priv *priv = ds->priv;
846 unsigned int secs = msecs / 1000;
847 unsigned int tmp_age_count;
848 unsigned int error = -1;
849 unsigned int age_count;
850 unsigned int age_unit;
851
852 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
853 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
854 return -ERANGE;
855
856 /* iterate through all possible age_count to find the closest pair */
857 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
858 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
859
860 if (tmp_age_unit <= AGE_UNIT_MAX) {
861 unsigned int tmp_error = secs -
862 (tmp_age_count + 1) * (tmp_age_unit + 1);
863
864 /* found a closer pair */
865 if (error > tmp_error) {
866 error = tmp_error;
867 age_count = tmp_age_count;
868 age_unit = tmp_age_unit;
869 }
870
871 /* found the exact match, so break the loop */
872 if (!error)
873 break;
874 }
875 }
876
877 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
878
879 return 0;
880}
881
25d15dee
DG		 882static const char *p5_intf_modes(unsigned int p5_interface)
883{
884 switch (p5_interface) {
885 case P5_DISABLED:
886 return "DISABLED";
887 case P5_INTF_SEL_PHY_P0:
888 return "PHY P0";
889 case P5_INTF_SEL_PHY_P4:
890 return "PHY P4";
891 case P5_INTF_SEL_GMAC5:
892 return "GMAC5";
25d15dee
DG		 893 default:
894 return "unknown";
895 }
896}
897
38f790a8
RD		 898static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
899{
900 struct mt7530_priv *priv = ds->priv;
901 u8 tx_delay = 0;
902 int val;
903
904 mutex_lock(&priv->reg_mutex);
905
906 val = mt7530_read(priv, MT7530_MHWTRAP);
907
908 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
909 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
910
911 switch (priv->p5_intf_sel) {
912 case P5_INTF_SEL_PHY_P0:
913 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
914 val |= MHWTRAP_PHY0_SEL;
df561f66 915 fallthrough;
38f790a8
RD		 916 case P5_INTF_SEL_PHY_P4:
917 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
918 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
919
920 /* Setup the MAC by default for the cpu port */
921 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
922 break;
923 case P5_INTF_SEL_GMAC5:
924 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
925 val &= ~MHWTRAP_P5_DIS;
926 break;
38f790a8 927 default:
01fc4294 928 break;
38f790a8
RD		 929 }
930
931 /* Setup RGMII settings */
932 if (phy_interface_mode_is_rgmii(interface)) {
933 val |= MHWTRAP_P5_RGMII_MODE;
934
935 /* P5 RGMII RX Clock Control: delay setting for 1000M */
936 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
937
938 /* Don't set delay in DSA mode */
939 if (!dsa_is_dsa_port(priv->ds, 5) &&
940 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
941 interface == PHY_INTERFACE_MODE_RGMII_ID))
942 tx_delay = 4; /* n * 0.5 ns */
943
944 /* P5 RGMII TX Clock Control: delay x */
945 mt7530_write(priv, MT7530_P5RGMIITXCR,
946 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
947
948 /* reduce P5 RGMII Tx driving, 8mA */
949 mt7530_write(priv, MT7530_IO_DRV_CR,
950 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
951 }
952
953 mt7530_write(priv, MT7530_MHWTRAP, val);
954
955 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
956 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
957
38f790a8
RD		 958 mutex_unlock(&priv->reg_mutex);
959}
960
d7c66073
AÜ		 961static void
962mt753x_trap_frames(struct mt7530_priv *priv)
963{
964 /* Trap BPDUs to the CPU port(s) */
965 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
966 MT753X_BPDU_CPU_ONLY);
8332cf6f 967
e94b590a
AÜ		 968 /* Trap 802.1X PAE frames to the CPU port(s) */
969 mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_PORT_FW_MASK,
970 MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY));
971
8332cf6f
AÜ		 972 /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */
973 mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK,
974 MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY));
d7c66073
AÜ		 975}
976
b8f126a8 977static int
c288575f 978mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
b8f126a8 979{
c288575f 980 struct mt7530_priv *priv = ds->priv;
0ce0c3cd 981 int ret;
c288575f
LC		 982
983 /* Setup max capability of CPU port at first */
0ce0c3cd
AD		 984 if (priv->info->cpu_port_config) {
985 ret = priv->info->cpu_port_config(ds, port);
986 if (ret)
987 return ret;
988 }
c288575f 989
b8f126a8
SW		 990 /* Enable Mediatek header mode on the cpu port */
991 mt7530_write(priv, MT7530_PVC_P(port),
992 PORT_SPEC_TAG);
993
120a56b0
AÜ		 994 /* Enable flooding on the CPU port */
995 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
996 UNU_FFP(BIT(port)));
b8f126a8 997
ff221029
AÜ		 998 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
999 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
1000 * is affine to the inbound user port.
1001 */
1002 if (priv->id == ID_MT7531 || priv->id == ID_MT7988)
1003 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port)));
1004
b8f126a8 1005 /* CPU port gets connected to all user ports of
c288575f 1006 * the switch.
b8f126a8
SW		 1007 */
1008 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 1009 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8 1010
6087175b
DQ		 1011 /* Set to fallback mode for independent VLAN learning */
1012 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1013 MT7530_PORT_FALLBACK_MODE);
1014
b8f126a8
SW		 1015 return 0;
1016}
1017
1018static int
1019mt7530_port_enable(struct dsa_switch *ds, int port,
1020 struct phy_device *phy)
1021{
1f9a6abe 1022 struct dsa_port *dp = dsa_to_port(ds, port);
b8f126a8
SW		 1023 struct mt7530_priv *priv = ds->priv;
1024
1025 mutex_lock(&priv->reg_mutex);
1026
b8f126a8
SW		 1027 /* Allow the user port gets connected to the cpu port and also
1028 * restore the port matrix if the port is the member of a certain
1029 * bridge.
1030 */
1f9a6abe
FW		 1031 if (dsa_port_is_user(dp)) {
1032 struct dsa_port *cpu_dp = dp->cpu_dp;
1033
1034 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index));
1035 }
b8f126a8
SW		 1036 priv->ports[port].enable = true;
1037 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1038 priv->ports[port].pm);
1d01145f 1039 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1040
1041 mutex_unlock(&priv->reg_mutex);
1042
1043 return 0;
1044}
1045
1046static void
75104db0 1047mt7530_port_disable(struct dsa_switch *ds, int port)
b8f126a8
SW		 1048{
1049 struct mt7530_priv *priv = ds->priv;
1050
1051 mutex_lock(&priv->reg_mutex);
1052
1053 /* Clear up all port matrix which could be restored in the next
1054 * enablement for the port.
1055 */
1056 priv->ports[port].enable = false;
1057 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1058 PCR_MATRIX_CLR);
1d01145f 1059 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1060
1061 mutex_unlock(&priv->reg_mutex);
1062}
1063
9470174e
DQ		 1064static int
1065mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1066{
1067 struct mt7530_priv *priv = ds->priv;
9470174e
DQ		 1068 int length;
1069 u32 val;
1070
1071 /* When a new MTU is set, DSA always set the CPU port's MTU to the
6ca80638 1072 * largest MTU of the user ports. Because the switch only has a global
9470174e
DQ		 1073 * RX length register, only allowing CPU port here is enough.
1074 */
1075 if (!dsa_is_cpu_port(ds, port))
1076 return 0;
1077
1557c679 1078 mt7530_mutex_lock(priv);
9470174e
DQ		 1079
1080 val = mt7530_mii_read(priv, MT7530_GMACCR);
1081 val &= ~MAX_RX_PKT_LEN_MASK;
1082
1083 /* RX length also includes Ethernet header, MTK tag, and FCS length */
1084 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1085 if (length <= 1522) {
1086 val |= MAX_RX_PKT_LEN_1522;
1087 } else if (length <= 1536) {
1088 val |= MAX_RX_PKT_LEN_1536;
1089 } else if (length <= 1552) {
1090 val |= MAX_RX_PKT_LEN_1552;
1091 } else {
1092 val &= ~MAX_RX_JUMBO_MASK;
1093 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1094 val |= MAX_RX_PKT_LEN_JUMBO;
1095 }
1096
1097 mt7530_mii_write(priv, MT7530_GMACCR, val);
1098
1557c679 1099 mt7530_mutex_unlock(priv);
9470174e
DQ		 1100
1101 return 0;
1102}
1103
1104static int
1105mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1106{
1107 return MT7530_MAX_MTU;
1108}
1109
b8f126a8
SW		 1110static void
1111mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1112{
1113 struct mt7530_priv *priv = ds->priv;
1114 u32 stp_state;
1115
1116 switch (state) {
1117 case BR_STATE_DISABLED:
1118 stp_state = MT7530_STP_DISABLED;
1119 break;
1120 case BR_STATE_BLOCKING:
1121 stp_state = MT7530_STP_BLOCKING;
1122 break;
1123 case BR_STATE_LISTENING:
1124 stp_state = MT7530_STP_LISTENING;
1125 break;
1126 case BR_STATE_LEARNING:
1127 stp_state = MT7530_STP_LEARNING;
1128 break;
1129 case BR_STATE_FORWARDING:
1130 default:
1131 stp_state = MT7530_STP_FORWARDING;
1132 break;
1133 }
1134
a9e3f62d
DQ		 1135 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED),
1136 FID_PST(FID_BRIDGED, stp_state));
b8f126a8
SW		 1137}
1138
5a30833b
DQ		 1139static int
1140mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1141 struct switchdev_brport_flags flags,
1142 struct netlink_ext_ack *extack)
1143{
1144 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1145 BR_BCAST_FLOOD))
1146 return -EINVAL;
1147
1148 return 0;
1149}
1150
1151static int
1152mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
1153 struct switchdev_brport_flags flags,
1154 struct netlink_ext_ack *extack)
1155{
1156 struct mt7530_priv *priv = ds->priv;
1157
1158 if (flags.mask & BR_LEARNING)
1159 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
1160 flags.val & BR_LEARNING ? 0 : SA_DIS);
1161
1162 if (flags.mask & BR_FLOOD)
1163 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
1164 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1165
1166 if (flags.mask & BR_MCAST_FLOOD)
1167 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1168 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1169
1170 if (flags.mask & BR_BCAST_FLOOD)
1171 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
1172 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1173
1174 return 0;
1175}
1176
b8f126a8
SW		 1177static int
1178mt7530_port_bridge_join(struct dsa_switch *ds, int port,
06b9cce4
VO		 1179 struct dsa_bridge bridge, bool *tx_fwd_offload,
1180 struct netlink_ext_ack *extack)
b8f126a8 1181{
872bb81d 1182 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1f9a6abe
FW		 1183 struct dsa_port *cpu_dp = dp->cpu_dp;
1184 u32 port_bitmap = BIT(cpu_dp->index);
872bb81d 1185 struct mt7530_priv *priv = ds->priv;
b8f126a8
SW		 1186
1187 mutex_lock(&priv->reg_mutex);
1188
872bb81d
VO		 1189 dsa_switch_for_each_user_port(other_dp, ds) {
1190 int other_port = other_dp->index;
1191
1192 if (dp == other_dp)
1193 continue;
1194
b8f126a8
SW		 1195 /* Add this port to the port matrix of the other ports in the
1196 * same bridge. If the port is disabled, port matrix is kept
1197 * and not being setup until the port becomes enabled.
1198 */
d3eed0e5 1199 if (!dsa_port_offloads_bridge(other_dp, &bridge))
872bb81d
VO		 1200 continue;
1201
1202 if (priv->ports[other_port].enable)
1203 mt7530_set(priv, MT7530_PCR_P(other_port),
1204 PCR_MATRIX(BIT(port)));
1205 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port));
1206
1207 port_bitmap |= BIT(other_port);
b8f126a8
SW		 1208 }
1209
1210 /* Add the all other ports to this port matrix. */
1211 if (priv->ports[port].enable)
1212 mt7530_rmw(priv, MT7530_PCR_P(port),
1213 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1214 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1215
6087175b
DQ		 1216 /* Set to fallback mode for independent VLAN learning */
1217 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1218 MT7530_PORT_FALLBACK_MODE);
1219
b8f126a8
SW		 1220 mutex_unlock(&priv->reg_mutex);
1221
1222 return 0;
1223}
1224
83163f7d
SW		 1225static void
1226mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1227{
1228 struct mt7530_priv *priv = ds->priv;
1229 bool all_user_ports_removed = true;
1230 int i;
1231
6087175b
DQ		 1232 /* This is called after .port_bridge_leave when leaving a VLAN-aware
1233 * bridge. Don't set standalone ports to fallback mode.
83163f7d 1234 */
41fb0cf1 1235 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
6087175b
DQ		 1236 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1237 MT7530_PORT_FALLBACK_MODE);
1238
8fbebef8
DQ		 1239 mt7530_rmw(priv, MT7530_PVC_P(port),
1240 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
e045124e 1241 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
8fbebef8
DQ		 1242 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
1243 MT7530_VLAN_ACC_ALL);
83163f7d 1244
6087175b
DQ		 1245 /* Set PVID to 0 */
1246 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1247 G0_PORT_VID_DEF);
1248
83163f7d
SW		 1249 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1250 if (dsa_is_user_port(ds, i) &&
68bb8ea8 1251 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
83163f7d
SW		 1252 all_user_ports_removed = false;
1253 break;
1254 }
1255 }
1256
1257 /* CPU port also does the same thing until all user ports belonging to
1258 * the CPU port get out of VLAN filtering mode.
1259 */
1260 if (all_user_ports_removed) {
1f9a6abe
FW		 1261 struct dsa_port *dp = dsa_to_port(ds, port);
1262 struct dsa_port *cpu_dp = dp->cpu_dp;
1263
1264 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index),
83163f7d 1265 PCR_MATRIX(dsa_user_ports(priv->ds)));
1f9a6abe 1266 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG
e045124e 1267 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d
SW		 1268 }
1269}
1270
1271static void
1272mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1273{
1274 struct mt7530_priv *priv = ds->priv;
1275
83163f7d 1276 /* Trapped into security mode allows packet forwarding through VLAN
6087175b 1277 * table lookup.
83163f7d 1278 */
6087175b 1279 if (dsa_is_user_port(ds, port)) {
38152ea3
DQ		 1280 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1281 MT7530_PORT_SECURITY_MODE);
6087175b
DQ		 1282 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1283 G0_PORT_VID(priv->ports[port].pvid));
8fbebef8
DQ		 1284
1285 /* Only accept tagged frames if PVID is not set */
1286 if (!priv->ports[port].pvid)
1287 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1288 MT7530_VLAN_ACC_TAGGED);
83163f7d 1289
0b6d6425
VO		 1290 /* Set the port as a user port which is to be able to recognize
1291 * VID from incoming packets before fetching entry within the
1292 * VLAN table.
1293 */
1294 mt7530_rmw(priv, MT7530_PVC_P(port),
1295 VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1296 VLAN_ATTR(MT7530_VLAN_USER) |
1297 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
1298 } else {
1299 /* Also set CPU ports to the "user" VLAN port attribute, to
1300 * allow VLAN classification, but keep the EG_TAG attribute as
1301 * "consistent" (i.o.w. don't change its value) for packets
1302 * received by the switch from the CPU, so that tagged packets
1303 * are forwarded to user ports as tagged, and untagged as
1304 * untagged.
1305 */
1306 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
1307 VLAN_ATTR(MT7530_VLAN_USER));
1308 }
83163f7d
SW		 1309}
1310
b8f126a8
SW		 1311static void
1312mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
d3eed0e5 1313 struct dsa_bridge bridge)
b8f126a8 1314{
872bb81d 1315 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1f9a6abe 1316 struct dsa_port *cpu_dp = dp->cpu_dp;
b8f126a8 1317 struct mt7530_priv *priv = ds->priv;
b8f126a8
SW		 1318
1319 mutex_lock(&priv->reg_mutex);
1320
872bb81d
VO		 1321 dsa_switch_for_each_user_port(other_dp, ds) {
1322 int other_port = other_dp->index;
1323
1324 if (dp == other_dp)
1325 continue;
1326
b8f126a8
SW		 1327 /* Remove this port from the port matrix of the other ports
1328 * in the same bridge. If the port is disabled, port matrix
1329 * is kept and not being setup until the port becomes enabled.
1330 */
d3eed0e5 1331 if (!dsa_port_offloads_bridge(other_dp, &bridge))
872bb81d
VO		 1332 continue;
1333
1334 if (priv->ports[other_port].enable)
1335 mt7530_clear(priv, MT7530_PCR_P(other_port),
1336 PCR_MATRIX(BIT(port)));
1337 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port));
b8f126a8
SW		 1338 }
1339
1340 /* Set the cpu port to be the only one in the port matrix of
1341 * this port.
1342 */
1343 if (priv->ports[port].enable)
1344 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1f9a6abe
FW		 1345 PCR_MATRIX(BIT(cpu_dp->index)));
1346 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index));
b8f126a8 1347
6087175b
DQ		 1348 /* When a port is removed from the bridge, the port would be set up
1349 * back to the default as is at initial boot which is a VLAN-unaware
1350 * port.
1351 */
1352 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1353 MT7530_PORT_MATRIX_MODE);
1354
b8f126a8
SW		 1355 mutex_unlock(&priv->reg_mutex);
1356}
1357
1358static int
b8f126a8 1359mt7530_port_fdb_add(struct dsa_switch *ds, int port,
c2693363
VO		 1360 const unsigned char *addr, u16 vid,
1361 struct dsa_db db)
b8f126a8
SW		 1362{
1363 struct mt7530_priv *priv = ds->priv;
1b6dd556 1364 int ret;
b8f126a8
SW		 1365 u8 port_mask = BIT(port);
1366
1367 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1368 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 1369 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 1370 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 1371
1372 return ret;
b8f126a8
SW		 1373}
1374
1375static int
1376mt7530_port_fdb_del(struct dsa_switch *ds, int port,
c2693363
VO		 1377 const unsigned char *addr, u16 vid,
1378 struct dsa_db db)
b8f126a8
SW		 1379{
1380 struct mt7530_priv *priv = ds->priv;
1381 int ret;
1382 u8 port_mask = BIT(port);
1383
1384 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1385 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 1386 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 1387 mutex_unlock(&priv->reg_mutex);
1388
1389 return ret;
1390}
1391
1392static int
1393mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1394 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 1395{
1396 struct mt7530_priv *priv = ds->priv;
1397 struct mt7530_fdb _fdb = { 0 };
1398 int cnt = MT7530_NUM_FDB_RECORDS;
1399 int ret = 0;
1400 u32 rsp = 0;
1401
1402 mutex_lock(&priv->reg_mutex);
1403
1404 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1405 if (ret < 0)
1406 goto err;
1407
1408 do {
1409 if (rsp & ATC_SRCH_HIT) {
1410 mt7530_fdb_read(priv, &_fdb);
1411 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 1412 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1413 data);
b8f126a8
SW		 1414 if (ret < 0)
1415 break;
1416 }
1417 }
1418 } while (--cnt &&
1419 !(rsp & ATC_SRCH_END) &&
1420 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1421err:
1422 mutex_unlock(&priv->reg_mutex);
1423
1424 return 0;
1425}
1426
5a30833b
DQ		 1427static int
1428mt7530_port_mdb_add(struct dsa_switch *ds, int port,
c2693363
VO		 1429 const struct switchdev_obj_port_mdb *mdb,
1430 struct dsa_db db)
5a30833b
DQ		 1431{
1432 struct mt7530_priv *priv = ds->priv;
1433 const u8 *addr = mdb->addr;
1434 u16 vid = mdb->vid;
1435 u8 port_mask = 0;
1436 int ret;
1437
1438 mutex_lock(&priv->reg_mutex);
1439
1440 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1441 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1442 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1443 & PORT_MAP_MASK;
1444
1445 port_mask |= BIT(port);
1446 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1447 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1448
1449 mutex_unlock(&priv->reg_mutex);
1450
1451 return ret;
1452}
1453
1454static int
1455mt7530_port_mdb_del(struct dsa_switch *ds, int port,
c2693363
VO		 1456 const struct switchdev_obj_port_mdb *mdb,
1457 struct dsa_db db)
5a30833b
DQ		 1458{
1459 struct mt7530_priv *priv = ds->priv;
1460 const u8 *addr = mdb->addr;
1461 u16 vid = mdb->vid;
1462 u8 port_mask = 0;
1463 int ret;
1464
1465 mutex_lock(&priv->reg_mutex);
1466
1467 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1468 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1469 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1470 & PORT_MAP_MASK;
1471
1472 port_mask &= ~BIT(port);
1473 mt7530_fdb_write(priv, vid, port_mask, addr, -1,
1474 port_mask ? STATIC_ENT : STATIC_EMP);
1475 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1476
1477 mutex_unlock(&priv->reg_mutex);
1478
1479 return ret;
1480}
1481
83163f7d
SW		 1482static int
1483mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1484{
1485 struct mt7530_dummy_poll p;
1486 u32 val;
1487 int ret;
1488
1489 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1490 mt7530_write(priv, MT7530_VTCR, val);
1491
1492 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1493 ret = readx_poll_timeout(_mt7530_read, &p, val,
1494 !(val & VTCR_BUSY), 20, 20000);
1495 if (ret < 0) {
1496 dev_err(priv->dev, "poll timeout\n");
1497 return ret;
1498 }
1499
1500 val = mt7530_read(priv, MT7530_VTCR);
1501 if (val & VTCR_INVALID) {
1502 dev_err(priv->dev, "read VTCR invalid\n");
1503 return -EINVAL;
1504 }
1505
1506 return 0;
1507}
1508
1509static int
89153ed6
VO		 1510mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1511 struct netlink_ext_ack *extack)
83163f7d 1512{
1f9a6abe
FW		 1513 struct dsa_port *dp = dsa_to_port(ds, port);
1514 struct dsa_port *cpu_dp = dp->cpu_dp;
1515
83163f7d
SW		 1516 if (vlan_filtering) {
1517 /* The port is being kept as VLAN-unaware port when bridge is
1518 * set up with vlan_filtering not being set, Otherwise, the
1519 * port and the corresponding CPU port is required the setup
1520 * for becoming a VLAN-aware port.
1521 */
1522 mt7530_port_set_vlan_aware(ds, port);
1f9a6abe 1523 mt7530_port_set_vlan_aware(ds, cpu_dp->index);
e3ee07d1
VO		 1524 } else {
1525 mt7530_port_set_vlan_unaware(ds, port);
83163f7d
SW		 1526 }
1527
1528 return 0;
1529}
1530
83163f7d
SW		 1531static void
1532mt7530_hw_vlan_add(struct mt7530_priv *priv,
1533 struct mt7530_hw_vlan_entry *entry)
1534{
a9c31741 1535 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
83163f7d
SW		 1536 u8 new_members;
1537 u32 val;
1538
a9c31741 1539 new_members = entry->old_members | BIT(entry->port);
83163f7d
SW		 1540
1541 /* Validate the entry with independent learning, create egress tag per
1542 * VLAN and joining the port as one of the port members.
1543 */
6087175b
DQ		 1544 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
1545 VLAN_VALID;
83163f7d
SW		 1546 mt7530_write(priv, MT7530_VAWD1, val);
1547
1548 /* Decide whether adding tag or not for those outgoing packets from the
1549 * port inside the VLAN.
a9c31741 1550 * CPU port is always taken as a tagged port for serving more than one
83163f7d
SW		 1551 * VLANs across and also being applied with egress type stack mode for
1552 * that VLAN tags would be appended after hardware special tag used as
1553 * DSA tag.
1554 */
a9c31741
FW		 1555 if (dsa_port_is_cpu(dp))
1556 val = MT7530_VLAN_EGRESS_STACK;
1557 else if (entry->untagged)
1558 val = MT7530_VLAN_EGRESS_UNTAG;
1559 else
1560 val = MT7530_VLAN_EGRESS_TAG;
83163f7d 1561 mt7530_rmw(priv, MT7530_VAWD2,
a9c31741
FW		 1562 ETAG_CTRL_P_MASK(entry->port),
1563 ETAG_CTRL_P(entry->port, val));
83163f7d
SW		 1564}
1565
1566static void
1567mt7530_hw_vlan_del(struct mt7530_priv *priv,
1568 struct mt7530_hw_vlan_entry *entry)
1569{
1570 u8 new_members;
1571 u32 val;
1572
1573 new_members = entry->old_members & ~BIT(entry->port);
1574
1575 val = mt7530_read(priv, MT7530_VAWD1);
1576 if (!(val & VLAN_VALID)) {
1577 dev_err(priv->dev,
1578 "Cannot be deleted due to invalid entry\n");
1579 return;
1580 }
1581
a9c31741 1582 if (new_members) {
83163f7d
SW		 1583 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1584 VLAN_VALID;
1585 mt7530_write(priv, MT7530_VAWD1, val);
1586 } else {
1587 mt7530_write(priv, MT7530_VAWD1, 0);
1588 mt7530_write(priv, MT7530_VAWD2, 0);
1589 }
1590}
1591
1592static void
1593mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1594 struct mt7530_hw_vlan_entry *entry,
1595 mt7530_vlan_op vlan_op)
1596{
1597 u32 val;
1598
1599 /* Fetch entry */
1600 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1601
1602 val = mt7530_read(priv, MT7530_VAWD1);
1603
1604 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1605
1606 /* Manipulate entry */
1607 vlan_op(priv, entry);
1608
1609 /* Flush result to hardware */
1610 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1611}
1612
1ca8a193
DQ		 1613static int
1614mt7530_setup_vlan0(struct mt7530_priv *priv)
1615{
1616 u32 val;
1617
1618 /* Validate the entry with independent learning, keep the original
1619 * ingress tag attribute.
1620 */
1621 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
1622 VLAN_VALID;
1623 mt7530_write(priv, MT7530_VAWD1, val);
1624
1625 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
1626}
1627
1958d581 1628static int
83163f7d 1629mt7530_port_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 1630 const struct switchdev_obj_port_vlan *vlan,
1631 struct netlink_ext_ack *extack)
83163f7d
SW		 1632{
1633 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1634 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1635 struct mt7530_hw_vlan_entry new_entry;
1636 struct mt7530_priv *priv = ds->priv;
83163f7d 1637
83163f7d
SW		 1638 mutex_lock(&priv->reg_mutex);
1639
b7a9e0da
VO		 1640 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1641 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
83163f7d
SW		 1642
1643 if (pvid) {
b7a9e0da 1644 priv->ports[port].pvid = vlan->vid;
6087175b 1645
8fbebef8
DQ		 1646 /* Accept all frames if PVID is set */
1647 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1648 MT7530_VLAN_ACC_ALL);
1649
6087175b
DQ		 1650 /* Only configure PVID if VLAN filtering is enabled */
1651 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1652 mt7530_rmw(priv, MT7530_PPBV1_P(port),
1653 G0_PORT_VID_MASK,
1654 G0_PORT_VID(vlan->vid));
8fbebef8
DQ		 1655 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
1656 /* This VLAN is overwritten without PVID, so unset it */
1657 priv->ports[port].pvid = G0_PORT_VID_DEF;
1658
1659 /* Only accept tagged frames if the port is VLAN-aware */
1660 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1661 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1662 MT7530_VLAN_ACC_TAGGED);
1663
1664 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1665 G0_PORT_VID_DEF);
83163f7d
SW		 1666 }
1667
1668 mutex_unlock(&priv->reg_mutex);
1958d581
VO		 1669
1670 return 0;
83163f7d
SW		 1671}
1672
1673static int
1674mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1675 const struct switchdev_obj_port_vlan *vlan)
1676{
1677 struct mt7530_hw_vlan_entry target_entry;
1678 struct mt7530_priv *priv = ds->priv;
83163f7d 1679
83163f7d
SW		 1680 mutex_lock(&priv->reg_mutex);
1681
b7a9e0da
VO		 1682 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1683 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1684 mt7530_hw_vlan_del);
83163f7d 1685
b7a9e0da
VO		 1686 /* PVID is being restored to the default whenever the PVID port
1687 * is being removed from the VLAN.
1688 */
6087175b
DQ		 1689 if (priv->ports[port].pvid == vlan->vid) {
1690 priv->ports[port].pvid = G0_PORT_VID_DEF;
8fbebef8
DQ		 1691
1692 /* Only accept tagged frames if the port is VLAN-aware */
1693 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1694 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1695 MT7530_VLAN_ACC_TAGGED);
1696
6087175b
DQ		 1697 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1698 G0_PORT_VID_DEF);
1699 }
83163f7d 1700
83163f7d
SW		 1701
1702 mutex_unlock(&priv->reg_mutex);
1703
1704 return 0;
1705}
1706
c288575f
LC		 1707static int mt753x_mirror_port_get(unsigned int id, u32 val)
1708{
1709 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1710 MIRROR_PORT(val);
1711}
1712
1713static int mt753x_mirror_port_set(unsigned int id, u32 val)
1714{
1715 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1716 MIRROR_PORT(val);
1717}
1718
1719static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
37feab60 1720 struct dsa_mall_mirror_tc_entry *mirror,
0148bb50 1721 bool ingress, struct netlink_ext_ack *extack)
37feab60
DQ		 1722{
1723 struct mt7530_priv *priv = ds->priv;
c288575f 1724 int monitor_port;
37feab60
DQ		 1725 u32 val;
1726
1727 /* Check for existent entry */
1728 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1729 return -EEXIST;
1730
c288575f 1731 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
37feab60
DQ		 1732
1733 /* MT7530 only supports one monitor port */
c288575f
LC		 1734 monitor_port = mt753x_mirror_port_get(priv->id, val);
1735 if (val & MT753X_MIRROR_EN(priv->id) &&
1736 monitor_port != mirror->to_local_port)
37feab60
DQ		 1737 return -EEXIST;
1738
c288575f
LC		 1739 val |= MT753X_MIRROR_EN(priv->id);
1740 val &= ~MT753X_MIRROR_MASK(priv->id);
1741 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1742 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1743
1744 val = mt7530_read(priv, MT7530_PCR_P(port));
1745 if (ingress) {
1746 val |= PORT_RX_MIR;
1747 priv->mirror_rx |= BIT(port);
1748 } else {
1749 val |= PORT_TX_MIR;
1750 priv->mirror_tx |= BIT(port);
1751 }
1752 mt7530_write(priv, MT7530_PCR_P(port), val);
1753
1754 return 0;
1755}
1756
c288575f 1757static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
37feab60
DQ		 1758 struct dsa_mall_mirror_tc_entry *mirror)
1759{
1760 struct mt7530_priv *priv = ds->priv;
1761 u32 val;
1762
1763 val = mt7530_read(priv, MT7530_PCR_P(port));
1764 if (mirror->ingress) {
1765 val &= ~PORT_RX_MIR;
1766 priv->mirror_rx &= ~BIT(port);
1767 } else {
1768 val &= ~PORT_TX_MIR;
1769 priv->mirror_tx &= ~BIT(port);
1770 }
1771 mt7530_write(priv, MT7530_PCR_P(port), val);
1772
1773 if (!priv->mirror_rx && !priv->mirror_tx) {
c288575f
LC		 1774 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1775 val &= ~MT753X_MIRROR_EN(priv->id);
1776 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1777 }
1778}
1779
b8f126a8 1780static enum dsa_tag_protocol
4d776482
FF		 1781mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1782 enum dsa_tag_protocol mp)
b8f126a8 1783{
244f8a80 1784 return DSA_TAG_PROTO_MTK;
b8f126a8
SW		 1785}
1786
63c75c05 1787#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 1788static inline u32
1789mt7530_gpio_to_bit(unsigned int offset)
1790{
1791 /* Map GPIO offset to register bit
1792 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2
1793 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5
1794 * [10: 8] port 2 LED 0..2 as GPIO 6..8
1795 * [14:12] port 3 LED 0..2 as GPIO 9..11
1796 * [18:16] port 4 LED 0..2 as GPIO 12..14
1797 */
1798 return BIT(offset + offset / 3);
1799}
1800
1801static int
1802mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1803{
1804 struct mt7530_priv *priv = gpiochip_get_data(gc);
1805 u32 bit = mt7530_gpio_to_bit(offset);
1806
1807 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1808}
1809
1810static void
1811mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1812{
1813 struct mt7530_priv *priv = gpiochip_get_data(gc);
1814 u32 bit = mt7530_gpio_to_bit(offset);
1815
1816 if (value)
1817 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1818 else
1819 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1820}
1821
1822static int
1823mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1824{
1825 struct mt7530_priv *priv = gpiochip_get_data(gc);
1826 u32 bit = mt7530_gpio_to_bit(offset);
1827
1828 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1829 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1830}
1831
1832static int
1833mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1834{
1835 struct mt7530_priv *priv = gpiochip_get_data(gc);
1836 u32 bit = mt7530_gpio_to_bit(offset);
1837
1838 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1839 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1840
1841 return 0;
1842}
1843
1844static int
1845mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1846{
1847 struct mt7530_priv *priv = gpiochip_get_data(gc);
1848 u32 bit = mt7530_gpio_to_bit(offset);
1849
1850 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1851
1852 if (value)
1853 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1854 else
1855 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1856
1857 mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1858
1859 return 0;
1860}
1861
1862static int
1863mt7530_setup_gpio(struct mt7530_priv *priv)
1864{
1865 struct device *dev = priv->dev;
1866 struct gpio_chip *gc;
1867
1868 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1869 if (!gc)
1870 return -ENOMEM;
1871
1872 mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1873 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1874 mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1875
1876 gc->label = "mt7530";
1877 gc->parent = dev;
1878 gc->owner = THIS_MODULE;
1879 gc->get_direction = mt7530_gpio_get_direction;
1880 gc->direction_input = mt7530_gpio_direction_input;
1881 gc->direction_output = mt7530_gpio_direction_output;
1882 gc->get = mt7530_gpio_get;
1883 gc->set = mt7530_gpio_set;
1884 gc->base = -1;
1885 gc->ngpio = 15;
1886 gc->can_sleep = true;
1887
1888 return devm_gpiochip_add_data(dev, gc, priv);
1889}
63c75c05 1890#endif /* CONFIG_GPIOLIB */
429a0ede 1891
ba751e28
DQ		 1892static irqreturn_t
1893mt7530_irq_thread_fn(int irq, void *dev_id)
1894{
1895 struct mt7530_priv *priv = dev_id;
1896 bool handled = false;
1897 u32 val;
1898 int p;
1899
1557c679 1900 mt7530_mutex_lock(priv);
ba751e28
DQ		 1901 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
1902 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
1557c679 1903 mt7530_mutex_unlock(priv);
ba751e28
DQ		 1904
1905 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1906 if (BIT(p) & val) {
1907 unsigned int irq;
1908
1909 irq = irq_find_mapping(priv->irq_domain, p);
1910 handle_nested_irq(irq);
1911 handled = true;
1912 }
1913 }
1914
1915 return IRQ_RETVAL(handled);
1916}
1917
1918static void
1919mt7530_irq_mask(struct irq_data *d)
1920{
1921 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1922
1923 priv->irq_enable &= ~BIT(d->hwirq);
1924}
1925
1926static void
1927mt7530_irq_unmask(struct irq_data *d)
1928{
1929 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1930
1931 priv->irq_enable |= BIT(d->hwirq);
1932}
1933
1934static void
1935mt7530_irq_bus_lock(struct irq_data *d)
1936{
1937 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1938
1557c679 1939 mt7530_mutex_lock(priv);
ba751e28
DQ		 1940}
1941
1942static void
1943mt7530_irq_bus_sync_unlock(struct irq_data *d)
1944{
1945 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1946
1947 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1557c679 1948 mt7530_mutex_unlock(priv);
ba751e28
DQ		 1949}
1950
1951static struct irq_chip mt7530_irq_chip = {
1952 .name = KBUILD_MODNAME,
1953 .irq_mask = mt7530_irq_mask,
1954 .irq_unmask = mt7530_irq_unmask,
1955 .irq_bus_lock = mt7530_irq_bus_lock,
1956 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock,
1957};
1958
1959static int
1960mt7530_irq_map(struct irq_domain *domain, unsigned int irq,
1961 irq_hw_number_t hwirq)
1962{
1963 irq_set_chip_data(irq, domain->host_data);
1964 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq);
1965 irq_set_nested_thread(irq, true);
1966 irq_set_noprobe(irq);
1967
1968 return 0;
1969}
1970
1971static const struct irq_domain_ops mt7530_irq_domain_ops = {
1972 .map = mt7530_irq_map,
1973 .xlate = irq_domain_xlate_onecell,
1974};
1975
110c18bf
DG		 1976static void
1977mt7988_irq_mask(struct irq_data *d)
1978{
1979 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1980
1981 priv->irq_enable &= ~BIT(d->hwirq);
1982 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1983}
1984
1985static void
1986mt7988_irq_unmask(struct irq_data *d)
1987{
1988 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1989
1990 priv->irq_enable |= BIT(d->hwirq);
1991 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1992}
1993
1994static struct irq_chip mt7988_irq_chip = {
1995 .name = KBUILD_MODNAME,
1996 .irq_mask = mt7988_irq_mask,
1997 .irq_unmask = mt7988_irq_unmask,
1998};
1999
2000static int
2001mt7988_irq_map(struct irq_domain *domain, unsigned int irq,
2002 irq_hw_number_t hwirq)
2003{
2004 irq_set_chip_data(irq, domain->host_data);
2005 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq);
2006 irq_set_nested_thread(irq, true);
2007 irq_set_noprobe(irq);
2008
2009 return 0;
2010}
2011
2012static const struct irq_domain_ops mt7988_irq_domain_ops = {
2013 .map = mt7988_irq_map,
2014 .xlate = irq_domain_xlate_onecell,
2015};
2016
ba751e28
DQ		 2017static void
2018mt7530_setup_mdio_irq(struct mt7530_priv *priv)
2019{
2020 struct dsa_switch *ds = priv->ds;
2021 int p;
2022
2023 for (p = 0; p < MT7530_NUM_PHYS; p++) {
2024 if (BIT(p) & ds->phys_mii_mask) {
2025 unsigned int irq;
2026
2027 irq = irq_create_mapping(priv->irq_domain, p);
6ca80638 2028 ds->user_mii_bus->irq[p] = irq;
ba751e28
DQ		 2029 }
2030 }
2031}
2032
2033static int
2034mt7530_setup_irq(struct mt7530_priv *priv)
2035{
2036 struct device *dev = priv->dev;
2037 struct device_node *np = dev->of_node;
2038 int ret;
2039
2040 if (!of_property_read_bool(np, "interrupt-controller")) {
2041 dev_info(dev, "no interrupt support\n");
2042 return 0;
2043 }
2044
2045 priv->irq = of_irq_get(np, 0);
2046 if (priv->irq <= 0) {
2047 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq);
2048 return priv->irq ? : -EINVAL;
2049 }
2050
110c18bf
DG		 2051 if (priv->id == ID_MT7988)
2052 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
2053 &mt7988_irq_domain_ops,
2054 priv);
2055 else
2056 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
2057 &mt7530_irq_domain_ops,
2058 priv);
2059
ba751e28
DQ		 2060 if (!priv->irq_domain) {
2061 dev_err(dev, "failed to create IRQ domain\n");
2062 return -ENOMEM;
2063 }
2064
2065 /* This register must be set for MT7530 to properly fire interrupts */
2066 if (priv->id != ID_MT7531)
2067 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
2068
2069 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
2070 IRQF_ONESHOT, KBUILD_MODNAME, priv);
2071 if (ret) {
2072 irq_domain_remove(priv->irq_domain);
2073 dev_err(dev, "failed to request IRQ: %d\n", ret);
2074 return ret;
2075 }
2076
2077 return 0;
2078}
2079
2080static void
2081mt7530_free_mdio_irq(struct mt7530_priv *priv)
2082{
2083 int p;
2084
2085 for (p = 0; p < MT7530_NUM_PHYS; p++) {
2086 if (BIT(p) & priv->ds->phys_mii_mask) {
2087 unsigned int irq;
2088
2089 irq = irq_find_mapping(priv->irq_domain, p);
2090 irq_dispose_mapping(irq);
2091 }
2092 }
2093}
2094
2095static void
2096mt7530_free_irq_common(struct mt7530_priv *priv)
2097{
2098 free_irq(priv->irq, priv);
2099 irq_domain_remove(priv->irq_domain);
2100}
2101
2102static void
2103mt7530_free_irq(struct mt7530_priv *priv)
2104{
91374ba5
AÜ		 2105 struct device_node *mnp, *np = priv->dev->of_node;
2106
2107 mnp = of_get_child_by_name(np, "mdio");
2108 if (!mnp)
2109 mt7530_free_mdio_irq(priv);
2110 of_node_put(mnp);
2111
ba751e28
DQ		 2112 mt7530_free_irq_common(priv);
2113}
2114
2115static int
2116mt7530_setup_mdio(struct mt7530_priv *priv)
2117{
91374ba5 2118 struct device_node *mnp, *np = priv->dev->of_node;
ba751e28
DQ		 2119 struct dsa_switch *ds = priv->ds;
2120 struct device *dev = priv->dev;
2121 struct mii_bus *bus;
2122 static int idx;
91374ba5
AÜ		 2123 int ret = 0;
2124
2125 mnp = of_get_child_by_name(np, "mdio");
2126
2127 if (mnp && !of_device_is_available(mnp))
2128 goto out;
ba751e28
DQ		 2129
2130 bus = devm_mdiobus_alloc(dev);
91374ba5
AÜ		 2131 if (!bus) {
2132 ret = -ENOMEM;
2133 goto out;
2134 }
2135
2136 if (!mnp)
2137 ds->user_mii_bus = bus;
ba751e28 2138
ba751e28
DQ		 2139 bus->priv = priv;
2140 bus->name = KBUILD_MODNAME "-mii";
2141 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
defa2e54
AL		 2142 bus->read = mt753x_phy_read_c22;
2143 bus->write = mt753x_phy_write_c22;
2144 bus->read_c45 = mt753x_phy_read_c45;
2145 bus->write_c45 = mt753x_phy_write_c45;
ba751e28
DQ		 2146 bus->parent = dev;
2147 bus->phy_mask = ~ds->phys_mii_mask;
2148
91374ba5 2149 if (priv->irq && !mnp)
ba751e28
DQ		 2150 mt7530_setup_mdio_irq(priv);
2151
91374ba5 2152 ret = devm_of_mdiobus_register(dev, bus, mnp);
ba751e28
DQ		 2153 if (ret) {
2154 dev_err(dev, "failed to register MDIO bus: %d\n", ret);
91374ba5 2155 if (priv->irq && !mnp)
ba751e28
DQ		 2156 mt7530_free_mdio_irq(priv);
2157 }
2158
91374ba5
AÜ		 2159out:
2160 of_node_put(mnp);
ba751e28
DQ		 2161 return ret;
2162}
2163
b8f126a8
SW		 2164static int
2165mt7530_setup(struct dsa_switch *ds)
2166{
2167 struct mt7530_priv *priv = ds->priv;
6e19bc26 2168 struct device_node *dn = NULL;
38f790a8
RD		 2169 struct device_node *phy_node;
2170 struct device_node *mac_np;
b8f126a8 2171 struct mt7530_dummy_poll p;
38f790a8 2172 phy_interface_t interface;
6e19bc26 2173 struct dsa_port *cpu_dp;
ca366d6c
RD		 2174 u32 id, val;
2175 int ret, i;
b8f126a8 2176
6ca80638 2177 /* The parent node of conduit netdev which holds the common system
b8f126a8
SW		 2178 * controller also is the container for two GMACs nodes representing
2179 * as two netdev instances.
2180 */
6e19bc26 2181 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6ca80638 2182 dn = cpu_dp->conduit->dev.of_node->parent;
6e19bc26 2183 /* It doesn't matter which CPU port is found first,
6ca80638 2184 * their conduits should share the same parent OF node
6e19bc26
FW		 2185 */
2186 break;
2187 }
2188
2189 if (!dn) {
6ca80638 2190 dev_err(ds->dev, "parent OF node of DSA conduit not found");
6e19bc26
FW		 2191 return -EINVAL;
2192 }
2193
0b69c54c 2194 ds->assisted_learning_on_cpu_port = true;
771c8901 2195 ds->mtu_enforcement_ingress = true;
b8f126a8 2196
ddda1ac1 2197 if (priv->id == ID_MT7530) {
ddda1ac1
GU		 2198 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
2199 ret = regulator_enable(priv->core_pwr);
2200 if (ret < 0) {
2201 dev_err(priv->dev,
2202 "Failed to enable core power: %d\n", ret);
2203 return ret;
2204 }
b8f126a8 2205
ddda1ac1
GU		 2206 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
2207 ret = regulator_enable(priv->io_pwr);
2208 if (ret < 0) {
2209 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
2210 ret);
2211 return ret;
2212 }
b8f126a8
SW		 2213 }
2214
2215 /* Reset whole chip through gpio pin or memory-mapped registers for
2216 * different type of hardware
2217 */
2218 if (priv->mcm) {
2219 reset_control_assert(priv->rstc);
2220 usleep_range(1000, 1100);
2221 reset_control_deassert(priv->rstc);
2222 } else {
2223 gpiod_set_value_cansleep(priv->reset, 0);
2224 usleep_range(1000, 1100);
2225 gpiod_set_value_cansleep(priv->reset, 1);
2226 }
2227
2228 /* Waiting for MT7530 got to stable */
2229 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2230 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2231 20, 1000000);
2232 if (ret < 0) {
2233 dev_err(priv->dev, "reset timeout\n");
2234 return ret;
2235 }
2236
2237 id = mt7530_read(priv, MT7530_CREV);
2238 id >>= CHIP_NAME_SHIFT;
2239 if (id != MT7530_ID) {
2240 dev_err(priv->dev, "chip %x can't be supported\n", id);
2241 return -ENODEV;
2242 }
2243
fd792909
AÜ		 2244 if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
2245 dev_err(priv->dev,
2246 "MT7530 with a 20MHz XTAL is not supported!\n");
2247 return -EINVAL;
2248 }
2249
b8f126a8
SW		 2250 /* Reset the switch through internal reset */
2251 mt7530_write(priv, MT7530_SYS_CTRL,
2252 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2253 SYS_CTRL_REG_RST);
2254
c8b8a3c6
VO		 2255 mt7530_pll_setup(priv);
2256
fdcc8ccd
AÜ		 2257 /* Lower Tx driving for TRGMII path */
2258 for (i = 0; i < NUM_TRGMII_CTRL; i++)
2259 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
2260 TD_DM_DRVP(8) | TD_DM_DRVN(8));
2261
2262 for (i = 0; i < NUM_TRGMII_CTRL; i++)
2263 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
2264 RD_TAP_MASK, RD_TAP(16));
2265
feb03fd1 2266 /* Enable port 6 */
b8f126a8
SW		 2267 val = mt7530_read(priv, MT7530_MHWTRAP);
2268 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
2269 val |= MHWTRAP_MANUAL;
2270 mt7530_write(priv, MT7530_MHWTRAP, val);
2271
ca366d6c
RD		 2272 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2273
d7c66073
AÜ		 2274 mt753x_trap_frames(priv);
2275
b8f126a8
SW		 2276 /* Enable and reset MIB counters */
2277 mt7530_mib_reset(ds);
2278
b8f126a8
SW		 2279 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2280 /* Disable forwarding by default on all ports */
2281 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2282 PCR_MATRIX_CLR);
2283
0b69c54c
DQ		 2284 /* Disable learning by default on all ports */
2285 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2286
0ce0c3cd
AD		 2287 if (dsa_is_cpu_port(ds, i)) {
2288 ret = mt753x_cpu_port_enable(ds, i);
2289 if (ret)
2290 return ret;
5a30833b 2291 } else {
75104db0 2292 mt7530_port_disable(ds, i);
6087175b
DQ		 2293
2294 /* Set default PVID to 0 on all user ports */
2295 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2296 G0_PORT_VID_DEF);
5a30833b 2297 }
e045124e
DQ		 2298 /* Enable consistent egress tag */
2299 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2300 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
b8f126a8
SW		 2301 }
2302
1ca8a193
DQ		 2303 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2304 ret = mt7530_setup_vlan0(priv);
2305 if (ret)
2306 return ret;
2307
38f790a8 2308 /* Setup port 5 */
38f790a8
RD		 2309 if (!dsa_is_unused_port(ds, 5)) {
2310 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
38f790a8 2311 } else {
152f8e8e
AÜ		 2312 /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
2313 * Set priv->p5_intf_sel to the appropriate value if PHY muxing
2314 * is detected.
2315 */
38f790a8
RD		 2316 for_each_child_of_node(dn, mac_np) {
2317 if (!of_device_is_compatible(mac_np,
2318 "mediatek,eth-mac"))
2319 continue;
2320
2321 ret = of_property_read_u32(mac_np, "reg", &id);
2322 if (ret < 0 || id != 1)
2323 continue;
2324
2325 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
0452800f
CG		 2326 if (!phy_node)
2327 continue;
2328
38f790a8 2329 if (phy_node->parent == priv->dev->of_node->parent) {
0c65b2b9 2330 ret = of_get_phy_mode(mac_np, &interface);
8e4efd47
SP		 2331 if (ret && ret != -ENODEV) {
2332 of_node_put(mac_np);
a9e9b091 2333 of_node_put(phy_node);
0c65b2b9 2334 return ret;
8e4efd47 2335 }
38f790a8
RD		 2336 id = of_mdio_parse_addr(ds->dev, phy_node);
2337 if (id == 0)
2338 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
2339 if (id == 4)
2340 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
2341 }
8e4efd47 2342 of_node_put(mac_np);
38f790a8
RD		 2343 of_node_put(phy_node);
2344 break;
2345 }
152f8e8e 2346
04a22bef
AÜ		 2347 if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
2348 priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
2349 mt7530_setup_port5(ds, interface);
38f790a8
RD		 2350 }
2351
63c75c05 2352#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 2353 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
2354 ret = mt7530_setup_gpio(priv);
2355 if (ret)
2356 return ret;
2357 }
63c75c05 2358#endif /* CONFIG_GPIOLIB */
429a0ede 2359
b8f126a8 2360 /* Flush the FDB table */
18bd5949 2361 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 2362 if (ret < 0)
2363 return ret;
2364
2365 return 0;
2366}
2367
7f54cc97
DG		 2368static int
2369mt7531_setup_common(struct dsa_switch *ds)
2370{
2371 struct mt7530_priv *priv = ds->priv;
7f54cc97
DG		 2372 int ret, i;
2373
d7c66073 2374 mt753x_trap_frames(priv);
7f54cc97
DG		 2375
2376 /* Enable and reset MIB counters */
2377 mt7530_mib_reset(ds);
2378
120a56b0
AÜ		 2379 /* Disable flooding on all ports */
2380 mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
2381 UNU_FFP_MASK);
2382
7f54cc97
DG		 2383 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2384 /* Disable forwarding by default on all ports */
2385 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2386 PCR_MATRIX_CLR);
2387
2388 /* Disable learning by default on all ports */
2389 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2390
2391 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
2392
2393 if (dsa_is_cpu_port(ds, i)) {
2394 ret = mt753x_cpu_port_enable(ds, i);
2395 if (ret)
2396 return ret;
2397 } else {
2398 mt7530_port_disable(ds, i);
2399
2400 /* Set default PVID to 0 on all user ports */
2401 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2402 G0_PORT_VID_DEF);
2403 }
2404
2405 /* Enable consistent egress tag */
2406 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2407 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2408 }
2409
2410 /* Flush the FDB table */
2411 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2412 if (ret < 0)
2413 return ret;
2414
2415 return 0;
2416}
2417
c288575f
LC		 2418static int
2419mt7531_setup(struct dsa_switch *ds)
2420{
2421 struct mt7530_priv *priv = ds->priv;
2422 struct mt7530_dummy_poll p;
2423 u32 val, id;
2424 int ret, i;
2425
2426 /* Reset whole chip through gpio pin or memory-mapped registers for
2427 * different type of hardware
2428 */
2429 if (priv->mcm) {
2430 reset_control_assert(priv->rstc);
2431 usleep_range(1000, 1100);
2432 reset_control_deassert(priv->rstc);
2433 } else {
2434 gpiod_set_value_cansleep(priv->reset, 0);
2435 usleep_range(1000, 1100);
2436 gpiod_set_value_cansleep(priv->reset, 1);
2437 }
2438
2439 /* Waiting for MT7530 got to stable */
2440 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2441 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2442 20, 1000000);
2443 if (ret < 0) {
2444 dev_err(priv->dev, "reset timeout\n");
2445 return ret;
2446 }
2447
2448 id = mt7530_read(priv, MT7531_CREV);
2449 id >>= CHIP_NAME_SHIFT;
2450
2451 if (id != MT7531_ID) {
2452 dev_err(priv->dev, "chip %x can't be supported\n", id);
2453 return -ENODEV;
2454 }
2455
1f4a85f2
AÜ		 2456 /* MT7531AE has got two SGMII units. One for port 5, one for port 6.
2457 * MT7531BE has got only one SGMII unit which is for port 6.
2458 */
2459 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
2460 priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
2461
728c2af6
AC		 2462 /* all MACs must be forced link-down before sw reset */
2463 for (i = 0; i < MT7530_NUM_PORTS; i++)
2464 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
2465
c288575f
LC		 2466 /* Reset the switch through internal reset */
2467 mt7530_write(priv, MT7530_SYS_CTRL,
2468 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2469 SYS_CTRL_REG_RST);
2470
1f4a85f2
AÜ		 2471 if (!priv->p5_sgmii) {
2472 mt7531_pll_setup(priv);
2473 } else {
6ca80638 2474 /* Let ds->user_mii_bus be able to access external phy. */
c288575f
LC		 2475 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
2476 MT7531_EXT_P_MDC_11);
2477 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
2478 MT7531_EXT_P_MDIO_12);
c288575f 2479 }
1f4a85f2
AÜ		 2480
2481 if (!dsa_is_unused_port(ds, 5))
2482 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
c288575f
LC		 2483
2484 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
2485 MT7531_GPIO0_INTERRUPT);
2486
2487 /* Let phylink decide the interface later. */
2488 priv->p5_interface = PHY_INTERFACE_MODE_NA;
2489 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2490
2491 /* Enable PHY core PLL, since phy_device has not yet been created
2492 * provided for phy_[read,write]_mmd_indirect is called, we provide
2493 * our own mt7531_ind_mmd_phy_[read,write] to complete this
2494 * function.
2495 */
2496 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
2497 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2498 val |= MT7531_PHY_PLL_BYPASS_MODE;
2499 val &= ~MT7531_PHY_PLL_OFF;
2500 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
2501 CORE_PLL_GROUP4, val);
2502
7f54cc97 2503 mt7531_setup_common(ds);
c288575f 2504
1ca8a193
DQ		 2505 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2506 ret = mt7530_setup_vlan0(priv);
2507 if (ret)
2508 return ret;
2509
0b69c54c 2510 ds->assisted_learning_on_cpu_port = true;
771c8901 2511 ds->mtu_enforcement_ingress = true;
c288575f 2512
c288575f
LC		 2513 return 0;
2514}
2515
59c2215f
RKO		 2516static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
2517 struct phylink_config *config)
2518{
2519 switch (port) {
05957aa7
AÜ		 2520 /* Ports which are connected to switch PHYs. There is no MII pinout. */
2521 case 0 ... 4:
59c2215f
RKO		 2522 __set_bit(PHY_INTERFACE_MODE_GMII,
2523 config->supported_interfaces);
2524 break;
2525
05957aa7
AÜ		 2526 /* Port 5 supports rgmii with delays, mii, and gmii. */
2527 case 5:
59c2215f
RKO		 2528 phy_interface_set_rgmii(config->supported_interfaces);
2529 __set_bit(PHY_INTERFACE_MODE_MII,
2530 config->supported_interfaces);
2531 __set_bit(PHY_INTERFACE_MODE_GMII,
2532 config->supported_interfaces);
2533 break;
2534
05957aa7
AÜ		 2535 /* Port 6 supports rgmii and trgmii. */
2536 case 6:
59c2215f
RKO		 2537 __set_bit(PHY_INTERFACE_MODE_RGMII,
2538 config->supported_interfaces);
2539 __set_bit(PHY_INTERFACE_MODE_TRGMII,
2540 config->supported_interfaces);
2541 break;
2542 }
2543}
2544
59c2215f
RKO		 2545static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
2546 struct phylink_config *config)
2547{
2548 struct mt7530_priv *priv = ds->priv;
2549
2550 switch (port) {
05957aa7
AÜ		 2551 /* Ports which are connected to switch PHYs. There is no MII pinout. */
2552 case 0 ... 4:
59c2215f
RKO		 2553 __set_bit(PHY_INTERFACE_MODE_GMII,
2554 config->supported_interfaces);
2555 break;
2556
05957aa7
AÜ		 2557 /* Port 5 supports rgmii with delays on MT7531BE, sgmii/802.3z on
2558 * MT7531AE.
2559 */
2560 case 5:
1f4a85f2 2561 if (!priv->p5_sgmii) {
59c2215f
RKO		 2562 phy_interface_set_rgmii(config->supported_interfaces);
2563 break;
2564 }
2565 fallthrough;
2566
05957aa7
AÜ		 2567 /* Port 6 supports sgmii/802.3z. */
2568 case 6:
59c2215f
RKO		 2569 __set_bit(PHY_INTERFACE_MODE_SGMII,
2570 config->supported_interfaces);
2571 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
2572 config->supported_interfaces);
2573 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
2574 config->supported_interfaces);
2575
2576 config->mac_capabilities |= MAC_2500FD;
2577 break;
2578 }
2579}
2580
110c18bf
DG		 2581static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
2582 struct phylink_config *config)
2583{
2584 phy_interface_zero(config->supported_interfaces);
2585
2586 switch (port) {
05957aa7
AÜ		 2587 /* Ports which are connected to switch PHYs. There is no MII pinout. */
2588 case 0 ... 4:
110c18bf
DG		 2589 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
2590 config->supported_interfaces);
2591 break;
2592
05957aa7 2593 /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
110c18bf
DG		 2594 case 6:
2595 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
2596 config->supported_interfaces);
2597 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
2598 MAC_10000FD;
2599 }
2600}
2601
88bdef8b
LC		 2602static int
2603mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2604{
2605 struct mt7530_priv *priv = ds->priv;
2606
2607 return priv->info->pad_setup(ds, state->interface);
2608}
2609
2610static int
2611mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2612 phy_interface_t interface)
2613{
2614 struct mt7530_priv *priv = ds->priv;
2615
2616 /* Only need to setup port5. */
2617 if (port != 5)
2618 return 0;
2619
2620 mt7530_setup_port5(priv->ds, interface);
2621
2622 return 0;
2623}
2624
c288575f
LC		 2625static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2626 phy_interface_t interface,
2627 struct phy_device *phydev)
2628{
2629 u32 val;
2630
1f4a85f2 2631 if (priv->p5_sgmii) {
c288575f
LC		 2632 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2633 port);
2634 return -EINVAL;
2635 }
2636
2637 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2638 val |= GP_CLK_EN;
2639 val &= ~GP_MODE_MASK;
2640 val |= GP_MODE(MT7531_GP_MODE_RGMII);
2641 val &= ~CLK_SKEW_IN_MASK;
2642 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2643 val &= ~CLK_SKEW_OUT_MASK;
2644 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2645 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2646
2647 /* Do not adjust rgmii delay when vendor phy driver presents. */
2648 if (!phydev || phy_driver_is_genphy(phydev)) {
2649 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2650 switch (interface) {
2651 case PHY_INTERFACE_MODE_RGMII:
2652 val |= TXCLK_NO_REVERSE;
2653 val |= RXCLK_NO_DELAY;
2654 break;
2655 case PHY_INTERFACE_MODE_RGMII_RXID:
2656 val |= TXCLK_NO_REVERSE;
2657 break;
2658 case PHY_INTERFACE_MODE_RGMII_TXID:
2659 val |= RXCLK_NO_DELAY;
2660 break;
2661 case PHY_INTERFACE_MODE_RGMII_ID:
2662 break;
2663 default:
2664 return -EINVAL;
2665 }
2666 }
2667 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2668
2669 return 0;
2670}
2671
c288575f
LC		 2672static bool mt753x_is_mac_port(u32 port)
2673{
2674 return (port == 5 || port == 6);
2675}
2676
110c18bf
DG		 2677static int
2678mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2679 phy_interface_t interface)
2680{
2681 if (dsa_is_cpu_port(ds, port) &&
2682 interface == PHY_INTERFACE_MODE_INTERNAL)
2683 return 0;
2684
2685 return -EINVAL;
2686}
2687
c288575f
LC		 2688static int
2689mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2690 phy_interface_t interface)
2691{
2692 struct mt7530_priv *priv = ds->priv;
2693 struct phy_device *phydev;
2694 struct dsa_port *dp;
2695
2696 if (!mt753x_is_mac_port(port)) {
2697 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2698 return -EINVAL;
2699 }
2700
2701 switch (interface) {
2702 case PHY_INTERFACE_MODE_RGMII:
2703 case PHY_INTERFACE_MODE_RGMII_ID:
2704 case PHY_INTERFACE_MODE_RGMII_RXID:
2705 case PHY_INTERFACE_MODE_RGMII_TXID:
2706 dp = dsa_to_port(ds, port);
6ca80638 2707 phydev = dp->user->phydev;
c288575f
LC		 2708 return mt7531_rgmii_setup(priv, port, interface, phydev);
2709 case PHY_INTERFACE_MODE_SGMII:
c288575f
LC		 2710 case PHY_INTERFACE_MODE_NA:
2711 case PHY_INTERFACE_MODE_1000BASEX:
2712 case PHY_INTERFACE_MODE_2500BASEX:
5b89aeae
DG		 2713 /* handled in SGMII PCS driver */
2714 return 0;
c288575f
LC		 2715 default:
2716 return -EINVAL;
2717 }
2718
2719 return -EINVAL;
2720}
2721
88bdef8b
LC		 2722static int
2723mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2724 const struct phylink_link_state *state)
2725{
2726 struct mt7530_priv *priv = ds->priv;
2727
2728 return priv->info->mac_port_config(ds, port, mode, state->interface);
2729}
2730
cbd1f243
RKO		 2731static struct phylink_pcs *
2732mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
2733 phy_interface_t interface)
2734{
2735 struct mt7530_priv *priv = ds->priv;
2736
2737 switch (interface) {
2738 case PHY_INTERFACE_MODE_TRGMII:
5b89aeae 2739 return &priv->pcs[port].pcs;
cbd1f243
RKO		 2740 case PHY_INTERFACE_MODE_SGMII:
2741 case PHY_INTERFACE_MODE_1000BASEX:
2742 case PHY_INTERFACE_MODE_2500BASEX:
5b89aeae 2743 return priv->ports[port].sgmii_pcs;
cbd1f243
RKO		 2744 default:
2745 return NULL;
2746 }
2747}
2748
88bdef8b
LC		 2749static void
2750mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2751 const struct phylink_link_state *state)
2752{
2753 struct mt7530_priv *priv = ds->priv;
2754 u32 mcr_cur, mcr_new;
2755
88bdef8b 2756 switch (port) {
05957aa7 2757 case 0 ... 4:
110c18bf
DG		 2758 if (state->interface != PHY_INTERFACE_MODE_GMII &&
2759 state->interface != PHY_INTERFACE_MODE_INTERNAL)
88bdef8b
LC		 2760 goto unsupported;
2761 break;
05957aa7 2762 case 5:
88bdef8b
LC		 2763 if (priv->p5_interface == state->interface)
2764 break;
2765
2766 if (mt753x_mac_config(ds, port, mode, state) < 0)
2767 goto unsupported;
38f790a8 2768
c288575f
LC		 2769 if (priv->p5_intf_sel != P5_DISABLED)
2770 priv->p5_interface = state->interface;
38f790a8 2771 break;
05957aa7 2772 case 6:
ca366d6c
RD		 2773 if (priv->p6_interface == state->interface)
2774 break;
2775
88bdef8b 2776 mt753x_pad_setup(ds, state);
ca366d6c 2777
88bdef8b
LC		 2778 if (mt753x_mac_config(ds, port, mode, state) < 0)
2779 goto unsupported;
ca366d6c 2780
ca366d6c
RD		 2781 priv->p6_interface = state->interface;
2782 break;
2783 default:
88bdef8b
LC		 2784unsupported:
2785 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2786 __func__, phy_modes(state->interface), port);
ca366d6c
RD		 2787 return;
2788 }
2789
ca366d6c
RD		 2790 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2791 mcr_new = mcr_cur;
1d01145f 2792 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
ca366d6c 2793 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
c288575f 2794 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
ca366d6c 2795
38f790a8
RD		 2796 /* Are we connected to external phy */
2797 if (port == 5 && dsa_is_user_port(ds, 5))
2798 mcr_new |= PMCR_EXT_PHY;
2799
ca366d6c
RD		 2800 if (mcr_new != mcr_cur)
2801 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2802}
2803
c288575f 2804static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
ca366d6c
RD		 2805 unsigned int mode,
2806 phy_interface_t interface)
2807{
2808 struct mt7530_priv *priv = ds->priv;
2809
1d01145f 2810 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
ca366d6c
RD		 2811}
2812
c288575f 2813static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
ca366d6c
RD		 2814 unsigned int mode,
2815 phy_interface_t interface,
5b502a7b
RK		 2816 struct phy_device *phydev,
2817 int speed, int duplex,
2818 bool tx_pause, bool rx_pause)
ca366d6c
RD		 2819{
2820 struct mt7530_priv *priv = ds->priv;
1d01145f
RD		 2821 u32 mcr;
2822
2823 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2824
c288575f
LC		 2825 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2826 * variants.
2827 */
dfa988b4 2828 if (interface == PHY_INTERFACE_MODE_TRGMII ||
c288575f
LC		 2829 (phy_interface_mode_is_8023z(interface))) {
2830 speed = SPEED_1000;
2831 duplex = DUPLEX_FULL;
2832 }
2833
1d01145f
RD		 2834 switch (speed) {
2835 case SPEED_1000:
2836 mcr |= PMCR_FORCE_SPEED_1000;
2837 break;
2838 case SPEED_100:
2839 mcr |= PMCR_FORCE_SPEED_100;
2840 break;
2841 }
2842 if (duplex == DUPLEX_FULL) {
2843 mcr |= PMCR_FORCE_FDX;
2844 if (tx_pause)
2845 mcr |= PMCR_TX_FC_EN;
2846 if (rx_pause)
2847 mcr |= PMCR_RX_FC_EN;
2848 }
ca366d6c 2849
53243d41 2850 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
40b5d2f1
RD		 2851 switch (speed) {
2852 case SPEED_1000:
2853 mcr |= PMCR_FORCE_EEE1G;
2854 break;
2855 case SPEED_100:
2856 mcr |= PMCR_FORCE_EEE100;
2857 break;
2858 }
2859 }
2860
1d01145f 2861 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
ca366d6c
RD		 2862}
2863
c288575f
LC		 2864static int
2865mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2866{
2867 struct mt7530_priv *priv = ds->priv;
2868 phy_interface_t interface;
2869 int speed;
0ce0c3cd 2870 int ret;
c288575f
LC		 2871
2872 switch (port) {
2873 case 5:
1f4a85f2 2874 if (!priv->p5_sgmii)
c288575f
LC		 2875 interface = PHY_INTERFACE_MODE_RGMII;
2876 else
2877 interface = PHY_INTERFACE_MODE_2500BASEX;
2878
2879 priv->p5_interface = interface;
2880 break;
2881 case 6:
2882 interface = PHY_INTERFACE_MODE_2500BASEX;
2883
c288575f
LC		 2884 priv->p6_interface = interface;
2885 break;
0ce0c3cd
AD		 2886 default:
2887 return -EINVAL;
c288575f
LC		 2888 }
2889
2890 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2891 speed = SPEED_2500;
2892 else
2893 speed = SPEED_1000;
2894
0ce0c3cd
AD		 2895 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2896 if (ret)
2897 return ret;
c288575f
LC		 2898 mt7530_write(priv, MT7530_PMCR_P(port),
2899 PMCR_CPU_PORT_SETTING(priv->id));
2900 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2901 speed, DUPLEX_FULL, true, true);
2902
2903 return 0;
2904}
2905
110c18bf
DG		 2906static int
2907mt7988_cpu_port_config(struct dsa_switch *ds, int port)
2908{
2909 struct mt7530_priv *priv = ds->priv;
2910
2911 mt7530_write(priv, MT7530_PMCR_P(port),
2912 PMCR_CPU_PORT_SETTING(priv->id));
2913
2914 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
2915 PHY_INTERFACE_MODE_INTERNAL, NULL,
2916 SPEED_10000, DUPLEX_FULL, true, true);
2917
2918 return 0;
2919}
2920
59c2215f
RKO		 2921static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
2922 struct phylink_config *config)
2923{
2924 struct mt7530_priv *priv = ds->priv;
2925
2926 /* This switch only supports full-duplex at 1Gbps */
2927 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
2928 MAC_10 | MAC_100 | MAC_1000FD;
2929
2930 priv->info->mac_port_get_caps(ds, port, config);
2931}
2932
9d0df207
RKO		 2933static int mt753x_pcs_validate(struct phylink_pcs *pcs,
2934 unsigned long *supported,
2935 const struct phylink_link_state *state)
ca366d6c 2936{
9d0df207
RKO		 2937 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */
2938 if (state->interface == PHY_INTERFACE_MODE_TRGMII ||
2939 phy_interface_mode_is_8023z(state->interface))
2940 phylink_clear(supported, Autoneg);
ca366d6c 2941
9d0df207 2942 return 0;
ca366d6c
RD		 2943}
2944
cbd1f243
RKO		 2945static void mt7530_pcs_get_state(struct phylink_pcs *pcs,
2946 struct phylink_link_state *state)
ca366d6c 2947{
cbd1f243
RKO		 2948 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
2949 int port = pcs_to_mt753x_pcs(pcs)->port;
ca366d6c
RD		 2950 u32 pmsr;
2951
ca366d6c
RD		 2952 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2953
2954 state->link = (pmsr & PMSR_LINK);
2955 state->an_complete = state->link;
2956 state->duplex = !!(pmsr & PMSR_DPX);
2957
2958 switch (pmsr & PMSR_SPEED_MASK) {
2959 case PMSR_SPEED_10:
2960 state->speed = SPEED_10;
2961 break;
2962 case PMSR_SPEED_100:
2963 state->speed = SPEED_100;
2964 break;
2965 case PMSR_SPEED_1000:
2966 state->speed = SPEED_1000;
2967 break;
2968 default:
2969 state->speed = SPEED_UNKNOWN;
2970 break;
2971 }
2972
2973 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2974 if (pmsr & PMSR_RX_FC)
2975 state->pause |= MLO_PAUSE_RX;
2976 if (pmsr & PMSR_TX_FC)
2977 state->pause |= MLO_PAUSE_TX;
ca366d6c
RD		 2978}
2979
6c1e4eca 2980static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
cbd1f243
RKO		 2981 phy_interface_t interface,
2982 const unsigned long *advertising,
2983 bool permit_pause_to_mac)
88bdef8b 2984{
cbd1f243
RKO		 2985 return 0;
2986}
88bdef8b 2987
cbd1f243
RKO		 2988static void mt7530_pcs_an_restart(struct phylink_pcs *pcs)
2989{
88bdef8b
LC		 2990}
2991
cbd1f243 2992static const struct phylink_pcs_ops mt7530_pcs_ops = {
9d0df207 2993 .pcs_validate = mt753x_pcs_validate,
cbd1f243
RKO		 2994 .pcs_get_state = mt7530_pcs_get_state,
2995 .pcs_config = mt753x_pcs_config,
2996 .pcs_an_restart = mt7530_pcs_an_restart,
2997};
2998
88bdef8b
LC		 2999static int
3000mt753x_setup(struct dsa_switch *ds)
3001{
3002 struct mt7530_priv *priv = ds->priv;
fae46308
RKO		 3003 int i, ret;
3004
3005 /* Initialise the PCS devices */
3006 for (i = 0; i < priv->ds->num_ports; i++) {
3007 priv->pcs[i].pcs.ops = priv->info->pcs_ops;
6c1e4eca 3008 priv->pcs[i].pcs.neg_mode = true;
fae46308
RKO		 3009 priv->pcs[i].priv = priv;
3010 priv->pcs[i].port = i;
3011 }
88bdef8b 3012
fae46308 3013 ret = priv->info->sw_setup(ds);
ba751e28
DQ		 3014 if (ret)
3015 return ret;
88bdef8b 3016
ba751e28
DQ		 3017 ret = mt7530_setup_irq(priv);
3018 if (ret)
3019 return ret;
88bdef8b 3020
ba751e28
DQ		 3021 ret = mt7530_setup_mdio(priv);
3022 if (ret && priv->irq)
3023 mt7530_free_irq_common(priv);
88bdef8b 3024
91daa4f6 3025 if (priv->create_sgmii) {
1f4a85f2 3026 ret = priv->create_sgmii(priv);
91daa4f6
DG		 3027 if (ret && priv->irq)
3028 mt7530_free_irq(priv);
3029 }
3030
ba751e28 3031 return ret;
88bdef8b
LC		 3032}
3033
40b5d2f1 3034static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,
d80a5233 3035 struct ethtool_keee *e)
40b5d2f1
RD		 3036{
3037 struct mt7530_priv *priv = ds->priv;
3038 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
3039
3040 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
3041 e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
3042
3043 return 0;
3044}
3045
3046static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
d80a5233 3047 struct ethtool_keee *e)
40b5d2f1
RD		 3048{
3049 struct mt7530_priv *priv = ds->priv;
3050 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;
3051
3052 if (e->tx_lpi_timer > 0xFFF)
3053 return -EINVAL;
3054
3055 set = SET_LPI_THRESH(e->tx_lpi_timer);
3056 if (!e->tx_lpi_enabled)
3057 /* Force LPI Mode without a delay */
3058 set |= LPI_MODE_EN;
3059 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
3060
3061 return 0;
3062}
3063
024d8577
AÜ		 3064static void
3065mt753x_conduit_state_change(struct dsa_switch *ds,
3066 const struct net_device *conduit,
3067 bool operational)
3068{
3069 struct dsa_port *cpu_dp = conduit->dsa_ptr;
3070 struct mt7530_priv *priv = ds->priv;
3071 int val = 0;
3072 u8 mask;
3073
3074 /* Set the CPU port to trap frames to for MT7530. Trapped frames will be
3075 * forwarded to the numerically smallest CPU port whose conduit
3076 * interface is up.
3077 */
3078 if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
3079 return;
3080
3081 mask = BIT(cpu_dp->index);
3082
3083 if (operational)
3084 priv->active_cpu_ports |= mask;
3085 else
3086 priv->active_cpu_ports &= ~mask;
3087
3088 if (priv->active_cpu_ports)
3089 val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
3090
3091 mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
3092}
3093
110c18bf
DG		 3094static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
3095{
3096 return 0;
3097}
3098
3099static int mt7988_setup(struct dsa_switch *ds)
3100{
3101 struct mt7530_priv *priv = ds->priv;
3102
3103 /* Reset the switch */
3104 reset_control_assert(priv->rstc);
3105 usleep_range(20, 50);
3106 reset_control_deassert(priv->rstc);
3107 usleep_range(20, 50);
3108
3109 /* Reset the switch PHYs */
3110 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
3111
3112 return mt7531_setup_common(ds);
3113}
3114
cb675afc 3115const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8 3116 .get_tag_protocol = mtk_get_tag_protocol,
88bdef8b 3117 .setup = mt753x_setup,
b79d7c14 3118 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port,
b8f126a8 3119 .get_strings = mt7530_get_strings,
b8f126a8
SW		 3120 .get_ethtool_stats = mt7530_get_ethtool_stats,
3121 .get_sset_count = mt7530_get_sset_count,
ea6d5c92 3122 .set_ageing_time = mt7530_set_ageing_time,
b8f126a8
SW		 3123 .port_enable = mt7530_port_enable,
3124 .port_disable = mt7530_port_disable,
9470174e
DQ		 3125 .port_change_mtu = mt7530_port_change_mtu,
3126 .port_max_mtu = mt7530_port_max_mtu,
b8f126a8 3127 .port_stp_state_set = mt7530_stp_state_set,
5a30833b
DQ		 3128 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags,
3129 .port_bridge_flags = mt7530_port_bridge_flags,
b8f126a8
SW		 3130 .port_bridge_join = mt7530_port_bridge_join,
3131 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 3132 .port_fdb_add = mt7530_port_fdb_add,
3133 .port_fdb_del = mt7530_port_fdb_del,
3134 .port_fdb_dump = mt7530_port_fdb_dump,
5a30833b
DQ		 3135 .port_mdb_add = mt7530_port_mdb_add,
3136 .port_mdb_del = mt7530_port_mdb_del,
83163f7d 3137 .port_vlan_filtering = mt7530_port_vlan_filtering,
83163f7d
SW		 3138 .port_vlan_add = mt7530_port_vlan_add,
3139 .port_vlan_del = mt7530_port_vlan_del,
c288575f
LC		 3140 .port_mirror_add = mt753x_port_mirror_add,
3141 .port_mirror_del = mt753x_port_mirror_del,
59c2215f 3142 .phylink_get_caps = mt753x_phylink_get_caps,
cbd1f243 3143 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs,
88bdef8b 3144 .phylink_mac_config = mt753x_phylink_mac_config,
c288575f
LC		 3145 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
3146 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
40b5d2f1
RD		 3147 .get_mac_eee = mt753x_get_mac_eee,
3148 .set_mac_eee = mt753x_set_mac_eee,
024d8577 3149 .conduit_state_change = mt753x_conduit_state_change,
b8f126a8 3150};
cb675afc 3151EXPORT_SYMBOL_GPL(mt7530_switch_ops);
b8f126a8 3152
cb675afc 3153const struct mt753x_info mt753x_table[] = {
88bdef8b
LC		 3154 [ID_MT7621] = {
3155 .id = ID_MT7621,
cbd1f243 3156 .pcs_ops = &mt7530_pcs_ops,
88bdef8b 3157 .sw_setup = mt7530_setup,
defa2e54
AL		 3158 .phy_read_c22 = mt7530_phy_read_c22,
3159 .phy_write_c22 = mt7530_phy_write_c22,
3160 .phy_read_c45 = mt7530_phy_read_c45,
3161 .phy_write_c45 = mt7530_phy_write_c45,
88bdef8b 3162 .pad_setup = mt7530_pad_clk_setup,
59c2215f 3163 .mac_port_get_caps = mt7530_mac_port_get_caps,
88bdef8b
LC		 3164 .mac_port_config = mt7530_mac_config,
3165 },
3166 [ID_MT7530] = {
3167 .id = ID_MT7530,
cbd1f243 3168 .pcs_ops = &mt7530_pcs_ops,
88bdef8b 3169 .sw_setup = mt7530_setup,
defa2e54
AL		 3170 .phy_read_c22 = mt7530_phy_read_c22,
3171 .phy_write_c22 = mt7530_phy_write_c22,
3172 .phy_read_c45 = mt7530_phy_read_c45,
3173 .phy_write_c45 = mt7530_phy_write_c45,
88bdef8b 3174 .pad_setup = mt7530_pad_clk_setup,
59c2215f 3175 .mac_port_get_caps = mt7530_mac_port_get_caps,
88bdef8b
LC		 3176 .mac_port_config = mt7530_mac_config,
3177 },
c288575f
LC		 3178 [ID_MT7531] = {
3179 .id = ID_MT7531,
5b89aeae 3180 .pcs_ops = &mt7530_pcs_ops,
c288575f 3181 .sw_setup = mt7531_setup,
defa2e54
AL		 3182 .phy_read_c22 = mt7531_ind_c22_phy_read,
3183 .phy_write_c22 = mt7531_ind_c22_phy_write,
3184 .phy_read_c45 = mt7531_ind_c45_phy_read,
3185 .phy_write_c45 = mt7531_ind_c45_phy_write,
c288575f
LC		 3186 .pad_setup = mt7531_pad_setup,
3187 .cpu_port_config = mt7531_cpu_port_config,
59c2215f 3188 .mac_port_get_caps = mt7531_mac_port_get_caps,
c288575f 3189 .mac_port_config = mt7531_mac_config,
c288575f 3190 },
110c18bf
DG		 3191 [ID_MT7988] = {
3192 .id = ID_MT7988,
3193 .pcs_ops = &mt7530_pcs_ops,
3194 .sw_setup = mt7988_setup,
3195 .phy_read_c22 = mt7531_ind_c22_phy_read,
3196 .phy_write_c22 = mt7531_ind_c22_phy_write,
3197 .phy_read_c45 = mt7531_ind_c45_phy_read,
3198 .phy_write_c45 = mt7531_ind_c45_phy_write,
3199 .pad_setup = mt7988_pad_setup,
3200 .cpu_port_config = mt7988_cpu_port_config,
3201 .mac_port_get_caps = mt7988_mac_port_get_caps,
3202 .mac_port_config = mt7988_mac_config,
3203 },
88bdef8b 3204};
cb675afc 3205EXPORT_SYMBOL_GPL(mt753x_table);
88bdef8b 3206
cb675afc 3207int
37c9c0d8 3208mt7530_probe_common(struct mt7530_priv *priv)
b8f126a8 3209{
37c9c0d8 3210 struct device *dev = priv->dev;
b8f126a8 3211
37c9c0d8 3212 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
b8f126a8
SW		 3213 if (!priv->ds)
3214 return -ENOMEM;
3215
37c9c0d8 3216 priv->ds->dev = dev;
342afce1 3217 priv->ds->num_ports = MT7530_NUM_PORTS;
7e99e347 3218
ddda1ac1
GU		 3219 /* Get the hardware identifier from the devicetree node.
3220 * We will need it for some of the clock and regulator setup.
3221 */
37c9c0d8 3222 priv->info = of_device_get_match_data(dev);
88bdef8b
LC		 3223 if (!priv->info)
3224 return -EINVAL;
3225
3226 /* Sanity check if these required device operations are filled
3227 * properly.
3228 */
3229 if (!priv->info->sw_setup || !priv->info->pad_setup ||
defa2e54 3230 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 ||
59c2215f 3231 !priv->info->mac_port_get_caps ||
cbd1f243 3232 !priv->info->mac_port_config)
88bdef8b
LC		 3233 return -EINVAL;
3234
3235 priv->id = priv->info->id;
37c9c0d8
DG		 3236 priv->dev = dev;
3237 priv->ds->priv = priv;
3238 priv->ds->ops = &mt7530_switch_ops;
3239 mutex_init(&priv->reg_mutex);
3240 dev_set_drvdata(dev, priv);
b8f126a8 3241
37c9c0d8
DG		 3242 return 0;
3243}
cb675afc 3244EXPORT_SYMBOL_GPL(mt7530_probe_common);
ddda1ac1 3245
cb675afc 3246void
720d7363
DG		 3247mt7530_remove_common(struct mt7530_priv *priv)
3248{
3249 if (priv->irq)
3250 mt7530_free_irq(priv);
3251
3252 dsa_unregister_switch(priv->ds);
3253
3254 mutex_destroy(&priv->reg_mutex);
3255}
cb675afc 3256EXPORT_SYMBOL_GPL(mt7530_remove_common);
b8f126a8
SW		 3257
3258MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
3259MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
3260MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)