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net: dsa: propagate extack to .port_vlan_add
[linux-block.git] / drivers / net / dsa / mt7530.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
b8f126a8
SW		 2/*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
b8f126a8
SW		 5 */
6#include <linux/etherdevice.h>
7#include <linux/if_bridge.h>
8#include <linux/iopoll.h>
9#include <linux/mdio.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
b8f126a8
SW		 13#include <linux/of_mdio.h>
14#include <linux/of_net.h>
15#include <linux/of_platform.h>
ca366d6c 16#include <linux/phylink.h>
b8f126a8
SW		 17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19#include <linux/reset.h>
eb976a55 20#include <linux/gpio/consumer.h>
429a0ede 21#include <linux/gpio/driver.h>
b8f126a8 22#include <net/dsa.h>
b8f126a8
SW		 23
24#include "mt7530.h"
25
26/* String, offset, and register size in bytes if different from 4 bytes */
27static const struct mt7530_mib_desc mt7530_mib[] = {
28 MIB_DESC(1, 0x00, "TxDrop"),
29 MIB_DESC(1, 0x04, "TxCrcErr"),
30 MIB_DESC(1, 0x08, "TxUnicast"),
31 MIB_DESC(1, 0x0c, "TxMulticast"),
32 MIB_DESC(1, 0x10, "TxBroadcast"),
33 MIB_DESC(1, 0x14, "TxCollision"),
34 MIB_DESC(1, 0x18, "TxSingleCollision"),
35 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
36 MIB_DESC(1, 0x20, "TxDeferred"),
37 MIB_DESC(1, 0x24, "TxLateCollision"),
38 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
39 MIB_DESC(1, 0x2c, "TxPause"),
40 MIB_DESC(1, 0x30, "TxPktSz64"),
41 MIB_DESC(1, 0x34, "TxPktSz65To127"),
42 MIB_DESC(1, 0x38, "TxPktSz128To255"),
43 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
44 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
45 MIB_DESC(1, 0x44, "Tx1024ToMax"),
46 MIB_DESC(2, 0x48, "TxBytes"),
47 MIB_DESC(1, 0x60, "RxDrop"),
48 MIB_DESC(1, 0x64, "RxFiltering"),
49 MIB_DESC(1, 0x6c, "RxMulticast"),
50 MIB_DESC(1, 0x70, "RxBroadcast"),
51 MIB_DESC(1, 0x74, "RxAlignErr"),
52 MIB_DESC(1, 0x78, "RxCrcErr"),
53 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
54 MIB_DESC(1, 0x80, "RxFragErr"),
55 MIB_DESC(1, 0x84, "RxOverSzErr"),
56 MIB_DESC(1, 0x88, "RxJabberErr"),
57 MIB_DESC(1, 0x8c, "RxPause"),
58 MIB_DESC(1, 0x90, "RxPktSz64"),
59 MIB_DESC(1, 0x94, "RxPktSz65To127"),
60 MIB_DESC(1, 0x98, "RxPktSz128To255"),
61 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
62 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
63 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
64 MIB_DESC(2, 0xa8, "RxBytes"),
65 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
66 MIB_DESC(1, 0xb4, "RxIngressDrop"),
67 MIB_DESC(1, 0xb8, "RxArlDrop"),
68};
69
b8f126a8
SW		 70static int
71core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
72{
73 struct mii_bus *bus = priv->bus;
74 int value, ret;
75
76 /* Write the desired MMD Devad */
77 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
78 if (ret < 0)
79 goto err;
80
81 /* Write the desired MMD register address */
82 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
83 if (ret < 0)
84 goto err;
85
86 /* Select the Function : DATA with no post increment */
87 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
88 if (ret < 0)
89 goto err;
90
91 /* Read the content of the MMD's selected register */
92 value = bus->read(bus, 0, MII_MMD_DATA);
93
94 return value;
95err:
96 dev_err(&bus->dev, "failed to read mmd register\n");
97
98 return ret;
99}
100
101static int
102core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
103 int devad, u32 data)
104{
105 struct mii_bus *bus = priv->bus;
106 int ret;
107
108 /* Write the desired MMD Devad */
109 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
110 if (ret < 0)
111 goto err;
112
113 /* Write the desired MMD register address */
114 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
115 if (ret < 0)
116 goto err;
117
118 /* Select the Function : DATA with no post increment */
119 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
120 if (ret < 0)
121 goto err;
122
123 /* Write the data into MMD's selected register */
124 ret = bus->write(bus, 0, MII_MMD_DATA, data);
125err:
126 if (ret < 0)
127 dev_err(&bus->dev,
128 "failed to write mmd register\n");
129 return ret;
130}
131
132static void
133core_write(struct mt7530_priv *priv, u32 reg, u32 val)
134{
135 struct mii_bus *bus = priv->bus;
136
137 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
138
139 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
140
141 mutex_unlock(&bus->mdio_lock);
142}
143
144static void
145core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
146{
147 struct mii_bus *bus = priv->bus;
148 u32 val;
149
150 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
151
152 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
153 val &= ~mask;
154 val |= set;
155 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
156
157 mutex_unlock(&bus->mdio_lock);
158}
159
160static void
161core_set(struct mt7530_priv *priv, u32 reg, u32 val)
162{
163 core_rmw(priv, reg, 0, val);
164}
165
166static void
167core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
168{
169 core_rmw(priv, reg, val, 0);
170}
171
172static int
173mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
174{
175 struct mii_bus *bus = priv->bus;
176 u16 page, r, lo, hi;
177 int ret;
178
179 page = (reg >> 6) & 0x3ff;
180 r = (reg >> 2) & 0xf;
181 lo = val & 0xffff;
182 hi = val >> 16;
183
184 /* MT7530 uses 31 as the pseudo port */
185 ret = bus->write(bus, 0x1f, 0x1f, page);
186 if (ret < 0)
187 goto err;
188
189 ret = bus->write(bus, 0x1f, r, lo);
190 if (ret < 0)
191 goto err;
192
193 ret = bus->write(bus, 0x1f, 0x10, hi);
194err:
195 if (ret < 0)
196 dev_err(&bus->dev,
197 "failed to write mt7530 register\n");
198 return ret;
199}
200
201static u32
202mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
203{
204 struct mii_bus *bus = priv->bus;
205 u16 page, r, lo, hi;
206 int ret;
207
208 page = (reg >> 6) & 0x3ff;
209 r = (reg >> 2) & 0xf;
210
211 /* MT7530 uses 31 as the pseudo port */
212 ret = bus->write(bus, 0x1f, 0x1f, page);
213 if (ret < 0) {
214 dev_err(&bus->dev,
215 "failed to read mt7530 register\n");
216 return ret;
217 }
218
219 lo = bus->read(bus, 0x1f, r);
220 hi = bus->read(bus, 0x1f, 0x10);
221
222 return (hi << 16) | (lo & 0xffff);
223}
224
225static void
226mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
227{
228 struct mii_bus *bus = priv->bus;
229
230 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
231
232 mt7530_mii_write(priv, reg, val);
233
234 mutex_unlock(&bus->mdio_lock);
235}
236
c288575f
LC		 237static u32
238_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
239{
240 return mt7530_mii_read(p->priv, p->reg);
241}
242
b8f126a8
SW		 243static u32
244_mt7530_read(struct mt7530_dummy_poll *p)
245{
246 struct mii_bus *bus = p->priv->bus;
247 u32 val;
248
249 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
250
251 val = mt7530_mii_read(p->priv, p->reg);
252
253 mutex_unlock(&bus->mdio_lock);
254
255 return val;
256}
257
258static u32
259mt7530_read(struct mt7530_priv *priv, u32 reg)
260{
261 struct mt7530_dummy_poll p;
262
263 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
264 return _mt7530_read(&p);
265}
266
267static void
268mt7530_rmw(struct mt7530_priv *priv, u32 reg,
269 u32 mask, u32 set)
270{
271 struct mii_bus *bus = priv->bus;
272 u32 val;
273
274 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
275
276 val = mt7530_mii_read(priv, reg);
277 val &= ~mask;
278 val |= set;
279 mt7530_mii_write(priv, reg, val);
280
281 mutex_unlock(&bus->mdio_lock);
282}
283
284static void
285mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
286{
287 mt7530_rmw(priv, reg, 0, val);
288}
289
290static void
291mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
292{
293 mt7530_rmw(priv, reg, val, 0);
294}
295
296static int
297mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
298{
299 u32 val;
300 int ret;
301 struct mt7530_dummy_poll p;
302
303 /* Set the command operating upon the MAC address entries */
304 val = ATC_BUSY | ATC_MAT(0) | cmd;
305 mt7530_write(priv, MT7530_ATC, val);
306
307 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
308 ret = readx_poll_timeout(_mt7530_read, &p, val,
309 !(val & ATC_BUSY), 20, 20000);
310 if (ret < 0) {
311 dev_err(priv->dev, "reset timeout\n");
312 return ret;
313 }
314
315 /* Additional sanity for read command if the specified
316 * entry is invalid
317 */
318 val = mt7530_read(priv, MT7530_ATC);
319 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
320 return -EINVAL;
321
322 if (rsp)
323 *rsp = val;
324
325 return 0;
326}
327
328static void
329mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
330{
331 u32 reg[3];
332 int i;
333
334 /* Read from ARL table into an array */
335 for (i = 0; i < 3; i++) {
336 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
337
338 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
339 __func__, __LINE__, i, reg[i]);
340 }
341
342 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
343 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
344 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
345 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
346 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
347 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
348 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
349 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
350 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
351 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
352}
353
354static void
355mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
356 u8 port_mask, const u8 *mac,
357 u8 aging, u8 type)
358{
359 u32 reg[3] = { 0 };
360 int i;
361
362 reg[1] |= vid & CVID_MASK;
363 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
364 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
365 /* STATIC_ENT indicate that entry is static wouldn't
366 * be aged out and STATIC_EMP specified as erasing an
367 * entry
368 */
369 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
370 reg[1] |= mac[5] << MAC_BYTE_5;
371 reg[1] |= mac[4] << MAC_BYTE_4;
372 reg[0] |= mac[3] << MAC_BYTE_3;
373 reg[0] |= mac[2] << MAC_BYTE_2;
374 reg[0] |= mac[1] << MAC_BYTE_1;
375 reg[0] |= mac[0] << MAC_BYTE_0;
376
377 /* Write array into the ARL table */
378 for (i = 0; i < 3; i++)
379 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
380}
381
88bdef8b 382/* Setup TX circuit including relevant PAD and driving */
b8f126a8 383static int
88bdef8b 384mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
b8f126a8
SW		 385{
386 struct mt7530_priv *priv = ds->priv;
7ef6f6f8
RD		 387 u32 ncpo1, ssc_delta, trgint, i, xtal;
388
389 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
390
391 if (xtal == HWTRAP_XTAL_20MHZ) {
392 dev_err(priv->dev,
393 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
394 __func__);
395 return -EINVAL;
396 }
b8f126a8 397
88bdef8b 398 switch (interface) {
b8f126a8
SW		 399 case PHY_INTERFACE_MODE_RGMII:
400 trgint = 0;
7ef6f6f8 401 /* PLL frequency: 125MHz */
b8f126a8 402 ncpo1 = 0x0c80;
b8f126a8
SW		 403 break;
404 case PHY_INTERFACE_MODE_TRGMII:
405 trgint = 1;
7ef6f6f8
RD		 406 if (priv->id == ID_MT7621) {
407 /* PLL frequency: 150MHz: 1.2GBit */
408 if (xtal == HWTRAP_XTAL_40MHZ)
409 ncpo1 = 0x0780;
410 if (xtal == HWTRAP_XTAL_25MHZ)
411 ncpo1 = 0x0a00;
412 } else { /* PLL frequency: 250MHz: 2.0Gbit */
413 if (xtal == HWTRAP_XTAL_40MHZ)
414 ncpo1 = 0x0c80;
415 if (xtal == HWTRAP_XTAL_25MHZ)
416 ncpo1 = 0x1400;
417 }
b8f126a8
SW		 418 break;
419 default:
88bdef8b
LC		 420 dev_err(priv->dev, "xMII interface %d not supported\n",
421 interface);
b8f126a8
SW		 422 return -EINVAL;
423 }
424
7ef6f6f8
RD		 425 if (xtal == HWTRAP_XTAL_25MHZ)
426 ssc_delta = 0x57;
427 else
428 ssc_delta = 0x87;
429
b8f126a8
SW		 430 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
431 P6_INTF_MODE(trgint));
432
433 /* Lower Tx Driving for TRGMII path */
434 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
435 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
436 TD_DM_DRVP(8) | TD_DM_DRVN(8));
437
438 /* Setup core clock for MT7530 */
439 if (!trgint) {
440 /* Disable MT7530 core clock */
441 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
442
443 /* Disable PLL, since phy_device has not yet been created
444 * provided for phy_[read,write]_mmd_indirect is called, we
445 * provide our own core_write_mmd_indirect to complete this
446 * function.
447 */
448 core_write_mmd_indirect(priv,
449 CORE_GSWPLL_GRP1,
450 MDIO_MMD_VEND2,
451 0);
452
453 /* Set core clock into 500Mhz */
454 core_write(priv, CORE_GSWPLL_GRP2,
455 RG_GSWPLL_POSDIV_500M(1) |
456 RG_GSWPLL_FBKDIV_500M(25));
457
458 /* Enable PLL */
459 core_write(priv, CORE_GSWPLL_GRP1,
460 RG_GSWPLL_EN_PRE |
461 RG_GSWPLL_POSDIV_200M(2) |
462 RG_GSWPLL_FBKDIV_200M(32));
463
464 /* Enable MT7530 core clock */
465 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
466 }
467
468 /* Setup the MT7530 TRGMII Tx Clock */
469 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
470 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
471 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
472 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
473 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
474 core_write(priv, CORE_PLL_GROUP4,
475 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
476 RG_SYSPLL_BIAS_LPF_EN);
477 core_write(priv, CORE_PLL_GROUP2,
478 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
479 RG_SYSPLL_POSDIV(1));
480 core_write(priv, CORE_PLL_GROUP7,
481 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
482 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
483 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
484 REG_GSWCK_EN | REG_TRGMIICK_EN);
485
486 if (!trgint)
487 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
488 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
489 RD_TAP_MASK, RD_TAP(16));
b8f126a8
SW		 490 return 0;
491}
492
c288575f
LC		 493static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
494{
495 u32 val;
496
497 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
498
499 return (val & PAD_DUAL_SGMII_EN) != 0;
500}
501
502static int
503mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
504{
505 struct mt7530_priv *priv = ds->priv;
506 u32 top_sig;
507 u32 hwstrap;
508 u32 xtal;
509 u32 val;
510
511 if (mt7531_dual_sgmii_supported(priv))
512 return 0;
513
514 val = mt7530_read(priv, MT7531_CREV);
515 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
516 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
517 if ((val & CHIP_REV_M) > 0)
518 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
519 HWTRAP_XTAL_FSEL_25MHZ;
520 else
521 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
522
523 /* Step 1 : Disable MT7531 COREPLL */
524 val = mt7530_read(priv, MT7531_PLLGP_EN);
525 val &= ~EN_COREPLL;
526 mt7530_write(priv, MT7531_PLLGP_EN, val);
527
528 /* Step 2: switch to XTAL output */
529 val = mt7530_read(priv, MT7531_PLLGP_EN);
530 val |= SW_CLKSW;
531 mt7530_write(priv, MT7531_PLLGP_EN, val);
532
533 val = mt7530_read(priv, MT7531_PLLGP_CR0);
534 val &= ~RG_COREPLL_EN;
535 mt7530_write(priv, MT7531_PLLGP_CR0, val);
536
537 /* Step 3: disable PLLGP and enable program PLLGP */
538 val = mt7530_read(priv, MT7531_PLLGP_EN);
539 val |= SW_PLLGP;
540 mt7530_write(priv, MT7531_PLLGP_EN, val);
541
542 /* Step 4: program COREPLL output frequency to 500MHz */
543 val = mt7530_read(priv, MT7531_PLLGP_CR0);
544 val &= ~RG_COREPLL_POSDIV_M;
545 val |= 2 << RG_COREPLL_POSDIV_S;
546 mt7530_write(priv, MT7531_PLLGP_CR0, val);
547 usleep_range(25, 35);
548
549 switch (xtal) {
550 case HWTRAP_XTAL_FSEL_25MHZ:
551 val = mt7530_read(priv, MT7531_PLLGP_CR0);
552 val &= ~RG_COREPLL_SDM_PCW_M;
553 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
554 mt7530_write(priv, MT7531_PLLGP_CR0, val);
555 break;
556 case HWTRAP_XTAL_FSEL_40MHZ:
557 val = mt7530_read(priv, MT7531_PLLGP_CR0);
558 val &= ~RG_COREPLL_SDM_PCW_M;
559 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
560 mt7530_write(priv, MT7531_PLLGP_CR0, val);
561 break;
0e8c266c 562 }
c288575f
LC		 563
564 /* Set feedback divide ratio update signal to high */
565 val = mt7530_read(priv, MT7531_PLLGP_CR0);
566 val |= RG_COREPLL_SDM_PCW_CHG;
567 mt7530_write(priv, MT7531_PLLGP_CR0, val);
568 /* Wait for at least 16 XTAL clocks */
569 usleep_range(10, 20);
570
571 /* Step 5: set feedback divide ratio update signal to low */
572 val = mt7530_read(priv, MT7531_PLLGP_CR0);
573 val &= ~RG_COREPLL_SDM_PCW_CHG;
574 mt7530_write(priv, MT7531_PLLGP_CR0, val);
575
576 /* Enable 325M clock for SGMII */
577 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
578
579 /* Enable 250SSC clock for RGMII */
580 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
581
582 /* Step 6: Enable MT7531 PLL */
583 val = mt7530_read(priv, MT7531_PLLGP_CR0);
584 val |= RG_COREPLL_EN;
585 mt7530_write(priv, MT7531_PLLGP_CR0, val);
586
587 val = mt7530_read(priv, MT7531_PLLGP_EN);
588 val |= EN_COREPLL;
589 mt7530_write(priv, MT7531_PLLGP_EN, val);
590 usleep_range(25, 35);
591
592 return 0;
593}
594
b8f126a8
SW		 595static void
596mt7530_mib_reset(struct dsa_switch *ds)
597{
598 struct mt7530_priv *priv = ds->priv;
599
600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
601 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
602}
603
b8f126a8
SW		 604static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
605{
606 struct mt7530_priv *priv = ds->priv;
607
608 return mdiobus_read_nested(priv->bus, port, regnum);
609}
610
360cc342
CIK		 611static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
612 u16 val)
b8f126a8
SW		 613{
614 struct mt7530_priv *priv = ds->priv;
615
616 return mdiobus_write_nested(priv->bus, port, regnum, val);
617}
618
c288575f
LC		 619static int
620mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
621 int regnum)
622{
623 struct mii_bus *bus = priv->bus;
624 struct mt7530_dummy_poll p;
625 u32 reg, val;
626 int ret;
627
628 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
629
630 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
631
632 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
633 !(val & MT7531_PHY_ACS_ST), 20, 100000);
634 if (ret < 0) {
635 dev_err(priv->dev, "poll timeout\n");
636 goto out;
637 }
638
639 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
640 MT7531_MDIO_DEV_ADDR(devad) | regnum;
641 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
642
643 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
644 !(val & MT7531_PHY_ACS_ST), 20, 100000);
645 if (ret < 0) {
646 dev_err(priv->dev, "poll timeout\n");
647 goto out;
648 }
649
650 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
651 MT7531_MDIO_DEV_ADDR(devad);
652 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
653
654 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
655 !(val & MT7531_PHY_ACS_ST), 20, 100000);
656 if (ret < 0) {
657 dev_err(priv->dev, "poll timeout\n");
658 goto out;
659 }
660
661 ret = val & MT7531_MDIO_RW_DATA_MASK;
662out:
663 mutex_unlock(&bus->mdio_lock);
664
665 return ret;
666}
667
668static int
669mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
670 int regnum, u32 data)
671{
672 struct mii_bus *bus = priv->bus;
673 struct mt7530_dummy_poll p;
674 u32 val, reg;
675 int ret;
676
677 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
678
679 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
680
681 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
682 !(val & MT7531_PHY_ACS_ST), 20, 100000);
683 if (ret < 0) {
684 dev_err(priv->dev, "poll timeout\n");
685 goto out;
686 }
687
688 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
689 MT7531_MDIO_DEV_ADDR(devad) | regnum;
690 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
691
692 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
693 !(val & MT7531_PHY_ACS_ST), 20, 100000);
694 if (ret < 0) {
695 dev_err(priv->dev, "poll timeout\n");
696 goto out;
697 }
698
699 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
700 MT7531_MDIO_DEV_ADDR(devad) | data;
701 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
702
703 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
704 !(val & MT7531_PHY_ACS_ST), 20, 100000);
705 if (ret < 0) {
706 dev_err(priv->dev, "poll timeout\n");
707 goto out;
708 }
709
710out:
711 mutex_unlock(&bus->mdio_lock);
712
713 return ret;
714}
715
716static int
717mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
718{
719 struct mii_bus *bus = priv->bus;
720 struct mt7530_dummy_poll p;
721 int ret;
722 u32 val;
723
724 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
725
726 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
727
728 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
729 !(val & MT7531_PHY_ACS_ST), 20, 100000);
730 if (ret < 0) {
731 dev_err(priv->dev, "poll timeout\n");
732 goto out;
733 }
734
735 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
736 MT7531_MDIO_REG_ADDR(regnum);
737
738 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
739
740 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
741 !(val & MT7531_PHY_ACS_ST), 20, 100000);
742 if (ret < 0) {
743 dev_err(priv->dev, "poll timeout\n");
744 goto out;
745 }
746
747 ret = val & MT7531_MDIO_RW_DATA_MASK;
748out:
749 mutex_unlock(&bus->mdio_lock);
750
751 return ret;
752}
753
754static int
755mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
756 u16 data)
757{
758 struct mii_bus *bus = priv->bus;
759 struct mt7530_dummy_poll p;
760 int ret;
761 u32 reg;
762
763 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
764
765 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
766
767 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
768 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
769 if (ret < 0) {
770 dev_err(priv->dev, "poll timeout\n");
771 goto out;
772 }
773
774 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
775 MT7531_MDIO_REG_ADDR(regnum) | data;
776
777 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
778
779 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
780 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
781 if (ret < 0) {
782 dev_err(priv->dev, "poll timeout\n");
783 goto out;
784 }
785
786out:
787 mutex_unlock(&bus->mdio_lock);
788
789 return ret;
790}
791
792static int
793mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
794{
795 struct mt7530_priv *priv = ds->priv;
796 int devad;
797 int ret;
798
799 if (regnum & MII_ADDR_C45) {
800 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
801 ret = mt7531_ind_c45_phy_read(priv, port, devad,
802 regnum & MII_REGADDR_C45_MASK);
803 } else {
804 ret = mt7531_ind_c22_phy_read(priv, port, regnum);
805 }
806
807 return ret;
808}
809
810static int
811mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
812 u16 data)
813{
814 struct mt7530_priv *priv = ds->priv;
815 int devad;
816 int ret;
817
818 if (regnum & MII_ADDR_C45) {
819 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
820 ret = mt7531_ind_c45_phy_write(priv, port, devad,
821 regnum & MII_REGADDR_C45_MASK,
822 data);
823 } else {
824 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
825 }
826
827 return ret;
828}
829
b8f126a8 830static void
89f09048
FF		 831mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
832 uint8_t *data)
b8f126a8
SW		 833{
834 int i;
835
89f09048
FF		 836 if (stringset != ETH_SS_STATS)
837 return;
838
b8f126a8
SW		 839 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
840 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
841 ETH_GSTRING_LEN);
842}
843
844static void
845mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
846 uint64_t *data)
847{
848 struct mt7530_priv *priv = ds->priv;
849 const struct mt7530_mib_desc *mib;
850 u32 reg, i;
851 u64 hi;
852
853 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
854 mib = &mt7530_mib[i];
855 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
856
857 data[i] = mt7530_read(priv, reg);
858 if (mib->size == 2) {
859 hi = mt7530_read(priv, reg + 4);
860 data[i] |= hi << 32;
861 }
862 }
863}
864
865static int
89f09048 866mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
b8f126a8 867{
89f09048
FF		 868 if (sset != ETH_SS_STATS)
869 return 0;
870
b8f126a8
SW		 871 return ARRAY_SIZE(mt7530_mib);
872}
873
ea6d5c92
DQ		 874static int
875mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
876{
877 struct mt7530_priv *priv = ds->priv;
878 unsigned int secs = msecs / 1000;
879 unsigned int tmp_age_count;
880 unsigned int error = -1;
881 unsigned int age_count;
882 unsigned int age_unit;
883
884 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
885 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
886 return -ERANGE;
887
888 /* iterate through all possible age_count to find the closest pair */
889 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
890 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
891
892 if (tmp_age_unit <= AGE_UNIT_MAX) {
893 unsigned int tmp_error = secs -
894 (tmp_age_count + 1) * (tmp_age_unit + 1);
895
896 /* found a closer pair */
897 if (error > tmp_error) {
898 error = tmp_error;
899 age_count = tmp_age_count;
900 age_unit = tmp_age_unit;
901 }
902
903 /* found the exact match, so break the loop */
904 if (!error)
905 break;
906 }
907 }
908
909 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
910
911 return 0;
912}
913
38f790a8
RD		 914static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
915{
916 struct mt7530_priv *priv = ds->priv;
917 u8 tx_delay = 0;
918 int val;
919
920 mutex_lock(&priv->reg_mutex);
921
922 val = mt7530_read(priv, MT7530_MHWTRAP);
923
924 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
925 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
926
927 switch (priv->p5_intf_sel) {
928 case P5_INTF_SEL_PHY_P0:
929 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
930 val |= MHWTRAP_PHY0_SEL;
df561f66 931 fallthrough;
38f790a8
RD		 932 case P5_INTF_SEL_PHY_P4:
933 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
934 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
935
936 /* Setup the MAC by default for the cpu port */
937 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
938 break;
939 case P5_INTF_SEL_GMAC5:
940 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
941 val &= ~MHWTRAP_P5_DIS;
942 break;
943 case P5_DISABLED:
944 interface = PHY_INTERFACE_MODE_NA;
945 break;
946 default:
947 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
948 priv->p5_intf_sel);
949 goto unlock_exit;
950 }
951
952 /* Setup RGMII settings */
953 if (phy_interface_mode_is_rgmii(interface)) {
954 val |= MHWTRAP_P5_RGMII_MODE;
955
956 /* P5 RGMII RX Clock Control: delay setting for 1000M */
957 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
958
959 /* Don't set delay in DSA mode */
960 if (!dsa_is_dsa_port(priv->ds, 5) &&
961 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
962 interface == PHY_INTERFACE_MODE_RGMII_ID))
963 tx_delay = 4; /* n * 0.5 ns */
964
965 /* P5 RGMII TX Clock Control: delay x */
966 mt7530_write(priv, MT7530_P5RGMIITXCR,
967 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
968
969 /* reduce P5 RGMII Tx driving, 8mA */
970 mt7530_write(priv, MT7530_IO_DRV_CR,
971 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
972 }
973
974 mt7530_write(priv, MT7530_MHWTRAP, val);
975
976 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
977 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
978
979 priv->p5_interface = interface;
980
981unlock_exit:
982 mutex_unlock(&priv->reg_mutex);
983}
984
b8f126a8 985static int
c288575f 986mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
b8f126a8 987{
c288575f 988 struct mt7530_priv *priv = ds->priv;
0ce0c3cd 989 int ret;
c288575f
LC		 990
991 /* Setup max capability of CPU port at first */
0ce0c3cd
AD		 992 if (priv->info->cpu_port_config) {
993 ret = priv->info->cpu_port_config(ds, port);
994 if (ret)
995 return ret;
996 }
c288575f 997
b8f126a8
SW		 998 /* Enable Mediatek header mode on the cpu port */
999 mt7530_write(priv, MT7530_PVC_P(port),
1000 PORT_SPEC_TAG);
1001
5e5502e0
DQ		 1002 /* Unknown multicast frame forwarding to the cpu port */
1003 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
b8f126a8 1004
ddda1ac1
GU		 1005 /* Set CPU port number */
1006 if (priv->id == ID_MT7621)
1007 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1008
b8f126a8 1009 /* CPU port gets connected to all user ports of
c288575f 1010 * the switch.
b8f126a8
SW		 1011 */
1012 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 1013 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8
SW		 1014
1015 return 0;
1016}
1017
1018static int
1019mt7530_port_enable(struct dsa_switch *ds, int port,
1020 struct phy_device *phy)
1021{
1022 struct mt7530_priv *priv = ds->priv;
1023
74be4bab
VD		 1024 if (!dsa_is_user_port(ds, port))
1025 return 0;
1026
b8f126a8
SW		 1027 mutex_lock(&priv->reg_mutex);
1028
b8f126a8
SW		 1029 /* Allow the user port gets connected to the cpu port and also
1030 * restore the port matrix if the port is the member of a certain
1031 * bridge.
1032 */
1033 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
1034 priv->ports[port].enable = true;
1035 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1036 priv->ports[port].pm);
1d01145f 1037 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1038
1039 mutex_unlock(&priv->reg_mutex);
1040
1041 return 0;
1042}
1043
1044static void
75104db0 1045mt7530_port_disable(struct dsa_switch *ds, int port)
b8f126a8
SW		 1046{
1047 struct mt7530_priv *priv = ds->priv;
1048
74be4bab
VD		 1049 if (!dsa_is_user_port(ds, port))
1050 return;
1051
b8f126a8
SW		 1052 mutex_lock(&priv->reg_mutex);
1053
1054 /* Clear up all port matrix which could be restored in the next
1055 * enablement for the port.
1056 */
1057 priv->ports[port].enable = false;
1058 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1059 PCR_MATRIX_CLR);
1d01145f 1060 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1061
1062 mutex_unlock(&priv->reg_mutex);
1063}
1064
9470174e
DQ		 1065static int
1066mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1067{
1068 struct mt7530_priv *priv = ds->priv;
1069 struct mii_bus *bus = priv->bus;
1070 int length;
1071 u32 val;
1072
1073 /* When a new MTU is set, DSA always set the CPU port's MTU to the
1074 * largest MTU of the slave ports. Because the switch only has a global
1075 * RX length register, only allowing CPU port here is enough.
1076 */
1077 if (!dsa_is_cpu_port(ds, port))
1078 return 0;
1079
1080 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1081
1082 val = mt7530_mii_read(priv, MT7530_GMACCR);
1083 val &= ~MAX_RX_PKT_LEN_MASK;
1084
1085 /* RX length also includes Ethernet header, MTK tag, and FCS length */
1086 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1087 if (length <= 1522) {
1088 val |= MAX_RX_PKT_LEN_1522;
1089 } else if (length <= 1536) {
1090 val |= MAX_RX_PKT_LEN_1536;
1091 } else if (length <= 1552) {
1092 val |= MAX_RX_PKT_LEN_1552;
1093 } else {
1094 val &= ~MAX_RX_JUMBO_MASK;
1095 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1096 val |= MAX_RX_PKT_LEN_JUMBO;
1097 }
1098
1099 mt7530_mii_write(priv, MT7530_GMACCR, val);
1100
1101 mutex_unlock(&bus->mdio_lock);
1102
1103 return 0;
1104}
1105
1106static int
1107mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1108{
1109 return MT7530_MAX_MTU;
1110}
1111
b8f126a8
SW		 1112static void
1113mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1114{
1115 struct mt7530_priv *priv = ds->priv;
1116 u32 stp_state;
1117
1118 switch (state) {
1119 case BR_STATE_DISABLED:
1120 stp_state = MT7530_STP_DISABLED;
1121 break;
1122 case BR_STATE_BLOCKING:
1123 stp_state = MT7530_STP_BLOCKING;
1124 break;
1125 case BR_STATE_LISTENING:
1126 stp_state = MT7530_STP_LISTENING;
1127 break;
1128 case BR_STATE_LEARNING:
1129 stp_state = MT7530_STP_LEARNING;
1130 break;
1131 case BR_STATE_FORWARDING:
1132 default:
1133 stp_state = MT7530_STP_FORWARDING;
1134 break;
1135 }
1136
1137 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
1138}
1139
1140static int
1141mt7530_port_bridge_join(struct dsa_switch *ds, int port,
1142 struct net_device *bridge)
1143{
1144 struct mt7530_priv *priv = ds->priv;
1145 u32 port_bitmap = BIT(MT7530_CPU_PORT);
1146 int i;
1147
1148 mutex_lock(&priv->reg_mutex);
1149
1150 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1151 /* Add this port to the port matrix of the other ports in the
1152 * same bridge. If the port is disabled, port matrix is kept
1153 * and not being setup until the port becomes enabled.
1154 */
4a5b85ff 1155 if (dsa_is_user_port(ds, i) && i != port) {
c8652c83 1156 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 1157 continue;
1158 if (priv->ports[i].enable)
1159 mt7530_set(priv, MT7530_PCR_P(i),
1160 PCR_MATRIX(BIT(port)));
1161 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
1162
1163 port_bitmap |= BIT(i);
1164 }
1165 }
1166
1167 /* Add the all other ports to this port matrix. */
1168 if (priv->ports[port].enable)
1169 mt7530_rmw(priv, MT7530_PCR_P(port),
1170 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1171 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1172
1173 mutex_unlock(&priv->reg_mutex);
1174
1175 return 0;
1176}
1177
83163f7d
SW		 1178static void
1179mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1180{
1181 struct mt7530_priv *priv = ds->priv;
1182 bool all_user_ports_removed = true;
1183 int i;
1184
1185 /* When a port is removed from the bridge, the port would be set up
1186 * back to the default as is at initial boot which is a VLAN-unaware
1187 * port.
1188 */
1189 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1190 MT7530_PORT_MATRIX_MODE);
e045124e
DQ		 1191 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1192 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
1193 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d 1194
83163f7d
SW		 1195 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1196 if (dsa_is_user_port(ds, i) &&
68bb8ea8 1197 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
83163f7d
SW		 1198 all_user_ports_removed = false;
1199 break;
1200 }
1201 }
1202
1203 /* CPU port also does the same thing until all user ports belonging to
1204 * the CPU port get out of VLAN filtering mode.
1205 */
1206 if (all_user_ports_removed) {
1207 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
1208 PCR_MATRIX(dsa_user_ports(priv->ds)));
e045124e
DQ		 1209 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
1210 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d
SW		 1211 }
1212}
1213
1214static void
1215mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1216{
1217 struct mt7530_priv *priv = ds->priv;
1218
1219 /* The real fabric path would be decided on the membership in the
1220 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
1221 * means potential VLAN can be consisting of certain subset of all
1222 * ports.
1223 */
1224 mt7530_rmw(priv, MT7530_PCR_P(port),
1225 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
1226
1227 /* Trapped into security mode allows packet forwarding through VLAN
38152ea3
DQ		 1228 * table lookup. CPU port is set to fallback mode to let untagged
1229 * frames pass through.
83163f7d 1230 */
38152ea3
DQ		 1231 if (dsa_is_cpu_port(ds, port))
1232 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1233 MT7530_PORT_FALLBACK_MODE);
1234 else
1235 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1236 MT7530_PORT_SECURITY_MODE);
83163f7d
SW		 1237
1238 /* Set the port as a user port which is to be able to recognize VID
1239 * from incoming packets before fetching entry within the VLAN table.
1240 */
e045124e
DQ		 1241 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1242 VLAN_ATTR(MT7530_VLAN_USER) |
1243 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
83163f7d
SW		 1244}
1245
b8f126a8
SW		 1246static void
1247mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
1248 struct net_device *bridge)
1249{
1250 struct mt7530_priv *priv = ds->priv;
1251 int i;
1252
1253 mutex_lock(&priv->reg_mutex);
1254
1255 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1256 /* Remove this port from the port matrix of the other ports
1257 * in the same bridge. If the port is disabled, port matrix
1258 * is kept and not being setup until the port becomes enabled.
83163f7d
SW		 1259 * And the other port's port matrix cannot be broken when the
1260 * other port is still a VLAN-aware port.
b8f126a8 1261 */
2a130551 1262 if (dsa_is_user_port(ds, i) && i != port &&
68bb8ea8 1263 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
c8652c83 1264 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 1265 continue;
1266 if (priv->ports[i].enable)
1267 mt7530_clear(priv, MT7530_PCR_P(i),
1268 PCR_MATRIX(BIT(port)));
1269 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
1270 }
1271 }
1272
1273 /* Set the cpu port to be the only one in the port matrix of
1274 * this port.
1275 */
1276 if (priv->ports[port].enable)
1277 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1278 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
1279 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
1280
1281 mutex_unlock(&priv->reg_mutex);
1282}
1283
1284static int
b8f126a8 1285mt7530_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 1286 const unsigned char *addr, u16 vid)
b8f126a8
SW		 1287{
1288 struct mt7530_priv *priv = ds->priv;
1b6dd556 1289 int ret;
b8f126a8
SW		 1290 u8 port_mask = BIT(port);
1291
1292 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1293 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 1294 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 1295 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 1296
1297 return ret;
b8f126a8
SW		 1298}
1299
1300static int
1301mt7530_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1302 const unsigned char *addr, u16 vid)
b8f126a8
SW		 1303{
1304 struct mt7530_priv *priv = ds->priv;
1305 int ret;
1306 u8 port_mask = BIT(port);
1307
1308 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1309 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 1310 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 1311 mutex_unlock(&priv->reg_mutex);
1312
1313 return ret;
1314}
1315
1316static int
1317mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1318 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 1319{
1320 struct mt7530_priv *priv = ds->priv;
1321 struct mt7530_fdb _fdb = { 0 };
1322 int cnt = MT7530_NUM_FDB_RECORDS;
1323 int ret = 0;
1324 u32 rsp = 0;
1325
1326 mutex_lock(&priv->reg_mutex);
1327
1328 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1329 if (ret < 0)
1330 goto err;
1331
1332 do {
1333 if (rsp & ATC_SRCH_HIT) {
1334 mt7530_fdb_read(priv, &_fdb);
1335 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 1336 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1337 data);
b8f126a8
SW		 1338 if (ret < 0)
1339 break;
1340 }
1341 }
1342 } while (--cnt &&
1343 !(rsp & ATC_SRCH_END) &&
1344 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1345err:
1346 mutex_unlock(&priv->reg_mutex);
1347
1348 return 0;
1349}
1350
83163f7d
SW		 1351static int
1352mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1353{
1354 struct mt7530_dummy_poll p;
1355 u32 val;
1356 int ret;
1357
1358 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1359 mt7530_write(priv, MT7530_VTCR, val);
1360
1361 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1362 ret = readx_poll_timeout(_mt7530_read, &p, val,
1363 !(val & VTCR_BUSY), 20, 20000);
1364 if (ret < 0) {
1365 dev_err(priv->dev, "poll timeout\n");
1366 return ret;
1367 }
1368
1369 val = mt7530_read(priv, MT7530_VTCR);
1370 if (val & VTCR_INVALID) {
1371 dev_err(priv->dev, "read VTCR invalid\n");
1372 return -EINVAL;
1373 }
1374
1375 return 0;
1376}
1377
1378static int
1379mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
bae33f2b 1380 bool vlan_filtering)
83163f7d 1381{
83163f7d
SW		 1382 if (vlan_filtering) {
1383 /* The port is being kept as VLAN-unaware port when bridge is
1384 * set up with vlan_filtering not being set, Otherwise, the
1385 * port and the corresponding CPU port is required the setup
1386 * for becoming a VLAN-aware port.
1387 */
1388 mt7530_port_set_vlan_aware(ds, port);
1389 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
e3ee07d1
VO		 1390 } else {
1391 mt7530_port_set_vlan_unaware(ds, port);
83163f7d
SW		 1392 }
1393
1394 return 0;
1395}
1396
83163f7d
SW		 1397static void
1398mt7530_hw_vlan_add(struct mt7530_priv *priv,
1399 struct mt7530_hw_vlan_entry *entry)
1400{
1401 u8 new_members;
1402 u32 val;
1403
1404 new_members = entry->old_members | BIT(entry->port) |
1405 BIT(MT7530_CPU_PORT);
1406
1407 /* Validate the entry with independent learning, create egress tag per
1408 * VLAN and joining the port as one of the port members.
1409 */
1410 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1411 mt7530_write(priv, MT7530_VAWD1, val);
1412
1413 /* Decide whether adding tag or not for those outgoing packets from the
1414 * port inside the VLAN.
1415 */
1416 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1417 MT7530_VLAN_EGRESS_TAG;
1418 mt7530_rmw(priv, MT7530_VAWD2,
1419 ETAG_CTRL_P_MASK(entry->port),
1420 ETAG_CTRL_P(entry->port, val));
1421
1422 /* CPU port is always taken as a tagged port for serving more than one
1423 * VLANs across and also being applied with egress type stack mode for
1424 * that VLAN tags would be appended after hardware special tag used as
1425 * DSA tag.
1426 */
1427 mt7530_rmw(priv, MT7530_VAWD2,
1428 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1429 ETAG_CTRL_P(MT7530_CPU_PORT,
1430 MT7530_VLAN_EGRESS_STACK));
1431}
1432
1433static void
1434mt7530_hw_vlan_del(struct mt7530_priv *priv,
1435 struct mt7530_hw_vlan_entry *entry)
1436{
1437 u8 new_members;
1438 u32 val;
1439
1440 new_members = entry->old_members & ~BIT(entry->port);
1441
1442 val = mt7530_read(priv, MT7530_VAWD1);
1443 if (!(val & VLAN_VALID)) {
1444 dev_err(priv->dev,
1445 "Cannot be deleted due to invalid entry\n");
1446 return;
1447 }
1448
1449 /* If certain member apart from CPU port is still alive in the VLAN,
1450 * the entry would be kept valid. Otherwise, the entry is got to be
1451 * disabled.
1452 */
1453 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1454 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1455 VLAN_VALID;
1456 mt7530_write(priv, MT7530_VAWD1, val);
1457 } else {
1458 mt7530_write(priv, MT7530_VAWD1, 0);
1459 mt7530_write(priv, MT7530_VAWD2, 0);
1460 }
1461}
1462
1463static void
1464mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1465 struct mt7530_hw_vlan_entry *entry,
1466 mt7530_vlan_op vlan_op)
1467{
1468 u32 val;
1469
1470 /* Fetch entry */
1471 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1472
1473 val = mt7530_read(priv, MT7530_VAWD1);
1474
1475 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1476
1477 /* Manipulate entry */
1478 vlan_op(priv, entry);
1479
1480 /* Flush result to hardware */
1481 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1482}
1483
1958d581 1484static int
83163f7d 1485mt7530_port_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 1486 const struct switchdev_obj_port_vlan *vlan,
1487 struct netlink_ext_ack *extack)
83163f7d
SW		 1488{
1489 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1490 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1491 struct mt7530_hw_vlan_entry new_entry;
1492 struct mt7530_priv *priv = ds->priv;
83163f7d 1493
83163f7d
SW		 1494 mutex_lock(&priv->reg_mutex);
1495
b7a9e0da
VO		 1496 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1497 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
83163f7d
SW		 1498
1499 if (pvid) {
1500 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
b7a9e0da
VO		 1501 G0_PORT_VID(vlan->vid));
1502 priv->ports[port].pvid = vlan->vid;
83163f7d
SW		 1503 }
1504
1505 mutex_unlock(&priv->reg_mutex);
1958d581
VO		 1506
1507 return 0;
83163f7d
SW		 1508}
1509
1510static int
1511mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1512 const struct switchdev_obj_port_vlan *vlan)
1513{
1514 struct mt7530_hw_vlan_entry target_entry;
1515 struct mt7530_priv *priv = ds->priv;
b7a9e0da 1516 u16 pvid;
83163f7d 1517
83163f7d
SW		 1518 mutex_lock(&priv->reg_mutex);
1519
1520 pvid = priv->ports[port].pvid;
b7a9e0da
VO		 1521 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1522 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1523 mt7530_hw_vlan_del);
83163f7d 1524
b7a9e0da
VO		 1525 /* PVID is being restored to the default whenever the PVID port
1526 * is being removed from the VLAN.
1527 */
1528 if (pvid == vlan->vid)
1529 pvid = G0_PORT_VID_DEF;
83163f7d
SW		 1530
1531 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1532 priv->ports[port].pvid = pvid;
1533
1534 mutex_unlock(&priv->reg_mutex);
1535
1536 return 0;
1537}
1538
c288575f
LC		 1539static int mt753x_mirror_port_get(unsigned int id, u32 val)
1540{
1541 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1542 MIRROR_PORT(val);
1543}
1544
1545static int mt753x_mirror_port_set(unsigned int id, u32 val)
1546{
1547 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1548 MIRROR_PORT(val);
1549}
1550
1551static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
37feab60
DQ		 1552 struct dsa_mall_mirror_tc_entry *mirror,
1553 bool ingress)
1554{
1555 struct mt7530_priv *priv = ds->priv;
c288575f 1556 int monitor_port;
37feab60
DQ		 1557 u32 val;
1558
1559 /* Check for existent entry */
1560 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1561 return -EEXIST;
1562
c288575f 1563 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
37feab60
DQ		 1564
1565 /* MT7530 only supports one monitor port */
c288575f
LC		 1566 monitor_port = mt753x_mirror_port_get(priv->id, val);
1567 if (val & MT753X_MIRROR_EN(priv->id) &&
1568 monitor_port != mirror->to_local_port)
37feab60
DQ		 1569 return -EEXIST;
1570
c288575f
LC		 1571 val |= MT753X_MIRROR_EN(priv->id);
1572 val &= ~MT753X_MIRROR_MASK(priv->id);
1573 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1574 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1575
1576 val = mt7530_read(priv, MT7530_PCR_P(port));
1577 if (ingress) {
1578 val |= PORT_RX_MIR;
1579 priv->mirror_rx |= BIT(port);
1580 } else {
1581 val |= PORT_TX_MIR;
1582 priv->mirror_tx |= BIT(port);
1583 }
1584 mt7530_write(priv, MT7530_PCR_P(port), val);
1585
1586 return 0;
1587}
1588
c288575f 1589static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
37feab60
DQ		 1590 struct dsa_mall_mirror_tc_entry *mirror)
1591{
1592 struct mt7530_priv *priv = ds->priv;
1593 u32 val;
1594
1595 val = mt7530_read(priv, MT7530_PCR_P(port));
1596 if (mirror->ingress) {
1597 val &= ~PORT_RX_MIR;
1598 priv->mirror_rx &= ~BIT(port);
1599 } else {
1600 val &= ~PORT_TX_MIR;
1601 priv->mirror_tx &= ~BIT(port);
1602 }
1603 mt7530_write(priv, MT7530_PCR_P(port), val);
1604
1605 if (!priv->mirror_rx && !priv->mirror_tx) {
c288575f
LC		 1606 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1607 val &= ~MT753X_MIRROR_EN(priv->id);
1608 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1609 }
1610}
1611
b8f126a8 1612static enum dsa_tag_protocol
4d776482
FF		 1613mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1614 enum dsa_tag_protocol mp)
b8f126a8
SW		 1615{
1616 struct mt7530_priv *priv = ds->priv;
1617
5ed4e3eb 1618 if (port != MT7530_CPU_PORT) {
b8f126a8
SW		 1619 dev_warn(priv->dev,
1620 "port not matched with tagging CPU port\n");
1621 return DSA_TAG_PROTO_NONE;
1622 } else {
1623 return DSA_TAG_PROTO_MTK;
1624 }
1625}
1626
429a0ede
DQ		 1627static inline u32
1628mt7530_gpio_to_bit(unsigned int offset)
1629{
1630 /* Map GPIO offset to register bit
1631 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2
1632 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5
1633 * [10: 8] port 2 LED 0..2 as GPIO 6..8
1634 * [14:12] port 3 LED 0..2 as GPIO 9..11
1635 * [18:16] port 4 LED 0..2 as GPIO 12..14
1636 */
1637 return BIT(offset + offset / 3);
1638}
1639
1640static int
1641mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1642{
1643 struct mt7530_priv *priv = gpiochip_get_data(gc);
1644 u32 bit = mt7530_gpio_to_bit(offset);
1645
1646 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1647}
1648
1649static void
1650mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1651{
1652 struct mt7530_priv *priv = gpiochip_get_data(gc);
1653 u32 bit = mt7530_gpio_to_bit(offset);
1654
1655 if (value)
1656 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1657 else
1658 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1659}
1660
1661static int
1662mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1663{
1664 struct mt7530_priv *priv = gpiochip_get_data(gc);
1665 u32 bit = mt7530_gpio_to_bit(offset);
1666
1667 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1668 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1669}
1670
1671static int
1672mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1673{
1674 struct mt7530_priv *priv = gpiochip_get_data(gc);
1675 u32 bit = mt7530_gpio_to_bit(offset);
1676
1677 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1678 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1679
1680 return 0;
1681}
1682
1683static int
1684mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1685{
1686 struct mt7530_priv *priv = gpiochip_get_data(gc);
1687 u32 bit = mt7530_gpio_to_bit(offset);
1688
1689 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1690
1691 if (value)
1692 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1693 else
1694 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1695
1696 mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1697
1698 return 0;
1699}
1700
1701static int
1702mt7530_setup_gpio(struct mt7530_priv *priv)
1703{
1704 struct device *dev = priv->dev;
1705 struct gpio_chip *gc;
1706
1707 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1708 if (!gc)
1709 return -ENOMEM;
1710
1711 mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1712 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1713 mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1714
1715 gc->label = "mt7530";
1716 gc->parent = dev;
1717 gc->owner = THIS_MODULE;
1718 gc->get_direction = mt7530_gpio_get_direction;
1719 gc->direction_input = mt7530_gpio_direction_input;
1720 gc->direction_output = mt7530_gpio_direction_output;
1721 gc->get = mt7530_gpio_get;
1722 gc->set = mt7530_gpio_set;
1723 gc->base = -1;
1724 gc->ngpio = 15;
1725 gc->can_sleep = true;
1726
1727 return devm_gpiochip_add_data(dev, gc, priv);
1728}
1729
b8f126a8
SW		 1730static int
1731mt7530_setup(struct dsa_switch *ds)
1732{
1733 struct mt7530_priv *priv = ds->priv;
38f790a8
RD		 1734 struct device_node *phy_node;
1735 struct device_node *mac_np;
b8f126a8 1736 struct mt7530_dummy_poll p;
38f790a8 1737 phy_interface_t interface;
ca366d6c
RD		 1738 struct device_node *dn;
1739 u32 id, val;
1740 int ret, i;
b8f126a8 1741
0abfd494 1742 /* The parent node of master netdev which holds the common system
b8f126a8
SW		 1743 * controller also is the container for two GMACs nodes representing
1744 * as two netdev instances.
1745 */
68bb8ea8 1746 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
771c8901 1747 ds->mtu_enforcement_ingress = true;
b8f126a8 1748
ddda1ac1 1749 if (priv->id == ID_MT7530) {
ddda1ac1
GU		 1750 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1751 ret = regulator_enable(priv->core_pwr);
1752 if (ret < 0) {
1753 dev_err(priv->dev,
1754 "Failed to enable core power: %d\n", ret);
1755 return ret;
1756 }
b8f126a8 1757
ddda1ac1
GU		 1758 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1759 ret = regulator_enable(priv->io_pwr);
1760 if (ret < 0) {
1761 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1762 ret);
1763 return ret;
1764 }
b8f126a8
SW		 1765 }
1766
1767 /* Reset whole chip through gpio pin or memory-mapped registers for
1768 * different type of hardware
1769 */
1770 if (priv->mcm) {
1771 reset_control_assert(priv->rstc);
1772 usleep_range(1000, 1100);
1773 reset_control_deassert(priv->rstc);
1774 } else {
1775 gpiod_set_value_cansleep(priv->reset, 0);
1776 usleep_range(1000, 1100);
1777 gpiod_set_value_cansleep(priv->reset, 1);
1778 }
1779
1780 /* Waiting for MT7530 got to stable */
1781 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1782 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1783 20, 1000000);
1784 if (ret < 0) {
1785 dev_err(priv->dev, "reset timeout\n");
1786 return ret;
1787 }
1788
1789 id = mt7530_read(priv, MT7530_CREV);
1790 id >>= CHIP_NAME_SHIFT;
1791 if (id != MT7530_ID) {
1792 dev_err(priv->dev, "chip %x can't be supported\n", id);
1793 return -ENODEV;
1794 }
1795
1796 /* Reset the switch through internal reset */
1797 mt7530_write(priv, MT7530_SYS_CTRL,
1798 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1799 SYS_CTRL_REG_RST);
1800
1801 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1802 val = mt7530_read(priv, MT7530_MHWTRAP);
1803 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1804 val |= MHWTRAP_MANUAL;
1805 mt7530_write(priv, MT7530_MHWTRAP, val);
1806
ca366d6c
RD		 1807 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1808
b8f126a8
SW		 1809 /* Enable and reset MIB counters */
1810 mt7530_mib_reset(ds);
1811
b8f126a8
SW		 1812 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1813 /* Disable forwarding by default on all ports */
1814 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1815 PCR_MATRIX_CLR);
1816
0ce0c3cd
AD		 1817 if (dsa_is_cpu_port(ds, i)) {
1818 ret = mt753x_cpu_port_enable(ds, i);
1819 if (ret)
1820 return ret;
1821 } else
75104db0 1822 mt7530_port_disable(ds, i);
e045124e
DQ		 1823
1824 /* Enable consistent egress tag */
1825 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1826 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
b8f126a8
SW		 1827 }
1828
38f790a8
RD		 1829 /* Setup port 5 */
1830 priv->p5_intf_sel = P5_DISABLED;
1831 interface = PHY_INTERFACE_MODE_NA;
1832
1833 if (!dsa_is_unused_port(ds, 5)) {
1834 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
0c65b2b9
AL		 1835 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
1836 if (ret && ret != -ENODEV)
1837 return ret;
38f790a8
RD		 1838 } else {
1839 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
1840 for_each_child_of_node(dn, mac_np) {
1841 if (!of_device_is_compatible(mac_np,
1842 "mediatek,eth-mac"))
1843 continue;
1844
1845 ret = of_property_read_u32(mac_np, "reg", &id);
1846 if (ret < 0 || id != 1)
1847 continue;
1848
1849 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
0452800f
CG		 1850 if (!phy_node)
1851 continue;
1852
38f790a8 1853 if (phy_node->parent == priv->dev->of_node->parent) {
0c65b2b9 1854 ret = of_get_phy_mode(mac_np, &interface);
8e4efd47
SP		 1855 if (ret && ret != -ENODEV) {
1856 of_node_put(mac_np);
0c65b2b9 1857 return ret;
8e4efd47 1858 }
38f790a8
RD		 1859 id = of_mdio_parse_addr(ds->dev, phy_node);
1860 if (id == 0)
1861 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
1862 if (id == 4)
1863 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
1864 }
8e4efd47 1865 of_node_put(mac_np);
38f790a8
RD		 1866 of_node_put(phy_node);
1867 break;
1868 }
1869 }
1870
429a0ede
DQ		 1871 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
1872 ret = mt7530_setup_gpio(priv);
1873 if (ret)
1874 return ret;
1875 }
1876
38f790a8
RD		 1877 mt7530_setup_port5(ds, interface);
1878
b8f126a8 1879 /* Flush the FDB table */
18bd5949 1880 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 1881 if (ret < 0)
1882 return ret;
1883
1884 return 0;
1885}
1886
c288575f
LC		 1887static int
1888mt7531_setup(struct dsa_switch *ds)
1889{
1890 struct mt7530_priv *priv = ds->priv;
1891 struct mt7530_dummy_poll p;
1892 u32 val, id;
1893 int ret, i;
1894
1895 /* Reset whole chip through gpio pin or memory-mapped registers for
1896 * different type of hardware
1897 */
1898 if (priv->mcm) {
1899 reset_control_assert(priv->rstc);
1900 usleep_range(1000, 1100);
1901 reset_control_deassert(priv->rstc);
1902 } else {
1903 gpiod_set_value_cansleep(priv->reset, 0);
1904 usleep_range(1000, 1100);
1905 gpiod_set_value_cansleep(priv->reset, 1);
1906 }
1907
1908 /* Waiting for MT7530 got to stable */
1909 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1910 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1911 20, 1000000);
1912 if (ret < 0) {
1913 dev_err(priv->dev, "reset timeout\n");
1914 return ret;
1915 }
1916
1917 id = mt7530_read(priv, MT7531_CREV);
1918 id >>= CHIP_NAME_SHIFT;
1919
1920 if (id != MT7531_ID) {
1921 dev_err(priv->dev, "chip %x can't be supported\n", id);
1922 return -ENODEV;
1923 }
1924
1925 /* Reset the switch through internal reset */
1926 mt7530_write(priv, MT7530_SYS_CTRL,
1927 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1928 SYS_CTRL_REG_RST);
1929
1930 if (mt7531_dual_sgmii_supported(priv)) {
1931 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
1932
1933 /* Let ds->slave_mii_bus be able to access external phy. */
1934 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
1935 MT7531_EXT_P_MDC_11);
1936 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
1937 MT7531_EXT_P_MDIO_12);
1938 } else {
1939 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
1940 }
1941 dev_dbg(ds->dev, "P5 support %s interface\n",
1942 p5_intf_modes(priv->p5_intf_sel));
1943
1944 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
1945 MT7531_GPIO0_INTERRUPT);
1946
1947 /* Let phylink decide the interface later. */
1948 priv->p5_interface = PHY_INTERFACE_MODE_NA;
1949 priv->p6_interface = PHY_INTERFACE_MODE_NA;
1950
1951 /* Enable PHY core PLL, since phy_device has not yet been created
1952 * provided for phy_[read,write]_mmd_indirect is called, we provide
1953 * our own mt7531_ind_mmd_phy_[read,write] to complete this
1954 * function.
1955 */
1956 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
1957 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
1958 val |= MT7531_PHY_PLL_BYPASS_MODE;
1959 val &= ~MT7531_PHY_PLL_OFF;
1960 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
1961 CORE_PLL_GROUP4, val);
1962
1963 /* BPDU to CPU port */
1964 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
1965 BIT(MT7530_CPU_PORT));
1966 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
1967 MT753X_BPDU_CPU_ONLY);
1968
1969 /* Enable and reset MIB counters */
1970 mt7530_mib_reset(ds);
1971
1972 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1973 /* Disable forwarding by default on all ports */
1974 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1975 PCR_MATRIX_CLR);
1976
1977 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
1978
0ce0c3cd
AD		 1979 if (dsa_is_cpu_port(ds, i)) {
1980 ret = mt753x_cpu_port_enable(ds, i);
1981 if (ret)
1982 return ret;
1983 } else
c288575f
LC		 1984 mt7530_port_disable(ds, i);
1985
1986 /* Enable consistent egress tag */
1987 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
1988 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
1989 }
1990
771c8901 1991 ds->mtu_enforcement_ingress = true;
c288575f
LC		 1992
1993 /* Flush the FDB table */
1994 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
1995 if (ret < 0)
1996 return ret;
1997
1998 return 0;
1999}
2000
88bdef8b
LC		 2001static bool
2002mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
2003 const struct phylink_link_state *state)
ca366d6c
RD		 2004{
2005 struct mt7530_priv *priv = ds->priv;
ca366d6c
RD		 2006
2007 switch (port) {
88bdef8b 2008 case 0 ... 4: /* Internal phy */
ca366d6c 2009 if (state->interface != PHY_INTERFACE_MODE_GMII)
88bdef8b 2010 return false;
ca366d6c 2011 break;
38f790a8 2012 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
38f790a8
RD		 2013 if (!phy_interface_mode_is_rgmii(state->interface) &&
2014 state->interface != PHY_INTERFACE_MODE_MII &&
2015 state->interface != PHY_INTERFACE_MODE_GMII)
88bdef8b
LC		 2016 return false;
2017 break;
2018 case 6: /* 1st cpu port */
2019 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
2020 state->interface != PHY_INTERFACE_MODE_TRGMII)
2021 return false;
2022 break;
2023 default:
2024 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2025 port);
2026 return false;
2027 }
2028
2029 return true;
2030}
2031
c288575f
LC		 2032static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
2033{
2034 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
2035}
2036
2037static bool
2038mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
2039 const struct phylink_link_state *state)
2040{
2041 struct mt7530_priv *priv = ds->priv;
2042
2043 switch (port) {
2044 case 0 ... 4: /* Internal phy */
2045 if (state->interface != PHY_INTERFACE_MODE_GMII)
2046 return false;
2047 break;
2048 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
2049 if (mt7531_is_rgmii_port(priv, port))
2050 return phy_interface_mode_is_rgmii(state->interface);
2051 fallthrough;
2052 case 6: /* 1st cpu port supports sgmii/8023z only */
2053 if (state->interface != PHY_INTERFACE_MODE_SGMII &&
2054 !phy_interface_mode_is_8023z(state->interface))
2055 return false;
2056 break;
2057 default:
2058 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
2059 port);
2060 return false;
2061 }
2062
2063 return true;
2064}
2065
88bdef8b
LC		 2066static bool
2067mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
2068 const struct phylink_link_state *state)
2069{
2070 struct mt7530_priv *priv = ds->priv;
2071
2072 return priv->info->phy_mode_supported(ds, port, state);
2073}
2074
2075static int
2076mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2077{
2078 struct mt7530_priv *priv = ds->priv;
2079
2080 return priv->info->pad_setup(ds, state->interface);
2081}
2082
2083static int
2084mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2085 phy_interface_t interface)
2086{
2087 struct mt7530_priv *priv = ds->priv;
2088
2089 /* Only need to setup port5. */
2090 if (port != 5)
2091 return 0;
2092
2093 mt7530_setup_port5(priv->ds, interface);
2094
2095 return 0;
2096}
2097
c288575f
LC		 2098static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2099 phy_interface_t interface,
2100 struct phy_device *phydev)
2101{
2102 u32 val;
2103
2104 if (!mt7531_is_rgmii_port(priv, port)) {
2105 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2106 port);
2107 return -EINVAL;
2108 }
2109
2110 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2111 val |= GP_CLK_EN;
2112 val &= ~GP_MODE_MASK;
2113 val |= GP_MODE(MT7531_GP_MODE_RGMII);
2114 val &= ~CLK_SKEW_IN_MASK;
2115 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2116 val &= ~CLK_SKEW_OUT_MASK;
2117 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2118 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2119
2120 /* Do not adjust rgmii delay when vendor phy driver presents. */
2121 if (!phydev || phy_driver_is_genphy(phydev)) {
2122 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2123 switch (interface) {
2124 case PHY_INTERFACE_MODE_RGMII:
2125 val |= TXCLK_NO_REVERSE;
2126 val |= RXCLK_NO_DELAY;
2127 break;
2128 case PHY_INTERFACE_MODE_RGMII_RXID:
2129 val |= TXCLK_NO_REVERSE;
2130 break;
2131 case PHY_INTERFACE_MODE_RGMII_TXID:
2132 val |= RXCLK_NO_DELAY;
2133 break;
2134 case PHY_INTERFACE_MODE_RGMII_ID:
2135 break;
2136 default:
2137 return -EINVAL;
2138 }
2139 }
2140 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2141
2142 return 0;
2143}
2144
2145static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
2146 unsigned long *supported)
2147{
2148 /* Port5 supports ethier RGMII or SGMII.
2149 * Port6 supports SGMII only.
2150 */
2151 switch (port) {
2152 case 5:
2153 if (mt7531_is_rgmii_port(priv, port))
2154 break;
2155 fallthrough;
2156 case 6:
2157 phylink_set(supported, 1000baseX_Full);
2158 phylink_set(supported, 2500baseX_Full);
2159 phylink_set(supported, 2500baseT_Full);
2160 }
2161}
2162
2163static void
2164mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
2165 unsigned int mode, phy_interface_t interface,
2166 int speed, int duplex)
2167{
2168 struct mt7530_priv *priv = ds->priv;
2169 unsigned int val;
2170
2171 /* For adjusting speed and duplex of SGMII force mode. */
2172 if (interface != PHY_INTERFACE_MODE_SGMII ||
2173 phylink_autoneg_inband(mode))
2174 return;
2175
2176 /* SGMII force mode setting */
2177 val = mt7530_read(priv, MT7531_SGMII_MODE(port));
2178 val &= ~MT7531_SGMII_IF_MODE_MASK;
2179
2180 switch (speed) {
2181 case SPEED_10:
2182 val |= MT7531_SGMII_FORCE_SPEED_10;
2183 break;
2184 case SPEED_100:
2185 val |= MT7531_SGMII_FORCE_SPEED_100;
2186 break;
2187 case SPEED_1000:
2188 val |= MT7531_SGMII_FORCE_SPEED_1000;
2189 break;
2190 }
2191
2192 /* MT7531 SGMII 1G force mode can only work in full duplex mode,
2193 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2194 */
2195 if ((speed == SPEED_10 || speed == SPEED_100) &&
2196 duplex != DUPLEX_FULL)
2197 val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
2198
2199 mt7530_write(priv, MT7531_SGMII_MODE(port), val);
2200}
2201
2202static bool mt753x_is_mac_port(u32 port)
2203{
2204 return (port == 5 || port == 6);
2205}
2206
2207static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
2208 phy_interface_t interface)
2209{
2210 u32 val;
2211
2212 if (!mt753x_is_mac_port(port))
2213 return -EINVAL;
2214
2215 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2216 MT7531_SGMII_PHYA_PWD);
2217
2218 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
2219 val &= ~MT7531_RG_TPHY_SPEED_MASK;
2220 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
2221 * encoding.
2222 */
2223 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
2224 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
2225 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
2226
2227 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2228
2229 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
2230 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
2231 */
2232 mt7530_rmw(priv, MT7531_SGMII_MODE(port),
2233 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
2234 MT7531_SGMII_FORCE_SPEED_1000);
2235
2236 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2237
2238 return 0;
2239}
2240
2241static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
2242 phy_interface_t interface)
2243{
2244 if (!mt753x_is_mac_port(port))
2245 return -EINVAL;
2246
2247 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
2248 MT7531_SGMII_PHYA_PWD);
2249
2250 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
2251 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
2252
2253 mt7530_set(priv, MT7531_SGMII_MODE(port),
2254 MT7531_SGMII_REMOTE_FAULT_DIS |
2255 MT7531_SGMII_SPEED_DUPLEX_AN);
2256
2257 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
2258 MT7531_SGMII_TX_CONFIG_MASK, 1);
2259
2260 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
2261
2262 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
2263
2264 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
2265
2266 return 0;
2267}
2268
2269static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
2270{
2271 struct mt7530_priv *priv = ds->priv;
2272 u32 val;
2273
2274 /* Only restart AN when AN is enabled */
2275 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2276 if (val & MT7531_SGMII_AN_ENABLE) {
2277 val |= MT7531_SGMII_AN_RESTART;
2278 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
2279 }
2280}
2281
2282static int
2283mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2284 phy_interface_t interface)
2285{
2286 struct mt7530_priv *priv = ds->priv;
2287 struct phy_device *phydev;
2288 struct dsa_port *dp;
2289
2290 if (!mt753x_is_mac_port(port)) {
2291 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2292 return -EINVAL;
2293 }
2294
2295 switch (interface) {
2296 case PHY_INTERFACE_MODE_RGMII:
2297 case PHY_INTERFACE_MODE_RGMII_ID:
2298 case PHY_INTERFACE_MODE_RGMII_RXID:
2299 case PHY_INTERFACE_MODE_RGMII_TXID:
2300 dp = dsa_to_port(ds, port);
2301 phydev = dp->slave->phydev;
2302 return mt7531_rgmii_setup(priv, port, interface, phydev);
2303 case PHY_INTERFACE_MODE_SGMII:
2304 return mt7531_sgmii_setup_mode_an(priv, port, interface);
2305 case PHY_INTERFACE_MODE_NA:
2306 case PHY_INTERFACE_MODE_1000BASEX:
2307 case PHY_INTERFACE_MODE_2500BASEX:
2308 if (phylink_autoneg_inband(mode))
2309 return -EINVAL;
2310
2311 return mt7531_sgmii_setup_mode_force(priv, port, interface);
2312 default:
2313 return -EINVAL;
2314 }
2315
2316 return -EINVAL;
2317}
2318
88bdef8b
LC		 2319static int
2320mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2321 const struct phylink_link_state *state)
2322{
2323 struct mt7530_priv *priv = ds->priv;
2324
2325 return priv->info->mac_port_config(ds, port, mode, state->interface);
2326}
2327
2328static void
2329mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2330 const struct phylink_link_state *state)
2331{
2332 struct mt7530_priv *priv = ds->priv;
2333 u32 mcr_cur, mcr_new;
2334
2335 if (!mt753x_phy_mode_supported(ds, port, state))
2336 goto unsupported;
2337
2338 switch (port) {
2339 case 0 ... 4: /* Internal phy */
2340 if (state->interface != PHY_INTERFACE_MODE_GMII)
2341 goto unsupported;
2342 break;
2343 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2344 if (priv->p5_interface == state->interface)
2345 break;
2346
2347 if (mt753x_mac_config(ds, port, mode, state) < 0)
2348 goto unsupported;
38f790a8 2349
c288575f
LC		 2350 if (priv->p5_intf_sel != P5_DISABLED)
2351 priv->p5_interface = state->interface;
38f790a8 2352 break;
ca366d6c
RD		 2353 case 6: /* 1st cpu port */
2354 if (priv->p6_interface == state->interface)
2355 break;
2356
88bdef8b 2357 mt753x_pad_setup(ds, state);
ca366d6c 2358
88bdef8b
LC		 2359 if (mt753x_mac_config(ds, port, mode, state) < 0)
2360 goto unsupported;
ca366d6c 2361
ca366d6c
RD		 2362 priv->p6_interface = state->interface;
2363 break;
2364 default:
88bdef8b
LC		 2365unsupported:
2366 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2367 __func__, phy_modes(state->interface), port);
ca366d6c
RD		 2368 return;
2369 }
2370
c288575f
LC		 2371 if (phylink_autoneg_inband(mode) &&
2372 state->interface != PHY_INTERFACE_MODE_SGMII) {
ca366d6c
RD		 2373 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
2374 __func__);
2375 return;
2376 }
2377
2378 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2379 mcr_new = mcr_cur;
1d01145f 2380 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
ca366d6c 2381 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
c288575f 2382 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
ca366d6c 2383
38f790a8
RD		 2384 /* Are we connected to external phy */
2385 if (port == 5 && dsa_is_user_port(ds, 5))
2386 mcr_new |= PMCR_EXT_PHY;
2387
ca366d6c
RD		 2388 if (mcr_new != mcr_cur)
2389 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2390}
2391
c288575f
LC		 2392static void
2393mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
2394{
2395 struct mt7530_priv *priv = ds->priv;
2396
2397 if (!priv->info->mac_pcs_an_restart)
2398 return;
2399
2400 priv->info->mac_pcs_an_restart(ds, port);
2401}
2402
2403static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
ca366d6c
RD		 2404 unsigned int mode,
2405 phy_interface_t interface)
2406{
2407 struct mt7530_priv *priv = ds->priv;
2408
1d01145f 2409 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
ca366d6c
RD		 2410}
2411
c288575f
LC		 2412static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
2413 unsigned int mode, phy_interface_t interface,
2414 int speed, int duplex)
2415{
2416 struct mt7530_priv *priv = ds->priv;
2417
2418 if (!priv->info->mac_pcs_link_up)
2419 return;
2420
2421 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2422}
2423
2424static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
ca366d6c
RD		 2425 unsigned int mode,
2426 phy_interface_t interface,
5b502a7b
RK		 2427 struct phy_device *phydev,
2428 int speed, int duplex,
2429 bool tx_pause, bool rx_pause)
ca366d6c
RD		 2430{
2431 struct mt7530_priv *priv = ds->priv;
1d01145f
RD		 2432 u32 mcr;
2433
c288575f
LC		 2434 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
2435
1d01145f
RD		 2436 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2437
c288575f
LC		 2438 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2439 * variants.
2440 */
2441 if (interface == PHY_INTERFACE_MODE_TRGMII ||
2442 (phy_interface_mode_is_8023z(interface))) {
2443 speed = SPEED_1000;
2444 duplex = DUPLEX_FULL;
2445 }
2446
1d01145f
RD		 2447 switch (speed) {
2448 case SPEED_1000:
2449 mcr |= PMCR_FORCE_SPEED_1000;
2450 break;
2451 case SPEED_100:
2452 mcr |= PMCR_FORCE_SPEED_100;
2453 break;
2454 }
2455 if (duplex == DUPLEX_FULL) {
2456 mcr |= PMCR_FORCE_FDX;
2457 if (tx_pause)
2458 mcr |= PMCR_TX_FC_EN;
2459 if (rx_pause)
2460 mcr |= PMCR_RX_FC_EN;
2461 }
ca366d6c 2462
1d01145f 2463 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
ca366d6c
RD		 2464}
2465
c288575f
LC		 2466static int
2467mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2468{
2469 struct mt7530_priv *priv = ds->priv;
2470 phy_interface_t interface;
2471 int speed;
0ce0c3cd 2472 int ret;
c288575f
LC		 2473
2474 switch (port) {
2475 case 5:
2476 if (mt7531_is_rgmii_port(priv, port))
2477 interface = PHY_INTERFACE_MODE_RGMII;
2478 else
2479 interface = PHY_INTERFACE_MODE_2500BASEX;
2480
2481 priv->p5_interface = interface;
2482 break;
2483 case 6:
2484 interface = PHY_INTERFACE_MODE_2500BASEX;
2485
2486 mt7531_pad_setup(ds, interface);
2487
2488 priv->p6_interface = interface;
2489 break;
0ce0c3cd
AD		 2490 default:
2491 return -EINVAL;
c288575f
LC		 2492 }
2493
2494 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2495 speed = SPEED_2500;
2496 else
2497 speed = SPEED_1000;
2498
0ce0c3cd
AD		 2499 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2500 if (ret)
2501 return ret;
c288575f
LC		 2502 mt7530_write(priv, MT7530_PMCR_P(port),
2503 PMCR_CPU_PORT_SETTING(priv->id));
2504 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2505 speed, DUPLEX_FULL, true, true);
2506
2507 return 0;
2508}
2509
88bdef8b
LC		 2510static void
2511mt7530_mac_port_validate(struct dsa_switch *ds, int port,
2512 unsigned long *supported)
2513{
2514 if (port == 5)
2515 phylink_set(supported, 1000baseX_Full);
2516}
2517
c288575f
LC		 2518static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
2519 unsigned long *supported)
2520{
2521 struct mt7530_priv *priv = ds->priv;
2522
2523 mt7531_sgmii_validate(priv, port, supported);
2524}
2525
88bdef8b
LC		 2526static void
2527mt753x_phylink_validate(struct dsa_switch *ds, int port,
2528 unsigned long *supported,
2529 struct phylink_link_state *state)
ca366d6c
RD		 2530{
2531 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
88bdef8b 2532 struct mt7530_priv *priv = ds->priv;
ca366d6c 2533
88bdef8b
LC		 2534 if (state->interface != PHY_INTERFACE_MODE_NA &&
2535 !mt753x_phy_mode_supported(ds, port, state)) {
ca366d6c
RD		 2536 linkmode_zero(supported);
2537 return;
2538 }
2539
2540 phylink_set_port_modes(mask);
ca366d6c 2541
c288575f
LC		 2542 if (state->interface != PHY_INTERFACE_MODE_TRGMII ||
2543 !phy_interface_mode_is_8023z(state->interface)) {
ca366d6c
RD		 2544 phylink_set(mask, 10baseT_Half);
2545 phylink_set(mask, 10baseT_Full);
2546 phylink_set(mask, 100baseT_Half);
2547 phylink_set(mask, 100baseT_Full);
88bdef8b 2548 phylink_set(mask, Autoneg);
38f790a8 2549 }
ca366d6c 2550
88bdef8b
LC		 2551 /* This switch only supports 1G full-duplex. */
2552 if (state->interface != PHY_INTERFACE_MODE_MII)
2553 phylink_set(mask, 1000baseT_Full);
2554
2555 priv->info->mac_port_validate(ds, port, mask);
2556
ca366d6c
RD		 2557 phylink_set(mask, Pause);
2558 phylink_set(mask, Asym_Pause);
2559
2560 linkmode_and(supported, supported, mask);
2561 linkmode_and(state->advertising, state->advertising, mask);
c288575f
LC		 2562
2563 /* We can only operate at 2500BaseX or 1000BaseX. If requested
2564 * to advertise both, only report advertising at 2500BaseX.
2565 */
2566 phylink_helper_basex_speed(state);
ca366d6c
RD		 2567}
2568
2569static int
2570mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
2571 struct phylink_link_state *state)
2572{
2573 struct mt7530_priv *priv = ds->priv;
2574 u32 pmsr;
2575
2576 if (port < 0 || port >= MT7530_NUM_PORTS)
2577 return -EINVAL;
2578
2579 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2580
2581 state->link = (pmsr & PMSR_LINK);
2582 state->an_complete = state->link;
2583 state->duplex = !!(pmsr & PMSR_DPX);
2584
2585 switch (pmsr & PMSR_SPEED_MASK) {
2586 case PMSR_SPEED_10:
2587 state->speed = SPEED_10;
2588 break;
2589 case PMSR_SPEED_100:
2590 state->speed = SPEED_100;
2591 break;
2592 case PMSR_SPEED_1000:
2593 state->speed = SPEED_1000;
2594 break;
2595 default:
2596 state->speed = SPEED_UNKNOWN;
2597 break;
2598 }
2599
2600 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2601 if (pmsr & PMSR_RX_FC)
2602 state->pause |= MLO_PAUSE_RX;
2603 if (pmsr & PMSR_TX_FC)
2604 state->pause |= MLO_PAUSE_TX;
2605
2606 return 1;
2607}
2608
c288575f
LC		 2609static int
2610mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
2611 struct phylink_link_state *state)
2612{
2613 u32 status, val;
2614 u16 config_reg;
2615
2616 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
2617 state->link = !!(status & MT7531_SGMII_LINK_STATUS);
2618 if (state->interface == PHY_INTERFACE_MODE_SGMII &&
2619 (status & MT7531_SGMII_AN_ENABLE)) {
2620 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
2621 config_reg = val >> 16;
2622
2623 switch (config_reg & LPA_SGMII_SPD_MASK) {
2624 case LPA_SGMII_1000:
2625 state->speed = SPEED_1000;
2626 break;
2627 case LPA_SGMII_100:
2628 state->speed = SPEED_100;
2629 break;
2630 case LPA_SGMII_10:
2631 state->speed = SPEED_10;
2632 break;
2633 default:
2634 dev_err(priv->dev, "invalid sgmii PHY speed\n");
2635 state->link = false;
2636 return -EINVAL;
2637 }
2638
2639 if (config_reg & LPA_SGMII_FULL_DUPLEX)
2640 state->duplex = DUPLEX_FULL;
2641 else
2642 state->duplex = DUPLEX_HALF;
2643 }
2644
2645 return 0;
2646}
2647
2648static int
2649mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
2650 struct phylink_link_state *state)
2651{
2652 struct mt7530_priv *priv = ds->priv;
2653
2654 if (state->interface == PHY_INTERFACE_MODE_SGMII)
2655 return mt7531_sgmii_pcs_get_state_an(priv, port, state);
2656
2657 return -EOPNOTSUPP;
2658}
2659
88bdef8b
LC		 2660static int
2661mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
2662 struct phylink_link_state *state)
2663{
2664 struct mt7530_priv *priv = ds->priv;
2665
2666 return priv->info->mac_port_get_state(ds, port, state);
2667}
2668
2669static int
2670mt753x_setup(struct dsa_switch *ds)
2671{
2672 struct mt7530_priv *priv = ds->priv;
2673
2674 return priv->info->sw_setup(ds);
2675}
2676
2677static int
2678mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)
2679{
2680 struct mt7530_priv *priv = ds->priv;
2681
2682 return priv->info->phy_read(ds, port, regnum);
2683}
2684
2685static int
2686mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2687{
2688 struct mt7530_priv *priv = ds->priv;
2689
2690 return priv->info->phy_write(ds, port, regnum, val);
2691}
2692
d78d6776 2693static const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8 2694 .get_tag_protocol = mtk_get_tag_protocol,
88bdef8b 2695 .setup = mt753x_setup,
b8f126a8 2696 .get_strings = mt7530_get_strings,
88bdef8b
LC		 2697 .phy_read = mt753x_phy_read,
2698 .phy_write = mt753x_phy_write,
b8f126a8
SW		 2699 .get_ethtool_stats = mt7530_get_ethtool_stats,
2700 .get_sset_count = mt7530_get_sset_count,
ea6d5c92 2701 .set_ageing_time = mt7530_set_ageing_time,
b8f126a8
SW		 2702 .port_enable = mt7530_port_enable,
2703 .port_disable = mt7530_port_disable,
9470174e
DQ		 2704 .port_change_mtu = mt7530_port_change_mtu,
2705 .port_max_mtu = mt7530_port_max_mtu,
b8f126a8
SW		 2706 .port_stp_state_set = mt7530_stp_state_set,
2707 .port_bridge_join = mt7530_port_bridge_join,
2708 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 2709 .port_fdb_add = mt7530_port_fdb_add,
2710 .port_fdb_del = mt7530_port_fdb_del,
2711 .port_fdb_dump = mt7530_port_fdb_dump,
83163f7d 2712 .port_vlan_filtering = mt7530_port_vlan_filtering,
83163f7d
SW		 2713 .port_vlan_add = mt7530_port_vlan_add,
2714 .port_vlan_del = mt7530_port_vlan_del,
c288575f
LC		 2715 .port_mirror_add = mt753x_port_mirror_add,
2716 .port_mirror_del = mt753x_port_mirror_del,
88bdef8b
LC		 2717 .phylink_validate = mt753x_phylink_validate,
2718 .phylink_mac_link_state = mt753x_phylink_mac_link_state,
2719 .phylink_mac_config = mt753x_phylink_mac_config,
c288575f
LC		 2720 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
2721 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
2722 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
b8f126a8
SW		 2723};
2724
88bdef8b
LC		 2725static const struct mt753x_info mt753x_table[] = {
2726 [ID_MT7621] = {
2727 .id = ID_MT7621,
2728 .sw_setup = mt7530_setup,
2729 .phy_read = mt7530_phy_read,
2730 .phy_write = mt7530_phy_write,
2731 .pad_setup = mt7530_pad_clk_setup,
2732 .phy_mode_supported = mt7530_phy_mode_supported,
2733 .mac_port_validate = mt7530_mac_port_validate,
2734 .mac_port_get_state = mt7530_phylink_mac_link_state,
2735 .mac_port_config = mt7530_mac_config,
2736 },
2737 [ID_MT7530] = {
2738 .id = ID_MT7530,
2739 .sw_setup = mt7530_setup,
2740 .phy_read = mt7530_phy_read,
2741 .phy_write = mt7530_phy_write,
2742 .pad_setup = mt7530_pad_clk_setup,
2743 .phy_mode_supported = mt7530_phy_mode_supported,
2744 .mac_port_validate = mt7530_mac_port_validate,
2745 .mac_port_get_state = mt7530_phylink_mac_link_state,
2746 .mac_port_config = mt7530_mac_config,
2747 },
c288575f
LC		 2748 [ID_MT7531] = {
2749 .id = ID_MT7531,
2750 .sw_setup = mt7531_setup,
2751 .phy_read = mt7531_ind_phy_read,
2752 .phy_write = mt7531_ind_phy_write,
2753 .pad_setup = mt7531_pad_setup,
2754 .cpu_port_config = mt7531_cpu_port_config,
2755 .phy_mode_supported = mt7531_phy_mode_supported,
2756 .mac_port_validate = mt7531_mac_port_validate,
2757 .mac_port_get_state = mt7531_phylink_mac_link_state,
2758 .mac_port_config = mt7531_mac_config,
2759 .mac_pcs_an_restart = mt7531_sgmii_restart_an,
2760 .mac_pcs_link_up = mt7531_sgmii_link_up_force,
2761 },
88bdef8b
LC		 2762};
2763
ddda1ac1 2764static const struct of_device_id mt7530_of_match[] = {
88bdef8b
LC		 2765 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
2766 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
c288575f 2767 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
ddda1ac1
GU		 2768 { /* sentinel */ },
2769};
2770MODULE_DEVICE_TABLE(of, mt7530_of_match);
2771
b8f126a8
SW		 2772static int
2773mt7530_probe(struct mdio_device *mdiodev)
2774{
2775 struct mt7530_priv *priv;
2776 struct device_node *dn;
2777
2778 dn = mdiodev->dev.of_node;
2779
2780 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2781 if (!priv)
2782 return -ENOMEM;
2783
7e99e347 2784 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
b8f126a8
SW		 2785 if (!priv->ds)
2786 return -ENOMEM;
2787
7e99e347
VD		 2788 priv->ds->dev = &mdiodev->dev;
2789 priv->ds->num_ports = DSA_MAX_PORTS;
2790
b8f126a8
SW		 2791 /* Use medatek,mcm property to distinguish hardware type that would
2792 * casues a little bit differences on power-on sequence.
2793 */
2794 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
2795 if (priv->mcm) {
2796 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
2797
2798 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
2799 if (IS_ERR(priv->rstc)) {
2800 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
2801 return PTR_ERR(priv->rstc);
2802 }
2803 }
2804
ddda1ac1
GU		 2805 /* Get the hardware identifier from the devicetree node.
2806 * We will need it for some of the clock and regulator setup.
2807 */
88bdef8b
LC		 2808 priv->info = of_device_get_match_data(&mdiodev->dev);
2809 if (!priv->info)
2810 return -EINVAL;
2811
2812 /* Sanity check if these required device operations are filled
2813 * properly.
2814 */
2815 if (!priv->info->sw_setup || !priv->info->pad_setup ||
2816 !priv->info->phy_read || !priv->info->phy_write ||
2817 !priv->info->phy_mode_supported ||
2818 !priv->info->mac_port_validate ||
2819 !priv->info->mac_port_get_state || !priv->info->mac_port_config)
2820 return -EINVAL;
2821
2822 priv->id = priv->info->id;
b8f126a8 2823
ddda1ac1
GU		 2824 if (priv->id == ID_MT7530) {
2825 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
2826 if (IS_ERR(priv->core_pwr))
2827 return PTR_ERR(priv->core_pwr);
2828
2829 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
2830 if (IS_ERR(priv->io_pwr))
2831 return PTR_ERR(priv->io_pwr);
2832 }
b8f126a8
SW		 2833
2834 /* Not MCM that indicates switch works as the remote standalone
2835 * integrated circuit so the GPIO pin would be used to complete
2836 * the reset, otherwise memory-mapped register accessing used
2837 * through syscon provides in the case of MCM.
2838 */
2839 if (!priv->mcm) {
2840 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
2841 GPIOD_OUT_LOW);
2842 if (IS_ERR(priv->reset)) {
2843 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
2844 return PTR_ERR(priv->reset);
2845 }
2846 }
2847
2848 priv->bus = mdiodev->bus;
2849 priv->dev = &mdiodev->dev;
2850 priv->ds->priv = priv;
2851 priv->ds->ops = &mt7530_switch_ops;
2852 mutex_init(&priv->reg_mutex);
2853 dev_set_drvdata(&mdiodev->dev, priv);
2854
23c9ee49 2855 return dsa_register_switch(priv->ds);
b8f126a8
SW		 2856}
2857
2858static void
2859mt7530_remove(struct mdio_device *mdiodev)
2860{
2861 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
2862 int ret = 0;
2863
2864 ret = regulator_disable(priv->core_pwr);
2865 if (ret < 0)
2866 dev_err(priv->dev,
2867 "Failed to disable core power: %d\n", ret);
2868
2869 ret = regulator_disable(priv->io_pwr);
2870 if (ret < 0)
2871 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
2872 ret);
2873
2874 dsa_unregister_switch(priv->ds);
2875 mutex_destroy(&priv->reg_mutex);
2876}
2877
b8f126a8
SW		 2878static struct mdio_driver mt7530_mdio_driver = {
2879 .probe = mt7530_probe,
2880 .remove = mt7530_remove,
2881 .mdiodrv.driver = {
2882 .name = "mt7530",
2883 .of_match_table = mt7530_of_match,
2884 },
2885};
2886
2887mdio_module_driver(mt7530_mdio_driver);
2888
2889MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
2890MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
2891MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)