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net: dsa: mt7530: move p5_intf_modes() function to mt7530.c
[linux-block.git] / drivers / net / dsa / mt7530.c
CommitLineData
1802d0be 1// SPDX-License-Identifier: GPL-2.0-only
b8f126a8
SW		 2/*
3 * Mediatek MT7530 DSA Switch driver
4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
b8f126a8
SW		 5 */
6#include <linux/etherdevice.h>
7#include <linux/if_bridge.h>
8#include <linux/iopoll.h>
9#include <linux/mdio.h>
10#include <linux/mfd/syscon.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
ba751e28 13#include <linux/of_irq.h>
b8f126a8
SW		 14#include <linux/of_mdio.h>
15#include <linux/of_net.h>
16#include <linux/of_platform.h>
5b89aeae 17#include <linux/pcs/pcs-mtk-lynxi.h>
ca366d6c 18#include <linux/phylink.h>
b8f126a8
SW		 19#include <linux/regmap.h>
20#include <linux/regulator/consumer.h>
21#include <linux/reset.h>
eb976a55 22#include <linux/gpio/consumer.h>
429a0ede 23#include <linux/gpio/driver.h>
b8f126a8 24#include <net/dsa.h>
b8f126a8
SW		 25
26#include "mt7530.h"
27
cbd1f243
RKO		 28static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
29{
30 return container_of(pcs, struct mt753x_pcs, pcs);
31}
32
b8f126a8
SW		 33/* String, offset, and register size in bytes if different from 4 bytes */
34static const struct mt7530_mib_desc mt7530_mib[] = {
35 MIB_DESC(1, 0x00, "TxDrop"),
36 MIB_DESC(1, 0x04, "TxCrcErr"),
37 MIB_DESC(1, 0x08, "TxUnicast"),
38 MIB_DESC(1, 0x0c, "TxMulticast"),
39 MIB_DESC(1, 0x10, "TxBroadcast"),
40 MIB_DESC(1, 0x14, "TxCollision"),
41 MIB_DESC(1, 0x18, "TxSingleCollision"),
42 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
43 MIB_DESC(1, 0x20, "TxDeferred"),
44 MIB_DESC(1, 0x24, "TxLateCollision"),
45 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
46 MIB_DESC(1, 0x2c, "TxPause"),
47 MIB_DESC(1, 0x30, "TxPktSz64"),
48 MIB_DESC(1, 0x34, "TxPktSz65To127"),
49 MIB_DESC(1, 0x38, "TxPktSz128To255"),
50 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
51 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
52 MIB_DESC(1, 0x44, "Tx1024ToMax"),
53 MIB_DESC(2, 0x48, "TxBytes"),
54 MIB_DESC(1, 0x60, "RxDrop"),
55 MIB_DESC(1, 0x64, "RxFiltering"),
aff51c5d 56 MIB_DESC(1, 0x68, "RxUnicast"),
b8f126a8
SW		 57 MIB_DESC(1, 0x6c, "RxMulticast"),
58 MIB_DESC(1, 0x70, "RxBroadcast"),
59 MIB_DESC(1, 0x74, "RxAlignErr"),
60 MIB_DESC(1, 0x78, "RxCrcErr"),
61 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
62 MIB_DESC(1, 0x80, "RxFragErr"),
63 MIB_DESC(1, 0x84, "RxOverSzErr"),
64 MIB_DESC(1, 0x88, "RxJabberErr"),
65 MIB_DESC(1, 0x8c, "RxPause"),
66 MIB_DESC(1, 0x90, "RxPktSz64"),
67 MIB_DESC(1, 0x94, "RxPktSz65To127"),
68 MIB_DESC(1, 0x98, "RxPktSz128To255"),
69 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
70 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
71 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
72 MIB_DESC(2, 0xa8, "RxBytes"),
73 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
74 MIB_DESC(1, 0xb4, "RxIngressDrop"),
75 MIB_DESC(1, 0xb8, "RxArlDrop"),
76};
77
4732315c
IL		 78/* Since phy_device has not yet been created and
79 * phy_{read,write}_mmd_indirect is not available, we provide our own
80 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
81 * to complete this function.
82 */
b8f126a8
SW		 83static int
84core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
85{
86 struct mii_bus *bus = priv->bus;
87 int value, ret;
88
89 /* Write the desired MMD Devad */
90 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
91 if (ret < 0)
92 goto err;
93
94 /* Write the desired MMD register address */
95 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
96 if (ret < 0)
97 goto err;
98
99 /* Select the Function : DATA with no post increment */
100 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
101 if (ret < 0)
102 goto err;
103
104 /* Read the content of the MMD's selected register */
105 value = bus->read(bus, 0, MII_MMD_DATA);
106
107 return value;
108err:
109 dev_err(&bus->dev, "failed to read mmd register\n");
110
111 return ret;
112}
113
114static int
115core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
116 int devad, u32 data)
117{
118 struct mii_bus *bus = priv->bus;
119 int ret;
120
121 /* Write the desired MMD Devad */
122 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
123 if (ret < 0)
124 goto err;
125
126 /* Write the desired MMD register address */
127 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
128 if (ret < 0)
129 goto err;
130
131 /* Select the Function : DATA with no post increment */
132 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
133 if (ret < 0)
134 goto err;
135
136 /* Write the data into MMD's selected register */
137 ret = bus->write(bus, 0, MII_MMD_DATA, data);
138err:
139 if (ret < 0)
140 dev_err(&bus->dev,
141 "failed to write mmd register\n");
142 return ret;
143}
144
145static void
1557c679 146mt7530_mutex_lock(struct mt7530_priv *priv)
b8f126a8 147{
1557c679
DG		 148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
149}
b8f126a8 150
1557c679
DG		 151static void
152mt7530_mutex_unlock(struct mt7530_priv *priv)
153{
154 mutex_unlock(&priv->bus->mdio_lock);
155}
156
157static void
158core_write(struct mt7530_priv *priv, u32 reg, u32 val)
159{
160 mt7530_mutex_lock(priv);
b8f126a8
SW		 161
162 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
163
1557c679 164 mt7530_mutex_unlock(priv);
b8f126a8
SW		 165}
166
167static void
168core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
169{
b8f126a8
SW		 170 u32 val;
171
1557c679 172 mt7530_mutex_lock(priv);
b8f126a8
SW		 173
174 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
175 val &= ~mask;
176 val |= set;
177 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
178
1557c679 179 mt7530_mutex_unlock(priv);
b8f126a8
SW		 180}
181
182static void
183core_set(struct mt7530_priv *priv, u32 reg, u32 val)
184{
185 core_rmw(priv, reg, 0, val);
186}
187
188static void
189core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
190{
191 core_rmw(priv, reg, val, 0);
192}
193
194static int
a08c0455 195mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
b8f126a8 196{
a08c0455 197 struct mii_bus *bus = context;
b8f126a8
SW		 198 u16 page, r, lo, hi;
199 int ret;
200
201 page = (reg >> 6) & 0x3ff;
202 r = (reg >> 2) & 0xf;
203 lo = val & 0xffff;
204 hi = val >> 16;
205
206 /* MT7530 uses 31 as the pseudo port */
207 ret = bus->write(bus, 0x1f, 0x1f, page);
208 if (ret < 0)
a08c0455 209 return ret;
b8f126a8
SW		 210
211 ret = bus->write(bus, 0x1f, r, lo);
212 if (ret < 0)
a08c0455 213 return ret;
b8f126a8
SW		 214
215 ret = bus->write(bus, 0x1f, 0x10, hi);
a08c0455
DG		 216 return ret;
217}
218
219static int
220mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
221{
222 int ret;
223
224 ret = regmap_write(priv->regmap, reg, val);
225
b8f126a8 226 if (ret < 0)
a08c0455 227 dev_err(priv->dev,
b8f126a8 228 "failed to write mt7530 register\n");
a08c0455 229
b8f126a8
SW		 230 return ret;
231}
232
a08c0455
DG		 233static int
234mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
b8f126a8 235{
a08c0455 236 struct mii_bus *bus = context;
b8f126a8
SW		 237 u16 page, r, lo, hi;
238 int ret;
239
240 page = (reg >> 6) & 0x3ff;
241 r = (reg >> 2) & 0xf;
242
243 /* MT7530 uses 31 as the pseudo port */
244 ret = bus->write(bus, 0x1f, 0x1f, page);
a08c0455
DG		 245 if (ret < 0)
246 return ret;
247
248 lo = bus->read(bus, 0x1f, r);
249 hi = bus->read(bus, 0x1f, 0x10);
250
251 *val = (hi << 16) | (lo & 0xffff);
252
253 return 0;
254}
255
256static u32
257mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
258{
259 int ret;
260 u32 val;
261
262 ret = regmap_read(priv->regmap, reg, &val);
263 if (ret) {
b6f56cdd 264 WARN_ON_ONCE(1);
a08c0455 265 dev_err(priv->dev,
b8f126a8 266 "failed to read mt7530 register\n");
b6f56cdd 267 return 0;
b8f126a8
SW		 268 }
269
a08c0455 270 return val;
b8f126a8
SW		 271}
272
273static void
274mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
275{
1557c679 276 mt7530_mutex_lock(priv);
b8f126a8
SW		 277
278 mt7530_mii_write(priv, reg, val);
279
1557c679 280 mt7530_mutex_unlock(priv);
b8f126a8
SW		 281}
282
c288575f
LC		 283static u32
284_mt7530_unlocked_read(struct mt7530_dummy_poll *p)
285{
286 return mt7530_mii_read(p->priv, p->reg);
287}
288
b8f126a8
SW		 289static u32
290_mt7530_read(struct mt7530_dummy_poll *p)
291{
b8f126a8
SW		 292 u32 val;
293
1557c679 294 mt7530_mutex_lock(p->priv);
b8f126a8
SW		 295
296 val = mt7530_mii_read(p->priv, p->reg);
297
1557c679 298 mt7530_mutex_unlock(p->priv);
b8f126a8
SW		 299
300 return val;
301}
302
303static u32
304mt7530_read(struct mt7530_priv *priv, u32 reg)
305{
306 struct mt7530_dummy_poll p;
307
308 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
309 return _mt7530_read(&p);
310}
311
312static void
313mt7530_rmw(struct mt7530_priv *priv, u32 reg,
314 u32 mask, u32 set)
315{
1557c679 316 mt7530_mutex_lock(priv);
b8f126a8 317
a08c0455 318 regmap_update_bits(priv->regmap, reg, mask, set);
b8f126a8 319
1557c679 320 mt7530_mutex_unlock(priv);
b8f126a8
SW		 321}
322
323static void
324mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
325{
a08c0455 326 mt7530_rmw(priv, reg, val, val);
b8f126a8
SW		 327}
328
329static void
330mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
331{
332 mt7530_rmw(priv, reg, val, 0);
333}
334
335static int
336mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
337{
338 u32 val;
339 int ret;
340 struct mt7530_dummy_poll p;
341
342 /* Set the command operating upon the MAC address entries */
343 val = ATC_BUSY | ATC_MAT(0) | cmd;
344 mt7530_write(priv, MT7530_ATC, val);
345
346 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
347 ret = readx_poll_timeout(_mt7530_read, &p, val,
348 !(val & ATC_BUSY), 20, 20000);
349 if (ret < 0) {
350 dev_err(priv->dev, "reset timeout\n");
351 return ret;
352 }
353
354 /* Additional sanity for read command if the specified
355 * entry is invalid
356 */
357 val = mt7530_read(priv, MT7530_ATC);
358 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
359 return -EINVAL;
360
361 if (rsp)
362 *rsp = val;
363
364 return 0;
365}
366
367static void
368mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
369{
370 u32 reg[3];
371 int i;
372
373 /* Read from ARL table into an array */
374 for (i = 0; i < 3; i++) {
375 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
376
377 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
378 __func__, __LINE__, i, reg[i]);
379 }
380
381 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
382 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
383 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
384 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
385 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
386 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
387 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
388 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
389 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
390 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
391}
392
393static void
394mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
395 u8 port_mask, const u8 *mac,
396 u8 aging, u8 type)
397{
398 u32 reg[3] = { 0 };
399 int i;
400
401 reg[1] |= vid & CVID_MASK;
73c447ca
DQ		 402 reg[1] |= ATA2_IVL;
403 reg[1] |= ATA2_FID(FID_BRIDGED);
b8f126a8
SW		 404 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
405 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
406 /* STATIC_ENT indicate that entry is static wouldn't
407 * be aged out and STATIC_EMP specified as erasing an
408 * entry
409 */
410 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
411 reg[1] |= mac[5] << MAC_BYTE_5;
412 reg[1] |= mac[4] << MAC_BYTE_4;
413 reg[0] |= mac[3] << MAC_BYTE_3;
414 reg[0] |= mac[2] << MAC_BYTE_2;
415 reg[0] |= mac[1] << MAC_BYTE_1;
416 reg[0] |= mac[0] << MAC_BYTE_0;
417
418 /* Write array into the ARL table */
419 for (i = 0; i < 3; i++)
420 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
421}
422
c8b8a3c6
VO		 423/* Set up switch core clock for MT7530 */
424static void mt7530_pll_setup(struct mt7530_priv *priv)
425{
8f058a6e
AÜ		 426 /* Disable core clock */
427 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
428
c8b8a3c6
VO		 429 /* Disable PLL */
430 core_write(priv, CORE_GSWPLL_GRP1, 0);
431
432 /* Set core clock into 500Mhz */
433 core_write(priv, CORE_GSWPLL_GRP2,
434 RG_GSWPLL_POSDIV_500M(1) |
435 RG_GSWPLL_FBKDIV_500M(25));
436
437 /* Enable PLL */
438 core_write(priv, CORE_GSWPLL_GRP1,
439 RG_GSWPLL_EN_PRE |
440 RG_GSWPLL_POSDIV_200M(2) |
441 RG_GSWPLL_FBKDIV_200M(32));
8f058a6e
AÜ		 442
443 udelay(20);
444
445 /* Enable core clock */
446 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
c8b8a3c6
VO		 447}
448
fdcc8ccd 449/* Setup port 6 interface mode and TRGMII TX circuit */
b8f126a8 450static int
88bdef8b 451mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
b8f126a8
SW		 452{
453 struct mt7530_priv *priv = ds->priv;
fdcc8ccd 454 u32 ncpo1, ssc_delta, trgint, xtal;
7ef6f6f8
RD		 455
456 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
457
458 if (xtal == HWTRAP_XTAL_20MHZ) {
459 dev_err(priv->dev,
460 "%s: MT7530 with a 20MHz XTAL is not supported!\n",
461 __func__);
462 return -EINVAL;
463 }
b8f126a8 464
88bdef8b 465 switch (interface) {
b8f126a8
SW		 466 case PHY_INTERFACE_MODE_RGMII:
467 trgint = 0;
b8f126a8
SW		 468 break;
469 case PHY_INTERFACE_MODE_TRGMII:
470 trgint = 1;
407b508b
AÜ		 471 if (xtal == HWTRAP_XTAL_25MHZ)
472 ssc_delta = 0x57;
473 else
474 ssc_delta = 0x87;
7ef6f6f8
RD		 475 if (priv->id == ID_MT7621) {
476 /* PLL frequency: 150MHz: 1.2GBit */
477 if (xtal == HWTRAP_XTAL_40MHZ)
478 ncpo1 = 0x0780;
479 if (xtal == HWTRAP_XTAL_25MHZ)
480 ncpo1 = 0x0a00;
481 } else { /* PLL frequency: 250MHz: 2.0Gbit */
482 if (xtal == HWTRAP_XTAL_40MHZ)
483 ncpo1 = 0x0c80;
484 if (xtal == HWTRAP_XTAL_25MHZ)
485 ncpo1 = 0x1400;
486 }
b8f126a8
SW		 487 break;
488 default:
88bdef8b
LC		 489 dev_err(priv->dev, "xMII interface %d not supported\n",
490 interface);
b8f126a8
SW		 491 return -EINVAL;
492 }
493
494 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
495 P6_INTF_MODE(trgint));
496
0b086d76 497 if (trgint) {
8f058a6e
AÜ		 498 /* Disable the MT7530 TRGMII clocks */
499 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
0b086d76
AÜ		 500
501 /* Setup the MT7530 TRGMII Tx Clock */
502 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
503 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
504 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
505 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
506 core_write(priv, CORE_PLL_GROUP4,
507 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
508 RG_SYSPLL_BIAS_LPF_EN);
509 core_write(priv, CORE_PLL_GROUP2,
510 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
511 RG_SYSPLL_POSDIV(1));
512 core_write(priv, CORE_PLL_GROUP7,
513 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
514 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
515
8f058a6e
AÜ		 516 /* Enable the MT7530 TRGMII clocks */
517 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
0b086d76
AÜ		 518 }
519
b8f126a8
SW		 520 return 0;
521}
522
c288575f
LC		 523static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
524{
525 u32 val;
526
527 val = mt7530_read(priv, MT7531_TOP_SIG_SR);
528
529 return (val & PAD_DUAL_SGMII_EN) != 0;
530}
531
532static int
533mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
534{
42bc4faf
AC		 535 return 0;
536}
537
538static void
539mt7531_pll_setup(struct mt7530_priv *priv)
540{
c288575f
LC		 541 u32 top_sig;
542 u32 hwstrap;
543 u32 xtal;
544 u32 val;
545
546 if (mt7531_dual_sgmii_supported(priv))
42bc4faf 547 return;
c288575f
LC		 548
549 val = mt7530_read(priv, MT7531_CREV);
550 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
551 hwstrap = mt7530_read(priv, MT7531_HWTRAP);
552 if ((val & CHIP_REV_M) > 0)
553 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
554 HWTRAP_XTAL_FSEL_25MHZ;
555 else
556 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
557
558 /* Step 1 : Disable MT7531 COREPLL */
559 val = mt7530_read(priv, MT7531_PLLGP_EN);
560 val &= ~EN_COREPLL;
561 mt7530_write(priv, MT7531_PLLGP_EN, val);
562
563 /* Step 2: switch to XTAL output */
564 val = mt7530_read(priv, MT7531_PLLGP_EN);
565 val |= SW_CLKSW;
566 mt7530_write(priv, MT7531_PLLGP_EN, val);
567
568 val = mt7530_read(priv, MT7531_PLLGP_CR0);
569 val &= ~RG_COREPLL_EN;
570 mt7530_write(priv, MT7531_PLLGP_CR0, val);
571
572 /* Step 3: disable PLLGP and enable program PLLGP */
573 val = mt7530_read(priv, MT7531_PLLGP_EN);
574 val |= SW_PLLGP;
575 mt7530_write(priv, MT7531_PLLGP_EN, val);
576
577 /* Step 4: program COREPLL output frequency to 500MHz */
578 val = mt7530_read(priv, MT7531_PLLGP_CR0);
579 val &= ~RG_COREPLL_POSDIV_M;
580 val |= 2 << RG_COREPLL_POSDIV_S;
581 mt7530_write(priv, MT7531_PLLGP_CR0, val);
582 usleep_range(25, 35);
583
584 switch (xtal) {
585 case HWTRAP_XTAL_FSEL_25MHZ:
586 val = mt7530_read(priv, MT7531_PLLGP_CR0);
587 val &= ~RG_COREPLL_SDM_PCW_M;
588 val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
589 mt7530_write(priv, MT7531_PLLGP_CR0, val);
590 break;
591 case HWTRAP_XTAL_FSEL_40MHZ:
592 val = mt7530_read(priv, MT7531_PLLGP_CR0);
593 val &= ~RG_COREPLL_SDM_PCW_M;
594 val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
595 mt7530_write(priv, MT7531_PLLGP_CR0, val);
596 break;
0e8c266c 597 }
c288575f
LC		 598
599 /* Set feedback divide ratio update signal to high */
600 val = mt7530_read(priv, MT7531_PLLGP_CR0);
601 val |= RG_COREPLL_SDM_PCW_CHG;
602 mt7530_write(priv, MT7531_PLLGP_CR0, val);
603 /* Wait for at least 16 XTAL clocks */
604 usleep_range(10, 20);
605
606 /* Step 5: set feedback divide ratio update signal to low */
607 val = mt7530_read(priv, MT7531_PLLGP_CR0);
608 val &= ~RG_COREPLL_SDM_PCW_CHG;
609 mt7530_write(priv, MT7531_PLLGP_CR0, val);
610
611 /* Enable 325M clock for SGMII */
612 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
613
614 /* Enable 250SSC clock for RGMII */
615 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
616
617 /* Step 6: Enable MT7531 PLL */
618 val = mt7530_read(priv, MT7531_PLLGP_CR0);
619 val |= RG_COREPLL_EN;
620 mt7530_write(priv, MT7531_PLLGP_CR0, val);
621
622 val = mt7530_read(priv, MT7531_PLLGP_EN);
623 val |= EN_COREPLL;
624 mt7530_write(priv, MT7531_PLLGP_EN, val);
625 usleep_range(25, 35);
c288575f
LC		 626}
627
b8f126a8
SW		 628static void
629mt7530_mib_reset(struct dsa_switch *ds)
630{
631 struct mt7530_priv *priv = ds->priv;
632
633 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
634 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
635}
636
defa2e54 637static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)
b8f126a8 638{
b8f126a8
SW		 639 return mdiobus_read_nested(priv->bus, port, regnum);
640}
641
defa2e54
AL		 642static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum,
643 u16 val)
b8f126a8 644{
b8f126a8
SW		 645 return mdiobus_write_nested(priv->bus, port, regnum, val);
646}
647
defa2e54
AL		 648static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port,
649 int devad, int regnum)
650{
651 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum);
652}
653
654static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad,
655 int regnum, u16 val)
656{
657 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val);
658}
659
c288575f
LC		 660static int
661mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
662 int regnum)
663{
c288575f
LC		 664 struct mt7530_dummy_poll p;
665 u32 reg, val;
666 int ret;
667
668 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
669
1557c679 670 mt7530_mutex_lock(priv);
c288575f
LC		 671
672 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
673 !(val & MT7531_PHY_ACS_ST), 20, 100000);
674 if (ret < 0) {
675 dev_err(priv->dev, "poll timeout\n");
676 goto out;
677 }
678
679 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
680 MT7531_MDIO_DEV_ADDR(devad) | regnum;
681 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
682
683 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
684 !(val & MT7531_PHY_ACS_ST), 20, 100000);
685 if (ret < 0) {
686 dev_err(priv->dev, "poll timeout\n");
687 goto out;
688 }
689
690 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
691 MT7531_MDIO_DEV_ADDR(devad);
692 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
693
694 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
695 !(val & MT7531_PHY_ACS_ST), 20, 100000);
696 if (ret < 0) {
697 dev_err(priv->dev, "poll timeout\n");
698 goto out;
699 }
700
701 ret = val & MT7531_MDIO_RW_DATA_MASK;
702out:
1557c679 703 mt7530_mutex_unlock(priv);
c288575f
LC		 704
705 return ret;
706}
707
708static int
709mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
defa2e54 710 int regnum, u16 data)
c288575f 711{
c288575f
LC		 712 struct mt7530_dummy_poll p;
713 u32 val, reg;
714 int ret;
715
716 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
717
1557c679 718 mt7530_mutex_lock(priv);
c288575f
LC		 719
720 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
721 !(val & MT7531_PHY_ACS_ST), 20, 100000);
722 if (ret < 0) {
723 dev_err(priv->dev, "poll timeout\n");
724 goto out;
725 }
726
727 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
728 MT7531_MDIO_DEV_ADDR(devad) | regnum;
729 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
730
731 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
732 !(val & MT7531_PHY_ACS_ST), 20, 100000);
733 if (ret < 0) {
734 dev_err(priv->dev, "poll timeout\n");
735 goto out;
736 }
737
738 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
739 MT7531_MDIO_DEV_ADDR(devad) | data;
740 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
741
742 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
743 !(val & MT7531_PHY_ACS_ST), 20, 100000);
744 if (ret < 0) {
745 dev_err(priv->dev, "poll timeout\n");
746 goto out;
747 }
748
749out:
1557c679 750 mt7530_mutex_unlock(priv);
c288575f
LC		 751
752 return ret;
753}
754
755static int
756mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
757{
c288575f
LC		 758 struct mt7530_dummy_poll p;
759 int ret;
760 u32 val;
761
762 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
763
1557c679 764 mt7530_mutex_lock(priv);
c288575f
LC		 765
766 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
767 !(val & MT7531_PHY_ACS_ST), 20, 100000);
768 if (ret < 0) {
769 dev_err(priv->dev, "poll timeout\n");
770 goto out;
771 }
772
773 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
774 MT7531_MDIO_REG_ADDR(regnum);
775
776 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
777
778 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
779 !(val & MT7531_PHY_ACS_ST), 20, 100000);
780 if (ret < 0) {
781 dev_err(priv->dev, "poll timeout\n");
782 goto out;
783 }
784
785 ret = val & MT7531_MDIO_RW_DATA_MASK;
786out:
1557c679 787 mt7530_mutex_unlock(priv);
c288575f
LC		 788
789 return ret;
790}
791
792static int
793mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
794 u16 data)
795{
c288575f
LC		 796 struct mt7530_dummy_poll p;
797 int ret;
798 u32 reg;
799
800 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
801
1557c679 802 mt7530_mutex_lock(priv);
c288575f
LC		 803
804 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
805 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
806 if (ret < 0) {
807 dev_err(priv->dev, "poll timeout\n");
808 goto out;
809 }
810
811 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
812 MT7531_MDIO_REG_ADDR(regnum) | data;
813
814 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
815
816 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
817 !(reg & MT7531_PHY_ACS_ST), 20, 100000);
818 if (ret < 0) {
819 dev_err(priv->dev, "poll timeout\n");
820 goto out;
821 }
822
823out:
1557c679 824 mt7530_mutex_unlock(priv);
c288575f
LC		 825
826 return ret;
827}
828
829static int
defa2e54 830mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum)
c288575f 831{
defa2e54 832 struct mt7530_priv *priv = bus->priv;
c288575f 833
defa2e54 834 return priv->info->phy_read_c22(priv, port, regnum);
c288575f
LC		 835}
836
837static int
defa2e54 838mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum)
c288575f 839{
defa2e54 840 struct mt7530_priv *priv = bus->priv;
c288575f 841
defa2e54 842 return priv->info->phy_read_c45(priv, port, devad, regnum);
c288575f
LC		 843}
844
ba751e28 845static int
defa2e54 846mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val)
ba751e28
DQ		 847{
848 struct mt7530_priv *priv = bus->priv;
849
defa2e54 850 return priv->info->phy_write_c22(priv, port, regnum, val);
ba751e28
DQ		 851}
852
853static int
defa2e54
AL		 854mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum,
855 u16 val)
ba751e28
DQ		 856{
857 struct mt7530_priv *priv = bus->priv;
858
defa2e54 859 return priv->info->phy_write_c45(priv, port, devad, regnum, val);
ba751e28
DQ		 860}
861
b8f126a8 862static void
89f09048
FF		 863mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
864 uint8_t *data)
b8f126a8
SW		 865{
866 int i;
867
89f09048
FF		 868 if (stringset != ETH_SS_STATS)
869 return;
870
b8f126a8
SW		 871 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
872 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
873 ETH_GSTRING_LEN);
874}
875
876static void
877mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
878 uint64_t *data)
879{
880 struct mt7530_priv *priv = ds->priv;
881 const struct mt7530_mib_desc *mib;
882 u32 reg, i;
883 u64 hi;
884
885 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
886 mib = &mt7530_mib[i];
887 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
888
889 data[i] = mt7530_read(priv, reg);
890 if (mib->size == 2) {
891 hi = mt7530_read(priv, reg + 4);
892 data[i] |= hi << 32;
893 }
894 }
895}
896
897static int
89f09048 898mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
b8f126a8 899{
89f09048
FF		 900 if (sset != ETH_SS_STATS)
901 return 0;
902
b8f126a8
SW		 903 return ARRAY_SIZE(mt7530_mib);
904}
905
ea6d5c92
DQ		 906static int
907mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
908{
909 struct mt7530_priv *priv = ds->priv;
910 unsigned int secs = msecs / 1000;
911 unsigned int tmp_age_count;
912 unsigned int error = -1;
913 unsigned int age_count;
914 unsigned int age_unit;
915
916 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */
917 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))
918 return -ERANGE;
919
920 /* iterate through all possible age_count to find the closest pair */
921 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {
922 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;
923
924 if (tmp_age_unit <= AGE_UNIT_MAX) {
925 unsigned int tmp_error = secs -
926 (tmp_age_count + 1) * (tmp_age_unit + 1);
927
928 /* found a closer pair */
929 if (error > tmp_error) {
930 error = tmp_error;
931 age_count = tmp_age_count;
932 age_unit = tmp_age_unit;
933 }
934
935 /* found the exact match, so break the loop */
936 if (!error)
937 break;
938 }
939 }
940
941 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));
942
943 return 0;
944}
945
25d15dee
DG		 946static const char *p5_intf_modes(unsigned int p5_interface)
947{
948 switch (p5_interface) {
949 case P5_DISABLED:
950 return "DISABLED";
951 case P5_INTF_SEL_PHY_P0:
952 return "PHY P0";
953 case P5_INTF_SEL_PHY_P4:
954 return "PHY P4";
955 case P5_INTF_SEL_GMAC5:
956 return "GMAC5";
957 case P5_INTF_SEL_GMAC5_SGMII:
958 return "GMAC5_SGMII";
959 default:
960 return "unknown";
961 }
962}
963
38f790a8
RD		 964static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
965{
966 struct mt7530_priv *priv = ds->priv;
967 u8 tx_delay = 0;
968 int val;
969
970 mutex_lock(&priv->reg_mutex);
971
972 val = mt7530_read(priv, MT7530_MHWTRAP);
973
974 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
975 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
976
977 switch (priv->p5_intf_sel) {
978 case P5_INTF_SEL_PHY_P0:
979 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
980 val |= MHWTRAP_PHY0_SEL;
df561f66 981 fallthrough;
38f790a8
RD		 982 case P5_INTF_SEL_PHY_P4:
983 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
984 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
985
986 /* Setup the MAC by default for the cpu port */
987 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
988 break;
989 case P5_INTF_SEL_GMAC5:
990 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
991 val &= ~MHWTRAP_P5_DIS;
992 break;
993 case P5_DISABLED:
994 interface = PHY_INTERFACE_MODE_NA;
995 break;
996 default:
997 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
998 priv->p5_intf_sel);
999 goto unlock_exit;
1000 }
1001
1002 /* Setup RGMII settings */
1003 if (phy_interface_mode_is_rgmii(interface)) {
1004 val |= MHWTRAP_P5_RGMII_MODE;
1005
1006 /* P5 RGMII RX Clock Control: delay setting for 1000M */
1007 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
1008
1009 /* Don't set delay in DSA mode */
1010 if (!dsa_is_dsa_port(priv->ds, 5) &&
1011 (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
1012 interface == PHY_INTERFACE_MODE_RGMII_ID))
1013 tx_delay = 4; /* n * 0.5 ns */
1014
1015 /* P5 RGMII TX Clock Control: delay x */
1016 mt7530_write(priv, MT7530_P5RGMIITXCR,
1017 CSR_RGMII_TXC_CFG(0x10 + tx_delay));
1018
1019 /* reduce P5 RGMII Tx driving, 8mA */
1020 mt7530_write(priv, MT7530_IO_DRV_CR,
1021 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
1022 }
1023
1024 mt7530_write(priv, MT7530_MHWTRAP, val);
1025
1026 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
1027 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
1028
1029 priv->p5_interface = interface;
1030
1031unlock_exit:
1032 mutex_unlock(&priv->reg_mutex);
1033}
1034
b8f126a8 1035static int
c288575f 1036mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
b8f126a8 1037{
c288575f 1038 struct mt7530_priv *priv = ds->priv;
0ce0c3cd 1039 int ret;
c288575f
LC		 1040
1041 /* Setup max capability of CPU port at first */
0ce0c3cd
AD		 1042 if (priv->info->cpu_port_config) {
1043 ret = priv->info->cpu_port_config(ds, port);
1044 if (ret)
1045 return ret;
1046 }
c288575f 1047
b8f126a8
SW		 1048 /* Enable Mediatek header mode on the cpu port */
1049 mt7530_write(priv, MT7530_PVC_P(port),
1050 PORT_SPEC_TAG);
1051
5a30833b
DQ		 1052 /* Disable flooding by default */
1053 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK,
1054 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port)));
b8f126a8 1055
ddda1ac1
GU		 1056 /* Set CPU port number */
1057 if (priv->id == ID_MT7621)
1058 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
1059
b8f126a8 1060 /* CPU port gets connected to all user ports of
c288575f 1061 * the switch.
b8f126a8
SW		 1062 */
1063 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 1064 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8 1065
6087175b
DQ		 1066 /* Set to fallback mode for independent VLAN learning */
1067 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1068 MT7530_PORT_FALLBACK_MODE);
1069
b8f126a8
SW		 1070 return 0;
1071}
1072
1073static int
1074mt7530_port_enable(struct dsa_switch *ds, int port,
1075 struct phy_device *phy)
1076{
1f9a6abe 1077 struct dsa_port *dp = dsa_to_port(ds, port);
b8f126a8
SW		 1078 struct mt7530_priv *priv = ds->priv;
1079
1080 mutex_lock(&priv->reg_mutex);
1081
b8f126a8
SW		 1082 /* Allow the user port gets connected to the cpu port and also
1083 * restore the port matrix if the port is the member of a certain
1084 * bridge.
1085 */
1f9a6abe
FW		 1086 if (dsa_port_is_user(dp)) {
1087 struct dsa_port *cpu_dp = dp->cpu_dp;
1088
1089 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index));
1090 }
b8f126a8
SW		 1091 priv->ports[port].enable = true;
1092 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1093 priv->ports[port].pm);
1d01145f 1094 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1095
1096 mutex_unlock(&priv->reg_mutex);
1097
1098 return 0;
1099}
1100
1101static void
75104db0 1102mt7530_port_disable(struct dsa_switch *ds, int port)
b8f126a8
SW		 1103{
1104 struct mt7530_priv *priv = ds->priv;
1105
1106 mutex_lock(&priv->reg_mutex);
1107
1108 /* Clear up all port matrix which could be restored in the next
1109 * enablement for the port.
1110 */
1111 priv->ports[port].enable = false;
1112 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1113 PCR_MATRIX_CLR);
1d01145f 1114 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
b8f126a8
SW		 1115
1116 mutex_unlock(&priv->reg_mutex);
1117}
1118
9470174e
DQ		 1119static int
1120mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1121{
1122 struct mt7530_priv *priv = ds->priv;
9470174e
DQ		 1123 int length;
1124 u32 val;
1125
1126 /* When a new MTU is set, DSA always set the CPU port's MTU to the
1127 * largest MTU of the slave ports. Because the switch only has a global
1128 * RX length register, only allowing CPU port here is enough.
1129 */
1130 if (!dsa_is_cpu_port(ds, port))
1131 return 0;
1132
1557c679 1133 mt7530_mutex_lock(priv);
9470174e
DQ		 1134
1135 val = mt7530_mii_read(priv, MT7530_GMACCR);
1136 val &= ~MAX_RX_PKT_LEN_MASK;
1137
1138 /* RX length also includes Ethernet header, MTK tag, and FCS length */
1139 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
1140 if (length <= 1522) {
1141 val |= MAX_RX_PKT_LEN_1522;
1142 } else if (length <= 1536) {
1143 val |= MAX_RX_PKT_LEN_1536;
1144 } else if (length <= 1552) {
1145 val |= MAX_RX_PKT_LEN_1552;
1146 } else {
1147 val &= ~MAX_RX_JUMBO_MASK;
1148 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
1149 val |= MAX_RX_PKT_LEN_JUMBO;
1150 }
1151
1152 mt7530_mii_write(priv, MT7530_GMACCR, val);
1153
1557c679 1154 mt7530_mutex_unlock(priv);
9470174e
DQ		 1155
1156 return 0;
1157}
1158
1159static int
1160mt7530_port_max_mtu(struct dsa_switch *ds, int port)
1161{
1162 return MT7530_MAX_MTU;
1163}
1164
b8f126a8
SW		 1165static void
1166mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1167{
1168 struct mt7530_priv *priv = ds->priv;
1169 u32 stp_state;
1170
1171 switch (state) {
1172 case BR_STATE_DISABLED:
1173 stp_state = MT7530_STP_DISABLED;
1174 break;
1175 case BR_STATE_BLOCKING:
1176 stp_state = MT7530_STP_BLOCKING;
1177 break;
1178 case BR_STATE_LISTENING:
1179 stp_state = MT7530_STP_LISTENING;
1180 break;
1181 case BR_STATE_LEARNING:
1182 stp_state = MT7530_STP_LEARNING;
1183 break;
1184 case BR_STATE_FORWARDING:
1185 default:
1186 stp_state = MT7530_STP_FORWARDING;
1187 break;
1188 }
1189
a9e3f62d
DQ		 1190 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED),
1191 FID_PST(FID_BRIDGED, stp_state));
b8f126a8
SW		 1192}
1193
5a30833b
DQ		 1194static int
1195mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1196 struct switchdev_brport_flags flags,
1197 struct netlink_ext_ack *extack)
1198{
1199 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1200 BR_BCAST_FLOOD))
1201 return -EINVAL;
1202
1203 return 0;
1204}
1205
1206static int
1207mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
1208 struct switchdev_brport_flags flags,
1209 struct netlink_ext_ack *extack)
1210{
1211 struct mt7530_priv *priv = ds->priv;
1212
1213 if (flags.mask & BR_LEARNING)
1214 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS,
1215 flags.val & BR_LEARNING ? 0 : SA_DIS);
1216
1217 if (flags.mask & BR_FLOOD)
1218 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
1219 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
1220
1221 if (flags.mask & BR_MCAST_FLOOD)
1222 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
1223 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
1224
1225 if (flags.mask & BR_BCAST_FLOOD)
1226 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
1227 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
1228
1229 return 0;
1230}
1231
b8f126a8
SW		 1232static int
1233mt7530_port_bridge_join(struct dsa_switch *ds, int port,
06b9cce4
VO		 1234 struct dsa_bridge bridge, bool *tx_fwd_offload,
1235 struct netlink_ext_ack *extack)
b8f126a8 1236{
872bb81d 1237 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1f9a6abe
FW		 1238 struct dsa_port *cpu_dp = dp->cpu_dp;
1239 u32 port_bitmap = BIT(cpu_dp->index);
872bb81d 1240 struct mt7530_priv *priv = ds->priv;
b8f126a8
SW		 1241
1242 mutex_lock(&priv->reg_mutex);
1243
872bb81d
VO		 1244 dsa_switch_for_each_user_port(other_dp, ds) {
1245 int other_port = other_dp->index;
1246
1247 if (dp == other_dp)
1248 continue;
1249
b8f126a8
SW		 1250 /* Add this port to the port matrix of the other ports in the
1251 * same bridge. If the port is disabled, port matrix is kept
1252 * and not being setup until the port becomes enabled.
1253 */
d3eed0e5 1254 if (!dsa_port_offloads_bridge(other_dp, &bridge))
872bb81d
VO		 1255 continue;
1256
1257 if (priv->ports[other_port].enable)
1258 mt7530_set(priv, MT7530_PCR_P(other_port),
1259 PCR_MATRIX(BIT(port)));
1260 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port));
1261
1262 port_bitmap |= BIT(other_port);
b8f126a8
SW		 1263 }
1264
1265 /* Add the all other ports to this port matrix. */
1266 if (priv->ports[port].enable)
1267 mt7530_rmw(priv, MT7530_PCR_P(port),
1268 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
1269 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
1270
6087175b
DQ		 1271 /* Set to fallback mode for independent VLAN learning */
1272 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1273 MT7530_PORT_FALLBACK_MODE);
1274
b8f126a8
SW		 1275 mutex_unlock(&priv->reg_mutex);
1276
1277 return 0;
1278}
1279
83163f7d
SW		 1280static void
1281mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
1282{
1283 struct mt7530_priv *priv = ds->priv;
1284 bool all_user_ports_removed = true;
1285 int i;
1286
6087175b
DQ		 1287 /* This is called after .port_bridge_leave when leaving a VLAN-aware
1288 * bridge. Don't set standalone ports to fallback mode.
83163f7d 1289 */
41fb0cf1 1290 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
6087175b
DQ		 1291 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1292 MT7530_PORT_FALLBACK_MODE);
1293
8fbebef8
DQ		 1294 mt7530_rmw(priv, MT7530_PVC_P(port),
1295 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
e045124e 1296 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
8fbebef8
DQ		 1297 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
1298 MT7530_VLAN_ACC_ALL);
83163f7d 1299
6087175b
DQ		 1300 /* Set PVID to 0 */
1301 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1302 G0_PORT_VID_DEF);
1303
83163f7d
SW		 1304 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1305 if (dsa_is_user_port(ds, i) &&
68bb8ea8 1306 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
83163f7d
SW		 1307 all_user_ports_removed = false;
1308 break;
1309 }
1310 }
1311
1312 /* CPU port also does the same thing until all user ports belonging to
1313 * the CPU port get out of VLAN filtering mode.
1314 */
1315 if (all_user_ports_removed) {
1f9a6abe
FW		 1316 struct dsa_port *dp = dsa_to_port(ds, port);
1317 struct dsa_port *cpu_dp = dp->cpu_dp;
1318
1319 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index),
83163f7d 1320 PCR_MATRIX(dsa_user_ports(priv->ds)));
1f9a6abe 1321 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG
e045124e 1322 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
83163f7d
SW		 1323 }
1324}
1325
1326static void
1327mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
1328{
1329 struct mt7530_priv *priv = ds->priv;
1330
83163f7d 1331 /* Trapped into security mode allows packet forwarding through VLAN
6087175b 1332 * table lookup.
83163f7d 1333 */
6087175b 1334 if (dsa_is_user_port(ds, port)) {
38152ea3
DQ		 1335 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1336 MT7530_PORT_SECURITY_MODE);
6087175b
DQ		 1337 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1338 G0_PORT_VID(priv->ports[port].pvid));
8fbebef8
DQ		 1339
1340 /* Only accept tagged frames if PVID is not set */
1341 if (!priv->ports[port].pvid)
1342 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1343 MT7530_VLAN_ACC_TAGGED);
83163f7d 1344
0b6d6425
VO		 1345 /* Set the port as a user port which is to be able to recognize
1346 * VID from incoming packets before fetching entry within the
1347 * VLAN table.
1348 */
1349 mt7530_rmw(priv, MT7530_PVC_P(port),
1350 VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
1351 VLAN_ATTR(MT7530_VLAN_USER) |
1352 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
1353 } else {
1354 /* Also set CPU ports to the "user" VLAN port attribute, to
1355 * allow VLAN classification, but keep the EG_TAG attribute as
1356 * "consistent" (i.o.w. don't change its value) for packets
1357 * received by the switch from the CPU, so that tagged packets
1358 * are forwarded to user ports as tagged, and untagged as
1359 * untagged.
1360 */
1361 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
1362 VLAN_ATTR(MT7530_VLAN_USER));
1363 }
83163f7d
SW		 1364}
1365
b8f126a8
SW		 1366static void
1367mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
d3eed0e5 1368 struct dsa_bridge bridge)
b8f126a8 1369{
872bb81d 1370 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1f9a6abe 1371 struct dsa_port *cpu_dp = dp->cpu_dp;
b8f126a8 1372 struct mt7530_priv *priv = ds->priv;
b8f126a8
SW		 1373
1374 mutex_lock(&priv->reg_mutex);
1375
872bb81d
VO		 1376 dsa_switch_for_each_user_port(other_dp, ds) {
1377 int other_port = other_dp->index;
1378
1379 if (dp == other_dp)
1380 continue;
1381
b8f126a8
SW		 1382 /* Remove this port from the port matrix of the other ports
1383 * in the same bridge. If the port is disabled, port matrix
1384 * is kept and not being setup until the port becomes enabled.
1385 */
d3eed0e5 1386 if (!dsa_port_offloads_bridge(other_dp, &bridge))
872bb81d
VO		 1387 continue;
1388
1389 if (priv->ports[other_port].enable)
1390 mt7530_clear(priv, MT7530_PCR_P(other_port),
1391 PCR_MATRIX(BIT(port)));
1392 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port));
b8f126a8
SW		 1393 }
1394
1395 /* Set the cpu port to be the only one in the port matrix of
1396 * this port.
1397 */
1398 if (priv->ports[port].enable)
1399 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
1f9a6abe
FW		 1400 PCR_MATRIX(BIT(cpu_dp->index)));
1401 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index));
b8f126a8 1402
6087175b
DQ		 1403 /* When a port is removed from the bridge, the port would be set up
1404 * back to the default as is at initial boot which is a VLAN-unaware
1405 * port.
1406 */
1407 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
1408 MT7530_PORT_MATRIX_MODE);
1409
b8f126a8
SW		 1410 mutex_unlock(&priv->reg_mutex);
1411}
1412
1413static int
b8f126a8 1414mt7530_port_fdb_add(struct dsa_switch *ds, int port,
c2693363
VO		 1415 const unsigned char *addr, u16 vid,
1416 struct dsa_db db)
b8f126a8
SW		 1417{
1418 struct mt7530_priv *priv = ds->priv;
1b6dd556 1419 int ret;
b8f126a8
SW		 1420 u8 port_mask = BIT(port);
1421
1422 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1423 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 1424 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 1425 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 1426
1427 return ret;
b8f126a8
SW		 1428}
1429
1430static int
1431mt7530_port_fdb_del(struct dsa_switch *ds, int port,
c2693363
VO		 1432 const unsigned char *addr, u16 vid,
1433 struct dsa_db db)
b8f126a8
SW		 1434{
1435 struct mt7530_priv *priv = ds->priv;
1436 int ret;
1437 u8 port_mask = BIT(port);
1438
1439 mutex_lock(&priv->reg_mutex);
6c2c1dcb 1440 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 1441 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 1442 mutex_unlock(&priv->reg_mutex);
1443
1444 return ret;
1445}
1446
1447static int
1448mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1449 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 1450{
1451 struct mt7530_priv *priv = ds->priv;
1452 struct mt7530_fdb _fdb = { 0 };
1453 int cnt = MT7530_NUM_FDB_RECORDS;
1454 int ret = 0;
1455 u32 rsp = 0;
1456
1457 mutex_lock(&priv->reg_mutex);
1458
1459 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
1460 if (ret < 0)
1461 goto err;
1462
1463 do {
1464 if (rsp & ATC_SRCH_HIT) {
1465 mt7530_fdb_read(priv, &_fdb);
1466 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 1467 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
1468 data);
b8f126a8
SW		 1469 if (ret < 0)
1470 break;
1471 }
1472 }
1473 } while (--cnt &&
1474 !(rsp & ATC_SRCH_END) &&
1475 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
1476err:
1477 mutex_unlock(&priv->reg_mutex);
1478
1479 return 0;
1480}
1481
5a30833b
DQ		 1482static int
1483mt7530_port_mdb_add(struct dsa_switch *ds, int port,
c2693363
VO		 1484 const struct switchdev_obj_port_mdb *mdb,
1485 struct dsa_db db)
5a30833b
DQ		 1486{
1487 struct mt7530_priv *priv = ds->priv;
1488 const u8 *addr = mdb->addr;
1489 u16 vid = mdb->vid;
1490 u8 port_mask = 0;
1491 int ret;
1492
1493 mutex_lock(&priv->reg_mutex);
1494
1495 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1496 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1497 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1498 & PORT_MAP_MASK;
1499
1500 port_mask |= BIT(port);
1501 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
1502 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1503
1504 mutex_unlock(&priv->reg_mutex);
1505
1506 return ret;
1507}
1508
1509static int
1510mt7530_port_mdb_del(struct dsa_switch *ds, int port,
c2693363
VO		 1511 const struct switchdev_obj_port_mdb *mdb,
1512 struct dsa_db db)
5a30833b
DQ		 1513{
1514 struct mt7530_priv *priv = ds->priv;
1515 const u8 *addr = mdb->addr;
1516 u16 vid = mdb->vid;
1517 u8 port_mask = 0;
1518 int ret;
1519
1520 mutex_lock(&priv->reg_mutex);
1521
1522 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
1523 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))
1524 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)
1525 & PORT_MAP_MASK;
1526
1527 port_mask &= ~BIT(port);
1528 mt7530_fdb_write(priv, vid, port_mask, addr, -1,
1529 port_mask ? STATIC_ENT : STATIC_EMP);
1530 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
1531
1532 mutex_unlock(&priv->reg_mutex);
1533
1534 return ret;
1535}
1536
83163f7d
SW		 1537static int
1538mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
1539{
1540 struct mt7530_dummy_poll p;
1541 u32 val;
1542 int ret;
1543
1544 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
1545 mt7530_write(priv, MT7530_VTCR, val);
1546
1547 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
1548 ret = readx_poll_timeout(_mt7530_read, &p, val,
1549 !(val & VTCR_BUSY), 20, 20000);
1550 if (ret < 0) {
1551 dev_err(priv->dev, "poll timeout\n");
1552 return ret;
1553 }
1554
1555 val = mt7530_read(priv, MT7530_VTCR);
1556 if (val & VTCR_INVALID) {
1557 dev_err(priv->dev, "read VTCR invalid\n");
1558 return -EINVAL;
1559 }
1560
1561 return 0;
1562}
1563
1564static int
89153ed6
VO		 1565mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1566 struct netlink_ext_ack *extack)
83163f7d 1567{
1f9a6abe
FW		 1568 struct dsa_port *dp = dsa_to_port(ds, port);
1569 struct dsa_port *cpu_dp = dp->cpu_dp;
1570
83163f7d
SW		 1571 if (vlan_filtering) {
1572 /* The port is being kept as VLAN-unaware port when bridge is
1573 * set up with vlan_filtering not being set, Otherwise, the
1574 * port and the corresponding CPU port is required the setup
1575 * for becoming a VLAN-aware port.
1576 */
1577 mt7530_port_set_vlan_aware(ds, port);
1f9a6abe 1578 mt7530_port_set_vlan_aware(ds, cpu_dp->index);
e3ee07d1
VO		 1579 } else {
1580 mt7530_port_set_vlan_unaware(ds, port);
83163f7d
SW		 1581 }
1582
1583 return 0;
1584}
1585
83163f7d
SW		 1586static void
1587mt7530_hw_vlan_add(struct mt7530_priv *priv,
1588 struct mt7530_hw_vlan_entry *entry)
1589{
a9c31741 1590 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
83163f7d
SW		 1591 u8 new_members;
1592 u32 val;
1593
a9c31741 1594 new_members = entry->old_members | BIT(entry->port);
83163f7d
SW		 1595
1596 /* Validate the entry with independent learning, create egress tag per
1597 * VLAN and joining the port as one of the port members.
1598 */
6087175b
DQ		 1599 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
1600 VLAN_VALID;
83163f7d
SW		 1601 mt7530_write(priv, MT7530_VAWD1, val);
1602
1603 /* Decide whether adding tag or not for those outgoing packets from the
1604 * port inside the VLAN.
a9c31741 1605 * CPU port is always taken as a tagged port for serving more than one
83163f7d
SW		 1606 * VLANs across and also being applied with egress type stack mode for
1607 * that VLAN tags would be appended after hardware special tag used as
1608 * DSA tag.
1609 */
a9c31741
FW		 1610 if (dsa_port_is_cpu(dp))
1611 val = MT7530_VLAN_EGRESS_STACK;
1612 else if (entry->untagged)
1613 val = MT7530_VLAN_EGRESS_UNTAG;
1614 else
1615 val = MT7530_VLAN_EGRESS_TAG;
83163f7d 1616 mt7530_rmw(priv, MT7530_VAWD2,
a9c31741
FW		 1617 ETAG_CTRL_P_MASK(entry->port),
1618 ETAG_CTRL_P(entry->port, val));
83163f7d
SW		 1619}
1620
1621static void
1622mt7530_hw_vlan_del(struct mt7530_priv *priv,
1623 struct mt7530_hw_vlan_entry *entry)
1624{
1625 u8 new_members;
1626 u32 val;
1627
1628 new_members = entry->old_members & ~BIT(entry->port);
1629
1630 val = mt7530_read(priv, MT7530_VAWD1);
1631 if (!(val & VLAN_VALID)) {
1632 dev_err(priv->dev,
1633 "Cannot be deleted due to invalid entry\n");
1634 return;
1635 }
1636
a9c31741 1637 if (new_members) {
83163f7d
SW		 1638 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1639 VLAN_VALID;
1640 mt7530_write(priv, MT7530_VAWD1, val);
1641 } else {
1642 mt7530_write(priv, MT7530_VAWD1, 0);
1643 mt7530_write(priv, MT7530_VAWD2, 0);
1644 }
1645}
1646
1647static void
1648mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1649 struct mt7530_hw_vlan_entry *entry,
1650 mt7530_vlan_op vlan_op)
1651{
1652 u32 val;
1653
1654 /* Fetch entry */
1655 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1656
1657 val = mt7530_read(priv, MT7530_VAWD1);
1658
1659 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1660
1661 /* Manipulate entry */
1662 vlan_op(priv, entry);
1663
1664 /* Flush result to hardware */
1665 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1666}
1667
1ca8a193
DQ		 1668static int
1669mt7530_setup_vlan0(struct mt7530_priv *priv)
1670{
1671 u32 val;
1672
1673 /* Validate the entry with independent learning, keep the original
1674 * ingress tag attribute.
1675 */
1676 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
1677 VLAN_VALID;
1678 mt7530_write(priv, MT7530_VAWD1, val);
1679
1680 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
1681}
1682
1958d581 1683static int
83163f7d 1684mt7530_port_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 1685 const struct switchdev_obj_port_vlan *vlan,
1686 struct netlink_ext_ack *extack)
83163f7d
SW		 1687{
1688 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1689 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1690 struct mt7530_hw_vlan_entry new_entry;
1691 struct mt7530_priv *priv = ds->priv;
83163f7d 1692
83163f7d
SW		 1693 mutex_lock(&priv->reg_mutex);
1694
b7a9e0da
VO		 1695 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1696 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
83163f7d
SW		 1697
1698 if (pvid) {
b7a9e0da 1699 priv->ports[port].pvid = vlan->vid;
6087175b 1700
8fbebef8
DQ		 1701 /* Accept all frames if PVID is set */
1702 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1703 MT7530_VLAN_ACC_ALL);
1704
6087175b
DQ		 1705 /* Only configure PVID if VLAN filtering is enabled */
1706 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1707 mt7530_rmw(priv, MT7530_PPBV1_P(port),
1708 G0_PORT_VID_MASK,
1709 G0_PORT_VID(vlan->vid));
8fbebef8
DQ		 1710 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
1711 /* This VLAN is overwritten without PVID, so unset it */
1712 priv->ports[port].pvid = G0_PORT_VID_DEF;
1713
1714 /* Only accept tagged frames if the port is VLAN-aware */
1715 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1716 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1717 MT7530_VLAN_ACC_TAGGED);
1718
1719 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1720 G0_PORT_VID_DEF);
83163f7d
SW		 1721 }
1722
1723 mutex_unlock(&priv->reg_mutex);
1958d581
VO		 1724
1725 return 0;
83163f7d
SW		 1726}
1727
1728static int
1729mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1730 const struct switchdev_obj_port_vlan *vlan)
1731{
1732 struct mt7530_hw_vlan_entry target_entry;
1733 struct mt7530_priv *priv = ds->priv;
83163f7d 1734
83163f7d
SW		 1735 mutex_lock(&priv->reg_mutex);
1736
b7a9e0da
VO		 1737 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1738 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
1739 mt7530_hw_vlan_del);
83163f7d 1740
b7a9e0da
VO		 1741 /* PVID is being restored to the default whenever the PVID port
1742 * is being removed from the VLAN.
1743 */
6087175b
DQ		 1744 if (priv->ports[port].pvid == vlan->vid) {
1745 priv->ports[port].pvid = G0_PORT_VID_DEF;
8fbebef8
DQ		 1746
1747 /* Only accept tagged frames if the port is VLAN-aware */
1748 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1749 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK,
1750 MT7530_VLAN_ACC_TAGGED);
1751
6087175b
DQ		 1752 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1753 G0_PORT_VID_DEF);
1754 }
83163f7d 1755
83163f7d
SW		 1756
1757 mutex_unlock(&priv->reg_mutex);
1758
1759 return 0;
1760}
1761
c288575f
LC		 1762static int mt753x_mirror_port_get(unsigned int id, u32 val)
1763{
1764 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
1765 MIRROR_PORT(val);
1766}
1767
1768static int mt753x_mirror_port_set(unsigned int id, u32 val)
1769{
1770 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
1771 MIRROR_PORT(val);
1772}
1773
1774static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
37feab60 1775 struct dsa_mall_mirror_tc_entry *mirror,
0148bb50 1776 bool ingress, struct netlink_ext_ack *extack)
37feab60
DQ		 1777{
1778 struct mt7530_priv *priv = ds->priv;
c288575f 1779 int monitor_port;
37feab60
DQ		 1780 u32 val;
1781
1782 /* Check for existent entry */
1783 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
1784 return -EEXIST;
1785
c288575f 1786 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
37feab60
DQ		 1787
1788 /* MT7530 only supports one monitor port */
c288575f
LC		 1789 monitor_port = mt753x_mirror_port_get(priv->id, val);
1790 if (val & MT753X_MIRROR_EN(priv->id) &&
1791 monitor_port != mirror->to_local_port)
37feab60
DQ		 1792 return -EEXIST;
1793
c288575f
LC		 1794 val |= MT753X_MIRROR_EN(priv->id);
1795 val &= ~MT753X_MIRROR_MASK(priv->id);
1796 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
1797 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1798
1799 val = mt7530_read(priv, MT7530_PCR_P(port));
1800 if (ingress) {
1801 val |= PORT_RX_MIR;
1802 priv->mirror_rx |= BIT(port);
1803 } else {
1804 val |= PORT_TX_MIR;
1805 priv->mirror_tx |= BIT(port);
1806 }
1807 mt7530_write(priv, MT7530_PCR_P(port), val);
1808
1809 return 0;
1810}
1811
c288575f 1812static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
37feab60
DQ		 1813 struct dsa_mall_mirror_tc_entry *mirror)
1814{
1815 struct mt7530_priv *priv = ds->priv;
1816 u32 val;
1817
1818 val = mt7530_read(priv, MT7530_PCR_P(port));
1819 if (mirror->ingress) {
1820 val &= ~PORT_RX_MIR;
1821 priv->mirror_rx &= ~BIT(port);
1822 } else {
1823 val &= ~PORT_TX_MIR;
1824 priv->mirror_tx &= ~BIT(port);
1825 }
1826 mt7530_write(priv, MT7530_PCR_P(port), val);
1827
1828 if (!priv->mirror_rx && !priv->mirror_tx) {
c288575f
LC		 1829 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
1830 val &= ~MT753X_MIRROR_EN(priv->id);
1831 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
37feab60
DQ		 1832 }
1833}
1834
b8f126a8 1835static enum dsa_tag_protocol
4d776482
FF		 1836mtk_get_tag_protocol(struct dsa_switch *ds, int port,
1837 enum dsa_tag_protocol mp)
b8f126a8 1838{
244f8a80 1839 return DSA_TAG_PROTO_MTK;
b8f126a8
SW		 1840}
1841
63c75c05 1842#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 1843static inline u32
1844mt7530_gpio_to_bit(unsigned int offset)
1845{
1846 /* Map GPIO offset to register bit
1847 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2
1848 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5
1849 * [10: 8] port 2 LED 0..2 as GPIO 6..8
1850 * [14:12] port 3 LED 0..2 as GPIO 9..11
1851 * [18:16] port 4 LED 0..2 as GPIO 12..14
1852 */
1853 return BIT(offset + offset / 3);
1854}
1855
1856static int
1857mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)
1858{
1859 struct mt7530_priv *priv = gpiochip_get_data(gc);
1860 u32 bit = mt7530_gpio_to_bit(offset);
1861
1862 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);
1863}
1864
1865static void
1866mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
1867{
1868 struct mt7530_priv *priv = gpiochip_get_data(gc);
1869 u32 bit = mt7530_gpio_to_bit(offset);
1870
1871 if (value)
1872 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1873 else
1874 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1875}
1876
1877static int
1878mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
1879{
1880 struct mt7530_priv *priv = gpiochip_get_data(gc);
1881 u32 bit = mt7530_gpio_to_bit(offset);
1882
1883 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?
1884 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1885}
1886
1887static int
1888mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
1889{
1890 struct mt7530_priv *priv = gpiochip_get_data(gc);
1891 u32 bit = mt7530_gpio_to_bit(offset);
1892
1893 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit);
1894 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);
1895
1896 return 0;
1897}
1898
1899static int
1900mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
1901{
1902 struct mt7530_priv *priv = gpiochip_get_data(gc);
1903 u32 bit = mt7530_gpio_to_bit(offset);
1904
1905 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit);
1906
1907 if (value)
1908 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit);
1909 else
1910 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);
1911
1912 mt7530_set(priv, MT7530_LED_GPIO_OE, bit);
1913
1914 return 0;
1915}
1916
1917static int
1918mt7530_setup_gpio(struct mt7530_priv *priv)
1919{
1920 struct device *dev = priv->dev;
1921 struct gpio_chip *gc;
1922
1923 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
1924 if (!gc)
1925 return -ENOMEM;
1926
1927 mt7530_write(priv, MT7530_LED_GPIO_OE, 0);
1928 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);
1929 mt7530_write(priv, MT7530_LED_IO_MODE, 0);
1930
1931 gc->label = "mt7530";
1932 gc->parent = dev;
1933 gc->owner = THIS_MODULE;
1934 gc->get_direction = mt7530_gpio_get_direction;
1935 gc->direction_input = mt7530_gpio_direction_input;
1936 gc->direction_output = mt7530_gpio_direction_output;
1937 gc->get = mt7530_gpio_get;
1938 gc->set = mt7530_gpio_set;
1939 gc->base = -1;
1940 gc->ngpio = 15;
1941 gc->can_sleep = true;
1942
1943 return devm_gpiochip_add_data(dev, gc, priv);
1944}
63c75c05 1945#endif /* CONFIG_GPIOLIB */
429a0ede 1946
ba751e28
DQ		 1947static irqreturn_t
1948mt7530_irq_thread_fn(int irq, void *dev_id)
1949{
1950 struct mt7530_priv *priv = dev_id;
1951 bool handled = false;
1952 u32 val;
1953 int p;
1954
1557c679 1955 mt7530_mutex_lock(priv);
ba751e28
DQ		 1956 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS);
1957 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val);
1557c679 1958 mt7530_mutex_unlock(priv);
ba751e28
DQ		 1959
1960 for (p = 0; p < MT7530_NUM_PHYS; p++) {
1961 if (BIT(p) & val) {
1962 unsigned int irq;
1963
1964 irq = irq_find_mapping(priv->irq_domain, p);
1965 handle_nested_irq(irq);
1966 handled = true;
1967 }
1968 }
1969
1970 return IRQ_RETVAL(handled);
1971}
1972
1973static void
1974mt7530_irq_mask(struct irq_data *d)
1975{
1976 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1977
1978 priv->irq_enable &= ~BIT(d->hwirq);
1979}
1980
1981static void
1982mt7530_irq_unmask(struct irq_data *d)
1983{
1984 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1985
1986 priv->irq_enable |= BIT(d->hwirq);
1987}
1988
1989static void
1990mt7530_irq_bus_lock(struct irq_data *d)
1991{
1992 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
1993
1557c679 1994 mt7530_mutex_lock(priv);
ba751e28
DQ		 1995}
1996
1997static void
1998mt7530_irq_bus_sync_unlock(struct irq_data *d)
1999{
2000 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
2001
2002 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
1557c679 2003 mt7530_mutex_unlock(priv);
ba751e28
DQ		 2004}
2005
2006static struct irq_chip mt7530_irq_chip = {
2007 .name = KBUILD_MODNAME,
2008 .irq_mask = mt7530_irq_mask,
2009 .irq_unmask = mt7530_irq_unmask,
2010 .irq_bus_lock = mt7530_irq_bus_lock,
2011 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock,
2012};
2013
2014static int
2015mt7530_irq_map(struct irq_domain *domain, unsigned int irq,
2016 irq_hw_number_t hwirq)
2017{
2018 irq_set_chip_data(irq, domain->host_data);
2019 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq);
2020 irq_set_nested_thread(irq, true);
2021 irq_set_noprobe(irq);
2022
2023 return 0;
2024}
2025
2026static const struct irq_domain_ops mt7530_irq_domain_ops = {
2027 .map = mt7530_irq_map,
2028 .xlate = irq_domain_xlate_onecell,
2029};
2030
2031static void
2032mt7530_setup_mdio_irq(struct mt7530_priv *priv)
2033{
2034 struct dsa_switch *ds = priv->ds;
2035 int p;
2036
2037 for (p = 0; p < MT7530_NUM_PHYS; p++) {
2038 if (BIT(p) & ds->phys_mii_mask) {
2039 unsigned int irq;
2040
2041 irq = irq_create_mapping(priv->irq_domain, p);
2042 ds->slave_mii_bus->irq[p] = irq;
2043 }
2044 }
2045}
2046
2047static int
2048mt7530_setup_irq(struct mt7530_priv *priv)
2049{
2050 struct device *dev = priv->dev;
2051 struct device_node *np = dev->of_node;
2052 int ret;
2053
2054 if (!of_property_read_bool(np, "interrupt-controller")) {
2055 dev_info(dev, "no interrupt support\n");
2056 return 0;
2057 }
2058
2059 priv->irq = of_irq_get(np, 0);
2060 if (priv->irq <= 0) {
2061 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq);
2062 return priv->irq ? : -EINVAL;
2063 }
2064
2065 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
2066 &mt7530_irq_domain_ops, priv);
2067 if (!priv->irq_domain) {
2068 dev_err(dev, "failed to create IRQ domain\n");
2069 return -ENOMEM;
2070 }
2071
2072 /* This register must be set for MT7530 to properly fire interrupts */
2073 if (priv->id != ID_MT7531)
2074 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);
2075
2076 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,
2077 IRQF_ONESHOT, KBUILD_MODNAME, priv);
2078 if (ret) {
2079 irq_domain_remove(priv->irq_domain);
2080 dev_err(dev, "failed to request IRQ: %d\n", ret);
2081 return ret;
2082 }
2083
2084 return 0;
2085}
2086
2087static void
2088mt7530_free_mdio_irq(struct mt7530_priv *priv)
2089{
2090 int p;
2091
2092 for (p = 0; p < MT7530_NUM_PHYS; p++) {
2093 if (BIT(p) & priv->ds->phys_mii_mask) {
2094 unsigned int irq;
2095
2096 irq = irq_find_mapping(priv->irq_domain, p);
2097 irq_dispose_mapping(irq);
2098 }
2099 }
2100}
2101
2102static void
2103mt7530_free_irq_common(struct mt7530_priv *priv)
2104{
2105 free_irq(priv->irq, priv);
2106 irq_domain_remove(priv->irq_domain);
2107}
2108
2109static void
2110mt7530_free_irq(struct mt7530_priv *priv)
2111{
2112 mt7530_free_mdio_irq(priv);
2113 mt7530_free_irq_common(priv);
2114}
2115
2116static int
2117mt7530_setup_mdio(struct mt7530_priv *priv)
2118{
2119 struct dsa_switch *ds = priv->ds;
2120 struct device *dev = priv->dev;
2121 struct mii_bus *bus;
2122 static int idx;
2123 int ret;
2124
2125 bus = devm_mdiobus_alloc(dev);
2126 if (!bus)
2127 return -ENOMEM;
2128
2129 ds->slave_mii_bus = bus;
2130 bus->priv = priv;
2131 bus->name = KBUILD_MODNAME "-mii";
2132 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
defa2e54
AL		 2133 bus->read = mt753x_phy_read_c22;
2134 bus->write = mt753x_phy_write_c22;
2135 bus->read_c45 = mt753x_phy_read_c45;
2136 bus->write_c45 = mt753x_phy_write_c45;
ba751e28
DQ		 2137 bus->parent = dev;
2138 bus->phy_mask = ~ds->phys_mii_mask;
2139
2140 if (priv->irq)
2141 mt7530_setup_mdio_irq(priv);
2142
9ffe3d09 2143 ret = devm_mdiobus_register(dev, bus);
ba751e28
DQ		 2144 if (ret) {
2145 dev_err(dev, "failed to register MDIO bus: %d\n", ret);
2146 if (priv->irq)
2147 mt7530_free_mdio_irq(priv);
2148 }
2149
2150 return ret;
2151}
2152
b8f126a8
SW		 2153static int
2154mt7530_setup(struct dsa_switch *ds)
2155{
2156 struct mt7530_priv *priv = ds->priv;
6e19bc26 2157 struct device_node *dn = NULL;
38f790a8
RD		 2158 struct device_node *phy_node;
2159 struct device_node *mac_np;
b8f126a8 2160 struct mt7530_dummy_poll p;
38f790a8 2161 phy_interface_t interface;
6e19bc26 2162 struct dsa_port *cpu_dp;
ca366d6c
RD		 2163 u32 id, val;
2164 int ret, i;
b8f126a8 2165
0abfd494 2166 /* The parent node of master netdev which holds the common system
b8f126a8
SW		 2167 * controller also is the container for two GMACs nodes representing
2168 * as two netdev instances.
2169 */
6e19bc26
FW		 2170 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
2171 dn = cpu_dp->master->dev.of_node->parent;
2172 /* It doesn't matter which CPU port is found first,
2173 * their masters should share the same parent OF node
2174 */
2175 break;
2176 }
2177
2178 if (!dn) {
2179 dev_err(ds->dev, "parent OF node of DSA master not found");
2180 return -EINVAL;
2181 }
2182
0b69c54c 2183 ds->assisted_learning_on_cpu_port = true;
771c8901 2184 ds->mtu_enforcement_ingress = true;
b8f126a8 2185
ddda1ac1 2186 if (priv->id == ID_MT7530) {
ddda1ac1
GU		 2187 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
2188 ret = regulator_enable(priv->core_pwr);
2189 if (ret < 0) {
2190 dev_err(priv->dev,
2191 "Failed to enable core power: %d\n", ret);
2192 return ret;
2193 }
b8f126a8 2194
ddda1ac1
GU		 2195 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
2196 ret = regulator_enable(priv->io_pwr);
2197 if (ret < 0) {
2198 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
2199 ret);
2200 return ret;
2201 }
b8f126a8
SW		 2202 }
2203
2204 /* Reset whole chip through gpio pin or memory-mapped registers for
2205 * different type of hardware
2206 */
2207 if (priv->mcm) {
2208 reset_control_assert(priv->rstc);
2209 usleep_range(1000, 1100);
2210 reset_control_deassert(priv->rstc);
2211 } else {
2212 gpiod_set_value_cansleep(priv->reset, 0);
2213 usleep_range(1000, 1100);
2214 gpiod_set_value_cansleep(priv->reset, 1);
2215 }
2216
2217 /* Waiting for MT7530 got to stable */
2218 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2219 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2220 20, 1000000);
2221 if (ret < 0) {
2222 dev_err(priv->dev, "reset timeout\n");
2223 return ret;
2224 }
2225
2226 id = mt7530_read(priv, MT7530_CREV);
2227 id >>= CHIP_NAME_SHIFT;
2228 if (id != MT7530_ID) {
2229 dev_err(priv->dev, "chip %x can't be supported\n", id);
2230 return -ENODEV;
2231 }
2232
2233 /* Reset the switch through internal reset */
2234 mt7530_write(priv, MT7530_SYS_CTRL,
2235 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2236 SYS_CTRL_REG_RST);
2237
c8b8a3c6
VO		 2238 mt7530_pll_setup(priv);
2239
fdcc8ccd
AÜ		 2240 /* Lower Tx driving for TRGMII path */
2241 for (i = 0; i < NUM_TRGMII_CTRL; i++)
2242 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
2243 TD_DM_DRVP(8) | TD_DM_DRVN(8));
2244
2245 for (i = 0; i < NUM_TRGMII_CTRL; i++)
2246 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
2247 RD_TAP_MASK, RD_TAP(16));
2248
feb03fd1 2249 /* Enable port 6 */
b8f126a8
SW		 2250 val = mt7530_read(priv, MT7530_MHWTRAP);
2251 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
2252 val |= MHWTRAP_MANUAL;
2253 mt7530_write(priv, MT7530_MHWTRAP, val);
2254
ca366d6c
RD		 2255 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2256
b8f126a8
SW		 2257 /* Enable and reset MIB counters */
2258 mt7530_mib_reset(ds);
2259
b8f126a8
SW		 2260 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2261 /* Disable forwarding by default on all ports */
2262 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2263 PCR_MATRIX_CLR);
2264
0b69c54c
DQ		 2265 /* Disable learning by default on all ports */
2266 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2267
0ce0c3cd
AD		 2268 if (dsa_is_cpu_port(ds, i)) {
2269 ret = mt753x_cpu_port_enable(ds, i);
2270 if (ret)
2271 return ret;
5a30833b 2272 } else {
75104db0 2273 mt7530_port_disable(ds, i);
6087175b
DQ		 2274
2275 /* Set default PVID to 0 on all user ports */
2276 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2277 G0_PORT_VID_DEF);
5a30833b 2278 }
e045124e
DQ		 2279 /* Enable consistent egress tag */
2280 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2281 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
b8f126a8
SW		 2282 }
2283
1ca8a193
DQ		 2284 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2285 ret = mt7530_setup_vlan0(priv);
2286 if (ret)
2287 return ret;
2288
38f790a8
RD		 2289 /* Setup port 5 */
2290 priv->p5_intf_sel = P5_DISABLED;
2291 interface = PHY_INTERFACE_MODE_NA;
2292
2293 if (!dsa_is_unused_port(ds, 5)) {
2294 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
0c65b2b9
AL		 2295 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
2296 if (ret && ret != -ENODEV)
2297 return ret;
38f790a8
RD		 2298 } else {
2299 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
2300 for_each_child_of_node(dn, mac_np) {
2301 if (!of_device_is_compatible(mac_np,
2302 "mediatek,eth-mac"))
2303 continue;
2304
2305 ret = of_property_read_u32(mac_np, "reg", &id);
2306 if (ret < 0 || id != 1)
2307 continue;
2308
2309 phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
0452800f
CG		 2310 if (!phy_node)
2311 continue;
2312
38f790a8 2313 if (phy_node->parent == priv->dev->of_node->parent) {
0c65b2b9 2314 ret = of_get_phy_mode(mac_np, &interface);
8e4efd47
SP		 2315 if (ret && ret != -ENODEV) {
2316 of_node_put(mac_np);
a9e9b091 2317 of_node_put(phy_node);
0c65b2b9 2318 return ret;
8e4efd47 2319 }
38f790a8
RD		 2320 id = of_mdio_parse_addr(ds->dev, phy_node);
2321 if (id == 0)
2322 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
2323 if (id == 4)
2324 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
2325 }
8e4efd47 2326 of_node_put(mac_np);
38f790a8
RD		 2327 of_node_put(phy_node);
2328 break;
2329 }
2330 }
2331
63c75c05 2332#ifdef CONFIG_GPIOLIB
429a0ede
DQ		 2333 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) {
2334 ret = mt7530_setup_gpio(priv);
2335 if (ret)
2336 return ret;
2337 }
63c75c05 2338#endif /* CONFIG_GPIOLIB */
429a0ede 2339
38f790a8
RD		 2340 mt7530_setup_port5(ds, interface);
2341
b8f126a8 2342 /* Flush the FDB table */
18bd5949 2343 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 2344 if (ret < 0)
2345 return ret;
2346
2347 return 0;
2348}
2349
c288575f
LC		 2350static int
2351mt7531_setup(struct dsa_switch *ds)
2352{
2353 struct mt7530_priv *priv = ds->priv;
2354 struct mt7530_dummy_poll p;
6e19bc26 2355 struct dsa_port *cpu_dp;
c288575f
LC		 2356 u32 val, id;
2357 int ret, i;
2358
2359 /* Reset whole chip through gpio pin or memory-mapped registers for
2360 * different type of hardware
2361 */
2362 if (priv->mcm) {
2363 reset_control_assert(priv->rstc);
2364 usleep_range(1000, 1100);
2365 reset_control_deassert(priv->rstc);
2366 } else {
2367 gpiod_set_value_cansleep(priv->reset, 0);
2368 usleep_range(1000, 1100);
2369 gpiod_set_value_cansleep(priv->reset, 1);
2370 }
2371
2372 /* Waiting for MT7530 got to stable */
2373 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
2374 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
2375 20, 1000000);
2376 if (ret < 0) {
2377 dev_err(priv->dev, "reset timeout\n");
2378 return ret;
2379 }
2380
2381 id = mt7530_read(priv, MT7531_CREV);
2382 id >>= CHIP_NAME_SHIFT;
2383
2384 if (id != MT7531_ID) {
2385 dev_err(priv->dev, "chip %x can't be supported\n", id);
2386 return -ENODEV;
2387 }
2388
728c2af6
AC		 2389 /* all MACs must be forced link-down before sw reset */
2390 for (i = 0; i < MT7530_NUM_PORTS; i++)
2391 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
2392
c288575f
LC		 2393 /* Reset the switch through internal reset */
2394 mt7530_write(priv, MT7530_SYS_CTRL,
2395 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
2396 SYS_CTRL_REG_RST);
2397
42bc4faf
AC		 2398 mt7531_pll_setup(priv);
2399
c288575f
LC		 2400 if (mt7531_dual_sgmii_supported(priv)) {
2401 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
2402
2403 /* Let ds->slave_mii_bus be able to access external phy. */
2404 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
2405 MT7531_EXT_P_MDC_11);
2406 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
2407 MT7531_EXT_P_MDIO_12);
2408 } else {
2409 priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
2410 }
2411 dev_dbg(ds->dev, "P5 support %s interface\n",
2412 p5_intf_modes(priv->p5_intf_sel));
2413
2414 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
2415 MT7531_GPIO0_INTERRUPT);
2416
2417 /* Let phylink decide the interface later. */
2418 priv->p5_interface = PHY_INTERFACE_MODE_NA;
2419 priv->p6_interface = PHY_INTERFACE_MODE_NA;
2420
2421 /* Enable PHY core PLL, since phy_device has not yet been created
2422 * provided for phy_[read,write]_mmd_indirect is called, we provide
2423 * our own mt7531_ind_mmd_phy_[read,write] to complete this
2424 * function.
2425 */
2426 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
2427 MDIO_MMD_VEND2, CORE_PLL_GROUP4);
2428 val |= MT7531_PHY_PLL_BYPASS_MODE;
2429 val &= ~MT7531_PHY_PLL_OFF;
2430 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
2431 CORE_PLL_GROUP4, val);
2432
2433 /* BPDU to CPU port */
6e19bc26
FW		 2434 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
2435 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
2436 BIT(cpu_dp->index));
2437 break;
2438 }
c288575f
LC		 2439 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
2440 MT753X_BPDU_CPU_ONLY);
2441
2442 /* Enable and reset MIB counters */
2443 mt7530_mib_reset(ds);
2444
2445 for (i = 0; i < MT7530_NUM_PORTS; i++) {
2446 /* Disable forwarding by default on all ports */
2447 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
2448 PCR_MATRIX_CLR);
2449
0b69c54c
DQ		 2450 /* Disable learning by default on all ports */
2451 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
2452
c288575f
LC		 2453 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
2454
0ce0c3cd
AD		 2455 if (dsa_is_cpu_port(ds, i)) {
2456 ret = mt753x_cpu_port_enable(ds, i);
2457 if (ret)
2458 return ret;
5a30833b 2459 } else {
c288575f 2460 mt7530_port_disable(ds, i);
6087175b
DQ		 2461
2462 /* Set default PVID to 0 on all user ports */
2463 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
2464 G0_PORT_VID_DEF);
5a30833b
DQ		 2465 }
2466
c288575f
LC		 2467 /* Enable consistent egress tag */
2468 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
2469 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
2470 }
2471
1ca8a193
DQ		 2472 /* Setup VLAN ID 0 for VLAN-unaware bridges */
2473 ret = mt7530_setup_vlan0(priv);
2474 if (ret)
2475 return ret;
2476
0b69c54c 2477 ds->assisted_learning_on_cpu_port = true;
771c8901 2478 ds->mtu_enforcement_ingress = true;
c288575f
LC		 2479
2480 /* Flush the FDB table */
2481 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
2482 if (ret < 0)
2483 return ret;
2484
2485 return 0;
2486}
2487
59c2215f
RKO		 2488static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
2489 struct phylink_config *config)
2490{
2491 switch (port) {
2492 case 0 ... 4: /* Internal phy */
2493 __set_bit(PHY_INTERFACE_MODE_GMII,
2494 config->supported_interfaces);
2495 break;
2496
2497 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2498 phy_interface_set_rgmii(config->supported_interfaces);
2499 __set_bit(PHY_INTERFACE_MODE_MII,
2500 config->supported_interfaces);
2501 __set_bit(PHY_INTERFACE_MODE_GMII,
2502 config->supported_interfaces);
2503 break;
2504
2505 case 6: /* 1st cpu port */
2506 __set_bit(PHY_INTERFACE_MODE_RGMII,
2507 config->supported_interfaces);
2508 __set_bit(PHY_INTERFACE_MODE_TRGMII,
2509 config->supported_interfaces);
2510 break;
2511 }
2512}
2513
c288575f
LC		 2514static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
2515{
2516 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
2517}
2518
59c2215f
RKO		 2519static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
2520 struct phylink_config *config)
2521{
2522 struct mt7530_priv *priv = ds->priv;
2523
2524 switch (port) {
2525 case 0 ... 4: /* Internal phy */
2526 __set_bit(PHY_INTERFACE_MODE_GMII,
2527 config->supported_interfaces);
2528 break;
2529
2530 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
2531 if (mt7531_is_rgmii_port(priv, port)) {
2532 phy_interface_set_rgmii(config->supported_interfaces);
2533 break;
2534 }
2535 fallthrough;
2536
2537 case 6: /* 1st cpu port supports sgmii/8023z only */
2538 __set_bit(PHY_INTERFACE_MODE_SGMII,
2539 config->supported_interfaces);
2540 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
2541 config->supported_interfaces);
2542 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
2543 config->supported_interfaces);
2544
2545 config->mac_capabilities |= MAC_2500FD;
2546 break;
2547 }
2548}
2549
88bdef8b
LC		 2550static int
2551mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
2552{
2553 struct mt7530_priv *priv = ds->priv;
2554
2555 return priv->info->pad_setup(ds, state->interface);
2556}
2557
2558static int
2559mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2560 phy_interface_t interface)
2561{
2562 struct mt7530_priv *priv = ds->priv;
2563
2564 /* Only need to setup port5. */
2565 if (port != 5)
2566 return 0;
2567
2568 mt7530_setup_port5(priv->ds, interface);
2569
2570 return 0;
2571}
2572
c288575f
LC		 2573static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
2574 phy_interface_t interface,
2575 struct phy_device *phydev)
2576{
2577 u32 val;
2578
2579 if (!mt7531_is_rgmii_port(priv, port)) {
2580 dev_err(priv->dev, "RGMII mode is not available for port %d\n",
2581 port);
2582 return -EINVAL;
2583 }
2584
2585 val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
2586 val |= GP_CLK_EN;
2587 val &= ~GP_MODE_MASK;
2588 val |= GP_MODE(MT7531_GP_MODE_RGMII);
2589 val &= ~CLK_SKEW_IN_MASK;
2590 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
2591 val &= ~CLK_SKEW_OUT_MASK;
2592 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
2593 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
2594
2595 /* Do not adjust rgmii delay when vendor phy driver presents. */
2596 if (!phydev || phy_driver_is_genphy(phydev)) {
2597 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
2598 switch (interface) {
2599 case PHY_INTERFACE_MODE_RGMII:
2600 val |= TXCLK_NO_REVERSE;
2601 val |= RXCLK_NO_DELAY;
2602 break;
2603 case PHY_INTERFACE_MODE_RGMII_RXID:
2604 val |= TXCLK_NO_REVERSE;
2605 break;
2606 case PHY_INTERFACE_MODE_RGMII_TXID:
2607 val |= RXCLK_NO_DELAY;
2608 break;
2609 case PHY_INTERFACE_MODE_RGMII_ID:
2610 break;
2611 default:
2612 return -EINVAL;
2613 }
2614 }
2615 mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
2616
2617 return 0;
2618}
2619
c288575f
LC		 2620static bool mt753x_is_mac_port(u32 port)
2621{
2622 return (port == 5 || port == 6);
2623}
2624
c288575f
LC		 2625static int
2626mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2627 phy_interface_t interface)
2628{
2629 struct mt7530_priv *priv = ds->priv;
2630 struct phy_device *phydev;
2631 struct dsa_port *dp;
2632
2633 if (!mt753x_is_mac_port(port)) {
2634 dev_err(priv->dev, "port %d is not a MAC port\n", port);
2635 return -EINVAL;
2636 }
2637
2638 switch (interface) {
2639 case PHY_INTERFACE_MODE_RGMII:
2640 case PHY_INTERFACE_MODE_RGMII_ID:
2641 case PHY_INTERFACE_MODE_RGMII_RXID:
2642 case PHY_INTERFACE_MODE_RGMII_TXID:
2643 dp = dsa_to_port(ds, port);
2644 phydev = dp->slave->phydev;
2645 return mt7531_rgmii_setup(priv, port, interface, phydev);
2646 case PHY_INTERFACE_MODE_SGMII:
c288575f
LC		 2647 case PHY_INTERFACE_MODE_NA:
2648 case PHY_INTERFACE_MODE_1000BASEX:
2649 case PHY_INTERFACE_MODE_2500BASEX:
5b89aeae
DG		 2650 /* handled in SGMII PCS driver */
2651 return 0;
c288575f
LC		 2652 default:
2653 return -EINVAL;
2654 }
2655
2656 return -EINVAL;
2657}
2658
88bdef8b
LC		 2659static int
2660mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2661 const struct phylink_link_state *state)
2662{
2663 struct mt7530_priv *priv = ds->priv;
2664
2665 return priv->info->mac_port_config(ds, port, mode, state->interface);
2666}
2667
cbd1f243
RKO		 2668static struct phylink_pcs *
2669mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
2670 phy_interface_t interface)
2671{
2672 struct mt7530_priv *priv = ds->priv;
2673
2674 switch (interface) {
2675 case PHY_INTERFACE_MODE_TRGMII:
5b89aeae 2676 return &priv->pcs[port].pcs;
cbd1f243
RKO		 2677 case PHY_INTERFACE_MODE_SGMII:
2678 case PHY_INTERFACE_MODE_1000BASEX:
2679 case PHY_INTERFACE_MODE_2500BASEX:
5b89aeae 2680 return priv->ports[port].sgmii_pcs;
cbd1f243
RKO		 2681 default:
2682 return NULL;
2683 }
2684}
2685
88bdef8b
LC		 2686static void
2687mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
2688 const struct phylink_link_state *state)
2689{
2690 struct mt7530_priv *priv = ds->priv;
2691 u32 mcr_cur, mcr_new;
2692
88bdef8b
LC		 2693 switch (port) {
2694 case 0 ... 4: /* Internal phy */
2695 if (state->interface != PHY_INTERFACE_MODE_GMII)
2696 goto unsupported;
2697 break;
2698 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
2699 if (priv->p5_interface == state->interface)
2700 break;
2701
2702 if (mt753x_mac_config(ds, port, mode, state) < 0)
2703 goto unsupported;
38f790a8 2704
c288575f
LC		 2705 if (priv->p5_intf_sel != P5_DISABLED)
2706 priv->p5_interface = state->interface;
38f790a8 2707 break;
ca366d6c
RD		 2708 case 6: /* 1st cpu port */
2709 if (priv->p6_interface == state->interface)
2710 break;
2711
88bdef8b 2712 mt753x_pad_setup(ds, state);
ca366d6c 2713
88bdef8b
LC		 2714 if (mt753x_mac_config(ds, port, mode, state) < 0)
2715 goto unsupported;
ca366d6c 2716
ca366d6c
RD		 2717 priv->p6_interface = state->interface;
2718 break;
2719 default:
88bdef8b
LC		 2720unsupported:
2721 dev_err(ds->dev, "%s: unsupported %s port: %i\n",
2722 __func__, phy_modes(state->interface), port);
ca366d6c
RD		 2723 return;
2724 }
2725
ca366d6c
RD		 2726 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
2727 mcr_new = mcr_cur;
1d01145f 2728 mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
ca366d6c 2729 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
c288575f 2730 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
ca366d6c 2731
38f790a8
RD		 2732 /* Are we connected to external phy */
2733 if (port == 5 && dsa_is_user_port(ds, 5))
2734 mcr_new |= PMCR_EXT_PHY;
2735
ca366d6c
RD		 2736 if (mcr_new != mcr_cur)
2737 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
2738}
2739
c288575f 2740static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
ca366d6c
RD		 2741 unsigned int mode,
2742 phy_interface_t interface)
2743{
2744 struct mt7530_priv *priv = ds->priv;
2745
1d01145f 2746 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
ca366d6c
RD		 2747}
2748
cbd1f243
RKO		 2749static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs,
2750 unsigned int mode,
2751 phy_interface_t interface,
2752 int speed, int duplex)
c288575f 2753{
cbd1f243
RKO		 2754 if (pcs->ops->pcs_link_up)
2755 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
c288575f
LC		 2756}
2757
2758static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
ca366d6c
RD		 2759 unsigned int mode,
2760 phy_interface_t interface,
5b502a7b
RK		 2761 struct phy_device *phydev,
2762 int speed, int duplex,
2763 bool tx_pause, bool rx_pause)
ca366d6c
RD		 2764{
2765 struct mt7530_priv *priv = ds->priv;
1d01145f
RD		 2766 u32 mcr;
2767
2768 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
2769
c288575f
LC		 2770 /* MT753x MAC works in 1G full duplex mode for all up-clocked
2771 * variants.
2772 */
2773 if (interface == PHY_INTERFACE_MODE_TRGMII ||
2774 (phy_interface_mode_is_8023z(interface))) {
2775 speed = SPEED_1000;
2776 duplex = DUPLEX_FULL;
2777 }
2778
1d01145f
RD		 2779 switch (speed) {
2780 case SPEED_1000:
2781 mcr |= PMCR_FORCE_SPEED_1000;
2782 break;
2783 case SPEED_100:
2784 mcr |= PMCR_FORCE_SPEED_100;
2785 break;
2786 }
2787 if (duplex == DUPLEX_FULL) {
2788 mcr |= PMCR_FORCE_FDX;
2789 if (tx_pause)
2790 mcr |= PMCR_TX_FC_EN;
2791 if (rx_pause)
2792 mcr |= PMCR_RX_FC_EN;
2793 }
ca366d6c 2794
53243d41 2795 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
40b5d2f1
RD		 2796 switch (speed) {
2797 case SPEED_1000:
2798 mcr |= PMCR_FORCE_EEE1G;
2799 break;
2800 case SPEED_100:
2801 mcr |= PMCR_FORCE_EEE100;
2802 break;
2803 }
2804 }
2805
1d01145f 2806 mt7530_set(priv, MT7530_PMCR_P(port), mcr);
ca366d6c
RD		 2807}
2808
c288575f
LC		 2809static int
2810mt7531_cpu_port_config(struct dsa_switch *ds, int port)
2811{
2812 struct mt7530_priv *priv = ds->priv;
2813 phy_interface_t interface;
2814 int speed;
0ce0c3cd 2815 int ret;
c288575f
LC		 2816
2817 switch (port) {
2818 case 5:
2819 if (mt7531_is_rgmii_port(priv, port))
2820 interface = PHY_INTERFACE_MODE_RGMII;
2821 else
2822 interface = PHY_INTERFACE_MODE_2500BASEX;
2823
2824 priv->p5_interface = interface;
2825 break;
2826 case 6:
2827 interface = PHY_INTERFACE_MODE_2500BASEX;
2828
c288575f
LC		 2829 priv->p6_interface = interface;
2830 break;
0ce0c3cd
AD		 2831 default:
2832 return -EINVAL;
c288575f
LC		 2833 }
2834
2835 if (interface == PHY_INTERFACE_MODE_2500BASEX)
2836 speed = SPEED_2500;
2837 else
2838 speed = SPEED_1000;
2839
0ce0c3cd
AD		 2840 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
2841 if (ret)
2842 return ret;
c288575f
LC		 2843 mt7530_write(priv, MT7530_PMCR_P(port),
2844 PMCR_CPU_PORT_SETTING(priv->id));
cbd1f243
RKO		 2845 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED,
2846 interface, speed, DUPLEX_FULL);
c288575f
LC		 2847 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
2848 speed, DUPLEX_FULL, true, true);
2849
2850 return 0;
2851}
2852
59c2215f
RKO		 2853static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
2854 struct phylink_config *config)
2855{
2856 struct mt7530_priv *priv = ds->priv;
2857
2858 /* This switch only supports full-duplex at 1Gbps */
2859 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
2860 MAC_10 | MAC_100 | MAC_1000FD;
2861
7b972512
RKO		 2862 /* This driver does not make use of the speed, duplex, pause or the
2863 * advertisement in its mac_config, so it is safe to mark this driver
2864 * as non-legacy.
2865 */
2866 config->legacy_pre_march2020 = false;
2867
59c2215f
RKO		 2868 priv->info->mac_port_get_caps(ds, port, config);
2869}
2870
9d0df207
RKO		 2871static int mt753x_pcs_validate(struct phylink_pcs *pcs,
2872 unsigned long *supported,
2873 const struct phylink_link_state *state)
ca366d6c 2874{
9d0df207
RKO		 2875 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */
2876 if (state->interface == PHY_INTERFACE_MODE_TRGMII ||
2877 phy_interface_mode_is_8023z(state->interface))
2878 phylink_clear(supported, Autoneg);
ca366d6c 2879
9d0df207 2880 return 0;
ca366d6c
RD		 2881}
2882
cbd1f243
RKO		 2883static void mt7530_pcs_get_state(struct phylink_pcs *pcs,
2884 struct phylink_link_state *state)
ca366d6c 2885{
cbd1f243
RKO		 2886 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv;
2887 int port = pcs_to_mt753x_pcs(pcs)->port;
ca366d6c
RD		 2888 u32 pmsr;
2889
ca366d6c
RD		 2890 pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
2891
2892 state->link = (pmsr & PMSR_LINK);
2893 state->an_complete = state->link;
2894 state->duplex = !!(pmsr & PMSR_DPX);
2895
2896 switch (pmsr & PMSR_SPEED_MASK) {
2897 case PMSR_SPEED_10:
2898 state->speed = SPEED_10;
2899 break;
2900 case PMSR_SPEED_100:
2901 state->speed = SPEED_100;
2902 break;
2903 case PMSR_SPEED_1000:
2904 state->speed = SPEED_1000;
2905 break;
2906 default:
2907 state->speed = SPEED_UNKNOWN;
2908 break;
2909 }
2910
2911 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
2912 if (pmsr & PMSR_RX_FC)
2913 state->pause |= MLO_PAUSE_RX;
2914 if (pmsr & PMSR_TX_FC)
2915 state->pause |= MLO_PAUSE_TX;
ca366d6c
RD		 2916}
2917
cbd1f243
RKO		 2918static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
2919 phy_interface_t interface,
2920 const unsigned long *advertising,
2921 bool permit_pause_to_mac)
88bdef8b 2922{
cbd1f243
RKO		 2923 return 0;
2924}
88bdef8b 2925
cbd1f243
RKO		 2926static void mt7530_pcs_an_restart(struct phylink_pcs *pcs)
2927{
88bdef8b
LC		 2928}
2929
cbd1f243 2930static const struct phylink_pcs_ops mt7530_pcs_ops = {
9d0df207 2931 .pcs_validate = mt753x_pcs_validate,
cbd1f243
RKO		 2932 .pcs_get_state = mt7530_pcs_get_state,
2933 .pcs_config = mt753x_pcs_config,
2934 .pcs_an_restart = mt7530_pcs_an_restart,
2935};
2936
1bd099c4
DG		 2937static void
2938mt7530_mdio_regmap_lock(void *mdio_lock)
5b89aeae 2939{
1bd099c4
DG		 2940 mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED);
2941}
5b89aeae 2942
1bd099c4
DG		 2943static void
2944mt7530_mdio_regmap_unlock(void *mdio_lock)
2945{
2946 mutex_unlock(mdio_lock);
2947}
5b89aeae 2948
a08c0455 2949static const struct regmap_bus mt7530_regmap_bus = {
5b89aeae
DG		 2950 .reg_write = mt7530_regmap_write,
2951 .reg_read = mt7530_regmap_read,
5b89aeae
DG		 2952};
2953
9ecc0016
DG		 2954static int
2955mt7531_create_sgmii(struct mt7530_priv *priv)
2956{
2957 struct regmap_config *mt7531_pcs_config[2];
2958 struct phylink_pcs *pcs;
2959 struct regmap *regmap;
2960 int i, ret = 0;
2961
2962 for (i = 0; i < 2; i++) {
2963 mt7531_pcs_config[i] = devm_kzalloc(priv->dev,
2964 sizeof(struct regmap_config),
2965 GFP_KERNEL);
2966 if (!mt7531_pcs_config[i]) {
2967 ret = -ENOMEM;
2968 break;
2969 }
2970
2971 mt7531_pcs_config[i]->name = i ? "port6" : "port5";
2972 mt7531_pcs_config[i]->reg_bits = 16;
2973 mt7531_pcs_config[i]->val_bits = 32;
2974 mt7531_pcs_config[i]->reg_stride = 4;
2975 mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i);
2976 mt7531_pcs_config[i]->max_register = 0x17c;
1bd099c4
DG		 2977 mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock;
2978 mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
2979 mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
9ecc0016
DG		 2980
2981 regmap = devm_regmap_init(priv->dev,
a08c0455 2982 &mt7530_regmap_bus, priv->bus,
9ecc0016
DG		 2983 mt7531_pcs_config[i]);
2984 if (IS_ERR(regmap)) {
2985 ret = PTR_ERR(regmap);
2986 break;
2987 }
2988 pcs = mtk_pcs_lynxi_create(priv->dev, regmap,
2989 MT7531_PHYA_CTRL_SIGNAL3, 0);
2990 if (!pcs) {
2991 ret = -ENXIO;
2992 break;
2993 }
2994 priv->ports[5 + i].sgmii_pcs = pcs;
2995 }
2996
2997 if (ret && i)
2998 mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs);
2999
3000 return ret;
3001}
cbd1f243 3002
88bdef8b
LC		 3003static int
3004mt753x_setup(struct dsa_switch *ds)
3005{
3006 struct mt7530_priv *priv = ds->priv;
fae46308
RKO		 3007 int i, ret;
3008
3009 /* Initialise the PCS devices */
3010 for (i = 0; i < priv->ds->num_ports; i++) {
3011 priv->pcs[i].pcs.ops = priv->info->pcs_ops;
3012 priv->pcs[i].priv = priv;
3013 priv->pcs[i].port = i;
3014 }
88bdef8b 3015
fae46308 3016 ret = priv->info->sw_setup(ds);
ba751e28
DQ		 3017 if (ret)
3018 return ret;
88bdef8b 3019
ba751e28
DQ		 3020 ret = mt7530_setup_irq(priv);
3021 if (ret)
3022 return ret;
88bdef8b 3023
ba751e28
DQ		 3024 ret = mt7530_setup_mdio(priv);
3025 if (ret && priv->irq)
3026 mt7530_free_irq_common(priv);
88bdef8b 3027
ba751e28 3028 return ret;
88bdef8b
LC		 3029}
3030
40b5d2f1
RD		 3031static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,
3032 struct ethtool_eee *e)
3033{
3034 struct mt7530_priv *priv = ds->priv;
3035 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
3036
3037 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
3038 e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
3039
3040 return 0;
3041}
3042
3043static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,
3044 struct ethtool_eee *e)
3045{
3046 struct mt7530_priv *priv = ds->priv;
3047 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;
3048
3049 if (e->tx_lpi_timer > 0xFFF)
3050 return -EINVAL;
3051
3052 set = SET_LPI_THRESH(e->tx_lpi_timer);
3053 if (!e->tx_lpi_enabled)
3054 /* Force LPI Mode without a delay */
3055 set |= LPI_MODE_EN;
3056 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
3057
3058 return 0;
3059}
3060
d78d6776 3061static const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8 3062 .get_tag_protocol = mtk_get_tag_protocol,
88bdef8b 3063 .setup = mt753x_setup,
b8f126a8 3064 .get_strings = mt7530_get_strings,
b8f126a8
SW		 3065 .get_ethtool_stats = mt7530_get_ethtool_stats,
3066 .get_sset_count = mt7530_get_sset_count,
ea6d5c92 3067 .set_ageing_time = mt7530_set_ageing_time,
b8f126a8
SW		 3068 .port_enable = mt7530_port_enable,
3069 .port_disable = mt7530_port_disable,
9470174e
DQ		 3070 .port_change_mtu = mt7530_port_change_mtu,
3071 .port_max_mtu = mt7530_port_max_mtu,
b8f126a8 3072 .port_stp_state_set = mt7530_stp_state_set,
5a30833b
DQ		 3073 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags,
3074 .port_bridge_flags = mt7530_port_bridge_flags,
b8f126a8
SW		 3075 .port_bridge_join = mt7530_port_bridge_join,
3076 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 3077 .port_fdb_add = mt7530_port_fdb_add,
3078 .port_fdb_del = mt7530_port_fdb_del,
3079 .port_fdb_dump = mt7530_port_fdb_dump,
5a30833b
DQ		 3080 .port_mdb_add = mt7530_port_mdb_add,
3081 .port_mdb_del = mt7530_port_mdb_del,
83163f7d 3082 .port_vlan_filtering = mt7530_port_vlan_filtering,
83163f7d
SW		 3083 .port_vlan_add = mt7530_port_vlan_add,
3084 .port_vlan_del = mt7530_port_vlan_del,
c288575f
LC		 3085 .port_mirror_add = mt753x_port_mirror_add,
3086 .port_mirror_del = mt753x_port_mirror_del,
59c2215f 3087 .phylink_get_caps = mt753x_phylink_get_caps,
cbd1f243 3088 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs,
88bdef8b 3089 .phylink_mac_config = mt753x_phylink_mac_config,
c288575f
LC		 3090 .phylink_mac_link_down = mt753x_phylink_mac_link_down,
3091 .phylink_mac_link_up = mt753x_phylink_mac_link_up,
40b5d2f1
RD		 3092 .get_mac_eee = mt753x_get_mac_eee,
3093 .set_mac_eee = mt753x_set_mac_eee,
b8f126a8
SW		 3094};
3095
88bdef8b
LC		 3096static const struct mt753x_info mt753x_table[] = {
3097 [ID_MT7621] = {
3098 .id = ID_MT7621,
cbd1f243 3099 .pcs_ops = &mt7530_pcs_ops,
88bdef8b 3100 .sw_setup = mt7530_setup,
defa2e54
AL		 3101 .phy_read_c22 = mt7530_phy_read_c22,
3102 .phy_write_c22 = mt7530_phy_write_c22,
3103 .phy_read_c45 = mt7530_phy_read_c45,
3104 .phy_write_c45 = mt7530_phy_write_c45,
88bdef8b 3105 .pad_setup = mt7530_pad_clk_setup,
59c2215f 3106 .mac_port_get_caps = mt7530_mac_port_get_caps,
88bdef8b
LC		 3107 .mac_port_config = mt7530_mac_config,
3108 },
3109 [ID_MT7530] = {
3110 .id = ID_MT7530,
cbd1f243 3111 .pcs_ops = &mt7530_pcs_ops,
88bdef8b 3112 .sw_setup = mt7530_setup,
defa2e54
AL		 3113 .phy_read_c22 = mt7530_phy_read_c22,
3114 .phy_write_c22 = mt7530_phy_write_c22,
3115 .phy_read_c45 = mt7530_phy_read_c45,
3116 .phy_write_c45 = mt7530_phy_write_c45,
88bdef8b 3117 .pad_setup = mt7530_pad_clk_setup,
59c2215f 3118 .mac_port_get_caps = mt7530_mac_port_get_caps,
88bdef8b
LC		 3119 .mac_port_config = mt7530_mac_config,
3120 },
c288575f
LC		 3121 [ID_MT7531] = {
3122 .id = ID_MT7531,
5b89aeae 3123 .pcs_ops = &mt7530_pcs_ops,
c288575f 3124 .sw_setup = mt7531_setup,
defa2e54
AL		 3125 .phy_read_c22 = mt7531_ind_c22_phy_read,
3126 .phy_write_c22 = mt7531_ind_c22_phy_write,
3127 .phy_read_c45 = mt7531_ind_c45_phy_read,
3128 .phy_write_c45 = mt7531_ind_c45_phy_write,
c288575f
LC		 3129 .pad_setup = mt7531_pad_setup,
3130 .cpu_port_config = mt7531_cpu_port_config,
59c2215f 3131 .mac_port_get_caps = mt7531_mac_port_get_caps,
c288575f 3132 .mac_port_config = mt7531_mac_config,
c288575f 3133 },
88bdef8b
LC		 3134};
3135
ddda1ac1 3136static const struct of_device_id mt7530_of_match[] = {
88bdef8b
LC		 3137 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
3138 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
c288575f 3139 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
ddda1ac1
GU		 3140 { /* sentinel */ },
3141};
3142MODULE_DEVICE_TABLE(of, mt7530_of_match);
3143
b8f126a8
SW		 3144static int
3145mt7530_probe(struct mdio_device *mdiodev)
3146{
a08c0455 3147 static struct regmap_config *regmap_config;
b8f126a8
SW		 3148 struct mt7530_priv *priv;
3149 struct device_node *dn;
6de28522 3150 int ret;
b8f126a8
SW		 3151
3152 dn = mdiodev->dev.of_node;
3153
3154 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
3155 if (!priv)
3156 return -ENOMEM;
3157
7e99e347 3158 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
b8f126a8
SW		 3159 if (!priv->ds)
3160 return -ENOMEM;
3161
7e99e347 3162 priv->ds->dev = &mdiodev->dev;
342afce1 3163 priv->ds->num_ports = MT7530_NUM_PORTS;
7e99e347 3164
b8f126a8
SW		 3165 /* Use medatek,mcm property to distinguish hardware type that would
3166 * casues a little bit differences on power-on sequence.
3167 */
3168 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
3169 if (priv->mcm) {
3170 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
3171
3172 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
3173 if (IS_ERR(priv->rstc)) {
3174 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3175 return PTR_ERR(priv->rstc);
3176 }
3177 }
3178
ddda1ac1
GU		 3179 /* Get the hardware identifier from the devicetree node.
3180 * We will need it for some of the clock and regulator setup.
3181 */
88bdef8b
LC		 3182 priv->info = of_device_get_match_data(&mdiodev->dev);
3183 if (!priv->info)
3184 return -EINVAL;
3185
3186 /* Sanity check if these required device operations are filled
3187 * properly.
3188 */
3189 if (!priv->info->sw_setup || !priv->info->pad_setup ||
defa2e54 3190 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 ||
59c2215f 3191 !priv->info->mac_port_get_caps ||
cbd1f243 3192 !priv->info->mac_port_config)
88bdef8b
LC		 3193 return -EINVAL;
3194
3195 priv->id = priv->info->id;
b8f126a8 3196
ddda1ac1
GU		 3197 if (priv->id == ID_MT7530) {
3198 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
3199 if (IS_ERR(priv->core_pwr))
3200 return PTR_ERR(priv->core_pwr);
3201
3202 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
3203 if (IS_ERR(priv->io_pwr))
3204 return PTR_ERR(priv->io_pwr);
3205 }
b8f126a8
SW		 3206
3207 /* Not MCM that indicates switch works as the remote standalone
3208 * integrated circuit so the GPIO pin would be used to complete
3209 * the reset, otherwise memory-mapped register accessing used
3210 * through syscon provides in the case of MCM.
3211 */
3212 if (!priv->mcm) {
3213 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
3214 GPIOD_OUT_LOW);
3215 if (IS_ERR(priv->reset)) {
3216 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
3217 return PTR_ERR(priv->reset);
3218 }
3219 }
3220
3221 priv->bus = mdiodev->bus;
3222 priv->dev = &mdiodev->dev;
3223 priv->ds->priv = priv;
3224 priv->ds->ops = &mt7530_switch_ops;
3225 mutex_init(&priv->reg_mutex);
3226 dev_set_drvdata(&mdiodev->dev, priv);
3227
a08c0455
DG		 3228 regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config),
3229 GFP_KERNEL);
3230 if (!regmap_config)
3231 return -ENOMEM;
3232
3233 regmap_config->reg_bits = 16;
3234 regmap_config->val_bits = 32;
3235 regmap_config->reg_stride = 4;
3236 regmap_config->max_register = MT7530_CREV;
3237 regmap_config->disable_locking = true;
3238 priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
3239 priv->bus, regmap_config);
3240 if (IS_ERR(priv->regmap))
3241 return PTR_ERR(priv->regmap);
3242
6de28522
DG		 3243 if (priv->id == ID_MT7531) {
3244 ret = mt7531_create_sgmii(priv);
3245 if (ret)
3246 return ret;
3247 }
3248
23c9ee49 3249 return dsa_register_switch(priv->ds);
b8f126a8
SW		 3250}
3251
3252static void
3253mt7530_remove(struct mdio_device *mdiodev)
3254{
3255 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
5b89aeae 3256 int ret = 0, i;
b8f126a8 3257
0650bf52
VO		 3258 if (!priv)
3259 return;
3260
b8f126a8
SW		 3261 ret = regulator_disable(priv->core_pwr);
3262 if (ret < 0)
3263 dev_err(priv->dev,
3264 "Failed to disable core power: %d\n", ret);
3265
3266 ret = regulator_disable(priv->io_pwr);
3267 if (ret < 0)
3268 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
3269 ret);
3270
ba751e28
DQ		 3271 if (priv->irq)
3272 mt7530_free_irq(priv);
3273
b8f126a8 3274 dsa_unregister_switch(priv->ds);
5b89aeae
DG		 3275
3276 for (i = 0; i < 2; ++i)
3277 mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs);
3278
b8f126a8 3279 mutex_destroy(&priv->reg_mutex);
0650bf52
VO		 3280}
3281
3282static void mt7530_shutdown(struct mdio_device *mdiodev)
3283{
3284 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
3285
3286 if (!priv)
3287 return;
3288
3289 dsa_switch_shutdown(priv->ds);
3290
3291 dev_set_drvdata(&mdiodev->dev, NULL);
b8f126a8
SW		 3292}
3293
b8f126a8
SW		 3294static struct mdio_driver mt7530_mdio_driver = {
3295 .probe = mt7530_probe,
3296 .remove = mt7530_remove,
0650bf52 3297 .shutdown = mt7530_shutdown,
b8f126a8
SW		 3298 .mdiodrv.driver = {
3299 .name = "mt7530",
3300 .of_match_table = mt7530_of_match,
3301 },
3302};
3303
3304mdio_module_driver(mt7530_mdio_driver);
3305
3306MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
3307MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
3308MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)