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net: dsa: Do not check for ethtool_ops validity
[linux-block.git] / drivers / net / dsa / mt7530.c
CommitLineData
b8f126a8
SW		 1/*
2 * Mediatek MT7530 DSA Switch driver
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <linux/etherdevice.h>
15#include <linux/if_bridge.h>
16#include <linux/iopoll.h>
17#include <linux/mdio.h>
18#include <linux/mfd/syscon.h>
19#include <linux/module.h>
20#include <linux/netdevice.h>
21#include <linux/of_gpio.h>
22#include <linux/of_mdio.h>
23#include <linux/of_net.h>
24#include <linux/of_platform.h>
25#include <linux/phy.h>
26#include <linux/regmap.h>
27#include <linux/regulator/consumer.h>
28#include <linux/reset.h>
eb976a55 29#include <linux/gpio/consumer.h>
b8f126a8 30#include <net/dsa.h>
b8f126a8
SW		 31
32#include "mt7530.h"
33
34/* String, offset, and register size in bytes if different from 4 bytes */
35static const struct mt7530_mib_desc mt7530_mib[] = {
36 MIB_DESC(1, 0x00, "TxDrop"),
37 MIB_DESC(1, 0x04, "TxCrcErr"),
38 MIB_DESC(1, 0x08, "TxUnicast"),
39 MIB_DESC(1, 0x0c, "TxMulticast"),
40 MIB_DESC(1, 0x10, "TxBroadcast"),
41 MIB_DESC(1, 0x14, "TxCollision"),
42 MIB_DESC(1, 0x18, "TxSingleCollision"),
43 MIB_DESC(1, 0x1c, "TxMultipleCollision"),
44 MIB_DESC(1, 0x20, "TxDeferred"),
45 MIB_DESC(1, 0x24, "TxLateCollision"),
46 MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
47 MIB_DESC(1, 0x2c, "TxPause"),
48 MIB_DESC(1, 0x30, "TxPktSz64"),
49 MIB_DESC(1, 0x34, "TxPktSz65To127"),
50 MIB_DESC(1, 0x38, "TxPktSz128To255"),
51 MIB_DESC(1, 0x3c, "TxPktSz256To511"),
52 MIB_DESC(1, 0x40, "TxPktSz512To1023"),
53 MIB_DESC(1, 0x44, "Tx1024ToMax"),
54 MIB_DESC(2, 0x48, "TxBytes"),
55 MIB_DESC(1, 0x60, "RxDrop"),
56 MIB_DESC(1, 0x64, "RxFiltering"),
57 MIB_DESC(1, 0x6c, "RxMulticast"),
58 MIB_DESC(1, 0x70, "RxBroadcast"),
59 MIB_DESC(1, 0x74, "RxAlignErr"),
60 MIB_DESC(1, 0x78, "RxCrcErr"),
61 MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
62 MIB_DESC(1, 0x80, "RxFragErr"),
63 MIB_DESC(1, 0x84, "RxOverSzErr"),
64 MIB_DESC(1, 0x88, "RxJabberErr"),
65 MIB_DESC(1, 0x8c, "RxPause"),
66 MIB_DESC(1, 0x90, "RxPktSz64"),
67 MIB_DESC(1, 0x94, "RxPktSz65To127"),
68 MIB_DESC(1, 0x98, "RxPktSz128To255"),
69 MIB_DESC(1, 0x9c, "RxPktSz256To511"),
70 MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
71 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
72 MIB_DESC(2, 0xa8, "RxBytes"),
73 MIB_DESC(1, 0xb0, "RxCtrlDrop"),
74 MIB_DESC(1, 0xb4, "RxIngressDrop"),
75 MIB_DESC(1, 0xb8, "RxArlDrop"),
76};
77
78static int
79mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
80{
81 int ret;
82
83 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
84 if (ret < 0)
85 dev_err(priv->dev,
86 "failed to priv write register\n");
87 return ret;
88}
89
90static u32
91mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
92{
93 int ret;
94 u32 val;
95
96 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
97 if (ret < 0) {
98 dev_err(priv->dev,
99 "failed to priv read register\n");
100 return ret;
101 }
102
103 return val;
104}
105
106static void
107mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
108 u32 mask, u32 set)
109{
110 u32 val;
111
112 val = mt7623_trgmii_read(priv, reg);
113 val &= ~mask;
114 val |= set;
115 mt7623_trgmii_write(priv, reg, val);
116}
117
118static void
119mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
120{
121 mt7623_trgmii_rmw(priv, reg, 0, val);
122}
123
124static void
125mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
126{
127 mt7623_trgmii_rmw(priv, reg, val, 0);
128}
129
130static int
131core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
132{
133 struct mii_bus *bus = priv->bus;
134 int value, ret;
135
136 /* Write the desired MMD Devad */
137 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
138 if (ret < 0)
139 goto err;
140
141 /* Write the desired MMD register address */
142 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
143 if (ret < 0)
144 goto err;
145
146 /* Select the Function : DATA with no post increment */
147 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
148 if (ret < 0)
149 goto err;
150
151 /* Read the content of the MMD's selected register */
152 value = bus->read(bus, 0, MII_MMD_DATA);
153
154 return value;
155err:
156 dev_err(&bus->dev, "failed to read mmd register\n");
157
158 return ret;
159}
160
161static int
162core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
163 int devad, u32 data)
164{
165 struct mii_bus *bus = priv->bus;
166 int ret;
167
168 /* Write the desired MMD Devad */
169 ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
170 if (ret < 0)
171 goto err;
172
173 /* Write the desired MMD register address */
174 ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
175 if (ret < 0)
176 goto err;
177
178 /* Select the Function : DATA with no post increment */
179 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
180 if (ret < 0)
181 goto err;
182
183 /* Write the data into MMD's selected register */
184 ret = bus->write(bus, 0, MII_MMD_DATA, data);
185err:
186 if (ret < 0)
187 dev_err(&bus->dev,
188 "failed to write mmd register\n");
189 return ret;
190}
191
192static void
193core_write(struct mt7530_priv *priv, u32 reg, u32 val)
194{
195 struct mii_bus *bus = priv->bus;
196
197 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
198
199 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
200
201 mutex_unlock(&bus->mdio_lock);
202}
203
204static void
205core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
206{
207 struct mii_bus *bus = priv->bus;
208 u32 val;
209
210 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
211
212 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
213 val &= ~mask;
214 val |= set;
215 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
216
217 mutex_unlock(&bus->mdio_lock);
218}
219
220static void
221core_set(struct mt7530_priv *priv, u32 reg, u32 val)
222{
223 core_rmw(priv, reg, 0, val);
224}
225
226static void
227core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
228{
229 core_rmw(priv, reg, val, 0);
230}
231
232static int
233mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
234{
235 struct mii_bus *bus = priv->bus;
236 u16 page, r, lo, hi;
237 int ret;
238
239 page = (reg >> 6) & 0x3ff;
240 r = (reg >> 2) & 0xf;
241 lo = val & 0xffff;
242 hi = val >> 16;
243
244 /* MT7530 uses 31 as the pseudo port */
245 ret = bus->write(bus, 0x1f, 0x1f, page);
246 if (ret < 0)
247 goto err;
248
249 ret = bus->write(bus, 0x1f, r, lo);
250 if (ret < 0)
251 goto err;
252
253 ret = bus->write(bus, 0x1f, 0x10, hi);
254err:
255 if (ret < 0)
256 dev_err(&bus->dev,
257 "failed to write mt7530 register\n");
258 return ret;
259}
260
261static u32
262mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
263{
264 struct mii_bus *bus = priv->bus;
265 u16 page, r, lo, hi;
266 int ret;
267
268 page = (reg >> 6) & 0x3ff;
269 r = (reg >> 2) & 0xf;
270
271 /* MT7530 uses 31 as the pseudo port */
272 ret = bus->write(bus, 0x1f, 0x1f, page);
273 if (ret < 0) {
274 dev_err(&bus->dev,
275 "failed to read mt7530 register\n");
276 return ret;
277 }
278
279 lo = bus->read(bus, 0x1f, r);
280 hi = bus->read(bus, 0x1f, 0x10);
281
282 return (hi << 16) | (lo & 0xffff);
283}
284
285static void
286mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
287{
288 struct mii_bus *bus = priv->bus;
289
290 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
291
292 mt7530_mii_write(priv, reg, val);
293
294 mutex_unlock(&bus->mdio_lock);
295}
296
297static u32
298_mt7530_read(struct mt7530_dummy_poll *p)
299{
300 struct mii_bus *bus = p->priv->bus;
301 u32 val;
302
303 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
304
305 val = mt7530_mii_read(p->priv, p->reg);
306
307 mutex_unlock(&bus->mdio_lock);
308
309 return val;
310}
311
312static u32
313mt7530_read(struct mt7530_priv *priv, u32 reg)
314{
315 struct mt7530_dummy_poll p;
316
317 INIT_MT7530_DUMMY_POLL(&p, priv, reg);
318 return _mt7530_read(&p);
319}
320
321static void
322mt7530_rmw(struct mt7530_priv *priv, u32 reg,
323 u32 mask, u32 set)
324{
325 struct mii_bus *bus = priv->bus;
326 u32 val;
327
328 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
329
330 val = mt7530_mii_read(priv, reg);
331 val &= ~mask;
332 val |= set;
333 mt7530_mii_write(priv, reg, val);
334
335 mutex_unlock(&bus->mdio_lock);
336}
337
338static void
339mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
340{
341 mt7530_rmw(priv, reg, 0, val);
342}
343
344static void
345mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
346{
347 mt7530_rmw(priv, reg, val, 0);
348}
349
350static int
351mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
352{
353 u32 val;
354 int ret;
355 struct mt7530_dummy_poll p;
356
357 /* Set the command operating upon the MAC address entries */
358 val = ATC_BUSY | ATC_MAT(0) | cmd;
359 mt7530_write(priv, MT7530_ATC, val);
360
361 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
362 ret = readx_poll_timeout(_mt7530_read, &p, val,
363 !(val & ATC_BUSY), 20, 20000);
364 if (ret < 0) {
365 dev_err(priv->dev, "reset timeout\n");
366 return ret;
367 }
368
369 /* Additional sanity for read command if the specified
370 * entry is invalid
371 */
372 val = mt7530_read(priv, MT7530_ATC);
373 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
374 return -EINVAL;
375
376 if (rsp)
377 *rsp = val;
378
379 return 0;
380}
381
382static void
383mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
384{
385 u32 reg[3];
386 int i;
387
388 /* Read from ARL table into an array */
389 for (i = 0; i < 3; i++) {
390 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
391
392 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
393 __func__, __LINE__, i, reg[i]);
394 }
395
396 fdb->vid = (reg[1] >> CVID) & CVID_MASK;
397 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
398 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
399 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
400 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
401 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
402 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
403 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
404 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
405 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
406}
407
408static void
409mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
410 u8 port_mask, const u8 *mac,
411 u8 aging, u8 type)
412{
413 u32 reg[3] = { 0 };
414 int i;
415
416 reg[1] |= vid & CVID_MASK;
417 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
418 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
419 /* STATIC_ENT indicate that entry is static wouldn't
420 * be aged out and STATIC_EMP specified as erasing an
421 * entry
422 */
423 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
424 reg[1] |= mac[5] << MAC_BYTE_5;
425 reg[1] |= mac[4] << MAC_BYTE_4;
426 reg[0] |= mac[3] << MAC_BYTE_3;
427 reg[0] |= mac[2] << MAC_BYTE_2;
428 reg[0] |= mac[1] << MAC_BYTE_1;
429 reg[0] |= mac[0] << MAC_BYTE_0;
430
431 /* Write array into the ARL table */
432 for (i = 0; i < 3; i++)
433 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
434}
435
436static int
437mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
438{
439 struct mt7530_priv *priv = ds->priv;
440 u32 ncpo1, ssc_delta, trgint, i;
441
442 switch (mode) {
443 case PHY_INTERFACE_MODE_RGMII:
444 trgint = 0;
445 ncpo1 = 0x0c80;
446 ssc_delta = 0x87;
447 break;
448 case PHY_INTERFACE_MODE_TRGMII:
449 trgint = 1;
450 ncpo1 = 0x1400;
451 ssc_delta = 0x57;
452 break;
453 default:
454 dev_err(priv->dev, "xMII mode %d not supported\n", mode);
455 return -EINVAL;
456 }
457
458 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
459 P6_INTF_MODE(trgint));
460
461 /* Lower Tx Driving for TRGMII path */
462 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
463 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
464 TD_DM_DRVP(8) | TD_DM_DRVN(8));
465
466 /* Setup core clock for MT7530 */
467 if (!trgint) {
468 /* Disable MT7530 core clock */
469 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
470
471 /* Disable PLL, since phy_device has not yet been created
472 * provided for phy_[read,write]_mmd_indirect is called, we
473 * provide our own core_write_mmd_indirect to complete this
474 * function.
475 */
476 core_write_mmd_indirect(priv,
477 CORE_GSWPLL_GRP1,
478 MDIO_MMD_VEND2,
479 0);
480
481 /* Set core clock into 500Mhz */
482 core_write(priv, CORE_GSWPLL_GRP2,
483 RG_GSWPLL_POSDIV_500M(1) |
484 RG_GSWPLL_FBKDIV_500M(25));
485
486 /* Enable PLL */
487 core_write(priv, CORE_GSWPLL_GRP1,
488 RG_GSWPLL_EN_PRE |
489 RG_GSWPLL_POSDIV_200M(2) |
490 RG_GSWPLL_FBKDIV_200M(32));
491
492 /* Enable MT7530 core clock */
493 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
494 }
495
496 /* Setup the MT7530 TRGMII Tx Clock */
497 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
498 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
499 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
500 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
501 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
502 core_write(priv, CORE_PLL_GROUP4,
503 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
504 RG_SYSPLL_BIAS_LPF_EN);
505 core_write(priv, CORE_PLL_GROUP2,
506 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
507 RG_SYSPLL_POSDIV(1));
508 core_write(priv, CORE_PLL_GROUP7,
509 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
510 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
511 core_set(priv, CORE_TRGMII_GSW_CLK_CG,
512 REG_GSWCK_EN | REG_TRGMIICK_EN);
513
514 if (!trgint)
515 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
516 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
517 RD_TAP_MASK, RD_TAP(16));
518 else
519 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
520
521 return 0;
522}
523
524static int
525mt7623_pad_clk_setup(struct dsa_switch *ds)
526{
527 struct mt7530_priv *priv = ds->priv;
528 int i;
529
530 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
531 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
532 TD_DM_DRVP(8) | TD_DM_DRVN(8));
533
534 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL);
535 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
536
537 return 0;
538}
539
540static void
541mt7530_mib_reset(struct dsa_switch *ds)
542{
543 struct mt7530_priv *priv = ds->priv;
544
545 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
546 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
547}
548
549static void
550mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable)
551{
552 u32 mask = PMCR_TX_EN | PMCR_RX_EN;
553
554 if (enable)
555 mt7530_set(priv, MT7530_PMCR_P(port), mask);
556 else
557 mt7530_clear(priv, MT7530_PMCR_P(port), mask);
558}
559
560static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
561{
562 struct mt7530_priv *priv = ds->priv;
563
564 return mdiobus_read_nested(priv->bus, port, regnum);
565}
566
360cc342
CIK		 567static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
568 u16 val)
b8f126a8
SW		 569{
570 struct mt7530_priv *priv = ds->priv;
571
572 return mdiobus_write_nested(priv->bus, port, regnum, val);
573}
574
575static void
576mt7530_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
577{
578 int i;
579
580 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
581 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
582 ETH_GSTRING_LEN);
583}
584
585static void
586mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
587 uint64_t *data)
588{
589 struct mt7530_priv *priv = ds->priv;
590 const struct mt7530_mib_desc *mib;
591 u32 reg, i;
592 u64 hi;
593
594 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
595 mib = &mt7530_mib[i];
596 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
597
598 data[i] = mt7530_read(priv, reg);
599 if (mib->size == 2) {
600 hi = mt7530_read(priv, reg + 4);
601 data[i] |= hi << 32;
602 }
603 }
604}
605
606static int
88c06054 607mt7530_get_sset_count(struct dsa_switch *ds, int port)
b8f126a8
SW		 608{
609 return ARRAY_SIZE(mt7530_mib);
610}
611
612static void mt7530_adjust_link(struct dsa_switch *ds, int port,
613 struct phy_device *phydev)
614{
615 struct mt7530_priv *priv = ds->priv;
616
617 if (phy_is_pseudo_fixed_link(phydev)) {
618 dev_dbg(priv->dev, "phy-mode for master device = %x\n",
619 phydev->interface);
620
621 /* Setup TX circuit incluing relevant PAD and driving */
622 mt7530_pad_clk_setup(ds, phydev->interface);
623
624 /* Setup RX circuit, relevant PAD and driving on the host
625 * which must be placed after the setup on the device side is
626 * all finished.
627 */
628 mt7623_pad_clk_setup(ds);
8e6f1521
JC		 629 } else {
630 u16 lcl_adv = 0, rmt_adv = 0;
631 u8 flowctrl;
632 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
633
634 switch (phydev->speed) {
635 case SPEED_1000:
636 mcr |= PMCR_FORCE_SPEED_1000;
637 break;
638 case SPEED_100:
639 mcr |= PMCR_FORCE_SPEED_100;
640 break;
641 };
642
643 if (phydev->link)
644 mcr |= PMCR_FORCE_LNK;
645
646 if (phydev->duplex) {
647 mcr |= PMCR_FORCE_FDX;
648
649 if (phydev->pause)
650 rmt_adv = LPA_PAUSE_CAP;
651 if (phydev->asym_pause)
652 rmt_adv |= LPA_PAUSE_ASYM;
653
654 if (phydev->advertising & ADVERTISED_Pause)
655 lcl_adv |= ADVERTISE_PAUSE_CAP;
656 if (phydev->advertising & ADVERTISED_Asym_Pause)
657 lcl_adv |= ADVERTISE_PAUSE_ASYM;
658
659 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
660
661 if (flowctrl & FLOW_CTRL_TX)
662 mcr |= PMCR_TX_FC_EN;
663 if (flowctrl & FLOW_CTRL_RX)
664 mcr |= PMCR_RX_FC_EN;
665 }
666 mt7530_write(priv, MT7530_PMCR_P(port), mcr);
b8f126a8
SW		 667 }
668}
669
670static int
671mt7530_cpu_port_enable(struct mt7530_priv *priv,
672 int port)
673{
674 /* Enable Mediatek header mode on the cpu port */
675 mt7530_write(priv, MT7530_PVC_P(port),
676 PORT_SPEC_TAG);
677
678 /* Setup the MAC by default for the cpu port */
679 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
680
681 /* Disable auto learning on the cpu port */
682 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
683
684 /* Unknown unicast frame fordwarding to the cpu port */
685 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port)));
686
687 /* CPU port gets connected to all user ports of
688 * the switch
689 */
690 mt7530_write(priv, MT7530_PCR_P(port),
02bc6e54 691 PCR_MATRIX(dsa_user_ports(priv->ds)));
b8f126a8
SW		 692
693 return 0;
694}
695
696static int
697mt7530_port_enable(struct dsa_switch *ds, int port,
698 struct phy_device *phy)
699{
700 struct mt7530_priv *priv = ds->priv;
701
702 mutex_lock(&priv->reg_mutex);
703
704 /* Setup the MAC for the user port */
705 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK);
706
707 /* Allow the user port gets connected to the cpu port and also
708 * restore the port matrix if the port is the member of a certain
709 * bridge.
710 */
711 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
712 priv->ports[port].enable = true;
713 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
714 priv->ports[port].pm);
715 mt7530_port_set_status(priv, port, 1);
716
717 mutex_unlock(&priv->reg_mutex);
718
719 return 0;
720}
721
722static void
723mt7530_port_disable(struct dsa_switch *ds, int port,
724 struct phy_device *phy)
725{
726 struct mt7530_priv *priv = ds->priv;
727
728 mutex_lock(&priv->reg_mutex);
729
730 /* Clear up all port matrix which could be restored in the next
731 * enablement for the port.
732 */
733 priv->ports[port].enable = false;
734 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
735 PCR_MATRIX_CLR);
736 mt7530_port_set_status(priv, port, 0);
737
738 mutex_unlock(&priv->reg_mutex);
739}
740
741static void
742mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
743{
744 struct mt7530_priv *priv = ds->priv;
745 u32 stp_state;
746
747 switch (state) {
748 case BR_STATE_DISABLED:
749 stp_state = MT7530_STP_DISABLED;
750 break;
751 case BR_STATE_BLOCKING:
752 stp_state = MT7530_STP_BLOCKING;
753 break;
754 case BR_STATE_LISTENING:
755 stp_state = MT7530_STP_LISTENING;
756 break;
757 case BR_STATE_LEARNING:
758 stp_state = MT7530_STP_LEARNING;
759 break;
760 case BR_STATE_FORWARDING:
761 default:
762 stp_state = MT7530_STP_FORWARDING;
763 break;
764 }
765
766 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
767}
768
769static int
770mt7530_port_bridge_join(struct dsa_switch *ds, int port,
771 struct net_device *bridge)
772{
773 struct mt7530_priv *priv = ds->priv;
774 u32 port_bitmap = BIT(MT7530_CPU_PORT);
775 int i;
776
777 mutex_lock(&priv->reg_mutex);
778
779 for (i = 0; i < MT7530_NUM_PORTS; i++) {
780 /* Add this port to the port matrix of the other ports in the
781 * same bridge. If the port is disabled, port matrix is kept
782 * and not being setup until the port becomes enabled.
783 */
4a5b85ff 784 if (dsa_is_user_port(ds, i) && i != port) {
c8652c83 785 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 786 continue;
787 if (priv->ports[i].enable)
788 mt7530_set(priv, MT7530_PCR_P(i),
789 PCR_MATRIX(BIT(port)));
790 priv->ports[i].pm |= PCR_MATRIX(BIT(port));
791
792 port_bitmap |= BIT(i);
793 }
794 }
795
796 /* Add the all other ports to this port matrix. */
797 if (priv->ports[port].enable)
798 mt7530_rmw(priv, MT7530_PCR_P(port),
799 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
800 priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
801
802 mutex_unlock(&priv->reg_mutex);
803
804 return 0;
805}
806
83163f7d
SW		 807static void
808mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
809{
810 struct mt7530_priv *priv = ds->priv;
811 bool all_user_ports_removed = true;
812 int i;
813
814 /* When a port is removed from the bridge, the port would be set up
815 * back to the default as is at initial boot which is a VLAN-unaware
816 * port.
817 */
818 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
819 MT7530_PORT_MATRIX_MODE);
820 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
821 VLAN_ATTR(MT7530_VLAN_TRANSPARENT));
822
823 priv->ports[port].vlan_filtering = false;
824
825 for (i = 0; i < MT7530_NUM_PORTS; i++) {
826 if (dsa_is_user_port(ds, i) &&
827 priv->ports[i].vlan_filtering) {
828 all_user_ports_removed = false;
829 break;
830 }
831 }
832
833 /* CPU port also does the same thing until all user ports belonging to
834 * the CPU port get out of VLAN filtering mode.
835 */
836 if (all_user_ports_removed) {
837 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
838 PCR_MATRIX(dsa_user_ports(priv->ds)));
839 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT),
840 PORT_SPEC_TAG);
841 }
842}
843
844static void
845mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
846{
847 struct mt7530_priv *priv = ds->priv;
848
849 /* The real fabric path would be decided on the membership in the
850 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS
851 * means potential VLAN can be consisting of certain subset of all
852 * ports.
853 */
854 mt7530_rmw(priv, MT7530_PCR_P(port),
855 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS));
856
857 /* Trapped into security mode allows packet forwarding through VLAN
858 * table lookup.
859 */
860 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
861 MT7530_PORT_SECURITY_MODE);
862
863 /* Set the port as a user port which is to be able to recognize VID
864 * from incoming packets before fetching entry within the VLAN table.
865 */
866 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK,
867 VLAN_ATTR(MT7530_VLAN_USER));
868}
869
b8f126a8
SW		 870static void
871mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
872 struct net_device *bridge)
873{
874 struct mt7530_priv *priv = ds->priv;
875 int i;
876
877 mutex_lock(&priv->reg_mutex);
878
879 for (i = 0; i < MT7530_NUM_PORTS; i++) {
880 /* Remove this port from the port matrix of the other ports
881 * in the same bridge. If the port is disabled, port matrix
882 * is kept and not being setup until the port becomes enabled.
83163f7d
SW		 883 * And the other port's port matrix cannot be broken when the
884 * other port is still a VLAN-aware port.
b8f126a8 885 */
83163f7d
SW		 886 if (!priv->ports[i].vlan_filtering &&
887 dsa_is_user_port(ds, i) && i != port) {
c8652c83 888 if (dsa_to_port(ds, i)->bridge_dev != bridge)
b8f126a8
SW		 889 continue;
890 if (priv->ports[i].enable)
891 mt7530_clear(priv, MT7530_PCR_P(i),
892 PCR_MATRIX(BIT(port)));
893 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
894 }
895 }
896
897 /* Set the cpu port to be the only one in the port matrix of
898 * this port.
899 */
900 if (priv->ports[port].enable)
901 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
902 PCR_MATRIX(BIT(MT7530_CPU_PORT)));
903 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
904
83163f7d
SW		 905 mt7530_port_set_vlan_unaware(ds, port);
906
b8f126a8
SW		 907 mutex_unlock(&priv->reg_mutex);
908}
909
910static int
b8f126a8 911mt7530_port_fdb_add(struct dsa_switch *ds, int port,
6c2c1dcb 912 const unsigned char *addr, u16 vid)
b8f126a8
SW		 913{
914 struct mt7530_priv *priv = ds->priv;
1b6dd556 915 int ret;
b8f126a8
SW		 916 u8 port_mask = BIT(port);
917
918 mutex_lock(&priv->reg_mutex);
6c2c1dcb 919 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
18bd5949 920 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8 921 mutex_unlock(&priv->reg_mutex);
1b6dd556
AS		 922
923 return ret;
b8f126a8
SW		 924}
925
926static int
927mt7530_port_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 928 const unsigned char *addr, u16 vid)
b8f126a8
SW		 929{
930 struct mt7530_priv *priv = ds->priv;
931 int ret;
932 u8 port_mask = BIT(port);
933
934 mutex_lock(&priv->reg_mutex);
6c2c1dcb 935 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
18bd5949 936 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
b8f126a8
SW		 937 mutex_unlock(&priv->reg_mutex);
938
939 return ret;
940}
941
942static int
943mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 944 dsa_fdb_dump_cb_t *cb, void *data)
b8f126a8
SW		 945{
946 struct mt7530_priv *priv = ds->priv;
947 struct mt7530_fdb _fdb = { 0 };
948 int cnt = MT7530_NUM_FDB_RECORDS;
949 int ret = 0;
950 u32 rsp = 0;
951
952 mutex_lock(&priv->reg_mutex);
953
954 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
955 if (ret < 0)
956 goto err;
957
958 do {
959 if (rsp & ATC_SRCH_HIT) {
960 mt7530_fdb_read(priv, &_fdb);
961 if (_fdb.port_mask & BIT(port)) {
2bedde1a
AS		 962 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
963 data);
b8f126a8
SW		 964 if (ret < 0)
965 break;
966 }
967 }
968 } while (--cnt &&
969 !(rsp & ATC_SRCH_END) &&
970 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
971err:
972 mutex_unlock(&priv->reg_mutex);
973
974 return 0;
975}
976
83163f7d
SW		 977static int
978mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
979{
980 struct mt7530_dummy_poll p;
981 u32 val;
982 int ret;
983
984 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
985 mt7530_write(priv, MT7530_VTCR, val);
986
987 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
988 ret = readx_poll_timeout(_mt7530_read, &p, val,
989 !(val & VTCR_BUSY), 20, 20000);
990 if (ret < 0) {
991 dev_err(priv->dev, "poll timeout\n");
992 return ret;
993 }
994
995 val = mt7530_read(priv, MT7530_VTCR);
996 if (val & VTCR_INVALID) {
997 dev_err(priv->dev, "read VTCR invalid\n");
998 return -EINVAL;
999 }
1000
1001 return 0;
1002}
1003
1004static int
1005mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
1006 bool vlan_filtering)
1007{
1008 struct mt7530_priv *priv = ds->priv;
1009
1010 priv->ports[port].vlan_filtering = vlan_filtering;
1011
1012 if (vlan_filtering) {
1013 /* The port is being kept as VLAN-unaware port when bridge is
1014 * set up with vlan_filtering not being set, Otherwise, the
1015 * port and the corresponding CPU port is required the setup
1016 * for becoming a VLAN-aware port.
1017 */
1018 mt7530_port_set_vlan_aware(ds, port);
1019 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
1020 }
1021
1022 return 0;
1023}
1024
1025static int
1026mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
1027 const struct switchdev_obj_port_vlan *vlan)
1028{
1029 /* nothing needed */
1030
1031 return 0;
1032}
1033
1034static void
1035mt7530_hw_vlan_add(struct mt7530_priv *priv,
1036 struct mt7530_hw_vlan_entry *entry)
1037{
1038 u8 new_members;
1039 u32 val;
1040
1041 new_members = entry->old_members | BIT(entry->port) |
1042 BIT(MT7530_CPU_PORT);
1043
1044 /* Validate the entry with independent learning, create egress tag per
1045 * VLAN and joining the port as one of the port members.
1046 */
1047 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
1048 mt7530_write(priv, MT7530_VAWD1, val);
1049
1050 /* Decide whether adding tag or not for those outgoing packets from the
1051 * port inside the VLAN.
1052 */
1053 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
1054 MT7530_VLAN_EGRESS_TAG;
1055 mt7530_rmw(priv, MT7530_VAWD2,
1056 ETAG_CTRL_P_MASK(entry->port),
1057 ETAG_CTRL_P(entry->port, val));
1058
1059 /* CPU port is always taken as a tagged port for serving more than one
1060 * VLANs across and also being applied with egress type stack mode for
1061 * that VLAN tags would be appended after hardware special tag used as
1062 * DSA tag.
1063 */
1064 mt7530_rmw(priv, MT7530_VAWD2,
1065 ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
1066 ETAG_CTRL_P(MT7530_CPU_PORT,
1067 MT7530_VLAN_EGRESS_STACK));
1068}
1069
1070static void
1071mt7530_hw_vlan_del(struct mt7530_priv *priv,
1072 struct mt7530_hw_vlan_entry *entry)
1073{
1074 u8 new_members;
1075 u32 val;
1076
1077 new_members = entry->old_members & ~BIT(entry->port);
1078
1079 val = mt7530_read(priv, MT7530_VAWD1);
1080 if (!(val & VLAN_VALID)) {
1081 dev_err(priv->dev,
1082 "Cannot be deleted due to invalid entry\n");
1083 return;
1084 }
1085
1086 /* If certain member apart from CPU port is still alive in the VLAN,
1087 * the entry would be kept valid. Otherwise, the entry is got to be
1088 * disabled.
1089 */
1090 if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
1091 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
1092 VLAN_VALID;
1093 mt7530_write(priv, MT7530_VAWD1, val);
1094 } else {
1095 mt7530_write(priv, MT7530_VAWD1, 0);
1096 mt7530_write(priv, MT7530_VAWD2, 0);
1097 }
1098}
1099
1100static void
1101mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
1102 struct mt7530_hw_vlan_entry *entry,
1103 mt7530_vlan_op vlan_op)
1104{
1105 u32 val;
1106
1107 /* Fetch entry */
1108 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
1109
1110 val = mt7530_read(priv, MT7530_VAWD1);
1111
1112 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
1113
1114 /* Manipulate entry */
1115 vlan_op(priv, entry);
1116
1117 /* Flush result to hardware */
1118 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
1119}
1120
1121static void
1122mt7530_port_vlan_add(struct dsa_switch *ds, int port,
1123 const struct switchdev_obj_port_vlan *vlan)
1124{
1125 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1126 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1127 struct mt7530_hw_vlan_entry new_entry;
1128 struct mt7530_priv *priv = ds->priv;
1129 u16 vid;
1130
1131 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1132 * being set.
1133 */
1134 if (!priv->ports[port].vlan_filtering)
1135 return;
1136
1137 mutex_lock(&priv->reg_mutex);
1138
1139 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1140 mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
1141 mt7530_hw_vlan_update(priv, vid, &new_entry,
1142 mt7530_hw_vlan_add);
1143 }
1144
1145 if (pvid) {
1146 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
1147 G0_PORT_VID(vlan->vid_end));
1148 priv->ports[port].pvid = vlan->vid_end;
1149 }
1150
1151 mutex_unlock(&priv->reg_mutex);
1152}
1153
1154static int
1155mt7530_port_vlan_del(struct dsa_switch *ds, int port,
1156 const struct switchdev_obj_port_vlan *vlan)
1157{
1158 struct mt7530_hw_vlan_entry target_entry;
1159 struct mt7530_priv *priv = ds->priv;
1160 u16 vid, pvid;
1161
1162 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not
1163 * being set.
1164 */
1165 if (!priv->ports[port].vlan_filtering)
1166 return 0;
1167
1168 mutex_lock(&priv->reg_mutex);
1169
1170 pvid = priv->ports[port].pvid;
1171 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1172 mt7530_hw_vlan_entry_init(&target_entry, port, 0);
1173 mt7530_hw_vlan_update(priv, vid, &target_entry,
1174 mt7530_hw_vlan_del);
1175
1176 /* PVID is being restored to the default whenever the PVID port
1177 * is being removed from the VLAN.
1178 */
1179 if (pvid == vid)
1180 pvid = G0_PORT_VID_DEF;
1181 }
1182
1183 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
1184 priv->ports[port].pvid = pvid;
1185
1186 mutex_unlock(&priv->reg_mutex);
1187
1188 return 0;
1189}
1190
b8f126a8 1191static enum dsa_tag_protocol
5ed4e3eb 1192mtk_get_tag_protocol(struct dsa_switch *ds, int port)
b8f126a8
SW		 1193{
1194 struct mt7530_priv *priv = ds->priv;
1195
5ed4e3eb 1196 if (port != MT7530_CPU_PORT) {
b8f126a8
SW		 1197 dev_warn(priv->dev,
1198 "port not matched with tagging CPU port\n");
1199 return DSA_TAG_PROTO_NONE;
1200 } else {
1201 return DSA_TAG_PROTO_MTK;
1202 }
1203}
1204
1205static int
1206mt7530_setup(struct dsa_switch *ds)
1207{
1208 struct mt7530_priv *priv = ds->priv;
1209 int ret, i;
1210 u32 id, val;
1211 struct device_node *dn;
1212 struct mt7530_dummy_poll p;
1213
0abfd494 1214 /* The parent node of master netdev which holds the common system
b8f126a8
SW		 1215 * controller also is the container for two GMACs nodes representing
1216 * as two netdev instances.
1217 */
f8b8b1cd 1218 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent;
b8f126a8
SW		 1219 priv->ethernet = syscon_node_to_regmap(dn);
1220 if (IS_ERR(priv->ethernet))
1221 return PTR_ERR(priv->ethernet);
1222
1223 regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
1224 ret = regulator_enable(priv->core_pwr);
1225 if (ret < 0) {
1226 dev_err(priv->dev,
1227 "Failed to enable core power: %d\n", ret);
1228 return ret;
1229 }
1230
1231 regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
1232 ret = regulator_enable(priv->io_pwr);
1233 if (ret < 0) {
1234 dev_err(priv->dev, "Failed to enable io pwr: %d\n",
1235 ret);
1236 return ret;
1237 }
1238
1239 /* Reset whole chip through gpio pin or memory-mapped registers for
1240 * different type of hardware
1241 */
1242 if (priv->mcm) {
1243 reset_control_assert(priv->rstc);
1244 usleep_range(1000, 1100);
1245 reset_control_deassert(priv->rstc);
1246 } else {
1247 gpiod_set_value_cansleep(priv->reset, 0);
1248 usleep_range(1000, 1100);
1249 gpiod_set_value_cansleep(priv->reset, 1);
1250 }
1251
1252 /* Waiting for MT7530 got to stable */
1253 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
1254 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
1255 20, 1000000);
1256 if (ret < 0) {
1257 dev_err(priv->dev, "reset timeout\n");
1258 return ret;
1259 }
1260
1261 id = mt7530_read(priv, MT7530_CREV);
1262 id >>= CHIP_NAME_SHIFT;
1263 if (id != MT7530_ID) {
1264 dev_err(priv->dev, "chip %x can't be supported\n", id);
1265 return -ENODEV;
1266 }
1267
1268 /* Reset the switch through internal reset */
1269 mt7530_write(priv, MT7530_SYS_CTRL,
1270 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
1271 SYS_CTRL_REG_RST);
1272
1273 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
1274 val = mt7530_read(priv, MT7530_MHWTRAP);
1275 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
1276 val |= MHWTRAP_MANUAL;
1277 mt7530_write(priv, MT7530_MHWTRAP, val);
1278
1279 /* Enable and reset MIB counters */
1280 mt7530_mib_reset(ds);
1281
1282 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK);
1283
1284 for (i = 0; i < MT7530_NUM_PORTS; i++) {
1285 /* Disable forwarding by default on all ports */
1286 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
1287 PCR_MATRIX_CLR);
1288
1289 if (dsa_is_cpu_port(ds, i))
1290 mt7530_cpu_port_enable(priv, i);
1291 else
1292 mt7530_port_disable(ds, i, NULL);
1293 }
1294
1295 /* Flush the FDB table */
18bd5949 1296 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
b8f126a8
SW		 1297 if (ret < 0)
1298 return ret;
1299
1300 return 0;
1301}
1302
d78d6776 1303static const struct dsa_switch_ops mt7530_switch_ops = {
b8f126a8
SW		 1304 .get_tag_protocol = mtk_get_tag_protocol,
1305 .setup = mt7530_setup,
1306 .get_strings = mt7530_get_strings,
1307 .phy_read = mt7530_phy_read,
1308 .phy_write = mt7530_phy_write,
1309 .get_ethtool_stats = mt7530_get_ethtool_stats,
1310 .get_sset_count = mt7530_get_sset_count,
1311 .adjust_link = mt7530_adjust_link,
1312 .port_enable = mt7530_port_enable,
1313 .port_disable = mt7530_port_disable,
1314 .port_stp_state_set = mt7530_stp_state_set,
1315 .port_bridge_join = mt7530_port_bridge_join,
1316 .port_bridge_leave = mt7530_port_bridge_leave,
b8f126a8
SW		 1317 .port_fdb_add = mt7530_port_fdb_add,
1318 .port_fdb_del = mt7530_port_fdb_del,
1319 .port_fdb_dump = mt7530_port_fdb_dump,
83163f7d
SW		 1320 .port_vlan_filtering = mt7530_port_vlan_filtering,
1321 .port_vlan_prepare = mt7530_port_vlan_prepare,
1322 .port_vlan_add = mt7530_port_vlan_add,
1323 .port_vlan_del = mt7530_port_vlan_del,
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SW		 1324};
1325
1326static int
1327mt7530_probe(struct mdio_device *mdiodev)
1328{
1329 struct mt7530_priv *priv;
1330 struct device_node *dn;
1331
1332 dn = mdiodev->dev.of_node;
1333
1334 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1335 if (!priv)
1336 return -ENOMEM;
1337
1338 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
1339 if (!priv->ds)
1340 return -ENOMEM;
1341
1342 /* Use medatek,mcm property to distinguish hardware type that would
1343 * casues a little bit differences on power-on sequence.
1344 */
1345 priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
1346 if (priv->mcm) {
1347 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
1348
1349 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
1350 if (IS_ERR(priv->rstc)) {
1351 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1352 return PTR_ERR(priv->rstc);
1353 }
1354 }
1355
1356 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
1357 if (IS_ERR(priv->core_pwr))
1358 return PTR_ERR(priv->core_pwr);
1359
1360 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
1361 if (IS_ERR(priv->io_pwr))
1362 return PTR_ERR(priv->io_pwr);
1363
1364 /* Not MCM that indicates switch works as the remote standalone
1365 * integrated circuit so the GPIO pin would be used to complete
1366 * the reset, otherwise memory-mapped register accessing used
1367 * through syscon provides in the case of MCM.
1368 */
1369 if (!priv->mcm) {
1370 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
1371 GPIOD_OUT_LOW);
1372 if (IS_ERR(priv->reset)) {
1373 dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
1374 return PTR_ERR(priv->reset);
1375 }
1376 }
1377
1378 priv->bus = mdiodev->bus;
1379 priv->dev = &mdiodev->dev;
1380 priv->ds->priv = priv;
1381 priv->ds->ops = &mt7530_switch_ops;
1382 mutex_init(&priv->reg_mutex);
1383 dev_set_drvdata(&mdiodev->dev, priv);
1384
23c9ee49 1385 return dsa_register_switch(priv->ds);
b8f126a8
SW		 1386}
1387
1388static void
1389mt7530_remove(struct mdio_device *mdiodev)
1390{
1391 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
1392 int ret = 0;
1393
1394 ret = regulator_disable(priv->core_pwr);
1395 if (ret < 0)
1396 dev_err(priv->dev,
1397 "Failed to disable core power: %d\n", ret);
1398
1399 ret = regulator_disable(priv->io_pwr);
1400 if (ret < 0)
1401 dev_err(priv->dev, "Failed to disable io pwr: %d\n",
1402 ret);
1403
1404 dsa_unregister_switch(priv->ds);
1405 mutex_destroy(&priv->reg_mutex);
1406}
1407
1408static const struct of_device_id mt7530_of_match[] = {
1409 { .compatible = "mediatek,mt7530" },
1410 { /* sentinel */ },
1411};
3c82b372 1412MODULE_DEVICE_TABLE(of, mt7530_of_match);
b8f126a8
SW		 1413
1414static struct mdio_driver mt7530_mdio_driver = {
1415 .probe = mt7530_probe,
1416 .remove = mt7530_remove,
1417 .mdiodrv.driver = {
1418 .name = "mt7530",
1419 .of_match_table = mt7530_of_match,
1420 },
1421};
1422
1423mdio_module_driver(mt7530_mdio_driver);
1424
1425MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
1426MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
1427MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)