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net: dsa: microchip: ksz9477: Add Wake on Magic Packet support
[linux-2.6-block.git] / drivers / net / dsa / microchip / ksz_common.c
CommitLineData
5b79c72e 1// SPDX-License-Identifier: GPL-2.0
b987e98e
WH		 2/*
3 * Microchip switch driver main logic
4 *
42fc6a4c 5 * Copyright (C) 2017-2019 Microchip Technology Inc.
b987e98e
WH		 6 */
7
8#include <linux/delay.h>
ab32f56a 9#include <linux/dsa/ksz_common.h>
b987e98e 10#include <linux/export.h>
924352c3 11#include <linux/gpio/consumer.h>
b987e98e
WH		 12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/platform_data/microchip-ksz.h>
15#include <linux/phy.h>
16#include <linux/etherdevice.h>
17#include <linux/if_bridge.h>
838c19f8 18#include <linux/if_vlan.h>
2d61298f 19#include <linux/if_hsr.h>
ff319a64
AR		 20#include <linux/irq.h>
21#include <linux/irqdomain.h>
f44a9010 22#include <linux/of.h>
ff319a64 23#include <linux/of_mdio.h>
c2e86691 24#include <linux/of_net.h>
1fe94f54 25#include <linux/micrel_phy.h>
b987e98e 26#include <net/dsa.h>
71d7920f 27#include <net/pkt_cls.h>
b987e98e
WH		 28#include <net/switchdev.h>
29
ffc60b55 30#include "ksz_common.h"
eac1ea20 31#include "ksz_ptp.h"
6ec23aaa
AR		 32#include "ksz8.h"
33#include "ksz9477.h"
55ab6ffa 34#include "lan937x.h"
7049f9b5 35
a530e6f2
AR		 36#define MIB_COUNTER_NUM 0x20
37
c6101dd7
AR		 38struct ksz_stats_raw {
39 u64 rx_hi;
40 u64 rx_undersize;
41 u64 rx_fragments;
42 u64 rx_oversize;
43 u64 rx_jabbers;
44 u64 rx_symbol_err;
45 u64 rx_crc_err;
46 u64 rx_align_err;
47 u64 rx_mac_ctrl;
48 u64 rx_pause;
49 u64 rx_bcast;
50 u64 rx_mcast;
51 u64 rx_ucast;
52 u64 rx_64_or_less;
53 u64 rx_65_127;
54 u64 rx_128_255;
55 u64 rx_256_511;
56 u64 rx_512_1023;
57 u64 rx_1024_1522;
58 u64 rx_1523_2000;
59 u64 rx_2001;
60 u64 tx_hi;
61 u64 tx_late_col;
62 u64 tx_pause;
63 u64 tx_bcast;
64 u64 tx_mcast;
65 u64 tx_ucast;
66 u64 tx_deferred;
67 u64 tx_total_col;
68 u64 tx_exc_col;
69 u64 tx_single_col;
70 u64 tx_mult_col;
71 u64 rx_total;
72 u64 tx_total;
73 u64 rx_discards;
74 u64 tx_discards;
75};
76
bde55dd9
OR		 77struct ksz88xx_stats_raw {
78 u64 rx;
79 u64 rx_hi;
80 u64 rx_undersize;
81 u64 rx_fragments;
82 u64 rx_oversize;
83 u64 rx_jabbers;
84 u64 rx_symbol_err;
85 u64 rx_crc_err;
86 u64 rx_align_err;
87 u64 rx_mac_ctrl;
88 u64 rx_pause;
89 u64 rx_bcast;
90 u64 rx_mcast;
91 u64 rx_ucast;
92 u64 rx_64_or_less;
93 u64 rx_65_127;
94 u64 rx_128_255;
95 u64 rx_256_511;
96 u64 rx_512_1023;
97 u64 rx_1024_1522;
98 u64 tx;
99 u64 tx_hi;
100 u64 tx_late_col;
101 u64 tx_pause;
102 u64 tx_bcast;
103 u64 tx_mcast;
104 u64 tx_ucast;
105 u64 tx_deferred;
106 u64 tx_total_col;
107 u64 tx_exc_col;
108 u64 tx_single_col;
109 u64 tx_mult_col;
110 u64 rx_discards;
111 u64 tx_discards;
112};
113
a530e6f2
AR		 114static const struct ksz_mib_names ksz88xx_mib_names[] = {
115 { 0x00, "rx" },
116 { 0x01, "rx_hi" },
117 { 0x02, "rx_undersize" },
118 { 0x03, "rx_fragments" },
119 { 0x04, "rx_oversize" },
120 { 0x05, "rx_jabbers" },
121 { 0x06, "rx_symbol_err" },
122 { 0x07, "rx_crc_err" },
123 { 0x08, "rx_align_err" },
124 { 0x09, "rx_mac_ctrl" },
125 { 0x0a, "rx_pause" },
126 { 0x0b, "rx_bcast" },
127 { 0x0c, "rx_mcast" },
128 { 0x0d, "rx_ucast" },
129 { 0x0e, "rx_64_or_less" },
130 { 0x0f, "rx_65_127" },
131 { 0x10, "rx_128_255" },
132 { 0x11, "rx_256_511" },
133 { 0x12, "rx_512_1023" },
134 { 0x13, "rx_1024_1522" },
135 { 0x14, "tx" },
136 { 0x15, "tx_hi" },
137 { 0x16, "tx_late_col" },
138 { 0x17, "tx_pause" },
139 { 0x18, "tx_bcast" },
140 { 0x19, "tx_mcast" },
141 { 0x1a, "tx_ucast" },
142 { 0x1b, "tx_deferred" },
143 { 0x1c, "tx_total_col" },
144 { 0x1d, "tx_exc_col" },
145 { 0x1e, "tx_single_col" },
146 { 0x1f, "tx_mult_col" },
147 { 0x100, "rx_discards" },
148 { 0x101, "tx_discards" },
149};
150
151static const struct ksz_mib_names ksz9477_mib_names[] = {
152 { 0x00, "rx_hi" },
153 { 0x01, "rx_undersize" },
154 { 0x02, "rx_fragments" },
155 { 0x03, "rx_oversize" },
156 { 0x04, "rx_jabbers" },
157 { 0x05, "rx_symbol_err" },
158 { 0x06, "rx_crc_err" },
159 { 0x07, "rx_align_err" },
160 { 0x08, "rx_mac_ctrl" },
161 { 0x09, "rx_pause" },
162 { 0x0A, "rx_bcast" },
163 { 0x0B, "rx_mcast" },
164 { 0x0C, "rx_ucast" },
165 { 0x0D, "rx_64_or_less" },
166 { 0x0E, "rx_65_127" },
167 { 0x0F, "rx_128_255" },
168 { 0x10, "rx_256_511" },
169 { 0x11, "rx_512_1023" },
170 { 0x12, "rx_1024_1522" },
171 { 0x13, "rx_1523_2000" },
172 { 0x14, "rx_2001" },
173 { 0x15, "tx_hi" },
174 { 0x16, "tx_late_col" },
175 { 0x17, "tx_pause" },
176 { 0x18, "tx_bcast" },
177 { 0x19, "tx_mcast" },
178 { 0x1A, "tx_ucast" },
179 { 0x1B, "tx_deferred" },
180 { 0x1C, "tx_total_col" },
181 { 0x1D, "tx_exc_col" },
182 { 0x1E, "tx_single_col" },
183 { 0x1F, "tx_mult_col" },
184 { 0x80, "rx_total" },
185 { 0x81, "tx_total" },
186 { 0x82, "rx_discards" },
187 { 0x83, "tx_discards" },
188};
189
d67d7247
OR		 190struct ksz_driver_strength_prop {
191 const char *name;
192 int offset;
193 int value;
194};
195
196enum ksz_driver_strength_type {
197 KSZ_DRIVER_STRENGTH_HI,
198 KSZ_DRIVER_STRENGTH_LO,
199 KSZ_DRIVER_STRENGTH_IO,
200};
201
202/**
203 * struct ksz_drive_strength - drive strength mapping
204 * @reg_val: register value
205 * @microamp: microamp value
206 */
207struct ksz_drive_strength {
208 u32 reg_val;
209 u32 microamp;
210};
211
212/* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
213 *
214 * This values are not documented in KSZ9477 variants but confirmed by
215 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
216 * and KSZ8563 are using same register (drive strength) settings like KSZ8795.
217 *
218 * Documentation in KSZ8795CLX provides more information with some
219 * recommendations:
220 * - for high speed signals
221 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
222 * 2.5V or 3.3V VDDIO.
223 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
224 * using 1.8V VDDIO.
225 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
226 * or 3.3V VDDIO.
227 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
228 * 5. In same interface, the heavy loading should use higher one of the
229 * drive current strength.
230 * - for low speed signals
231 * 1. 3.3V VDDIO, use either 4 mA or 8 mA.
232 * 2. 2.5V VDDIO, use either 8 mA or 12 mA.
233 * 3. 1.8V VDDIO, use either 12 mA or 16 mA.
234 * 4. If it is heavy loading, can use higher drive current strength.
235 */
236static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
237 { SW_DRIVE_STRENGTH_2MA, 2000 },
238 { SW_DRIVE_STRENGTH_4MA, 4000 },
239 { SW_DRIVE_STRENGTH_8MA, 8000 },
240 { SW_DRIVE_STRENGTH_12MA, 12000 },
241 { SW_DRIVE_STRENGTH_16MA, 16000 },
242 { SW_DRIVE_STRENGTH_20MA, 20000 },
243 { SW_DRIVE_STRENGTH_24MA, 24000 },
244 { SW_DRIVE_STRENGTH_28MA, 28000 },
245};
246
247/* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, ..
248 * variants.
249 * This values are documented in KSZ8873 and KSZ8863 datasheets.
250 */
251static const struct ksz_drive_strength ksz8830_drive_strengths[] = {
252 { 0, 8000 },
253 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
254};
255
6ec23aaa
AR		 256static const struct ksz_dev_ops ksz8_dev_ops = {
257 .setup = ksz8_setup,
258 .get_port_addr = ksz8_get_port_addr,
259 .cfg_port_member = ksz8_cfg_port_member,
260 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
261 .port_setup = ksz8_port_setup,
262 .r_phy = ksz8_r_phy,
263 .w_phy = ksz8_w_phy,
769e2695 264 .r_mib_cnt = ksz8_r_mib_cnt,
6ec23aaa 265 .r_mib_pkt = ksz8_r_mib_pkt,
bde55dd9 266 .r_mib_stat64 = ksz88xx_r_mib_stats64,
6ec23aaa
AR		 267 .freeze_mib = ksz8_freeze_mib,
268 .port_init_cnt = ksz8_port_init_cnt,
269 .fdb_dump = ksz8_fdb_dump,
57795412
OR		 270 .fdb_add = ksz8_fdb_add,
271 .fdb_del = ksz8_fdb_del,
6ec23aaa
AR		 272 .mdb_add = ksz8_mdb_add,
273 .mdb_del = ksz8_mdb_del,
274 .vlan_filtering = ksz8_port_vlan_filtering,
275 .vlan_add = ksz8_port_vlan_add,
276 .vlan_del = ksz8_port_vlan_del,
277 .mirror_add = ksz8_port_mirror_add,
278 .mirror_del = ksz8_port_mirror_del,
279 .get_caps = ksz8_get_caps,
280 .config_cpu_port = ksz8_config_cpu_port,
281 .enable_stp_addr = ksz8_enable_stp_addr,
282 .reset = ksz8_reset_switch,
283 .init = ksz8_switch_init,
284 .exit = ksz8_switch_exit,
29d1e85f 285 .change_mtu = ksz8_change_mtu,
6ec23aaa
AR		 286};
287
3015c503
OR		 288static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
289 unsigned int mode,
290 phy_interface_t interface,
291 struct phy_device *phydev, int speed,
292 int duplex, bool tx_pause,
293 bool rx_pause);
294
6ec23aaa
AR		 295static const struct ksz_dev_ops ksz9477_dev_ops = {
296 .setup = ksz9477_setup,
297 .get_port_addr = ksz9477_get_port_addr,
298 .cfg_port_member = ksz9477_cfg_port_member,
299 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
300 .port_setup = ksz9477_port_setup,
2c119d99 301 .set_ageing_time = ksz9477_set_ageing_time,
6ec23aaa
AR		 302 .r_phy = ksz9477_r_phy,
303 .w_phy = ksz9477_w_phy,
304 .r_mib_cnt = ksz9477_r_mib_cnt,
305 .r_mib_pkt = ksz9477_r_mib_pkt,
306 .r_mib_stat64 = ksz_r_mib_stats64,
307 .freeze_mib = ksz9477_freeze_mib,
308 .port_init_cnt = ksz9477_port_init_cnt,
309 .vlan_filtering = ksz9477_port_vlan_filtering,
310 .vlan_add = ksz9477_port_vlan_add,
311 .vlan_del = ksz9477_port_vlan_del,
312 .mirror_add = ksz9477_port_mirror_add,
313 .mirror_del = ksz9477_port_mirror_del,
314 .get_caps = ksz9477_get_caps,
315 .fdb_dump = ksz9477_fdb_dump,
316 .fdb_add = ksz9477_fdb_add,
317 .fdb_del = ksz9477_fdb_del,
318 .mdb_add = ksz9477_mdb_add,
319 .mdb_del = ksz9477_mdb_del,
320 .change_mtu = ksz9477_change_mtu,
3015c503 321 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
d264f244
OR		 322 .get_wol = ksz9477_get_wol,
323 .set_wol = ksz9477_set_wol,
6ec23aaa 324 .config_cpu_port = ksz9477_config_cpu_port,
71d7920f 325 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
6ec23aaa
AR		 326 .enable_stp_addr = ksz9477_enable_stp_addr,
327 .reset = ksz9477_reset_switch,
328 .init = ksz9477_switch_init,
329 .exit = ksz9477_switch_exit,
330};
331
55ab6ffa
AR		 332static const struct ksz_dev_ops lan937x_dev_ops = {
333 .setup = lan937x_setup,
c9cd961c 334 .teardown = lan937x_teardown,
55ab6ffa
AR		 335 .get_port_addr = ksz9477_get_port_addr,
336 .cfg_port_member = ksz9477_cfg_port_member,
ab882368 337 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
55ab6ffa 338 .port_setup = lan937x_port_setup,
2c119d99 339 .set_ageing_time = lan937x_set_ageing_time,
ffaf1de2
AR		 340 .r_phy = lan937x_r_phy,
341 .w_phy = lan937x_w_phy,
55ab6ffa
AR		 342 .r_mib_cnt = ksz9477_r_mib_cnt,
343 .r_mib_pkt = ksz9477_r_mib_pkt,
344 .r_mib_stat64 = ksz_r_mib_stats64,
345 .freeze_mib = ksz9477_freeze_mib,
346 .port_init_cnt = ksz9477_port_init_cnt,
347 .vlan_filtering = ksz9477_port_vlan_filtering,
348 .vlan_add = ksz9477_port_vlan_add,
349 .vlan_del = ksz9477_port_vlan_del,
350 .mirror_add = ksz9477_port_mirror_add,
351 .mirror_del = ksz9477_port_mirror_del,
c14e878d 352 .get_caps = lan937x_phylink_get_caps,
b19ac41f 353 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
55ab6ffa
AR		 354 .fdb_dump = ksz9477_fdb_dump,
355 .fdb_add = ksz9477_fdb_add,
356 .fdb_del = ksz9477_fdb_del,
357 .mdb_add = ksz9477_mdb_add,
358 .mdb_del = ksz9477_mdb_del,
ab882368 359 .change_mtu = lan937x_change_mtu,
3015c503 360 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
55ab6ffa 361 .config_cpu_port = lan937x_config_cpu_port,
71d7920f 362 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
55ab6ffa
AR		 363 .enable_stp_addr = ksz9477_enable_stp_addr,
364 .reset = lan937x_reset_switch,
365 .init = lan937x_switch_init,
366 .exit = lan937x_switch_exit,
367};
368
a02579df 369static const u16 ksz8795_regs[] = {
e5de2ad1 370 [REG_SW_MAC_ADDR] = 0x68,
486f9ca7
AR		 371 [REG_IND_CTRL_0] = 0x6E,
372 [REG_IND_DATA_8] = 0x70,
373 [REG_IND_DATA_CHECK] = 0x72,
374 [REG_IND_DATA_HI] = 0x71,
375 [REG_IND_DATA_LO] = 0x75,
376 [REG_IND_MIB_CHECK] = 0x74,
377 [REG_IND_BYTE] = 0xA0,
378 [P_FORCE_CTRL] = 0x0C,
379 [P_LINK_STATUS] = 0x0E,
380 [P_LOCAL_CTRL] = 0x07,
381 [P_NEG_RESTART_CTRL] = 0x0D,
382 [P_REMOTE_STATUS] = 0x08,
383 [P_SPEED_STATUS] = 0x09,
384 [S_TAIL_TAG_CTRL] = 0x0C,
6877102f 385 [P_STP_CTRL] = 0x02,
9d95329c
AR		 386 [S_START_CTRL] = 0x01,
387 [S_BROADCAST_CTRL] = 0x06,
388 [S_MULTICAST_CTRL] = 0x04,
aa5b8b73 389 [P_XMII_CTRL_0] = 0x06,
5ae06327 390 [P_XMII_CTRL_1] = 0x06,
486f9ca7
AR		 391};
392
d23a5e18
AR		 393static const u32 ksz8795_masks[] = {
394 [PORT_802_1P_REMAPPING] = BIT(7),
395 [SW_TAIL_TAG_ENABLE] = BIT(1),
396 [MIB_COUNTER_OVERFLOW] = BIT(6),
397 [MIB_COUNTER_VALID] = BIT(5),
398 [VLAN_TABLE_FID] = GENMASK(6, 0),
399 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
400 [VLAN_TABLE_VALID] = BIT(12),
401 [STATIC_MAC_TABLE_VALID] = BIT(21),
402 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
403 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
4bdf79d6
TH		 404 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
405 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
d23a5e18 406 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
4bdf79d6 407 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
d23a5e18
AR		 408 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
409 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
4bdf79d6 410 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
d23a5e18
AR		 411 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
412 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
8560664f
AR		 413 [P_MII_TX_FLOW_CTRL] = BIT(5),
414 [P_MII_RX_FLOW_CTRL] = BIT(5),
d23a5e18
AR		 415};
416
aa5b8b73
AR		 417static const u8 ksz8795_xmii_ctrl0[] = {
418 [P_MII_100MBIT] = 0,
419 [P_MII_10MBIT] = 1,
8560664f
AR		 420 [P_MII_FULL_DUPLEX] = 0,
421 [P_MII_HALF_DUPLEX] = 1,
aa5b8b73
AR		 422};
423
46f80fa8 424static const u8 ksz8795_xmii_ctrl1[] = {
dc1c596e
AR		 425 [P_RGMII_SEL] = 3,
426 [P_GMII_SEL] = 2,
427 [P_RMII_SEL] = 1,
428 [P_MII_SEL] = 0,
46f80fa8
AR		 429 [P_GMII_1GBIT] = 1,
430 [P_GMII_NOT_1GBIT] = 0,
431};
432
34e48383
AR		 433static const u8 ksz8795_shifts[] = {
434 [VLAN_TABLE_MEMBERSHIP_S] = 7,
435 [VLAN_TABLE] = 16,
436 [STATIC_MAC_FWD_PORTS] = 16,
437 [STATIC_MAC_FID] = 24,
438 [DYNAMIC_MAC_ENTRIES_H] = 3,
439 [DYNAMIC_MAC_ENTRIES] = 29,
440 [DYNAMIC_MAC_FID] = 16,
441 [DYNAMIC_MAC_TIMESTAMP] = 27,
442 [DYNAMIC_MAC_SRC_PORT] = 24,
443};
444
a02579df 445static const u16 ksz8863_regs[] = {
02e987f5 446 [REG_SW_MAC_ADDR] = 0x70,
486f9ca7
AR		 447 [REG_IND_CTRL_0] = 0x79,
448 [REG_IND_DATA_8] = 0x7B,
449 [REG_IND_DATA_CHECK] = 0x7B,
450 [REG_IND_DATA_HI] = 0x7C,
451 [REG_IND_DATA_LO] = 0x80,
452 [REG_IND_MIB_CHECK] = 0x80,
453 [P_FORCE_CTRL] = 0x0C,
454 [P_LINK_STATUS] = 0x0E,
455 [P_LOCAL_CTRL] = 0x0C,
456 [P_NEG_RESTART_CTRL] = 0x0D,
457 [P_REMOTE_STATUS] = 0x0E,
458 [P_SPEED_STATUS] = 0x0F,
459 [S_TAIL_TAG_CTRL] = 0x03,
6877102f 460 [P_STP_CTRL] = 0x02,
9d95329c
AR		 461 [S_START_CTRL] = 0x01,
462 [S_BROADCAST_CTRL] = 0x06,
463 [S_MULTICAST_CTRL] = 0x04,
486f9ca7
AR		 464};
465
d23a5e18
AR		 466static const u32 ksz8863_masks[] = {
467 [PORT_802_1P_REMAPPING] = BIT(3),
468 [SW_TAIL_TAG_ENABLE] = BIT(6),
469 [MIB_COUNTER_OVERFLOW] = BIT(7),
470 [MIB_COUNTER_VALID] = BIT(6),
471 [VLAN_TABLE_FID] = GENMASK(15, 12),
472 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
473 [VLAN_TABLE_VALID] = BIT(19),
474 [STATIC_MAC_TABLE_VALID] = BIT(19),
475 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
9aa5757e 476 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
d23a5e18
AR		 477 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
478 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
5d90492d 479 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
492606cd 480 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
d23a5e18 481 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
5d90492d 482 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
d23a5e18
AR		 483 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
484 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
485 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
486};
487
34e48383
AR		 488static u8 ksz8863_shifts[] = {
489 [VLAN_TABLE_MEMBERSHIP_S] = 16,
490 [STATIC_MAC_FWD_PORTS] = 16,
491 [STATIC_MAC_FID] = 22,
5d90492d 492 [DYNAMIC_MAC_ENTRIES_H] = 8,
34e48383
AR		 493 [DYNAMIC_MAC_ENTRIES] = 24,
494 [DYNAMIC_MAC_FID] = 16,
b3177aab 495 [DYNAMIC_MAC_TIMESTAMP] = 22,
34e48383
AR		 496 [DYNAMIC_MAC_SRC_PORT] = 20,
497};
498
6877102f 499static const u16 ksz9477_regs[] = {
e5de2ad1 500 [REG_SW_MAC_ADDR] = 0x0302,
6877102f 501 [P_STP_CTRL] = 0x0B04,
9d95329c
AR		 502 [S_START_CTRL] = 0x0300,
503 [S_BROADCAST_CTRL] = 0x0332,
504 [S_MULTICAST_CTRL] = 0x0331,
aa5b8b73 505 [P_XMII_CTRL_0] = 0x0300,
46f80fa8 506 [P_XMII_CTRL_1] = 0x0301,
457c182a
AR		 507};
508
509static const u32 ksz9477_masks[] = {
510 [ALU_STAT_WRITE] = 0,
511 [ALU_STAT_READ] = 1,
8560664f
AR		 512 [P_MII_TX_FLOW_CTRL] = BIT(5),
513 [P_MII_RX_FLOW_CTRL] = BIT(3),
457c182a
AR		 514};
515
516static const u8 ksz9477_shifts[] = {
517 [ALU_STAT_INDEX] = 16,
518};
519
aa5b8b73
AR		 520static const u8 ksz9477_xmii_ctrl0[] = {
521 [P_MII_100MBIT] = 1,
522 [P_MII_10MBIT] = 0,
8560664f
AR		 523 [P_MII_FULL_DUPLEX] = 1,
524 [P_MII_HALF_DUPLEX] = 0,
aa5b8b73
AR		 525};
526
46f80fa8 527static const u8 ksz9477_xmii_ctrl1[] = {
dc1c596e
AR		 528 [P_RGMII_SEL] = 0,
529 [P_RMII_SEL] = 1,
530 [P_GMII_SEL] = 2,
531 [P_MII_SEL] = 3,
46f80fa8
AR		 532 [P_GMII_1GBIT] = 0,
533 [P_GMII_NOT_1GBIT] = 1,
534};
535
457c182a
AR		 536static const u32 lan937x_masks[] = {
537 [ALU_STAT_WRITE] = 1,
538 [ALU_STAT_READ] = 2,
8560664f
AR		 539 [P_MII_TX_FLOW_CTRL] = BIT(5),
540 [P_MII_RX_FLOW_CTRL] = BIT(3),
457c182a 541};
6877102f 542
457c182a
AR		 543static const u8 lan937x_shifts[] = {
544 [ALU_STAT_INDEX] = 8,
6877102f
AR		 545};
546
41131bac
OR		 547static const struct regmap_range ksz8563_valid_regs[] = {
548 regmap_reg_range(0x0000, 0x0003),
549 regmap_reg_range(0x0006, 0x0006),
550 regmap_reg_range(0x000f, 0x001f),
551 regmap_reg_range(0x0100, 0x0100),
552 regmap_reg_range(0x0104, 0x0107),
553 regmap_reg_range(0x010d, 0x010d),
554 regmap_reg_range(0x0110, 0x0113),
555 regmap_reg_range(0x0120, 0x012b),
556 regmap_reg_range(0x0201, 0x0201),
557 regmap_reg_range(0x0210, 0x0213),
558 regmap_reg_range(0x0300, 0x0300),
559 regmap_reg_range(0x0302, 0x031b),
560 regmap_reg_range(0x0320, 0x032b),
561 regmap_reg_range(0x0330, 0x0336),
562 regmap_reg_range(0x0338, 0x033e),
563 regmap_reg_range(0x0340, 0x035f),
564 regmap_reg_range(0x0370, 0x0370),
565 regmap_reg_range(0x0378, 0x0378),
566 regmap_reg_range(0x037c, 0x037d),
567 regmap_reg_range(0x0390, 0x0393),
568 regmap_reg_range(0x0400, 0x040e),
569 regmap_reg_range(0x0410, 0x042f),
570 regmap_reg_range(0x0500, 0x0519),
571 regmap_reg_range(0x0520, 0x054b),
572 regmap_reg_range(0x0550, 0x05b3),
573
574 /* port 1 */
575 regmap_reg_range(0x1000, 0x1001),
576 regmap_reg_range(0x1004, 0x100b),
577 regmap_reg_range(0x1013, 0x1013),
578 regmap_reg_range(0x1017, 0x1017),
579 regmap_reg_range(0x101b, 0x101b),
580 regmap_reg_range(0x101f, 0x1021),
581 regmap_reg_range(0x1030, 0x1030),
582 regmap_reg_range(0x1100, 0x1111),
583 regmap_reg_range(0x111a, 0x111d),
584 regmap_reg_range(0x1122, 0x1127),
585 regmap_reg_range(0x112a, 0x112b),
586 regmap_reg_range(0x1136, 0x1139),
587 regmap_reg_range(0x113e, 0x113f),
588 regmap_reg_range(0x1400, 0x1401),
589 regmap_reg_range(0x1403, 0x1403),
590 regmap_reg_range(0x1410, 0x1417),
591 regmap_reg_range(0x1420, 0x1423),
592 regmap_reg_range(0x1500, 0x1507),
593 regmap_reg_range(0x1600, 0x1612),
594 regmap_reg_range(0x1800, 0x180f),
595 regmap_reg_range(0x1900, 0x1907),
596 regmap_reg_range(0x1914, 0x191b),
597 regmap_reg_range(0x1a00, 0x1a03),
598 regmap_reg_range(0x1a04, 0x1a08),
599 regmap_reg_range(0x1b00, 0x1b01),
600 regmap_reg_range(0x1b04, 0x1b04),
601 regmap_reg_range(0x1c00, 0x1c05),
602 regmap_reg_range(0x1c08, 0x1c1b),
603
604 /* port 2 */
605 regmap_reg_range(0x2000, 0x2001),
606 regmap_reg_range(0x2004, 0x200b),
607 regmap_reg_range(0x2013, 0x2013),
608 regmap_reg_range(0x2017, 0x2017),
609 regmap_reg_range(0x201b, 0x201b),
610 regmap_reg_range(0x201f, 0x2021),
611 regmap_reg_range(0x2030, 0x2030),
612 regmap_reg_range(0x2100, 0x2111),
613 regmap_reg_range(0x211a, 0x211d),
614 regmap_reg_range(0x2122, 0x2127),
615 regmap_reg_range(0x212a, 0x212b),
616 regmap_reg_range(0x2136, 0x2139),
617 regmap_reg_range(0x213e, 0x213f),
618 regmap_reg_range(0x2400, 0x2401),
619 regmap_reg_range(0x2403, 0x2403),
620 regmap_reg_range(0x2410, 0x2417),
621 regmap_reg_range(0x2420, 0x2423),
622 regmap_reg_range(0x2500, 0x2507),
623 regmap_reg_range(0x2600, 0x2612),
624 regmap_reg_range(0x2800, 0x280f),
625 regmap_reg_range(0x2900, 0x2907),
626 regmap_reg_range(0x2914, 0x291b),
627 regmap_reg_range(0x2a00, 0x2a03),
628 regmap_reg_range(0x2a04, 0x2a08),
629 regmap_reg_range(0x2b00, 0x2b01),
630 regmap_reg_range(0x2b04, 0x2b04),
631 regmap_reg_range(0x2c00, 0x2c05),
632 regmap_reg_range(0x2c08, 0x2c1b),
633
634 /* port 3 */
635 regmap_reg_range(0x3000, 0x3001),
636 regmap_reg_range(0x3004, 0x300b),
637 regmap_reg_range(0x3013, 0x3013),
638 regmap_reg_range(0x3017, 0x3017),
639 regmap_reg_range(0x301b, 0x301b),
640 regmap_reg_range(0x301f, 0x3021),
641 regmap_reg_range(0x3030, 0x3030),
642 regmap_reg_range(0x3300, 0x3301),
643 regmap_reg_range(0x3303, 0x3303),
644 regmap_reg_range(0x3400, 0x3401),
645 regmap_reg_range(0x3403, 0x3403),
646 regmap_reg_range(0x3410, 0x3417),
647 regmap_reg_range(0x3420, 0x3423),
648 regmap_reg_range(0x3500, 0x3507),
649 regmap_reg_range(0x3600, 0x3612),
650 regmap_reg_range(0x3800, 0x380f),
651 regmap_reg_range(0x3900, 0x3907),
652 regmap_reg_range(0x3914, 0x391b),
653 regmap_reg_range(0x3a00, 0x3a03),
654 regmap_reg_range(0x3a04, 0x3a08),
655 regmap_reg_range(0x3b00, 0x3b01),
656 regmap_reg_range(0x3b04, 0x3b04),
657 regmap_reg_range(0x3c00, 0x3c05),
658 regmap_reg_range(0x3c08, 0x3c1b),
659};
660
661static const struct regmap_access_table ksz8563_register_set = {
662 .yes_ranges = ksz8563_valid_regs,
663 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
664};
665
74e792b5
OR		 666static const struct regmap_range ksz9477_valid_regs[] = {
667 regmap_reg_range(0x0000, 0x0003),
668 regmap_reg_range(0x0006, 0x0006),
669 regmap_reg_range(0x0010, 0x001f),
670 regmap_reg_range(0x0100, 0x0100),
671 regmap_reg_range(0x0103, 0x0107),
672 regmap_reg_range(0x010d, 0x010d),
673 regmap_reg_range(0x0110, 0x0113),
674 regmap_reg_range(0x0120, 0x012b),
675 regmap_reg_range(0x0201, 0x0201),
676 regmap_reg_range(0x0210, 0x0213),
677 regmap_reg_range(0x0300, 0x0300),
678 regmap_reg_range(0x0302, 0x031b),
679 regmap_reg_range(0x0320, 0x032b),
680 regmap_reg_range(0x0330, 0x0336),
3a8b8ea6
RN		 681 regmap_reg_range(0x0338, 0x033b),
682 regmap_reg_range(0x033e, 0x033e),
74e792b5
OR		 683 regmap_reg_range(0x0340, 0x035f),
684 regmap_reg_range(0x0370, 0x0370),
685 regmap_reg_range(0x0378, 0x0378),
686 regmap_reg_range(0x037c, 0x037d),
687 regmap_reg_range(0x0390, 0x0393),
688 regmap_reg_range(0x0400, 0x040e),
689 regmap_reg_range(0x0410, 0x042f),
690 regmap_reg_range(0x0444, 0x044b),
691 regmap_reg_range(0x0450, 0x046f),
692 regmap_reg_range(0x0500, 0x0519),
693 regmap_reg_range(0x0520, 0x054b),
694 regmap_reg_range(0x0550, 0x05b3),
695 regmap_reg_range(0x0604, 0x060b),
696 regmap_reg_range(0x0610, 0x0612),
697 regmap_reg_range(0x0614, 0x062c),
698 regmap_reg_range(0x0640, 0x0645),
699 regmap_reg_range(0x0648, 0x064d),
700
701 /* port 1 */
702 regmap_reg_range(0x1000, 0x1001),
703 regmap_reg_range(0x1013, 0x1013),
704 regmap_reg_range(0x1017, 0x1017),
705 regmap_reg_range(0x101b, 0x101b),
706 regmap_reg_range(0x101f, 0x1020),
707 regmap_reg_range(0x1030, 0x1030),
708 regmap_reg_range(0x1100, 0x1115),
709 regmap_reg_range(0x111a, 0x111f),
8d7ae22a
LM		 710 regmap_reg_range(0x1120, 0x112b),
711 regmap_reg_range(0x1134, 0x113b),
712 regmap_reg_range(0x113c, 0x113f),
74e792b5
OR		 713 regmap_reg_range(0x1400, 0x1401),
714 regmap_reg_range(0x1403, 0x1403),
715 regmap_reg_range(0x1410, 0x1417),
716 regmap_reg_range(0x1420, 0x1423),
717 regmap_reg_range(0x1500, 0x1507),
718 regmap_reg_range(0x1600, 0x1613),
719 regmap_reg_range(0x1800, 0x180f),
720 regmap_reg_range(0x1820, 0x1827),
721 regmap_reg_range(0x1830, 0x1837),
722 regmap_reg_range(0x1840, 0x184b),
723 regmap_reg_range(0x1900, 0x1907),
724 regmap_reg_range(0x1914, 0x191b),
725 regmap_reg_range(0x1920, 0x1920),
726 regmap_reg_range(0x1923, 0x1927),
727 regmap_reg_range(0x1a00, 0x1a03),
728 regmap_reg_range(0x1a04, 0x1a07),
729 regmap_reg_range(0x1b00, 0x1b01),
730 regmap_reg_range(0x1b04, 0x1b04),
731 regmap_reg_range(0x1c00, 0x1c05),
732 regmap_reg_range(0x1c08, 0x1c1b),
733
734 /* port 2 */
735 regmap_reg_range(0x2000, 0x2001),
736 regmap_reg_range(0x2013, 0x2013),
737 regmap_reg_range(0x2017, 0x2017),
738 regmap_reg_range(0x201b, 0x201b),
739 regmap_reg_range(0x201f, 0x2020),
740 regmap_reg_range(0x2030, 0x2030),
741 regmap_reg_range(0x2100, 0x2115),
742 regmap_reg_range(0x211a, 0x211f),
8d7ae22a
LM		 743 regmap_reg_range(0x2120, 0x212b),
744 regmap_reg_range(0x2134, 0x213b),
745 regmap_reg_range(0x213c, 0x213f),
74e792b5
OR		 746 regmap_reg_range(0x2400, 0x2401),
747 regmap_reg_range(0x2403, 0x2403),
748 regmap_reg_range(0x2410, 0x2417),
749 regmap_reg_range(0x2420, 0x2423),
750 regmap_reg_range(0x2500, 0x2507),
751 regmap_reg_range(0x2600, 0x2613),
752 regmap_reg_range(0x2800, 0x280f),
753 regmap_reg_range(0x2820, 0x2827),
754 regmap_reg_range(0x2830, 0x2837),
755 regmap_reg_range(0x2840, 0x284b),
756 regmap_reg_range(0x2900, 0x2907),
757 regmap_reg_range(0x2914, 0x291b),
758 regmap_reg_range(0x2920, 0x2920),
759 regmap_reg_range(0x2923, 0x2927),
760 regmap_reg_range(0x2a00, 0x2a03),
761 regmap_reg_range(0x2a04, 0x2a07),
762 regmap_reg_range(0x2b00, 0x2b01),
763 regmap_reg_range(0x2b04, 0x2b04),
764 regmap_reg_range(0x2c00, 0x2c05),
765 regmap_reg_range(0x2c08, 0x2c1b),
766
767 /* port 3 */
768 regmap_reg_range(0x3000, 0x3001),
769 regmap_reg_range(0x3013, 0x3013),
770 regmap_reg_range(0x3017, 0x3017),
771 regmap_reg_range(0x301b, 0x301b),
772 regmap_reg_range(0x301f, 0x3020),
773 regmap_reg_range(0x3030, 0x3030),
774 regmap_reg_range(0x3100, 0x3115),
775 regmap_reg_range(0x311a, 0x311f),
8d7ae22a
LM		 776 regmap_reg_range(0x3120, 0x312b),
777 regmap_reg_range(0x3134, 0x313b),
778 regmap_reg_range(0x313c, 0x313f),
74e792b5
OR		 779 regmap_reg_range(0x3400, 0x3401),
780 regmap_reg_range(0x3403, 0x3403),
781 regmap_reg_range(0x3410, 0x3417),
782 regmap_reg_range(0x3420, 0x3423),
783 regmap_reg_range(0x3500, 0x3507),
784 regmap_reg_range(0x3600, 0x3613),
785 regmap_reg_range(0x3800, 0x380f),
786 regmap_reg_range(0x3820, 0x3827),
787 regmap_reg_range(0x3830, 0x3837),
788 regmap_reg_range(0x3840, 0x384b),
789 regmap_reg_range(0x3900, 0x3907),
790 regmap_reg_range(0x3914, 0x391b),
791 regmap_reg_range(0x3920, 0x3920),
792 regmap_reg_range(0x3923, 0x3927),
793 regmap_reg_range(0x3a00, 0x3a03),
794 regmap_reg_range(0x3a04, 0x3a07),
795 regmap_reg_range(0x3b00, 0x3b01),
796 regmap_reg_range(0x3b04, 0x3b04),
797 regmap_reg_range(0x3c00, 0x3c05),
798 regmap_reg_range(0x3c08, 0x3c1b),
799
800 /* port 4 */
801 regmap_reg_range(0x4000, 0x4001),
802 regmap_reg_range(0x4013, 0x4013),
803 regmap_reg_range(0x4017, 0x4017),
804 regmap_reg_range(0x401b, 0x401b),
805 regmap_reg_range(0x401f, 0x4020),
806 regmap_reg_range(0x4030, 0x4030),
807 regmap_reg_range(0x4100, 0x4115),
808 regmap_reg_range(0x411a, 0x411f),
8d7ae22a
LM		 809 regmap_reg_range(0x4120, 0x412b),
810 regmap_reg_range(0x4134, 0x413b),
811 regmap_reg_range(0x413c, 0x413f),
74e792b5
OR		 812 regmap_reg_range(0x4400, 0x4401),
813 regmap_reg_range(0x4403, 0x4403),
814 regmap_reg_range(0x4410, 0x4417),
815 regmap_reg_range(0x4420, 0x4423),
816 regmap_reg_range(0x4500, 0x4507),
817 regmap_reg_range(0x4600, 0x4613),
818 regmap_reg_range(0x4800, 0x480f),
819 regmap_reg_range(0x4820, 0x4827),
820 regmap_reg_range(0x4830, 0x4837),
821 regmap_reg_range(0x4840, 0x484b),
822 regmap_reg_range(0x4900, 0x4907),
823 regmap_reg_range(0x4914, 0x491b),
824 regmap_reg_range(0x4920, 0x4920),
825 regmap_reg_range(0x4923, 0x4927),
826 regmap_reg_range(0x4a00, 0x4a03),
827 regmap_reg_range(0x4a04, 0x4a07),
828 regmap_reg_range(0x4b00, 0x4b01),
829 regmap_reg_range(0x4b04, 0x4b04),
830 regmap_reg_range(0x4c00, 0x4c05),
831 regmap_reg_range(0x4c08, 0x4c1b),
832
833 /* port 5 */
834 regmap_reg_range(0x5000, 0x5001),
835 regmap_reg_range(0x5013, 0x5013),
836 regmap_reg_range(0x5017, 0x5017),
837 regmap_reg_range(0x501b, 0x501b),
838 regmap_reg_range(0x501f, 0x5020),
839 regmap_reg_range(0x5030, 0x5030),
840 regmap_reg_range(0x5100, 0x5115),
841 regmap_reg_range(0x511a, 0x511f),
8d7ae22a
LM		 842 regmap_reg_range(0x5120, 0x512b),
843 regmap_reg_range(0x5134, 0x513b),
844 regmap_reg_range(0x513c, 0x513f),
74e792b5
OR		 845 regmap_reg_range(0x5400, 0x5401),
846 regmap_reg_range(0x5403, 0x5403),
847 regmap_reg_range(0x5410, 0x5417),
848 regmap_reg_range(0x5420, 0x5423),
849 regmap_reg_range(0x5500, 0x5507),
850 regmap_reg_range(0x5600, 0x5613),
851 regmap_reg_range(0x5800, 0x580f),
852 regmap_reg_range(0x5820, 0x5827),
853 regmap_reg_range(0x5830, 0x5837),
854 regmap_reg_range(0x5840, 0x584b),
855 regmap_reg_range(0x5900, 0x5907),
856 regmap_reg_range(0x5914, 0x591b),
857 regmap_reg_range(0x5920, 0x5920),
858 regmap_reg_range(0x5923, 0x5927),
859 regmap_reg_range(0x5a00, 0x5a03),
860 regmap_reg_range(0x5a04, 0x5a07),
861 regmap_reg_range(0x5b00, 0x5b01),
862 regmap_reg_range(0x5b04, 0x5b04),
863 regmap_reg_range(0x5c00, 0x5c05),
864 regmap_reg_range(0x5c08, 0x5c1b),
865
866 /* port 6 */
867 regmap_reg_range(0x6000, 0x6001),
868 regmap_reg_range(0x6013, 0x6013),
869 regmap_reg_range(0x6017, 0x6017),
870 regmap_reg_range(0x601b, 0x601b),
871 regmap_reg_range(0x601f, 0x6020),
872 regmap_reg_range(0x6030, 0x6030),
873 regmap_reg_range(0x6300, 0x6301),
874 regmap_reg_range(0x6400, 0x6401),
875 regmap_reg_range(0x6403, 0x6403),
876 regmap_reg_range(0x6410, 0x6417),
877 regmap_reg_range(0x6420, 0x6423),
878 regmap_reg_range(0x6500, 0x6507),
879 regmap_reg_range(0x6600, 0x6613),
880 regmap_reg_range(0x6800, 0x680f),
881 regmap_reg_range(0x6820, 0x6827),
882 regmap_reg_range(0x6830, 0x6837),
883 regmap_reg_range(0x6840, 0x684b),
884 regmap_reg_range(0x6900, 0x6907),
885 regmap_reg_range(0x6914, 0x691b),
886 regmap_reg_range(0x6920, 0x6920),
887 regmap_reg_range(0x6923, 0x6927),
888 regmap_reg_range(0x6a00, 0x6a03),
889 regmap_reg_range(0x6a04, 0x6a07),
890 regmap_reg_range(0x6b00, 0x6b01),
891 regmap_reg_range(0x6b04, 0x6b04),
892 regmap_reg_range(0x6c00, 0x6c05),
893 regmap_reg_range(0x6c08, 0x6c1b),
894
895 /* port 7 */
896 regmap_reg_range(0x7000, 0x7001),
897 regmap_reg_range(0x7013, 0x7013),
898 regmap_reg_range(0x7017, 0x7017),
899 regmap_reg_range(0x701b, 0x701b),
900 regmap_reg_range(0x701f, 0x7020),
901 regmap_reg_range(0x7030, 0x7030),
902 regmap_reg_range(0x7200, 0x7203),
903 regmap_reg_range(0x7206, 0x7207),
904 regmap_reg_range(0x7300, 0x7301),
905 regmap_reg_range(0x7400, 0x7401),
906 regmap_reg_range(0x7403, 0x7403),
907 regmap_reg_range(0x7410, 0x7417),
908 regmap_reg_range(0x7420, 0x7423),
909 regmap_reg_range(0x7500, 0x7507),
910 regmap_reg_range(0x7600, 0x7613),
911 regmap_reg_range(0x7800, 0x780f),
912 regmap_reg_range(0x7820, 0x7827),
913 regmap_reg_range(0x7830, 0x7837),
914 regmap_reg_range(0x7840, 0x784b),
915 regmap_reg_range(0x7900, 0x7907),
916 regmap_reg_range(0x7914, 0x791b),
917 regmap_reg_range(0x7920, 0x7920),
918 regmap_reg_range(0x7923, 0x7927),
919 regmap_reg_range(0x7a00, 0x7a03),
920 regmap_reg_range(0x7a04, 0x7a07),
921 regmap_reg_range(0x7b00, 0x7b01),
922 regmap_reg_range(0x7b04, 0x7b04),
923 regmap_reg_range(0x7c00, 0x7c05),
924 regmap_reg_range(0x7c08, 0x7c1b),
925};
926
927static const struct regmap_access_table ksz9477_register_set = {
928 .yes_ranges = ksz9477_valid_regs,
929 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
930};
931
6674e7fd
RN		 932static const struct regmap_range ksz9896_valid_regs[] = {
933 regmap_reg_range(0x0000, 0x0003),
934 regmap_reg_range(0x0006, 0x0006),
935 regmap_reg_range(0x0010, 0x001f),
936 regmap_reg_range(0x0100, 0x0100),
937 regmap_reg_range(0x0103, 0x0107),
938 regmap_reg_range(0x010d, 0x010d),
939 regmap_reg_range(0x0110, 0x0113),
940 regmap_reg_range(0x0120, 0x0127),
941 regmap_reg_range(0x0201, 0x0201),
942 regmap_reg_range(0x0210, 0x0213),
943 regmap_reg_range(0x0300, 0x0300),
944 regmap_reg_range(0x0302, 0x030b),
945 regmap_reg_range(0x0310, 0x031b),
946 regmap_reg_range(0x0320, 0x032b),
947 regmap_reg_range(0x0330, 0x0336),
948 regmap_reg_range(0x0338, 0x033b),
949 regmap_reg_range(0x033e, 0x033e),
950 regmap_reg_range(0x0340, 0x035f),
951 regmap_reg_range(0x0370, 0x0370),
952 regmap_reg_range(0x0378, 0x0378),
953 regmap_reg_range(0x037c, 0x037d),
954 regmap_reg_range(0x0390, 0x0393),
955 regmap_reg_range(0x0400, 0x040e),
956 regmap_reg_range(0x0410, 0x042f),
957
958 /* port 1 */
959 regmap_reg_range(0x1000, 0x1001),
960 regmap_reg_range(0x1013, 0x1013),
961 regmap_reg_range(0x1017, 0x1017),
962 regmap_reg_range(0x101b, 0x101b),
963 regmap_reg_range(0x101f, 0x1020),
964 regmap_reg_range(0x1030, 0x1030),
965 regmap_reg_range(0x1100, 0x1115),
966 regmap_reg_range(0x111a, 0x111f),
967 regmap_reg_range(0x1122, 0x1127),
968 regmap_reg_range(0x112a, 0x112b),
969 regmap_reg_range(0x1136, 0x1139),
970 regmap_reg_range(0x113e, 0x113f),
971 regmap_reg_range(0x1400, 0x1401),
972 regmap_reg_range(0x1403, 0x1403),
973 regmap_reg_range(0x1410, 0x1417),
974 regmap_reg_range(0x1420, 0x1423),
975 regmap_reg_range(0x1500, 0x1507),
976 regmap_reg_range(0x1600, 0x1612),
977 regmap_reg_range(0x1800, 0x180f),
978 regmap_reg_range(0x1820, 0x1827),
979 regmap_reg_range(0x1830, 0x1837),
980 regmap_reg_range(0x1840, 0x184b),
981 regmap_reg_range(0x1900, 0x1907),
982 regmap_reg_range(0x1914, 0x1915),
983 regmap_reg_range(0x1a00, 0x1a03),
984 regmap_reg_range(0x1a04, 0x1a07),
985 regmap_reg_range(0x1b00, 0x1b01),
986 regmap_reg_range(0x1b04, 0x1b04),
987
988 /* port 2 */
989 regmap_reg_range(0x2000, 0x2001),
990 regmap_reg_range(0x2013, 0x2013),
991 regmap_reg_range(0x2017, 0x2017),
992 regmap_reg_range(0x201b, 0x201b),
993 regmap_reg_range(0x201f, 0x2020),
994 regmap_reg_range(0x2030, 0x2030),
995 regmap_reg_range(0x2100, 0x2115),
996 regmap_reg_range(0x211a, 0x211f),
997 regmap_reg_range(0x2122, 0x2127),
998 regmap_reg_range(0x212a, 0x212b),
999 regmap_reg_range(0x2136, 0x2139),
1000 regmap_reg_range(0x213e, 0x213f),
1001 regmap_reg_range(0x2400, 0x2401),
1002 regmap_reg_range(0x2403, 0x2403),
1003 regmap_reg_range(0x2410, 0x2417),
1004 regmap_reg_range(0x2420, 0x2423),
1005 regmap_reg_range(0x2500, 0x2507),
1006 regmap_reg_range(0x2600, 0x2612),
1007 regmap_reg_range(0x2800, 0x280f),
1008 regmap_reg_range(0x2820, 0x2827),
1009 regmap_reg_range(0x2830, 0x2837),
1010 regmap_reg_range(0x2840, 0x284b),
1011 regmap_reg_range(0x2900, 0x2907),
1012 regmap_reg_range(0x2914, 0x2915),
1013 regmap_reg_range(0x2a00, 0x2a03),
1014 regmap_reg_range(0x2a04, 0x2a07),
1015 regmap_reg_range(0x2b00, 0x2b01),
1016 regmap_reg_range(0x2b04, 0x2b04),
1017
1018 /* port 3 */
1019 regmap_reg_range(0x3000, 0x3001),
1020 regmap_reg_range(0x3013, 0x3013),
1021 regmap_reg_range(0x3017, 0x3017),
1022 regmap_reg_range(0x301b, 0x301b),
1023 regmap_reg_range(0x301f, 0x3020),
1024 regmap_reg_range(0x3030, 0x3030),
1025 regmap_reg_range(0x3100, 0x3115),
1026 regmap_reg_range(0x311a, 0x311f),
1027 regmap_reg_range(0x3122, 0x3127),
1028 regmap_reg_range(0x312a, 0x312b),
1029 regmap_reg_range(0x3136, 0x3139),
1030 regmap_reg_range(0x313e, 0x313f),
1031 regmap_reg_range(0x3400, 0x3401),
1032 regmap_reg_range(0x3403, 0x3403),
1033 regmap_reg_range(0x3410, 0x3417),
1034 regmap_reg_range(0x3420, 0x3423),
1035 regmap_reg_range(0x3500, 0x3507),
1036 regmap_reg_range(0x3600, 0x3612),
1037 regmap_reg_range(0x3800, 0x380f),
1038 regmap_reg_range(0x3820, 0x3827),
1039 regmap_reg_range(0x3830, 0x3837),
1040 regmap_reg_range(0x3840, 0x384b),
1041 regmap_reg_range(0x3900, 0x3907),
1042 regmap_reg_range(0x3914, 0x3915),
1043 regmap_reg_range(0x3a00, 0x3a03),
1044 regmap_reg_range(0x3a04, 0x3a07),
1045 regmap_reg_range(0x3b00, 0x3b01),
1046 regmap_reg_range(0x3b04, 0x3b04),
1047
1048 /* port 4 */
1049 regmap_reg_range(0x4000, 0x4001),
1050 regmap_reg_range(0x4013, 0x4013),
1051 regmap_reg_range(0x4017, 0x4017),
1052 regmap_reg_range(0x401b, 0x401b),
1053 regmap_reg_range(0x401f, 0x4020),
1054 regmap_reg_range(0x4030, 0x4030),
1055 regmap_reg_range(0x4100, 0x4115),
1056 regmap_reg_range(0x411a, 0x411f),
1057 regmap_reg_range(0x4122, 0x4127),
1058 regmap_reg_range(0x412a, 0x412b),
1059 regmap_reg_range(0x4136, 0x4139),
1060 regmap_reg_range(0x413e, 0x413f),
1061 regmap_reg_range(0x4400, 0x4401),
1062 regmap_reg_range(0x4403, 0x4403),
1063 regmap_reg_range(0x4410, 0x4417),
1064 regmap_reg_range(0x4420, 0x4423),
1065 regmap_reg_range(0x4500, 0x4507),
1066 regmap_reg_range(0x4600, 0x4612),
1067 regmap_reg_range(0x4800, 0x480f),
1068 regmap_reg_range(0x4820, 0x4827),
1069 regmap_reg_range(0x4830, 0x4837),
1070 regmap_reg_range(0x4840, 0x484b),
1071 regmap_reg_range(0x4900, 0x4907),
1072 regmap_reg_range(0x4914, 0x4915),
1073 regmap_reg_range(0x4a00, 0x4a03),
1074 regmap_reg_range(0x4a04, 0x4a07),
1075 regmap_reg_range(0x4b00, 0x4b01),
1076 regmap_reg_range(0x4b04, 0x4b04),
1077
1078 /* port 5 */
1079 regmap_reg_range(0x5000, 0x5001),
1080 regmap_reg_range(0x5013, 0x5013),
1081 regmap_reg_range(0x5017, 0x5017),
1082 regmap_reg_range(0x501b, 0x501b),
1083 regmap_reg_range(0x501f, 0x5020),
1084 regmap_reg_range(0x5030, 0x5030),
1085 regmap_reg_range(0x5100, 0x5115),
1086 regmap_reg_range(0x511a, 0x511f),
1087 regmap_reg_range(0x5122, 0x5127),
1088 regmap_reg_range(0x512a, 0x512b),
1089 regmap_reg_range(0x5136, 0x5139),
1090 regmap_reg_range(0x513e, 0x513f),
1091 regmap_reg_range(0x5400, 0x5401),
1092 regmap_reg_range(0x5403, 0x5403),
1093 regmap_reg_range(0x5410, 0x5417),
1094 regmap_reg_range(0x5420, 0x5423),
1095 regmap_reg_range(0x5500, 0x5507),
1096 regmap_reg_range(0x5600, 0x5612),
1097 regmap_reg_range(0x5800, 0x580f),
1098 regmap_reg_range(0x5820, 0x5827),
1099 regmap_reg_range(0x5830, 0x5837),
1100 regmap_reg_range(0x5840, 0x584b),
1101 regmap_reg_range(0x5900, 0x5907),
1102 regmap_reg_range(0x5914, 0x5915),
1103 regmap_reg_range(0x5a00, 0x5a03),
1104 regmap_reg_range(0x5a04, 0x5a07),
1105 regmap_reg_range(0x5b00, 0x5b01),
1106 regmap_reg_range(0x5b04, 0x5b04),
1107
1108 /* port 6 */
1109 regmap_reg_range(0x6000, 0x6001),
1110 regmap_reg_range(0x6013, 0x6013),
1111 regmap_reg_range(0x6017, 0x6017),
1112 regmap_reg_range(0x601b, 0x601b),
1113 regmap_reg_range(0x601f, 0x6020),
1114 regmap_reg_range(0x6030, 0x6030),
1115 regmap_reg_range(0x6100, 0x6115),
1116 regmap_reg_range(0x611a, 0x611f),
1117 regmap_reg_range(0x6122, 0x6127),
1118 regmap_reg_range(0x612a, 0x612b),
1119 regmap_reg_range(0x6136, 0x6139),
1120 regmap_reg_range(0x613e, 0x613f),
1121 regmap_reg_range(0x6300, 0x6301),
1122 regmap_reg_range(0x6400, 0x6401),
1123 regmap_reg_range(0x6403, 0x6403),
1124 regmap_reg_range(0x6410, 0x6417),
1125 regmap_reg_range(0x6420, 0x6423),
1126 regmap_reg_range(0x6500, 0x6507),
1127 regmap_reg_range(0x6600, 0x6612),
1128 regmap_reg_range(0x6800, 0x680f),
1129 regmap_reg_range(0x6820, 0x6827),
1130 regmap_reg_range(0x6830, 0x6837),
1131 regmap_reg_range(0x6840, 0x684b),
1132 regmap_reg_range(0x6900, 0x6907),
1133 regmap_reg_range(0x6914, 0x6915),
1134 regmap_reg_range(0x6a00, 0x6a03),
1135 regmap_reg_range(0x6a04, 0x6a07),
1136 regmap_reg_range(0x6b00, 0x6b01),
1137 regmap_reg_range(0x6b04, 0x6b04),
1138};
1139
1140static const struct regmap_access_table ksz9896_register_set = {
1141 .yes_ranges = ksz9896_valid_regs,
1142 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1143};
1144
d0dec333
OR		 1145static const struct regmap_range ksz8873_valid_regs[] = {
1146 regmap_reg_range(0x00, 0x01),
1147 /* global control register */
1148 regmap_reg_range(0x02, 0x0f),
1149
1150 /* port registers */
1151 regmap_reg_range(0x10, 0x1d),
1152 regmap_reg_range(0x1e, 0x1f),
1153 regmap_reg_range(0x20, 0x2d),
1154 regmap_reg_range(0x2e, 0x2f),
1155 regmap_reg_range(0x30, 0x39),
1156 regmap_reg_range(0x3f, 0x3f),
1157
1158 /* advanced control registers */
1159 regmap_reg_range(0x60, 0x6f),
1160 regmap_reg_range(0x70, 0x75),
1161 regmap_reg_range(0x76, 0x78),
1162 regmap_reg_range(0x79, 0x7a),
1163 regmap_reg_range(0x7b, 0x83),
1164 regmap_reg_range(0x8e, 0x99),
1165 regmap_reg_range(0x9a, 0xa5),
1166 regmap_reg_range(0xa6, 0xa6),
1167 regmap_reg_range(0xa7, 0xaa),
1168 regmap_reg_range(0xab, 0xae),
1169 regmap_reg_range(0xaf, 0xba),
1170 regmap_reg_range(0xbb, 0xbc),
1171 regmap_reg_range(0xbd, 0xbd),
1172 regmap_reg_range(0xc0, 0xc0),
1173 regmap_reg_range(0xc2, 0xc2),
1174 regmap_reg_range(0xc3, 0xc3),
1175 regmap_reg_range(0xc4, 0xc4),
1176 regmap_reg_range(0xc6, 0xc6),
1177};
1178
1179static const struct regmap_access_table ksz8873_register_set = {
1180 .yes_ranges = ksz8873_valid_regs,
1181 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1182};
1183
eee16b14 1184const struct ksz_chip_data ksz_switch_chips[] = {
b4490809
OR		 1185 [KSZ8563] = {
1186 .chip_id = KSZ8563_CHIP_ID,
1187 .dev_name = "KSZ8563",
1188 .num_vlans = 4096,
1189 .num_alus = 4096,
1190 .num_statics = 16,
1191 .cpu_ports = 0x07, /* can be configured as cpu port */
1192 .port_cnt = 3, /* total port count */
4630d142 1193 .port_nirqs = 3,
e30f33a5 1194 .num_tx_queues = 4,
71d7920f 1195 .tc_cbs_supported = true,
c570f861 1196 .tc_ets_supported = true,
b4490809
OR		 1197 .ops = &ksz9477_dev_ops,
1198 .mib_names = ksz9477_mib_names,
1199 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1200 .reg_mib_cnt = MIB_COUNTER_NUM,
1201 .regs = ksz9477_regs,
1202 .masks = ksz9477_masks,
1203 .shifts = ksz9477_shifts,
1204 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1205 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1206 .supports_mii = {false, false, true},
1207 .supports_rmii = {false, false, true},
1208 .supports_rgmii = {false, false, true},
1209 .internal_phy = {true, true, false},
505bf320 1210 .gbit_capable = {false, false, true},
41131bac
OR		 1211 .wr_table = &ksz8563_register_set,
1212 .rd_table = &ksz8563_register_set,
b4490809
OR		 1213 },
1214
462d5250
AR		 1215 [KSZ8795] = {
1216 .chip_id = KSZ8795_CHIP_ID,
1217 .dev_name = "KSZ8795",
1218 .num_vlans = 4096,
1219 .num_alus = 0,
1220 .num_statics = 8,
1221 .cpu_ports = 0x10, /* can be configured as cpu port */
1222 .port_cnt = 5, /* total cpu and user ports */
e30f33a5 1223 .num_tx_queues = 4,
6ec23aaa 1224 .ops = &ksz8_dev_ops,
462d5250 1225 .ksz87xx_eee_link_erratum = true,
a530e6f2
AR		 1226 .mib_names = ksz9477_mib_names,
1227 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1228 .reg_mib_cnt = MIB_COUNTER_NUM,
486f9ca7 1229 .regs = ksz8795_regs,
d23a5e18 1230 .masks = ksz8795_masks,
34e48383 1231 .shifts = ksz8795_shifts,
aa5b8b73 1232 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
46f80fa8 1233 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
65ac79e1
AR		 1234 .supports_mii = {false, false, false, false, true},
1235 .supports_rmii = {false, false, false, false, true},
1236 .supports_rgmii = {false, false, false, false, true},
1237 .internal_phy = {true, true, true, true, false},
462d5250
AR		 1238 },
1239
1240 [KSZ8794] = {
1241 /* WARNING
1242 * =======
1243 * KSZ8794 is similar to KSZ8795, except the port map
1244 * contains a gap between external and CPU ports, the
1245 * port map is NOT continuous. The per-port register
1246 * map is shifted accordingly too, i.e. registers at
1247 * offset 0x40 are NOT used on KSZ8794 and they ARE
1248 * used on KSZ8795 for external port 3.
1249 * external cpu
1250 * KSZ8794 0,1,2 4
1251 * KSZ8795 0,1,2,3 4
1252 * KSZ8765 0,1,2,3 4
1253 * port_cnt is configured as 5, even though it is 4
1254 */
1255 .chip_id = KSZ8794_CHIP_ID,
1256 .dev_name = "KSZ8794",
1257 .num_vlans = 4096,
1258 .num_alus = 0,
1259 .num_statics = 8,
1260 .cpu_ports = 0x10, /* can be configured as cpu port */
1261 .port_cnt = 5, /* total cpu and user ports */
e30f33a5 1262 .num_tx_queues = 4,
6ec23aaa 1263 .ops = &ksz8_dev_ops,
462d5250 1264 .ksz87xx_eee_link_erratum = true,
a530e6f2
AR		 1265 .mib_names = ksz9477_mib_names,
1266 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1267 .reg_mib_cnt = MIB_COUNTER_NUM,
486f9ca7 1268 .regs = ksz8795_regs,
d23a5e18 1269 .masks = ksz8795_masks,
34e48383 1270 .shifts = ksz8795_shifts,
aa5b8b73 1271 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
46f80fa8 1272 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
65ac79e1
AR		 1273 .supports_mii = {false, false, false, false, true},
1274 .supports_rmii = {false, false, false, false, true},
1275 .supports_rgmii = {false, false, false, false, true},
1276 .internal_phy = {true, true, true, false, false},
462d5250
AR		 1277 },
1278
1279 [KSZ8765] = {
1280 .chip_id = KSZ8765_CHIP_ID,
1281 .dev_name = "KSZ8765",
1282 .num_vlans = 4096,
1283 .num_alus = 0,
1284 .num_statics = 8,
1285 .cpu_ports = 0x10, /* can be configured as cpu port */
1286 .port_cnt = 5, /* total cpu and user ports */
e30f33a5 1287 .num_tx_queues = 4,
6ec23aaa 1288 .ops = &ksz8_dev_ops,
462d5250 1289 .ksz87xx_eee_link_erratum = true,
a530e6f2
AR		 1290 .mib_names = ksz9477_mib_names,
1291 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1292 .reg_mib_cnt = MIB_COUNTER_NUM,
486f9ca7 1293 .regs = ksz8795_regs,
d23a5e18 1294 .masks = ksz8795_masks,
34e48383 1295 .shifts = ksz8795_shifts,
aa5b8b73 1296 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
46f80fa8 1297 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
65ac79e1
AR		 1298 .supports_mii = {false, false, false, false, true},
1299 .supports_rmii = {false, false, false, false, true},
1300 .supports_rgmii = {false, false, false, false, true},
1301 .internal_phy = {true, true, true, true, false},
462d5250
AR		 1302 },
1303
1304 [KSZ8830] = {
1305 .chip_id = KSZ8830_CHIP_ID,
1306 .dev_name = "KSZ8863/KSZ8873",
1307 .num_vlans = 16,
1308 .num_alus = 0,
1309 .num_statics = 8,
1310 .cpu_ports = 0x4, /* can be configured as cpu port */
1311 .port_cnt = 3,
e30f33a5 1312 .num_tx_queues = 4,
6ec23aaa 1313 .ops = &ksz8_dev_ops,
a530e6f2
AR		 1314 .mib_names = ksz88xx_mib_names,
1315 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1316 .reg_mib_cnt = MIB_COUNTER_NUM,
486f9ca7 1317 .regs = ksz8863_regs,
d23a5e18 1318 .masks = ksz8863_masks,
34e48383 1319 .shifts = ksz8863_shifts,
65ac79e1
AR		 1320 .supports_mii = {false, false, true},
1321 .supports_rmii = {false, false, true},
1322 .internal_phy = {true, true, false},
d0dec333
OR		 1323 .wr_table = &ksz8873_register_set,
1324 .rd_table = &ksz8873_register_set,
462d5250
AR		 1325 },
1326
1327 [KSZ9477] = {
1328 .chip_id = KSZ9477_CHIP_ID,
1329 .dev_name = "KSZ9477",
1330 .num_vlans = 4096,
1331 .num_alus = 4096,
1332 .num_statics = 16,
1333 .cpu_ports = 0x7F, /* can be configured as cpu port */
1334 .port_cnt = 7, /* total physical port count */
978f1f72 1335 .port_nirqs = 4,
e30f33a5 1336 .num_tx_queues = 4,
71d7920f 1337 .tc_cbs_supported = true,
c570f861 1338 .tc_ets_supported = true,
6ec23aaa 1339 .ops = &ksz9477_dev_ops,
a530e6f2
AR		 1340 .mib_names = ksz9477_mib_names,
1341 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1342 .reg_mib_cnt = MIB_COUNTER_NUM,
6877102f 1343 .regs = ksz9477_regs,
457c182a
AR		 1344 .masks = ksz9477_masks,
1345 .shifts = ksz9477_shifts,
aa5b8b73 1346 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
46f80fa8 1347 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
65ac79e1
AR		 1348 .supports_mii = {false, false, false, false,
1349 false, true, false},
1350 .supports_rmii = {false, false, false, false,
1351 false, true, false},
1352 .supports_rgmii = {false, false, false, false,
1353 false, true, false},
1354 .internal_phy = {true, true, true, true,
1355 true, false, false},
505bf320 1356 .gbit_capable = {true, true, true, true, true, true, true},
74e792b5
OR		 1357 .wr_table = &ksz9477_register_set,
1358 .rd_table = &ksz9477_register_set,
462d5250
AR		 1359 },
1360
2eb3ff3c
RN		 1361 [KSZ9896] = {
1362 .chip_id = KSZ9896_CHIP_ID,
1363 .dev_name = "KSZ9896",
1364 .num_vlans = 4096,
1365 .num_alus = 4096,
1366 .num_statics = 16,
1367 .cpu_ports = 0x3F, /* can be configured as cpu port */
1368 .port_cnt = 6, /* total physical port count */
978f1f72 1369 .port_nirqs = 2,
e30f33a5 1370 .num_tx_queues = 4,
2eb3ff3c 1371 .ops = &ksz9477_dev_ops,
2eb3ff3c
RN		 1372 .mib_names = ksz9477_mib_names,
1373 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1374 .reg_mib_cnt = MIB_COUNTER_NUM,
1375 .regs = ksz9477_regs,
1376 .masks = ksz9477_masks,
1377 .shifts = ksz9477_shifts,
1378 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1379 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1380 .supports_mii = {false, false, false, false,
1381 false, true},
1382 .supports_rmii = {false, false, false, false,
1383 false, true},
1384 .supports_rgmii = {false, false, false, false,
1385 false, true},
1386 .internal_phy = {true, true, true, true,
1387 true, false},
1388 .gbit_capable = {true, true, true, true, true, true},
6674e7fd
RN		 1389 .wr_table = &ksz9896_register_set,
1390 .rd_table = &ksz9896_register_set,
2eb3ff3c
RN		 1391 },
1392
462d5250
AR		 1393 [KSZ9897] = {
1394 .chip_id = KSZ9897_CHIP_ID,
1395 .dev_name = "KSZ9897",
1396 .num_vlans = 4096,
1397 .num_alus = 4096,
1398 .num_statics = 16,
1399 .cpu_ports = 0x7F, /* can be configured as cpu port */
1400 .port_cnt = 7, /* total physical port count */
978f1f72 1401 .port_nirqs = 2,
e30f33a5 1402 .num_tx_queues = 4,
6ec23aaa 1403 .ops = &ksz9477_dev_ops,
a530e6f2
AR		 1404 .mib_names = ksz9477_mib_names,
1405 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1406 .reg_mib_cnt = MIB_COUNTER_NUM,
6877102f 1407 .regs = ksz9477_regs,
457c182a
AR		 1408 .masks = ksz9477_masks,
1409 .shifts = ksz9477_shifts,
aa5b8b73 1410 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
46f80fa8 1411 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
65ac79e1
AR		 1412 .supports_mii = {false, false, false, false,
1413 false, true, true},
1414 .supports_rmii = {false, false, false, false,
1415 false, true, true},
1416 .supports_rgmii = {false, false, false, false,
1417 false, true, true},
1418 .internal_phy = {true, true, true, true,
1419 true, false, false},
505bf320 1420 .gbit_capable = {true, true, true, true, true, true, true},
462d5250
AR		 1421 },
1422
1423 [KSZ9893] = {
1424 .chip_id = KSZ9893_CHIP_ID,
1425 .dev_name = "KSZ9893",
1426 .num_vlans = 4096,
1427 .num_alus = 4096,
1428 .num_statics = 16,
1429 .cpu_ports = 0x07, /* can be configured as cpu port */
1430 .port_cnt = 3, /* total port count */
978f1f72 1431 .port_nirqs = 2,
e30f33a5 1432 .num_tx_queues = 4,
6ec23aaa 1433 .ops = &ksz9477_dev_ops,
a530e6f2
AR		 1434 .mib_names = ksz9477_mib_names,
1435 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1436 .reg_mib_cnt = MIB_COUNTER_NUM,
6877102f 1437 .regs = ksz9477_regs,
457c182a
AR		 1438 .masks = ksz9477_masks,
1439 .shifts = ksz9477_shifts,
aa5b8b73 1440 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
46f80fa8 1441 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
65ac79e1
AR		 1442 .supports_mii = {false, false, true},
1443 .supports_rmii = {false, false, true},
1444 .supports_rgmii = {false, false, true},
1445 .internal_phy = {true, true, false},
505bf320 1446 .gbit_capable = {true, true, true},
462d5250
AR		 1447 },
1448
ef912fe4
RS		 1449 [KSZ9563] = {
1450 .chip_id = KSZ9563_CHIP_ID,
1451 .dev_name = "KSZ9563",
1452 .num_vlans = 4096,
1453 .num_alus = 4096,
1454 .num_statics = 16,
1455 .cpu_ports = 0x07, /* can be configured as cpu port */
1456 .port_cnt = 3, /* total port count */
1457 .port_nirqs = 3,
e30f33a5 1458 .num_tx_queues = 4,
71d7920f 1459 .tc_cbs_supported = true,
c570f861 1460 .tc_ets_supported = true,
ef912fe4
RS		 1461 .ops = &ksz9477_dev_ops,
1462 .mib_names = ksz9477_mib_names,
1463 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1464 .reg_mib_cnt = MIB_COUNTER_NUM,
1465 .regs = ksz9477_regs,
1466 .masks = ksz9477_masks,
1467 .shifts = ksz9477_shifts,
1468 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1469 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1470 .supports_mii = {false, false, true},
1471 .supports_rmii = {false, false, true},
1472 .supports_rgmii = {false, false, true},
1473 .internal_phy = {true, true, false},
1474 .gbit_capable = {true, true, true},
1475 },
1476
462d5250
AR		 1477 [KSZ9567] = {
1478 .chip_id = KSZ9567_CHIP_ID,
1479 .dev_name = "KSZ9567",
1480 .num_vlans = 4096,
1481 .num_alus = 4096,
1482 .num_statics = 16,
1483 .cpu_ports = 0x7F, /* can be configured as cpu port */
1484 .port_cnt = 7, /* total physical port count */
978f1f72 1485 .port_nirqs = 3,
e30f33a5 1486 .num_tx_queues = 4,
71d7920f 1487 .tc_cbs_supported = true,
c570f861 1488 .tc_ets_supported = true,
6ec23aaa 1489 .ops = &ksz9477_dev_ops,
a530e6f2
AR		 1490 .mib_names = ksz9477_mib_names,
1491 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1492 .reg_mib_cnt = MIB_COUNTER_NUM,
6877102f 1493 .regs = ksz9477_regs,
457c182a
AR		 1494 .masks = ksz9477_masks,
1495 .shifts = ksz9477_shifts,
aa5b8b73 1496 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
46f80fa8 1497 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
65ac79e1
AR		 1498 .supports_mii = {false, false, false, false,
1499 false, true, true},
1500 .supports_rmii = {false, false, false, false,
1501 false, true, true},
1502 .supports_rgmii = {false, false, false, false,
1503 false, true, true},
1504 .internal_phy = {true, true, true, true,
1505 true, false, false},
505bf320 1506 .gbit_capable = {true, true, true, true, true, true, true},
462d5250
AR		 1507 },
1508
1509 [LAN9370] = {
1510 .chip_id = LAN9370_CHIP_ID,
1511 .dev_name = "LAN9370",
1512 .num_vlans = 4096,
1513 .num_alus = 1024,
1514 .num_statics = 256,
1515 .cpu_ports = 0x10, /* can be configured as cpu port */
1516 .port_cnt = 5, /* total physical port count */
978f1f72 1517 .port_nirqs = 6,
e30f33a5 1518 .num_tx_queues = 8,
71d7920f 1519 .tc_cbs_supported = true,
c570f861 1520 .tc_ets_supported = true,
55ab6ffa 1521 .ops = &lan937x_dev_ops,
a530e6f2
AR		 1522 .mib_names = ksz9477_mib_names,
1523 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1524 .reg_mib_cnt = MIB_COUNTER_NUM,
6877102f 1525 .regs = ksz9477_regs,
457c182a
AR		 1526 .masks = lan937x_masks,
1527 .shifts = lan937x_shifts,
aa5b8b73 1528 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
46f80fa8 1529 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
65ac79e1
AR		 1530 .supports_mii = {false, false, false, false, true},
1531 .supports_rmii = {false, false, false, false, true},
1532 .supports_rgmii = {false, false, false, false, true},
1533 .internal_phy = {true, true, true, true, false},
462d5250
AR		 1534 },
1535
1536 [LAN9371] = {
1537 .chip_id = LAN9371_CHIP_ID,
1538 .dev_name = "LAN9371",
1539 .num_vlans = 4096,
1540 .num_alus = 1024,
1541 .num_statics = 256,
1542 .cpu_ports = 0x30, /* can be configured as cpu port */
1543 .port_cnt = 6, /* total physical port count */
978f1f72 1544 .port_nirqs = 6,
e30f33a5 1545 .num_tx_queues = 8,
71d7920f 1546 .tc_cbs_supported = true,
c570f861 1547 .tc_ets_supported = true,
55ab6ffa 1548 .ops = &lan937x_dev_ops,
a530e6f2
AR		 1549 .mib_names = ksz9477_mib_names,
1550 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1551 .reg_mib_cnt = MIB_COUNTER_NUM,
6877102f 1552 .regs = ksz9477_regs,
457c182a
AR		 1553 .masks = lan937x_masks,
1554 .shifts = lan937x_shifts,
aa5b8b73 1555 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
46f80fa8 1556 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
65ac79e1
AR		 1557 .supports_mii = {false, false, false, false, true, true},
1558 .supports_rmii = {false, false, false, false, true, true},
1559 .supports_rgmii = {false, false, false, false, true, true},
1560 .internal_phy = {true, true, true, true, false, false},
462d5250
AR		 1561 },
1562
1563 [LAN9372] = {
1564 .chip_id = LAN9372_CHIP_ID,
1565 .dev_name = "LAN9372",
1566 .num_vlans = 4096,
1567 .num_alus = 1024,
1568 .num_statics = 256,
1569 .cpu_ports = 0x30, /* can be configured as cpu port */
1570 .port_cnt = 8, /* total physical port count */
978f1f72 1571 .port_nirqs = 6,
e30f33a5 1572 .num_tx_queues = 8,
71d7920f 1573 .tc_cbs_supported = true,
c570f861 1574 .tc_ets_supported = true,
55ab6ffa 1575 .ops = &lan937x_dev_ops,
a530e6f2
AR		 1576 .mib_names = ksz9477_mib_names,
1577 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1578 .reg_mib_cnt = MIB_COUNTER_NUM,
6877102f 1579 .regs = ksz9477_regs,
457c182a
AR		 1580 .masks = lan937x_masks,
1581 .shifts = lan937x_shifts,
aa5b8b73 1582 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
46f80fa8 1583 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
65ac79e1
AR		 1584 .supports_mii = {false, false, false, false,
1585 true, true, false, false},
1586 .supports_rmii = {false, false, false, false,
1587 true, true, false, false},
1588 .supports_rgmii = {false, false, false, false,
1589 true, true, false, false},
1590 .internal_phy = {true, true, true, true,
1591 false, false, true, true},
462d5250
AR		 1592 },
1593
1594 [LAN9373] = {
1595 .chip_id = LAN9373_CHIP_ID,
1596 .dev_name = "LAN9373",
1597 .num_vlans = 4096,
1598 .num_alus = 1024,
1599 .num_statics = 256,
1600 .cpu_ports = 0x38, /* can be configured as cpu port */
1601 .port_cnt = 5, /* total physical port count */
978f1f72 1602 .port_nirqs = 6,
e30f33a5 1603 .num_tx_queues = 8,
71d7920f 1604 .tc_cbs_supported = true,
c570f861 1605 .tc_ets_supported = true,
55ab6ffa 1606 .ops = &lan937x_dev_ops,
a530e6f2
AR		 1607 .mib_names = ksz9477_mib_names,
1608 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1609 .reg_mib_cnt = MIB_COUNTER_NUM,
6877102f 1610 .regs = ksz9477_regs,
457c182a
AR		 1611 .masks = lan937x_masks,
1612 .shifts = lan937x_shifts,
aa5b8b73 1613 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
46f80fa8 1614 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
65ac79e1
AR		 1615 .supports_mii = {false, false, false, false,
1616 true, true, false, false},
1617 .supports_rmii = {false, false, false, false,
1618 true, true, false, false},
1619 .supports_rgmii = {false, false, false, false,
1620 true, true, false, false},
1621 .internal_phy = {true, true, true, false,
1622 false, false, true, true},
462d5250
AR		 1623 },
1624
1625 [LAN9374] = {
1626 .chip_id = LAN9374_CHIP_ID,
1627 .dev_name = "LAN9374",
1628 .num_vlans = 4096,
1629 .num_alus = 1024,
1630 .num_statics = 256,
1631 .cpu_ports = 0x30, /* can be configured as cpu port */
1632 .port_cnt = 8, /* total physical port count */
978f1f72 1633 .port_nirqs = 6,
e30f33a5 1634 .num_tx_queues = 8,
71d7920f 1635 .tc_cbs_supported = true,
c570f861 1636 .tc_ets_supported = true,
55ab6ffa 1637 .ops = &lan937x_dev_ops,
a530e6f2
AR		 1638 .mib_names = ksz9477_mib_names,
1639 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1640 .reg_mib_cnt = MIB_COUNTER_NUM,
6877102f 1641 .regs = ksz9477_regs,
457c182a
AR		 1642 .masks = lan937x_masks,
1643 .shifts = lan937x_shifts,
aa5b8b73 1644 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
46f80fa8 1645 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
65ac79e1
AR		 1646 .supports_mii = {false, false, false, false,
1647 true, true, false, false},
1648 .supports_rmii = {false, false, false, false,
1649 true, true, false, false},
1650 .supports_rgmii = {false, false, false, false,
1651 true, true, false, false},
1652 .internal_phy = {true, true, true, true,
1653 false, false, true, true},
462d5250
AR		 1654 },
1655};
eee16b14 1656EXPORT_SYMBOL_GPL(ksz_switch_chips);
462d5250
AR		 1657
1658static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1659{
1660 int i;
1661
1662 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1663 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1664
1665 if (chip->chip_id == prod_num)
1666 return chip;
1667 }
1668
1669 return NULL;
1670}
1671
eee16b14
AR		 1672static int ksz_check_device_id(struct ksz_device *dev)
1673{
1674 const struct ksz_chip_data *dt_chip_data;
1675
1676 dt_chip_data = of_device_get_match_data(dev->dev);
1677
1678 /* Check for Device Tree and Chip ID */
1679 if (dt_chip_data->chip_id != dev->chip_id) {
1680 dev_err(dev->dev,
1681 "Device tree specifies chip %s but found %s, please fix it!\n",
1682 dt_chip_data->dev_name, dev->info->dev_name);
1683 return -ENODEV;
1684 }
1685
1686 return 0;
1687}
1688
1958eee8
AR		 1689static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1690 struct phylink_config *config)
65ac79e1
AR		 1691{
1692 struct ksz_device *dev = ds->priv;
1693
65ac79e1
AR		 1694 if (dev->info->supports_mii[port])
1695 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1696
1697 if (dev->info->supports_rmii[port])
1698 __set_bit(PHY_INTERFACE_MODE_RMII,
1699 config->supported_interfaces);
1700
1701 if (dev->info->supports_rgmii[port])
1702 phy_interface_set_rgmii(config->supported_interfaces);
1703
5fbb08eb 1704 if (dev->info->internal_phy[port]) {
65ac79e1
AR		 1705 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1706 config->supported_interfaces);
5fbb08eb
VO		 1707 /* Compatibility for phylib's default interface type when the
1708 * phy-mode property is absent
1709 */
1710 __set_bit(PHY_INTERFACE_MODE_GMII,
1711 config->supported_interfaces);
1712 }
7012033c
AR		 1713
1714 if (dev->dev_ops->get_caps)
1715 dev->dev_ops->get_caps(dev, port, config);
65ac79e1 1716}
65ac79e1 1717
c6101dd7
AR		 1718void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1719{
c4748ff6 1720 struct ethtool_pause_stats *pstats;
c6101dd7
AR		 1721 struct rtnl_link_stats64 *stats;
1722 struct ksz_stats_raw *raw;
1723 struct ksz_port_mib *mib;
1724
1725 mib = &dev->ports[port].mib;
1726 stats = &mib->stats64;
c4748ff6 1727 pstats = &mib->pause_stats;
c6101dd7
AR		 1728 raw = (struct ksz_stats_raw *)mib->counters;
1729
1730 spin_lock(&mib->stats64_lock);
1731
961d6c70
OR		 1732 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1733 raw->rx_pause;
1734 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1735 raw->tx_pause;
c6101dd7
AR		 1736
1737 /* HW counters are counting bytes + FCS which is not acceptable
1738 * for rtnl_link_stats64 interface
1739 */
1740 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1741 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1742
1743 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1744 raw->rx_oversize;
1745
1746 stats->rx_crc_errors = raw->rx_crc_err;
1747 stats->rx_frame_errors = raw->rx_align_err;
1748 stats->rx_dropped = raw->rx_discards;
1749 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1750 stats->rx_frame_errors + stats->rx_dropped;
1751
1752 stats->tx_window_errors = raw->tx_late_col;
1753 stats->tx_fifo_errors = raw->tx_discards;
1754 stats->tx_aborted_errors = raw->tx_exc_col;
1755 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1756 stats->tx_aborted_errors;
1757
1758 stats->multicast = raw->rx_mcast;
1759 stats->collisions = raw->tx_total_col;
1760
c4748ff6
OR		 1761 pstats->tx_pause_frames = raw->tx_pause;
1762 pstats->rx_pause_frames = raw->rx_pause;
1763
c6101dd7
AR		 1764 spin_unlock(&mib->stats64_lock);
1765}
c6101dd7 1766
bde55dd9
OR		 1767void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
1768{
1769 struct ethtool_pause_stats *pstats;
1770 struct rtnl_link_stats64 *stats;
1771 struct ksz88xx_stats_raw *raw;
1772 struct ksz_port_mib *mib;
1773
1774 mib = &dev->ports[port].mib;
1775 stats = &mib->stats64;
1776 pstats = &mib->pause_stats;
1777 raw = (struct ksz88xx_stats_raw *)mib->counters;
1778
1779 spin_lock(&mib->stats64_lock);
1780
1781 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1782 raw->rx_pause;
1783 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1784 raw->tx_pause;
1785
1786 /* HW counters are counting bytes + FCS which is not acceptable
1787 * for rtnl_link_stats64 interface
1788 */
1789 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
1790 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
1791
1792 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1793 raw->rx_oversize;
1794
1795 stats->rx_crc_errors = raw->rx_crc_err;
1796 stats->rx_frame_errors = raw->rx_align_err;
1797 stats->rx_dropped = raw->rx_discards;
1798 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1799 stats->rx_frame_errors + stats->rx_dropped;
1800
1801 stats->tx_window_errors = raw->tx_late_col;
1802 stats->tx_fifo_errors = raw->tx_discards;
1803 stats->tx_aborted_errors = raw->tx_exc_col;
1804 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1805 stats->tx_aborted_errors;
1806
1807 stats->multicast = raw->rx_mcast;
1808 stats->collisions = raw->tx_total_col;
1809
1810 pstats->tx_pause_frames = raw->tx_pause;
1811 pstats->rx_pause_frames = raw->rx_pause;
1812
1813 spin_unlock(&mib->stats64_lock);
1814}
1815
1958eee8
AR		 1816static void ksz_get_stats64(struct dsa_switch *ds, int port,
1817 struct rtnl_link_stats64 *s)
c6101dd7
AR		 1818{
1819 struct ksz_device *dev = ds->priv;
1820 struct ksz_port_mib *mib;
1821
1822 mib = &dev->ports[port].mib;
1823
1824 spin_lock(&mib->stats64_lock);
1825 memcpy(s, &mib->stats64, sizeof(*s));
1826 spin_unlock(&mib->stats64_lock);
1827}
c6101dd7 1828
c4748ff6
OR		 1829static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1830 struct ethtool_pause_stats *pause_stats)
1831{
1832 struct ksz_device *dev = ds->priv;
1833 struct ksz_port_mib *mib;
1834
1835 mib = &dev->ports[port].mib;
1836
1837 spin_lock(&mib->stats64_lock);
1838 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1839 spin_unlock(&mib->stats64_lock);
1840}
1841
1958eee8
AR		 1842static void ksz_get_strings(struct dsa_switch *ds, int port,
1843 u32 stringset, uint8_t *buf)
997d2126
AR		 1844{
1845 struct ksz_device *dev = ds->priv;
1846 int i;
1847
1848 if (stringset != ETH_SS_STATS)
1849 return;
1850
1851 for (i = 0; i < dev->info->mib_cnt; i++) {
1852 memcpy(buf + i * ETH_GSTRING_LEN,
1853 dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1854 }
1855}
997d2126 1856
e593df51 1857static void ksz_update_port_member(struct ksz_device *dev, int port)
b987e98e 1858{
b3612ccd
OR		 1859 struct ksz_port *p = &dev->ports[port];
1860 struct dsa_switch *ds = dev->ds;
1861 u8 port_member = 0, cpu_port;
1862 const struct dsa_port *dp;
3d00827a 1863 int i, j;
b987e98e 1864
b3612ccd
OR		 1865 if (!dsa_is_user_port(ds, port))
1866 return;
1867
1868 dp = dsa_to_port(ds, port);
1869 cpu_port = BIT(dsa_upstream_port(ds, port));
1870
1871 for (i = 0; i < ds->num_ports; i++) {
1872 const struct dsa_port *other_dp = dsa_to_port(ds, i);
1873 struct ksz_port *other_p = &dev->ports[i];
1874 u8 val = 0;
1875
1876 if (!dsa_is_user_port(ds, i))
c2e86691 1877 continue;
b3612ccd
OR		 1878 if (port == i)
1879 continue;
41fb0cf1 1880 if (!dsa_port_bridge_same(dp, other_dp))
c2e86691 1881 continue;
3d00827a
SS		 1882 if (other_p->stp_state != BR_STATE_FORWARDING)
1883 continue;
c2e86691 1884
3d00827a 1885 if (p->stp_state == BR_STATE_FORWARDING) {
b3612ccd
OR		 1886 val |= BIT(port);
1887 port_member |= BIT(i);
1888 }
1889
3d00827a
SS		 1890 /* Retain port [i]'s relationship to other ports than [port] */
1891 for (j = 0; j < ds->num_ports; j++) {
1892 const struct dsa_port *third_dp;
1893 struct ksz_port *third_p;
1894
1895 if (j == i)
1896 continue;
1897 if (j == port)
1898 continue;
1899 if (!dsa_is_user_port(ds, j))
1900 continue;
1901 third_p = &dev->ports[j];
1902 if (third_p->stp_state != BR_STATE_FORWARDING)
1903 continue;
1904 third_dp = dsa_to_port(ds, j);
1905 if (dsa_port_bridge_same(other_dp, third_dp))
1906 val |= BIT(j);
1907 }
1908
b3612ccd 1909 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
b987e98e 1910 }
b3612ccd
OR		 1911
1912 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
b987e98e
WH		 1913}
1914
ff319a64
AR		 1915static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
1916{
1917 struct ksz_device *dev = bus->priv;
1918 u16 val;
1919 int ret;
1920
ff319a64
AR		 1921 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
1922 if (ret < 0)
1923 return ret;
1924
1925 return val;
1926}
1927
1928static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
1929 u16 val)
1930{
1931 struct ksz_device *dev = bus->priv;
1932
ff319a64
AR		 1933 return dev->dev_ops->w_phy(dev, addr, regnum, val);
1934}
1935
1936static int ksz_irq_phy_setup(struct ksz_device *dev)
1937{
1938 struct dsa_switch *ds = dev->ds;
1939 int phy;
1940 int irq;
1941 int ret;
1942
1943 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
1944 if (BIT(phy) & ds->phys_mii_mask) {
1945 irq = irq_find_mapping(dev->ports[phy].pirq.domain,
1946 PORT_SRC_PHY_INT);
1947 if (irq < 0) {
1948 ret = irq;
1949 goto out;
1950 }
6ca80638 1951 ds->user_mii_bus->irq[phy] = irq;
ff319a64
AR		 1952 }
1953 }
1954 return 0;
1955out:
1956 while (phy--)
1957 if (BIT(phy) & ds->phys_mii_mask)
6ca80638 1958 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
ff319a64
AR		 1959
1960 return ret;
1961}
1962
1963static void ksz_irq_phy_free(struct ksz_device *dev)
1964{
1965 struct dsa_switch *ds = dev->ds;
1966 int phy;
1967
1968 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
1969 if (BIT(phy) & ds->phys_mii_mask)
6ca80638 1970 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
ff319a64
AR		 1971}
1972
1973static int ksz_mdio_register(struct ksz_device *dev)
1974{
1975 struct dsa_switch *ds = dev->ds;
1976 struct device_node *mdio_np;
1977 struct mii_bus *bus;
1978 int ret;
1979
1980 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
1981 if (!mdio_np)
1982 return 0;
1983
1984 bus = devm_mdiobus_alloc(ds->dev);
1985 if (!bus) {
1986 of_node_put(mdio_np);
1987 return -ENOMEM;
1988 }
1989
1990 bus->priv = dev;
1991 bus->read = ksz_sw_mdio_read;
1992 bus->write = ksz_sw_mdio_write;
6ca80638 1993 bus->name = "ksz user smi";
ff319a64
AR		 1994 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
1995 bus->parent = ds->dev;
1996 bus->phy_mask = ~ds->phys_mii_mask;
1997
6ca80638 1998 ds->user_mii_bus = bus;
ff319a64
AR		 1999
2000 if (dev->irq > 0) {
2001 ret = ksz_irq_phy_setup(dev);
2002 if (ret) {
2003 of_node_put(mdio_np);
2004 return ret;
2005 }
2006 }
2007
2008 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
2009 if (ret) {
2010 dev_err(ds->dev, "unable to register MDIO bus %s\n",
2011 bus->id);
2012 if (dev->irq > 0)
2013 ksz_irq_phy_free(dev);
2014 }
2015
2016 of_node_put(mdio_np);
2017
2018 return ret;
2019}
2020
e1add7dd 2021static void ksz_irq_mask(struct irq_data *d)
ff319a64 2022{
e1add7dd 2023 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
ff319a64 2024
e1add7dd 2025 kirq->masked |= BIT(d->hwirq);
ff319a64
AR		 2026}
2027
e1add7dd 2028static void ksz_irq_unmask(struct irq_data *d)
ff319a64 2029{
e1add7dd 2030 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
ff319a64 2031
e1add7dd 2032 kirq->masked &= ~BIT(d->hwirq);
ff319a64
AR		 2033}
2034
e1add7dd 2035static void ksz_irq_bus_lock(struct irq_data *d)
ff319a64 2036{
e1add7dd 2037 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
ff319a64 2038
e1add7dd 2039 mutex_lock(&kirq->dev->lock_irq);
ff319a64
AR		 2040}
2041
e1add7dd 2042static void ksz_irq_bus_sync_unlock(struct irq_data *d)
ff319a64 2043{
e1add7dd
AR		 2044 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2045 struct ksz_device *dev = kirq->dev;
ff319a64
AR		 2046 int ret;
2047
e1add7dd 2048 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
ff319a64
AR		 2049 if (ret)
2050 dev_err(dev->dev, "failed to change IRQ mask\n");
2051
2052 mutex_unlock(&dev->lock_irq);
2053}
2054
e1add7dd
AR		 2055static const struct irq_chip ksz_irq_chip = {
2056 .name = "ksz-irq",
2057 .irq_mask = ksz_irq_mask,
2058 .irq_unmask = ksz_irq_unmask,
2059 .irq_bus_lock = ksz_irq_bus_lock,
2060 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
ff319a64
AR		 2061};
2062
e1add7dd
AR		 2063static int ksz_irq_domain_map(struct irq_domain *d,
2064 unsigned int irq, irq_hw_number_t hwirq)
ff319a64 2065{
ff319a64 2066 irq_set_chip_data(irq, d->host_data);
e1add7dd 2067 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
ff319a64
AR		 2068 irq_set_noprobe(irq);
2069
2070 return 0;
2071}
2072
e1add7dd
AR		 2073static const struct irq_domain_ops ksz_irq_domain_ops = {
2074 .map = ksz_irq_domain_map,
ff319a64
AR		 2075 .xlate = irq_domain_xlate_twocell,
2076};
2077
e1add7dd 2078static void ksz_irq_free(struct ksz_irq *kirq)
ff319a64
AR		 2079{
2080 int irq, virq;
2081
e1add7dd 2082 free_irq(kirq->irq_num, kirq);
ff319a64 2083
e1add7dd
AR		 2084 for (irq = 0; irq < kirq->nirqs; irq++) {
2085 virq = irq_find_mapping(kirq->domain, irq);
ff319a64
AR		 2086 irq_dispose_mapping(virq);
2087 }
2088
e1add7dd 2089 irq_domain_remove(kirq->domain);
ff319a64
AR		 2090}
2091
e1add7dd 2092static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
ff319a64 2093{
e1add7dd 2094 struct ksz_irq *kirq = dev_id;
ff319a64 2095 unsigned int nhandled = 0;
e1add7dd 2096 struct ksz_device *dev;
ff319a64 2097 unsigned int sub_irq;
e1add7dd 2098 u8 data;
ff319a64 2099 int ret;
e1add7dd 2100 u8 n;
ff319a64 2101
e1add7dd
AR		 2102 dev = kirq->dev;
2103
2104 /* Read interrupt status register */
2105 ret = ksz_read8(dev, kirq->reg_status, &data);
ff319a64
AR		 2106 if (ret)
2107 goto out;
2108
e1add7dd
AR		 2109 for (n = 0; n < kirq->nirqs; ++n) {
2110 if (data & BIT(n)) {
2111 sub_irq = irq_find_mapping(kirq->domain, n);
ff319a64
AR		 2112 handle_nested_irq(sub_irq);
2113 ++nhandled;
2114 }
2115 }
2116out:
2117 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2118}
2119
e1add7dd 2120static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
ff319a64 2121{
e1add7dd 2122 int ret, n;
ff319a64 2123
e1add7dd
AR		 2124 kirq->dev = dev;
2125 kirq->masked = ~0;
ff319a64 2126
e1add7dd
AR		 2127 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
2128 &ksz_irq_domain_ops, kirq);
2129 if (!kirq->domain)
2130 return -ENOMEM;
ff319a64 2131
e1add7dd
AR		 2132 for (n = 0; n < kirq->nirqs; n++)
2133 irq_create_mapping(kirq->domain, n);
ff319a64 2134
e1add7dd 2135 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
62e027fb 2136 IRQF_ONESHOT, kirq->name, kirq);
ff319a64
AR		 2137 if (ret)
2138 goto out;
2139
2140 return 0;
2141
2142out:
e1add7dd 2143 ksz_irq_free(kirq);
ff319a64
AR		 2144
2145 return ret;
2146}
2147
e1add7dd 2148static int ksz_girq_setup(struct ksz_device *dev)
ff319a64 2149{
e1add7dd 2150 struct ksz_irq *girq = &dev->girq;
ff319a64 2151
e1add7dd
AR		 2152 girq->nirqs = dev->info->port_cnt;
2153 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2154 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2155 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
ff319a64 2156
e1add7dd 2157 girq->irq_num = dev->irq;
ff319a64 2158
e1add7dd 2159 return ksz_irq_common_setup(dev, girq);
ff319a64
AR		 2160}
2161
2162static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2163{
e1add7dd 2164 struct ksz_irq *pirq = &dev->ports[p].pirq;
ff319a64 2165
e1add7dd
AR		 2166 pirq->nirqs = dev->info->port_nirqs;
2167 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2168 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2169 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
ff319a64 2170
e1add7dd
AR		 2171 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2172 if (pirq->irq_num < 0)
2173 return pirq->irq_num;
ff319a64 2174
e1add7dd 2175 return ksz_irq_common_setup(dev, pirq);
ff319a64
AR		 2176}
2177
1958eee8 2178static int ksz_setup(struct dsa_switch *ds)
d2822e68
AR		 2179{
2180 struct ksz_device *dev = ds->priv;
ff319a64 2181 struct dsa_port *dp;
15f7cfae 2182 struct ksz_port *p;
9d95329c 2183 const u16 *regs;
d2822e68
AR		 2184 int ret;
2185
9d95329c
AR		 2186 regs = dev->info->regs;
2187
d2822e68
AR		 2188 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2189 dev->info->num_vlans, GFP_KERNEL);
2190 if (!dev->vlan_cache)
2191 return -ENOMEM;
2192
2193 ret = dev->dev_ops->reset(dev);
2194 if (ret) {
2195 dev_err(ds->dev, "failed to reset switch\n");
2196 return ret;
2197 }
2198
1ca6437f 2199 /* set broadcast storm protection 10% rate */
b8311f46 2200 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
1ca6437f
AR		 2201 BROADCAST_STORM_RATE,
2202 (BROADCAST_STORM_VALUE *
2203 BROADCAST_STORM_PROT_RATE) / 100);
2204
d2822e68
AR		 2205 dev->dev_ops->config_cpu_port(ds);
2206
2207 dev->dev_ops->enable_stp_addr(dev);
2208
e30f33a5
AR		 2209 ds->num_tx_queues = dev->info->num_tx_queues;
2210
b8311f46 2211 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
0abab9f3
AR		 2212 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2213
d2822e68
AR		 2214 ksz_init_mib_timer(dev);
2215
2216 ds->configure_vlan_while_not_filtering = false;
2217
2218 if (dev->dev_ops->setup) {
2219 ret = dev->dev_ops->setup(ds);
2220 if (ret)
2221 return ret;
2222 }
2223
15f7cfae
VO		 2224 /* Start with learning disabled on standalone user ports, and enabled
2225 * on the CPU port. In lack of other finer mechanisms, learning on the
2226 * CPU port will avoid flooding bridge local addresses on the network
2227 * in some cases.
2228 */
2229 p = &dev->ports[dev->cpu_port];
2230 p->learning = true;
2231
ff319a64
AR		 2232 if (dev->irq > 0) {
2233 ret = ksz_girq_setup(dev);
2234 if (ret)
2235 return ret;
2236
2237 dsa_switch_for_each_user_port(dp, dev->ds) {
2238 ret = ksz_pirq_setup(dev, dp->index);
2239 if (ret)
2240 goto out_girq;
cc13ab18
AR		 2241
2242 ret = ksz_ptp_irq_setup(ds, dp->index);
2243 if (ret)
2244 goto out_pirq;
ff319a64
AR		 2245 }
2246 }
2247
eac1ea20
CE		 2248 ret = ksz_ptp_clock_register(ds);
2249 if (ret) {
2250 dev_err(dev->dev, "Failed to register PTP clock: %d\n", ret);
cc13ab18 2251 goto out_ptpirq;
eac1ea20
CE		 2252 }
2253
ff319a64
AR		 2254 ret = ksz_mdio_register(dev);
2255 if (ret < 0) {
2256 dev_err(dev->dev, "failed to register the mdio");
eac1ea20 2257 goto out_ptp_clock_unregister;
ff319a64
AR		 2258 }
2259
ad08ac18 2260 /* start switch */
b8311f46 2261 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
ad08ac18
AR		 2262 SW_START, SW_START);
2263
d2822e68 2264 return 0;
ff319a64 2265
eac1ea20
CE		 2266out_ptp_clock_unregister:
2267 ksz_ptp_clock_unregister(ds);
cc13ab18
AR		 2268out_ptpirq:
2269 if (dev->irq > 0)
2270 dsa_switch_for_each_user_port(dp, dev->ds)
2271 ksz_ptp_irq_free(ds, dp->index);
ff319a64
AR		 2272out_pirq:
2273 if (dev->irq > 0)
2274 dsa_switch_for_each_user_port(dp, dev->ds)
e1add7dd 2275 ksz_irq_free(&dev->ports[dp->index].pirq);
ff319a64
AR		 2276out_girq:
2277 if (dev->irq > 0)
e1add7dd 2278 ksz_irq_free(&dev->girq);
ff319a64
AR		 2279
2280 return ret;
d2822e68 2281}
d2822e68 2282
c9cd961c
AR		 2283static void ksz_teardown(struct dsa_switch *ds)
2284{
2285 struct ksz_device *dev = ds->priv;
ff319a64
AR		 2286 struct dsa_port *dp;
2287
eac1ea20
CE		 2288 ksz_ptp_clock_unregister(ds);
2289
ff319a64 2290 if (dev->irq > 0) {
cc13ab18
AR		 2291 dsa_switch_for_each_user_port(dp, dev->ds) {
2292 ksz_ptp_irq_free(ds, dp->index);
2293
e1add7dd 2294 ksz_irq_free(&dev->ports[dp->index].pirq);
cc13ab18 2295 }
ff319a64 2296
e1add7dd 2297 ksz_irq_free(&dev->girq);
ff319a64 2298 }
c9cd961c
AR		 2299
2300 if (dev->dev_ops->teardown)
2301 dev->dev_ops->teardown(ds);
2302}
2303
7c6ff470
TH		 2304static void port_r_cnt(struct ksz_device *dev, int port)
2305{
2306 struct ksz_port_mib *mib = &dev->ports[port].mib;
2307 u64 *dropped;
2308
2309 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
a530e6f2 2310 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
7c6ff470
TH		 2311 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2312 &mib->counters[mib->cnt_ptr]);
2313 ++mib->cnt_ptr;
2314 }
2315
2316 /* last one in storage */
a530e6f2 2317 dropped = &mib->counters[dev->info->mib_cnt];
7c6ff470
TH		 2318
2319 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
a530e6f2 2320 while (mib->cnt_ptr < dev->info->mib_cnt) {
7c6ff470
TH		 2321 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2322 dropped, &mib->counters[mib->cnt_ptr]);
2323 ++mib->cnt_ptr;
2324 }
2325 mib->cnt_ptr = 0;
2326}
2327
2328static void ksz_mib_read_work(struct work_struct *work)
2329{
2330 struct ksz_device *dev = container_of(work, struct ksz_device,
469b390e 2331 mib_read.work);
7c6ff470
TH		 2332 struct ksz_port_mib *mib;
2333 struct ksz_port *p;
2334 int i;
2335
462d5250 2336 for (i = 0; i < dev->info->port_cnt; i++) {
6bb9e376
RH		 2337 if (dsa_is_unused_port(dev->ds, i))
2338 continue;
2339
7c6ff470
TH		 2340 p = &dev->ports[i];
2341 mib = &p->mib;
2342 mutex_lock(&mib->cnt_mutex);
2343
2344 /* Only read MIB counters when the port is told to do.
2345 * If not, read only dropped counters when link is not up.
2346 */
2347 if (!p->read) {
2348 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2349
6ca80638 2350 if (!netif_carrier_ok(dp->user))
a530e6f2 2351 mib->cnt_ptr = dev->info->reg_mib_cnt;
7c6ff470
TH		 2352 }
2353 port_r_cnt(dev, i);
2354 p->read = false;
a7f4f13a
OR		 2355
2356 if (dev->dev_ops->r_mib_stat64)
2357 dev->dev_ops->r_mib_stat64(dev, i);
2358
7c6ff470
TH		 2359 mutex_unlock(&mib->cnt_mutex);
2360 }
7c6ff470 2361
469b390e 2362 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
7c6ff470
TH		 2363}
2364
2365void ksz_init_mib_timer(struct ksz_device *dev)
2366{
2367 int i;
2368
469b390e
GM		 2369 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2370
b094c679
PV		 2371 for (i = 0; i < dev->info->port_cnt; i++) {
2372 struct ksz_port_mib *mib = &dev->ports[i].mib;
2373
7c6ff470 2374 dev->dev_ops->port_init_cnt(dev, i);
b094c679
PV		 2375
2376 mib->cnt_ptr = 0;
2377 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2378 }
7c6ff470 2379}
7c6ff470 2380
1958eee8 2381static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
b987e98e
WH		 2382{
2383 struct ksz_device *dev = ds->priv;
c2e86691 2384 u16 val = 0xffff;
8f420456 2385 int ret;
b987e98e 2386
8f420456
OR		 2387 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2388 if (ret)
2389 return ret;
b987e98e
WH		 2390
2391 return val;
2392}
2393
1958eee8 2394static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
b987e98e
WH		 2395{
2396 struct ksz_device *dev = ds->priv;
8f420456 2397 int ret;
b987e98e 2398
8f420456
OR		 2399 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2400 if (ret)
2401 return ret;
b987e98e
WH		 2402
2403 return 0;
2404}
2405
1958eee8 2406static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
1fe94f54
AR		 2407{
2408 struct ksz_device *dev = ds->priv;
2409
08c6d8ba
LM		 2410 switch (dev->chip_id) {
2411 case KSZ8830_CHIP_ID:
1fe94f54
AR		 2412 /* Silicon Errata Sheet (DS80000830A):
2413 * Port 1 does not work with LinkMD Cable-Testing.
2414 * Port 1 does not respond to received PAUSE control frames.
2415 */
2416 if (!port)
2417 return MICREL_KSZ8_P1_ERRATA;
08c6d8ba
LM		 2418 break;
2419 case KSZ9477_CHIP_ID:
2420 /* KSZ9477 Errata DS80000754C
2421 *
2422 * Module 4: Energy Efficient Ethernet (EEE) feature select must
2423 * be manually disabled
2424 * The EEE feature is enabled by default, but it is not fully
2425 * operational. It must be manually disabled through register
2426 * controls. If not disabled, the PHY ports can auto-negotiate
2427 * to enable EEE, and this feature can cause link drops when
2428 * linked to another device supporting EEE.
2429 */
2430 return MICREL_NO_EEE;
1fe94f54
AR		 2431 }
2432
2433 return 0;
2434}
1fe94f54 2435
1958eee8
AR		 2436static void ksz_mac_link_down(struct dsa_switch *ds, int port,
2437 unsigned int mode, phy_interface_t interface)
c30d894b
TH		 2438{
2439 struct ksz_device *dev = ds->priv;
2440 struct ksz_port *p = &dev->ports[port];
2441
2442 /* Read all MIB counters when the link is going down. */
143a102e 2443 p->read = true;
8098bd69
CE		 2444 /* timer started */
2445 if (dev->mib_read_interval)
2446 schedule_delayed_work(&dev->mib_read, 0);
143a102e 2447}
143a102e 2448
1958eee8 2449static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
b987e98e
WH		 2450{
2451 struct ksz_device *dev = ds->priv;
2452
89f09048
FF		 2453 if (sset != ETH_SS_STATS)
2454 return 0;
2455
a530e6f2 2456 return dev->info->mib_cnt;
b987e98e
WH		 2457}
2458
1958eee8
AR		 2459static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2460 uint64_t *buf)
7c6ff470
TH		 2461{
2462 const struct dsa_port *dp = dsa_to_port(ds, port);
2463 struct ksz_device *dev = ds->priv;
2464 struct ksz_port_mib *mib;
2465
2466 mib = &dev->ports[port].mib;
2467 mutex_lock(&mib->cnt_mutex);
2468
2469 /* Only read dropped counters if no link. */
6ca80638 2470 if (!netif_carrier_ok(dp->user))
a530e6f2 2471 mib->cnt_ptr = dev->info->reg_mib_cnt;
7c6ff470 2472 port_r_cnt(dev, port);
a530e6f2 2473 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
7c6ff470
TH		 2474 mutex_unlock(&mib->cnt_mutex);
2475}
7c6ff470 2476
1958eee8
AR		 2477static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2478 struct dsa_bridge bridge,
2479 bool *tx_fwd_offload,
2480 struct netlink_ext_ack *extack)
b987e98e 2481{
c2e86691
TH		 2482 /* port_stp_state_set() will be called after to put the port in
2483 * appropriate state so there is no need to do anything.
2484 */
b987e98e 2485
c2e86691 2486 return 0;
b987e98e
WH		 2487}
2488
1958eee8
AR		 2489static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2490 struct dsa_bridge bridge)
b987e98e 2491{
c2e86691
TH		 2492 /* port_stp_state_set() will be called after to put the port in
2493 * forwarding state so there is no need to do anything.
2494 */
b987e98e
WH		 2495}
2496
1958eee8 2497static void ksz_port_fast_age(struct dsa_switch *ds, int port)
b987e98e
WH		 2498{
2499 struct ksz_device *dev = ds->priv;
b987e98e 2500
c2e86691 2501 dev->dev_ops->flush_dyn_mac_table(dev, port);
b987e98e
WH		 2502}
2503
2c119d99
AR		 2504static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2505{
2506 struct ksz_device *dev = ds->priv;
2507
2508 if (!dev->dev_ops->set_ageing_time)
2509 return -EOPNOTSUPP;
2510
2511 return dev->dev_ops->set_ageing_time(dev, msecs);
2512}
2513
1958eee8
AR		 2514static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2515 const unsigned char *addr, u16 vid,
2516 struct dsa_db db)
e587be75
AR		 2517{
2518 struct ksz_device *dev = ds->priv;
2519
2520 if (!dev->dev_ops->fdb_add)
2521 return -EOPNOTSUPP;
2522
2523 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2524}
e587be75 2525
1958eee8
AR		 2526static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2527 const unsigned char *addr,
2528 u16 vid, struct dsa_db db)
e587be75
AR		 2529{
2530 struct ksz_device *dev = ds->priv;
2531
2532 if (!dev->dev_ops->fdb_del)
2533 return -EOPNOTSUPP;
2534
2535 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2536}
e587be75 2537
1958eee8
AR		 2538static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2539 dsa_fdb_dump_cb_t *cb, void *data)
b987e98e
WH		 2540{
2541 struct ksz_device *dev = ds->priv;
b987e98e 2542
e587be75
AR		 2543 if (!dev->dev_ops->fdb_dump)
2544 return -EOPNOTSUPP;
2545
2546 return dev->dev_ops->fdb_dump(dev, port, cb, data);
b987e98e
WH		 2547}
2548
1958eee8
AR		 2549static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2550 const struct switchdev_obj_port_mdb *mdb,
2551 struct dsa_db db)
b987e98e
WH		 2552{
2553 struct ksz_device *dev = ds->priv;
b987e98e 2554
980c7d17
AR		 2555 if (!dev->dev_ops->mdb_add)
2556 return -EOPNOTSUPP;
b987e98e 2557
980c7d17 2558 return dev->dev_ops->mdb_add(dev, port, mdb, db);
b987e98e
WH		 2559}
2560
1958eee8
AR		 2561static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2562 const struct switchdev_obj_port_mdb *mdb,
2563 struct dsa_db db)
b987e98e
WH		 2564{
2565 struct ksz_device *dev = ds->priv;
b987e98e 2566
980c7d17
AR		 2567 if (!dev->dev_ops->mdb_del)
2568 return -EOPNOTSUPP;
b987e98e 2569
980c7d17 2570 return dev->dev_ops->mdb_del(dev, port, mdb, db);
b987e98e
WH		 2571}
2572
15299227 2573static int ksz_port_setup(struct dsa_switch *ds, int port)
b987e98e
WH		 2574{
2575 struct ksz_device *dev = ds->priv;
2576
74be4bab
VD		 2577 if (!dsa_is_user_port(ds, port))
2578 return 0;
2579
6ca80638 2580 /* setup user port */
c2e86691 2581 dev->dev_ops->port_setup(dev, port, false);
b987e98e 2582
c2e86691
TH		 2583 /* port_stp_state_set() will be called after to enable the port so
2584 * there is no need to do anything.
2585 */
b987e98e
WH		 2586
2587 return 0;
2588}
2589
e593df51 2590void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
de6dd626
AR		 2591{
2592 struct ksz_device *dev = ds->priv;
2593 struct ksz_port *p;
6877102f 2594 const u16 *regs;
de6dd626 2595 u8 data;
e593df51 2596
6877102f 2597 regs = dev->info->regs;
de6dd626 2598
6877102f 2599 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
de6dd626
AR		 2600 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2601
15f7cfae
VO		 2602 p = &dev->ports[port];
2603
de6dd626
AR		 2604 switch (state) {
2605 case BR_STATE_DISABLED:
2606 data |= PORT_LEARN_DISABLE;
2607 break;
2608 case BR_STATE_LISTENING:
2609 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2610 break;
2611 case BR_STATE_LEARNING:
2612 data |= PORT_RX_ENABLE;
15f7cfae
VO		 2613 if (!p->learning)
2614 data |= PORT_LEARN_DISABLE;
de6dd626
AR		 2615 break;
2616 case BR_STATE_FORWARDING:
2617 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
15f7cfae
VO		 2618 if (!p->learning)
2619 data |= PORT_LEARN_DISABLE;
de6dd626
AR		 2620 break;
2621 case BR_STATE_BLOCKING:
2622 data |= PORT_LEARN_DISABLE;
2623 break;
2624 default:
2625 dev_err(ds->dev, "invalid STP state: %d\n", state);
2626 return;
2627 }
2628
6877102f 2629 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
de6dd626 2630
de6dd626
AR		 2631 p->stp_state = state;
2632
2633 ksz_update_port_member(dev, port);
2634}
de6dd626 2635
002841be
OR		 2636static void ksz_port_teardown(struct dsa_switch *ds, int port)
2637{
2638 struct ksz_device *dev = ds->priv;
2639
2640 switch (dev->chip_id) {
2641 case KSZ8563_CHIP_ID:
2642 case KSZ9477_CHIP_ID:
2643 case KSZ9563_CHIP_ID:
2644 case KSZ9567_CHIP_ID:
2645 case KSZ9893_CHIP_ID:
2646 case KSZ9896_CHIP_ID:
2647 case KSZ9897_CHIP_ID:
2648 if (dsa_is_user_port(ds, port))
2649 ksz9477_port_acl_free(dev, port);
2650 }
2651}
2652
15f7cfae
VO		 2653static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2654 struct switchdev_brport_flags flags,
2655 struct netlink_ext_ack *extack)
2656{
2657 if (flags.mask & ~BR_LEARNING)
2658 return -EINVAL;
2659
2660 return 0;
2661}
2662
2663static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2664 struct switchdev_brport_flags flags,
2665 struct netlink_ext_ack *extack)
2666{
2667 struct ksz_device *dev = ds->priv;
2668 struct ksz_port *p = &dev->ports[port];
2669
2670 if (flags.mask & BR_LEARNING) {
2671 p->learning = !!(flags.val & BR_LEARNING);
2672
2673 /* Make the change take effect immediately */
2674 ksz_port_stp_state_set(ds, port, p->stp_state);
2675 }
2676
2677 return 0;
2678}
2679
1958eee8
AR		 2680static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2681 int port,
2682 enum dsa_tag_protocol mp)
534a0431
AR		 2683{
2684 struct ksz_device *dev = ds->priv;
2685 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2686
2687 if (dev->chip_id == KSZ8795_CHIP_ID ||
2688 dev->chip_id == KSZ8794_CHIP_ID ||
2689 dev->chip_id == KSZ8765_CHIP_ID)
2690 proto = DSA_TAG_PROTO_KSZ8795;
2691
2692 if (dev->chip_id == KSZ8830_CHIP_ID ||
b4490809 2693 dev->chip_id == KSZ8563_CHIP_ID ||
ef912fe4
RS		 2694 dev->chip_id == KSZ9893_CHIP_ID ||
2695 dev->chip_id == KSZ9563_CHIP_ID)
534a0431
AR		 2696 proto = DSA_TAG_PROTO_KSZ9893;
2697
2698 if (dev->chip_id == KSZ9477_CHIP_ID ||
2eb3ff3c 2699 dev->chip_id == KSZ9896_CHIP_ID ||
534a0431
AR		 2700 dev->chip_id == KSZ9897_CHIP_ID ||
2701 dev->chip_id == KSZ9567_CHIP_ID)
2702 proto = DSA_TAG_PROTO_KSZ9477;
2703
99b16df0
AR		 2704 if (is_lan937x(dev))
2705 proto = DSA_TAG_PROTO_LAN937X_VALUE;
2706
534a0431
AR		 2707 return proto;
2708}
534a0431 2709
ab32f56a
CE		 2710static int ksz_connect_tag_protocol(struct dsa_switch *ds,
2711 enum dsa_tag_protocol proto)
2712{
2713 struct ksz_tagger_data *tagger_data;
2714
2715 tagger_data = ksz_tagger_data(ds);
2716 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
2717
2718 return 0;
2719}
2720
1958eee8
AR		 2721static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2722 bool flag, struct netlink_ext_ack *extack)
f0d997e3
AR		 2723{
2724 struct ksz_device *dev = ds->priv;
2725
2726 if (!dev->dev_ops->vlan_filtering)
2727 return -EOPNOTSUPP;
2728
2729 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2730}
f0d997e3 2731
1958eee8
AR		 2732static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2733 const struct switchdev_obj_port_vlan *vlan,
2734 struct netlink_ext_ack *extack)
f0d997e3
AR		 2735{
2736 struct ksz_device *dev = ds->priv;
2737
2738 if (!dev->dev_ops->vlan_add)
2739 return -EOPNOTSUPP;
2740
2741 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2742}
f0d997e3 2743
1958eee8
AR		 2744static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2745 const struct switchdev_obj_port_vlan *vlan)
f0d997e3
AR		 2746{
2747 struct ksz_device *dev = ds->priv;
2748
2749 if (!dev->dev_ops->vlan_del)
2750 return -EOPNOTSUPP;
2751
2752 return dev->dev_ops->vlan_del(dev, port, vlan);
2753}
f0d997e3 2754
1958eee8
AR		 2755static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2756 struct dsa_mall_mirror_tc_entry *mirror,
2757 bool ingress, struct netlink_ext_ack *extack)
00a298bb
AR		 2758{
2759 struct ksz_device *dev = ds->priv;
2760
2761 if (!dev->dev_ops->mirror_add)
2762 return -EOPNOTSUPP;
2763
2764 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2765}
00a298bb 2766
1958eee8
AR		 2767static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2768 struct dsa_mall_mirror_tc_entry *mirror)
00a298bb
AR		 2769{
2770 struct ksz_device *dev = ds->priv;
2771
2772 if (dev->dev_ops->mirror_del)
2773 dev->dev_ops->mirror_del(dev, port, mirror);
2774}
00a298bb 2775
1958eee8 2776static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
1fe94f54
AR		 2777{
2778 struct ksz_device *dev = ds->priv;
2779
2780 if (!dev->dev_ops->change_mtu)
2781 return -EOPNOTSUPP;
2782
2783 return dev->dev_ops->change_mtu(dev, port, mtu);
2784}
1fe94f54 2785
1958eee8 2786static int ksz_max_mtu(struct dsa_switch *ds, int port)
1fe94f54
AR		 2787{
2788 struct ksz_device *dev = ds->priv;
2789
838c19f8 2790 switch (dev->chip_id) {
29d1e85f
OR		 2791 case KSZ8795_CHIP_ID:
2792 case KSZ8794_CHIP_ID:
2793 case KSZ8765_CHIP_ID:
2794 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2795 case KSZ8830_CHIP_ID:
2796 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
838c19f8
OR		 2797 case KSZ8563_CHIP_ID:
2798 case KSZ9477_CHIP_ID:
2799 case KSZ9563_CHIP_ID:
2800 case KSZ9567_CHIP_ID:
2801 case KSZ9893_CHIP_ID:
2802 case KSZ9896_CHIP_ID:
2803 case KSZ9897_CHIP_ID:
2804 case LAN9370_CHIP_ID:
2805 case LAN9371_CHIP_ID:
2806 case LAN9372_CHIP_ID:
2807 case LAN9373_CHIP_ID:
2808 case LAN9374_CHIP_ID:
2809 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
2810 }
1fe94f54 2811
838c19f8 2812 return -EOPNOTSUPP;
1fe94f54 2813}
1fe94f54 2814
69d3b36c
OR		 2815static int ksz_validate_eee(struct dsa_switch *ds, int port)
2816{
2817 struct ksz_device *dev = ds->priv;
2818
2819 if (!dev->info->internal_phy[port])
2820 return -EOPNOTSUPP;
2821
2822 switch (dev->chip_id) {
2823 case KSZ8563_CHIP_ID:
2824 case KSZ9477_CHIP_ID:
2825 case KSZ9563_CHIP_ID:
2826 case KSZ9567_CHIP_ID:
2827 case KSZ9893_CHIP_ID:
2828 case KSZ9896_CHIP_ID:
2829 case KSZ9897_CHIP_ID:
2830 return 0;
2831 }
2832
2833 return -EOPNOTSUPP;
2834}
2835
2836static int ksz_get_mac_eee(struct dsa_switch *ds, int port,
2837 struct ethtool_eee *e)
2838{
2839 int ret;
2840
2841 ret = ksz_validate_eee(ds, port);
2842 if (ret)
2843 return ret;
2844
2845 /* There is no documented control of Tx LPI configuration. */
2846 e->tx_lpi_enabled = true;
2847
2848 /* There is no documented control of Tx LPI timer. According to tests
2849 * Tx LPI timer seems to be set by default to minimal value.
2850 */
2851 e->tx_lpi_timer = 0;
2852
2853 return 0;
2854}
2855
2856static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
2857 struct ethtool_eee *e)
2858{
2859 struct ksz_device *dev = ds->priv;
2860 int ret;
2861
2862 ret = ksz_validate_eee(ds, port);
2863 if (ret)
2864 return ret;
2865
2866 if (!e->tx_lpi_enabled) {
2867 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
2868 return -EINVAL;
2869 }
2870
2871 if (e->tx_lpi_timer) {
2872 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
2873 return -EINVAL;
2874 }
2875
2876 return 0;
2877}
2878
f3d890f5
AR		 2879static void ksz_set_xmii(struct ksz_device *dev, int port,
2880 phy_interface_t interface)
dc1c596e
AR		 2881{
2882 const u8 *bitval = dev->info->xmii_ctrl1;
b19ac41f 2883 struct ksz_port *p = &dev->ports[port];
dc1c596e
AR		 2884 const u16 *regs = dev->info->regs;
2885 u8 data8;
2886
2887 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2888
b19ac41f
AR		 2889 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2890 P_RGMII_ID_EG_ENABLE);
dc1c596e
AR		 2891
2892 switch (interface) {
2893 case PHY_INTERFACE_MODE_MII:
2894 data8 |= bitval[P_MII_SEL];
2895 break;
2896 case PHY_INTERFACE_MODE_RMII:
2897 data8 |= bitval[P_RMII_SEL];
2898 break;
2899 case PHY_INTERFACE_MODE_GMII:
2900 data8 |= bitval[P_GMII_SEL];
2901 break;
2902 case PHY_INTERFACE_MODE_RGMII:
2903 case PHY_INTERFACE_MODE_RGMII_ID:
2904 case PHY_INTERFACE_MODE_RGMII_TXID:
2905 case PHY_INTERFACE_MODE_RGMII_RXID:
2906 data8 |= bitval[P_RGMII_SEL];
0ab7f6bf 2907 /* On KSZ9893, disable RGMII in-band status support */
32cbac21 2908 if (dev->chip_id == KSZ9893_CHIP_ID ||
ef912fe4
RS		 2909 dev->chip_id == KSZ8563_CHIP_ID ||
2910 dev->chip_id == KSZ9563_CHIP_ID)
0ab7f6bf 2911 data8 &= ~P_MII_MAC_MODE;
dc1c596e
AR		 2912 break;
2913 default:
2914 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2915 phy_modes(interface), port);
2916 return;
2917 }
2918
b19ac41f
AR		 2919 if (p->rgmii_tx_val)
2920 data8 |= P_RGMII_ID_EG_ENABLE;
2921
2922 if (p->rgmii_rx_val)
2923 data8 |= P_RGMII_ID_IG_ENABLE;
2924
dc1c596e
AR		 2925 /* Write the updated value */
2926 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2927}
2928
0ab7f6bf
AR		 2929phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
2930{
2931 const u8 *bitval = dev->info->xmii_ctrl1;
2932 const u16 *regs = dev->info->regs;
2933 phy_interface_t interface;
2934 u8 data8;
2935 u8 val;
2936
2937 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2938
2939 val = FIELD_GET(P_MII_SEL_M, data8);
2940
2941 if (val == bitval[P_MII_SEL]) {
2942 if (gbit)
2943 interface = PHY_INTERFACE_MODE_GMII;
2944 else
2945 interface = PHY_INTERFACE_MODE_MII;
2946 } else if (val == bitval[P_RMII_SEL]) {
2947 interface = PHY_INTERFACE_MODE_RGMII;
2948 } else {
2949 interface = PHY_INTERFACE_MODE_RGMII;
2950 if (data8 & P_RGMII_ID_EG_ENABLE)
2951 interface = PHY_INTERFACE_MODE_RGMII_TXID;
2952 if (data8 & P_RGMII_ID_IG_ENABLE) {
2953 interface = PHY_INTERFACE_MODE_RGMII_RXID;
2954 if (data8 & P_RGMII_ID_EG_ENABLE)
2955 interface = PHY_INTERFACE_MODE_RGMII_ID;
2956 }
2957 }
2958
2959 return interface;
2960}
2961
a0cb1aa4
AR		 2962static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
2963 unsigned int mode,
2964 const struct phylink_link_state *state)
2965{
2966 struct ksz_device *dev = ds->priv;
2967
f3d890f5
AR		 2968 if (ksz_is_ksz88x3(dev))
2969 return;
2970
2971 /* Internal PHYs */
2972 if (dev->info->internal_phy[port])
2973 return;
2974
2975 if (phylink_autoneg_inband(mode)) {
2976 dev_err(dev->dev, "In-band AN not supported!\n");
2977 return;
2978 }
2979
2980 ksz_set_xmii(dev, port, state->interface);
2981
a0cb1aa4
AR		 2982 if (dev->dev_ops->phylink_mac_config)
2983 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
b19ac41f
AR		 2984
2985 if (dev->dev_ops->setup_rgmii_delay)
2986 dev->dev_ops->setup_rgmii_delay(dev, port);
a0cb1aa4
AR		 2987}
2988
46f80fa8
AR		 2989bool ksz_get_gbit(struct ksz_device *dev, int port)
2990{
2991 const u8 *bitval = dev->info->xmii_ctrl1;
2992 const u16 *regs = dev->info->regs;
2993 bool gbit = false;
2994 u8 data8;
2995 bool val;
2996
2997 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2998
2999 val = FIELD_GET(P_GMII_1GBIT_M, data8);
3000
3001 if (val == bitval[P_GMII_1GBIT])
3002 gbit = true;
3003
3004 return gbit;
3005}
3006
0ab7f6bf 3007static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
46f80fa8
AR		 3008{
3009 const u8 *bitval = dev->info->xmii_ctrl1;
3010 const u16 *regs = dev->info->regs;
3011 u8 data8;
3012
3013 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3014
3015 data8 &= ~P_GMII_1GBIT_M;
3016
3017 if (gbit)
3018 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
3019 else
3020 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
3021
3022 /* Write the updated value */
3023 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3024}
3025
aa5b8b73
AR		 3026static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
3027{
3028 const u8 *bitval = dev->info->xmii_ctrl0;
3029 const u16 *regs = dev->info->regs;
3030 u8 data8;
3031
3032 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
3033
3034 data8 &= ~P_MII_100MBIT_M;
3035
3036 if (speed == SPEED_100)
3037 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
3038 else
3039 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
3040
3041 /* Write the updated value */
3042 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
3043}
3044
da8cd085 3045static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
aa5b8b73
AR		 3046{
3047 if (speed == SPEED_1000)
3048 ksz_set_gbit(dev, port, true);
3049 else
3050 ksz_set_gbit(dev, port, false);
3051
3052 if (speed == SPEED_100 || speed == SPEED_10)
3053 ksz_set_100_10mbit(dev, port, speed);
3054}
3055
da8cd085
AR		 3056static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
3057 bool tx_pause, bool rx_pause)
8560664f
AR		 3058{
3059 const u8 *bitval = dev->info->xmii_ctrl0;
3060 const u32 *masks = dev->info->masks;
3061 const u16 *regs = dev->info->regs;
3062 u8 mask;
3063 u8 val;
3064
3065 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
3066 masks[P_MII_RX_FLOW_CTRL];
3067
3068 if (duplex == DUPLEX_FULL)
3069 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
3070 else
3071 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
3072
3073 if (tx_pause)
3074 val |= masks[P_MII_TX_FLOW_CTRL];
3075
3076 if (rx_pause)
3077 val |= masks[P_MII_RX_FLOW_CTRL];
3078
3079 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
3080}
3081
3015c503
OR		 3082static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
3083 unsigned int mode,
3084 phy_interface_t interface,
3085 struct phy_device *phydev, int speed,
3086 int duplex, bool tx_pause,
3087 bool rx_pause)
f597d3ad 3088{
da8cd085
AR		 3089 struct ksz_port *p;
3090
3091 p = &dev->ports[port];
3092
3093 /* Internal PHYs */
3094 if (dev->info->internal_phy[port])
3095 return;
3096
3097 p->phydev.speed = speed;
3098
3099 ksz_port_set_xmii_speed(dev, port, speed);
3100
3101 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3015c503
OR		 3102}
3103
3104static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
3105 unsigned int mode,
3106 phy_interface_t interface,
3107 struct phy_device *phydev, int speed,
3108 int duplex, bool tx_pause, bool rx_pause)
3109{
3110 struct ksz_device *dev = ds->priv;
f597d3ad
AR		 3111
3112 if (dev->dev_ops->phylink_mac_link_up)
3113 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
3114 phydev, speed, duplex,
3115 tx_pause, rx_pause);
3116}
3117
91a98917
AR		 3118static int ksz_switch_detect(struct ksz_device *dev)
3119{
b4490809 3120 u8 id1, id2, id4;
91a98917
AR		 3121 u16 id16;
3122 u32 id32;
3123 int ret;
3124
3125 /* read chip id */
3126 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
3127 if (ret)
3128 return ret;
3129
3130 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3131 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3132
3133 switch (id1) {
3134 case KSZ87_FAMILY_ID:
3135 if (id2 == KSZ87_CHIP_ID_95) {
3136 u8 val;
3137
3138 dev->chip_id = KSZ8795_CHIP_ID;
3139
3140 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
3141 if (val & KSZ8_PORT_FIBER_MODE)
3142 dev->chip_id = KSZ8765_CHIP_ID;
3143 } else if (id2 == KSZ87_CHIP_ID_94) {
3144 dev->chip_id = KSZ8794_CHIP_ID;
3145 } else {
3146 return -ENODEV;
3147 }
3148 break;
3149 case KSZ88_FAMILY_ID:
3150 if (id2 == KSZ88_CHIP_ID_63)
3151 dev->chip_id = KSZ8830_CHIP_ID;
3152 else
3153 return -ENODEV;
3154 break;
3155 default:
3156 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
3157 if (ret)
3158 return ret;
3159
3160 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3161 id32 &= ~0xFF;
3162
3163 switch (id32) {
3164 case KSZ9477_CHIP_ID:
2eb3ff3c 3165 case KSZ9896_CHIP_ID:
91a98917 3166 case KSZ9897_CHIP_ID:
91a98917
AR		 3167 case KSZ9567_CHIP_ID:
3168 case LAN9370_CHIP_ID:
3169 case LAN9371_CHIP_ID:
3170 case LAN9372_CHIP_ID:
3171 case LAN9373_CHIP_ID:
3172 case LAN9374_CHIP_ID:
3173 dev->chip_id = id32;
b4490809
OR		 3174 break;
3175 case KSZ9893_CHIP_ID:
3176 ret = ksz_read8(dev, REG_CHIP_ID4,
3177 &id4);
3178 if (ret)
3179 return ret;
3180
3181 if (id4 == SKU_ID_KSZ8563)
3182 dev->chip_id = KSZ8563_CHIP_ID;
ef912fe4
RS		 3183 else if (id4 == SKU_ID_KSZ9563)
3184 dev->chip_id = KSZ9563_CHIP_ID;
b4490809
OR		 3185 else
3186 dev->chip_id = KSZ9893_CHIP_ID;
3187
91a98917
AR		 3188 break;
3189 default:
3190 dev_err(dev->dev,
3191 "unsupported switch detected %x)\n", id32);
3192 return -ENODEV;
3193 }
3194 }
3195 return 0;
3196}
3197
002841be
OR		 3198static int ksz_cls_flower_add(struct dsa_switch *ds, int port,
3199 struct flow_cls_offload *cls, bool ingress)
3200{
3201 struct ksz_device *dev = ds->priv;
3202
3203 switch (dev->chip_id) {
3204 case KSZ8563_CHIP_ID:
3205 case KSZ9477_CHIP_ID:
3206 case KSZ9563_CHIP_ID:
3207 case KSZ9567_CHIP_ID:
3208 case KSZ9893_CHIP_ID:
3209 case KSZ9896_CHIP_ID:
3210 case KSZ9897_CHIP_ID:
3211 return ksz9477_cls_flower_add(ds, port, cls, ingress);
3212 }
3213
3214 return -EOPNOTSUPP;
3215}
3216
3217static int ksz_cls_flower_del(struct dsa_switch *ds, int port,
3218 struct flow_cls_offload *cls, bool ingress)
3219{
3220 struct ksz_device *dev = ds->priv;
3221
3222 switch (dev->chip_id) {
3223 case KSZ8563_CHIP_ID:
3224 case KSZ9477_CHIP_ID:
3225 case KSZ9563_CHIP_ID:
3226 case KSZ9567_CHIP_ID:
3227 case KSZ9893_CHIP_ID:
3228 case KSZ9896_CHIP_ID:
3229 case KSZ9897_CHIP_ID:
3230 return ksz9477_cls_flower_del(ds, port, cls, ingress);
3231 }
3232
3233 return -EOPNOTSUPP;
3234}
3235
71d7920f
AR		 3236/* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3237 * is converted to Hex-decimal using the successive multiplication method. On
3238 * every step, integer part is taken and decimal part is carry forwarded.
3239 */
3240static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3241{
3242 u32 cinc = 0;
3243 u32 txrate;
3244 u32 rate;
3245 u8 temp;
3246 u8 i;
3247
3248 txrate = idle_slope - send_slope;
3249
3250 if (!txrate)
3251 return -EINVAL;
3252
3253 rate = idle_slope;
3254
3255 /* 24 bit register */
3256 for (i = 0; i < 6; i++) {
3257 rate = rate * 16;
3258
3259 temp = rate / txrate;
3260
3261 rate %= txrate;
3262
3263 cinc = ((cinc << 4) | temp);
3264 }
3265
3266 *bw = cinc;
3267
3268 return 0;
3269}
3270
69444581
OR		 3271static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
3272 u8 shaper)
3273{
3274 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3275 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
3276 FIELD_PREP(MTI_SHAPING_M, shaper));
3277}
3278
71d7920f
AR		 3279static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3280 struct tc_cbs_qopt_offload *qopt)
3281{
3282 struct ksz_device *dev = ds->priv;
3283 int ret;
3284 u32 bw;
3285
3286 if (!dev->info->tc_cbs_supported)
3287 return -EOPNOTSUPP;
3288
3289 if (qopt->queue > dev->info->num_tx_queues)
3290 return -EINVAL;
3291
3292 /* Queue Selection */
3293 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
3294 if (ret)
3295 return ret;
3296
3297 if (!qopt->enable)
69444581
OR		 3298 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3299 MTI_SHAPING_OFF);
71d7920f
AR		 3300
3301 /* High Credit */
3302 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3303 qopt->hicredit);
3304 if (ret)
3305 return ret;
3306
3307 /* Low Credit */
3308 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3309 qopt->locredit);
3310 if (ret)
3311 return ret;
3312
3313 /* Credit Increment Register */
3314 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
3315 if (ret)
3316 return ret;
3317
3318 if (dev->dev_ops->tc_cbs_set_cinc) {
3319 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3320 if (ret)
3321 return ret;
3322 }
3323
69444581
OR		 3324 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3325 MTI_SHAPING_SRP);
71d7920f
AR		 3326}
3327
c570f861
OR		 3328static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
3329{
3330 int queue, ret;
3331
3332 /* Configuration will not take effect until the last Port Queue X
3333 * Egress Limit Control Register is written.
3334 */
3335 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3336 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
3337 KSZ9477_OUT_RATE_NO_LIMIT);
3338 if (ret)
3339 return ret;
3340 }
3341
3342 return 0;
3343}
3344
3345static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
3346 int band)
3347{
3348 /* Compared to queues, bands prioritize packets differently. In strict
3349 * priority mode, the lowest priority is assigned to Queue 0 while the
3350 * highest priority is given to Band 0.
3351 */
3352 return p->bands - 1 - band;
3353}
3354
3355static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
3356{
3357 int ret;
3358
3359 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3360 if (ret)
3361 return ret;
3362
3363 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3364 MTI_SHAPING_OFF);
3365}
3366
3367static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
3368 int weight)
3369{
3370 int ret;
3371
3372 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
3373 if (ret)
3374 return ret;
3375
3376 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3377 MTI_SHAPING_OFF);
3378 if (ret)
3379 return ret;
3380
3381 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
3382}
3383
3384static int ksz_tc_ets_add(struct ksz_device *dev, int port,
3385 struct tc_ets_qopt_offload_replace_params *p)
3386{
3387 int ret, band, tc_prio;
3388 u32 queue_map = 0;
3389
3390 /* In order to ensure proper prioritization, it is necessary to set the
3391 * rate limit for the related queue to zero. Otherwise strict priority
3392 * or WRR mode will not work. This is a hardware limitation.
3393 */
3394 ret = ksz_disable_egress_rate_limit(dev, port);
3395 if (ret)
3396 return ret;
3397
3398 /* Configure queue scheduling mode for all bands. Currently only strict
3399 * prio mode is supported.
3400 */
3401 for (band = 0; band < p->bands; band++) {
3402 int queue = ksz_ets_band_to_queue(p, band);
3403
3404 ret = ksz_queue_set_strict(dev, port, queue);
3405 if (ret)
3406 return ret;
3407 }
3408
3409 /* Configure the mapping between traffic classes and queues. Note:
3410 * priomap variable support 16 traffic classes, but the chip can handle
3411 * only 8 classes.
3412 */
3413 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
3414 int queue;
3415
3416 if (tc_prio > KSZ9477_MAX_TC_PRIO)
3417 break;
3418
3419 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
3420 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3421 }
3422
3423 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3424}
3425
3426static int ksz_tc_ets_del(struct ksz_device *dev, int port)
3427{
3428 int ret, queue, tc_prio, s;
3429 u32 queue_map = 0;
3430
3431 /* To restore the default chip configuration, set all queues to use the
3432 * WRR scheduler with a weight of 1.
3433 */
3434 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3435 ret = ksz_queue_set_wrr(dev, port, queue,
3436 KSZ9477_DEFAULT_WRR_WEIGHT);
3437 if (ret)
3438 return ret;
3439 }
3440
3441 switch (dev->info->num_tx_queues) {
3442 case 2:
3443 s = 2;
3444 break;
3445 case 4:
3446 s = 1;
3447 break;
3448 case 8:
3449 s = 0;
3450 break;
3451 default:
3452 return -EINVAL;
3453 }
3454
3455 /* Revert the queue mapping for TC-priority to its default setting on
3456 * the chip.
3457 */
3458 for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) {
3459 int queue;
3460
3461 queue = tc_prio >> s;
3462 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
3463 }
3464
3465 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3466}
3467
3468static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
3469 struct tc_ets_qopt_offload_replace_params *p)
3470{
3471 int band;
3472
3473 /* Since it is not feasible to share one port among multiple qdisc,
3474 * the user must configure all available queues appropriately.
3475 */
3476 if (p->bands != dev->info->num_tx_queues) {
3477 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
3478 dev->info->num_tx_queues);
3479 return -EOPNOTSUPP;
3480 }
3481
3482 for (band = 0; band < p->bands; ++band) {
3483 /* The KSZ switches utilize a weighted round robin configuration
3484 * where a certain number of packets can be transmitted from a
3485 * queue before the next queue is serviced. For more information
3486 * on this, refer to section 5.2.8.4 of the KSZ8565R
3487 * documentation on the Port Transmit Queue Control 1 Register.
3488 * However, the current ETS Qdisc implementation (as of February
3489 * 2023) assigns a weight to each queue based on the number of
3490 * bytes or extrapolated bandwidth in percentages. Since this
3491 * differs from the KSZ switches' method and we don't want to
3492 * fake support by converting bytes to packets, it is better to
3493 * return an error instead.
3494 */
3495 if (p->quanta[band]) {
3496 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
3497 return -EOPNOTSUPP;
3498 }
3499 }
3500
3501 return 0;
3502}
3503
3504static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
3505 struct tc_ets_qopt_offload *qopt)
3506{
3507 struct ksz_device *dev = ds->priv;
3508 int ret;
3509
3510 if (!dev->info->tc_ets_supported)
3511 return -EOPNOTSUPP;
3512
3513 if (qopt->parent != TC_H_ROOT) {
3514 dev_err(dev->dev, "Parent should be \"root\"\n");
3515 return -EOPNOTSUPP;
3516 }
3517
3518 switch (qopt->command) {
3519 case TC_ETS_REPLACE:
3520 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
3521 if (ret)
3522 return ret;
3523
3524 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
3525 case TC_ETS_DESTROY:
3526 return ksz_tc_ets_del(dev, port);
3527 case TC_ETS_STATS:
3528 case TC_ETS_GRAFT:
3529 return -EOPNOTSUPP;
3530 }
3531
3532 return -EOPNOTSUPP;
3533}
3534
71d7920f
AR		 3535static int ksz_setup_tc(struct dsa_switch *ds, int port,
3536 enum tc_setup_type type, void *type_data)
3537{
3538 switch (type) {
3539 case TC_SETUP_QDISC_CBS:
3540 return ksz_setup_tc_cbs(ds, port, type_data);
c570f861
OR		 3541 case TC_SETUP_QDISC_ETS:
3542 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
71d7920f
AR		 3543 default:
3544 return -EOPNOTSUPP;
3545 }
3546}
3547
d264f244
OR		 3548static void ksz_get_wol(struct dsa_switch *ds, int port,
3549 struct ethtool_wolinfo *wol)
3550{
3551 struct ksz_device *dev = ds->priv;
3552
3553 if (dev->dev_ops->get_wol)
3554 dev->dev_ops->get_wol(dev, port, wol);
3555}
3556
3557static int ksz_set_wol(struct dsa_switch *ds, int port,
3558 struct ethtool_wolinfo *wol)
3559{
3560 struct ksz_device *dev = ds->priv;
3561
3562 if (dev->dev_ops->set_wol)
3563 return dev->dev_ops->set_wol(dev, port, wol);
3564
3565 return -EOPNOTSUPP;
3566}
3567
2d61298f
LM		 3568static int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
3569 const unsigned char *addr)
3570{
3571 struct dsa_port *dp = dsa_to_port(ds, port);
3b454b63 3572 struct ethtool_wolinfo wol;
2d61298f
LM		 3573
3574 if (dp->hsr_dev) {
3575 dev_err(ds->dev,
3576 "Cannot change MAC address on port %d with active HSR offload\n",
3577 port);
3578 return -EBUSY;
3579 }
3580
3b454b63
OR		 3581 ksz_get_wol(ds, dp->index, &wol);
3582 if (wol.wolopts & WAKE_MAGIC) {
3583 dev_err(ds->dev,
3584 "Cannot change MAC address on port %d with active Wake on Magic Packet\n",
3585 port);
3586 return -EBUSY;
3587 }
3588
2d61298f
LM		 3589 return 0;
3590}
3591
3b454b63
OR		 3592/**
3593 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port
3594 * can be used as a global address.
3595 * @ds: Pointer to the DSA switch structure.
3596 * @port: The port number on which the MAC address is to be checked.
3597 *
3598 * This function examines the MAC address set on the specified port and
3599 * determines if it can be used as a global address for the switch.
3600 *
3601 * Return: true if the port's MAC address can be used as a global address, false
3602 * otherwise.
3603 */
3604bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
3605{
3606 struct net_device *user = dsa_to_port(ds, port)->user;
3607 const unsigned char *addr = user->dev_addr;
3608 struct ksz_switch_macaddr *switch_macaddr;
3609 struct ksz_device *dev = ds->priv;
3610
3611 ASSERT_RTNL();
3612
3613 switch_macaddr = dev->switch_macaddr;
3614 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr))
3615 return false;
3616
3617 return true;
3618}
3619
2d61298f
LM		 3620/* Program the switch's MAC address register with the MAC address of the
3621 * requesting user port. This single address is used by the switch for multiple
3622 * features, like HSR self-address filtering and WoL. Other user ports are
3623 * allowed to share ownership of this address as long as their MAC address is
3624 * the same. The user ports' MAC addresses must not change while they have
3625 * ownership of the switch MAC address.
3626 */
3b454b63
OR		 3627int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
3628 struct netlink_ext_ack *extack)
2d61298f 3629{
6ca80638
FF		 3630 struct net_device *user = dsa_to_port(ds, port)->user;
3631 const unsigned char *addr = user->dev_addr;
2d61298f
LM		 3632 struct ksz_switch_macaddr *switch_macaddr;
3633 struct ksz_device *dev = ds->priv;
3634 const u16 *regs = dev->info->regs;
3635 int i;
3636
3637 /* Make sure concurrent MAC address changes are blocked */
3638 ASSERT_RTNL();
3639
3640 switch_macaddr = dev->switch_macaddr;
3641 if (switch_macaddr) {
3642 if (!ether_addr_equal(switch_macaddr->addr, addr)) {
3643 NL_SET_ERR_MSG_FMT_MOD(extack,
3644 "Switch already configured for MAC address %pM",
3645 switch_macaddr->addr);
3646 return -EBUSY;
3647 }
3648
3649 refcount_inc(&switch_macaddr->refcount);
3650 return 0;
3651 }
3652
3653 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL);
3654 if (!switch_macaddr)
3655 return -ENOMEM;
3656
3657 ether_addr_copy(switch_macaddr->addr, addr);
3658 refcount_set(&switch_macaddr->refcount, 1);
3659 dev->switch_macaddr = switch_macaddr;
3660
3661 /* Program the switch MAC address to hardware */
3662 for (i = 0; i < ETH_ALEN; i++)
3663 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]);
3664
3665 return 0;
3666}
3667
3b454b63 3668void ksz_switch_macaddr_put(struct dsa_switch *ds)
2d61298f
LM		 3669{
3670 struct ksz_switch_macaddr *switch_macaddr;
3671 struct ksz_device *dev = ds->priv;
3672 const u16 *regs = dev->info->regs;
3673 int i;
3674
3675 /* Make sure concurrent MAC address changes are blocked */
3676 ASSERT_RTNL();
3677
3678 switch_macaddr = dev->switch_macaddr;
3679 if (!refcount_dec_and_test(&switch_macaddr->refcount))
3680 return;
3681
3682 for (i = 0; i < ETH_ALEN; i++)
3683 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0);
3684
3685 dev->switch_macaddr = NULL;
3686 kfree(switch_macaddr);
3687}
3688
3689static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr,
3690 struct netlink_ext_ack *extack)
3691{
3692 struct ksz_device *dev = ds->priv;
3693 enum hsr_version ver;
3694 int ret;
3695
3696 ret = hsr_get_version(hsr, &ver);
3697 if (ret)
3698 return ret;
3699
3700 if (dev->chip_id != KSZ9477_CHIP_ID) {
3701 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload");
3702 return -EOPNOTSUPP;
3703 }
3704
3705 /* KSZ9477 can support HW offloading of only 1 HSR device */
3706 if (dev->hsr_dev && hsr != dev->hsr_dev) {
3707 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR");
3708 return -EOPNOTSUPP;
3709 }
3710
3711 /* KSZ9477 only supports HSR v0 and v1 */
3712 if (!(ver == HSR_V0 || ver == HSR_V1)) {
3713 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported");
3714 return -EOPNOTSUPP;
3715 }
3716
3717 /* Self MAC address filtering, to avoid frames traversing
3718 * the HSR ring more than once.
3719 */
3720 ret = ksz_switch_macaddr_get(ds, port, extack);
3721 if (ret)
3722 return ret;
3723
3724 ksz9477_hsr_join(ds, port, hsr);
3725 dev->hsr_dev = hsr;
3726 dev->hsr_ports |= BIT(port);
3727
3728 return 0;
3729}
3730
3731static int ksz_hsr_leave(struct dsa_switch *ds, int port,
3732 struct net_device *hsr)
3733{
3734 struct ksz_device *dev = ds->priv;
3735
3736 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID);
3737
3738 ksz9477_hsr_leave(ds, port, hsr);
3739 dev->hsr_ports &= ~BIT(port);
3740 if (!dev->hsr_ports)
3741 dev->hsr_dev = NULL;
3742
3743 ksz_switch_macaddr_put(ds);
3744
3745 return 0;
3746}
3747
1958eee8
AR		 3748static const struct dsa_switch_ops ksz_switch_ops = {
3749 .get_tag_protocol = ksz_get_tag_protocol,
ab32f56a 3750 .connect_tag_protocol = ksz_connect_tag_protocol,
1958eee8
AR		 3751 .get_phy_flags = ksz_get_phy_flags,
3752 .setup = ksz_setup,
c9cd961c 3753 .teardown = ksz_teardown,
1958eee8
AR		 3754 .phy_read = ksz_phy_read16,
3755 .phy_write = ksz_phy_write16,
3756 .phylink_get_caps = ksz_phylink_get_caps,
a0cb1aa4 3757 .phylink_mac_config = ksz_phylink_mac_config,
f597d3ad 3758 .phylink_mac_link_up = ksz_phylink_mac_link_up,
1958eee8 3759 .phylink_mac_link_down = ksz_mac_link_down,
15299227 3760 .port_setup = ksz_port_setup,
2c119d99 3761 .set_ageing_time = ksz_set_ageing_time,
1958eee8
AR		 3762 .get_strings = ksz_get_strings,
3763 .get_ethtool_stats = ksz_get_ethtool_stats,
3764 .get_sset_count = ksz_sset_count,
3765 .port_bridge_join = ksz_port_bridge_join,
3766 .port_bridge_leave = ksz_port_bridge_leave,
2d61298f
LM		 3767 .port_hsr_join = ksz_hsr_join,
3768 .port_hsr_leave = ksz_hsr_leave,
3769 .port_set_mac_address = ksz_port_set_mac_address,
1958eee8 3770 .port_stp_state_set = ksz_port_stp_state_set,
002841be 3771 .port_teardown = ksz_port_teardown,
15f7cfae
VO		 3772 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
3773 .port_bridge_flags = ksz_port_bridge_flags,
1958eee8
AR		 3774 .port_fast_age = ksz_port_fast_age,
3775 .port_vlan_filtering = ksz_port_vlan_filtering,
3776 .port_vlan_add = ksz_port_vlan_add,
3777 .port_vlan_del = ksz_port_vlan_del,
3778 .port_fdb_dump = ksz_port_fdb_dump,
3779 .port_fdb_add = ksz_port_fdb_add,
3780 .port_fdb_del = ksz_port_fdb_del,
3781 .port_mdb_add = ksz_port_mdb_add,
3782 .port_mdb_del = ksz_port_mdb_del,
3783 .port_mirror_add = ksz_port_mirror_add,
3784 .port_mirror_del = ksz_port_mirror_del,
3785 .get_stats64 = ksz_get_stats64,
c4748ff6 3786 .get_pause_stats = ksz_get_pause_stats,
1958eee8
AR		 3787 .port_change_mtu = ksz_change_mtu,
3788 .port_max_mtu = ksz_max_mtu,
d264f244
OR		 3789 .get_wol = ksz_get_wol,
3790 .set_wol = ksz_set_wol,
c59e12a1
CE		 3791 .get_ts_info = ksz_get_ts_info,
3792 .port_hwtstamp_get = ksz_hwtstamp_get,
3793 .port_hwtstamp_set = ksz_hwtstamp_set,
ab32f56a 3794 .port_txtstamp = ksz_port_txtstamp,
90188fff 3795 .port_rxtstamp = ksz_port_rxtstamp,
002841be
OR		 3796 .cls_flower_add = ksz_cls_flower_add,
3797 .cls_flower_del = ksz_cls_flower_del,
71d7920f 3798 .port_setup_tc = ksz_setup_tc,
69d3b36c
OR		 3799 .get_mac_eee = ksz_get_mac_eee,
3800 .set_mac_eee = ksz_set_mac_eee,
1958eee8
AR		 3801};
3802
ee394fea 3803struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
b987e98e
WH		 3804{
3805 struct dsa_switch *ds;
3806 struct ksz_device *swdev;
3807
7e99e347 3808 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
b987e98e
WH		 3809 if (!ds)
3810 return NULL;
3811
7e99e347
VD		 3812 ds->dev = base;
3813 ds->num_ports = DSA_MAX_PORTS;
1958eee8 3814 ds->ops = &ksz_switch_ops;
7e99e347 3815
b987e98e
WH		 3816 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
3817 if (!swdev)
3818 return NULL;
3819
3820 ds->priv = swdev;
3821 swdev->dev = base;
3822
3823 swdev->ds = ds;
3824 swdev->priv = priv;
b987e98e
WH		 3825
3826 return swdev;
3827}
3828EXPORT_SYMBOL(ksz_switch_alloc);
3829
b19ac41f
AR		 3830static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
3831 struct device_node *port_dn)
3832{
3833 phy_interface_t phy_mode = dev->ports[port_num].interface;
3834 int rx_delay = -1, tx_delay = -1;
3835
3836 if (!phy_interface_mode_is_rgmii(phy_mode))
3837 return;
3838
3839 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
3840 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
3841
3842 if (rx_delay == -1 && tx_delay == -1) {
3843 dev_warn(dev->dev,
3844 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
3845 "please update device tree to specify \"rx-internal-delay-ps\" and "
3846 "\"tx-internal-delay-ps\"",
3847 port_num);
3848
3849 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
3850 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3851 rx_delay = 2000;
3852
3853 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
3854 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
3855 tx_delay = 2000;
3856 }
3857
3858 if (rx_delay < 0)
3859 rx_delay = 0;
3860 if (tx_delay < 0)
3861 tx_delay = 0;
3862
3863 dev->ports[port_num].rgmii_rx_val = rx_delay;
3864 dev->ports[port_num].rgmii_tx_val = tx_delay;
3865}
3866
d67d7247
OR		 3867/**
3868 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
3869 * register value.
3870 * @array: The array of drive strength values to search.
3871 * @array_size: The size of the array.
3872 * @microamp: The drive strength value in microamp to be converted.
3873 *
3874 * This function searches the array of drive strength values for the given
3875 * microamp value and returns the corresponding register value for that drive.
3876 *
3877 * Returns: If found, the corresponding register value for that drive strength
3878 * is returned. Otherwise, -EINVAL is returned indicating an invalid value.
3879 */
3880static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
3881 size_t array_size, int microamp)
3882{
3883 int i;
3884
3885 for (i = 0; i < array_size; i++) {
3886 if (array[i].microamp == microamp)
3887 return array[i].reg_val;
3888 }
3889
3890 return -EINVAL;
3891}
3892
3893/**
3894 * ksz_drive_strength_error() - Report invalid drive strength value
3895 * @dev: ksz device
3896 * @array: The array of drive strength values to search.
3897 * @array_size: The size of the array.
3898 * @microamp: Invalid drive strength value in microamp
3899 *
3900 * This function logs an error message when an unsupported drive strength value
3901 * is detected. It lists out all the supported drive strength values for
3902 * reference in the error message.
3903 */
3904static void ksz_drive_strength_error(struct ksz_device *dev,
3905 const struct ksz_drive_strength *array,
3906 size_t array_size, int microamp)
3907{
3908 char supported_values[100];
3909 size_t remaining_size;
3910 int added_len;
3911 char *ptr;
3912 int i;
3913
3914 remaining_size = sizeof(supported_values);
3915 ptr = supported_values;
3916
3917 for (i = 0; i < array_size; i++) {
3918 added_len = snprintf(ptr, remaining_size,
3919 i == 0 ? "%d" : ", %d", array[i].microamp);
3920
3921 if (added_len >= remaining_size)
3922 break;
3923
3924 ptr += added_len;
3925 remaining_size -= added_len;
3926 }
3927
3928 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
3929 microamp, supported_values);
3930}
3931
3932/**
3933 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477
3934 * chip variants.
3935 * @dev: ksz device
3936 * @props: Array of drive strength properties to be applied
3937 * @num_props: Number of properties in the array
3938 *
3939 * This function configures the drive strength for various KSZ9477 chip variants
3940 * based on the provided properties. It handles chip-specific nuances and
3941 * ensures only valid drive strengths are written to the respective chip.
3942 *
3943 * Return: 0 on successful configuration, a negative error code on failure.
3944 */
3945static int ksz9477_drive_strength_write(struct ksz_device *dev,
3946 struct ksz_driver_strength_prop *props,
3947 int num_props)
3948{
3949 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
3950 int i, ret, reg;
3951 u8 mask = 0;
3952 u8 val = 0;
3953
3954 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
3955 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
3956 props[KSZ_DRIVER_STRENGTH_IO].name);
3957
3958 if (dev->chip_id == KSZ8795_CHIP_ID ||
3959 dev->chip_id == KSZ8794_CHIP_ID ||
3960 dev->chip_id == KSZ8765_CHIP_ID)
3961 reg = KSZ8795_REG_SW_CTRL_20;
3962 else
3963 reg = KSZ9477_REG_SW_IO_STRENGTH;
3964
3965 for (i = 0; i < num_props; i++) {
3966 if (props[i].value == -1)
3967 continue;
3968
3969 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths,
3970 array_size, props[i].value);
3971 if (ret < 0) {
3972 ksz_drive_strength_error(dev, ksz9477_drive_strengths,
3973 array_size, props[i].value);
3974 return ret;
3975 }
3976
3977 mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
3978 val |= ret << props[i].offset;
3979 }
3980
3981 return ksz_rmw8(dev, reg, mask, val);
3982}
3983
3984/**
3985 * ksz8830_drive_strength_write() - Set the drive strength configuration for
3986 * KSZ8830 compatible chip variants.
3987 * @dev: ksz device
3988 * @props: Array of drive strength properties to be set
3989 * @num_props: Number of properties in the array
3990 *
3991 * This function applies the specified drive strength settings to KSZ8830 chip
3992 * variants (KSZ8873, KSZ8863).
3993 * It ensures the configurations align with what the chip variant supports and
3994 * warns or errors out on unsupported settings.
3995 *
3996 * Return: 0 on success, error code otherwise
3997 */
3998static int ksz8830_drive_strength_write(struct ksz_device *dev,
3999 struct ksz_driver_strength_prop *props,
4000 int num_props)
4001{
4002 size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths);
4003 int microamp;
4004 int i, ret;
4005
4006 for (i = 0; i < num_props; i++) {
4007 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
4008 continue;
4009
4010 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4011 props[i].name);
4012 }
4013
4014 microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
4015 ret = ksz_drive_strength_to_reg(ksz8830_drive_strengths, array_size,
4016 microamp);
4017 if (ret < 0) {
4018 ksz_drive_strength_error(dev, ksz8830_drive_strengths,
4019 array_size, microamp);
4020 return ret;
4021 }
4022
4023 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
4024 KSZ8873_DRIVE_STRENGTH_16MA, ret);
4025}
4026
4027/**
4028 * ksz_parse_drive_strength() - Extract and apply drive strength configurations
4029 * from device tree properties.
4030 * @dev: ksz device
4031 *
4032 * This function reads the specified drive strength properties from the
4033 * device tree, validates against the supported chip variants, and sets
4034 * them accordingly. An error should be critical here, as the drive strength
4035 * settings are crucial for EMI compliance.
4036 *
4037 * Return: 0 on success, error code otherwise
4038 */
4039static int ksz_parse_drive_strength(struct ksz_device *dev)
4040{
4041 struct ksz_driver_strength_prop of_props[] = {
4042 [KSZ_DRIVER_STRENGTH_HI] = {
4043 .name = "microchip,hi-drive-strength-microamp",
4044 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
4045 .value = -1,
4046 },
4047 [KSZ_DRIVER_STRENGTH_LO] = {
4048 .name = "microchip,lo-drive-strength-microamp",
4049 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
4050 .value = -1,
4051 },
4052 [KSZ_DRIVER_STRENGTH_IO] = {
4053 .name = "microchip,io-drive-strength-microamp",
4054 .offset = 0, /* don't care */
4055 .value = -1,
4056 },
4057 };
4058 struct device_node *np = dev->dev->of_node;
4059 bool have_any_prop = false;
4060 int i, ret;
4061
4062 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4063 ret = of_property_read_u32(np, of_props[i].name,
4064 &of_props[i].value);
4065 if (ret && ret != -EINVAL)
4066 dev_warn(dev->dev, "Failed to read %s\n",
4067 of_props[i].name);
4068 if (ret)
4069 continue;
4070
4071 have_any_prop = true;
4072 }
4073
4074 if (!have_any_prop)
4075 return 0;
4076
4077 switch (dev->chip_id) {
4078 case KSZ8830_CHIP_ID:
4079 return ksz8830_drive_strength_write(dev, of_props,
4080 ARRAY_SIZE(of_props));
4081 case KSZ8795_CHIP_ID:
4082 case KSZ8794_CHIP_ID:
4083 case KSZ8765_CHIP_ID:
4084 case KSZ8563_CHIP_ID:
4085 case KSZ9477_CHIP_ID:
4086 case KSZ9563_CHIP_ID:
4087 case KSZ9567_CHIP_ID:
4088 case KSZ9893_CHIP_ID:
4089 case KSZ9896_CHIP_ID:
4090 case KSZ9897_CHIP_ID:
4091 return ksz9477_drive_strength_write(dev, of_props,
4092 ARRAY_SIZE(of_props));
4093 default:
4094 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4095 if (of_props[i].value == -1)
4096 continue;
4097
4098 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4099 of_props[i].name);
4100 }
4101 }
4102
4103 return 0;
4104}
4105
6ec23aaa 4106int ksz_switch_register(struct ksz_device *dev)
b987e98e 4107{
462d5250 4108 const struct ksz_chip_data *info;
912aae27 4109 struct device_node *port, *ports;
0c65b2b9 4110 phy_interface_t interface;
edecfa98 4111 unsigned int port_num;
b987e98e 4112 int ret;
198b3478 4113 int i;
b987e98e
WH		 4114
4115 if (dev->pdata)
4116 dev->chip_id = dev->pdata->chip_id;
4117
924352c3
MV		 4118 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
4119 GPIOD_OUT_LOW);
4120 if (IS_ERR(dev->reset_gpio))
4121 return PTR_ERR(dev->reset_gpio);
4122
4123 if (dev->reset_gpio) {
22e72b5e 4124 gpiod_set_value_cansleep(dev->reset_gpio, 1);
5b797980 4125 usleep_range(10000, 12000);
22e72b5e 4126 gpiod_set_value_cansleep(dev->reset_gpio, 0);
1c45ba93 4127 msleep(100);
924352c3
MV		 4128 }
4129
7049f9b5 4130 mutex_init(&dev->dev_mutex);
013572a2 4131 mutex_init(&dev->regmap_mutex);
284fb78e
TH		 4132 mutex_init(&dev->alu_mutex);
4133 mutex_init(&dev->vlan_mutex);
4134
91a98917
AR		 4135 ret = ksz_switch_detect(dev);
4136 if (ret)
4137 return ret;
b987e98e 4138
462d5250
AR		 4139 info = ksz_lookup_info(dev->chip_id);
4140 if (!info)
4141 return -ENODEV;
4142
4143 /* Update the compatible info with the probed one */
4144 dev->info = info;
4145
91a98917
AR		 4146 dev_info(dev->dev, "found switch: %s, rev %i\n",
4147 dev->info->dev_name, dev->chip_rev);
4148
eee16b14
AR		 4149 ret = ksz_check_device_id(dev);
4150 if (ret)
4151 return ret;
4152
6ec23aaa 4153 dev->dev_ops = dev->info->ops;
91a98917 4154
c2e86691 4155 ret = dev->dev_ops->init(dev);
b987e98e
WH		 4156 if (ret)
4157 return ret;
4158
198b3478
AR		 4159 dev->ports = devm_kzalloc(dev->dev,
4160 dev->info->port_cnt * sizeof(struct ksz_port),
4161 GFP_KERNEL);
4162 if (!dev->ports)
4163 return -ENOMEM;
4164
4165 for (i = 0; i < dev->info->port_cnt; i++) {
4166 spin_lock_init(&dev->ports[i].mib.stats64_lock);
4167 mutex_init(&dev->ports[i].mib.cnt_mutex);
4168 dev->ports[i].mib.counters =
4169 devm_kzalloc(dev->dev,
4170 sizeof(u64) * (dev->info->mib_cnt + 1),
4171 GFP_KERNEL);
4172 if (!dev->ports[i].mib.counters)
4173 return -ENOMEM;
f3c16545
AR		 4174
4175 dev->ports[i].ksz_dev = dev;
4176 dev->ports[i].num = i;
198b3478
AR		 4177 }
4178
4179 /* set the real number of ports */
4180 dev->ds->num_ports = dev->info->port_cnt;
4181
8c29bebb
TH		 4182 /* Host port interface will be self detected, or specifically set in
4183 * device tree.
4184 */
462d5250 4185 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
edecfa98 4186 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
c2e86691 4187 if (dev->dev->of_node) {
d67d7247
OR		 4188 ret = ksz_parse_drive_strength(dev);
4189 if (ret)
4190 return ret;
4191
0c65b2b9
AL		 4192 ret = of_get_phy_mode(dev->dev->of_node, &interface);
4193 if (ret == 0)
edecfa98 4194 dev->compat_interface = interface;
44e53c88
CE		 4195 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
4196 if (!ports)
4197 ports = of_get_child_by_name(dev->dev->of_node, "ports");
a14bd747 4198 if (ports) {
912aae27
HG		 4199 for_each_available_child_of_node(ports, port) {
4200 if (of_property_read_u32(port, "reg",
4201 &port_num))
4202 continue;
84f7e0bb 4203 if (!(dev->port_mask & BIT(port_num))) {
4204 of_node_put(port);
a14bd747 4205 of_node_put(ports);
912aae27 4206 return -EINVAL;
84f7e0bb 4207 }
912aae27
HG		 4208 of_get_phy_mode(port,
4209 &dev->ports[port_num].interface);
b19ac41f
AR		 4210
4211 ksz_parse_rgmii_delay(dev, port_num, port);
912aae27 4212 }
a14bd747
LH		 4213 of_node_put(ports);
4214 }
79c8bd15
RH		 4215 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
4216 "microchip,synclko-125");
48bf8b8a
RH		 4217 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
4218 "microchip,synclko-disable");
4219 if (dev->synclko_125 && dev->synclko_disable) {
4220 dev_err(dev->dev, "inconsistent synclko settings\n");
4221 return -EINVAL;
4222 }
aed7425d
OR		 4223
4224 dev->wakeup_source = of_property_read_bool(dev->dev->of_node,
4225 "wakeup-source");
c2e86691
TH		 4226 }
4227
4228 ret = dsa_register_switch(dev->ds);
4229 if (ret) {
4230 dev->dev_ops->exit(dev);
4231 return ret;
4232 }
4233
8098bd69 4234 /* Read MIB counters every 30 seconds to avoid overflow. */
12c740c8 4235 dev->mib_read_interval = msecs_to_jiffies(5000);
8098bd69
CE		 4236
4237 /* Start the MIB timer. */
4238 schedule_delayed_work(&dev->mib_read, 0);
4239
7a8988a1 4240 return ret;
b987e98e
WH		 4241}
4242EXPORT_SYMBOL(ksz_switch_register);
4243
4244void ksz_switch_remove(struct ksz_device *dev)
4245{
7c6ff470 4246 /* timer started */
ef1100ef
AR		 4247 if (dev->mib_read_interval) {
4248 dev->mib_read_interval = 0;
469b390e 4249 cancel_delayed_work_sync(&dev->mib_read);
ef1100ef 4250 }
7c6ff470 4251
c2e86691 4252 dev->dev_ops->exit(dev);
b987e98e 4253 dsa_unregister_switch(dev->ds);
924352c3
MV		 4254
4255 if (dev->reset_gpio)
22e72b5e 4256 gpiod_set_value_cansleep(dev->reset_gpio, 1);
924352c3 4257
b987e98e
WH		 4258}
4259EXPORT_SYMBOL(ksz_switch_remove);
4260
4261MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
4262MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
4263MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)