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a1292595 JB |
1 | /* |
2 | * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | */ | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/gpio/consumer.h> | |
17 | #include <linux/regmap.h> | |
18 | #include <linux/mutex.h> | |
19 | #include <linux/mii.h> | |
4d6a78b4 | 20 | #include <linux/phy.h> |
d99a86ae | 21 | #include <linux/if_bridge.h> |
0620427e | 22 | #include <linux/etherdevice.h> |
a1292595 JB |
23 | |
24 | #include "lan9303.h" | |
25 | ||
a368ca53 EH |
26 | #define LAN9303_NUM_PORTS 3 |
27 | ||
ab78acb1 EH |
28 | /* 13.2 System Control and Status Registers |
29 | * Multiply register number by 4 to get address offset. | |
30 | */ | |
a1292595 JB |
31 | #define LAN9303_CHIP_REV 0x14 |
32 | # define LAN9303_CHIP_ID 0x9303 | |
33 | #define LAN9303_IRQ_CFG 0x15 | |
34 | # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8) | |
35 | # define LAN9303_IRQ_CFG_IRQ_POL BIT(4) | |
36 | # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0) | |
37 | #define LAN9303_INT_STS 0x16 | |
38 | # define LAN9303_INT_STS_PHY_INT2 BIT(27) | |
39 | # define LAN9303_INT_STS_PHY_INT1 BIT(26) | |
40 | #define LAN9303_INT_EN 0x17 | |
41 | # define LAN9303_INT_EN_PHY_INT2_EN BIT(27) | |
42 | # define LAN9303_INT_EN_PHY_INT1_EN BIT(26) | |
43 | #define LAN9303_HW_CFG 0x1D | |
44 | # define LAN9303_HW_CFG_READY BIT(27) | |
45 | # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26) | |
46 | # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25) | |
47 | #define LAN9303_PMI_DATA 0x29 | |
48 | #define LAN9303_PMI_ACCESS 0x2A | |
49 | # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11) | |
50 | # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6) | |
51 | # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0) | |
52 | # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1) | |
53 | #define LAN9303_MANUAL_FC_1 0x68 | |
54 | #define LAN9303_MANUAL_FC_2 0x69 | |
55 | #define LAN9303_MANUAL_FC_0 0x6a | |
56 | #define LAN9303_SWITCH_CSR_DATA 0x6b | |
57 | #define LAN9303_SWITCH_CSR_CMD 0x6c | |
58 | #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31) | |
59 | #define LAN9303_SWITCH_CSR_CMD_RW BIT(30) | |
60 | #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16)) | |
61 | #define LAN9303_VIRT_PHY_BASE 0x70 | |
62 | #define LAN9303_VIRT_SPECIAL_CTRL 0x77 | |
4d6a78b4 | 63 | #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/ |
a1292595 | 64 | |
ab78acb1 EH |
65 | /*13.4 Switch Fabric Control and Status Registers |
66 | * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA. | |
67 | */ | |
a1292595 JB |
68 | #define LAN9303_SW_DEV_ID 0x0000 |
69 | #define LAN9303_SW_RESET 0x0001 | |
70 | #define LAN9303_SW_RESET_RESET BIT(0) | |
71 | #define LAN9303_SW_IMR 0x0004 | |
72 | #define LAN9303_SW_IPR 0x0005 | |
73 | #define LAN9303_MAC_VER_ID_0 0x0400 | |
74 | #define LAN9303_MAC_RX_CFG_0 0x0401 | |
75 | # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1) | |
76 | # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0) | |
77 | #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410 | |
78 | #define LAN9303_MAC_RX_64_CNT_0 0x0411 | |
79 | #define LAN9303_MAC_RX_127_CNT_0 0x0412 | |
80 | #define LAN9303_MAC_RX_255_CNT_0 0x413 | |
81 | #define LAN9303_MAC_RX_511_CNT_0 0x0414 | |
82 | #define LAN9303_MAC_RX_1023_CNT_0 0x0415 | |
83 | #define LAN9303_MAC_RX_MAX_CNT_0 0x0416 | |
84 | #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417 | |
85 | #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418 | |
86 | #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419 | |
87 | #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a | |
88 | #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b | |
89 | #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c | |
90 | #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d | |
91 | #define LAN9303_MAC_RX_JABB_CNT_0 0x041e | |
92 | #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f | |
93 | #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420 | |
94 | #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421 | |
95 | #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422 | |
96 | #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423 | |
97 | ||
98 | #define LAN9303_MAC_TX_CFG_0 0x0440 | |
99 | # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2) | |
100 | # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1) | |
101 | # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0) | |
102 | #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451 | |
103 | #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452 | |
104 | #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453 | |
105 | #define LAN9303_MAC_TX_64_CNT_0 0x0454 | |
106 | #define LAN9303_MAC_TX_127_CNT_0 0x0455 | |
107 | #define LAN9303_MAC_TX_255_CNT_0 0x0456 | |
108 | #define LAN9303_MAC_TX_511_CNT_0 0x0457 | |
109 | #define LAN9303_MAC_TX_1023_CNT_0 0x0458 | |
110 | #define LAN9303_MAC_TX_MAX_CNT_0 0x0459 | |
111 | #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a | |
112 | #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c | |
113 | #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d | |
114 | #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e | |
115 | #define LAN9303_MAC_TX_LATECOL_0 0x045f | |
116 | #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460 | |
117 | #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461 | |
118 | #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462 | |
119 | #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463 | |
120 | ||
121 | #define LAN9303_MAC_VER_ID_1 0x0800 | |
122 | #define LAN9303_MAC_RX_CFG_1 0x0801 | |
123 | #define LAN9303_MAC_TX_CFG_1 0x0840 | |
124 | #define LAN9303_MAC_VER_ID_2 0x0c00 | |
125 | #define LAN9303_MAC_RX_CFG_2 0x0c01 | |
126 | #define LAN9303_MAC_TX_CFG_2 0x0c40 | |
127 | #define LAN9303_SWE_ALR_CMD 0x1800 | |
ab335349 EH |
128 | # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2) |
129 | # define LAN9303_ALR_CMD_GET_FIRST BIT(1) | |
130 | # define LAN9303_ALR_CMD_GET_NEXT BIT(0) | |
131 | #define LAN9303_SWE_ALR_WR_DAT_0 0x1801 | |
132 | #define LAN9303_SWE_ALR_WR_DAT_1 0x1802 | |
133 | # define LAN9303_ALR_DAT1_VALID BIT(26) | |
134 | # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25) | |
135 | # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25) | |
136 | # define LAN9303_ALR_DAT1_STATIC BIT(24) | |
137 | # define LAN9303_ALR_DAT1_PORT_BITOFFS 16 | |
138 | # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS) | |
139 | #define LAN9303_SWE_ALR_RD_DAT_0 0x1805 | |
140 | #define LAN9303_SWE_ALR_RD_DAT_1 0x1806 | |
141 | #define LAN9303_SWE_ALR_CMD_STS 0x1808 | |
142 | # define ALR_STS_MAKE_PEND BIT(0) | |
a1292595 JB |
143 | #define LAN9303_SWE_VLAN_CMD 0x180b |
144 | # define LAN9303_SWE_VLAN_CMD_RNW BIT(5) | |
145 | # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4) | |
146 | #define LAN9303_SWE_VLAN_WR_DATA 0x180c | |
147 | #define LAN9303_SWE_VLAN_RD_DATA 0x180e | |
148 | # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17) | |
149 | # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16) | |
150 | # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15) | |
151 | # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14) | |
152 | # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13) | |
153 | # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12) | |
154 | #define LAN9303_SWE_VLAN_CMD_STS 0x1810 | |
155 | #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840 | |
2aee4307 EH |
156 | # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7) |
157 | # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p) | |
a1292595 JB |
158 | #define LAN9303_SWE_PORT_STATE 0x1843 |
159 | # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0) | |
160 | # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5) | |
161 | # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4) | |
162 | # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0) | |
163 | # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3) | |
164 | # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2) | |
165 | # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0) | |
166 | # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1) | |
167 | # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0) | |
d99a86ae | 168 | # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3) |
a1292595 JB |
169 | #define LAN9303_SWE_PORT_MIRROR 0x1846 |
170 | # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8) | |
171 | # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7) | |
172 | # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6) | |
173 | # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5) | |
174 | # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4) | |
175 | # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3) | |
176 | # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2) | |
177 | # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1) | |
178 | # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0) | |
d99a86ae | 179 | # define LAN9303_SWE_PORT_MIRROR_DISABLED 0 |
a1292595 | 180 | #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847 |
f7e3bfa1 | 181 | #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3 |
a1292595 JB |
182 | #define LAN9303_BM_CFG 0x1c00 |
183 | #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c | |
184 | # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16)) | |
185 | # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8)) | |
186 | # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0)) | |
187 | ||
451d3ca0 | 188 | #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0)) |
a1292595 JB |
189 | |
190 | /* the built-in PHYs are of type LAN911X */ | |
191 | #define MII_LAN911X_SPECIAL_MODES 0x12 | |
192 | #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f | |
193 | ||
194 | static const struct regmap_range lan9303_valid_regs[] = { | |
195 | regmap_reg_range(0x14, 0x17), /* misc, interrupt */ | |
196 | regmap_reg_range(0x19, 0x19), /* endian test */ | |
197 | regmap_reg_range(0x1d, 0x1d), /* hardware config */ | |
198 | regmap_reg_range(0x23, 0x24), /* general purpose timer */ | |
199 | regmap_reg_range(0x27, 0x27), /* counter */ | |
200 | regmap_reg_range(0x29, 0x2a), /* PMI index regs */ | |
201 | regmap_reg_range(0x68, 0x6a), /* flow control */ | |
202 | regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */ | |
203 | regmap_reg_range(0x6d, 0x6f), /* misc */ | |
204 | regmap_reg_range(0x70, 0x77), /* virtual phy */ | |
205 | regmap_reg_range(0x78, 0x7a), /* GPIO */ | |
206 | regmap_reg_range(0x7c, 0x7e), /* MAC & reset */ | |
207 | regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */ | |
208 | }; | |
209 | ||
210 | static const struct regmap_range lan9303_reserved_ranges[] = { | |
211 | regmap_reg_range(0x00, 0x13), | |
212 | regmap_reg_range(0x18, 0x18), | |
213 | regmap_reg_range(0x1a, 0x1c), | |
214 | regmap_reg_range(0x1e, 0x22), | |
215 | regmap_reg_range(0x25, 0x26), | |
216 | regmap_reg_range(0x28, 0x28), | |
217 | regmap_reg_range(0x2b, 0x67), | |
218 | regmap_reg_range(0x7b, 0x7b), | |
219 | regmap_reg_range(0x7f, 0x7f), | |
220 | regmap_reg_range(0xb8, 0xff), | |
221 | }; | |
222 | ||
223 | const struct regmap_access_table lan9303_register_set = { | |
224 | .yes_ranges = lan9303_valid_regs, | |
225 | .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs), | |
226 | .no_ranges = lan9303_reserved_ranges, | |
227 | .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges), | |
228 | }; | |
229 | EXPORT_SYMBOL(lan9303_register_set); | |
230 | ||
231 | static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg) | |
232 | { | |
233 | int ret, i; | |
234 | ||
235 | /* we can lose arbitration for the I2C case, because the device | |
236 | * tries to detect and read an external EEPROM after reset and acts as | |
237 | * a master on the shared I2C bus itself. This conflicts with our | |
238 | * attempts to access the device as a slave at the same moment. | |
239 | */ | |
240 | for (i = 0; i < 5; i++) { | |
241 | ret = regmap_read(regmap, offset, reg); | |
242 | if (!ret) | |
243 | return 0; | |
244 | if (ret != -EAGAIN) | |
245 | break; | |
246 | msleep(500); | |
247 | } | |
248 | ||
249 | return -EIO; | |
250 | } | |
251 | ||
252 | static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum) | |
253 | { | |
254 | int ret; | |
255 | u32 val; | |
256 | ||
257 | if (regnum > MII_EXPANSION) | |
258 | return -EINVAL; | |
259 | ||
260 | ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val); | |
261 | if (ret) | |
262 | return ret; | |
263 | ||
264 | return val & 0xffff; | |
265 | } | |
266 | ||
267 | static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val) | |
268 | { | |
269 | if (regnum > MII_EXPANSION) | |
270 | return -EINVAL; | |
271 | ||
272 | return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val); | |
273 | } | |
274 | ||
9e866e5d | 275 | static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip) |
a1292595 JB |
276 | { |
277 | int ret, i; | |
278 | u32 reg; | |
279 | ||
280 | for (i = 0; i < 25; i++) { | |
281 | ret = lan9303_read(chip->regmap, LAN9303_PMI_ACCESS, ®); | |
282 | if (ret) { | |
283 | dev_err(chip->dev, | |
284 | "Failed to read pmi access status: %d\n", ret); | |
285 | return ret; | |
286 | } | |
287 | if (!(reg & LAN9303_PMI_ACCESS_MII_BUSY)) | |
288 | return 0; | |
ec5c91c6 | 289 | usleep_range(1000, 2000); |
a1292595 JB |
290 | } |
291 | ||
292 | return -EIO; | |
293 | } | |
294 | ||
9e866e5d | 295 | static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum) |
a1292595 JB |
296 | { |
297 | int ret; | |
298 | u32 val; | |
299 | ||
300 | val = LAN9303_PMI_ACCESS_PHY_ADDR(addr); | |
301 | val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); | |
302 | ||
303 | mutex_lock(&chip->indirect_mutex); | |
304 | ||
9e866e5d | 305 | ret = lan9303_indirect_phy_wait_for_completion(chip); |
a1292595 JB |
306 | if (ret) |
307 | goto on_error; | |
308 | ||
309 | /* start the MII read cycle */ | |
310 | ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val); | |
311 | if (ret) | |
312 | goto on_error; | |
313 | ||
9e866e5d | 314 | ret = lan9303_indirect_phy_wait_for_completion(chip); |
a1292595 JB |
315 | if (ret) |
316 | goto on_error; | |
317 | ||
318 | /* read the result of this operation */ | |
319 | ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val); | |
320 | if (ret) | |
321 | goto on_error; | |
322 | ||
323 | mutex_unlock(&chip->indirect_mutex); | |
324 | ||
325 | return val & 0xffff; | |
326 | ||
327 | on_error: | |
328 | mutex_unlock(&chip->indirect_mutex); | |
329 | return ret; | |
330 | } | |
331 | ||
9e866e5d EH |
332 | static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr, |
333 | int regnum, u16 val) | |
a1292595 JB |
334 | { |
335 | int ret; | |
336 | u32 reg; | |
337 | ||
338 | reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr); | |
339 | reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum); | |
340 | reg |= LAN9303_PMI_ACCESS_MII_WRITE; | |
341 | ||
342 | mutex_lock(&chip->indirect_mutex); | |
343 | ||
9e866e5d | 344 | ret = lan9303_indirect_phy_wait_for_completion(chip); |
a1292595 JB |
345 | if (ret) |
346 | goto on_error; | |
347 | ||
348 | /* write the data first... */ | |
349 | ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val); | |
350 | if (ret) | |
351 | goto on_error; | |
352 | ||
353 | /* ...then start the MII write cycle */ | |
354 | ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg); | |
355 | ||
356 | on_error: | |
357 | mutex_unlock(&chip->indirect_mutex); | |
358 | return ret; | |
359 | } | |
360 | ||
2c340898 EH |
361 | const struct lan9303_phy_ops lan9303_indirect_phy_ops = { |
362 | .phy_read = lan9303_indirect_phy_read, | |
363 | .phy_write = lan9303_indirect_phy_write, | |
364 | }; | |
365 | EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops); | |
366 | ||
a1292595 JB |
367 | static int lan9303_switch_wait_for_completion(struct lan9303 *chip) |
368 | { | |
369 | int ret, i; | |
370 | u32 reg; | |
371 | ||
372 | for (i = 0; i < 25; i++) { | |
373 | ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_CMD, ®); | |
374 | if (ret) { | |
375 | dev_err(chip->dev, | |
376 | "Failed to read csr command status: %d\n", ret); | |
377 | return ret; | |
378 | } | |
379 | if (!(reg & LAN9303_SWITCH_CSR_CMD_BUSY)) | |
380 | return 0; | |
ec5c91c6 | 381 | usleep_range(1000, 2000); |
a1292595 JB |
382 | } |
383 | ||
384 | return -EIO; | |
385 | } | |
386 | ||
387 | static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val) | |
388 | { | |
389 | u32 reg; | |
390 | int ret; | |
391 | ||
392 | reg = regnum; | |
393 | reg |= LAN9303_SWITCH_CSR_CMD_LANES; | |
394 | reg |= LAN9303_SWITCH_CSR_CMD_BUSY; | |
395 | ||
396 | mutex_lock(&chip->indirect_mutex); | |
397 | ||
398 | ret = lan9303_switch_wait_for_completion(chip); | |
399 | if (ret) | |
400 | goto on_error; | |
401 | ||
402 | ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); | |
403 | if (ret) { | |
404 | dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret); | |
405 | goto on_error; | |
406 | } | |
407 | ||
408 | /* trigger write */ | |
409 | ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); | |
410 | if (ret) | |
411 | dev_err(chip->dev, "Failed to write csr command reg: %d\n", | |
412 | ret); | |
413 | ||
414 | on_error: | |
415 | mutex_unlock(&chip->indirect_mutex); | |
416 | return ret; | |
417 | } | |
418 | ||
419 | static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val) | |
420 | { | |
421 | u32 reg; | |
422 | int ret; | |
423 | ||
424 | reg = regnum; | |
425 | reg |= LAN9303_SWITCH_CSR_CMD_LANES; | |
426 | reg |= LAN9303_SWITCH_CSR_CMD_RW; | |
427 | reg |= LAN9303_SWITCH_CSR_CMD_BUSY; | |
428 | ||
429 | mutex_lock(&chip->indirect_mutex); | |
430 | ||
431 | ret = lan9303_switch_wait_for_completion(chip); | |
432 | if (ret) | |
433 | goto on_error; | |
434 | ||
435 | /* trigger read */ | |
436 | ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg); | |
437 | if (ret) { | |
438 | dev_err(chip->dev, "Failed to write csr command reg: %d\n", | |
439 | ret); | |
440 | goto on_error; | |
441 | } | |
442 | ||
443 | ret = lan9303_switch_wait_for_completion(chip); | |
444 | if (ret) | |
445 | goto on_error; | |
446 | ||
447 | ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val); | |
448 | if (ret) | |
449 | dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret); | |
450 | on_error: | |
451 | mutex_unlock(&chip->indirect_mutex); | |
452 | return ret; | |
453 | } | |
454 | ||
2aee4307 EH |
455 | static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum, |
456 | u32 val, u32 mask) | |
457 | { | |
458 | int ret; | |
459 | u32 reg; | |
460 | ||
461 | ret = lan9303_read_switch_reg(chip, regnum, ®); | |
462 | if (ret) | |
463 | return ret; | |
464 | ||
465 | reg = (reg & ~mask) | val; | |
466 | ||
467 | return lan9303_write_switch_reg(chip, regnum, reg); | |
468 | } | |
469 | ||
451d3ca0 EH |
470 | static int lan9303_write_switch_port(struct lan9303 *chip, int port, |
471 | u16 regnum, u32 val) | |
472 | { | |
473 | return lan9303_write_switch_reg( | |
474 | chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); | |
475 | } | |
476 | ||
0a967b4a EH |
477 | static int lan9303_read_switch_port(struct lan9303 *chip, int port, |
478 | u16 regnum, u32 *val) | |
479 | { | |
480 | return lan9303_read_switch_reg( | |
481 | chip, LAN9303_SWITCH_PORT_REG(port, regnum), val); | |
482 | } | |
483 | ||
a1292595 JB |
484 | static int lan9303_detect_phy_setup(struct lan9303 *chip) |
485 | { | |
486 | int reg; | |
487 | ||
488 | /* depending on the 'phy_addr_sel_strap' setting, the three phys are | |
489 | * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the | |
490 | * 'phy_addr_sel_strap' setting directly, so we need a test, which | |
491 | * configuration is active: | |
492 | * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0 | |
493 | * and the IDs are 0-1-2, else it contains something different from | |
494 | * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3. | |
d329ac88 | 495 | * 0xffff is returned on MDIO read with no response. |
a1292595 | 496 | */ |
2c340898 | 497 | reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES); |
a1292595 JB |
498 | if (reg < 0) { |
499 | dev_err(chip->dev, "Failed to detect phy config: %d\n", reg); | |
500 | return reg; | |
501 | } | |
502 | ||
d329ac88 | 503 | if ((reg != 0) && (reg != 0xffff)) |
a1292595 JB |
504 | chip->phy_addr_sel_strap = 1; |
505 | else | |
506 | chip->phy_addr_sel_strap = 0; | |
507 | ||
508 | dev_dbg(chip->dev, "Phy setup '%s' detected\n", | |
509 | chip->phy_addr_sel_strap ? "1-2-3" : "0-1-2"); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
ab335349 EH |
514 | /* Map ALR-port bits to port bitmap, and back */ |
515 | static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 }; | |
516 | static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 }; | |
517 | ||
0620427e EH |
518 | /* Return pointer to first free ALR cache entry, return NULL if none */ |
519 | static struct lan9303_alr_cache_entry * | |
520 | lan9303_alr_cache_find_free(struct lan9303 *chip) | |
521 | { | |
522 | int i; | |
523 | struct lan9303_alr_cache_entry *entr = chip->alr_cache; | |
524 | ||
525 | for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) | |
526 | if (entr->port_map == 0) | |
527 | return entr; | |
528 | ||
529 | return NULL; | |
530 | } | |
531 | ||
532 | /* Return pointer to ALR cache entry matching MAC address */ | |
533 | static struct lan9303_alr_cache_entry * | |
534 | lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr) | |
535 | { | |
536 | int i; | |
537 | struct lan9303_alr_cache_entry *entr = chip->alr_cache; | |
538 | ||
539 | BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1, | |
540 | "ether_addr_equal require u16 alignment"); | |
541 | ||
542 | for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++) | |
543 | if (ether_addr_equal(entr->mac_addr, mac_addr)) | |
544 | return entr; | |
545 | ||
546 | return NULL; | |
547 | } | |
548 | ||
ab335349 EH |
549 | /* Wait a while until mask & reg == value. Otherwise return timeout. */ |
550 | static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, | |
551 | int mask, char value) | |
552 | { | |
553 | int i; | |
554 | ||
555 | for (i = 0; i < 0x1000; i++) { | |
556 | u32 reg; | |
557 | ||
558 | lan9303_read_switch_reg(chip, regno, ®); | |
559 | if ((reg & mask) == value) | |
560 | return 0; | |
561 | usleep_range(1000, 2000); | |
562 | } | |
563 | return -ETIMEDOUT; | |
564 | } | |
565 | ||
566 | static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1) | |
567 | { | |
568 | lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0); | |
569 | lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1); | |
570 | lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, | |
571 | LAN9303_ALR_CMD_MAKE_ENTRY); | |
572 | lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND, | |
573 | 0); | |
574 | lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
579 | typedef void alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1, | |
580 | int portmap, void *ctx); | |
581 | ||
582 | static void lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx) | |
583 | { | |
584 | int i; | |
585 | ||
586 | lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, | |
587 | LAN9303_ALR_CMD_GET_FIRST); | |
588 | lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); | |
589 | ||
590 | for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) { | |
591 | u32 dat0, dat1; | |
592 | int alrport, portmap; | |
593 | ||
594 | lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0); | |
595 | lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1); | |
596 | if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL) | |
597 | break; | |
598 | ||
599 | alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >> | |
600 | LAN9303_ALR_DAT1_PORT_BITOFFS; | |
601 | portmap = alrport_2_portmap[alrport]; | |
602 | ||
603 | cb(chip, dat0, dat1, portmap, ctx); | |
604 | ||
605 | lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, | |
606 | LAN9303_ALR_CMD_GET_NEXT); | |
607 | lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0); | |
608 | } | |
609 | } | |
610 | ||
611 | static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6]) | |
612 | { | |
613 | mac[0] = (dat0 >> 0) & 0xff; | |
614 | mac[1] = (dat0 >> 8) & 0xff; | |
615 | mac[2] = (dat0 >> 16) & 0xff; | |
616 | mac[3] = (dat0 >> 24) & 0xff; | |
617 | mac[4] = (dat1 >> 0) & 0xff; | |
618 | mac[5] = (dat1 >> 8) & 0xff; | |
619 | } | |
620 | ||
621 | struct del_port_learned_ctx { | |
622 | int port; | |
623 | }; | |
624 | ||
625 | /* Clear learned (non-static) entry on given port */ | |
626 | static void alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0, | |
627 | u32 dat1, int portmap, void *ctx) | |
628 | { | |
629 | struct del_port_learned_ctx *del_ctx = ctx; | |
630 | int port = del_ctx->port; | |
631 | ||
632 | if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC)) | |
633 | return; | |
634 | ||
635 | /* learned entries has only one port, we can just delete */ | |
636 | dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */ | |
637 | lan9303_alr_make_entry_raw(chip, dat0, dat1); | |
638 | } | |
639 | ||
640 | struct port_fdb_dump_ctx { | |
641 | int port; | |
642 | void *data; | |
643 | dsa_fdb_dump_cb_t *cb; | |
644 | }; | |
645 | ||
646 | static void alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0, | |
647 | u32 dat1, int portmap, void *ctx) | |
648 | { | |
649 | struct port_fdb_dump_ctx *dump_ctx = ctx; | |
650 | u8 mac[ETH_ALEN]; | |
651 | bool is_static; | |
652 | ||
653 | if ((BIT(dump_ctx->port) & portmap) == 0) | |
654 | return; | |
655 | ||
656 | alr_reg_to_mac(dat0, dat1, mac); | |
657 | is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC); | |
658 | dump_ctx->cb(mac, 0, is_static, dump_ctx->data); | |
659 | } | |
660 | ||
0620427e EH |
661 | /* Set a static ALR entry. Delete entry if port_map is zero */ |
662 | static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac, | |
663 | u8 port_map, bool stp_override) | |
664 | { | |
665 | u32 dat0, dat1, alr_port; | |
666 | ||
667 | dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map); | |
668 | dat1 = LAN9303_ALR_DAT1_STATIC; | |
669 | if (port_map) | |
670 | dat1 |= LAN9303_ALR_DAT1_VALID; | |
671 | /* otherwise no ports: delete entry */ | |
672 | if (stp_override) | |
673 | dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID; | |
674 | ||
675 | alr_port = portmap_2_alrport[port_map & 7]; | |
676 | dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK; | |
677 | dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS; | |
678 | ||
679 | dat0 = 0; | |
680 | dat0 |= (mac[0] << 0); | |
681 | dat0 |= (mac[1] << 8); | |
682 | dat0 |= (mac[2] << 16); | |
683 | dat0 |= (mac[3] << 24); | |
684 | ||
685 | dat1 |= (mac[4] << 0); | |
686 | dat1 |= (mac[5] << 8); | |
687 | ||
688 | lan9303_alr_make_entry_raw(chip, dat0, dat1); | |
689 | } | |
690 | ||
691 | /* Add port to static ALR entry, create new static entry if needed */ | |
692 | static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port, | |
693 | bool stp_override) | |
694 | { | |
695 | struct lan9303_alr_cache_entry *entr; | |
696 | ||
697 | entr = lan9303_alr_cache_find_mac(chip, mac); | |
698 | if (!entr) { /*New entry */ | |
699 | entr = lan9303_alr_cache_find_free(chip); | |
700 | if (!entr) | |
701 | return -ENOSPC; | |
702 | ether_addr_copy(entr->mac_addr, mac); | |
703 | } | |
704 | entr->port_map |= BIT(port); | |
705 | entr->stp_override = stp_override; | |
706 | lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override); | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
711 | /* Delete static port from ALR entry, delete entry if last port */ | |
712 | static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port) | |
713 | { | |
714 | struct lan9303_alr_cache_entry *entr; | |
715 | ||
716 | entr = lan9303_alr_cache_find_mac(chip, mac); | |
717 | if (!entr) | |
718 | return 0; /* no static entry found */ | |
719 | ||
720 | entr->port_map &= ~BIT(port); | |
721 | if (entr->port_map == 0) /* zero means its free again */ | |
30482e4e | 722 | eth_zero_addr(entr->mac_addr); |
0620427e EH |
723 | lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override); |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
9c84258e EH |
728 | static int lan9303_disable_processing_port(struct lan9303 *chip, |
729 | unsigned int port) | |
a1292595 JB |
730 | { |
731 | int ret; | |
732 | ||
733 | /* disable RX, but keep register reset default values else */ | |
451d3ca0 EH |
734 | ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, |
735 | LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES); | |
a1292595 JB |
736 | if (ret) |
737 | return ret; | |
738 | ||
739 | /* disable TX, but keep register reset default values else */ | |
451d3ca0 | 740 | return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, |
a1292595 JB |
741 | LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | |
742 | LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE); | |
743 | } | |
744 | ||
9c84258e EH |
745 | static int lan9303_enable_processing_port(struct lan9303 *chip, |
746 | unsigned int port) | |
a1292595 JB |
747 | { |
748 | int ret; | |
749 | ||
750 | /* enable RX and keep register reset default values else */ | |
451d3ca0 EH |
751 | ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0, |
752 | LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES | | |
753 | LAN9303_MAC_RX_CFG_X_RX_ENABLE); | |
a1292595 JB |
754 | if (ret) |
755 | return ret; | |
756 | ||
757 | /* enable TX and keep register reset default values else */ | |
451d3ca0 | 758 | return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0, |
a1292595 JB |
759 | LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT | |
760 | LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE | | |
761 | LAN9303_MAC_TX_CFG_X_TX_ENABLE); | |
762 | } | |
763 | ||
f7e3bfa1 EH |
764 | /* forward special tagged packets from port 0 to port 1 *or* port 2 */ |
765 | static int lan9303_setup_tagging(struct lan9303 *chip) | |
766 | { | |
767 | int ret; | |
768 | u32 val; | |
769 | /* enable defining the destination port via special VLAN tagging | |
770 | * for port 0 | |
771 | */ | |
772 | ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE, | |
773 | LAN9303_SWE_INGRESS_PORT_TYPE_VLAN); | |
774 | if (ret) | |
775 | return ret; | |
776 | ||
777 | /* tag incoming packets at port 1 and 2 on their way to port 0 to be | |
778 | * able to discover their source port | |
779 | */ | |
780 | val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0; | |
781 | return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val); | |
782 | } | |
783 | ||
a1292595 JB |
784 | /* We want a special working switch: |
785 | * - do not forward packets between port 1 and 2 | |
786 | * - forward everything from port 1 to port 0 | |
787 | * - forward everything from port 2 to port 0 | |
a1292595 JB |
788 | */ |
789 | static int lan9303_separate_ports(struct lan9303 *chip) | |
790 | { | |
791 | int ret; | |
792 | ||
e9292f2c | 793 | lan9303_alr_del_port(chip, eth_stp_addr, 0); |
a1292595 JB |
794 | ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, |
795 | LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 | | |
796 | LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 | | |
797 | LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 | | |
798 | LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING | | |
799 | LAN9303_SWE_PORT_MIRROR_SNIFF_ALL); | |
800 | if (ret) | |
801 | return ret; | |
802 | ||
a1292595 JB |
803 | /* prevent port 1 and 2 from forwarding packets by their own */ |
804 | return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, | |
805 | LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 | | |
806 | LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 | | |
807 | LAN9303_SWE_PORT_STATE_BLOCKING_PORT2); | |
808 | } | |
809 | ||
d99a86ae EH |
810 | static void lan9303_bridge_ports(struct lan9303 *chip) |
811 | { | |
812 | /* ports bridged: remove mirroring */ | |
813 | lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR, | |
814 | LAN9303_SWE_PORT_MIRROR_DISABLED); | |
815 | ||
816 | lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, | |
817 | chip->swe_port_state); | |
e9292f2c | 818 | lan9303_alr_add_port(chip, eth_stp_addr, 0, true); |
d99a86ae EH |
819 | } |
820 | ||
a1292595 JB |
821 | static int lan9303_handle_reset(struct lan9303 *chip) |
822 | { | |
823 | if (!chip->reset_gpio) | |
824 | return 0; | |
825 | ||
826 | if (chip->reset_duration != 0) | |
827 | msleep(chip->reset_duration); | |
828 | ||
829 | /* release (deassert) reset and activate the device */ | |
830 | gpiod_set_value_cansleep(chip->reset_gpio, 0); | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
835 | /* stop processing packets for all ports */ | |
836 | static int lan9303_disable_processing(struct lan9303 *chip) | |
837 | { | |
b3d14a2b | 838 | int p; |
a1292595 | 839 | |
3c91b0c1 | 840 | for (p = 1; p < LAN9303_NUM_PORTS; p++) { |
9c84258e | 841 | int ret = lan9303_disable_processing_port(chip, p); |
b3d14a2b EH |
842 | |
843 | if (ret) | |
844 | return ret; | |
845 | } | |
846 | ||
847 | return 0; | |
a1292595 JB |
848 | } |
849 | ||
850 | static int lan9303_check_device(struct lan9303 *chip) | |
851 | { | |
852 | int ret; | |
853 | u32 reg; | |
854 | ||
855 | ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®); | |
856 | if (ret) { | |
857 | dev_err(chip->dev, "failed to read chip revision register: %d\n", | |
858 | ret); | |
859 | if (!chip->reset_gpio) { | |
860 | dev_dbg(chip->dev, | |
861 | "hint: maybe failed due to missing reset GPIO\n"); | |
862 | } | |
863 | return ret; | |
864 | } | |
865 | ||
866 | if ((reg >> 16) != LAN9303_CHIP_ID) { | |
867 | dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n", | |
868 | reg >> 16); | |
869 | return ret; | |
870 | } | |
871 | ||
872 | /* The default state of the LAN9303 device is to forward packets between | |
873 | * all ports (if not configured differently by an external EEPROM). | |
874 | * The initial state of a DSA device must be forwarding packets only | |
875 | * between the external and the internal ports and no forwarding | |
876 | * between the external ports. In preparation we stop packet handling | |
877 | * at all for now until the LAN9303 device is re-programmed accordingly. | |
878 | */ | |
879 | ret = lan9303_disable_processing(chip); | |
880 | if (ret) | |
881 | dev_warn(chip->dev, "failed to disable switching %d\n", ret); | |
882 | ||
883 | dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff); | |
884 | ||
885 | ret = lan9303_detect_phy_setup(chip); | |
886 | if (ret) { | |
887 | dev_err(chip->dev, | |
888 | "failed to discover phy bootstrap setup: %d\n", ret); | |
889 | return ret; | |
890 | } | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
895 | /* ---------------------------- DSA -----------------------------------*/ | |
896 | ||
5ed4e3eb FF |
897 | static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds, |
898 | int port) | |
a1292595 JB |
899 | { |
900 | return DSA_TAG_PROTO_LAN9303; | |
901 | } | |
902 | ||
903 | static int lan9303_setup(struct dsa_switch *ds) | |
904 | { | |
905 | struct lan9303 *chip = ds->priv; | |
906 | int ret; | |
907 | ||
908 | /* Make sure that port 0 is the cpu port */ | |
909 | if (!dsa_is_cpu_port(ds, 0)) { | |
910 | dev_err(chip->dev, "port 0 is not the CPU port\n"); | |
911 | return -EINVAL; | |
912 | } | |
913 | ||
f7e3bfa1 EH |
914 | ret = lan9303_setup_tagging(chip); |
915 | if (ret) | |
916 | dev_err(chip->dev, "failed to setup port tagging %d\n", ret); | |
917 | ||
a1292595 JB |
918 | ret = lan9303_separate_ports(chip); |
919 | if (ret) | |
920 | dev_err(chip->dev, "failed to separate ports %d\n", ret); | |
921 | ||
9c84258e | 922 | ret = lan9303_enable_processing_port(chip, 0); |
a1292595 JB |
923 | if (ret) |
924 | dev_err(chip->dev, "failed to re-enable switching %d\n", ret); | |
925 | ||
2aee4307 EH |
926 | /* Trap IGMP to port 0 */ |
927 | ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG, | |
928 | LAN9303_SWE_GLB_INGR_IGMP_TRAP | | |
929 | LAN9303_SWE_GLB_INGR_IGMP_PORT(0), | |
930 | LAN9303_SWE_GLB_INGR_IGMP_PORT(1) | | |
931 | LAN9303_SWE_GLB_INGR_IGMP_PORT(2)); | |
932 | if (ret) | |
933 | dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret); | |
934 | ||
a1292595 JB |
935 | return 0; |
936 | } | |
937 | ||
938 | struct lan9303_mib_desc { | |
939 | unsigned int offset; /* offset of first MAC */ | |
940 | const char *name; | |
941 | }; | |
942 | ||
943 | static const struct lan9303_mib_desc lan9303_mib[] = { | |
944 | { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", }, | |
945 | { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", }, | |
946 | { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", }, | |
947 | { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", }, | |
948 | { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", }, | |
949 | { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", }, | |
950 | { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", }, | |
951 | { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", }, | |
952 | { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", }, | |
953 | { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", }, | |
954 | { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", }, | |
955 | { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", }, | |
956 | { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", }, | |
957 | { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", }, | |
958 | { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", }, | |
959 | { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", }, | |
960 | { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", }, | |
961 | { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", }, | |
962 | { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", }, | |
963 | { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", }, | |
964 | { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", }, | |
965 | { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", }, | |
966 | { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "TxUnderRun", }, | |
967 | { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", }, | |
968 | { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", }, | |
969 | { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", }, | |
970 | { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", }, | |
971 | { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", }, | |
972 | { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", }, | |
973 | { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", }, | |
974 | { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", }, | |
975 | { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", }, | |
976 | { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", }, | |
977 | { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", }, | |
978 | { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", }, | |
979 | { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", }, | |
980 | { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", }, | |
981 | }; | |
982 | ||
983 | static void lan9303_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
984 | { | |
985 | unsigned int u; | |
986 | ||
987 | for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { | |
988 | strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name, | |
989 | ETH_GSTRING_LEN); | |
990 | } | |
991 | } | |
992 | ||
993 | static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port, | |
994 | uint64_t *data) | |
995 | { | |
996 | struct lan9303 *chip = ds->priv; | |
0a967b4a | 997 | unsigned int u; |
a1292595 JB |
998 | |
999 | for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) { | |
0a967b4a EH |
1000 | u32 reg; |
1001 | int ret; | |
1002 | ||
1003 | ret = lan9303_read_switch_port( | |
1004 | chip, port, lan9303_mib[u].offset, ®); | |
1005 | ||
a1292595 | 1006 | if (ret) |
0a967b4a EH |
1007 | dev_warn(chip->dev, "Reading status port %d reg %u failed\n", |
1008 | port, lan9303_mib[u].offset); | |
a1292595 JB |
1009 | data[u] = reg; |
1010 | } | |
1011 | } | |
1012 | ||
1013 | static int lan9303_get_sset_count(struct dsa_switch *ds) | |
1014 | { | |
1015 | return ARRAY_SIZE(lan9303_mib); | |
1016 | } | |
1017 | ||
1018 | static int lan9303_phy_read(struct dsa_switch *ds, int phy, int regnum) | |
1019 | { | |
1020 | struct lan9303 *chip = ds->priv; | |
1021 | int phy_base = chip->phy_addr_sel_strap; | |
1022 | ||
1023 | if (phy == phy_base) | |
1024 | return lan9303_virt_phy_reg_read(chip, regnum); | |
1025 | if (phy > phy_base + 2) | |
1026 | return -ENODEV; | |
1027 | ||
2c340898 | 1028 | return chip->ops->phy_read(chip, phy, regnum); |
a1292595 JB |
1029 | } |
1030 | ||
1031 | static int lan9303_phy_write(struct dsa_switch *ds, int phy, int regnum, | |
1032 | u16 val) | |
1033 | { | |
1034 | struct lan9303 *chip = ds->priv; | |
1035 | int phy_base = chip->phy_addr_sel_strap; | |
1036 | ||
1037 | if (phy == phy_base) | |
1038 | return lan9303_virt_phy_reg_write(chip, regnum, val); | |
1039 | if (phy > phy_base + 2) | |
1040 | return -ENODEV; | |
1041 | ||
2c340898 | 1042 | return chip->ops->phy_write(chip, phy, regnum, val); |
a1292595 JB |
1043 | } |
1044 | ||
4d6a78b4 EH |
1045 | static void lan9303_adjust_link(struct dsa_switch *ds, int port, |
1046 | struct phy_device *phydev) | |
1047 | { | |
1048 | struct lan9303 *chip = ds->priv; | |
1049 | int ctl, res; | |
1050 | ||
1051 | if (!phy_is_pseudo_fixed_link(phydev)) | |
1052 | return; | |
1053 | ||
1054 | ctl = lan9303_phy_read(ds, port, MII_BMCR); | |
1055 | ||
1056 | ctl &= ~BMCR_ANENABLE; | |
1057 | ||
1058 | if (phydev->speed == SPEED_100) | |
1059 | ctl |= BMCR_SPEED100; | |
1060 | else if (phydev->speed == SPEED_10) | |
1061 | ctl &= ~BMCR_SPEED100; | |
1062 | else | |
1063 | dev_err(ds->dev, "unsupported speed: %d\n", phydev->speed); | |
1064 | ||
1065 | if (phydev->duplex == DUPLEX_FULL) | |
1066 | ctl |= BMCR_FULLDPLX; | |
1067 | else | |
1068 | ctl &= ~BMCR_FULLDPLX; | |
1069 | ||
1070 | res = lan9303_phy_write(ds, port, MII_BMCR, ctl); | |
1071 | ||
1072 | if (port == chip->phy_addr_sel_strap) { | |
1073 | /* Virtual Phy: Remove Turbo 200Mbit mode */ | |
1074 | lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl); | |
1075 | ||
1076 | ctl &= ~LAN9303_VIRT_SPECIAL_TURBO; | |
1077 | res = regmap_write(chip->regmap, | |
1078 | LAN9303_VIRT_SPECIAL_CTRL, ctl); | |
1079 | } | |
1080 | } | |
1081 | ||
a1292595 JB |
1082 | static int lan9303_port_enable(struct dsa_switch *ds, int port, |
1083 | struct phy_device *phy) | |
1084 | { | |
1085 | struct lan9303 *chip = ds->priv; | |
1086 | ||
ac71a1f9 | 1087 | return lan9303_enable_processing_port(chip, port); |
a1292595 JB |
1088 | } |
1089 | ||
1090 | static void lan9303_port_disable(struct dsa_switch *ds, int port, | |
1091 | struct phy_device *phy) | |
1092 | { | |
1093 | struct lan9303 *chip = ds->priv; | |
1094 | ||
ac71a1f9 EH |
1095 | lan9303_disable_processing_port(chip, port); |
1096 | lan9303_phy_write(ds, chip->phy_addr_sel_strap + port, | |
1097 | MII_BMCR, BMCR_PDOWN); | |
a1292595 JB |
1098 | } |
1099 | ||
d99a86ae EH |
1100 | static int lan9303_port_bridge_join(struct dsa_switch *ds, int port, |
1101 | struct net_device *br) | |
1102 | { | |
1103 | struct lan9303 *chip = ds->priv; | |
1104 | ||
1105 | dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); | |
c8652c83 | 1106 | if (dsa_to_port(ds, 1)->bridge_dev == dsa_to_port(ds, 2)->bridge_dev) { |
d99a86ae EH |
1107 | lan9303_bridge_ports(chip); |
1108 | chip->is_bridged = true; /* unleash stp_state_set() */ | |
1109 | } | |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port, | |
1115 | struct net_device *br) | |
1116 | { | |
1117 | struct lan9303 *chip = ds->priv; | |
1118 | ||
1119 | dev_dbg(chip->dev, "%s(port %d)\n", __func__, port); | |
1120 | if (chip->is_bridged) { | |
1121 | lan9303_separate_ports(chip); | |
1122 | chip->is_bridged = false; | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port, | |
1127 | u8 state) | |
1128 | { | |
1129 | int portmask, portstate; | |
1130 | struct lan9303 *chip = ds->priv; | |
1131 | ||
1132 | dev_dbg(chip->dev, "%s(port %d, state %d)\n", | |
1133 | __func__, port, state); | |
1134 | ||
1135 | switch (state) { | |
1136 | case BR_STATE_DISABLED: | |
1137 | portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; | |
1138 | break; | |
1139 | case BR_STATE_BLOCKING: | |
1140 | case BR_STATE_LISTENING: | |
1141 | portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0; | |
1142 | break; | |
1143 | case BR_STATE_LEARNING: | |
1144 | portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0; | |
1145 | break; | |
1146 | case BR_STATE_FORWARDING: | |
1147 | portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0; | |
1148 | break; | |
1149 | default: | |
1150 | portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0; | |
1151 | dev_err(chip->dev, "unknown stp state: port %d, state %d\n", | |
1152 | port, state); | |
1153 | } | |
1154 | ||
1155 | portmask = 0x3 << (port * 2); | |
1156 | portstate <<= (port * 2); | |
1157 | ||
1158 | chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate; | |
1159 | ||
1160 | if (chip->is_bridged) | |
1161 | lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE, | |
1162 | chip->swe_port_state); | |
1163 | /* else: touching SWE_PORT_STATE would break port separation */ | |
1164 | } | |
1165 | ||
ab335349 EH |
1166 | static void lan9303_port_fast_age(struct dsa_switch *ds, int port) |
1167 | { | |
1168 | struct lan9303 *chip = ds->priv; | |
1169 | struct del_port_learned_ctx del_ctx = { | |
1170 | .port = port, | |
1171 | }; | |
1172 | ||
1173 | dev_dbg(chip->dev, "%s(%d)\n", __func__, port); | |
1174 | lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx); | |
1175 | } | |
1176 | ||
0620427e EH |
1177 | static int lan9303_port_fdb_add(struct dsa_switch *ds, int port, |
1178 | const unsigned char *addr, u16 vid) | |
1179 | { | |
1180 | struct lan9303 *chip = ds->priv; | |
1181 | ||
1182 | dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); | |
1183 | if (vid) | |
1184 | return -EOPNOTSUPP; | |
1185 | ||
1186 | return lan9303_alr_add_port(chip, addr, port, false); | |
1187 | } | |
1188 | ||
1189 | static int lan9303_port_fdb_del(struct dsa_switch *ds, int port, | |
1190 | const unsigned char *addr, u16 vid) | |
1191 | ||
1192 | { | |
1193 | struct lan9303 *chip = ds->priv; | |
1194 | ||
1195 | dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); | |
1196 | if (vid) | |
1197 | return -EOPNOTSUPP; | |
1198 | lan9303_alr_del_port(chip, addr, port); | |
1199 | ||
1200 | return 0; | |
1201 | } | |
1202 | ||
ab335349 EH |
1203 | static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port, |
1204 | dsa_fdb_dump_cb_t *cb, void *data) | |
1205 | { | |
1206 | struct lan9303 *chip = ds->priv; | |
1207 | struct port_fdb_dump_ctx dump_ctx = { | |
1208 | .port = port, | |
1209 | .data = data, | |
1210 | .cb = cb, | |
1211 | }; | |
1212 | ||
1213 | dev_dbg(chip->dev, "%s(%d)\n", __func__, port); | |
1214 | lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx); | |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | ||
0620427e EH |
1219 | static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port, |
1220 | const struct switchdev_obj_port_mdb *mdb, | |
1221 | struct switchdev_trans *trans) | |
1222 | { | |
1223 | struct lan9303 *chip = ds->priv; | |
1224 | ||
1225 | dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, | |
1226 | mdb->vid); | |
1227 | if (mdb->vid) | |
1228 | return -EOPNOTSUPP; | |
1229 | if (lan9303_alr_cache_find_mac(chip, mdb->addr)) | |
1230 | return 0; | |
1231 | if (!lan9303_alr_cache_find_free(chip)) | |
1232 | return -ENOSPC; | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
1237 | static void lan9303_port_mdb_add(struct dsa_switch *ds, int port, | |
1238 | const struct switchdev_obj_port_mdb *mdb, | |
1239 | struct switchdev_trans *trans) | |
1240 | { | |
1241 | struct lan9303 *chip = ds->priv; | |
1242 | ||
1243 | dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, | |
1244 | mdb->vid); | |
1245 | lan9303_alr_add_port(chip, mdb->addr, port, false); | |
1246 | } | |
1247 | ||
1248 | static int lan9303_port_mdb_del(struct dsa_switch *ds, int port, | |
1249 | const struct switchdev_obj_port_mdb *mdb) | |
1250 | { | |
1251 | struct lan9303 *chip = ds->priv; | |
1252 | ||
1253 | dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr, | |
1254 | mdb->vid); | |
1255 | if (mdb->vid) | |
1256 | return -EOPNOTSUPP; | |
1257 | lan9303_alr_del_port(chip, mdb->addr, port); | |
1258 | ||
1259 | return 0; | |
1260 | } | |
1261 | ||
d78d6776 | 1262 | static const struct dsa_switch_ops lan9303_switch_ops = { |
a1292595 JB |
1263 | .get_tag_protocol = lan9303_get_tag_protocol, |
1264 | .setup = lan9303_setup, | |
1265 | .get_strings = lan9303_get_strings, | |
1266 | .phy_read = lan9303_phy_read, | |
1267 | .phy_write = lan9303_phy_write, | |
4d6a78b4 | 1268 | .adjust_link = lan9303_adjust_link, |
a1292595 JB |
1269 | .get_ethtool_stats = lan9303_get_ethtool_stats, |
1270 | .get_sset_count = lan9303_get_sset_count, | |
1271 | .port_enable = lan9303_port_enable, | |
1272 | .port_disable = lan9303_port_disable, | |
d99a86ae EH |
1273 | .port_bridge_join = lan9303_port_bridge_join, |
1274 | .port_bridge_leave = lan9303_port_bridge_leave, | |
1275 | .port_stp_state_set = lan9303_port_stp_state_set, | |
ab335349 | 1276 | .port_fast_age = lan9303_port_fast_age, |
0620427e EH |
1277 | .port_fdb_add = lan9303_port_fdb_add, |
1278 | .port_fdb_del = lan9303_port_fdb_del, | |
ab335349 | 1279 | .port_fdb_dump = lan9303_port_fdb_dump, |
0620427e EH |
1280 | .port_mdb_prepare = lan9303_port_mdb_prepare, |
1281 | .port_mdb_add = lan9303_port_mdb_add, | |
1282 | .port_mdb_del = lan9303_port_mdb_del, | |
a1292595 JB |
1283 | }; |
1284 | ||
1285 | static int lan9303_register_switch(struct lan9303 *chip) | |
1286 | { | |
274cdb46 | 1287 | chip->ds = dsa_switch_alloc(chip->dev, LAN9303_NUM_PORTS); |
a1292595 JB |
1288 | if (!chip->ds) |
1289 | return -ENOMEM; | |
1290 | ||
1291 | chip->ds->priv = chip; | |
1292 | chip->ds->ops = &lan9303_switch_ops; | |
1293 | chip->ds->phys_mii_mask = chip->phy_addr_sel_strap ? 0xe : 0x7; | |
1294 | ||
23c9ee49 | 1295 | return dsa_register_switch(chip->ds); |
a1292595 JB |
1296 | } |
1297 | ||
1298 | static void lan9303_probe_reset_gpio(struct lan9303 *chip, | |
1299 | struct device_node *np) | |
1300 | { | |
1301 | chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset", | |
1302 | GPIOD_OUT_LOW); | |
1303 | ||
97438abc | 1304 | if (IS_ERR(chip->reset_gpio)) { |
a1292595 JB |
1305 | dev_dbg(chip->dev, "No reset GPIO defined\n"); |
1306 | return; | |
1307 | } | |
1308 | ||
1309 | chip->reset_duration = 200; | |
1310 | ||
1311 | if (np) { | |
1312 | of_property_read_u32(np, "reset-duration", | |
1313 | &chip->reset_duration); | |
1314 | } else { | |
1315 | dev_dbg(chip->dev, "reset duration defaults to 200 ms\n"); | |
1316 | } | |
1317 | ||
1318 | /* A sane reset duration should not be longer than 1s */ | |
1319 | if (chip->reset_duration > 1000) | |
1320 | chip->reset_duration = 1000; | |
1321 | } | |
1322 | ||
1323 | int lan9303_probe(struct lan9303 *chip, struct device_node *np) | |
1324 | { | |
1325 | int ret; | |
1326 | ||
1327 | mutex_init(&chip->indirect_mutex); | |
1328 | ||
1329 | lan9303_probe_reset_gpio(chip, np); | |
1330 | ||
1331 | ret = lan9303_handle_reset(chip); | |
1332 | if (ret) | |
1333 | return ret; | |
1334 | ||
1335 | ret = lan9303_check_device(chip); | |
1336 | if (ret) | |
1337 | return ret; | |
1338 | ||
1339 | ret = lan9303_register_switch(chip); | |
1340 | if (ret) { | |
1341 | dev_dbg(chip->dev, "Failed to register switch: %d\n", ret); | |
1342 | return ret; | |
1343 | } | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | EXPORT_SYMBOL(lan9303_probe); | |
1348 | ||
1349 | int lan9303_remove(struct lan9303 *chip) | |
1350 | { | |
1351 | int rc; | |
1352 | ||
1353 | rc = lan9303_disable_processing(chip); | |
1354 | if (rc != 0) | |
1355 | dev_warn(chip->dev, "shutting down failed\n"); | |
1356 | ||
1357 | dsa_unregister_switch(chip->ds); | |
1358 | ||
1359 | /* assert reset to the whole device to prevent it from doing anything */ | |
1360 | gpiod_set_value_cansleep(chip->reset_gpio, 1); | |
1361 | gpiod_unexport(chip->reset_gpio); | |
1362 | ||
1363 | return 0; | |
1364 | } | |
1365 | EXPORT_SYMBOL(lan9303_remove); | |
1366 | ||
1367 | MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>"); | |
1368 | MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch"); | |
1369 | MODULE_LICENSE("GPL v2"); |