[linux-2.6-block.git] / drivers / net / dsa / bcm_sf2.h

/*
 * Broadcom Starfighter2 private context
 *
 * Copyright (C) 2014, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __BCM_SF2_H
#define __BCM_SF2_H

#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/if_vlan.h>

#include <net/dsa.h>

#include "bcm_sf2_regs.h"
#include "b53/b53_priv.h"

struct bcm_sf2_hw_params {
	u16	top_rev;
	u16	core_rev;
	u16	gphy_rev;
	u32	num_gphy;
	u8	num_acb_queue;
	u8	num_rgmii;
	u8	num_ports;
	u8	fcb_pause_override:1;
	u8	acb_packets_inflight:1;
};

#define BCM_SF2_REGS_NAME {\
	"core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
}

#define BCM_SF2_REGS_NUM	6

struct bcm_sf2_port_status {
	unsigned int link;
};

struct bcm_sf2_cfp_priv {
	/* Mutex protecting concurrent accesses to the CFP registers */
	struct mutex lock;
	DECLARE_BITMAP(used, CFP_NUM_RULES);
	DECLARE_BITMAP(unique, CFP_NUM_RULES);
	unsigned int rules_cnt;
	struct list_head rules_list;
};

struct bcm_sf2_priv {
	/* Base registers, keep those in order with BCM_SF2_REGS_NAME */
	void __iomem			*core;
	void __iomem			*reg;
	void __iomem			*intrl2_0;
	void __iomem			*intrl2_1;
	void __iomem			*fcb;
	void __iomem			*acb;

	/* Register offsets indirection tables */
	u32 				type;
	const u16			*reg_offsets;
	unsigned int			core_reg_align;
	unsigned int			num_cfp_rules;

	/* spinlock protecting access to the indirect registers */
	spinlock_t			indir_lock;

	int				irq0;
	int				irq1;
	u32				irq0_stat;
	u32				irq0_mask;
	u32				irq1_stat;
	u32				irq1_mask;

	/* Backing b53_device */
	struct b53_device		*dev;

	struct bcm_sf2_hw_params	hw_params;

	struct bcm_sf2_port_status	port_sts[DSA_MAX_PORTS];

	/* Mask of ports enabled for Wake-on-LAN */
	u32				wol_ports_mask;

	/* MoCA port location */
	int				moca_port;

	/* Bitmask of ports having an integrated PHY */
	unsigned int			int_phy_mask;

	/* Master and slave MDIO bus controller */
	unsigned int			indir_phy_mask;
	struct device_node		*master_mii_dn;
	struct mii_bus			*slave_mii_bus;
	struct mii_bus			*master_mii_bus;

	/* Bitmask of ports needing BRCM tags */
	unsigned int			brcm_tag_mask;

	/* CFP rules context */
	struct bcm_sf2_cfp_priv		cfp;
};

static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
{
	struct b53_device *dev = ds->priv;

	return dev->priv;
}

static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off)
{
	return off << priv->core_reg_align;
}

#define SF2_IO_MACRO(name) \
static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off)	\
{									\
	return readl_relaxed(priv->name + off);				\
}									\
static inline void name##_writel(struct bcm_sf2_priv *priv,		\
				  u32 val, u32 off)			\
{									\
	writel_relaxed(val, priv->name + off);				\
}									\

/* Accesses to 64-bits register requires us to latch the hi/lo pairs
 * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
 * spinlock is automatically grabbed and released to provide relative
 * atomiticy with latched reads/writes.
 */
#define SF2_IO64_MACRO(name) \
static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off)	\
{									\
	u32 indir, dir;							\
	spin_lock(&priv->indir_lock);					\
	dir = name##_readl(priv, off);					\
	indir = reg_readl(priv, REG_DIR_DATA_READ);			\
	spin_unlock(&priv->indir_lock);					\
	return (u64)indir << 32 | dir;					\
}									\
static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val,	\
							u32 off)	\
{									\
	spin_lock(&priv->indir_lock);					\
	reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE);	\
	name##_writel(priv, lower_32_bits(val), off);			\
	spin_unlock(&priv->indir_lock);					\
}

#define SWITCH_INTR_L2(which)						\
static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
						u32 mask)		\
{									\
	priv->irq##which##_mask &= ~(mask);				\
	intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR);	\
}									\
static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
						u32 mask)		\
{									\
	intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET);	\
	priv->irq##which##_mask |= (mask);				\
}									\

static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off)
{
	u32 tmp = bcm_sf2_mangle_addr(priv, off);
	return readl_relaxed(priv->core + tmp);
}

static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off)
{
	u32 tmp = bcm_sf2_mangle_addr(priv, off);
	writel_relaxed(val, priv->core + tmp);
}

static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off)
{
	return readl_relaxed(priv->reg + priv->reg_offsets[off]);
}

static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off)
{
	writel_relaxed(val, priv->reg + priv->reg_offsets[off]);
}

SF2_IO64_MACRO(core);
SF2_IO_MACRO(intrl2_0);
SF2_IO_MACRO(intrl2_1);
SF2_IO_MACRO(fcb);
SF2_IO_MACRO(acb);

SWITCH_INTR_L2(0);
SWITCH_INTR_L2(1);

/* RXNFC */
int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
		      struct ethtool_rxnfc *nfc, u32 *rule_locs);
int bcm_sf2_set_rxnfc(struct dsa_switch *ds, int port,
		      struct ethtool_rxnfc *nfc);
int bcm_sf2_cfp_rst(struct bcm_sf2_priv *priv);
void bcm_sf2_cfp_exit(struct dsa_switch *ds);
int bcm_sf2_cfp_resume(struct dsa_switch *ds);
void bcm_sf2_cfp_get_strings(struct dsa_switch *ds, int port,
			     u32 stringset, uint8_t *data);
void bcm_sf2_cfp_get_ethtool_stats(struct dsa_switch *ds, int port,
				   uint64_t *data);
int bcm_sf2_cfp_get_sset_count(struct dsa_switch *ds, int port, int sset);

#endif /* __BCM_SF2_H */
Commit	Line	Data
246d7f77 FF	1	/*
	2	* Broadcom Starfighter2 private context
	3	*
	4	* Copyright (C) 2014, Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#ifndef __BCM_SF2_H
	13	#define __BCM_SF2_H
	14
	15	#include <linux/platform_device.h>
	16	#include <linux/kernel.h>
	17	#include <linux/io.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/mutex.h>
	20	#include <linux/mii.h>
450b05c1	21	#include <linux/ethtool.h>
680060d3 FF	22	#include <linux/types.h>
680060d3 FF	23	#include <linux/bitops.h>
9c57a771	24	#include <linux/if_vlan.h>
246d7f77 FF	25
	26	#include <net/dsa.h>
	27
	28	#include "bcm_sf2_regs.h"
f458995b	29	#include "b53/b53_priv.h"
246d7f77 FF	30
	31	struct bcm_sf2_hw_params {
	32	u16 top_rev;
	33	u16 core_rev;
aa9aef77	34	u16 gphy_rev;
246d7f77 FF	35	u32 num_gphy;
	36	u8 num_acb_queue;
	37	u8 num_rgmii;
	38	u8 num_ports;
	39	u8 fcb_pause_override:1;
	40	u8 acb_packets_inflight:1;
	41	};
	42
	43	#define BCM_SF2_REGS_NAME {\
	44	"core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
	45	}
	46
	47	#define BCM_SF2_REGS_NUM 6
	48
	49	struct bcm_sf2_port_status {
	50	unsigned int link;
680060d3 FF	51	};
680060d3 FF	52
7318166c FF	53	struct bcm_sf2_cfp_priv {
	54	/* Mutex protecting concurrent accesses to the CFP registers */
	55	struct mutex lock;
	56	DECLARE_BITMAP(used, CFP_NUM_RULES);
ba0696c2	57	DECLARE_BITMAP(unique, CFP_NUM_RULES);
7318166c	58	unsigned int rules_cnt;
ae7a5aff	59	struct list_head rules_list;
7318166c FF	60	};
7318166c FF	61
246d7f77 FF	62	struct bcm_sf2_priv {
	63	/* Base registers, keep those in order with BCM_SF2_REGS_NAME */
	64	void __iomem *core;
	65	void __iomem *reg;
	66	void __iomem *intrl2_0;
	67	void __iomem *intrl2_1;
	68	void __iomem *fcb;
	69	void __iomem *acb;
	70
a78e86ed FF	71	/* Register offsets indirection tables */
	72	u32 type;
	73	const u16 *reg_offsets;
	74	unsigned int core_reg_align;
df191632	75	unsigned int num_cfp_rules;
a78e86ed	76
246d7f77 FF	77	/* spinlock protecting access to the indirect registers */
	78	spinlock_t indir_lock;
	79
	80	int irq0;
	81	int irq1;
	82	u32 irq0_stat;
	83	u32 irq0_mask;
	84	u32 irq1_stat;
	85	u32 irq1_mask;
	86
f458995b FF	87	/* Backing b53_device */
	88	struct b53_device *dev;
	89
246d7f77 FF	90	struct bcm_sf2_hw_params hw_params;
	91
	92	struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS];
96e65d7f FF	93
	94	/* Mask of ports enabled for Wake-on-LAN */
	95	u32 wol_ports_mask;
8b7c94e3 FF	96
	97	/* MoCA port location */
	98	int moca_port;
	99
	100	/* Bitmask of ports having an integrated PHY */
	101	unsigned int int_phy_mask;
461cd1b0 FF	102
	103	/* Master and slave MDIO bus controller */
	104	unsigned int indir_phy_mask;
	105	struct device_node *master_mii_dn;
	106	struct mii_bus *slave_mii_bus;
	107	struct mii_bus *master_mii_bus;
64ff2aef FF	108
	109	/* Bitmask of ports needing BRCM tags */
	110	unsigned int brcm_tag_mask;
7318166c FF	111
	112	/* CFP rules context */
	113	struct bcm_sf2_cfp_priv cfp;
246d7f77 FF	114	};
246d7f77 FF	115
f458995b FF	116	static inline struct bcm_sf2_priv bcm_sf2_to_priv(struct dsa_switch ds)
f458995b FF	117	{
04bed143	118	struct b53_device *dev = ds->priv;
f458995b FF	119
	120	return dev->priv;
	121	}
	122
a78e86ed FF	123	static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off)
	124	{
	125	return off << priv->core_reg_align;
	126	}
	127
246d7f77 FF	128	#define SF2_IO_MACRO(name) \
	129	static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
	130	{ \
fdb71a2d	131	return readl_relaxed(priv->name + off); \
246d7f77 FF	132	} \
	133	static inline void name##_writel(struct bcm_sf2_priv *priv, \
	134	u32 val, u32 off) \
	135	{ \
fdb71a2d	136	writel_relaxed(val, priv->name + off); \
246d7f77 FF	137	} \
	138
	139	/* Accesses to 64-bits register requires us to latch the hi/lo pairs
	140	* using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
	141	* spinlock is automatically grabbed and released to provide relative
	142	* atomiticy with latched reads/writes.
	143	*/
	144	#define SF2_IO64_MACRO(name) \
	145	static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
	146	{ \
	147	u32 indir, dir; \
	148	spin_lock(&priv->indir_lock); \
329b5c58	149	dir = name##_readl(priv, off); \
ddede6d5	150	indir = reg_readl(priv, REG_DIR_DATA_READ); \
246d7f77 FF	151	spin_unlock(&priv->indir_lock); \
	152	return (u64)indir << 32 \| dir; \
	153	} \
03679a14 FF	154	static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val, \
03679a14 FF	155	u32 off) \
246d7f77 FF	156	{ \
	157	spin_lock(&priv->indir_lock); \
	158	reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \
329b5c58	159	name##_writel(priv, lower_32_bits(val), off); \
246d7f77 FF	160	spin_unlock(&priv->indir_lock); \
	161	}
	162
	163	#define SWITCH_INTR_L2(which) \
	164	static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
	165	u32 mask) \
	166	{ \
246d7f77	167	priv->irq##which##_mask &= ~(mask); \
4f101c47	168	intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
246d7f77 FF	169	} \
	170	static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
	171	u32 mask) \
	172	{ \
	173	intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
	174	priv->irq##which##_mask \|= (mask); \
	175	} \
	176
a78e86ed FF	177	static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off)
	178	{
	179	u32 tmp = bcm_sf2_mangle_addr(priv, off);
fdb71a2d	180	return readl_relaxed(priv->core + tmp);
a78e86ed FF	181	}
	182
	183	static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off)
	184	{
	185	u32 tmp = bcm_sf2_mangle_addr(priv, off);
fdb71a2d	186	writel_relaxed(val, priv->core + tmp);
a78e86ed FF	187	}
	188
	189	static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off)
	190	{
fdb71a2d	191	return readl_relaxed(priv->reg + priv->reg_offsets[off]);
a78e86ed FF	192	}
	193
	194	static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off)
	195	{
fdb71a2d	196	writel_relaxed(val, priv->reg + priv->reg_offsets[off]);
a78e86ed FF	197	}
a78e86ed FF	198
246d7f77 FF	199	SF2_IO64_MACRO(core);
	200	SF2_IO_MACRO(intrl2_0);
	201	SF2_IO_MACRO(intrl2_1);
	202	SF2_IO_MACRO(fcb);
	203	SF2_IO_MACRO(acb);
	204
	205	SWITCH_INTR_L2(0);
	206	SWITCH_INTR_L2(1);
	207
7318166c FF	208	/* RXNFC */
	209	int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
	210	struct ethtool_rxnfc nfc, u32 rule_locs);
	211	int bcm_sf2_set_rxnfc(struct dsa_switch *ds, int port,
	212	struct ethtool_rxnfc *nfc);
	213	int bcm_sf2_cfp_rst(struct bcm_sf2_priv *priv);
ae7a5aff	214	void bcm_sf2_cfp_exit(struct dsa_switch *ds);
1c0130f0	215	int bcm_sf2_cfp_resume(struct dsa_switch *ds);
f4ae9c08 FF	216	void bcm_sf2_cfp_get_strings(struct dsa_switch *ds, int port,
	217	u32 stringset, uint8_t *data);
	218	void bcm_sf2_cfp_get_ethtool_stats(struct dsa_switch *ds, int port,
	219	uint64_t *data);
	220	int bcm_sf2_cfp_get_sset_count(struct dsa_switch *ds, int port, int sset);
7318166c	221
246d7f77	222	#endif /* __BCM_SF2_H */