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net: dsa: bcm_sf2: Fix driver removal
[linux-2.6-block.git] / drivers / net / dsa / bcm_sf2.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
246d7f77
FF		 2/*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
246d7f77
FF		 6 */
7
8#include <linux/list.h>
9#include <linux/module.h>
10#include <linux/netdevice.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
246d7f77
FF		 13#include <linux/phy.h>
14#include <linux/phy_fixed.h>
bc0cb653 15#include <linux/phylink.h>
246d7f77
FF		 16#include <linux/mii.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/of_address.h>
8b7c94e3 20#include <linux/of_net.h>
461cd1b0 21#include <linux/of_mdio.h>
246d7f77 22#include <net/dsa.h>
96e65d7f 23#include <linux/ethtool.h>
12f460f2 24#include <linux/if_bridge.h>
aafc66f1 25#include <linux/brcmphy.h>
680060d3 26#include <linux/etherdevice.h>
f458995b 27#include <linux/platform_data/b53.h>
246d7f77
FF		 28
29#include "bcm_sf2.h"
30#include "bcm_sf2_regs.h"
f458995b
FF		 31#include "b53/b53_priv.h"
32#include "b53/b53_regs.h"
246d7f77 33
ebb2ac4f
FF		 34static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
35{
36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
c837fc81 37 unsigned int i;
ebb2ac4f
FF		 38 u32 reg, offset;
39
ebb2ac4f
FF		 40 /* Enable the port memories */
41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
42 reg &= ~P_TXQ_PSM_VDD(port);
43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
44
ebb2ac4f
FF		 45 /* Enable forwarding */
46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
47
48 /* Enable IMP port in dumb mode */
49 reg = core_readl(priv, CORE_SWITCH_CTRL);
50 reg |= MII_DUMB_FWDG_EN;
51 core_writel(priv, reg, CORE_SWITCH_CTRL);
52
c837fc81
FF		 53 /* Configure Traffic Class to QoS mapping, allow each priority to map
54 * to a different queue number
55 */
56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
58 reg |= i << (PRT_TO_QID_SHIFT * i);
59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
60
b409a9ef 61 b53_brcm_hdr_setup(ds, port);
246d7f77 62
5fc0f212
FF		 63 if (port == 8) {
64 if (priv->type == BCM7445_DEVICE_ID)
65 offset = CORE_STS_OVERRIDE_IMP;
66 else
67 offset = CORE_STS_OVERRIDE_IMP2;
68
69 /* Force link status for IMP port */
70 reg = core_readl(priv, offset);
71 reg |= (MII_SW_OR | LINK_STS);
72 core_writel(priv, reg, offset);
73
74 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
75 reg = core_readl(priv, CORE_IMP_CTL);
76 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
77 reg &= ~(RX_DIS | TX_DIS);
78 core_writel(priv, reg, CORE_IMP_CTL);
79 } else {
80 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
81 reg &= ~(RX_DIS | TX_DIS);
82 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
83 }
246d7f77
FF		 84}
85
b083668c
FF		 86static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
87{
f458995b 88 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
b083668c
FF		 89 u32 reg;
90
b083668c 91 reg = reg_readl(priv, REG_SPHY_CNTRL);
9af197a8
FF		 92 if (enable) {
93 reg |= PHY_RESET;
4b52d010 94 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
9af197a8
FF		 95 reg_writel(priv, reg, REG_SPHY_CNTRL);
96 udelay(21);
97 reg = reg_readl(priv, REG_SPHY_CNTRL);
98 reg &= ~PHY_RESET;
99 } else {
100 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
101 reg_writel(priv, reg, REG_SPHY_CNTRL);
102 mdelay(1);
103 reg |= CK25_DIS;
104 }
b083668c 105 reg_writel(priv, reg, REG_SPHY_CNTRL);
9af197a8
FF		 106
107 /* Use PHY-driven LED signaling */
108 if (!enable) {
109 reg = reg_readl(priv, REG_LED_CNTRL(0));
110 reg |= SPDLNK_SRC_SEL;
111 reg_writel(priv, reg, REG_LED_CNTRL(0));
112 }
b083668c
FF		 113}
114
8b7c94e3
FF		 115static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
116 int port)
117{
118 unsigned int off;
119
120 switch (port) {
121 case 7:
122 off = P7_IRQ_OFF;
123 break;
124 case 0:
125 /* Port 0 interrupts are located on the first bank */
126 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
127 return;
128 default:
129 off = P_IRQ_OFF(port);
130 break;
131 }
132
133 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
134}
135
136static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
137 int port)
138{
139 unsigned int off;
140
141 switch (port) {
142 case 7:
143 off = P7_IRQ_OFF;
144 break;
145 case 0:
146 /* Port 0 interrupts are located on the first bank */
147 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
148 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
149 return;
150 default:
151 off = P_IRQ_OFF(port);
152 break;
153 }
154
155 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
156 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
157}
158
b6d045db
FF		 159static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
160 struct phy_device *phy)
246d7f77 161{
f458995b 162 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
e1b9147c 163 unsigned int i;
246d7f77
FF		 164 u32 reg;
165
74be4bab
VD		 166 if (!dsa_is_user_port(ds, port))
167 return 0;
168
246d7f77
FF		 169 /* Clear the memory power down */
170 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
171 reg &= ~P_TXQ_PSM_VDD(port);
172 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
173
c0e6820b
FF		 174 /* Enable learning */
175 reg = core_readl(priv, CORE_DIS_LEARN);
176 reg &= ~BIT(port);
177 core_writel(priv, reg, CORE_DIS_LEARN);
178
64ff2aef
FF		 179 /* Enable Broadcom tags for that port if requested */
180 if (priv->brcm_tag_mask & BIT(port))
b409a9ef 181 b53_brcm_hdr_setup(ds, port);
64ff2aef 182
e1b9147c
FF		 183 /* Configure Traffic Class to QoS mapping, allow each priority to map
184 * to a different queue number
185 */
186 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
18118377 187 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
e1b9147c
FF		 188 reg |= i << (PRT_TO_QID_SHIFT * i);
189 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
190
9af197a8 191 /* Re-enable the GPHY and re-apply workarounds */
8b7c94e3 192 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
9af197a8
FF		 193 bcm_sf2_gphy_enable_set(ds, true);
194 if (phy) {
195 /* if phy_stop() has been called before, phy
196 * will be in halted state, and phy_start()
197 * will call resume.
198 *
199 * the resume path does not configure back
200 * autoneg settings, and since we hard reset
201 * the phy manually here, we need to reset the
202 * state machine also.
203 */
204 phy->state = PHY_READY;
205 phy_init_hw(phy);
206 }
207 }
208
8b7c94e3
FF		 209 /* Enable MoCA port interrupts to get notified */
210 if (port == priv->moca_port)
211 bcm_sf2_port_intr_enable(priv, port);
246d7f77 212
32e47ff0
FF		 213 /* Set per-queue pause threshold to 32 */
214 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
215
216 /* Set ACB threshold to 24 */
217 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
218 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
219 SF2_NUM_EGRESS_QUEUES + i));
220 reg &= ~XOFF_THRESHOLD_MASK;
221 reg |= 24;
222 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
223 SF2_NUM_EGRESS_QUEUES + i));
224 }
225
f86ad77f 226 return b53_enable_port(ds, port, phy);
246d7f77
FF		 227}
228
75104db0 229static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
246d7f77 230{
f458995b 231 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
5c17a07c 232 u32 reg;
246d7f77 233
c0e6820b
FF		 234 /* Disable learning while in WoL mode */
235 if (priv->wol_ports_mask & (1 << port)) {
236 reg = core_readl(priv, CORE_DIS_LEARN);
237 reg |= BIT(port);
238 core_writel(priv, reg, CORE_DIS_LEARN);
96e65d7f 239 return;
c0e6820b 240 }
96e65d7f 241
8b7c94e3
FF		 242 if (port == priv->moca_port)
243 bcm_sf2_port_intr_disable(priv, port);
b6d045db 244
8b7c94e3 245 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
9af197a8
FF		 246 bcm_sf2_gphy_enable_set(ds, false);
247
75104db0 248 b53_disable_port(ds, port);
246d7f77
FF		 249
250 /* Power down the port memory */
251 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
252 reg |= P_TXQ_PSM_VDD(port);
253 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
254}
255
450b05c1 256
461cd1b0
FF		 257static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
258 int regnum, u16 val)
259{
260 int ret = 0;
261 u32 reg;
262
263 reg = reg_readl(priv, REG_SWITCH_CNTRL);
264 reg |= MDIO_MASTER_SEL;
265 reg_writel(priv, reg, REG_SWITCH_CNTRL);
266
267 /* Page << 8 | offset */
268 reg = 0x70;
269 reg <<= 2;
270 core_writel(priv, addr, reg);
271
272 /* Page << 8 | offset */
273 reg = 0x80 << 8 | regnum << 1;
274 reg <<= 2;
275
276 if (op)
277 ret = core_readl(priv, reg);
278 else
279 core_writel(priv, val, reg);
280
281 reg = reg_readl(priv, REG_SWITCH_CNTRL);
282 reg &= ~MDIO_MASTER_SEL;
283 reg_writel(priv, reg, REG_SWITCH_CNTRL);
284
285 return ret & 0xffff;
286}
287
288static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
289{
290 struct bcm_sf2_priv *priv = bus->priv;
291
292 /* Intercept reads from Broadcom pseudo-PHY address, else, send
293 * them to our master MDIO bus controller
294 */
295 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
296 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
297 else
2cfe8f82 298 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
461cd1b0
FF		 299}
300
301static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
302 u16 val)
303{
304 struct bcm_sf2_priv *priv = bus->priv;
305
306 /* Intercept writes to the Broadcom pseudo-PHY address, else,
307 * send them to our master MDIO bus controller
308 */
309 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
e49505f7 310 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
461cd1b0 311 else
e49505f7
KL		 312 return mdiobus_write_nested(priv->master_mii_bus, addr,
313 regnum, val);
461cd1b0
FF		 314}
315
246d7f77
FF		 316static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
317{
bc0cb653
FF		 318 struct dsa_switch *ds = dev_id;
319 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
246d7f77
FF		 320
321 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
322 ~priv->irq0_mask;
323 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
324
325 return IRQ_HANDLED;
326}
327
328static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
329{
bc0cb653
FF		 330 struct dsa_switch *ds = dev_id;
331 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
246d7f77
FF		 332
333 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
334 ~priv->irq1_mask;
335 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
336
bc0cb653
FF		 337 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
338 priv->port_sts[7].link = true;
339 dsa_port_phylink_mac_change(ds, 7, true);
340 }
341 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
342 priv->port_sts[7].link = false;
343 dsa_port_phylink_mac_change(ds, 7, false);
344 }
246d7f77
FF		 345
346 return IRQ_HANDLED;
347}
348
33f84614
FF		 349static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
350{
351 unsigned int timeout = 1000;
352 u32 reg;
353
354 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
355 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
356 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
357
358 do {
359 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
360 if (!(reg & SOFTWARE_RESET))
361 break;
362
363 usleep_range(1000, 2000);
364 } while (timeout-- > 0);
365
366 if (timeout == 0)
367 return -ETIMEDOUT;
368
369 return 0;
370}
371
691c9a8f
FF		 372static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
373{
f01d5988 374 intrl2_0_mask_set(priv, 0xffffffff);
691c9a8f 375 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
f01d5988 376 intrl2_1_mask_set(priv, 0xffffffff);
691c9a8f 377 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
691c9a8f
FF		 378}
379
8b7c94e3
FF		 380static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
381 struct device_node *dn)
382{
383 struct device_node *port;
8b7c94e3
FF		 384 int mode;
385 unsigned int port_num;
8b7c94e3
FF		 386
387 priv->moca_port = -1;
388
389 for_each_available_child_of_node(dn, port) {
390 if (of_property_read_u32(port, "reg", &port_num))
391 continue;
392
393 /* Internal PHYs get assigned a specific 'phy-mode' property
394 * value: "internal" to help flag them before MDIO probing
395 * has completed, since they might be turned off at that
396 * time
397 */
398 mode = of_get_phy_mode(port);
bedd00c8
FF		 399 if (mode < 0)
400 continue;
401
402 if (mode == PHY_INTERFACE_MODE_INTERNAL)
403 priv->int_phy_mask |= 1 << port_num;
8b7c94e3
FF		 404
405 if (mode == PHY_INTERFACE_MODE_MOCA)
406 priv->moca_port = port_num;
64ff2aef
FF		 407
408 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
409 priv->brcm_tag_mask |= 1 << port_num;
8b7c94e3
FF		 410 }
411}
412
461cd1b0
FF		 413static int bcm_sf2_mdio_register(struct dsa_switch *ds)
414{
f458995b 415 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
461cd1b0
FF		 416 struct device_node *dn;
417 static int index;
418 int err;
419
420 /* Find our integrated MDIO bus node */
421 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
422 priv->master_mii_bus = of_mdio_find_bus(dn);
423 if (!priv->master_mii_bus)
424 return -EPROBE_DEFER;
425
426 get_device(&priv->master_mii_bus->dev);
427 priv->master_mii_dn = dn;
428
429 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
430 if (!priv->slave_mii_bus)
431 return -ENOMEM;
432
433 priv->slave_mii_bus->priv = priv;
434 priv->slave_mii_bus->name = "sf2 slave mii";
435 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
436 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
437 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
438 index++);
439 priv->slave_mii_bus->dev.of_node = dn;
440
441 /* Include the pseudo-PHY address to divert reads towards our
442 * workaround. This is only required for 7445D0, since 7445E0
443 * disconnects the internal switch pseudo-PHY such that we can use the
444 * regular SWITCH_MDIO master controller instead.
445 *
446 * Here we flag the pseudo PHY as needing special treatment and would
447 * otherwise make all other PHY read/writes go to the master MDIO bus
448 * controller that comes with this switch backed by the "mdio-unimac"
449 * driver.
450 */
451 if (of_machine_is_compatible("brcm,bcm7445d0"))
452 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
453 else
454 priv->indir_phy_mask = 0;
455
456 ds->phys_mii_mask = priv->indir_phy_mask;
457 ds->slave_mii_bus = priv->slave_mii_bus;
458 priv->slave_mii_bus->parent = ds->dev->parent;
459 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
460
00e798c7
FF		 461 err = of_mdiobus_register(priv->slave_mii_bus, dn);
462 if (err && dn)
461cd1b0
FF		 463 of_node_put(dn);
464
465 return err;
466}
467
468static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
469{
470 mdiobus_unregister(priv->slave_mii_bus);
1ddc5d3e 471 of_node_put(priv->master_mii_dn);
461cd1b0
FF		 472}
473
aa9aef77
FF		 474static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
475{
f458995b 476 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
aa9aef77
FF		 477
478 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
479 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
480 * the REG_PHY_REVISION register layout is.
481 */
482
483 return priv->hw_params.gphy_rev;
484}
485
bc0cb653
FF		 486static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
487 unsigned long *supported,
488 struct phylink_link_state *state)
489{
738a2e4b 490 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
bc0cb653
FF		 491 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
492
493 if (!phy_interface_mode_is_rgmii(state->interface) &&
494 state->interface != PHY_INTERFACE_MODE_MII &&
495 state->interface != PHY_INTERFACE_MODE_REVMII &&
496 state->interface != PHY_INTERFACE_MODE_GMII &&
497 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
498 state->interface != PHY_INTERFACE_MODE_MOCA) {
499 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
738a2e4b
FF		 500 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
501 dev_err(ds->dev,
502 "Unsupported interface: %d for port %d\n",
503 state->interface, port);
bc0cb653
FF		 504 return;
505 }
506
507 /* Allow all the expected bits */
508 phylink_set(mask, Autoneg);
509 phylink_set_port_modes(mask);
510 phylink_set(mask, Pause);
511 phylink_set(mask, Asym_Pause);
512
513 /* With the exclusion of MII and Reverse MII, we support Gigabit,
514 * including Half duplex
515 */
516 if (state->interface != PHY_INTERFACE_MODE_MII &&
517 state->interface != PHY_INTERFACE_MODE_REVMII) {
518 phylink_set(mask, 1000baseT_Full);
519 phylink_set(mask, 1000baseT_Half);
520 }
521
522 phylink_set(mask, 10baseT_Half);
523 phylink_set(mask, 10baseT_Full);
524 phylink_set(mask, 100baseT_Half);
525 phylink_set(mask, 100baseT_Full);
526
527 bitmap_and(supported, supported, mask,
528 __ETHTOOL_LINK_MODE_MASK_NBITS);
529 bitmap_and(state->advertising, state->advertising, mask,
530 __ETHTOOL_LINK_MODE_MASK_NBITS);
531}
532
533static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
534 unsigned int mode,
535 const struct phylink_link_state *state)
536{
537 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
538 u32 id_mode_dis = 0, port_mode;
539 u32 reg, offset;
540
738a2e4b
FF		 541 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
542 return;
543
bc0cb653
FF		 544 if (priv->type == BCM7445_DEVICE_ID)
545 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
546 else
547 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
548
549 switch (state->interface) {
550 case PHY_INTERFACE_MODE_RGMII:
551 id_mode_dis = 1;
552 /* fallthrough */
553 case PHY_INTERFACE_MODE_RGMII_TXID:
554 port_mode = EXT_GPHY;
555 break;
556 case PHY_INTERFACE_MODE_MII:
557 port_mode = EXT_EPHY;
558 break;
559 case PHY_INTERFACE_MODE_REVMII:
560 port_mode = EXT_REVMII;
561 break;
562 default:
563 /* all other PHYs: internal and MoCA */
564 goto force_link;
565 }
566
567 /* Clear id_mode_dis bit, and the existing port mode, let
568 * RGMII_MODE_EN bet set by mac_link_{up,down}
569 */
570 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
571 reg &= ~ID_MODE_DIS;
572 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
573 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
574
575 reg |= port_mode;
576 if (id_mode_dis)
577 reg |= ID_MODE_DIS;
578
579 if (state->pause & MLO_PAUSE_TXRX_MASK) {
580 if (state->pause & MLO_PAUSE_TX)
581 reg |= TX_PAUSE_EN;
582 reg |= RX_PAUSE_EN;
583 }
584
585 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
586
587force_link:
588 /* Force link settings detected from the PHY */
589 reg = SW_OVERRIDE;
590 switch (state->speed) {
591 case SPEED_1000:
592 reg |= SPDSTS_1000 << SPEED_SHIFT;
593 break;
594 case SPEED_100:
595 reg |= SPDSTS_100 << SPEED_SHIFT;
596 break;
597 }
598
599 if (state->link)
600 reg |= LINK_STS;
601 if (state->duplex == DUPLEX_FULL)
602 reg |= DUPLX_MODE;
603
604 core_writel(priv, reg, offset);
605}
606
607static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
608 phy_interface_t interface, bool link)
609{
610 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
611 u32 reg;
612
613 if (!phy_interface_mode_is_rgmii(interface) &&
614 interface != PHY_INTERFACE_MODE_MII &&
615 interface != PHY_INTERFACE_MODE_REVMII)
616 return;
617
618 /* If the link is down, just disable the interface to conserve power */
619 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
620 if (link)
621 reg |= RGMII_MODE_EN;
622 else
623 reg &= ~RGMII_MODE_EN;
624 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
625}
626
627static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
628 unsigned int mode,
629 phy_interface_t interface)
630{
631 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
632}
633
634static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
635 unsigned int mode,
636 phy_interface_t interface,
637 struct phy_device *phydev)
638{
639 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
640 struct ethtool_eee *p = &priv->dev->ports[port].eee;
641
642 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
643
644 if (mode == MLO_AN_PHY && phydev)
645 p->eee_enabled = b53_eee_init(ds, port, phydev);
646}
647
648static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
649 struct phylink_link_state *status)
650{
651 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
652
653 status->link = false;
654
655 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
656 * which means that we need to force the link at the port override
657 * level to get the data to flow. We do use what the interrupt handler
658 * did determine before.
659 *
660 * For the other ports, we just force the link status, since this is
661 * a fixed PHY device.
662 */
663 if (port == priv->moca_port) {
664 status->link = priv->port_sts[port].link;
665 /* For MoCA interfaces, also force a link down notification
666 * since some version of the user-space daemon (mocad) use
667 * cmd->autoneg to force the link, which messes up the PHY
668 * state machine and make it go in PHY_FORCING state instead.
669 */
670 if (!status->link)
671 netif_carrier_off(ds->ports[port].slave);
672 status->duplex = DUPLEX_FULL;
673 } else {
674 status->link = true;
675 }
676}
677
32e47ff0
FF		 678static void bcm_sf2_enable_acb(struct dsa_switch *ds)
679{
680 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
681 u32 reg;
682
683 /* Enable ACB globally */
684 reg = acb_readl(priv, ACB_CONTROL);
685 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
686 acb_writel(priv, reg, ACB_CONTROL);
687 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
688 reg |= ACB_EN | ACB_ALGORITHM;
689 acb_writel(priv, reg, ACB_CONTROL);
690}
691
8cfa9498
FF		 692static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
693{
f458995b 694 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
8cfa9498
FF		 695 unsigned int port;
696
691c9a8f 697 bcm_sf2_intr_disable(priv);
8cfa9498
FF		 698
699 /* Disable all ports physically present including the IMP
700 * port, the other ones have already been disabled during
701 * bcm_sf2_sw_setup
702 */
8d6ea932 703 for (port = 0; port < ds->num_ports; port++) {
4a5b85ff 704 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
75104db0 705 bcm_sf2_port_disable(ds, port);
8cfa9498
FF		 706 }
707
708 return 0;
709}
710
8cfa9498
FF		 711static int bcm_sf2_sw_resume(struct dsa_switch *ds)
712{
f458995b 713 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
8cfa9498
FF		 714 int ret;
715
716 ret = bcm_sf2_sw_rst(priv);
717 if (ret) {
718 pr_err("%s: failed to software reset switch\n", __func__);
719 return ret;
720 }
721
1c0130f0
FF		 722 ret = bcm_sf2_cfp_resume(ds);
723 if (ret)
724 return ret;
725
b083668c
FF		 726 if (priv->hw_params.num_gphy == 1)
727 bcm_sf2_gphy_enable_set(ds, true);
8cfa9498 728
abd01ba2 729 ds->ops->setup(ds);
32e47ff0 730
8cfa9498
FF		 731 return 0;
732}
733
96e65d7f
FF		 734static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
735 struct ethtool_wolinfo *wol)
736{
f8b8b1cd 737 struct net_device *p = ds->ports[port].cpu_dp->master;
f458995b 738 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
c3152ec4 739 struct ethtool_wolinfo pwol = { };
96e65d7f
FF		 740
741 /* Get the parent device WoL settings */
c3152ec4
FF		 742 if (p->ethtool_ops->get_wol)
743 p->ethtool_ops->get_wol(p, &pwol);
96e65d7f
FF		 744
745 /* Advertise the parent device supported settings */
746 wol->supported = pwol.supported;
747 memset(&wol->sopass, 0, sizeof(wol->sopass));
748
749 if (pwol.wolopts & WAKE_MAGICSECURE)
750 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
751
752 if (priv->wol_ports_mask & (1 << port))
753 wol->wolopts = pwol.wolopts;
754 else
755 wol->wolopts = 0;
756}
757
758static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
759 struct ethtool_wolinfo *wol)
760{
f8b8b1cd 761 struct net_device *p = ds->ports[port].cpu_dp->master;
f458995b 762 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0abfd494 763 s8 cpu_port = ds->ports[port].cpu_dp->index;
c3152ec4 764 struct ethtool_wolinfo pwol = { };
96e65d7f 765
c3152ec4
FF		 766 if (p->ethtool_ops->get_wol)
767 p->ethtool_ops->get_wol(p, &pwol);
96e65d7f
FF		 768 if (wol->wolopts & ~pwol.supported)
769 return -EINVAL;
770
771 if (wol->wolopts)
772 priv->wol_ports_mask |= (1 << port);
773 else
774 priv->wol_ports_mask &= ~(1 << port);
775
776 /* If we have at least one port enabled, make sure the CPU port
777 * is also enabled. If the CPU port is the last one enabled, we disable
778 * it since this configuration does not make sense.
779 */
780 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
781 priv->wol_ports_mask |= (1 << cpu_port);
782 else
783 priv->wol_ports_mask &= ~(1 << cpu_port);
784
785 return p->ethtool_ops->set_wol(p, wol);
786}
787
7fbb1a92
FF		 788static int bcm_sf2_sw_setup(struct dsa_switch *ds)
789{
f458995b 790 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
7fbb1a92 791 unsigned int port;
d9338023 792
21a2774e 793 /* Enable all valid ports and disable those unused */
d9338023 794 for (port = 0; port < priv->hw_params.num_ports; port++) {
21a2774e 795 /* IMP port receives special treatment */
4a5b85ff 796 if (dsa_is_user_port(ds, port))
21a2774e
FF		 797 bcm_sf2_port_setup(ds, port, NULL);
798 else if (dsa_is_cpu_port(ds, port))
d9338023 799 bcm_sf2_imp_setup(ds, port);
21a2774e 800 else
75104db0 801 bcm_sf2_port_disable(ds, port);
d9338023
FF		 802 }
803
5c1a6eaf 804 b53_configure_vlan(ds);
32e47ff0 805 bcm_sf2_enable_acb(ds);
d9338023
FF		 806
807 return 0;
808}
809
f458995b
FF		 810/* The SWITCH_CORE register space is managed by b53 but operates on a page +
811 * register basis so we need to translate that into an address that the
812 * bus-glue understands.
813 */
814#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
815
816static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
817 u8 *val)
818{
819 struct bcm_sf2_priv *priv = dev->priv;
820
821 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
822
823 return 0;
824}
825
826static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
827 u16 *val)
828{
829 struct bcm_sf2_priv *priv = dev->priv;
830
831 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
832
833 return 0;
834}
835
836static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
837 u32 *val)
838{
839 struct bcm_sf2_priv *priv = dev->priv;
840
841 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
842
843 return 0;
844}
845
846static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
847 u64 *val)
848{
849 struct bcm_sf2_priv *priv = dev->priv;
850
851 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
852
853 return 0;
854}
855
856static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
857 u8 value)
858{
859 struct bcm_sf2_priv *priv = dev->priv;
860
861 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
862
863 return 0;
864}
865
866static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
867 u16 value)
868{
869 struct bcm_sf2_priv *priv = dev->priv;
870
871 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
872
873 return 0;
874}
875
876static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
877 u32 value)
878{
879 struct bcm_sf2_priv *priv = dev->priv;
880
881 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
882
883 return 0;
884}
885
886static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
887 u64 value)
888{
889 struct bcm_sf2_priv *priv = dev->priv;
890
891 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
892
893 return 0;
894}
895
7e3108fa 896static const struct b53_io_ops bcm_sf2_io_ops = {
f458995b
FF		 897 .read8 = bcm_sf2_core_read8,
898 .read16 = bcm_sf2_core_read16,
899 .read32 = bcm_sf2_core_read32,
900 .read48 = bcm_sf2_core_read64,
901 .read64 = bcm_sf2_core_read64,
902 .write8 = bcm_sf2_core_write8,
903 .write16 = bcm_sf2_core_write16,
904 .write32 = bcm_sf2_core_write32,
905 .write48 = bcm_sf2_core_write64,
906 .write64 = bcm_sf2_core_write64,
907};
908
badd62c2
FF		 909static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
910 u32 stringset, uint8_t *data)
911{
f4ae9c08
FF		 912 int cnt = b53_get_sset_count(ds, port, stringset);
913
badd62c2 914 b53_get_strings(ds, port, stringset, data);
f4ae9c08
FF		 915 bcm_sf2_cfp_get_strings(ds, port, stringset,
916 data + cnt * ETH_GSTRING_LEN);
badd62c2
FF		 917}
918
919static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
920 uint64_t *data)
921{
f4ae9c08
FF		 922 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
923
badd62c2 924 b53_get_ethtool_stats(ds, port, data);
f4ae9c08 925 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
badd62c2
FF		 926}
927
928static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
929 int sset)
930{
f4ae9c08
FF		 931 int cnt = b53_get_sset_count(ds, port, sset);
932
933 if (cnt < 0)
934 return cnt;
935
936 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
937
938 return cnt;
badd62c2
FF		 939}
940
a82f67af 941static const struct dsa_switch_ops bcm_sf2_ops = {
9f66816a 942 .get_tag_protocol = b53_get_tag_protocol,
73095cb1 943 .setup = bcm_sf2_sw_setup,
badd62c2
FF		 944 .get_strings = bcm_sf2_sw_get_strings,
945 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
946 .get_sset_count = bcm_sf2_sw_get_sset_count,
c7d28c9d 947 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
73095cb1 948 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
bc0cb653
FF		 949 .phylink_validate = bcm_sf2_sw_validate,
950 .phylink_mac_config = bcm_sf2_sw_mac_config,
951 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
952 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
953 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
73095cb1
FF		 954 .suspend = bcm_sf2_sw_suspend,
955 .resume = bcm_sf2_sw_resume,
956 .get_wol = bcm_sf2_sw_get_wol,
957 .set_wol = bcm_sf2_sw_set_wol,
958 .port_enable = bcm_sf2_port_setup,
959 .port_disable = bcm_sf2_port_disable,
22256b0a
FF		 960 .get_mac_eee = b53_get_mac_eee,
961 .set_mac_eee = b53_set_mac_eee,
73095cb1
FF		 962 .port_bridge_join = b53_br_join,
963 .port_bridge_leave = b53_br_leave,
964 .port_stp_state_set = b53_br_set_stp_state,
965 .port_fast_age = b53_br_fast_age,
966 .port_vlan_filtering = b53_vlan_filtering,
967 .port_vlan_prepare = b53_vlan_prepare,
968 .port_vlan_add = b53_vlan_add,
969 .port_vlan_del = b53_vlan_del,
73095cb1
FF		 970 .port_fdb_dump = b53_fdb_dump,
971 .port_fdb_add = b53_fdb_add,
972 .port_fdb_del = b53_fdb_del,
7318166c
FF		 973 .get_rxnfc = bcm_sf2_get_rxnfc,
974 .set_rxnfc = bcm_sf2_set_rxnfc,
ec960de6
FF		 975 .port_mirror_add = b53_mirror_add,
976 .port_mirror_del = b53_mirror_del,
73095cb1
FF		 977};
978
a78e86ed
FF		 979struct bcm_sf2_of_data {
980 u32 type;
981 const u16 *reg_offsets;
982 unsigned int core_reg_align;
df191632 983 unsigned int num_cfp_rules;
a78e86ed
FF		 984};
985
986/* Register offsets for the SWITCH_REG_* block */
987static const u16 bcm_sf2_7445_reg_offsets[] = {
988 [REG_SWITCH_CNTRL] = 0x00,
989 [REG_SWITCH_STATUS] = 0x04,
990 [REG_DIR_DATA_WRITE] = 0x08,
991 [REG_DIR_DATA_READ] = 0x0C,
992 [REG_SWITCH_REVISION] = 0x18,
993 [REG_PHY_REVISION] = 0x1C,
994 [REG_SPHY_CNTRL] = 0x2C,
995 [REG_RGMII_0_CNTRL] = 0x34,
996 [REG_RGMII_1_CNTRL] = 0x40,
997 [REG_RGMII_2_CNTRL] = 0x4c,
998 [REG_LED_0_CNTRL] = 0x90,
999 [REG_LED_1_CNTRL] = 0x94,
1000 [REG_LED_2_CNTRL] = 0x98,
1001};
1002
1003static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1004 .type = BCM7445_DEVICE_ID,
1005 .core_reg_align = 0,
1006 .reg_offsets = bcm_sf2_7445_reg_offsets,
df191632 1007 .num_cfp_rules = 256,
a78e86ed
FF		 1008};
1009
0fe99338
FF		 1010static const u16 bcm_sf2_7278_reg_offsets[] = {
1011 [REG_SWITCH_CNTRL] = 0x00,
1012 [REG_SWITCH_STATUS] = 0x04,
1013 [REG_DIR_DATA_WRITE] = 0x08,
1014 [REG_DIR_DATA_READ] = 0x0c,
1015 [REG_SWITCH_REVISION] = 0x10,
1016 [REG_PHY_REVISION] = 0x14,
1017 [REG_SPHY_CNTRL] = 0x24,
1018 [REG_RGMII_0_CNTRL] = 0xe0,
1019 [REG_RGMII_1_CNTRL] = 0xec,
1020 [REG_RGMII_2_CNTRL] = 0xf8,
1021 [REG_LED_0_CNTRL] = 0x40,
1022 [REG_LED_1_CNTRL] = 0x4c,
1023 [REG_LED_2_CNTRL] = 0x58,
1024};
1025
1026static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1027 .type = BCM7278_DEVICE_ID,
1028 .core_reg_align = 1,
1029 .reg_offsets = bcm_sf2_7278_reg_offsets,
df191632 1030 .num_cfp_rules = 128,
0fe99338
FF		 1031};
1032
a78e86ed
FF		 1033static const struct of_device_id bcm_sf2_of_match[] = {
1034 { .compatible = "brcm,bcm7445-switch-v4.0",
1035 .data = &bcm_sf2_7445_data
1036 },
0fe99338
FF		 1037 { .compatible = "brcm,bcm7278-switch-v4.0",
1038 .data = &bcm_sf2_7278_data
3b07d788
FF		 1039 },
1040 { .compatible = "brcm,bcm7278-switch-v4.8",
1041 .data = &bcm_sf2_7278_data
0fe99338 1042 },
a78e86ed
FF		 1043 { /* sentinel */ },
1044};
1045MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1046
d9338023
FF		 1047static int bcm_sf2_sw_probe(struct platform_device *pdev)
1048{
1049 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1050 struct device_node *dn = pdev->dev.of_node;
a78e86ed
FF		 1051 const struct of_device_id *of_id = NULL;
1052 const struct bcm_sf2_of_data *data;
f458995b 1053 struct b53_platform_data *pdata;
a4c61b92 1054 struct dsa_switch_ops *ops;
d9338023 1055 struct bcm_sf2_priv *priv;
f458995b 1056 struct b53_device *dev;
d9338023
FF		 1057 struct dsa_switch *ds;
1058 void __iomem **base;
7fbb1a92
FF		 1059 unsigned int i;
1060 u32 reg, rev;
1061 int ret;
1062
f458995b
FF		 1063 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1064 if (!priv)
1065 return -ENOMEM;
1066
a4c61b92
FF		 1067 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1068 if (!ops)
1069 return -ENOMEM;
1070
f458995b
FF		 1071 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1072 if (!dev)
d9338023
FF		 1073 return -ENOMEM;
1074
f458995b
FF		 1075 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1076 if (!pdata)
1077 return -ENOMEM;
1078
a78e86ed
FF		 1079 of_id = of_match_node(bcm_sf2_of_match, dn);
1080 if (!of_id || !of_id->data)
1081 return -EINVAL;
1082
1083 data = of_id->data;
1084
1085 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1086 priv->type = data->type;
1087 priv->reg_offsets = data->reg_offsets;
1088 priv->core_reg_align = data->core_reg_align;
df191632 1089 priv->num_cfp_rules = data->num_cfp_rules;
a78e86ed 1090
f458995b
FF		 1091 /* Auto-detection using standard registers will not work, so
1092 * provide an indication of what kind of device we are for
1093 * b53_common to work with
1094 */
a78e86ed 1095 pdata->chip_id = priv->type;
f458995b
FF		 1096 dev->pdata = pdata;
1097
1098 priv->dev = dev;
1099 ds = dev->ds;
73095cb1 1100 ds->ops = &bcm_sf2_ops;
d9338023 1101
18118377
FF		 1102 /* Advertise the 8 egress queues */
1103 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1104
f458995b 1105 dev_set_drvdata(&pdev->dev, priv);
d9338023 1106
7fbb1a92 1107 spin_lock_init(&priv->indir_lock);
7318166c 1108 mutex_init(&priv->cfp.lock);
ae7a5aff 1109 INIT_LIST_HEAD(&priv->cfp.rules_list);
7318166c
FF		 1110
1111 /* CFP rule #0 cannot be used for specific classifications, flag it as
1112 * permanently used
1113 */
1114 set_bit(0, priv->cfp.used);
ba0696c2 1115 set_bit(0, priv->cfp.unique);
7fbb1a92 1116
d9338023 1117 bcm_sf2_identify_ports(priv, dn->child);
7fbb1a92
FF		 1118
1119 priv->irq0 = irq_of_parse_and_map(dn, 0);
1120 priv->irq1 = irq_of_parse_and_map(dn, 1);
1121
1122 base = &priv->core;
1123 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
42376788 1124 *base = devm_platform_ioremap_resource(pdev, i);
4bd11675 1125 if (IS_ERR(*base)) {
7fbb1a92 1126 pr_err("unable to find register: %s\n", reg_names[i]);
4bd11675 1127 return PTR_ERR(*base);
7fbb1a92
FF		 1128 }
1129 base++;
1130 }
1131
1132 ret = bcm_sf2_sw_rst(priv);
1133 if (ret) {
1134 pr_err("unable to software reset switch: %d\n", ret);
4bd11675 1135 return ret;
7fbb1a92
FF		 1136 }
1137
c04a17d2
FF		 1138 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1139
7fbb1a92
FF		 1140 ret = bcm_sf2_mdio_register(ds);
1141 if (ret) {
1142 pr_err("failed to register MDIO bus\n");
4bd11675 1143 return ret;
7fbb1a92
FF		 1144 }
1145
c04a17d2
FF		 1146 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1147
7318166c
FF		 1148 ret = bcm_sf2_cfp_rst(priv);
1149 if (ret) {
1150 pr_err("failed to reset CFP\n");
1151 goto out_mdio;
1152 }
1153
7fbb1a92
FF		 1154 /* Disable all interrupts and request them */
1155 bcm_sf2_intr_disable(priv);
1156
4bd11675 1157 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
bc0cb653 1158 "switch_0", ds);
7fbb1a92
FF		 1159 if (ret < 0) {
1160 pr_err("failed to request switch_0 IRQ\n");
bb9c0fa3 1161 goto out_mdio;
7fbb1a92
FF		 1162 }
1163
4bd11675 1164 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
bc0cb653 1165 "switch_1", ds);
7fbb1a92
FF		 1166 if (ret < 0) {
1167 pr_err("failed to request switch_1 IRQ\n");
4bd11675 1168 goto out_mdio;
7fbb1a92
FF		 1169 }
1170
1171 /* Reset the MIB counters */
1172 reg = core_readl(priv, CORE_GMNCFGCFG);
1173 reg |= RST_MIB_CNT;
1174 core_writel(priv, reg, CORE_GMNCFGCFG);
1175 reg &= ~RST_MIB_CNT;
1176 core_writel(priv, reg, CORE_GMNCFGCFG);
1177
1178 /* Get the maximum number of ports for this switch */
1179 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1180 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1181 priv->hw_params.num_ports = DSA_MAX_PORTS;
1182
1183 /* Assume a single GPHY setup if we can't read that property */
1184 if (of_property_read_u32(dn, "brcm,num-gphy",
1185 &priv->hw_params.num_gphy))
1186 priv->hw_params.num_gphy = 1;
1187
7fbb1a92
FF		 1188 rev = reg_readl(priv, REG_SWITCH_REVISION);
1189 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1190 SWITCH_TOP_REV_MASK;
1191 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1192
1193 rev = reg_readl(priv, REG_PHY_REVISION);
1194 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1195
f458995b 1196 ret = b53_switch_register(dev);
d9338023 1197 if (ret)
4bd11675 1198 goto out_mdio;
d9338023 1199
fbb7bc45
FF		 1200 dev_info(&pdev->dev,
1201 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1202 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1203 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1204 priv->irq0, priv->irq1);
7fbb1a92
FF		 1205
1206 return 0;
1207
bb9c0fa3
FF		 1208out_mdio:
1209 bcm_sf2_mdio_unregister(priv);
7fbb1a92
FF		 1210 return ret;
1211}
1212
d9338023 1213static int bcm_sf2_sw_remove(struct platform_device *pdev)
246d7f77 1214{
f458995b 1215 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
d9338023 1216
d9338023 1217 priv->wol_ports_mask = 0;
e684000b
FF		 1218 /* Disable interrupts */
1219 bcm_sf2_intr_disable(priv);
f458995b 1220 dsa_unregister_switch(priv->dev->ds);
ae7a5aff 1221 bcm_sf2_cfp_exit(priv->dev->ds);
d9338023 1222 bcm_sf2_mdio_unregister(priv);
246d7f77
FF		 1223
1224 return 0;
1225}
246d7f77 1226
2399d614
FF		 1227static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1228{
1229 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1230
1231 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1232 * successful MDIO bus scan to occur. If we did turn off the GPHY
1233 * before (e.g: port_disable), this will also power it back on.
4a2947e3
FF		 1234 *
1235 * Do not rely on kexec_in_progress, just power the PHY on.
2399d614
FF		 1236 */
1237 if (priv->hw_params.num_gphy == 1)
4a2947e3 1238 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
2399d614
FF		 1239}
1240
d9338023
FF		 1241#ifdef CONFIG_PM_SLEEP
1242static int bcm_sf2_suspend(struct device *dev)
246d7f77 1243{
63382e0a 1244 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
d9338023 1245
f458995b 1246 return dsa_switch_suspend(priv->dev->ds);
246d7f77 1247}
d9338023
FF		 1248
1249static int bcm_sf2_resume(struct device *dev)
1250{
63382e0a 1251 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
d9338023 1252
f458995b 1253 return dsa_switch_resume(priv->dev->ds);
d9338023
FF		 1254}
1255#endif /* CONFIG_PM_SLEEP */
1256
1257static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1258 bcm_sf2_suspend, bcm_sf2_resume);
1259
d9338023
FF		 1260
1261static struct platform_driver bcm_sf2_driver = {
1262 .probe = bcm_sf2_sw_probe,
1263 .remove = bcm_sf2_sw_remove,
2399d614 1264 .shutdown = bcm_sf2_sw_shutdown,
d9338023
FF		 1265 .driver = {
1266 .name = "brcm-sf2",
1267 .of_match_table = bcm_sf2_of_match,
1268 .pm = &bcm_sf2_pm_ops,
1269 },
1270};
1271module_platform_driver(bcm_sf2_driver);
246d7f77
FF		 1272
1273MODULE_AUTHOR("Broadcom Corporation");
1274MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1275MODULE_LICENSE("GPL");
1276MODULE_ALIAS("platform:brcm-sf2");
Linux 6.x block layer and io_uring tree(s)