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Merge tag 'devprop-5.12-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[linux-2.6-block.git] / drivers / net / dsa / bcm_sf2.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
246d7f77
FF		 2/*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
246d7f77
FF		 6 */
7
8#include <linux/list.h>
9#include <linux/module.h>
10#include <linux/netdevice.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
246d7f77
FF		 13#include <linux/phy.h>
14#include <linux/phy_fixed.h>
bc0cb653 15#include <linux/phylink.h>
246d7f77 16#include <linux/mii.h>
e9ec5c3b 17#include <linux/clk.h>
246d7f77
FF		 18#include <linux/of.h>
19#include <linux/of_irq.h>
20#include <linux/of_address.h>
8b7c94e3 21#include <linux/of_net.h>
461cd1b0 22#include <linux/of_mdio.h>
246d7f77 23#include <net/dsa.h>
96e65d7f 24#include <linux/ethtool.h>
12f460f2 25#include <linux/if_bridge.h>
aafc66f1 26#include <linux/brcmphy.h>
680060d3 27#include <linux/etherdevice.h>
f458995b 28#include <linux/platform_data/b53.h>
246d7f77
FF		 29
30#include "bcm_sf2.h"
31#include "bcm_sf2_regs.h"
f458995b
FF		 32#include "b53/b53_priv.h"
33#include "b53/b53_regs.h"
246d7f77 34
2ee3adc4
FF		 35/* Return the number of active ports, not counting the IMP (CPU) port */
36static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
37{
38 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
39 unsigned int port, count = 0;
40
41 for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) {
42 if (dsa_is_cpu_port(ds, port))
43 continue;
44 if (priv->port_sts[port].enabled)
45 count++;
46 }
47
48 return count;
49}
50
51static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
52{
53 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
54 unsigned long new_rate;
55 unsigned int ports_active;
56 /* Frequenty in Mhz */
d978d6d0 57 static const unsigned long rate_table[] = {
2ee3adc4
FF		 58 59220000,
59 60820000,
60 62500000,
61 62500000,
62 };
63
64 ports_active = bcm_sf2_num_active_ports(ds);
65 if (ports_active == 0 || !priv->clk_mdiv)
66 return;
67
68 /* If we overflow our table, just use the recommended operational
69 * frequency
70 */
71 if (ports_active > ARRAY_SIZE(rate_table))
72 new_rate = 90000000;
73 else
74 new_rate = rate_table[ports_active - 1];
75 clk_set_rate(priv->clk_mdiv, new_rate);
76}
77
ebb2ac4f
FF		 78static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
79{
80 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
c837fc81 81 unsigned int i;
ebb2ac4f
FF		 82 u32 reg, offset;
83
ebb2ac4f
FF		 84 /* Enable the port memories */
85 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
86 reg &= ~P_TXQ_PSM_VDD(port);
87 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
88
ebb2ac4f
FF		 89 /* Enable forwarding */
90 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
91
92 /* Enable IMP port in dumb mode */
93 reg = core_readl(priv, CORE_SWITCH_CTRL);
94 reg |= MII_DUMB_FWDG_EN;
95 core_writel(priv, reg, CORE_SWITCH_CTRL);
96
c837fc81
FF		 97 /* Configure Traffic Class to QoS mapping, allow each priority to map
98 * to a different queue number
99 */
100 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
101 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
102 reg |= i << (PRT_TO_QID_SHIFT * i);
103 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
104
b409a9ef 105 b53_brcm_hdr_setup(ds, port);
246d7f77 106
5fc0f212 107 if (port == 8) {
73b7a604
RM		 108 if (priv->type == BCM4908_DEVICE_ID ||
109 priv->type == BCM7445_DEVICE_ID)
5fc0f212
FF		 110 offset = CORE_STS_OVERRIDE_IMP;
111 else
112 offset = CORE_STS_OVERRIDE_IMP2;
113
114 /* Force link status for IMP port */
115 reg = core_readl(priv, offset);
de34d708 116 reg |= (MII_SW_OR | LINK_STS);
98c5f7d4 117 reg &= ~GMII_SPEED_UP_2G;
5fc0f212
FF		 118 core_writel(priv, reg, offset);
119
120 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
121 reg = core_readl(priv, CORE_IMP_CTL);
122 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
123 reg &= ~(RX_DIS | TX_DIS);
124 core_writel(priv, reg, CORE_IMP_CTL);
125 } else {
126 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
127 reg &= ~(RX_DIS | TX_DIS);
128 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
129 }
2ee3adc4
FF		 130
131 priv->port_sts[port].enabled = true;
246d7f77
FF		 132}
133
b083668c
FF		 134static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
135{
f458995b 136 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
b083668c
FF		 137 u32 reg;
138
b083668c 139 reg = reg_readl(priv, REG_SPHY_CNTRL);
9af197a8
FF		 140 if (enable) {
141 reg |= PHY_RESET;
4b52d010 142 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
9af197a8
FF		 143 reg_writel(priv, reg, REG_SPHY_CNTRL);
144 udelay(21);
145 reg = reg_readl(priv, REG_SPHY_CNTRL);
146 reg &= ~PHY_RESET;
147 } else {
148 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
149 reg_writel(priv, reg, REG_SPHY_CNTRL);
150 mdelay(1);
151 reg |= CK25_DIS;
152 }
b083668c 153 reg_writel(priv, reg, REG_SPHY_CNTRL);
9af197a8
FF		 154
155 /* Use PHY-driven LED signaling */
156 if (!enable) {
157 reg = reg_readl(priv, REG_LED_CNTRL(0));
158 reg |= SPDLNK_SRC_SEL;
159 reg_writel(priv, reg, REG_LED_CNTRL(0));
160 }
b083668c
FF		 161}
162
8b7c94e3
FF		 163static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
164 int port)
165{
166 unsigned int off;
167
168 switch (port) {
169 case 7:
170 off = P7_IRQ_OFF;
171 break;
172 case 0:
173 /* Port 0 interrupts are located on the first bank */
174 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
175 return;
176 default:
177 off = P_IRQ_OFF(port);
178 break;
179 }
180
181 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
182}
183
184static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
185 int port)
186{
187 unsigned int off;
188
189 switch (port) {
190 case 7:
191 off = P7_IRQ_OFF;
192 break;
193 case 0:
194 /* Port 0 interrupts are located on the first bank */
195 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
196 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
197 return;
198 default:
199 off = P_IRQ_OFF(port);
200 break;
201 }
202
203 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
204 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
205}
206
b6d045db
FF		 207static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
208 struct phy_device *phy)
246d7f77 209{
f458995b 210 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
e1b9147c 211 unsigned int i;
246d7f77
FF		 212 u32 reg;
213
74be4bab
VD		 214 if (!dsa_is_user_port(ds, port))
215 return 0;
216
2ee3adc4
FF		 217 priv->port_sts[port].enabled = true;
218
219 bcm_sf2_recalc_clock(ds);
220
246d7f77
FF		 221 /* Clear the memory power down */
222 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
223 reg &= ~P_TXQ_PSM_VDD(port);
224 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
225
64ff2aef 226 /* Enable Broadcom tags for that port if requested */
f9b3827e 227 if (priv->brcm_tag_mask & BIT(port))
b409a9ef 228 b53_brcm_hdr_setup(ds, port);
64ff2aef 229
e1b9147c
FF		 230 /* Configure Traffic Class to QoS mapping, allow each priority to map
231 * to a different queue number
232 */
233 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
18118377 234 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
e1b9147c
FF		 235 reg |= i << (PRT_TO_QID_SHIFT * i);
236 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
237
9af197a8 238 /* Re-enable the GPHY and re-apply workarounds */
8b7c94e3 239 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
9af197a8
FF		 240 bcm_sf2_gphy_enable_set(ds, true);
241 if (phy) {
242 /* if phy_stop() has been called before, phy
243 * will be in halted state, and phy_start()
244 * will call resume.
245 *
246 * the resume path does not configure back
247 * autoneg settings, and since we hard reset
248 * the phy manually here, we need to reset the
249 * state machine also.
250 */
251 phy->state = PHY_READY;
252 phy_init_hw(phy);
253 }
254 }
255
8b7c94e3
FF		 256 /* Enable MoCA port interrupts to get notified */
257 if (port == priv->moca_port)
258 bcm_sf2_port_intr_enable(priv, port);
246d7f77 259
32e47ff0
FF		 260 /* Set per-queue pause threshold to 32 */
261 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
262
263 /* Set ACB threshold to 24 */
264 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
265 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
266 SF2_NUM_EGRESS_QUEUES + i));
267 reg &= ~XOFF_THRESHOLD_MASK;
268 reg |= 24;
269 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
270 SF2_NUM_EGRESS_QUEUES + i));
271 }
272
f86ad77f 273 return b53_enable_port(ds, port, phy);
246d7f77
FF		 274}
275
75104db0 276static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
246d7f77 277{
f458995b 278 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
5c17a07c 279 u32 reg;
246d7f77 280
c0e6820b
FF		 281 /* Disable learning while in WoL mode */
282 if (priv->wol_ports_mask & (1 << port)) {
283 reg = core_readl(priv, CORE_DIS_LEARN);
284 reg |= BIT(port);
285 core_writel(priv, reg, CORE_DIS_LEARN);
96e65d7f 286 return;
c0e6820b 287 }
96e65d7f 288
8b7c94e3
FF		 289 if (port == priv->moca_port)
290 bcm_sf2_port_intr_disable(priv, port);
b6d045db 291
8b7c94e3 292 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
9af197a8
FF		 293 bcm_sf2_gphy_enable_set(ds, false);
294
75104db0 295 b53_disable_port(ds, port);
246d7f77
FF		 296
297 /* Power down the port memory */
298 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
299 reg |= P_TXQ_PSM_VDD(port);
300 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
2ee3adc4
FF		 301
302 priv->port_sts[port].enabled = false;
303
304 bcm_sf2_recalc_clock(ds);
246d7f77
FF		 305}
306
450b05c1 307
461cd1b0
FF		 308static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
309 int regnum, u16 val)
310{
311 int ret = 0;
312 u32 reg;
313
314 reg = reg_readl(priv, REG_SWITCH_CNTRL);
315 reg |= MDIO_MASTER_SEL;
316 reg_writel(priv, reg, REG_SWITCH_CNTRL);
317
318 /* Page << 8 | offset */
319 reg = 0x70;
320 reg <<= 2;
321 core_writel(priv, addr, reg);
322
323 /* Page << 8 | offset */
324 reg = 0x80 << 8 | regnum << 1;
325 reg <<= 2;
326
327 if (op)
328 ret = core_readl(priv, reg);
329 else
330 core_writel(priv, val, reg);
331
332 reg = reg_readl(priv, REG_SWITCH_CNTRL);
333 reg &= ~MDIO_MASTER_SEL;
334 reg_writel(priv, reg, REG_SWITCH_CNTRL);
335
336 return ret & 0xffff;
337}
338
339static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
340{
341 struct bcm_sf2_priv *priv = bus->priv;
342
343 /* Intercept reads from Broadcom pseudo-PHY address, else, send
344 * them to our master MDIO bus controller
345 */
346 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
347 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
348 else
2cfe8f82 349 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
461cd1b0
FF		 350}
351
352static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
353 u16 val)
354{
355 struct bcm_sf2_priv *priv = bus->priv;
356
357 /* Intercept writes to the Broadcom pseudo-PHY address, else,
358 * send them to our master MDIO bus controller
359 */
360 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
e49505f7 361 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
461cd1b0 362 else
e49505f7
KL		 363 return mdiobus_write_nested(priv->master_mii_bus, addr,
364 regnum, val);
461cd1b0
FF		 365}
366
246d7f77
FF		 367static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
368{
bc0cb653
FF		 369 struct dsa_switch *ds = dev_id;
370 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
246d7f77
FF		 371
372 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
373 ~priv->irq0_mask;
374 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
375
376 return IRQ_HANDLED;
377}
378
379static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
380{
bc0cb653
FF		 381 struct dsa_switch *ds = dev_id;
382 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
246d7f77
FF		 383
384 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
385 ~priv->irq1_mask;
386 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
387
bc0cb653
FF		 388 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
389 priv->port_sts[7].link = true;
390 dsa_port_phylink_mac_change(ds, 7, true);
391 }
392 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
393 priv->port_sts[7].link = false;
394 dsa_port_phylink_mac_change(ds, 7, false);
395 }
246d7f77
FF		 396
397 return IRQ_HANDLED;
398}
399
33f84614
FF		 400static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
401{
402 unsigned int timeout = 1000;
403 u32 reg;
eee87e43
FF		 404 int ret;
405
406 /* The watchdog reset does not work on 7278, we need to hit the
407 * "external" reset line through the reset controller.
408 */
bf9279cd 409 if (priv->type == BCM7278_DEVICE_ID) {
eee87e43
FF		 410 ret = reset_control_assert(priv->rcdev);
411 if (ret)
412 return ret;
413
414 return reset_control_deassert(priv->rcdev);
415 }
33f84614
FF		 416
417 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
418 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
419 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
420
421 do {
422 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
423 if (!(reg & SOFTWARE_RESET))
424 break;
425
426 usleep_range(1000, 2000);
427 } while (timeout-- > 0);
428
429 if (timeout == 0)
430 return -ETIMEDOUT;
431
432 return 0;
433}
434
691c9a8f
FF		 435static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
436{
f01d5988 437 intrl2_0_mask_set(priv, 0xffffffff);
691c9a8f 438 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
f01d5988 439 intrl2_1_mask_set(priv, 0xffffffff);
691c9a8f 440 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
691c9a8f
FF		 441}
442
8b7c94e3
FF		 443static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
444 struct device_node *dn)
445{
446 struct device_node *port;
8b7c94e3 447 unsigned int port_num;
8c280440 448 struct property *prop;
0c65b2b9
AL		 449 phy_interface_t mode;
450 int err;
8b7c94e3
FF		 451
452 priv->moca_port = -1;
453
454 for_each_available_child_of_node(dn, port) {
455 if (of_property_read_u32(port, "reg", &port_num))
456 continue;
457
458 /* Internal PHYs get assigned a specific 'phy-mode' property
459 * value: "internal" to help flag them before MDIO probing
460 * has completed, since they might be turned off at that
461 * time
462 */
0c65b2b9
AL		 463 err = of_get_phy_mode(port, &mode);
464 if (err)
bedd00c8
FF		 465 continue;
466
467 if (mode == PHY_INTERFACE_MODE_INTERNAL)
468 priv->int_phy_mask |= 1 << port_num;
8b7c94e3
FF		 469
470 if (mode == PHY_INTERFACE_MODE_MOCA)
471 priv->moca_port = port_num;
64ff2aef
FF		 472
473 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
474 priv->brcm_tag_mask |= 1 << port_num;
8c280440
FF		 475
476 /* Ensure that port 5 is not picked up as a DSA CPU port
477 * flavour but a regular port instead. We should be using
478 * devlink to be able to set the port flavour.
479 */
480 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
481 prop = of_find_property(port, "ethernet", NULL);
482 if (prop)
483 of_remove_property(port, prop);
484 }
8b7c94e3
FF		 485 }
486}
487
461cd1b0
FF		 488static int bcm_sf2_mdio_register(struct dsa_switch *ds)
489{
f458995b 490 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
771089c2
FF		 491 struct device_node *dn, *child;
492 struct phy_device *phydev;
493 struct property *prop;
461cd1b0 494 static int index;
771089c2 495 int err, reg;
461cd1b0
FF		 496
497 /* Find our integrated MDIO bus node */
498 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
499 priv->master_mii_bus = of_mdio_find_bus(dn);
cf3c4663
PB		 500 if (!priv->master_mii_bus) {
501 of_node_put(dn);
461cd1b0 502 return -EPROBE_DEFER;
cf3c4663 503 }
461cd1b0
FF		 504
505 get_device(&priv->master_mii_bus->dev);
506 priv->master_mii_dn = dn;
507
508 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
cf3c4663
PB		 509 if (!priv->slave_mii_bus) {
510 of_node_put(dn);
461cd1b0 511 return -ENOMEM;
cf3c4663 512 }
461cd1b0
FF		 513
514 priv->slave_mii_bus->priv = priv;
515 priv->slave_mii_bus->name = "sf2 slave mii";
516 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
517 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
518 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
519 index++);
520 priv->slave_mii_bus->dev.of_node = dn;
521
522 /* Include the pseudo-PHY address to divert reads towards our
523 * workaround. This is only required for 7445D0, since 7445E0
524 * disconnects the internal switch pseudo-PHY such that we can use the
525 * regular SWITCH_MDIO master controller instead.
526 *
527 * Here we flag the pseudo PHY as needing special treatment and would
528 * otherwise make all other PHY read/writes go to the master MDIO bus
529 * controller that comes with this switch backed by the "mdio-unimac"
530 * driver.
531 */
532 if (of_machine_is_compatible("brcm,bcm7445d0"))
0fa45ee3 533 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
461cd1b0
FF		 534 else
535 priv->indir_phy_mask = 0;
536
537 ds->phys_mii_mask = priv->indir_phy_mask;
538 ds->slave_mii_bus = priv->slave_mii_bus;
539 priv->slave_mii_bus->parent = ds->dev->parent;
540 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
541
771089c2
FF		 542 /* We need to make sure that of_phy_connect() will not work by
543 * removing the 'phandle' and 'linux,phandle' properties and
544 * unregister the existing PHY device that was already registered.
545 */
546 for_each_available_child_of_node(dn, child) {
547 if (of_property_read_u32(child, "reg", &reg) ||
548 reg >= PHY_MAX_ADDR)
549 continue;
550
551 if (!(priv->indir_phy_mask & BIT(reg)))
552 continue;
553
554 prop = of_find_property(child, "phandle", NULL);
555 if (prop)
556 of_remove_property(child, prop);
557
558 prop = of_find_property(child, "linux,phandle", NULL);
559 if (prop)
560 of_remove_property(child, prop);
561
562 phydev = of_phy_find_device(child);
563 if (phydev)
564 phy_device_remove(phydev);
565 }
566
536fab5b 567 err = mdiobus_register(priv->slave_mii_bus);
00e798c7 568 if (err && dn)
461cd1b0
FF		 569 of_node_put(dn);
570
571 return err;
572}
573
574static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
575{
576 mdiobus_unregister(priv->slave_mii_bus);
1ddc5d3e 577 of_node_put(priv->master_mii_dn);
461cd1b0
FF		 578}
579
aa9aef77
FF		 580static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
581{
f458995b 582 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
aa9aef77
FF		 583
584 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
585 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
586 * the REG_PHY_REVISION register layout is.
587 */
588
589 return priv->hw_params.gphy_rev;
590}
591
bc0cb653
FF		 592static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
593 unsigned long *supported,
594 struct phylink_link_state *state)
595{
738a2e4b 596 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
bc0cb653
FF		 597 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
598
599 if (!phy_interface_mode_is_rgmii(state->interface) &&
600 state->interface != PHY_INTERFACE_MODE_MII &&
601 state->interface != PHY_INTERFACE_MODE_REVMII &&
602 state->interface != PHY_INTERFACE_MODE_GMII &&
603 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
604 state->interface != PHY_INTERFACE_MODE_MOCA) {
605 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
738a2e4b
FF		 606 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
607 dev_err(ds->dev,
608 "Unsupported interface: %d for port %d\n",
609 state->interface, port);
bc0cb653
FF		 610 return;
611 }
612
613 /* Allow all the expected bits */
614 phylink_set(mask, Autoneg);
615 phylink_set_port_modes(mask);
616 phylink_set(mask, Pause);
617 phylink_set(mask, Asym_Pause);
618
619 /* With the exclusion of MII and Reverse MII, we support Gigabit,
620 * including Half duplex
621 */
622 if (state->interface != PHY_INTERFACE_MODE_MII &&
623 state->interface != PHY_INTERFACE_MODE_REVMII) {
624 phylink_set(mask, 1000baseT_Full);
625 phylink_set(mask, 1000baseT_Half);
626 }
627
628 phylink_set(mask, 10baseT_Half);
629 phylink_set(mask, 10baseT_Full);
630 phylink_set(mask, 100baseT_Half);
631 phylink_set(mask, 100baseT_Full);
632
633 bitmap_and(supported, supported, mask,
634 __ETHTOOL_LINK_MODE_MASK_NBITS);
635 bitmap_and(state->advertising, state->advertising, mask,
636 __ETHTOOL_LINK_MODE_MASK_NBITS);
637}
638
639static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
640 unsigned int mode,
641 const struct phylink_link_state *state)
642{
643 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
644 u32 id_mode_dis = 0, port_mode;
50cc2020 645 u32 reg;
bc0cb653 646
738a2e4b
FF		 647 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
648 return;
649
bc0cb653
FF		 650 switch (state->interface) {
651 case PHY_INTERFACE_MODE_RGMII:
652 id_mode_dis = 1;
df561f66 653 fallthrough;
bc0cb653
FF		 654 case PHY_INTERFACE_MODE_RGMII_TXID:
655 port_mode = EXT_GPHY;
656 break;
657 case PHY_INTERFACE_MODE_MII:
658 port_mode = EXT_EPHY;
659 break;
660 case PHY_INTERFACE_MODE_REVMII:
661 port_mode = EXT_REVMII;
662 break;
663 default:
50cc2020
RK		 664 /* Nothing required for all other PHYs: internal and MoCA */
665 return;
bc0cb653
FF		 666 }
667
668 /* Clear id_mode_dis bit, and the existing port mode, let
669 * RGMII_MODE_EN bet set by mac_link_{up,down}
670 */
671 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
672 reg &= ~ID_MODE_DIS;
673 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
bc0cb653
FF		 674
675 reg |= port_mode;
676 if (id_mode_dis)
677 reg |= ID_MODE_DIS;
678
bc0cb653 679 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
bc0cb653
FF		 680}
681
682static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
683 phy_interface_t interface, bool link)
684{
685 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
686 u32 reg;
687
688 if (!phy_interface_mode_is_rgmii(interface) &&
689 interface != PHY_INTERFACE_MODE_MII &&
690 interface != PHY_INTERFACE_MODE_REVMII)
691 return;
692
693 /* If the link is down, just disable the interface to conserve power */
694 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
695 if (link)
696 reg |= RGMII_MODE_EN;
697 else
698 reg &= ~RGMII_MODE_EN;
699 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
700}
701
702static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
703 unsigned int mode,
704 phy_interface_t interface)
705{
2d1f90f9
RK		 706 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
707 u32 reg, offset;
708
709 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
73b7a604
RM		 710 if (priv->type == BCM4908_DEVICE_ID ||
711 priv->type == BCM7445_DEVICE_ID)
2d1f90f9
RK		 712 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
713 else
714 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
715
716 reg = core_readl(priv, offset);
717 reg &= ~LINK_STS;
718 core_writel(priv, reg, offset);
719 }
720
bc0cb653
FF		 721 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
722}
723
724static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
725 unsigned int mode,
726 phy_interface_t interface,
5b502a7b
RK		 727 struct phy_device *phydev,
728 int speed, int duplex,
729 bool tx_pause, bool rx_pause)
bc0cb653
FF		 730{
731 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
732 struct ethtool_eee *p = &priv->dev->ports[port].eee;
2d1f90f9 733 u32 reg, offset;
bc0cb653
FF		 734
735 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
736
2d1f90f9 737 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
73b7a604
RM		 738 if (priv->type == BCM4908_DEVICE_ID ||
739 priv->type == BCM7445_DEVICE_ID)
2d1f90f9
RK		 740 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
741 else
742 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
743
981015ac
RK		 744 if (interface == PHY_INTERFACE_MODE_RGMII ||
745 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
746 interface == PHY_INTERFACE_MODE_MII ||
747 interface == PHY_INTERFACE_MODE_REVMII) {
748 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
749 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
750
751 if (tx_pause)
752 reg |= TX_PAUSE_EN;
753 if (rx_pause)
754 reg |= RX_PAUSE_EN;
755
756 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
757 }
758
50cc2020
RK		 759 reg = SW_OVERRIDE | LINK_STS;
760 switch (speed) {
761 case SPEED_1000:
762 reg |= SPDSTS_1000 << SPEED_SHIFT;
763 break;
764 case SPEED_100:
765 reg |= SPDSTS_100 << SPEED_SHIFT;
766 break;
767 }
768
769 if (duplex == DUPLEX_FULL)
770 reg |= DUPLX_MODE;
771
2d1f90f9
RK		 772 core_writel(priv, reg, offset);
773 }
774
bc0cb653
FF		 775 if (mode == MLO_AN_PHY && phydev)
776 p->eee_enabled = b53_eee_init(ds, port, phydev);
777}
778
779static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
780 struct phylink_link_state *status)
781{
782 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
783
784 status->link = false;
785
786 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
787 * which means that we need to force the link at the port override
788 * level to get the data to flow. We do use what the interrupt handler
789 * did determine before.
790 *
791 * For the other ports, we just force the link status, since this is
792 * a fixed PHY device.
793 */
794 if (port == priv->moca_port) {
795 status->link = priv->port_sts[port].link;
796 /* For MoCA interfaces, also force a link down notification
797 * since some version of the user-space daemon (mocad) use
798 * cmd->autoneg to force the link, which messes up the PHY
799 * state machine and make it go in PHY_FORCING state instead.
800 */
801 if (!status->link)
68bb8ea8 802 netif_carrier_off(dsa_to_port(ds, port)->slave);
bc0cb653
FF		 803 status->duplex = DUPLEX_FULL;
804 } else {
805 status->link = true;
806 }
807}
808
32e47ff0
FF		 809static void bcm_sf2_enable_acb(struct dsa_switch *ds)
810{
811 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
812 u32 reg;
813
814 /* Enable ACB globally */
815 reg = acb_readl(priv, ACB_CONTROL);
816 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
817 acb_writel(priv, reg, ACB_CONTROL);
818 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
819 reg |= ACB_EN | ACB_ALGORITHM;
820 acb_writel(priv, reg, ACB_CONTROL);
821}
822
8cfa9498
FF		 823static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
824{
f458995b 825 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
8cfa9498
FF		 826 unsigned int port;
827
691c9a8f 828 bcm_sf2_intr_disable(priv);
8cfa9498
FF		 829
830 /* Disable all ports physically present including the IMP
831 * port, the other ones have already been disabled during
832 * bcm_sf2_sw_setup
833 */
8d6ea932 834 for (port = 0; port < ds->num_ports; port++) {
4a5b85ff 835 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
75104db0 836 bcm_sf2_port_disable(ds, port);
8cfa9498
FF		 837 }
838
e9ec5c3b
FF		 839 if (!priv->wol_ports_mask)
840 clk_disable_unprepare(priv->clk);
841
8cfa9498
FF		 842 return 0;
843}
844
8cfa9498
FF		 845static int bcm_sf2_sw_resume(struct dsa_switch *ds)
846{
f458995b 847 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
8cfa9498
FF		 848 int ret;
849
e9ec5c3b
FF		 850 if (!priv->wol_ports_mask)
851 clk_prepare_enable(priv->clk);
852
8cfa9498
FF		 853 ret = bcm_sf2_sw_rst(priv);
854 if (ret) {
855 pr_err("%s: failed to software reset switch\n", __func__);
856 return ret;
857 }
858
1c0130f0
FF		 859 ret = bcm_sf2_cfp_resume(ds);
860 if (ret)
861 return ret;
862
b083668c
FF		 863 if (priv->hw_params.num_gphy == 1)
864 bcm_sf2_gphy_enable_set(ds, true);
8cfa9498 865
abd01ba2 866 ds->ops->setup(ds);
32e47ff0 867
8cfa9498
FF		 868 return 0;
869}
870
96e65d7f
FF		 871static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
872 struct ethtool_wolinfo *wol)
873{
68bb8ea8 874 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
f458995b 875 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
c3152ec4 876 struct ethtool_wolinfo pwol = { };
96e65d7f
FF		 877
878 /* Get the parent device WoL settings */
c3152ec4
FF		 879 if (p->ethtool_ops->get_wol)
880 p->ethtool_ops->get_wol(p, &pwol);
96e65d7f
FF		 881
882 /* Advertise the parent device supported settings */
883 wol->supported = pwol.supported;
884 memset(&wol->sopass, 0, sizeof(wol->sopass));
885
886 if (pwol.wolopts & WAKE_MAGICSECURE)
887 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
888
889 if (priv->wol_ports_mask & (1 << port))
890 wol->wolopts = pwol.wolopts;
891 else
892 wol->wolopts = 0;
893}
894
895static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
896 struct ethtool_wolinfo *wol)
897{
68bb8ea8 898 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
f458995b 899 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
68bb8ea8 900 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
c3152ec4 901 struct ethtool_wolinfo pwol = { };
96e65d7f 902
c3152ec4
FF		 903 if (p->ethtool_ops->get_wol)
904 p->ethtool_ops->get_wol(p, &pwol);
96e65d7f
FF		 905 if (wol->wolopts & ~pwol.supported)
906 return -EINVAL;
907
908 if (wol->wolopts)
909 priv->wol_ports_mask |= (1 << port);
910 else
911 priv->wol_ports_mask &= ~(1 << port);
912
913 /* If we have at least one port enabled, make sure the CPU port
914 * is also enabled. If the CPU port is the last one enabled, we disable
915 * it since this configuration does not make sense.
916 */
917 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
918 priv->wol_ports_mask |= (1 << cpu_port);
919 else
920 priv->wol_ports_mask &= ~(1 << cpu_port);
921
922 return p->ethtool_ops->set_wol(p, wol);
923}
924
7fbb1a92
FF		 925static int bcm_sf2_sw_setup(struct dsa_switch *ds)
926{
f458995b 927 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
7fbb1a92 928 unsigned int port;
d9338023 929
21a2774e 930 /* Enable all valid ports and disable those unused */
d9338023 931 for (port = 0; port < priv->hw_params.num_ports; port++) {
21a2774e 932 /* IMP port receives special treatment */
4a5b85ff 933 if (dsa_is_user_port(ds, port))
21a2774e
FF		 934 bcm_sf2_port_setup(ds, port, NULL);
935 else if (dsa_is_cpu_port(ds, port))
d9338023 936 bcm_sf2_imp_setup(ds, port);
21a2774e 937 else
75104db0 938 bcm_sf2_port_disable(ds, port);
d9338023
FF		 939 }
940
5c1a6eaf 941 b53_configure_vlan(ds);
32e47ff0 942 bcm_sf2_enable_acb(ds);
d9338023 943
4f6a5caf
FF		 944 return b53_setup_devlink_resources(ds);
945}
946
947static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
948{
949 dsa_devlink_resources_unregister(ds);
d9338023
FF		 950}
951
f458995b
FF		 952/* The SWITCH_CORE register space is managed by b53 but operates on a page +
953 * register basis so we need to translate that into an address that the
954 * bus-glue understands.
955 */
956#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
957
958static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
959 u8 *val)
960{
961 struct bcm_sf2_priv *priv = dev->priv;
962
963 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
964
965 return 0;
966}
967
968static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
969 u16 *val)
970{
971 struct bcm_sf2_priv *priv = dev->priv;
972
973 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
974
975 return 0;
976}
977
978static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
979 u32 *val)
980{
981 struct bcm_sf2_priv *priv = dev->priv;
982
983 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
984
985 return 0;
986}
987
988static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
989 u64 *val)
990{
991 struct bcm_sf2_priv *priv = dev->priv;
992
993 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
994
995 return 0;
996}
997
998static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
999 u8 value)
1000{
1001 struct bcm_sf2_priv *priv = dev->priv;
1002
1003 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1004
1005 return 0;
1006}
1007
1008static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1009 u16 value)
1010{
1011 struct bcm_sf2_priv *priv = dev->priv;
1012
1013 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1014
1015 return 0;
1016}
1017
1018static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1019 u32 value)
1020{
1021 struct bcm_sf2_priv *priv = dev->priv;
1022
1023 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1024
1025 return 0;
1026}
1027
1028static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1029 u64 value)
1030{
1031 struct bcm_sf2_priv *priv = dev->priv;
1032
1033 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1034
1035 return 0;
1036}
1037
7e3108fa 1038static const struct b53_io_ops bcm_sf2_io_ops = {
f458995b
FF		 1039 .read8 = bcm_sf2_core_read8,
1040 .read16 = bcm_sf2_core_read16,
1041 .read32 = bcm_sf2_core_read32,
1042 .read48 = bcm_sf2_core_read64,
1043 .read64 = bcm_sf2_core_read64,
1044 .write8 = bcm_sf2_core_write8,
1045 .write16 = bcm_sf2_core_write16,
1046 .write32 = bcm_sf2_core_write32,
1047 .write48 = bcm_sf2_core_write64,
1048 .write64 = bcm_sf2_core_write64,
1049};
1050
badd62c2
FF		 1051static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1052 u32 stringset, uint8_t *data)
1053{
f4ae9c08
FF		 1054 int cnt = b53_get_sset_count(ds, port, stringset);
1055
badd62c2 1056 b53_get_strings(ds, port, stringset, data);
f4ae9c08
FF		 1057 bcm_sf2_cfp_get_strings(ds, port, stringset,
1058 data + cnt * ETH_GSTRING_LEN);
badd62c2
FF		 1059}
1060
1061static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1062 uint64_t *data)
1063{
f4ae9c08
FF		 1064 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
1065
badd62c2 1066 b53_get_ethtool_stats(ds, port, data);
f4ae9c08 1067 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
badd62c2
FF		 1068}
1069
1070static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1071 int sset)
1072{
f4ae9c08
FF		 1073 int cnt = b53_get_sset_count(ds, port, sset);
1074
1075 if (cnt < 0)
1076 return cnt;
1077
1078 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1079
1080 return cnt;
badd62c2
FF		 1081}
1082
a82f67af 1083static const struct dsa_switch_ops bcm_sf2_ops = {
9f66816a 1084 .get_tag_protocol = b53_get_tag_protocol,
73095cb1 1085 .setup = bcm_sf2_sw_setup,
4f6a5caf 1086 .teardown = bcm_sf2_sw_teardown,
badd62c2
FF		 1087 .get_strings = bcm_sf2_sw_get_strings,
1088 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1089 .get_sset_count = bcm_sf2_sw_get_sset_count,
c7d28c9d 1090 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
73095cb1 1091 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
bc0cb653
FF		 1092 .phylink_validate = bcm_sf2_sw_validate,
1093 .phylink_mac_config = bcm_sf2_sw_mac_config,
1094 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
1095 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
1096 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
73095cb1
FF		 1097 .suspend = bcm_sf2_sw_suspend,
1098 .resume = bcm_sf2_sw_resume,
1099 .get_wol = bcm_sf2_sw_get_wol,
1100 .set_wol = bcm_sf2_sw_set_wol,
1101 .port_enable = bcm_sf2_port_setup,
1102 .port_disable = bcm_sf2_port_disable,
22256b0a
FF		 1103 .get_mac_eee = b53_get_mac_eee,
1104 .set_mac_eee = b53_set_mac_eee,
73095cb1
FF		 1105 .port_bridge_join = b53_br_join,
1106 .port_bridge_leave = b53_br_leave,
e6dd86ed
FF		 1107 .port_pre_bridge_flags = b53_br_flags_pre,
1108 .port_bridge_flags = b53_br_flags,
73095cb1 1109 .port_stp_state_set = b53_br_set_stp_state,
e6dd86ed 1110 .port_set_mrouter = b53_set_mrouter,
73095cb1
FF		 1111 .port_fast_age = b53_br_fast_age,
1112 .port_vlan_filtering = b53_vlan_filtering,
73095cb1
FF		 1113 .port_vlan_add = b53_vlan_add,
1114 .port_vlan_del = b53_vlan_del,
73095cb1
FF		 1115 .port_fdb_dump = b53_fdb_dump,
1116 .port_fdb_add = b53_fdb_add,
1117 .port_fdb_del = b53_fdb_del,
7318166c
FF		 1118 .get_rxnfc = bcm_sf2_get_rxnfc,
1119 .set_rxnfc = bcm_sf2_set_rxnfc,
ec960de6
FF		 1120 .port_mirror_add = b53_mirror_add,
1121 .port_mirror_del = b53_mirror_del,
29bb5e83
FF		 1122 .port_mdb_add = b53_mdb_add,
1123 .port_mdb_del = b53_mdb_del,
73095cb1
FF		 1124};
1125
a78e86ed
FF		 1126struct bcm_sf2_of_data {
1127 u32 type;
1128 const u16 *reg_offsets;
1129 unsigned int core_reg_align;
df191632 1130 unsigned int num_cfp_rules;
a78e86ed
FF		 1131};
1132
73b7a604
RM		 1133static const u16 bcm_sf2_4908_reg_offsets[] = {
1134 [REG_SWITCH_CNTRL] = 0x00,
1135 [REG_SWITCH_STATUS] = 0x04,
1136 [REG_DIR_DATA_WRITE] = 0x08,
1137 [REG_DIR_DATA_READ] = 0x0c,
1138 [REG_SWITCH_REVISION] = 0x10,
1139 [REG_PHY_REVISION] = 0x14,
1140 [REG_SPHY_CNTRL] = 0x24,
1141 [REG_CROSSBAR] = 0xc8,
1142 [REG_RGMII_0_CNTRL] = 0xe0,
1143 [REG_RGMII_1_CNTRL] = 0xec,
1144 [REG_RGMII_2_CNTRL] = 0xf8,
1145 [REG_LED_0_CNTRL] = 0x40,
1146 [REG_LED_1_CNTRL] = 0x4c,
1147 [REG_LED_2_CNTRL] = 0x58,
1148};
1149
1150static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
1151 .type = BCM4908_DEVICE_ID,
1152 .core_reg_align = 0,
1153 .reg_offsets = bcm_sf2_4908_reg_offsets,
1154 .num_cfp_rules = 0, /* FIXME */
1155};
1156
a78e86ed
FF		 1157/* Register offsets for the SWITCH_REG_* block */
1158static const u16 bcm_sf2_7445_reg_offsets[] = {
1159 [REG_SWITCH_CNTRL] = 0x00,
1160 [REG_SWITCH_STATUS] = 0x04,
1161 [REG_DIR_DATA_WRITE] = 0x08,
1162 [REG_DIR_DATA_READ] = 0x0C,
1163 [REG_SWITCH_REVISION] = 0x18,
1164 [REG_PHY_REVISION] = 0x1C,
1165 [REG_SPHY_CNTRL] = 0x2C,
1166 [REG_RGMII_0_CNTRL] = 0x34,
1167 [REG_RGMII_1_CNTRL] = 0x40,
1168 [REG_RGMII_2_CNTRL] = 0x4c,
1169 [REG_LED_0_CNTRL] = 0x90,
1170 [REG_LED_1_CNTRL] = 0x94,
1171 [REG_LED_2_CNTRL] = 0x98,
1172};
1173
1174static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1175 .type = BCM7445_DEVICE_ID,
1176 .core_reg_align = 0,
1177 .reg_offsets = bcm_sf2_7445_reg_offsets,
df191632 1178 .num_cfp_rules = 256,
a78e86ed
FF		 1179};
1180
0fe99338
FF		 1181static const u16 bcm_sf2_7278_reg_offsets[] = {
1182 [REG_SWITCH_CNTRL] = 0x00,
1183 [REG_SWITCH_STATUS] = 0x04,
1184 [REG_DIR_DATA_WRITE] = 0x08,
1185 [REG_DIR_DATA_READ] = 0x0c,
1186 [REG_SWITCH_REVISION] = 0x10,
1187 [REG_PHY_REVISION] = 0x14,
1188 [REG_SPHY_CNTRL] = 0x24,
1189 [REG_RGMII_0_CNTRL] = 0xe0,
1190 [REG_RGMII_1_CNTRL] = 0xec,
1191 [REG_RGMII_2_CNTRL] = 0xf8,
1192 [REG_LED_0_CNTRL] = 0x40,
1193 [REG_LED_1_CNTRL] = 0x4c,
1194 [REG_LED_2_CNTRL] = 0x58,
1195};
1196
1197static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1198 .type = BCM7278_DEVICE_ID,
1199 .core_reg_align = 1,
1200 .reg_offsets = bcm_sf2_7278_reg_offsets,
df191632 1201 .num_cfp_rules = 128,
0fe99338
FF		 1202};
1203
a78e86ed 1204static const struct of_device_id bcm_sf2_of_match[] = {
73b7a604
RM		 1205 { .compatible = "brcm,bcm4908-switch",
1206 .data = &bcm_sf2_4908_data
1207 },
a78e86ed
FF		 1208 { .compatible = "brcm,bcm7445-switch-v4.0",
1209 .data = &bcm_sf2_7445_data
1210 },
0fe99338
FF		 1211 { .compatible = "brcm,bcm7278-switch-v4.0",
1212 .data = &bcm_sf2_7278_data
3b07d788
FF		 1213 },
1214 { .compatible = "brcm,bcm7278-switch-v4.8",
1215 .data = &bcm_sf2_7278_data
0fe99338 1216 },
a78e86ed
FF		 1217 { /* sentinel */ },
1218};
1219MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1220
d9338023
FF		 1221static int bcm_sf2_sw_probe(struct platform_device *pdev)
1222{
1223 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1224 struct device_node *dn = pdev->dev.of_node;
a78e86ed
FF		 1225 const struct of_device_id *of_id = NULL;
1226 const struct bcm_sf2_of_data *data;
f458995b 1227 struct b53_platform_data *pdata;
a4c61b92 1228 struct dsa_switch_ops *ops;
afa3b592 1229 struct device_node *ports;
d9338023 1230 struct bcm_sf2_priv *priv;
f458995b 1231 struct b53_device *dev;
d9338023
FF		 1232 struct dsa_switch *ds;
1233 void __iomem **base;
7fbb1a92
FF		 1234 unsigned int i;
1235 u32 reg, rev;
1236 int ret;
1237
f458995b
FF		 1238 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1239 if (!priv)
1240 return -ENOMEM;
1241
a4c61b92
FF		 1242 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1243 if (!ops)
1244 return -ENOMEM;
1245
f458995b
FF		 1246 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1247 if (!dev)
d9338023
FF		 1248 return -ENOMEM;
1249
f458995b
FF		 1250 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1251 if (!pdata)
1252 return -ENOMEM;
1253
a78e86ed
FF		 1254 of_id = of_match_node(bcm_sf2_of_match, dn);
1255 if (!of_id || !of_id->data)
1256 return -EINVAL;
1257
1258 data = of_id->data;
1259
1260 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1261 priv->type = data->type;
1262 priv->reg_offsets = data->reg_offsets;
1263 priv->core_reg_align = data->core_reg_align;
df191632 1264 priv->num_cfp_rules = data->num_cfp_rules;
a78e86ed 1265
eee87e43
FF		 1266 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1267 "switch");
bf9279cd 1268 if (IS_ERR(priv->rcdev))
eee87e43
FF		 1269 return PTR_ERR(priv->rcdev);
1270
f458995b
FF		 1271 /* Auto-detection using standard registers will not work, so
1272 * provide an indication of what kind of device we are for
1273 * b53_common to work with
1274 */
a78e86ed 1275 pdata->chip_id = priv->type;
f458995b
FF		 1276 dev->pdata = pdata;
1277
1278 priv->dev = dev;
1279 ds = dev->ds;
73095cb1 1280 ds->ops = &bcm_sf2_ops;
d9338023 1281
18118377
FF		 1282 /* Advertise the 8 egress queues */
1283 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1284
f458995b 1285 dev_set_drvdata(&pdev->dev, priv);
d9338023 1286
7fbb1a92 1287 spin_lock_init(&priv->indir_lock);
7318166c 1288 mutex_init(&priv->cfp.lock);
ae7a5aff 1289 INIT_LIST_HEAD(&priv->cfp.rules_list);
7318166c
FF		 1290
1291 /* CFP rule #0 cannot be used for specific classifications, flag it as
1292 * permanently used
1293 */
1294 set_bit(0, priv->cfp.used);
ba0696c2 1295 set_bit(0, priv->cfp.unique);
7fbb1a92 1296
8dbe4c5d
FF		 1297 /* Balance of_node_put() done by of_find_node_by_name() */
1298 of_node_get(dn);
afa3b592
FF		 1299 ports = of_find_node_by_name(dn, "ports");
1300 if (ports) {
1301 bcm_sf2_identify_ports(priv, ports);
1302 of_node_put(ports);
1303 }
7fbb1a92
FF		 1304
1305 priv->irq0 = irq_of_parse_and_map(dn, 0);
1306 priv->irq1 = irq_of_parse_and_map(dn, 1);
1307
1308 base = &priv->core;
1309 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
42376788 1310 *base = devm_platform_ioremap_resource(pdev, i);
4bd11675 1311 if (IS_ERR(*base)) {
7fbb1a92 1312 pr_err("unable to find register: %s\n", reg_names[i]);
4bd11675 1313 return PTR_ERR(*base);
7fbb1a92
FF		 1314 }
1315 base++;
1316 }
1317
e9ec5c3b
FF		 1318 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch");
1319 if (IS_ERR(priv->clk))
1320 return PTR_ERR(priv->clk);
1321
1322 clk_prepare_enable(priv->clk);
1323
2ee3adc4
FF		 1324 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv");
1325 if (IS_ERR(priv->clk_mdiv)) {
1326 ret = PTR_ERR(priv->clk_mdiv);
1327 goto out_clk;
1328 }
1329
1330 clk_prepare_enable(priv->clk_mdiv);
1331
7fbb1a92
FF		 1332 ret = bcm_sf2_sw_rst(priv);
1333 if (ret) {
1334 pr_err("unable to software reset switch: %d\n", ret);
2ee3adc4 1335 goto out_clk_mdiv;
7fbb1a92
FF		 1336 }
1337
c04a17d2
FF		 1338 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1339
7fbb1a92
FF		 1340 ret = bcm_sf2_mdio_register(ds);
1341 if (ret) {
1342 pr_err("failed to register MDIO bus\n");
2ee3adc4 1343 goto out_clk_mdiv;
7fbb1a92
FF		 1344 }
1345
c04a17d2
FF		 1346 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1347
7318166c
FF		 1348 ret = bcm_sf2_cfp_rst(priv);
1349 if (ret) {
1350 pr_err("failed to reset CFP\n");
1351 goto out_mdio;
1352 }
1353
7fbb1a92
FF		 1354 /* Disable all interrupts and request them */
1355 bcm_sf2_intr_disable(priv);
1356
4bd11675 1357 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
bc0cb653 1358 "switch_0", ds);
7fbb1a92
FF		 1359 if (ret < 0) {
1360 pr_err("failed to request switch_0 IRQ\n");
bb9c0fa3 1361 goto out_mdio;
7fbb1a92
FF		 1362 }
1363
4bd11675 1364 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
bc0cb653 1365 "switch_1", ds);
7fbb1a92
FF		 1366 if (ret < 0) {
1367 pr_err("failed to request switch_1 IRQ\n");
4bd11675 1368 goto out_mdio;
7fbb1a92
FF		 1369 }
1370
1371 /* Reset the MIB counters */
1372 reg = core_readl(priv, CORE_GMNCFGCFG);
1373 reg |= RST_MIB_CNT;
1374 core_writel(priv, reg, CORE_GMNCFGCFG);
1375 reg &= ~RST_MIB_CNT;
1376 core_writel(priv, reg, CORE_GMNCFGCFG);
1377
1378 /* Get the maximum number of ports for this switch */
1379 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1380 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1381 priv->hw_params.num_ports = DSA_MAX_PORTS;
1382
1383 /* Assume a single GPHY setup if we can't read that property */
1384 if (of_property_read_u32(dn, "brcm,num-gphy",
1385 &priv->hw_params.num_gphy))
1386 priv->hw_params.num_gphy = 1;
1387
7fbb1a92
FF		 1388 rev = reg_readl(priv, REG_SWITCH_REVISION);
1389 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1390 SWITCH_TOP_REV_MASK;
1391 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1392
1393 rev = reg_readl(priv, REG_PHY_REVISION);
1394 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1395
f458995b 1396 ret = b53_switch_register(dev);
d9338023 1397 if (ret)
4bd11675 1398 goto out_mdio;
d9338023 1399
fbb7bc45
FF		 1400 dev_info(&pdev->dev,
1401 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1402 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1403 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1404 priv->irq0, priv->irq1);
7fbb1a92
FF		 1405
1406 return 0;
1407
bb9c0fa3
FF		 1408out_mdio:
1409 bcm_sf2_mdio_unregister(priv);
2ee3adc4
FF		 1410out_clk_mdiv:
1411 clk_disable_unprepare(priv->clk_mdiv);
e9ec5c3b
FF		 1412out_clk:
1413 clk_disable_unprepare(priv->clk);
7fbb1a92
FF		 1414 return ret;
1415}
1416
d9338023 1417static int bcm_sf2_sw_remove(struct platform_device *pdev)
246d7f77 1418{
f458995b 1419 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
d9338023 1420
d9338023 1421 priv->wol_ports_mask = 0;
e684000b
FF		 1422 /* Disable interrupts */
1423 bcm_sf2_intr_disable(priv);
f458995b 1424 dsa_unregister_switch(priv->dev->ds);
ae7a5aff 1425 bcm_sf2_cfp_exit(priv->dev->ds);
d9338023 1426 bcm_sf2_mdio_unregister(priv);
2ee3adc4 1427 clk_disable_unprepare(priv->clk_mdiv);
e9ec5c3b 1428 clk_disable_unprepare(priv->clk);
bf9279cd 1429 if (priv->type == BCM7278_DEVICE_ID)
eee87e43 1430 reset_control_assert(priv->rcdev);
246d7f77
FF		 1431
1432 return 0;
1433}
246d7f77 1434
2399d614
FF		 1435static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1436{
1437 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1438
1439 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1440 * successful MDIO bus scan to occur. If we did turn off the GPHY
1441 * before (e.g: port_disable), this will also power it back on.
4a2947e3
FF		 1442 *
1443 * Do not rely on kexec_in_progress, just power the PHY on.
2399d614
FF		 1444 */
1445 if (priv->hw_params.num_gphy == 1)
4a2947e3 1446 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
2399d614
FF		 1447}
1448
d9338023
FF		 1449#ifdef CONFIG_PM_SLEEP
1450static int bcm_sf2_suspend(struct device *dev)
246d7f77 1451{
63382e0a 1452 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
d9338023 1453
f458995b 1454 return dsa_switch_suspend(priv->dev->ds);
246d7f77 1455}
d9338023
FF		 1456
1457static int bcm_sf2_resume(struct device *dev)
1458{
63382e0a 1459 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
d9338023 1460
f458995b 1461 return dsa_switch_resume(priv->dev->ds);
d9338023
FF		 1462}
1463#endif /* CONFIG_PM_SLEEP */
1464
1465static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1466 bcm_sf2_suspend, bcm_sf2_resume);
1467
d9338023
FF		 1468
1469static struct platform_driver bcm_sf2_driver = {
1470 .probe = bcm_sf2_sw_probe,
1471 .remove = bcm_sf2_sw_remove,
2399d614 1472 .shutdown = bcm_sf2_sw_shutdown,
d9338023
FF		 1473 .driver = {
1474 .name = "brcm-sf2",
1475 .of_match_table = bcm_sf2_of_match,
1476 .pm = &bcm_sf2_pm_ops,
1477 },
1478};
1479module_platform_driver(bcm_sf2_driver);
246d7f77
FF		 1480
1481MODULE_AUTHOR("Broadcom Corporation");
1482MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1483MODULE_LICENSE("GPL");
1484MODULE_ALIAS("platform:brcm-sf2");
Linux 6.x block layer and io_uring tree(s)