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Merge branch 'linus' into x86/urgent
[linux-2.6-block.git] / drivers / net / dsa / bcm_sf2.c
CommitLineData
246d7f77
FF		 1/*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
246d7f77
FF		 17#include <linux/phy.h>
18#include <linux/phy_fixed.h>
bc0cb653 19#include <linux/phylink.h>
246d7f77
FF		 20#include <linux/mii.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
8b7c94e3 24#include <linux/of_net.h>
461cd1b0 25#include <linux/of_mdio.h>
246d7f77 26#include <net/dsa.h>
96e65d7f 27#include <linux/ethtool.h>
12f460f2 28#include <linux/if_bridge.h>
aafc66f1 29#include <linux/brcmphy.h>
680060d3 30#include <linux/etherdevice.h>
f458995b 31#include <linux/platform_data/b53.h>
246d7f77
FF		 32
33#include "bcm_sf2.h"
34#include "bcm_sf2_regs.h"
f458995b
FF		 35#include "b53/b53_priv.h"
36#include "b53/b53_regs.h"
246d7f77 37
ebb2ac4f
FF		 38static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
39{
40 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
c837fc81 41 unsigned int i;
ebb2ac4f
FF		 42 u32 reg, offset;
43
44 if (priv->type == BCM7445_DEVICE_ID)
45 offset = CORE_STS_OVERRIDE_IMP;
46 else
47 offset = CORE_STS_OVERRIDE_IMP2;
48
49 /* Enable the port memories */
50 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
51 reg &= ~P_TXQ_PSM_VDD(port);
52 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
53
54 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
55 reg = core_readl(priv, CORE_IMP_CTL);
56 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
57 reg &= ~(RX_DIS | TX_DIS);
58 core_writel(priv, reg, CORE_IMP_CTL);
59
60 /* Enable forwarding */
61 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
62
63 /* Enable IMP port in dumb mode */
64 reg = core_readl(priv, CORE_SWITCH_CTRL);
65 reg |= MII_DUMB_FWDG_EN;
66 core_writel(priv, reg, CORE_SWITCH_CTRL);
67
c837fc81
FF		 68 /* Configure Traffic Class to QoS mapping, allow each priority to map
69 * to a different queue number
70 */
71 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
72 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
73 reg |= i << (PRT_TO_QID_SHIFT * i);
74 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
75
b409a9ef 76 b53_brcm_hdr_setup(ds, port);
246d7f77
FF		 77
78 /* Force link status for IMP port */
0fe99338 79 reg = core_readl(priv, offset);
246d7f77 80 reg |= (MII_SW_OR | LINK_STS);
0fe99338 81 core_writel(priv, reg, offset);
246d7f77
FF		 82}
83
b083668c
FF		 84static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
85{
f458995b 86 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
b083668c
FF		 87 u32 reg;
88
b083668c 89 reg = reg_readl(priv, REG_SPHY_CNTRL);
9af197a8
FF		 90 if (enable) {
91 reg |= PHY_RESET;
4b52d010 92 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
9af197a8
FF		 93 reg_writel(priv, reg, REG_SPHY_CNTRL);
94 udelay(21);
95 reg = reg_readl(priv, REG_SPHY_CNTRL);
96 reg &= ~PHY_RESET;
97 } else {
98 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
99 reg_writel(priv, reg, REG_SPHY_CNTRL);
100 mdelay(1);
101 reg |= CK25_DIS;
102 }
b083668c 103 reg_writel(priv, reg, REG_SPHY_CNTRL);
9af197a8
FF		 104
105 /* Use PHY-driven LED signaling */
106 if (!enable) {
107 reg = reg_readl(priv, REG_LED_CNTRL(0));
108 reg |= SPDLNK_SRC_SEL;
109 reg_writel(priv, reg, REG_LED_CNTRL(0));
110 }
b083668c
FF		 111}
112
8b7c94e3
FF		 113static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
114 int port)
115{
116 unsigned int off;
117
118 switch (port) {
119 case 7:
120 off = P7_IRQ_OFF;
121 break;
122 case 0:
123 /* Port 0 interrupts are located on the first bank */
124 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
125 return;
126 default:
127 off = P_IRQ_OFF(port);
128 break;
129 }
130
131 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
132}
133
134static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
135 int port)
136{
137 unsigned int off;
138
139 switch (port) {
140 case 7:
141 off = P7_IRQ_OFF;
142 break;
143 case 0:
144 /* Port 0 interrupts are located on the first bank */
145 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
146 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
147 return;
148 default:
149 off = P_IRQ_OFF(port);
150 break;
151 }
152
153 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
154 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
155}
156
b6d045db
FF		 157static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
158 struct phy_device *phy)
246d7f77 159{
f458995b 160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
e1b9147c 161 unsigned int i;
246d7f77
FF		 162 u32 reg;
163
164 /* Clear the memory power down */
165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
166 reg &= ~P_TXQ_PSM_VDD(port);
167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
168
64ff2aef
FF		 169 /* Enable Broadcom tags for that port if requested */
170 if (priv->brcm_tag_mask & BIT(port))
b409a9ef 171 b53_brcm_hdr_setup(ds, port);
64ff2aef 172
e1b9147c
FF		 173 /* Configure Traffic Class to QoS mapping, allow each priority to map
174 * to a different queue number
175 */
176 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
18118377 177 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
e1b9147c
FF		 178 reg |= i << (PRT_TO_QID_SHIFT * i);
179 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
180
9af197a8 181 /* Re-enable the GPHY and re-apply workarounds */
8b7c94e3 182 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
9af197a8
FF		 183 bcm_sf2_gphy_enable_set(ds, true);
184 if (phy) {
185 /* if phy_stop() has been called before, phy
186 * will be in halted state, and phy_start()
187 * will call resume.
188 *
189 * the resume path does not configure back
190 * autoneg settings, and since we hard reset
191 * the phy manually here, we need to reset the
192 * state machine also.
193 */
194 phy->state = PHY_READY;
195 phy_init_hw(phy);
196 }
197 }
198
8b7c94e3
FF		 199 /* Enable MoCA port interrupts to get notified */
200 if (port == priv->moca_port)
201 bcm_sf2_port_intr_enable(priv, port);
246d7f77 202
32e47ff0
FF		 203 /* Set per-queue pause threshold to 32 */
204 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
205
206 /* Set ACB threshold to 24 */
207 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
208 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
209 SF2_NUM_EGRESS_QUEUES + i));
210 reg &= ~XOFF_THRESHOLD_MASK;
211 reg |= 24;
212 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
213 SF2_NUM_EGRESS_QUEUES + i));
214 }
215
f86ad77f 216 return b53_enable_port(ds, port, phy);
246d7f77
FF		 217}
218
b6d045db
FF		 219static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
220 struct phy_device *phy)
246d7f77 221{
f458995b 222 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
246d7f77
FF		 223 u32 off, reg;
224
96e65d7f
FF		 225 if (priv->wol_ports_mask & (1 << port))
226 return;
227
8b7c94e3
FF		 228 if (port == priv->moca_port)
229 bcm_sf2_port_intr_disable(priv, port);
b6d045db 230
8b7c94e3 231 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
9af197a8
FF		 232 bcm_sf2_gphy_enable_set(ds, false);
233
246d7f77
FF		 234 if (dsa_is_cpu_port(ds, port))
235 off = CORE_IMP_CTL;
236 else
237 off = CORE_G_PCTL_PORT(port);
238
f86ad77f 239 b53_disable_port(ds, port, phy);
246d7f77
FF		 240
241 /* Power down the port memory */
242 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
243 reg |= P_TXQ_PSM_VDD(port);
244 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
245}
246
450b05c1 247
461cd1b0
FF		 248static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
249 int regnum, u16 val)
250{
251 int ret = 0;
252 u32 reg;
253
254 reg = reg_readl(priv, REG_SWITCH_CNTRL);
255 reg |= MDIO_MASTER_SEL;
256 reg_writel(priv, reg, REG_SWITCH_CNTRL);
257
258 /* Page << 8 | offset */
259 reg = 0x70;
260 reg <<= 2;
261 core_writel(priv, addr, reg);
262
263 /* Page << 8 | offset */
264 reg = 0x80 << 8 | regnum << 1;
265 reg <<= 2;
266
267 if (op)
268 ret = core_readl(priv, reg);
269 else
270 core_writel(priv, val, reg);
271
272 reg = reg_readl(priv, REG_SWITCH_CNTRL);
273 reg &= ~MDIO_MASTER_SEL;
274 reg_writel(priv, reg, REG_SWITCH_CNTRL);
275
276 return ret & 0xffff;
277}
278
279static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
280{
281 struct bcm_sf2_priv *priv = bus->priv;
282
283 /* Intercept reads from Broadcom pseudo-PHY address, else, send
284 * them to our master MDIO bus controller
285 */
286 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
287 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
288 else
2cfe8f82 289 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
461cd1b0
FF		 290}
291
292static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
293 u16 val)
294{
295 struct bcm_sf2_priv *priv = bus->priv;
296
297 /* Intercept writes to the Broadcom pseudo-PHY address, else,
298 * send them to our master MDIO bus controller
299 */
300 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
301 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
302 else
2cfe8f82 303 mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val);
461cd1b0
FF		 304
305 return 0;
306}
307
246d7f77
FF		 308static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
309{
bc0cb653
FF		 310 struct dsa_switch *ds = dev_id;
311 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
246d7f77
FF		 312
313 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
314 ~priv->irq0_mask;
315 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
316
317 return IRQ_HANDLED;
318}
319
320static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
321{
bc0cb653
FF		 322 struct dsa_switch *ds = dev_id;
323 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
246d7f77
FF		 324
325 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
326 ~priv->irq1_mask;
327 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
328
bc0cb653
FF		 329 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
330 priv->port_sts[7].link = true;
331 dsa_port_phylink_mac_change(ds, 7, true);
332 }
333 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
334 priv->port_sts[7].link = false;
335 dsa_port_phylink_mac_change(ds, 7, false);
336 }
246d7f77
FF		 337
338 return IRQ_HANDLED;
339}
340
33f84614
FF		 341static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
342{
343 unsigned int timeout = 1000;
344 u32 reg;
345
346 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
347 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
348 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
349
350 do {
351 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
352 if (!(reg & SOFTWARE_RESET))
353 break;
354
355 usleep_range(1000, 2000);
356 } while (timeout-- > 0);
357
358 if (timeout == 0)
359 return -ETIMEDOUT;
360
361 return 0;
362}
363
691c9a8f
FF		 364static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
365{
f01d5988 366 intrl2_0_mask_set(priv, 0xffffffff);
691c9a8f 367 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
f01d5988 368 intrl2_1_mask_set(priv, 0xffffffff);
691c9a8f 369 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
691c9a8f
FF		 370}
371
8b7c94e3
FF		 372static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
373 struct device_node *dn)
374{
375 struct device_node *port;
8b7c94e3
FF		 376 int mode;
377 unsigned int port_num;
8b7c94e3
FF		 378
379 priv->moca_port = -1;
380
381 for_each_available_child_of_node(dn, port) {
382 if (of_property_read_u32(port, "reg", &port_num))
383 continue;
384
385 /* Internal PHYs get assigned a specific 'phy-mode' property
386 * value: "internal" to help flag them before MDIO probing
387 * has completed, since they might be turned off at that
388 * time
389 */
390 mode = of_get_phy_mode(port);
bedd00c8
FF		 391 if (mode < 0)
392 continue;
393
394 if (mode == PHY_INTERFACE_MODE_INTERNAL)
395 priv->int_phy_mask |= 1 << port_num;
8b7c94e3
FF		 396
397 if (mode == PHY_INTERFACE_MODE_MOCA)
398 priv->moca_port = port_num;
64ff2aef
FF		 399
400 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
401 priv->brcm_tag_mask |= 1 << port_num;
8b7c94e3
FF		 402 }
403}
404
461cd1b0
FF		 405static int bcm_sf2_mdio_register(struct dsa_switch *ds)
406{
f458995b 407 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
461cd1b0
FF		 408 struct device_node *dn;
409 static int index;
410 int err;
411
412 /* Find our integrated MDIO bus node */
413 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
414 priv->master_mii_bus = of_mdio_find_bus(dn);
415 if (!priv->master_mii_bus)
416 return -EPROBE_DEFER;
417
418 get_device(&priv->master_mii_bus->dev);
419 priv->master_mii_dn = dn;
420
421 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
422 if (!priv->slave_mii_bus)
423 return -ENOMEM;
424
425 priv->slave_mii_bus->priv = priv;
426 priv->slave_mii_bus->name = "sf2 slave mii";
427 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
428 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
429 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
430 index++);
431 priv->slave_mii_bus->dev.of_node = dn;
432
433 /* Include the pseudo-PHY address to divert reads towards our
434 * workaround. This is only required for 7445D0, since 7445E0
435 * disconnects the internal switch pseudo-PHY such that we can use the
436 * regular SWITCH_MDIO master controller instead.
437 *
438 * Here we flag the pseudo PHY as needing special treatment and would
439 * otherwise make all other PHY read/writes go to the master MDIO bus
440 * controller that comes with this switch backed by the "mdio-unimac"
441 * driver.
442 */
443 if (of_machine_is_compatible("brcm,bcm7445d0"))
444 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
445 else
446 priv->indir_phy_mask = 0;
447
448 ds->phys_mii_mask = priv->indir_phy_mask;
449 ds->slave_mii_bus = priv->slave_mii_bus;
450 priv->slave_mii_bus->parent = ds->dev->parent;
451 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
452
00e798c7
FF		 453 err = of_mdiobus_register(priv->slave_mii_bus, dn);
454 if (err && dn)
461cd1b0
FF		 455 of_node_put(dn);
456
457 return err;
458}
459
460static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
461{
462 mdiobus_unregister(priv->slave_mii_bus);
463 if (priv->master_mii_dn)
464 of_node_put(priv->master_mii_dn);
465}
466
aa9aef77
FF		 467static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
468{
f458995b 469 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
aa9aef77
FF		 470
471 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
472 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
473 * the REG_PHY_REVISION register layout is.
474 */
475
476 return priv->hw_params.gphy_rev;
477}
478
bc0cb653
FF		 479static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
480 unsigned long *supported,
481 struct phylink_link_state *state)
482{
483 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
484
485 if (!phy_interface_mode_is_rgmii(state->interface) &&
486 state->interface != PHY_INTERFACE_MODE_MII &&
487 state->interface != PHY_INTERFACE_MODE_REVMII &&
488 state->interface != PHY_INTERFACE_MODE_GMII &&
489 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
490 state->interface != PHY_INTERFACE_MODE_MOCA) {
491 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
492 dev_err(ds->dev,
493 "Unsupported interface: %d\n", state->interface);
494 return;
495 }
496
497 /* Allow all the expected bits */
498 phylink_set(mask, Autoneg);
499 phylink_set_port_modes(mask);
500 phylink_set(mask, Pause);
501 phylink_set(mask, Asym_Pause);
502
503 /* With the exclusion of MII and Reverse MII, we support Gigabit,
504 * including Half duplex
505 */
506 if (state->interface != PHY_INTERFACE_MODE_MII &&
507 state->interface != PHY_INTERFACE_MODE_REVMII) {
508 phylink_set(mask, 1000baseT_Full);
509 phylink_set(mask, 1000baseT_Half);
510 }
511
512 phylink_set(mask, 10baseT_Half);
513 phylink_set(mask, 10baseT_Full);
514 phylink_set(mask, 100baseT_Half);
515 phylink_set(mask, 100baseT_Full);
516
517 bitmap_and(supported, supported, mask,
518 __ETHTOOL_LINK_MODE_MASK_NBITS);
519 bitmap_and(state->advertising, state->advertising, mask,
520 __ETHTOOL_LINK_MODE_MASK_NBITS);
521}
522
523static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
524 unsigned int mode,
525 const struct phylink_link_state *state)
526{
527 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
528 u32 id_mode_dis = 0, port_mode;
529 u32 reg, offset;
530
531 if (priv->type == BCM7445_DEVICE_ID)
532 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
533 else
534 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
535
536 switch (state->interface) {
537 case PHY_INTERFACE_MODE_RGMII:
538 id_mode_dis = 1;
539 /* fallthrough */
540 case PHY_INTERFACE_MODE_RGMII_TXID:
541 port_mode = EXT_GPHY;
542 break;
543 case PHY_INTERFACE_MODE_MII:
544 port_mode = EXT_EPHY;
545 break;
546 case PHY_INTERFACE_MODE_REVMII:
547 port_mode = EXT_REVMII;
548 break;
549 default:
550 /* all other PHYs: internal and MoCA */
551 goto force_link;
552 }
553
554 /* Clear id_mode_dis bit, and the existing port mode, let
555 * RGMII_MODE_EN bet set by mac_link_{up,down}
556 */
557 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
558 reg &= ~ID_MODE_DIS;
559 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
560 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
561
562 reg |= port_mode;
563 if (id_mode_dis)
564 reg |= ID_MODE_DIS;
565
566 if (state->pause & MLO_PAUSE_TXRX_MASK) {
567 if (state->pause & MLO_PAUSE_TX)
568 reg |= TX_PAUSE_EN;
569 reg |= RX_PAUSE_EN;
570 }
571
572 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
573
574force_link:
575 /* Force link settings detected from the PHY */
576 reg = SW_OVERRIDE;
577 switch (state->speed) {
578 case SPEED_1000:
579 reg |= SPDSTS_1000 << SPEED_SHIFT;
580 break;
581 case SPEED_100:
582 reg |= SPDSTS_100 << SPEED_SHIFT;
583 break;
584 }
585
586 if (state->link)
587 reg |= LINK_STS;
588 if (state->duplex == DUPLEX_FULL)
589 reg |= DUPLX_MODE;
590
591 core_writel(priv, reg, offset);
592}
593
594static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
595 phy_interface_t interface, bool link)
596{
597 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
598 u32 reg;
599
600 if (!phy_interface_mode_is_rgmii(interface) &&
601 interface != PHY_INTERFACE_MODE_MII &&
602 interface != PHY_INTERFACE_MODE_REVMII)
603 return;
604
605 /* If the link is down, just disable the interface to conserve power */
606 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
607 if (link)
608 reg |= RGMII_MODE_EN;
609 else
610 reg &= ~RGMII_MODE_EN;
611 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
612}
613
614static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
615 unsigned int mode,
616 phy_interface_t interface)
617{
618 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
619}
620
621static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
622 unsigned int mode,
623 phy_interface_t interface,
624 struct phy_device *phydev)
625{
626 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
627 struct ethtool_eee *p = &priv->dev->ports[port].eee;
628
629 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
630
631 if (mode == MLO_AN_PHY && phydev)
632 p->eee_enabled = b53_eee_init(ds, port, phydev);
633}
634
635static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
636 struct phylink_link_state *status)
637{
638 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
639
640 status->link = false;
641
642 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
643 * which means that we need to force the link at the port override
644 * level to get the data to flow. We do use what the interrupt handler
645 * did determine before.
646 *
647 * For the other ports, we just force the link status, since this is
648 * a fixed PHY device.
649 */
650 if (port == priv->moca_port) {
651 status->link = priv->port_sts[port].link;
652 /* For MoCA interfaces, also force a link down notification
653 * since some version of the user-space daemon (mocad) use
654 * cmd->autoneg to force the link, which messes up the PHY
655 * state machine and make it go in PHY_FORCING state instead.
656 */
657 if (!status->link)
658 netif_carrier_off(ds->ports[port].slave);
659 status->duplex = DUPLEX_FULL;
660 } else {
661 status->link = true;
662 }
663}
664
32e47ff0
FF		 665static void bcm_sf2_enable_acb(struct dsa_switch *ds)
666{
667 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
668 u32 reg;
669
670 /* Enable ACB globally */
671 reg = acb_readl(priv, ACB_CONTROL);
672 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
673 acb_writel(priv, reg, ACB_CONTROL);
674 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
675 reg |= ACB_EN | ACB_ALGORITHM;
676 acb_writel(priv, reg, ACB_CONTROL);
677}
678
8cfa9498
FF		 679static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
680{
f458995b 681 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
8cfa9498
FF		 682 unsigned int port;
683
691c9a8f 684 bcm_sf2_intr_disable(priv);
8cfa9498
FF		 685
686 /* Disable all ports physically present including the IMP
687 * port, the other ones have already been disabled during
688 * bcm_sf2_sw_setup
689 */
690 for (port = 0; port < DSA_MAX_PORTS; port++) {
4a5b85ff 691 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
b6d045db 692 bcm_sf2_port_disable(ds, port, NULL);
8cfa9498
FF		 693 }
694
695 return 0;
696}
697
8cfa9498
FF		 698static int bcm_sf2_sw_resume(struct dsa_switch *ds)
699{
f458995b 700 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
8cfa9498 701 unsigned int port;
8cfa9498
FF		 702 int ret;
703
704 ret = bcm_sf2_sw_rst(priv);
705 if (ret) {
706 pr_err("%s: failed to software reset switch\n", __func__);
707 return ret;
708 }
709
b083668c
FF		 710 if (priv->hw_params.num_gphy == 1)
711 bcm_sf2_gphy_enable_set(ds, true);
8cfa9498
FF		 712
713 for (port = 0; port < DSA_MAX_PORTS; port++) {
4a5b85ff 714 if (dsa_is_user_port(ds, port))
b6d045db 715 bcm_sf2_port_setup(ds, port, NULL);
8cfa9498
FF		 716 else if (dsa_is_cpu_port(ds, port))
717 bcm_sf2_imp_setup(ds, port);
718 }
719
32e47ff0
FF		 720 bcm_sf2_enable_acb(ds);
721
8cfa9498
FF		 722 return 0;
723}
724
96e65d7f
FF		 725static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
726 struct ethtool_wolinfo *wol)
727{
f8b8b1cd 728 struct net_device *p = ds->ports[port].cpu_dp->master;
f458995b 729 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
96e65d7f
FF		 730 struct ethtool_wolinfo pwol;
731
732 /* Get the parent device WoL settings */
733 p->ethtool_ops->get_wol(p, &pwol);
734
735 /* Advertise the parent device supported settings */
736 wol->supported = pwol.supported;
737 memset(&wol->sopass, 0, sizeof(wol->sopass));
738
739 if (pwol.wolopts & WAKE_MAGICSECURE)
740 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
741
742 if (priv->wol_ports_mask & (1 << port))
743 wol->wolopts = pwol.wolopts;
744 else
745 wol->wolopts = 0;
746}
747
748static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
749 struct ethtool_wolinfo *wol)
750{
f8b8b1cd 751 struct net_device *p = ds->ports[port].cpu_dp->master;
f458995b 752 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
0abfd494 753 s8 cpu_port = ds->ports[port].cpu_dp->index;
96e65d7f
FF		 754 struct ethtool_wolinfo pwol;
755
756 p->ethtool_ops->get_wol(p, &pwol);
757 if (wol->wolopts & ~pwol.supported)
758 return -EINVAL;
759
760 if (wol->wolopts)
761 priv->wol_ports_mask |= (1 << port);
762 else
763 priv->wol_ports_mask &= ~(1 << port);
764
765 /* If we have at least one port enabled, make sure the CPU port
766 * is also enabled. If the CPU port is the last one enabled, we disable
767 * it since this configuration does not make sense.
768 */
769 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
770 priv->wol_ports_mask |= (1 << cpu_port);
771 else
772 priv->wol_ports_mask &= ~(1 << cpu_port);
773
774 return p->ethtool_ops->set_wol(p, wol);
775}
776
7fbb1a92
FF		 777static int bcm_sf2_sw_setup(struct dsa_switch *ds)
778{
f458995b 779 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
7fbb1a92 780 unsigned int port;
d9338023 781
21a2774e 782 /* Enable all valid ports and disable those unused */
d9338023 783 for (port = 0; port < priv->hw_params.num_ports; port++) {
21a2774e 784 /* IMP port receives special treatment */
4a5b85ff 785 if (dsa_is_user_port(ds, port))
21a2774e
FF		 786 bcm_sf2_port_setup(ds, port, NULL);
787 else if (dsa_is_cpu_port(ds, port))
d9338023 788 bcm_sf2_imp_setup(ds, port);
21a2774e 789 else
d9338023
FF		 790 bcm_sf2_port_disable(ds, port, NULL);
791 }
792
5c1a6eaf 793 b53_configure_vlan(ds);
32e47ff0 794 bcm_sf2_enable_acb(ds);
d9338023
FF		 795
796 return 0;
797}
798
f458995b
FF		 799/* The SWITCH_CORE register space is managed by b53 but operates on a page +
800 * register basis so we need to translate that into an address that the
801 * bus-glue understands.
802 */
803#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
804
805static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
806 u8 *val)
807{
808 struct bcm_sf2_priv *priv = dev->priv;
809
810 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
811
812 return 0;
813}
814
815static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
816 u16 *val)
817{
818 struct bcm_sf2_priv *priv = dev->priv;
819
820 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
821
822 return 0;
823}
824
825static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
826 u32 *val)
827{
828 struct bcm_sf2_priv *priv = dev->priv;
829
830 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
831
832 return 0;
833}
834
835static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
836 u64 *val)
837{
838 struct bcm_sf2_priv *priv = dev->priv;
839
840 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
841
842 return 0;
843}
844
845static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
846 u8 value)
847{
848 struct bcm_sf2_priv *priv = dev->priv;
849
850 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
851
852 return 0;
853}
854
855static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
856 u16 value)
857{
858 struct bcm_sf2_priv *priv = dev->priv;
859
860 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
861
862 return 0;
863}
864
865static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
866 u32 value)
867{
868 struct bcm_sf2_priv *priv = dev->priv;
869
870 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
871
872 return 0;
873}
874
875static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
876 u64 value)
877{
878 struct bcm_sf2_priv *priv = dev->priv;
879
880 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
881
882 return 0;
883}
884
7e3108fa 885static const struct b53_io_ops bcm_sf2_io_ops = {
f458995b
FF		 886 .read8 = bcm_sf2_core_read8,
887 .read16 = bcm_sf2_core_read16,
888 .read32 = bcm_sf2_core_read32,
889 .read48 = bcm_sf2_core_read64,
890 .read64 = bcm_sf2_core_read64,
891 .write8 = bcm_sf2_core_write8,
892 .write16 = bcm_sf2_core_write16,
893 .write32 = bcm_sf2_core_write32,
894 .write48 = bcm_sf2_core_write64,
895 .write64 = bcm_sf2_core_write64,
896};
897
a82f67af 898static const struct dsa_switch_ops bcm_sf2_ops = {
9f66816a 899 .get_tag_protocol = b53_get_tag_protocol,
73095cb1
FF		 900 .setup = bcm_sf2_sw_setup,
901 .get_strings = b53_get_strings,
902 .get_ethtool_stats = b53_get_ethtool_stats,
903 .get_sset_count = b53_get_sset_count,
c7d28c9d 904 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
73095cb1 905 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
bc0cb653
FF		 906 .phylink_validate = bcm_sf2_sw_validate,
907 .phylink_mac_config = bcm_sf2_sw_mac_config,
908 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
909 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
910 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
73095cb1
FF		 911 .suspend = bcm_sf2_sw_suspend,
912 .resume = bcm_sf2_sw_resume,
913 .get_wol = bcm_sf2_sw_get_wol,
914 .set_wol = bcm_sf2_sw_set_wol,
915 .port_enable = bcm_sf2_port_setup,
916 .port_disable = bcm_sf2_port_disable,
22256b0a
FF		 917 .get_mac_eee = b53_get_mac_eee,
918 .set_mac_eee = b53_set_mac_eee,
73095cb1
FF		 919 .port_bridge_join = b53_br_join,
920 .port_bridge_leave = b53_br_leave,
921 .port_stp_state_set = b53_br_set_stp_state,
922 .port_fast_age = b53_br_fast_age,
923 .port_vlan_filtering = b53_vlan_filtering,
924 .port_vlan_prepare = b53_vlan_prepare,
925 .port_vlan_add = b53_vlan_add,
926 .port_vlan_del = b53_vlan_del,
73095cb1
FF		 927 .port_fdb_dump = b53_fdb_dump,
928 .port_fdb_add = b53_fdb_add,
929 .port_fdb_del = b53_fdb_del,
7318166c
FF		 930 .get_rxnfc = bcm_sf2_get_rxnfc,
931 .set_rxnfc = bcm_sf2_set_rxnfc,
ec960de6
FF		 932 .port_mirror_add = b53_mirror_add,
933 .port_mirror_del = b53_mirror_del,
73095cb1
FF		 934};
935
a78e86ed
FF		 936struct bcm_sf2_of_data {
937 u32 type;
938 const u16 *reg_offsets;
939 unsigned int core_reg_align;
df191632 940 unsigned int num_cfp_rules;
a78e86ed
FF		 941};
942
943/* Register offsets for the SWITCH_REG_* block */
944static const u16 bcm_sf2_7445_reg_offsets[] = {
945 [REG_SWITCH_CNTRL] = 0x00,
946 [REG_SWITCH_STATUS] = 0x04,
947 [REG_DIR_DATA_WRITE] = 0x08,
948 [REG_DIR_DATA_READ] = 0x0C,
949 [REG_SWITCH_REVISION] = 0x18,
950 [REG_PHY_REVISION] = 0x1C,
951 [REG_SPHY_CNTRL] = 0x2C,
952 [REG_RGMII_0_CNTRL] = 0x34,
953 [REG_RGMII_1_CNTRL] = 0x40,
954 [REG_RGMII_2_CNTRL] = 0x4c,
955 [REG_LED_0_CNTRL] = 0x90,
956 [REG_LED_1_CNTRL] = 0x94,
957 [REG_LED_2_CNTRL] = 0x98,
958};
959
960static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
961 .type = BCM7445_DEVICE_ID,
962 .core_reg_align = 0,
963 .reg_offsets = bcm_sf2_7445_reg_offsets,
df191632 964 .num_cfp_rules = 256,
a78e86ed
FF		 965};
966
0fe99338
FF		 967static const u16 bcm_sf2_7278_reg_offsets[] = {
968 [REG_SWITCH_CNTRL] = 0x00,
969 [REG_SWITCH_STATUS] = 0x04,
970 [REG_DIR_DATA_WRITE] = 0x08,
971 [REG_DIR_DATA_READ] = 0x0c,
972 [REG_SWITCH_REVISION] = 0x10,
973 [REG_PHY_REVISION] = 0x14,
974 [REG_SPHY_CNTRL] = 0x24,
975 [REG_RGMII_0_CNTRL] = 0xe0,
976 [REG_RGMII_1_CNTRL] = 0xec,
977 [REG_RGMII_2_CNTRL] = 0xf8,
978 [REG_LED_0_CNTRL] = 0x40,
979 [REG_LED_1_CNTRL] = 0x4c,
980 [REG_LED_2_CNTRL] = 0x58,
981};
982
983static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
984 .type = BCM7278_DEVICE_ID,
985 .core_reg_align = 1,
986 .reg_offsets = bcm_sf2_7278_reg_offsets,
df191632 987 .num_cfp_rules = 128,
0fe99338
FF		 988};
989
a78e86ed
FF		 990static const struct of_device_id bcm_sf2_of_match[] = {
991 { .compatible = "brcm,bcm7445-switch-v4.0",
992 .data = &bcm_sf2_7445_data
993 },
0fe99338
FF		 994 { .compatible = "brcm,bcm7278-switch-v4.0",
995 .data = &bcm_sf2_7278_data
3b07d788
FF		 996 },
997 { .compatible = "brcm,bcm7278-switch-v4.8",
998 .data = &bcm_sf2_7278_data
0fe99338 999 },
a78e86ed
FF		 1000 { /* sentinel */ },
1001};
1002MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1003
d9338023
FF		 1004static int bcm_sf2_sw_probe(struct platform_device *pdev)
1005{
1006 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1007 struct device_node *dn = pdev->dev.of_node;
a78e86ed
FF		 1008 const struct of_device_id *of_id = NULL;
1009 const struct bcm_sf2_of_data *data;
f458995b 1010 struct b53_platform_data *pdata;
a4c61b92 1011 struct dsa_switch_ops *ops;
d9338023 1012 struct bcm_sf2_priv *priv;
f458995b 1013 struct b53_device *dev;
d9338023
FF		 1014 struct dsa_switch *ds;
1015 void __iomem **base;
4bd11675 1016 struct resource *r;
7fbb1a92
FF		 1017 unsigned int i;
1018 u32 reg, rev;
1019 int ret;
1020
f458995b
FF		 1021 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1022 if (!priv)
1023 return -ENOMEM;
1024
a4c61b92
FF		 1025 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1026 if (!ops)
1027 return -ENOMEM;
1028
f458995b
FF		 1029 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1030 if (!dev)
d9338023
FF		 1031 return -ENOMEM;
1032
f458995b
FF		 1033 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1034 if (!pdata)
1035 return -ENOMEM;
1036
a78e86ed
FF		 1037 of_id = of_match_node(bcm_sf2_of_match, dn);
1038 if (!of_id || !of_id->data)
1039 return -EINVAL;
1040
1041 data = of_id->data;
1042
1043 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1044 priv->type = data->type;
1045 priv->reg_offsets = data->reg_offsets;
1046 priv->core_reg_align = data->core_reg_align;
df191632 1047 priv->num_cfp_rules = data->num_cfp_rules;
a78e86ed 1048
f458995b
FF		 1049 /* Auto-detection using standard registers will not work, so
1050 * provide an indication of what kind of device we are for
1051 * b53_common to work with
1052 */
a78e86ed 1053 pdata->chip_id = priv->type;
f458995b
FF		 1054 dev->pdata = pdata;
1055
1056 priv->dev = dev;
1057 ds = dev->ds;
73095cb1 1058 ds->ops = &bcm_sf2_ops;
d9338023 1059
18118377
FF		 1060 /* Advertise the 8 egress queues */
1061 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1062
f458995b 1063 dev_set_drvdata(&pdev->dev, priv);
d9338023 1064
7fbb1a92
FF		 1065 spin_lock_init(&priv->indir_lock);
1066 mutex_init(&priv->stats_mutex);
7318166c
FF		 1067 mutex_init(&priv->cfp.lock);
1068
1069 /* CFP rule #0 cannot be used for specific classifications, flag it as
1070 * permanently used
1071 */
1072 set_bit(0, priv->cfp.used);
ba0696c2 1073 set_bit(0, priv->cfp.unique);
7fbb1a92 1074
d9338023 1075 bcm_sf2_identify_ports(priv, dn->child);
7fbb1a92
FF		 1076
1077 priv->irq0 = irq_of_parse_and_map(dn, 0);
1078 priv->irq1 = irq_of_parse_and_map(dn, 1);
1079
1080 base = &priv->core;
1081 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
4bd11675
FF		 1082 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1083 *base = devm_ioremap_resource(&pdev->dev, r);
1084 if (IS_ERR(*base)) {
7fbb1a92 1085 pr_err("unable to find register: %s\n", reg_names[i]);
4bd11675 1086 return PTR_ERR(*base);
7fbb1a92
FF		 1087 }
1088 base++;
1089 }
1090
1091 ret = bcm_sf2_sw_rst(priv);
1092 if (ret) {
1093 pr_err("unable to software reset switch: %d\n", ret);
4bd11675 1094 return ret;
7fbb1a92
FF		 1095 }
1096
1097 ret = bcm_sf2_mdio_register(ds);
1098 if (ret) {
1099 pr_err("failed to register MDIO bus\n");
4bd11675 1100 return ret;
7fbb1a92
FF		 1101 }
1102
7318166c
FF		 1103 ret = bcm_sf2_cfp_rst(priv);
1104 if (ret) {
1105 pr_err("failed to reset CFP\n");
1106 goto out_mdio;
1107 }
1108
7fbb1a92
FF		 1109 /* Disable all interrupts and request them */
1110 bcm_sf2_intr_disable(priv);
1111
4bd11675 1112 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
bc0cb653 1113 "switch_0", ds);
7fbb1a92
FF		 1114 if (ret < 0) {
1115 pr_err("failed to request switch_0 IRQ\n");
bb9c0fa3 1116 goto out_mdio;
7fbb1a92
FF		 1117 }
1118
4bd11675 1119 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
bc0cb653 1120 "switch_1", ds);
7fbb1a92
FF		 1121 if (ret < 0) {
1122 pr_err("failed to request switch_1 IRQ\n");
4bd11675 1123 goto out_mdio;
7fbb1a92
FF		 1124 }
1125
1126 /* Reset the MIB counters */
1127 reg = core_readl(priv, CORE_GMNCFGCFG);
1128 reg |= RST_MIB_CNT;
1129 core_writel(priv, reg, CORE_GMNCFGCFG);
1130 reg &= ~RST_MIB_CNT;
1131 core_writel(priv, reg, CORE_GMNCFGCFG);
1132
1133 /* Get the maximum number of ports for this switch */
1134 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1135 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1136 priv->hw_params.num_ports = DSA_MAX_PORTS;
1137
1138 /* Assume a single GPHY setup if we can't read that property */
1139 if (of_property_read_u32(dn, "brcm,num-gphy",
1140 &priv->hw_params.num_gphy))
1141 priv->hw_params.num_gphy = 1;
1142
7fbb1a92
FF		 1143 rev = reg_readl(priv, REG_SWITCH_REVISION);
1144 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1145 SWITCH_TOP_REV_MASK;
1146 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1147
1148 rev = reg_readl(priv, REG_PHY_REVISION);
1149 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1150
f458995b 1151 ret = b53_switch_register(dev);
d9338023 1152 if (ret)
4bd11675 1153 goto out_mdio;
d9338023 1154
7fbb1a92
FF		 1155 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1156 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1157 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1158 priv->core, priv->irq0, priv->irq1);
1159
1160 return 0;
1161
bb9c0fa3
FF		 1162out_mdio:
1163 bcm_sf2_mdio_unregister(priv);
7fbb1a92
FF		 1164 return ret;
1165}
1166
d9338023 1167static int bcm_sf2_sw_remove(struct platform_device *pdev)
246d7f77 1168{
f458995b 1169 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
d9338023
FF		 1170
1171 /* Disable all ports and interrupts */
1172 priv->wol_ports_mask = 0;
f458995b
FF		 1173 bcm_sf2_sw_suspend(priv->dev->ds);
1174 dsa_unregister_switch(priv->dev->ds);
d9338023 1175 bcm_sf2_mdio_unregister(priv);
246d7f77
FF		 1176
1177 return 0;
1178}
246d7f77 1179
2399d614
FF		 1180static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1181{
1182 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1183
1184 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1185 * successful MDIO bus scan to occur. If we did turn off the GPHY
1186 * before (e.g: port_disable), this will also power it back on.
4a2947e3
FF		 1187 *
1188 * Do not rely on kexec_in_progress, just power the PHY on.
2399d614
FF		 1189 */
1190 if (priv->hw_params.num_gphy == 1)
4a2947e3 1191 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
2399d614
FF		 1192}
1193
d9338023
FF		 1194#ifdef CONFIG_PM_SLEEP
1195static int bcm_sf2_suspend(struct device *dev)
246d7f77 1196{
d9338023 1197 struct platform_device *pdev = to_platform_device(dev);
f458995b 1198 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
d9338023 1199
f458995b 1200 return dsa_switch_suspend(priv->dev->ds);
246d7f77 1201}
d9338023
FF		 1202
1203static int bcm_sf2_resume(struct device *dev)
1204{
1205 struct platform_device *pdev = to_platform_device(dev);
f458995b 1206 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
d9338023 1207
f458995b 1208 return dsa_switch_resume(priv->dev->ds);
d9338023
FF		 1209}
1210#endif /* CONFIG_PM_SLEEP */
1211
1212static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1213 bcm_sf2_suspend, bcm_sf2_resume);
1214
d9338023
FF		 1215
1216static struct platform_driver bcm_sf2_driver = {
1217 .probe = bcm_sf2_sw_probe,
1218 .remove = bcm_sf2_sw_remove,
2399d614 1219 .shutdown = bcm_sf2_sw_shutdown,
d9338023
FF		 1220 .driver = {
1221 .name = "brcm-sf2",
1222 .of_match_table = bcm_sf2_of_match,
1223 .pm = &bcm_sf2_pm_ops,
1224 },
1225};
1226module_platform_driver(bcm_sf2_driver);
246d7f77
FF		 1227
1228MODULE_AUTHOR("Broadcom Corporation");
1229MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1230MODULE_LICENSE("GPL");
1231MODULE_ALIAS("platform:brcm-sf2");
Linux 6.x block layer and io_uring tree(s)